[
  {
    "path": "README.md",
    "content": "iCESugar-pro\n-----------\n* [iCESugar-pro](#iCESugar-pro) \n* [Hardware](#hardware)\n\t* [ECP5](#ecp5)\n\t* [SDRAM](#sdram)\n\t* [SPI-Flash](#spi-flash)\n\t* [Clock](#clock)\n\t* [Peripheral](#peripheral)\n\t* [JTAG](#jtag)\n\t* [iCELink](#icelink)\n* [Virtual machine image](#virtual-machine-image)\n* [How to setup](#how-to-setup-env)\n* [How to buy](#how-to-buy)\n* [Copyright Statement](#copyright-statement)\n* [Reference](#reference)\n\n# iCESugar-pro\niCESugar-pro is a FPGA development board based on Lattice LFE5U-25F-6BG256C, which is fully supported by the open source toolchain (yosys & nextpnr), the board is designed in DDR2 SODIMM form factor with 106 usable IOs, with on-board 32MB SDRAM, it can run RISC-V Linux. The on-board iCELink debugger (base on ARM Mbed DAPLink) supports drag-and-drop programming, you can just drag the FPGA bitstream into the virtual disk to program, and with a additional USB CDC serial port direct connect to FPGA, so you can only use one Type C cable to develop and test.  \n<div align=center>\n<img src=\"https://github.com/wuxx/icesugar-pro/blob/master/doc/iCESugar-pro-1.jpg\" width = \"700\" alt=\"\" align=center />    \n<img src=\"https://github.com/wuxx/icesugar-pro/blob/master/doc/iCESugar-pro-2.jpg\" width = \"700\" alt=\"\" align=center />    \n<img src=\"https://github.com/wuxx/icesugar-pro/blob/master/doc/iCESugar-pro-3.jpg\" width = \"700\" alt=\"\" align=center />    \n</div>\n\n# Hardware\n### ECP5\nLFE5U-25F-6BG256C (BGA256 0.8mm pitch)\n1. LUTs: 24K\n2. sysMEM Blocks: 18Kb x 56\n3. Embedded Memory: 1008Kb\n4. Distributed RAM bits: 194Kb\n5. 18 x 18 Multipliers: 28\n6. PLL x 1\n\n### SDRAM\n SDRAM uses IS42S16160B (32MB)\n\n### SPI-Flash\n SPI Flash uses W25Q256JV (32MB)\n\n### Clock\nA 25MHz crystal is connect to P6\n\n### Peripheral\n2. a RGB LED is connected to {A11, A12, B11}\n3. a SDCARD slot, support SPI/SDIO\n4. 106 usable IOs out with SODIMM-DDR2-200P, broken out with the ext-board.\n\n### JTAG\nThe native JTAG of ECP5 is connect to the on-board iCELink, you can flash bitstream with this JTAG interface (called JTAG1).\nThere is also another JTAG interface (actually, just some GPIOs of ECP5) connected to the iCELink too (called JTAG2),\nif you design a SoC with a JTAG interface support, then you can use the JTAG2 to debug your SoC. Only one JTAG works at once.\nSo use the icesprog tool with command `icesprog -j 1 or 2` to switch between these two JTAG interface.\n```\n$icesprog -j 1\nJTAG --> [JTAG-1]\n         [JTAG-1]\n         TCK:  iCELink-PB6  -- ECP5-JTAG-TCK (25F-BG256-T10)\n         TMS:  iCELink-PB4  -- ECP5-JTAG-TMS (25F-BG256-T11)\n         TDI:  iCELink-PB5  -- ECP5-JTAG-TDI (25F-BG256-R11)\n         TDO:  iCELink-PB3  -- ECP5-JTAG-TDO (25F-BG256-M10)\n\n         [JTAG-2]\n         TCK:  iCELink-PA14 -- ECP5-IO-PL8D  (25F-BG256-F5)\n         TMS:  iCELink-PA13 -- ECP5-IO-PL17A (25F-BG256-H5)\n         TDI:  iCELink-PA0  -- ECP5-IO-PL38A (25F-BG256-N4)\n         TDO:  iCELink-PA1  -- ECP5-IO-PL17D (25F-BG256-J5)\n\ndone\n```\n\n### iCELink\niCESugar-pro has a on-board debugger named iCELink (base on APM32F1)，only needing one USB wire to program the FPGA and debug it:   \n1. Drag and drop programming, just drop the bitstream into the virtual USB drive named iCELink then wait a few seconds while the iCELink firmware programs it for you.\n2. USB CDC serial port, it can use to communicate with FPGA\n3. 2 JTAG interfaces for flashing the ECP5 or debugging your SoC on ECP5\n4. use the command tool `icesprog` to flash or do more config, here is the help info\n```\n$icesprog -h\nusage: /home/pi/oss/icesugar/tools/icesprog.arm [OPTION] [FILE]\n             -w | --write                   write spi-flash or gpio\n             -r | --read                    read  spi-flash or gpio\n             -e | --erase                   erase spi-flash\n             -p | --probe                   probe spi-flash\n             -o | --offset                  spi-flash offset\n             -l | --len                     len of write/read\n             -g | --gpio                    icelink gpio write/read\n             -m | --mode                    icelink gpio mode\n             -j | --jtag-sel                jtag interface select (1 or 2)\n             -c | --clk-sel                 clk source select (1 to 4)\n             -h | --help                    display help info\n\n             -- version 1.1a --\n\n```\n#### Tips\ncause the iCELink connect some GPIOs to the ECP5, you can control this GPIOs with `icesprog` to do some self defined behavior, \nfor example, to control the iCELink-PA14 -- ECP5-F5 line out low, type these command.\n```\n$icesprog -g PA14 -m out\n$icesprog -g PA14 -w 0\n```\n\n#### How To Program\nThere are multiple ways to program the bitstream.\n1. Drag and drop programming, this is the fastest and simplest way to flash.  \n2. Using the command `icesprog xxx.bit`, this can provide more configable parameters.  \n3. Using the command `dapprog xxx.bit (program to flash) or dapprog xxx.svf (program to SRAM)`  \nthe `icesprog` binary and source code is in [icesugar](https://github.com/wuxx/icesugar/tree/master/tools) repo, and the `dapprog` is a bash wrapper of openocd command, click [here](https://github.com/wuxx/icesugar-pro/tree/master/tools) to check how to setup.\n\n# Virtual machine image\nlink：https://pan.baidu.com/s/1vV2ckFpOuyd600Y47Tl1sw  \nverify code：i3en  \n`user: ubuntu`  \n`passwd: ubuntu`\n\nThe env include yosys, nextpnr, icestorm, gcc, sbt.\n\n# How to setup enviroment\n## Linux\nIt is reccomended that you use the virtual machine image, it simple and convenient.\\\nAlternatively, you can download the toolchain for programming the FPGA unit by following the instructions in the \"Installing Toolkits\" section below and the RISC-V compiler for running your code has a tutorial linked in the \"Other tools\" section.\n\n## Windows\nIf you don't want to use the virtual machine image you need to use the Windows Subsystem For Linux 2 (WSL2) as not all components of the toolchain has native windows versions.\\\nInstall WSL using [this tutorial.](https://learn.microsoft.com/en-us/windows/wsl/install) By default it uses ubuntu, which this section is written for. Once WSL is installed and configured you can open it by searching for 'WSL' from the start menu.\\\nOnce in the WSL desktop you will need to preform the following commands to install the needed toolkits.\n\n## Installing Toolkits (Windows and Linux)\nThe easiest way to get all needed tools is using the [YosysHQ oss-cad-suite](https://github.com/YosysHQ/oss-cad-suite-build). All you need to do is download and extract the repository to a location on your machine such as the home folder. After you extract it you'll need to update your PATH variable so your terminal can use the programs.\\\nDo this by editing your `.bashrc` file on your home folder using `sudo nano .bashrc` from there. Scrolll to the end of the file and in a new line add `export PATH=\"$PATH:/home/YOUR_ACCOUNT_NAME_HERE/oss-cad-suite/bin\"`\n\n### Other tools\nDapprog is included in the tools folder and can be executed from there. ecpprog is included in the install for nextpnr and the RISC-V gcc toolchain used for code compilation can be installed using [this tutorial](https://github.com/riscv-collab/riscv-gnu-toolchain)\n\n\n## Building demo files\nIf you want to use the demo files as is you just need to program the bitstream provided in the [`demo`](./demo) folder. \n<!-- The relative location allows this link to work both online and locally-->\nIf you want to change how the demos behave you will need to rebuild them. For the blink, hdmi and uart tests you just need to run `make` in the same folder to update them with your changes. For the litex_linux demo you will need to have the [litex repository](https://github.com/litex-hub/linux-on-litex-vexriscv) downloaded locally and will need to modify the `top.ys` file where it lists `INSTALL_DIR` with the location you put the repo.\n\n# How to buy\nYou can buy iCESugar-pro and PMOD peripherals from our offcial aliexpress shop [Muse Lab Factory Store](https://miusecn-muselab-tech.aliexpress.com/) or [Tindie Store](https://www.tindie.com/products/johnnywu/icesugar-pro-fpga-development-board/)\n\n# Copyright Statement\nThe HDMI test verilog source code is from [github.com/DoctorWkt/ULX3S-Blinky](https://github.com/DoctorWkt/ULX3S-Blinky)  \nThe Litex on Linux project is from [github.com/litex-hub/linux-on-litex-vexriscv](https://github.com/litex-hub/linux-on-litex-vexriscv)  \nFor hobby and personal usage, you are free to use the iCESugar-pro, you can also make the board yourself using the documentation & firmware in this repo.  \nFor the commercial usage, if you get iCESugar-pro Board from our official shop and use in other commercial product, that's no problem, otherwise, please contact us in advance.  \n\n# Reference\n### Colorlight-FPGA-Projects\nhttps://github.com/wuxx/Colorlight-FPGA-Projects\n### icestorm toolchain\nhttp://www.clifford.at/icestorm/\n### riscv gcc toolchain\nhttps://xpack.github.io/riscv-none-embed-gcc/install/\nhttps://www.sifive.com/software\n### iCESugar\nhttps://github.com/wuxx/icesugar\n### iCESugar-nano\nhttps://github.com/wuxx/icesugar-nano\n### Examples\nhttps://github.com/damdoy/ice40_ultraplus_examples  \nhttps://github.com/icebreaker-fpga/icebreaker-examples\n### SpinalHDL\nhttps://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Getting%20Started/index.html\n"
  },
  {
    "path": "demo/README.md",
    "content": "## litex_no_dram\n`$picocom -b 115200 /dev/ttyACM0`  \n`$dapprog litex_no_dram.bit`\n\n## litex_with_dram\n`$picocom -b 38400 /dev/ttyACM0`  \n`$dapprog litex_with_dram.bit`\n\n"
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 (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t\t\t409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000000000000000000000000000000000FF23FF00\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000008000000000000000000000000000000000000000000000000000000FF23FF00000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000008000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000FF409B00000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t\t\t9B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000FF409B0000000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000FF409B000000000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000FF99690000000080000000080000000080000000080000000020000000020000\n\t\t\t00002000000002000000002000000002000000002000000002000000002000000002000000002000\n\t\t\t0000020000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000FFB90B0000004000000004000000004000000004000000001000000001000000001000000001\n\t\t\t000000001000000001000000001000000001000000001000000001000000001000000001000000FF\n\t\t\t409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000000000000000000000000000000000FFE75600\n\t\t\t00000200000000200000000200000000200000000080000000080000000080000000080000000080\n\t\t\t000000080000000080000000080000000080000000080000000080000000080000FF409B00000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000FF409B00000000000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t\t\t9B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000000000000000FF408C0004004000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000000FF7EFF0000001000000001000000001000000001000000000400\n\t\t\t00000040000000040000000040000000040000000040000000040000000040000000040000000040\n\t\t\t0000000400000000400000FF409B0000000000000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000020000000020000000020000000020000000020000000020000000020000000020000000020\n\t\t\t000000020000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000FF7EFF00000010000000010000000010000000010000000004000000004000000004000000\n\t\t\t00400000000400000000400000000400000000400000000400000000400000000400000000400000\n\t\t\tFF997C00000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000080000FF409B\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000FF409B000000000000000000000000000000000000000000000000000000);\nSDR\t2952\tTDI  (FFFFFFFF0000007A11\n\t\t\t110000000000000143FFFFFFFFFFFFFFFFFFFFFFFFFFE75600000002000000002000000002000000\n\t\t\t00200000000080000000080000000080000000080000000080000000080000000080000000080000\n\t\t\t000080000000080000000080000000080000FF558E00000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000000000000C0000FF60EC00000040000000040000000040000000040000000010\n\t\t\t00000001000000001000000001000000001000000001000000001000000001000000001000000001\n\t\t\t000000001000000001080000FF409B00000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000FF996900000000800000000800000000800000000800000000200000000200);\n\nSIR\t8\tTDI  (FF);\nRUNTEST\tIDLE\t100 TCK\t1.00E-02 SEC;\n\nSIR\t8\tTDI  (C0);\nRUNTEST\tIDLE\t2 TCK\t1.00E-03 SEC;\nSDR\t32\tTDI  (00000000)\n\t\t\tTDO  (00000000)\n\t\t\tMASK (FFFFFFFF);\n\nSIR\t8\tTDI  (26);\nRUNTEST\tIDLE\t2 TCK\t2.00E-01 SEC;\n\nSIR\t8\tTDI  (FF);\nRUNTEST\tIDLE\t2 TCK\t1.00E-03 SEC;\n\nSIR\t8\tTDI  (3C);\nSDR\t32\tTDI  (00000000)\n\t\t\tTDO  (00000100)\n\t\t\tMASK (00002100);\n"
  },
  {
    "path": "demo/blink_flash.svf",
    "content": "//ULX2S / ULX3S JTAG programmer v 3.0.92 (built Sep 19 2020 14:37:22)\n//START\r\nSTATE IDLE;\nSTATE RESET;\nSTATE IDLE;\n\nSIR\t8\tTDI\t(E0);\nSDR\t32\tTDI\t(00000000)\n\tTDO\t(41111043)\n\tMASK\t(FFFFFFFF);\n\nSIR\t8\tTDI\t(1C);\nSDR\t510\tTDI\t(3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);\n\nSIR\t8\tTDI\t(C6);\nSDR\t8\tTDI\t(00);\nRUNTEST IDLE    2 TCK;\n\nSIR\t8\tTDI\t(0e);\nSDR\t8\tTDI\t(01);\nRUNTEST IDLE\t32 TCK 1.00E-01 SEC;\n\nSIR\t8\tTDI\t(3C);\nSDR\t32\tTDI\t(00000000)\n\tTDO\t(00000000)\n\tMASK\t(0000B000);\n\nSTATE RESET;\nSTATE IDLE;\nSIR\t8\tTDI(FF);\nRUNTEST IDLE\t32 TCK;\nSIR\t8\tTDI(3A);\nSDR\t16\tTDI(68FE);\nRUNTEST IDLE\t32 TCK;\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000001B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000801B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000401B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000c01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000201B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000a01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000601B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000e01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000101B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(20);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF2B8D000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000051B889410000006200000002000000\n\t44C208888200000047000000DCFFFFFFFFCDBDFFFFFF008C1CCC82E24282C26CB462AC4CB4AAACA26232045C2E4E860A00FF00000040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000800040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000400040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000200040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000a00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000e00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000100040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000900040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000d00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000700040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF91DE000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000400000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000880040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000400000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000480040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF91\n\tDE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000280040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000a80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000680040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000e80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000180040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000980040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000001FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000580040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB00000000d80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000380040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000b80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000780040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF277100000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000600FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF2703000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000001800000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000040040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000840040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000440040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000c40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000240040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000640040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000e40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000140040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000940040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000540040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000040000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF718F0000000000000000000000000000000000000000000000000000000000000000000000000000000000340040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF84CB00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000100000000FF581100000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0020000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000b40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF84CB0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000100000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000740040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF8FA600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000001000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000f40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tC58A000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000001000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000001000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF658D00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000800800000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFC58A000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000\n\t000000FFC58A0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000cc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000800000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFA2120000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFA212000000000000000000000000000000000000000000006c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000006000000000FFD4D90000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000004000000000FF9EF800000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000006000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9EF800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000006000000000FF9EF8000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000006000000000FFD4D9\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000004000000000FF9EF80000000000000000000000000000000000000000000000009c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000006006000000FF14600000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000006006000000FF9EF80000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000006000000000FF9EF800000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000006000000000FF005c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000006006000000FFFDFF00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000006006008000FF1460000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000006006000000FF1460\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000006006008000FF14600000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000006006000000FF14600000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000006006000000FF146000000000000000000000000000000000000000000000000000003c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000004000000FF6E7000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000002AA2B2000000FF9EF800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000006000000000FF38DB000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000006008000000FFFDFF00bc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004000000FF43A3000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000556554000000FF62350000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000002AA2A2000000FFB38B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFE6B800000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000008000000FF623500000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000002AA2A2000000FFB38B00000000000000000000000000000000000000000000000000000000fc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000004000000000FF91BB000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000002802000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF8FA60000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000FF409B000000020040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF91BB0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000002802000000FF5E4100000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000004006000000FFD4D900000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000820040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000006000000000FF51C5000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000001006000000000FFAD51000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000004002000000FF409B000000000000000000000000000000000000000000000000000000000000420040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000006002000000FFB2180000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000006186000000FFCA030000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000006000000FFB38B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000004000000FF9EF80000000000c20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000407006000000FFABE400000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000200006000000FFCA03000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000006000000FFE770000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000220040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000006806000000FF14600000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000006006000000FF14600000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000006006000000FF52BF0000000000000000000000000000000000000000000000000000000000000000a20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000600E000000FFF6E900000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000006806000000FFFE4B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000001806806000000FFDB5D000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000001006006000000FFF6E900000000000000620040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000006816000000FFF67F000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000026006000000FF14600000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000006006000000FFB2430000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000006006000000FF5E4C00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000001007006000000FF905D00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000046006000000FFFAAC00000000000000000000000000000000000000000000000000000000000000000000120040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0001006006000000FF1460000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000006006000000FFF6E9000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000006806000000FF14600000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000006006000000FF1460000000000000000000920040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000001000006000000FF31760000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000806806000000FF146000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000006006000000FFDB5D00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000520040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000506006000000FF1460000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000006006000000FF053E000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000001000006000000FF053E000000000000000000000000000000000000000000000000000000000000000000000000d20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00E60C000000FF078F0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000096000000000FFB38B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000004000000FF618F00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000810A4E000000FF475C0000000000000000000000320040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000001003402000000FFDC0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000B04920000000FF3913000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000002000000FFBAAA000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t842902000000FFF1CF0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000804800000000FFBAEF0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000008C106000000FFE85B0000000000000000000000000000000000000000000000000000000000000000000000000000720040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000002A85\n\t28000000FFF3C600000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000D10B20000000FF0AB700000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0001001000000000FF7BCD000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000288238000000FF164900000000000000000000000000f20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000002492000000FF0182000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t288000000000FFC4A60000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000040000000000FF48210000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010420\n\t02000000FF619A00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000100404006000000FF6D7800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000844820000000FFCC1A000000000000000000000000000000000000000000000000000000000000000000000000000000008a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000600008\n\t0000FFA123000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000080416004000000FFDB0C000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t020002000000FFCAEA0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000001014000000000FF38320000000000000000000000000000004a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000006000100000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF471F00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028815000\n\t0000FFF9F7000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000040050000000FF8BED000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t006500000000FF6D350000000000000000000000000000000000000000000000000000000000000000000000000000000000002a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000000000\n\tFF7F8E0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000001556550000000FFF55D0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002AE2\n\t00000000FF596700000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000806000000000FFF8830000000000000000000000000000000000aa0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000046000000000FFABBD00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000\n\t0004FF3919000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000A8E2A8000004FF51C5000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001006a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028E2A8000000\n\tFF7CE70000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000026000000000FF9EF80000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000060\n\t00000000FF1AC50000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (06000000FFA3\n\t4400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000002AE2AE000000FF3A2B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000055655600\n\t0000FF1460000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000006006000000FFCBC3000000000000000000000000000000000000001a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000026006000000FF1460000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006006000000\n\tFF415B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000028E2AE000000FF14600000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000060009a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000006006000000FFD7\n\tAE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000406006000000FF85BE00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000014700600\n\t0000FFF67F000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFC36100\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000546006000000FFCA03000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006000000\n\tFF4F120000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000001006000000FF1460000000000000000000000000000000000000000000da0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000006010000000FF51020000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000804000000FFCA\n\t0300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000006000000FF146000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600600003a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000020800000000FF3FD500\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000028C842000000FFD27E000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000026546000000\n\tFF92BD000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF5478000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000004880000000FF71260000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000515556000000FFBE\n\tB400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000002AA20A000000FF400D00000000000000000000000000000000000000000000007a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000001000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF41B700\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000041000000000FF2609000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028A2AA00000000fa0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000004000000000FF5E86000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000001002802000000FF658D0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000800800000000FF8F\n\tA60000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000060040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A60000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000001000000000000FF733200000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000002002000000FF5E4100\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000004006000000FFD4D900000000000000000000000000000000000000000000000000860040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000096000000FF9EF8000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000006000000000FF9EF8000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000006000000000FFAD510000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000004002000000FF8F00460040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000006006000000FF5FD60000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000060E6000000FF288A00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000806000000FFA46E00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000001006006000000FF288A000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000806000000FFC646000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000016000000FF1460000000000000000000000000000000000000000000000000000000260040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000806186000000FF14600000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000006006000000FF14600000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000006006000000FFDB5D00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000001006006000000FFDB5D0000a60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000006006000000FF905D00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000046006000000FF905D000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000046006000000FF7587000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000660040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000001006000000000FF965A0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000001806000000000FFF6E90000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000006806000000FF14600000000000000000000000000000000000000000000000000000000000e60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000006000000000FF9EF800000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000006000000000FF7C7100000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000006800000000FF9EF8000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000006000000000FF51C500000000160040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000006000000000FF9EF8000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000006000000000FF9EF80000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000006000000000FF9EF80000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000960040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF51C500000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000001006000000000FF9EF800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000006000000000FF9EF800000000000000000000000000000000000000000000000000000000000000560040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000800020000000FFCE40000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000D16500000000FF9EF8000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000006000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000d60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000063E0000000FF078F0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000096000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF9F8E00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000360040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000001002020000000FFFC1F000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000B08800000000FFD4D9000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000004000000000FFD9BD000000000000000000000000000000000000000000000000000000000000000000b60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000288020000000FF9C9A0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000802D08000000FF75F20000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000844800000000FF960F00000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000008C080000000FFDD0D0000000000000000760040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000002A8028000000FF9D4600000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000D10928000000FF689F000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000001001080000000FF1908000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000002202000000FFB2EF0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000288480000000FF73C10000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000020400000000FF5D3400000000000000000000000000000000000000000000000000000000000000000000000e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t01508000000000FF383200000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000001042002000000FF738A00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000050014006000000FFE2C5000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000844848000000FFBB91000000000000000000008e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000006000080000FF5194000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000028026004000000FF84CF0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000284002000000FFB41D0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00006006100000FFCA0300000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000006000000FFCA0300000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000006000000FF471F00000000000000000000000000000000000000000000000000000000000000000000000000ce0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t6006000000FF8B1A000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000288006000000FF4E3E000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000040006000000FF14600000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000006006000000FFE7AD0000000000000000000000002e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000006006000000FF126F0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00556006000000FF785B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000012AE006000000FF146000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004\n\t6006000000FF1460000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000006006000000FF92E6000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000A8E006000000FF14600000000000000000000000000000000000000000000000000000000000000000000000000000006e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006006\n\t000000FF415B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000028E2AE000000FFF67F0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00026006000000FF146000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000006006000000FF905D0000000000000000000000000000ee0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000006006000000FFA34400000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002A\n\tE2AE000000FF3A2B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000556556000000FF1460000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000026006\n\t000000FF14600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000006006000000FF415B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0028E2AE000000FF146000000000000000000000000000000000000000000000000000000000000000000000000000000000009e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000060000\n\t00FF146000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000006006000000FF146000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t6006000000FFD7AE000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000406006000000FFF67F000000000000000000000000000000005e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000006006000000FFD7AE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000406006\n\t000000FFCA030000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000006000000FFCA030000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000061000000\n\t00FF510200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000804000000FFCA0300000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0006000000FF1460000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A212000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFFB85000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028C942\n\t000000FF33F50000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000026436000000FF5AA8000000000000000000000000000000000000be0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000028A2AA000000FF51C80000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050000000\n\t00FF179200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000555D56000000FF14D200000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002A007e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tA284000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000020000000000FFA212000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800\n\t000000FF8608800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008000FFD4D9\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000004000000000FF0ABA0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000\n\t00FFD3A600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000010000FF409B0000000000000000000000000000000000000000010040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000004000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t0ABA000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000002000000000FF3D46000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000810040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000FF9EF8\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000006000000000FF9EF80000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000060000000\n\t00FFD4D90000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000410040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFF9F60000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000027000000000FF7B2200000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000246000000000FF\n\t888E000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000110000000FF835500000000000000000000000000000000000000000000c10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000006000000000FF1BE9000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000007000000000FFA212\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000800000000FF84900000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000088000000210040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000806400000000FF89350000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000006940000000FF9EF800000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000006000000000FF\n\t9EF800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9EF800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000006000000000FF2CF9000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000062A0000000FF9EF8\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000006000000000FF8822000000000000000000000000000000000000000000000000610040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000006006000000FF5E4C0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000001007006000000FF59670000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000806000000000FFBBEE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000806800000000FF00e10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000006004000000FF146000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000006006000000FF1460000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000006006000000FF1460\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000006000000000FF9EF80000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000006000000000FF6DE80000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000006004000000FF6DE80000000000000000000000000000000000000000000000000000910040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000001000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9EF800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000006000000000FF5967000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000806000000000FF9EF800510040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000800006000000FFAD1C000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000506512000000FFE7700000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000006002000000FF8FA60000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000006000000000FF4F6000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000096818000000FFFB1700000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000046000000FF0D9C00000000000000000000000000000000000000000000000000000000310040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000008C2AC000000FFBC0F000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000001002002000000FF5DCD000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000B04780000000FFA2120000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000FF9EF8000000b10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000288000000000FF56B20000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000822002000000FFE05600000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000804004000000FF131500000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000710040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000002A8000000000FF0536000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000D10000000000FFE83E000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000001001800000000FF0182000000000000000000000000000000000000000000000000000000000000f10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000844804000000FF73320000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000002002000000FF01820000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000288000000000FF400D00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000020800000000FFE39D0000000000090040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000001405000000000FF391E00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000001003002000000FF27C9000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000004004000000FF86E2000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000890040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000006000000000FF5D360000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000406000000000FF39130000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000002000000FF5D3B0000000000000000000000000000000000000000000000000000000000000000490040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000006084000000FFF9AA00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000002004000000FFB38B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000004000000FF27C9000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000004004000000FF9EF800000000000000c90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000802006000000FF22BB000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000288224000000FFAFB10000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000044014000000FF0FC00000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000290040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000006000000000FFE36E00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000D52550000000FF64DB00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000AAE2AE000000FF47BD00000000000000000000000000000000000000000000000000000000000000000000a90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000006020000000FF9A48000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000042030000000FF5AA8000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000006100000000FF449F0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000A8A200000000FF9EF8000000000000000000690040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000004006000000FF17420000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000028E200000000FF20B000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000022110000000FF867200000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000006000000FFE965000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000002AC2AE000000FFE448000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000550556000000FF5E41000000000000000000000000000000000000000000000000000000000000000000000000190040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t114006000000FFBC5E0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000024006000000FFF8620000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000400E000000FFAD5900000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000028C2A6000000FFCA030000000000000000000000990040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000004006000000FF5E4100000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000004006000000FF5E41000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000004006000000FF1FBD000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000590040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t004006000000FF1FBD0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000114006000000FF5E410000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000004006000000FF5E410000000000000000000000000000000000000000000000000000000000000000000000000000d90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000040\n\t00000000FF9EF800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000006000000000FF5E4100000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000004006000000FF5E41000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000004006000000FF5E4100000000000000000000000000390040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000002AA2AA000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFC4160000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000002AA2AA000000FFD4D90000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000AA2\n\tAA000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF980200000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000356556000000FFC41600000000000000000000000000000000000000000000000000000000000000000000000000000000790040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF83550000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000400000000000FF05F0800000000000000000000000000000f90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000850040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000450040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000250040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFA2\n\t8400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000020000000000FFC4A600000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000a50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000650040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000150040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000950040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000550040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000d50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000350040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000750040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000f50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000008d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00004d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000002d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000ad0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000ed0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000001d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000005d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000dd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000bd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000007d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000030040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000830040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000430040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000c30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000230040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000630040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000e30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000130040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000930040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000530040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000330040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000b30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000730040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000cb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF002b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ab0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000006b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00eb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000009b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000005b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000003b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000bb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000fb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000070040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000870040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000470040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000c70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000270040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000a70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000670040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000170040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000970040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000570040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000d70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000370040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000770040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000f70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000008f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000004f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000af0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ef0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000001f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000df0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40003f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bf0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000007f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000ff0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000808040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000408040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000208040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000a08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000608040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000e08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000108040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000908040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000508040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000d08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000308040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000b08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000708040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000088040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000888040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000488040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000c88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000288040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000688040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000e88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000188040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000988040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000588040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000388040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000b88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000788040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000048040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00848040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000448040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000c48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00248040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000648040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000e48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000148040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000948040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000548040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000348040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000b48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000748040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000f48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000004c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000cc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000ac8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000006c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000001c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000009c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000003c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000fc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000828040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000428040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000228040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000a28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000628040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000128040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000928040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000528040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000d28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000328040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000728040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000f28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000008a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000004a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000002a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000aa8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000ea8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000001a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000005a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000da8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000ba8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000007a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000068040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000868040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000468040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000c68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000268040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000668040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000e68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000168040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000968040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000568040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000368040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000b68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00768040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B008e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000ce8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000002e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000006e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000ee8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000009e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000005e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000003e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000be8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000fe8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000018040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000002000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000818040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF7F6C0000000000000000000000000000000000000000000000000000000000000000000000000000418040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000c18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000218040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000a18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000618040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000118040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000918040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000518040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000318040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000718040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000f18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000098040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000898040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000498040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000298040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000a98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000698040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000198040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000998040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000598040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000d98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000398040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000798040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000f98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000058040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000858040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000458040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000258040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000a58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000658040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000e58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000158040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000958040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000558040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000d58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000358040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000b58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000758040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000008d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000002d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ad8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000ed8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000005d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00dd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000bd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A007d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000038040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000838040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000438040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000c38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000238040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000638040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000e38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000138040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000938040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000538040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000338040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000b38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000738040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000f38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000004b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000cb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000ab8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000006b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000009b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000003b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000fb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000078040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000878040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000478040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000c78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000278040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000a78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000678040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000178040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000978040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000578040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000d78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000378040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000778040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000f78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000008f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000004f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000002f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000af8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000ef8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000001f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000005f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000df8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000bf8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000007f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ff8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000804040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000404040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000204040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000604040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000e04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00104040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000904040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000504040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00d04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000304040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000b04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000704040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000084040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000884040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000484040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000c84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000284040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000684040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000e84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000184040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000984040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000584040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000384040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000b84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000784040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000f84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000044040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000844040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000444040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000c44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000244040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000644040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000144040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000944040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000544040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000344040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000744040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000f44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40000c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000004c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000cc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000ac4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000006c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000001c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000009c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000dc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000003c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000007c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000fc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000824040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000424040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000224040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000a24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000624040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000e24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000124040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000924040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000524040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000d24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000324040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000724040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000008a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000002a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF00aa4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000ea4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE001a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000005a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000da4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000ba4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000007a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000064040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000864040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000464040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000c64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000264040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000664040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000e64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000164040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000964040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000564040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000364040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000b64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000764040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000f64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000ce4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0004FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000006e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000009e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000003e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000be4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000fe4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000014040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000814040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000414040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000c14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000214040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000a14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000614040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000114040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000914040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000514040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000d14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000314040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000714040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000f14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000094040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000894040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000494040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000294040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000a94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000694040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000004FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000e94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000194040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000994040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000594040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000d94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000394040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE09A8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000794040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000054040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000854040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00454040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000254040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00a54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000654040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000e54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000154040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000954040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000554040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000d54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000354040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000b54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000754040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000008d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000cd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000000000000000002d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ad4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000006d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000ed4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000009d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000005d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000003d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000bd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000034040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000834040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000434040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF75DE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000c34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75\n\tDE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000004FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000234040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000634040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF75DE000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400e34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000134040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000934040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000534040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000334040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000b34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000734040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000f34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000004b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000cb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000ab4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000006b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000001b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000009b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000db4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000003b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000007b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000fb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000074040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000874040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000474040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000274040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000004FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000a74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t04FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000674040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000174040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000974040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000574040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000d74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000374040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000774040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00f74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000008f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B004f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000002f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000af4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000ef4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000001f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000005f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000df4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000bf4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000007f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ff4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000080c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000c0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000020c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000060c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000000000000000e0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000090c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000050c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000030c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000b0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000070c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000008c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000088c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000048c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF75DE000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000c8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040028c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (DE0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000068c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF7500e8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000098c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000058c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000038c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000b8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000078c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000f8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000004c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000084c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000044c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000c4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000a4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000064c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000014c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000094c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000054c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000d4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000034c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000074c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000f4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000008cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000004cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t04FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ccc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000acc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF\n\t75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ecc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000001cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000dcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF003cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000007cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00fcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000082c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000042c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000000022c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000a2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000062c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000e2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000012c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000092c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000052c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000d2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000032c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000b2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000072c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000008ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000004FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000cac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000000002ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000006ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000eac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000005ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000bac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000006c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000086c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000046c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (DE0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000004FF409B00000000000000000000000000000000000000000000000000c6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF750026c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000066c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000e6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000016c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000096c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000056c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000036c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000b6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000f6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000004ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000cec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000aec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000006ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000001ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000009ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000dec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000003ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000007ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000fec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000041c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF\n\t75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000021c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04FF75DE0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000a1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000061c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000011c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0091c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000051c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000d1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0031c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000071c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000f1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000089c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000049c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000029c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000a9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000069c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000e9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000019c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000099c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000059c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000d9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000039c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000b9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000079c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000005c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000085c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000045c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000c5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000000000000000000025c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000065c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000e5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000015c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000095c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000055c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000035c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000b5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000075c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40008dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000000000cdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00002dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000adc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000006dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000edc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000009dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000005dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ddc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000000000000000003dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000bdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000fdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000003c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000083c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000043c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000c3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000023c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000a3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000063c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000013c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000093c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000053c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000d3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000033c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000073c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000f3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000004bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000abc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF006bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ebc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000001bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B009bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000dbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A8000003bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000007bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000fbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000087c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000047c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000027c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000a7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000067c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000e7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000017c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000097c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000057c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000d7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000037c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000b7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000077c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000008fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000002fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000afc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000efc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000005fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000bfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40007fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000002040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000802040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000402040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000c02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000202040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000602040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000e02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000102040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000902040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000502040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000302040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000b02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000702040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000f02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000082040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000882040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000482040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000c82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000282040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000a82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000682040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000182040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000982040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000582040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000382040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000782040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000f82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000842040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000442040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00c42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000242040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000a42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00642040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000142040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000942040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000542040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000d42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000342040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000742040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000f42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000008c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000004c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000002c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000ac2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000ec2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000001c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000005c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFE09A800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000dc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000007c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000822040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000422040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000222040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000622040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000e22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000122040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000922040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000522040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000d22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000322040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000b22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000722040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000008a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000ca2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000002a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aa2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000006a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000ea2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000009a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000005a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000da2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000003a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000ba2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000fa2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000062040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000862040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000462040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000c62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000262040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000a62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000662040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000162040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000962040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000562040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000362040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000762040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000f62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF000e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000004e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00ce2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000ae2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000006e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000001e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000009e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A8000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000de2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000003e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000be2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000007e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000fe2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000812040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000412040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000212040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000a12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000612040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000e12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000112040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000912040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000512040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000d12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000312040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000712040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000092040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000892040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000492040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000292040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000692040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000e92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000192040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000992040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000592040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000d92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000392040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000b92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000792040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000052040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000852040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000452040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000c52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000252040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000652040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000e52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000152040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000952040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000552040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000352040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000b52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000752040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000f52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000004d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000cd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ad2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000006d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ed2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000009d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000003d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00bd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000fd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00032040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000832040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000432040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000c32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000232040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000a32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000632040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000132040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000932040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000532040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000d32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000332040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000732040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000f32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000008b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000004b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000002b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000ab2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000eb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000001b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000005b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000db2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000007b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000072040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000872040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000472040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000272040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000a72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000672040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000e72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000172040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000972040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000572040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000d72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000372040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000b72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000772040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000008f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000cf2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000002f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000af2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000006f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000ef2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0800000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000009f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF368D0000000000000000000000000000000000000008000000000000000000000000000000000000000000000000\n\t000000000000000000000002000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF368D00000000000000000000000000005f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000df2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000003f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000bf2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000ff2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000c0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000060a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000090a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0050a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000030a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00b0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000070a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000f0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000008a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000088a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000048a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000c8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000a8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000068a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000018a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF368D000000000000000000000000000000000000000800000000000000000000000000000000000000\n\t0000000000000000000000000000000002000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000098a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF368D0000000000000000000000000000\n\t0000000000080000000000000000000000000000000000000000000000000000000000000000000000020000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000058a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000d8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000038a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000078a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000f8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000084a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000044a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000024a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000a4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000064a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000014a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000094a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000054a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000d4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000034a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000074a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000008ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40004ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000002ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000aca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000eca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000001ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000005ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000dca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000bca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000007ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000002a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000082a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000c2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000022a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000062a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000e2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000092a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000052a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000032a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000b2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000072a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000caa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aaa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000006aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00eaa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000009aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B005aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000daa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000003aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000baa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000faa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000006a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000086a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000046a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000c6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000026a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000a6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000066a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000016a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000096a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000056a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000d6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000036a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000076a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000f6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000008ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000004ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000002ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000aea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000001ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFE09A800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000dea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000007ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000fea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000081a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000041a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000021a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000a1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000061a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000e1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000011a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000091a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000051a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000d1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000031a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000b1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000071a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000009a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000089a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000049a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000c9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000029a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000069a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000e9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000019a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000099a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFE09A8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000059a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000039a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000b9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000079a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000005a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000085a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000045a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000c5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0025a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000065a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00e5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000015a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000095a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000055a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000035a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000b5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000075a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000f5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000004da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000cda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000ada040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000006da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000001da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000009da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000dda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000003da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000007da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000fda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000083a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000043a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000023a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000a3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000063a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000013a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000093a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000053a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000d3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF400033a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000073a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000f3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000008ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000004ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000002ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000aba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000eba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000001ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000005ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000dba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000bba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000007ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000007a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000087a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000047a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000c7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000027a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000067a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000e7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000017a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000097a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000057a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000037a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000b7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000077a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF008fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000cfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B002fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000afa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000006fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000efa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000009fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000005fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000003fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000bfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000ffa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000006040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000806040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000406040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000c06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000206040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000a06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000606040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000106040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000906040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000506040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000d06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000306040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000706040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000f06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000086040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000886040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000486040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000286040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000a86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000686040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000186040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000986040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000586040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000d86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000386040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000786040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000f86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000046040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000846040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000446040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000246040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000a46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000646040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000e46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000146040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000946040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000546040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000d46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000346040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000b46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000746040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000008c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000cc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000002c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000ec6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000005c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000bc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF007c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000026040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00826040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000426040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000c26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000226040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000626040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000e26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000126040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000926040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000526040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000326040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000b26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000726040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000f26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000004a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000ca6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000aa6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000006a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000001a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000009a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000da6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000003a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000fa6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000066040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000866040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000466040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000266040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000a66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000666040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000166040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000966040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000566040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000d66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000366040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000766040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000f66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000008e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000004e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ce6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000002e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000ae6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000ee6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000001e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000005e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000de6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000be6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000007e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000016040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000816040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000416040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000216040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000616040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000e16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000116040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000916040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000516040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00d16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000316040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000b16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00716040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000096040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000896040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000496040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000c96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000296040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000696040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000e96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000196040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000996040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000596040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000396040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000b96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000796040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000f96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000056040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000856040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000456040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000c56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000256040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000a56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000656040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000156040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000956040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000556040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000356040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000756040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000f56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000004d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000cd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000ad6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00006d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ed6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000001d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000009d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000dd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000003d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000007d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000fd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000036040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000836040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000436040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000236040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000a36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000636040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000e36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000136040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000936040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000536040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000d36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000336040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000b36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000736040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000008b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000002b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ab6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000eb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF001b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000005b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00db6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000bb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000007b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000076040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000876040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000476040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000c76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000276040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000676040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000e76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000176040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000976040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000576040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000376040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000b76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000776040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000f76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000004f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000cf6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000af6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000006f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ef6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000009f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000df6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000003f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bf6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000ff6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF400000e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000040e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000c0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000a0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000060e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000010e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000090e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000d0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000030e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000070e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000f0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000088e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000048e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000028e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000a8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000068e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000e8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000018e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000098e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000058e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000d8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000038e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000078e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000084e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000044e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000024e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00a4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000064e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000e4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0014e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000094e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000054e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000d4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000034e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000b4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000074e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000008ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000cce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000002ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ace040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000006ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000ece040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000009ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000005ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000003ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000bce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000fce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000002e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000082e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000c2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000062e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000092e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000052e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000032e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000b2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000072e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000f2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000004ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000cae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000aae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000006ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000001ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000009ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000dae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000003ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000007ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000fae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000086e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000046e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000026e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000a6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000066e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000e6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000016e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000096e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000056e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000d6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000036e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000076e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000008ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF004ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000002ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00aee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000eee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000001ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000005ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000dee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000bee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000007ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000001e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000081e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000c1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000021e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000061e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000e1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000091e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000051e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000031e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000b1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000071e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000009e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000089e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000049e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000c9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000029e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000069e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000019e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000099e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF400059e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000039e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000b9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000079e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000f9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000005e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000085e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000045e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000c5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000025e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000a5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000065e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000015e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000095e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000055e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000d5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000035e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000075e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000f5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000008de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000004de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000002de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000ade040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ede040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000001de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000dde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000007de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00fde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000083e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0043e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000023e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000a3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000063e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000e3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000013e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000093e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000053e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000d3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000033e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000b3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000073e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000008be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000cbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000002be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000abe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000006be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000ebe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000009be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000005be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000003be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000bbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000007e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000087e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000047e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000c7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000027e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000067e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000e7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000017e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000097e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000057e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000037e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000b7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000077e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000f7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000004fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000cfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000afe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000006fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000efe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000001fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000009fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000dfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000003fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000007fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t04FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000ffe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t04FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000801040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000401040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000201040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000a01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000601040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tD15B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000101040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000901040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t087B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000501040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000d01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00301040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000701040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00f01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000004000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000\n\t00000000000000000000000000000000FFA4BE00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000004000000000000000000000000000000000000000000000000000000000FFA4BE00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000\n\t0000000000000000000000000000000000000000FFA4BE00000000000000000000000000000000000000000000000000000000881040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FFA4BE000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000004000000000000000000000000000000000000000000000000000000000FFA4BE000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000\n\t000000000000000000000000000000000000FFA4BE0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000FFA4BE000000481040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000004000000000000000000000000000000000000000000000000000000000FFA4BE0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000\n\t00000000000000000000000000000000FFA4BE00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000004000000000000000000000000000000000000000000000000000000000FFA4BE00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000c81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000\n\t0000000000000000000000000000FFA4BE000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000004000000000000000000000000000000000000000000000000000000000FFA4BE000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000\n\t000000000000000000000000000000000000FFA4BE000000000000000000000000000000000000000000000000000000000000281040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFA4BE0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000\n\t00000000000000000000000000000000FFA4BE00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000004000000000000000000000000000000000000000000000000000000000FFA4BE0000000000a81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000002AA000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFAD55000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000002AA000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000681040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000002AA000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF09170000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000005560000000000000000000000000\n\t00000000000000000000000000000000FFAD550000000000000000000000000000000000000000000000000000000000000000e81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0D5480000000000000181040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000981040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000581040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000d81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000381040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000b81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000781040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000041040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000841040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000441040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000c41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000241040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000641040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000e41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000141040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000941040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000541040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000341040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000b41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000741040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000cc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40002c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000006c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000ec1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000009c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000005c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000003c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000bc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000fc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000021040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000821040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000421040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000c21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000221040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000a21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000621040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000121040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000921040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000521040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000d21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000321040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000721040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000f21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000004a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000aa1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A8000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000001a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF009a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000001FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000da1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB003a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000007a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000001FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000fa1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000061040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000861040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000461040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000261040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000a61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000661040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000001FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000001FF409B00000000000000000000000000000000000000000000000000000000000000000000e61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB000000000000000000161040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000961040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000561040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000d61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000361040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000b61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000761040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000008e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000ce1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000002e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000ee1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000005e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000be1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000011040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000811040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000411040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000c11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000211040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000611040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000e11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000911040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000511040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000311040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000b11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000020000\n\t00000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000711040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF93BA0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFA6FF0000000000000000000000000000000000000000000000000000000000000000000000f11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000091040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000891040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000491040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000c91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF097A0000000000000000000000000000000000\n\t0000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF097A00000000000000000000000000\n\t000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000291040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000a91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF097A0000000000000000000000000000000000\n\t0000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000691040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF097A000000000000000000000000000000000000000800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF097A000000000000000000000000000000\n\t000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000191040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000991040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000591040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000d91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000391040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000791040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000f91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000051040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000851040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000451040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000251040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000a51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00651040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000151040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00951040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000551040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000d51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000351040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000751040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000f51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000008d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000004d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000002d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000ad1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000ed1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000001d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000005d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000dd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000bd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000007d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000031040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000200\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000831040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF2D3000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000040000000000000000040000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFCF97000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000040000000000431040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFA23C0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000200FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000231040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000631040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF8E940000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000e31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9C\n\t8600000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000131040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000931040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000531040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFB6D200000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB6\n\tD20000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000331040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000b31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000731040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI 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(000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000cb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI 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  },
  {
    "path": "demo/blink_green.svf",
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IDLE    100 TCK;\n\nSIR\t8\tTDI\t(26);\nRUNTEST IDLE    2 TCK   2.00E-03 SEC;\n\nSIR\t8\tTDI\t(FF);\nRUNTEST IDLE    2 TCK   1.00E-03 SEC;\n\nSIR\t8\tTDI\t(3C);\nSDR\t32\tTDI\t(00000000)\n\tTDO\t(00000100)\n\tMASK\t(00002100);\n\n//END\r\n"
  },
  {
    "path": "demo/colorlight_5a_75b_flash.svf",
    "content": "//ULX2S / ULX3S JTAG programmer v 3.0.92 (built Sep 19 2020 14:37:22)\n//START\r\nSTATE IDLE;\nSTATE RESET;\nSTATE IDLE;\n\nSIR\t8\tTDI\t(E0);\nSDR\t32\tTDI\t(00000000)\n\tTDO\t(41111043)\n\tMASK\t(FFFFFFFF);\n\nSIR\t8\tTDI\t(1C);\nSDR\t510\tTDI\t(3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);\n\nSIR\t8\tTDI\t(C6);\nSDR\t8\tTDI\t(00);\nRUNTEST IDLE    2 TCK;\n\nSIR\t8\tTDI\t(0e);\nSDR\t8\tTDI\t(01);\nRUNTEST IDLE\t32 TCK 1.00E-01 SEC;\n\nSIR\t8\tTDI\t(3C);\nSDR\t32\tTDI\t(00000000)\n\tTDO\t(00000000)\n\tMASK\t(0000B000);\n\nSTATE RESET;\nSTATE IDLE;\nSIR\t8\tTDI(FF);\nRUNTEST IDLE\t32 TCK;\nSIR\t8\tTDI(3A);\nSDR\t16\tTDI(68FE);\nRUNTEST IDLE\t32 TCK;\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000001B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000801B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000401B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000c01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000201B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000a01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000601B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000e01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000101B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000901B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000501B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(20);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI 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(000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000200040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI 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(000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000e00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF4A910000000000000000000000000000001800100040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000900040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000d00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000700040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000880040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000480040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000280040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000a80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000680040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000e80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FFD3590000000000000000000000000000000000000010000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000180040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000980040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000580040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF8C9600000000000000\n\t0000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFC495000000000000000000000000040000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8C9600000000d80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC4950000000000\n\t000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000380040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000b80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000780040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF835F00000000000000000000000000000000000010000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF2179000000000000000000000000000000000000080000000000000000000000000000040040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000840040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000440040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000200000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000c40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF20E4000000000000000000000000200000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF20E400000000000000000000240040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000640040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000e40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000140040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000940040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000540040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000340040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000b40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000740040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000f40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000cc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000006c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000009c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF005c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000003c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00bc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000fc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000020040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF211A00000000\n\t000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000820040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF211A000000000000\n\t0000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000420040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000c20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000220040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000a20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000620040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000120040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000920040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000520040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000d20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000320040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000720040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000f20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000008a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000004a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000002a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000aa0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000001a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000da0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000007a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000060040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000860040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000460040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000260040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000a60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000400000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000660040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF80ED0000000000000000000000000000000000000000000000000000000000e60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80ED00000000160040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000960040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000560040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000d60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000360040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000b60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000760040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000008e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF8DC200000000000000000000000000000000000000000000000000000000000000000000000000000002\n\t00000000000000000000000000000000000000000000000000000000000000000000FF8DC200000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000ce0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000002e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000006e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000ee0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000009e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000005e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000be0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000010040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000810040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000410040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000c10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000210040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000610040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00e10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000910040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00510040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000310040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000b10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000710040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000f10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000090040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000890040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000490040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000c90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000290040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000a90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000690040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000190040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000990040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000590040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000d90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000390040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000790040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000000000000000000000f90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000850040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000450040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000250040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000a50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000650040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFA6DA000000000000000000000000000000000000000000000000\n\t0000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFA6DA0000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFA6DA000000000000000000000000000000000000000000150040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FFA6DA0000000000000000000000000000000000000000000000000000\n\t000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000FFA6\n\tDA00000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFA6DA00000000000000000000000000000000000000000000\n\t000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000950040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000550040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000d50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000350040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF807400000000000000000000000000000000000000000000000000000000\n\t00000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000750040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8074000000\n\t0000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF81460000000000000000000000000000000000000000000000000000\n\t000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000FF4000f50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000800000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF3647000000000000000000000000000000000000000000000000000000000000\n\t0000000000041000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF80740000000000000000000000000000000000000000000000000000008d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFBB1A00000000000000000000000000000000000000000000000000000000\n\t00000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000FF814600004d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE04F0000000000\n\t000000000000000000000000000000000000000000000000000000000000000A000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000002d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF060E00000000000000000000000000000000000000000000000000000000000000000000\n\t00000A04000000000000000000000000000000000000000000000000000000000000000000000000FFC6E100000000000000\n\t0000000000000000000000000000000000000000000000000000000000020400000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000ad0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0406000000000000000000000000000000000000000000000000000000000000000000000000FF6635000000000000000000\n\t0000000000000000000000000000000000000000000000000000000804000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF073C0000000000\n\t0000000000000000000000000000000000000000000000000000000000000012040000000000000000000000000000000000006d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFA6DA00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFB58D00000000000000000000000000000000000000000000000000000000000000ed0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FFC6E1000000000000000000000000000000000000000000000000000000000000000000000000\n\t0204000000000000000000000000000000000000000000000000000000000000000000000000FF66AC000000000000000000\n\t0000000000000000000000000000000000000000000000000000000404000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF75FB0000000000000000000000000000000000000000000000000000000000000000\n\t000000000006000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000001d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000004\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF66AC0000000000000000000000\n\t0000000000000000000000000000000000000000000000000004040000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFA6DA00000000000000000000000000000000000000000000000000000000000000000000\n\t00000004000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFA6DA0000000000000000000000000000000000000000000000000000000000000000005d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF93BA00000000000000000000000000000000000000000000000000000000000000000000\n\t00000002000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000dd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000002000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF80ED0000000000000000000000000000000000000000000000000000000000000000000000000400\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF80ED0000000000000000000000\n\t0000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF20A00000000000000000000000000000000000000000000000000000000000000000000000bd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000007d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF93BA000000000000000000000000000000\n\t0000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF20A00000000000000000000000\n\t000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000fd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000030040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFF23B000000000000000000000000000000020000000000000000000000000000000000000000000200000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF211A0000000000000000000000000000000200000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF93BA000000000000000000000000830040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000430040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF20A0000000000000000000000000000000\n\t0000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF20A0000000000000000000000000000000000000000000000000000000000000000000000000020000c30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000230040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FFA6DA00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF20A0000000000000000000000000000000000000000000000000000000000000000000000000020000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFA6DA000000000000000000000000000000\n\t000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000a30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000040004000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF75FB0000000000000000000000000000000000000000000000000000000000000000000000000006000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFC6E10000000000000000000000000000000000\n\t0000000000000000000000000000000000000002040000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF5D5B0000000000000000000000000000000000000000000000000000000000000000000000020004000000630040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF727100000000000000000000000000000000180000000000000000000000000000000000000000060000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF471100000000000000000000000000000000180000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF11DB00000000000000000000000000000000e30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF7271000000000000000000000000000000001800000000\n\t0000000000000000000000000000000006000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFA1500000000000000000000000000000000018000000000000000000000000000000000000000004000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFA1500000000000000000000000000000000018\n\t000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000130040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000080800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFA15000000000000000000000000000000000180000000000000000000000000000000000000000040000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF124A00000000000000000000000000000000180000\n\t0000020002000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF840E00000000000000000000000000000000180000000004000400000000000000100800000000040000000000930040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t4711000000000000000000000000000000001800000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF4711000000000000000000000000000000001800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF47110000000000000000000000000000000018000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFE474000000000000000000000000000000001800530040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF5FE70000000000000000000000000000002018000000000000\n\t0000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFD70D00000000000000000000000000000000180000000000000000000000000000000000000001000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF943000000000000000000000000000000000180000\n\t000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000d30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t0895000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF4711000000000000000000000000000000001800000000000000000000000000000000000000000000000000000000330040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF4711\n\t0000000000000000000000000000000018000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFB3F00000000000000000000000000000004008000000000000\n\t0000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF807400000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF821C0000000000000000000000000000000008000000b30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FFD08700000000000000000000000000000000000000000000000000\n\t00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t42F3000000000000000000000000000000000800000000000000000000000000000000000000080000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFDE56000000000000000000000000000000001000000000\n\t000000000000000000000000000000088200000000000000000000000000000000000000000000000000000000000000000000730040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80ED\n\t0000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF80740000000000000000000000000000000000000000000000\n\t0000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF81460000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000f30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF53550000\n\t0000000000000000000000000000000000000000000000000000000000000000000008020000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF20A000000000000000000000000000000000000000000000000000\n\t00000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FFB0AA000000000000000000000000000000400000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF7045\n\t0000000000000000000000000000004000000000000000000000000000000000000000000800000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF8E7A0000000000000000000000000000000000000000000000\n\t0000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000008b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF8E7A00000000000000000000000000000000000000000000000000\n\t00000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF8146000000000000000000000000000000000000000000000000cb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF80ED0000000000000000000000000000000000000000000000000000000000\n\t000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000FF16440000\n\t000000000000000000000000000AA00000000000000000000000000000000000000000020000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF807400000000000000000000000000000000000000000000000000\n\t00000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000FF002b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000001004000000000000000000000000000000000000000000000000000000000000000000000000FF807400000000\n\t0000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFED25000000000000000000000000000000154000000000000000000000\n\t0000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000FFC565\n\t0000000000000000000000000000000AA000000000000000000000000000000000000000000000000000000000000000000000ab0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFA6430000000000000000000000000000000000000000000000000000000000\n\t000000000000000C04000000000000000000000000000000000000000000000000000000000000000000000000FFA6DA0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFE2F90000000000000000000000000000000AA00000000000000000006b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF93BA00000000000000000000000000000000000000000000000000000000000000\n\t00000000000002000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFEED4000000000000000000000000000000000000000000000000000000\n\t0000000000000000000084000000000000000000000000000000000000000000000000000000000000000000000000FFA6DA00eb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000004000000000000000000000000000000000000000000000000000000000000000000000000FF36C6000000000000\n\t0000000000000000000000000000000000000000000000000000000000000104000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFC6E10000000000000000000000000000000000000000000000000000000000\n\t000000000000000204000000000000000000000000000000000000000000000000000000000000000000000000FFA6DA0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000001b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000002000040000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF93BA00000000000000000000000000000000000000000000000000000000000000\n\t00000000000002000000000000000000000000000000000000000000000000000000000000000000000000FF66AC00000000\n\t0000000000000000000000000000000000000000000000000000000000000000040400000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFA6DA000000000000000000000000000000000000000000000000000000009b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF2086000000000000000000000000000000200000000000000000000000000000000000\n\t0000200000000000000000000000000000000000000000000000000000000000000000000000000000FFB0AA000000000000\n\t0000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF43230000000000000000000000000000000000000000000000000000000000\n\t000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000FF1EDE0000005b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000003b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFD08700000000000000000000000000000000000000000000000000000000000000\n\t00000000000100000000000000000000000000000000000000000000000000000000000000000000000000FF08950000000000bb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF20A0000000000000\n\t0000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000007b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF20A00000000000000000\n\t0000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000fb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FFC0DA00000000000000000000000000400000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFC0DA000000000000000000000000004000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF93BA00000000000000070040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF68AE000000000000000000000000\n\t0000000000000000000000000000000000000000000000000280000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF68AE0000000000000000\n\t000000000000000000000000000000000000000000000000000000000280000000000000000000000000000000000000000000870040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF80ED00000000000000000000000000000000000000000000000000000000000000000000000004\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000470040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF81F2000000000000000000000000000000000000000000000000000000000000000000000800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF20A0000000000000000000000000\n\t0000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF93BA0000000000000000000000000000000000000000000000000000000000000000000000\n\t000002000000000000000000000000000000000000000000000000000000000000000000000000FF81F2000000000000000000c70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000006000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000270040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000048000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF75FB000000000000000000000000000000000000000000000000000000000000000000000000000600\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF75FB000000000000000000000000000000000000000000000000000000000000000000000000a70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FFA6CD0080000000000000000000000000000000000000000000000000000000000000000000000404000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFE5E700000000000000000000000000000000000000000000000000000000000000000000000001\n\t06000000000000000000000000000000000000000000000000000000000000000000000000FFC8E30000000000000000000000670040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF66BB00800000000000000000000000000000\n\t0000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000010000000000000000000000006000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFA6DA0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000170040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFA6DA00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF8A6F00000000000000000000000000970040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFBF0F000000000000000000000000000000000000\n\t0000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000570040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF807400000000000000000000000000000000000000000000000000000000000000000000000008000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000d70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF93BA000000000000000000000000000000000000\n\t0000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000370040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF814600000000000000000000000000000000000000000000000000000000000000000000000010000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF807400000000000000000000000000000000\n\t000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000b70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF5D20000000000000000000000000000000000000\n\t0000000000000000000000000000000000000800000000000000000000000000000000000800000000000000000000000000\n\t000000000000FF8074000000000000000000000000000000000000000000000000000000000000000000000000080000000000770040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF5D2000000000000000000000000000000000000000000000000000000000000000000000000008000000000000\n\t00000000000000000000000800000000000000000000000000000000000000FF7BED0000000000000000000000000000000000f70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF5D2000000000000000000000000000000000000000000000\n\t0000000000000000000000000000080000000000000000000000000000000000080000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF5D200000000000000000000000000000000000000000\n\t0000000000000000000000000000000008000000000000000000000000000000000008000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000008f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF7B\n\tED00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000\n\t00000000001000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000004f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000800000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF80740000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF81460000000000000000000000000000000000000000\n\t000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000cf0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF5D20000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000002f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFE24200\n\t0000000000000000000000000000000000000000000000000000000000000000000000100400000000000000000000000000\n\t0000001004000000000000000000000000000000000000FF8074000000000000000000000000000000000000000000000000\n\t0000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFD9340000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000\n\t000000000000000004000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000af0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000004000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF19\n\tDB00000000000000000000000000000000000000000000000000000000000000000000000008040000000000000000000000\n\t00000000000004000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFD934000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000ef0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFD9340000000000000000000000000000000000000000000000000000\n\t000000000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFD93400000000000000000000000000000000000000000000001f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFD93400000000000000000000000000000000000000000000000000000000\n\t00000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFD934000000000000000000000000000000000000000000000000\n\t0000000000000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000009f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFDA9A0000000000000000000000000000000000000000000000000000\n\t000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000FFDA\n\t9A00000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000005f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000df0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40003f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bf0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000200\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000007f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FFAC4D0000000000000000000000000000000000000000000000000000000000000000\n\t000000000002000000000000000000000000000000000002000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAC4D0000ff0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF41A9000000000000000000000000000000000000000000000000000000000000\n\t0000000000001800000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9DCF0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000808040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF243500000000000000000000000000000000000000000000000000000000000000000000\n\t00000482000000000000000000000000000000000002000000000000000000000000000000000000FF211A00000000000000\n\t0000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9DCF00000000408040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0200000000000000000000000000000000000000000000000000000000000000000000000000FF73BE000000000000000000\n\t0000000000000400000000000000000000000000000000000000000300000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000840000000000000000000000000000000000040000000000\n\t00000000000000000000000000FFC8E300000000000000000000000000000000000000000000000000000000000000000000\n\t00000480000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF20A000000000000000000000000000000000000000000000000000000000000000208040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FFB90F000000000000000000000000000000000000000000000000000000000000000000000000\n\t0204000000000000000000000000000000000004000000000000000000000000000000000000FF0126000000000000000000\n\t0000000000000000000000000000000000000000000000000000000184000000000000000000000000000000000004000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF913A000000000000a08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFD9340000000000000000000000\n\t0000000000000000000000000000000000000000000000000000040000000000000000000000000000000000040000000000\n\t00000000000000000000000000FFEE7F00000060000000000000000000000000000000000000000000000000000000000000\n\t00000004000000000000000000000000000000000204000000000000000000000000000000000000FFB90F00000000000000\n\t000000000000000000000000000000000000000000000000000000000002040000000000000000000000000000000000040000608040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FFD934000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004000000000000000000000000000000000004000000000000000000000000000000000000FF9B18000000000000000000\n\t0000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000202000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000e08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FFB3050000000000000000000000000000000000000000000000100000000500000000100000000506\n\t000000100000000110000000000000000006000000000000000000000000000000000000FFD9340000000000000000000000\n\t0000000000000000000000000000000000000000000000000000040000000000000000000000000000000000040000000000\n\t00000000000000000000000000FFD93400000000000000000000000000000000000000000000000000000000000000000000\n\t00000004000000000000000000000000000000000004000000000000000000000000000000000000FFD9340000000000000000108040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFE90B00000000000000000000000000\n\t0000000000000000000000000000000000000008000000028000000008000000008800000000000000000000000000000000\n\t0000000000000000000000FF35E2000000000000000000000000000000000000000000000000000000000000000000000000\n\t0006000000000000000000000000000000000006000000000000000000000000000000000000FFEA79000000000000000000\n\t000000000000000000000000000008000000020000000000000000000000000000000000000000000000000000000000000000908040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFC0980000000000000000000000000000000000000000000000000000000100000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000508040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF625500000000000000000000000000\n\t0000000000000000000000000000000000000000000000080000000000000000000000000000000000082000000000000000\n\t0000000000000000000000FF649C000000000000000000000000000000000000000000000000000000000000000000000000\n\t0040000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000d08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000000000\n\t0000000000000000000000000800000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFCDEC0000000000000000000000000000000000000000000000000000000000000000000000000020\n\t000000000000000000000000000000000020000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000308040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000009000000000000000000000000000000000009000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF7BED00000000000000000000000000\n\t0000000000000000000000000000000000000000000000100000000000000000000000000000000000100000000000000000\n\t0000000000000000000000FF5D2000000000000000000000000000000000000000000000000000000000000000000000000000b08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF7BED000000000000000000000000000000000000000000000000000000000000000000000000100000000000\n\t0000000000000000000000001000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFB1F60000000000000000000000000000000000000000000000000000000000000000000000000802\n\t000000000000000000000000000000000802000000000000000000000000000000000000FF7697000000000000000000000000708040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000002000000000000000000000000000000000000FF6B2C0000000000000000000000000000000000\n\t0000000000000000000000000000000000000001000000000000000000000000000000000001000000000000000000000000\n\t00000000000000FF17F500000000000000000000000000000000000000000000000000000000000000000000000002000000\n\t00000000000000000000000000000200000000000000000000000000000000000000FF5D2000000000000000000000000000\n\t000000000000000000000000000000000000000000000008000000000000000000000000000000000008000000000000000000f08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000020000020000000000000000000000000000000000001000000000000000000000000000000\n\t0000000000FF1F2A0000000000000000000000000000000000000000000000000000000000000000000000000C0200000000\n\t0000000000000000000000000C02000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF7F6C000000000000000000000000000000000000000000000000000000000000000000000000000000088040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF80030000000000000000000000000000000000000000000000000000000000000000000000000000100000000000\n\t000000000000000000000000000000000000000000000000000000000000FFC3E90000000000000000000000000000000000\n\t0000000000000000000000000000000000002010000000000000000000000000000000000010000000000000000000000000\n\t00000000000000FF7BED00000000000000000000000000000000000000000000000000000000000000000000000010000000\n\t00000000000000000000000000001000000000000000000000000000000000000000FF9FBA0000000000000000000000000000888040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000002000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFCEC8000000000000000000000000000000\n\t000000000000000000000000000000000040000000000000000000000000000000000000000000800000000000000000000000488040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000900000000000000000000000000000000000800000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFAC4D0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000020000000000000000000000000000000000020000000000000000000000\n\t00000000000000FF7B3D0000000000000000000000000000000000000000000000000000000000000000000000000002100600c88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF17F500000000000000000000000000000000000000\n\t0000000000000000000000000000000000020000000000000000000000000000000000020000000000000000000000000000\n\t0000000000FFBD4F000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000080000000000000000000000000000000000000FFCD3C00000000000000000000000000000000288040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000200000000000000000000000000000000000000FF0E94000000000000000000000000000000000000000000\n\t0000000000000000000000000000001006000000000000000000000000000000001006000000000000000000000000000000\n\t000000FF76970000000000000000000000000000000000000000000000000000000000000000000000000900000000000000\n\t000000000000000000000900000000000000000000000000000000000000FFD9340000000000000000000000000000000000\n\t000000000000000000000000000000000000000004000000000000000000000000000000000004000000000000000000000000a88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFC48F00000000000000000000000000000000000000\n\t0000000000000000000000000000000000080400000000000000000000000000000000080400000000000000000000000000\n\t0000000000FF17F500000000000000000000000000000000000000000000000000000000000000000000000002000000000000688040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tD934000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000\n\t0000000000000004000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFD934000000000000000000000000000000000000e88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000004000000000000000000000000000000000000FFD9340000000000000000000000000000000000000000000000\n\t0000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000000000\n\t00FF35E200000000000000000000000000000000000000000000000000000000000000000000000000060000000000000000\n\t00000000000000000006000000000000000000000000000000000000FFD93400000000000000000000000000000000000000\n\t000000000000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000188040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000FF\n\t4FDF000000000000000000000000000000000000000000000000000000000000000000000020000400000000000000000000\n\t0000080000000004000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFD934000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000988040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFD1F90000000000000000000000000000000000000000000000\n\t0000000000000000000000002000000000000000000000000000000000004000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF69FD0000000000000000000000000000000000000000588040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF1D45000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000d88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000100000000000000000000000000000000000100000000000000000000000000000000000000FF1997\n\t0000000000000000000000000000000000000000000000000000000000000000000000000082000000000000000000000000\n\t000000000082000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000388040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tB7B8000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000\n\t0000000000000200000000000000000000000000000000000000FF6B2C00000000000000000000000000000000000000000000b88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0400000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80A1\n\t8000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000788040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000440000000080000000000000000000000000000000000000000000000000000000000000000000FFAC4D0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000\n\t00000002000000000000000000000000000000000000FFFCCC00000000000000000000000000000000000000000000000000\n\t00000000000000000000000050000000000000000000000000000000000050000000000000000000000000000000000000FF\n\t2E3100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFC791000000000000000000000000000000000000000000000000000000\n\t0000000000000000440000000000000000000000000000000000000000000000000000000000000000000000000000FF8636\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000\n\t000000000000000000000000000000000000000000000000FF04C6000000000000000000000000000000000000000000000000048040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF80740000000000000000000000000000000000000000000000000000000000\n\t000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000FFBEB10000\n\t0000000000000000000000000000000000000000000000000000000000000000000000280000000000000000000000000000\n\t00000028000000000000000000000000000000000000FF6CA200000000000000000000000000000000000000000000000000\n\t00000000000000000000000802000000000000000000000000000000000002000000000000000000000000000000000000FF00848040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF2E31000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000448040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF77CE0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000200000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000c48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000002000000\n\t00000000000000000000000000000000FF17D500000000000000000000000000000000000000000000000000000000000000\n\t00000000008004000000000000000000000000000000000004000000000000000000000000000000000000FF8E7A00000000\n\t0000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00248040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000204000200000000000000000000000000000204000000000000000000000000000000000000FF3FDA000000000000\n\t0000000000000000000000000000000000000000000000000000000000000104000200000000000000000000000000000104\n\t000000000000000000000000000000000000FFDEEC0000000000000000000000000000000000000000000000000000000000\n\t0000000000000000A4000000000000000000000000000000000084000000000000000000000000000000000000FFA5F70000\n\t000000000000000000000000000000000000000000000000000000000000000000000220000000000000000000000000000000a48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFD93400000000000000000000000000000000000000000000000000000000000000\n\t00000000000004000000000000000000000000000000000004000000000000000000000000000000000000FFD93400000000\n\t0000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000\n\t0004000000000000000000000000000000000000FF430300000000000000000000000000000000000000000000000000000000648040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000400000000\n\t0000000000000000000000000000FF0460000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004000000000000000000000000000000000804000000000000000000000000000000000000FF35E2000000000000\n\t0000000000000000000000000000000000000000000000000000000000000006000000000000000000000000000000000006\n\t000000000000000000000000000000000000FF9DCF0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000FF409B000000e48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200000000\n\t000004000000000000000000000000000000000004000000000000000000000000000000000000FF5DEA0000000000000000\n\t00000000000000000000000000050004000000001000051008000000000C0005081000000000200004001000000000040000\n\t00000000000000000000000000000000FFD93400000000000000000000000000000000000000000000000000000000000000\n\t00000000000004000000000000000000000000000000000004000000000000000000000000000000000000FFD93400000000\n\t000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000148040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFE7C2000000000000000000000000000000000000000000000000000000000000008808\n\t0000000008000288080000000020000200080000000000000000000000000000000000000000000000FFD934000000000000\n\t0000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000004\n\t000000000000000000000000000000000000FF707D000000000000000000000000000000000000000000008000000000000800948040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF66AC0000000000000000\n\t0000000000000000000000000004000400000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000548040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF152E000000000000000000000000000000000000000000000000000000000000000000\n\t0000000880000000000000000000000000000000000800000000000000000000000000000000000000FF2C83000000000000\n\t000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000003200d48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000800000000000000000000000000000000000820000000000000\n\t000000000000000000000000FFF54C0000000000000000000000000000000000000000000000000000000000000000000000\n\t000012000000000000000000000000000000000002000000000000000000000000000000000000FFD34E0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000C00000000000000000000000000000000000080000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000348040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF0A5D00000000000000000000000000000000000000000000000000000000000000000000000008\n\t02000000000000000000000000000000000902000000000000000000000000000000000000FFAC4D00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000200000000\n\t0000000000000000000000000000FFD36B000000000000000000000000000000000000000000000000000000000000000000\n\t0000001048000000000000000000000000000000001000000000000000000000000000000000000000FF625500000000000000b48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000080000\n\t0000000000000000000000000000000900000000000000000000000000000000000000FFD540000800000000000000000000\n\t0000000000000000000000000000000000000000000000001000000000000000000000000000000000001400000000000000\n\t000000000000000000000000FF809C0008000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF152E0000000000000000\n\t000000000000000000000000000000000000000000000000000000000880000000000000000000000000000000000800000000748040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFC89200080000000000000000000000000000000000000000000000000000000000000000000000\n\t80000000000000000000000000000000000000000000000000000000000000000000000000FF20A000000000000000000000\n\t0000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFE68B00000000000000000000000000000000000000000000000000000000000000000000f48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FFD1A0000000000000000000000000000000000000000000000000000000000000008000000000000200\n\t0000000000000000000020000000000002000000000000000000000000000000000000FF3D1B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000A00000000000000000000000000000000000800000000000000\n\t000000000000000000000000FF77CE0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000200000000000000000000000000000000000000FF409B0000000000000000000c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000040000000100000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFEADA40080000000000000000000000000000000000000000000000000000000000000000800000\n\t00000000000000000000000000000080000000000000000000000000000000000000000000FFA6BE40000000000000000000\n\t0000000000000000000000000000000000000000000000010000080000000000000000000000000000008010080000000000008c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000018000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF7BED000000000000000000000000000000000000000000000000000000000000000000000000100000\n\t0000000000000000000000000000001000000000000000000000000000000000000000FF1962000800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000\n\t000000000000000000000000FF11190000000000000000000000000000000000000000000000000000000000000100000000004c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF5D200000000000000000000000000000000000000000000000000000000000000000000000000800000000\n\t000000000000000000000000000800000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF196100000010000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000080000000000000000000000000000000000FF404A0008000800000000000000cc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000000000\n\t00000000000000000000000404000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF744C200000000000000000000000000000000000000000000000000000000000000000000000000200\n\t0000000000000000000000000000000002000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000004000000000000000000000000000000000004000000000000000000000000\n\t000000000000FF12434000000000000000000000000000000000000000000000000000000000000000000000001004000000\n\t000000000000000000000000001004000000000000000000000000000000000000FF9D270008000000000000000000000000\n\t0000000000000000000000000000000000000000000008000000000000000000000000000000000008000000000000000000\n\t00000000000000000000FFD7A50000000000000000000000000000000000000000000000000000000000000000000000000200ac8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FFD93400000000000000000000000000000000000000000000000000000000000000000000000000040000000000\n\t00000000000000000000000004000000000000000000000000000000000000FFD93400000000000000000000000000000000\n\t0000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000000000\n\t0000000000000000FF33AC0000000000000000000000000000000000000000000000000000000000000000000000000C0400\n\t0000000000000000000000000000000A04000000000000000000000000000000000000FFD934000000000000000000000000006c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000004000000000000000000000000000000000000FF1939001000000000000000000000000000000000\n\t0000000000000000000000000000000000000004000000000000000000000000000000000004000000000000000000000000\n\t000000000000FFE09A8000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFF5410000000000000000000000000000\n\t000000000000000000000000000000000000000000000080000000000000000000000000000000000080000000000000000000ec8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000004040000000000000000000000000000000002040000000000000000000000000000\n\t00000000FFB79E00000000000000000000000000000000000000000000000000000000000000000000000000040000000000\n\t00000000000000000000000404000000000000000000000000000000000000FF6CEE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000008400000000000000000000000000000000008400000000000000000000\n\t0000000000000000FFB90F000000000000000000000000000000000000000000000000000000000000000000000000020400001c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF33CC800000000000000000000000000000000000000000000000000000000000000000000002800000000000000000\n\t0000000000000400000000000000000000000000000000000000000000FFAFA2000000000000000000000000000000000000\n\t0000000000000000000000000000000000000004000000000000000000000080000000000004000000000000000000000000\n\t000000000000FF809C0008000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF2E170000000000000000000000000000009c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000100000000000000000000000000000000000000000000000000FF99690000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000804000000000000000000000000\n\t00000000FF06AC80000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000400000000000000000000000000000000000000000000FFD5FA80000000000000000000000000000000\n\t0000000000000000000000000000000000000002800000000000000000000000000000000000000000000000000000000000005c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF3364000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000\n\t000000000000FFADB7000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF6B2C0000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000\n\t000000000000000100000000000000000000000000000000000000FFD0870000000000000000000000000000000000000000\n\t0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF1D4E80000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000080000000000000000000000000000000000000FF609D00000000000000000000000000000000003c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF80ED00000000000000000000000000000000000000000000\n\t0000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFE230100000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000bc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000400000000000000000000000000000000000200000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF269B8800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF809C00080000000000000000000000000000000000000000000000000000000000000000000000000000000000007c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF3F\n\t5100000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFB7B800000000000000000000000000000000000000fc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFBF0F0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000828040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF6B2C0000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000\n\t000000000000000100000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000428040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFF54100000000000000000000000000000000000000000000\n\t000000000000000000000000000000800000000000000000000000000000000000800000000000000000000000000000000000c28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000FFD93400\n\t0000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000\n\t0000000004000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000228040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFAE4F000000\n\t0000000000000000000000000000000000000000000000000000000000000000000084000000000000000000000000000000\n\t000024000000000000000000000000000000000000FFAE4F0000000000000000000000000000000000000000000000000000\n\t000000000000000000000084000000000000000000000000000000000024000000000000000000000000000000000000FFD7\n\tD200000000000000000000000000000000000000000000000000000000000000000000000000040800000000000000000000\n\t00000000000404000000000000000000000000000000000000FF20D70000000000000000000000000000000000000000000000a28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000004\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3B0400\n\t0000000000000000000000000000000000000000000000000000000000000000000000000608000000000000000000000000\n\t0000000406000000000000000000000000000000000000FF6860000000000000000000000000000000000000000000000000\n\t180000000000000000000000000400000000000000000000000000000000040400000000000000000000000000000000000000628040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF35E2000000\n\t0000000000000000000000000000000000000000000000000000000000000000000006000000000000000000000000000000\n\t000006000000000000000000000000000000000000FFB9780000000000000000000000000000000000000000000000000000\n\t000000000000000000000004080000000000000000000000000000000004000000000000000000000000000000000000FF2E\n\t310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFD85C00000000000000000000000000000000000000000000000000000002\n\t00000100000100000404000100000100000010000100000000000004000000000000000000000000000000000000FFD93400\n\t0000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000\n\t0000000004000000000000000000000000000000000000FFD93400000000000000000000000000000000000000000000000000128040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF96E1000000\n\t0000000000000000000000000000000000000000000000000200000000000000000200000080000080000008000080000000\n\t000000000000000000000000000000000000000000FFD9340000000000000000000000000000000000000000000000000000\n\t000000000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF4000928040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAC4D0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000\n\t02000000000000000000000000000000000000FF6D0B00000000000000000000000000000000000000000000000000000000\n\t00000100000100000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000528040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000800\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2E7D000000\n\t0000000000000000000000000000000000000000000000000000000000000000000808000000000000000000000000000000\n\t000808000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000d28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001000000000\n\t000000000000000000000000000000FF5D200000000000000000000000000000000000000000000000000000000000000000\n\t000000000800000000000000000000000000000000000800000000000000000000000000000000000000FFD0870000000000\n\t0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF33C60000328040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000800000000000000000000000000000000000800000000000000000000000000000000000000FFE8FA00000000000000\n\t0000000000000000000000000000000000000000000000000000000000088000000000000000000000000000000000088000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEBF1000000\n\t000000000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000b28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000800000000\n\t000000000000000000000000000000FF973B0000000000000000000000000000000000000000000000000000000000000000\n\t000000001002000000000000000000000000000000001002000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF5D200000000000000000000000000000000000000000000000000000000000728040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF6B2C00000000000000\n\t0000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000010000\n\t0000000000000000000000000000000000FF4E0A000000000000000000000000000000000000000000000000000000000000\n\t0000000000000200000000000000000000000000000000000400000000000000000000000000000000000000FF5D2000000000f28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t1002000000000000000000000000000000001002000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFB1F60000000000000000000000000000000000000000000000000000000000000000\n\t000000000802000000000000000000000000000000000802000000000000000000000000000000000000FFB7B80000000000\n\t0000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000002000a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF009700000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000400000000000000000000000000000000FF7BED00000000000000\n\t0000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000100000\n\t0000000000000000000000000000000000FF973B000000000000000000000000000000000000000000000000000000000000008a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000004a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF5D200000000000000000000000\n\t0000000000000000000000000000000000000000000000000008000000000000000000000000000000000008000000000000\n\t00000000000000000000000000FFF54100000000000000000000000000000000000000000000000000000000000000000000\n\t00000080000000000000000000000000000000000080000000000000000000000000000000000000FF609D00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FFF541000000000000000000000000000000000000000000000000000000000000000000000000\n\t0080000000000000000000000000000000000080000000000000000000000000000000000000FF17F5000000000000000000\n\t0000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000200000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000002a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF17F50000000000000000000000000000000000000000000000000000000000000000000000000200\n\t000000000000000000000000000000000200000000000000000000000000000000000000FFE2420000000000000000000000\n\t0000000000000000000000000000000000000000000000000010040000000000000000000000000000000010040000000000\n\t00000000000000000000000000FF5D2000000000000000000000000000000000000000000000000000000000000000000000\n\t00000800000000000000000000000000000000000800000000000000000000000000000000000000FFD9340000000000000000aa8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000020000\n\t00000000000000000000000000000002000000000000000000000000000000000000FFD93400000000000000000000000000\n\t0000000000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FF7F6C000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000002000000000000000000000000000000000000FF17AE000000000000000000\n\t0000000000000000000000000000000000000000000000000000000806000000000000000000000000000000000804000000006a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000004000000000000000000000000000000000004000000000000000000\n\t000000000000000000FFD9340000000000000000000000000000000000000000000000000000000000000000000000000004\n\t000000000000000000000000000000000004000000000000000000000000000000000000FF7F6C0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000\n\t00000000000000000000000000FFAC4D0000000000000000000000000000000000000000000000000000000000000000000000ea8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFD93400000000000000000000000000000000000000000000000000000000000000000000000000040000\n\t00000000000000000000000000000004000000000000000000000000000000000000FFD93400000000000000000000000000\n\t0000000000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FFD934000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004000000000000000000000000000000000004000000000000000000000000000000000000FFD934000000000000000000001a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFF230000000000000000000000000000000\n\t0000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF43730000000000000000000000000000000000000000000000000000000000000000000080000004\n\t000000000000000000000000000080000004000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000020000000000000000000000000001000000020000000000000000000000\n\t00000000000000FF035D00000000000000000000000000000000000000000000000000000000000000000000000000000001\n\t10000000000000000000000000000000000010000000000000000000000000000000FF961A00000000000000000000000000\n\t0000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFF230000000000000000000000000000000000000000000000000020000000000000000000000005a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF035D000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000110000000000000000000000000000000000010000000000000\n\t000000000000000000FF7F6C0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000002000000000000000000000000000000000000FF35C1000000000000000000000000da8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000400000000000000000000000000000000000000FFFB300000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000\n\t00000000000000FFBD4F00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000080000000000000000000000000000000000000FFD08700000000000000000000000000\n\t0000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000003a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000008200000000000000000000000000000000000200000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFEE47000000000000000000000000000000000000000000000000000000000000000000000000040000ba8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF2E310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000400000000000000000000000000000000000000FF20A00000000000000000000000000000000000\n\t0000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFE44300000000000000000000000000007a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF789C00000000000000000000000000000000000000\n\t0000000000000000010000000000000020000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF805A010000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF7E700100000000000000000000000000000000000000000000000000000000000000000000000028000000000000\n\t000000000000000000000028000000000000000000000000000000000000FF1C450000000000000000000000000000000000\n\t0000000000000000000001000000000000004000020000000000000000000000000000000000020000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000068040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFBEB1000000000000000000000000000000000000000000000000000000000000000000000000002800000000\n\t0000000000000000000000000028000000000000000000000000000000000000FF409B00000000000000000000000000000000868040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000468040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000020000000000000000000000000000000000020000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000c68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t17F5000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000\n\t0000000000000200000000000000000000000000000000000000FFD934000000000000000000000000000000000000000000\n\t0000000000000000000000000000000004000000000000000000000000000000000004000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFAC4D000000000000000000000000000000000000268040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000004000000000000000000000000000000000000FFAA230000000000000000000000000000000000000000000000\n\t00000000000000000000000000020C0000000000000000000000000000000802840000000000000000000000000000000000\n\t00FFFD4D000000000000000000000000000000000000000000000000000000000000000000000000000C0000000000000000\n\t00000000000000080084000000000000000000000000000000000000FFD93400000000000000000000000000000000000000\n\t000000000000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000a68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000800000000000000000000000000000000000800000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFD934000000000000000000000000000000000000000000\n\t0000000000000000000000000000000004000000000000000000000000000000000004000000000000000000000000000000\n\t000000FFD934000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000668040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFD934\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000\n\t000000000004000000000000000000000000000000000000FFC48F0000000000000000000000000000000000000000000000\n\t0000000000000000000000000008040000000000000000000000000000000008040000000000000000000000000000000000\n\t00FF35E200000000000000000000000000000000000000000000000000000000000000000000000000060000000000000000\n\t00000000000000000006000000000000000000000000000000000000FF5D200000000000000000000000000000000000000000e68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000004000000000000000000000000000000000000FFB5E600000000000000000000000000000000000000000000000000\n\t00000020000000000000200006000000000000000000000000000000000006000000000000000000000000000000000000FF\n\t4613000000000000000000000000000000000000000000000010000000044000000010008040044400000010010040044000\n\t0000100000000004000000000000000000000000000000000000FFE761000000000000000000000000000000000000000000\n\t000000004000000000000000000000000400000000000000000000000000000000000400000000000000000000000000000000168040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF982F0000000000000000000000000000000000000000000000\n\t0000000000000000000800800002200000000800802002200000000800000000000000000000000000000000000000000000\n\t00FFD9340000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000968040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t6B09000000000000000000000000000000000000000000000010004000040000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000568040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FFDF7C000000000000000000000000000000000000000000000000000000\n\t0000000000000000000200000000000000000000000000000000000008000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF38CB0000000000000000000000000000000000000000000000\n\t000000000000000000000000000AA0000000000000000000000000000000000808000000000000000000000000000000000000d68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000001100000000000000000000000000000000001100000000000000000000000000000000000000FF757B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000009500000000000000000000000000000\n\t00000940000000000000000000000000000000000000FF80AA00400000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tBA9700000000000000000000000000000000000000000000000000000000000000000000000000A00000000000000000000000368040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (CD3C00000000\n\t0000000000000000000000000000000000000000000000000000000000000000090000000000000000000000000000000000\n\t0800000000000000000000000000000000000000FFA0F4000000000000000000000000000000000000000000000000000000\n\t0000000000000000000800000000000000000000000000000000000880000000000000000000000000000000000000FF8346\n\t0040000000000000000000000000000000000000000000000000000000000000000000000050000000000000000000000000\n\t000000000040000000000000000000000000000000000000FF505A000000000000000000000000000000000000000000000000b68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000200\n\t000000000000000000000000000000000000FF76970000000000000000000000000000000000000000000000000000000000\n\t000000000000000900000000000000000000000000000000000900000000000000000000000000000000000000FFBBEA0008\n\t0000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000\n\t00001000000000000000000000000000000000000000FF809C00080000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00768040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000400000000000000000000000000000000000400000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF6C4A000800000000000000000000000000000000000000000000000000\n\t0000000000000000000002000000000000000000000000000000000002000000000000000000000000000000000000FF17F5\n\t000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000f68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000000\n\t0000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000800\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5D200000\n\t0000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000\n\t00000800000000000000000000000000000000000000FFEE4700000000000000000000000000000000000000000000000000000e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF709D400800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAD21008e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFACD2000800000000\n\t0000000000000000000000000000000000000000000000000000000000000002100000000000000000000000000000000002\n\t000000000000000000000000000000000000FF7BED0000000000000000000000000000000000000000000000000000000000\n\t000000000000001000000000000000000000000000000000001000000000000000000000000000000000000000FFE0D00008\n\t0000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000004e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF5D2000000000000000000000000000000000000000000000000000000000000000\n\t00000000000800000000000000000000000000000000000800000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000ce8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080200000000\n\t0000000000000000000000000000FF2E17000000000000000000000000000000000000000000000000000000000000000000\n\t0000000404000000000000000000000000000000000204000000000000000000000000000000000000FFAC4D000000000000\n\t0000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000002\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF989A2000002e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000C04000000000000000000000000000000000A04000000000000000000000000000000000000FFD9340000000000000000\n\t0000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000040000\n\t00000000000000000000000000000000FFFE9540000000000000000000000000000000000000000000000000000000000000\n\t00000000001006000000000000000000000000000000001006000000000000000000000000000000000000FF71F100080000\n\t000000000000000000000000000000000000000000000000000000000000000008020000000000000000000000000000000000ae8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFD934000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004000000000000000000000000000000000004000000000000000000000000000000000000FF629F000000000000\n\t0000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000104\n\t000000000000000000000000000000000000FF33AC0000000000000000000000000000000000000000000000000000000000006e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FFB90F0000000000000000000000000000000000000000000000000000000000000000000000\n\t000204000000000000000000000000000000000004000000000000000000000000000000000000FFD9340000000000000000\n\t0000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000040000\n\t00000000000000000000000000000000FF8E3080000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000400000000000000000000000000000000000000FF08950000000000ee8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF2E1700000000000000000000\n\t0000000000000000000000000000000000000000000000000000040400000000000000000000000000000000020400000000\n\t0000000000000000000000000000FF35E2000000000000000000000000000000000000000000000000000000000000000000\n\t0000000006000000000000000000000000000000000006000000000000000000000000000000000000FFACE9000800000000\n\t0000000000000000000000000000000000000000000000000000000000000084000000000000000000000000000000000084001e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000210000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF54708008000000000000000000000000000000000000000000000000000000000000000000\n\t208000000000000000000000000000000000660000000000000000000000000000000000000000FF50530000000000000000\n\t0000000000000000000000000000000000000000000000000000200000040000000000000000000000000000800000040000\n\t00000000000000000000000000000000FF809C00080000000000000000000000000000000000000000000000000000000000009e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF125600000000000000000000000000000000000000000000000000000000000000000000400000\n\t00000000000000000000000000000100000000000000000000000000000000000000000000FFDC2980001000000000000000\n\t0000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000008000000\n\t0000000000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF855F800000000000005e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000008000\n\t0000000000000000000000000000000100000000000000000000000000000000000000FF859A000010000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFF3FC0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000100000de8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFAC4D00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000200000000\n\t0000000000000000000000000000FF133F800000000000000000000000000000000000000000000000000000000000000000003e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF209D800800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFDBB8900000000000000000000000\n\t0000000000000000000000000000000000000000000000000400000000000000000000000000000000000200000000000000\n\t000000000000000000000000FFF5410000000000000000000000000000000000000000000000000000000000000000000000\n\t000080000000000000000000000000000000000080000000000000000000000000000000000000FF80FA008000000000000000be8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFB1D80880000000000000000000000000\n\t0000000000000000000000000000000000000000000004000000000000000000000000000000000002000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000002\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF7C7E000000000000000000000000000000000000000000020002000000000000000000000000000000\n\t0000000000000000000000000000000000400000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000fe8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF211A0000000000000000000000000000000200000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFE95300000000000000000000000000000000000000000004000400000000000000000000000000\n\t00000000000000000000000000000000000000400000000000000000000000000000000000FF81190006000000000000000000018040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000002000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000818040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF7B8D0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000480000880000000000000000000000002203200000080000000000\n\t00000000000000000000FF368D0000000000000000000000000000000000000008000000000000000000000000000000000000418040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF3209000000000000000000000000000000000000000000000000000000000000000000000000002800\n\t0088000000000000000000000000420420000008000000000000000000000000000000FFBD4F00000000000000000000000000c18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000404000000000000000000000000000000000000FF20A0000000000000000000000000000000000000\n\t0000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFD9340000000000000000000000000000000000000000000000000000000000000000000000000004000000\n\t000000000000000000000000000004000000000000000000000000000000000000FF06E40000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000180000000000000000000218040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000\n\t00000000FFB90F00000000000000000000000000000000000000000000000000000000000000000000000002040000000000\n\t00000000000000000000000004000000000000000000000000000000000000FFD93400000000000000000000000000000000\n\t0000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000000000\n\t0000000000000000FFB79E00000000000000000000000000000000000000000000000000000000000000000000000000040000a18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFB79E0000000000000000000000000000000000000000000000000000000000000000000000000004000000\n\t000000000000000000000000000404000000000000000000000000000000000000FFD934000000000000000000000000000000618040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000000\n\t000000000000000004000000000000000000000000000000000000FFD9340000000000000000000000000000000000000000\n\t0000000000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000\n\t00000000FFD93400000000000000000000000000000000000000000000000000000000000000000000000000040000000000\n\t00000000000000000000000004000000000000000000000000000000000000FFD93400000000000000000000000000000000\n\t000000000000000000000000000000000000000000040000000000000000000000000000000000040000000000000000000000e18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000400000000000000000000000000000000000400000000000000000000000000000000\n\t0000FF52A3000000000000000000000000000000000000000000020002000000000000000000000000000000000000000002\n\t0000000000000000000000000000000000000000000000000000000000FF189C000000000000000000000000000000000000\n\t000000050004000000001000051008000000000C000508000000040020000508400000000004000000000000000000000000\n\t000000000000FFA675000000000000000000000000000000000000000000000000000000000000000000000000000400000000118040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF632600000000000000000000000000000000000000000000000000000000000000880800000000080002882000\n\t00000020000288200000000000000000000000000000000000000000000000FFD9340000000000000000000000000000000000918040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000810000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF520A000000000000000000000000000000000000\n\t000000010000000000001000040000000000000000000000000000000000000000000000000000000000000000000000000000518040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFE29B0000000000000000000000000000000000000000000000000000000000000000000000000800000000000000d18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF7B\n\tED00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000\n\t00000000001000000000000000000000000000000000000000FF5D2000000000000000000000000000000000000000000000\n\t0000000000000000000000000000080000000000000000000000000000000000080000000000000000000000000000000000\n\t0000FFBF47000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000008000000000000000000000000000000000000FF409B00000000000000000000000000000000000000318040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000002000000000000000000000000000000000000FF5D20000000000000000000000000000000000000000000000000\n\t0000000000000000000000000800000000000000000000000000000000000800000000000000000000000000000000000000\n\tFF76970000000000000000000000000000000000000000000000000000000000000000000000000900000000000000000000\n\t000000000000000900000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000400000000000000000000000000000000000400000000000000000000000000000000000000FF5D\n\t2000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000\n\t00000000000800000000000000000000000000000000000000FF7BED00000000000000000000000000000000000000000000\n\t0000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000000000000\n\t0000FFAC4D00000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000718040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF77CE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000200000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF19970000000000000000000000000000000000000000000000000000000000000000000000000082000000000000000000\n\t000000000000000082000000000000000000000000000000000000FFEE47000000000000000000000000000000000000000000f18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t001000000000000000000000000000000000000000FF7BED0000000000000000000000000000000000000000000000000000\n\t000000000000000000001000000000000000000000000000000000001000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF9D5600000000000000000000000000000000000000000000\n\t00000000000000000000000000000C000000000000000000000000000000000008000000000000000000000000000000000000098040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF0097000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000\n\tFF7BED000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000898040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFA3CA000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000\n\t000000000200000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAC\n\t4D00000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000\n\t00000000000002000000000000000000000000000000000000FF83CC0000000000000000000000000000000000000000000000498040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000002\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5D2000\n\t0000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000\n\t0000000800000000000000000000000000000000000000FF2D53000000000000000000000000000000000000000000000000\n\t000000000000000000000000010000000000000000000000000000000000008000000000000000000000000000000000000000c98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000800000000000000000000000000000000000800000000000000000000000000000000000000FFD934000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000\n\t000004000000000000000000000000000000000000FF2D530000000000000000000000000000000000000000000000000000\n\t000000000000000000000100000000000000000000000000000000000080000000000000000000000000000000000000FF17\n\tF50000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000298040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (250000000000\n\t000000000000000000000000000000000000000000000000000000000000000804000000000000000000000000000000000C\n\t04000000000000000000000000000000000000FF20A000000000000000000000000000000000000000000000000000000000\n\t00000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000FFE24200\n\t0000000000000000000000000000000000000000000000000000000000000000000000100400000000000000000000000000\n\t0000001004000000000000000000000000000000000000FF5D2000000000000000000000000000000000000000000000000000a98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFAC4D000000000000000000000000000000000000000000000000000000000000\n\t0000000000000002000000000000000000000000000000000002000000000000000000000000000000000000FFD934000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000\n\t000004000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAA00698040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000006000000000000000000000000000000000006000000000000000000000000000000000000FFD9340000000000\n\t0000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000\n\t04000000000000000000000000000000000000FFD93400000000000000000000000000000000000000000000000000000000\n\t00000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000200\n\t0000000000000000000000000000000000FFD934000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FFD934000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000\n\t000004000000000000000000000000000000000000FF35E2000000000000000000000000000000000000000000000000000000198040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF51AE00000000000000000000000000000000000000000000000000000000\n\t00000000000000020004000000000000000000000000000200000004000000000000000000000000000000000000FFAC4D0000998040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFD96500000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008\n\t0000000000000000000000000000000000FFE89B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000080000000000000000000000000000000FFC801000000\n\t000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000020000598040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000\n\t000000000000000000000000000000FFE89B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000080000000000000000000000000000000FFD9650000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00080000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000d98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF80ED00000000000000000000000000000000000000000000000000000000000000000000\n\t00000400000000000000000000000000000000000000000000000000000000000000000000000000FF089500000000000000\n\t0000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBD4F00000000398040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0002000000000000000000000000000000000402000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF6B2C0000000000\n\t000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000100b98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000\n\t00000000000000000000000000FF77CE00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000200000000000000000000000000000000000000FF20A000000000000000\n\t0000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF62E680000000000000000000000000000000000000000000000000000000000000798040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FFAC21000000000000000000000000000000000000000000000000000000000000000000000000\n\t0208000000000000000000000000000000000000000000000000000000000000000000000000FF62FA004000000000000000\n\t0000000040000000000000000000000000000000000100000480000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF7F6C000000000000f98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF0C6C0000000000000000000000\n\t0000000000000000000000000000000000000000000000000004080000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFB5AC00400000000000\n\t000000000000400000000000000000000000000000000001000005000000020000000000000000000000000000000000020000058040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000010000000000000000000000000000000000010000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000858040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FFF5410000000000000000000000000000000000000000000000000000000000000000000000000080\n\t000000000000000000000000000000000080000000000000000000000000000000000000FF5B010020000000000000000000\n\t0000000000000000000000000000000000000000000000000000020000000000000000000000000000000002020000000000\n\t00000000000000000000000000FFEE2800200000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000400000000000000000000000000000000000000FF6B2C0000000000000000458040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000404000000000000000000000000000000000004000000000000000000\n\t000000000000000000FF80FA0080000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFD9340000000000000000000000\n\t0000000000000000000000000000000000000000000000000000040000000000000000000000000000000000040000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000258040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFD93400000000000000000000000000000000000000000000000000000000000000000000000000040000\n\t00000000000000000000000000000004000000000000000000000000000000000000FF194200000000000000000000000000\n\t0000000000000000000000000000000000000000000000040400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FF35E2000000000000000000000000000000000000000000000000000000000000000000000000\n\t0006000000000000000000000000000000000006000000000000000000000000000000000000FFD92300800000000000000000a58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000400000000\n\t0000000000000000000000000004000000000000000000000000000000000000FFD087000000000000000000000000000000\n\t0000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF515B0080000000000000000000\n\t000000000000000000000000000000000000000000000000000084000000000000000000000000000000000004000000000000658040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000060000000000000000000000000000000000060000000000000000000000\n\t00000000000000FFD93400000000000000000000000000000000000000000000000000000000000000000000000000040000\n\t00000000000000000000000000000004000000000000000000000000000000000000FFD93400000000000000000000000000\n\t0000000000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FF195500800000000000000000000000000000000000000000000000000000000000000000000000e58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFD934000000000000000000000000000000000000000000000000000000000000000000000000000400000000\n\t0000000000000000000000000004000000000000000000000000000000000000FFCFA6000000000000000000000000000000\n\t0000000000000000000000000000000020000080000004000000000000000000000000000000000004000000000000000000\n\t000000000000000000FF1D530000000000000000000000000000000000000000000000000400000000000040000110000004\n\t000040000120000000000080000000000004000000000000000000000000000000000000FF35E2000000000000000000000000158040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF4F6900000000000000000000000000\n\t000000000000000000000000000000000000000000080000000000200000A00000000000800000000000000000000000000000958040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000008D000000000000000000000000000000000080000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF65CE000000000000000000000000000000000000000000000000040000000000000000000000000000558040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF08950000000000000000000000000000000000000000000000000000000000000000000000000080000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFAC4D0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000020000000000000000000000000000000000020000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF68280000000000000000000000000000d58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF843100000000000000000000000000000000000000\n\t0000000000000000000000000000000000100000000000000000000000000000000000100800000000000000000000000000\n\t0000000000FFEF22000000000000000000000000000000000000000000000000000000000000000000000000082000000000\n\t0000000000000000000000000800000000000000000000000000000000000000FF73A1000000000000000000000000000000\n\t000000000000000000000000000000000000000000000800000000000000000000000000000000001000000000000000000000358040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000180000000000000000000000000000000\n\t000000FF5D200000000000000000000000000000000000000000000000000000000000000000000000000800000000000000\n\t000000000000000000000800000000000000000000000000000000000000FF152E0000000000000000000000000000000000\n\t0000000000000000000000000000000000000008800000000000000000000000000000000008000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000b58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF20A000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF5D2000000000000000000000000000000000000000\n\t0000000000000000000000000000000000080000000000000000000000000000000000080000000000000000000000000000\n\t0000000000FF7BED000000000000000000000000000000000000000000000000000000000000000000000000100000000000\n\t0000000000000000000000001000000000000000000000000000000000000000FF06E400000000000000000000000000000000758040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000C00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF2E310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000400000000000000000000000000000000000000FF3C510000000000000000000000000000000000\n\t000000000000000000000000000000000000000102000000000000000000000000000000000002000000000000000000000000f58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF9B6000000000000000000000000000000000000000000000000000000000000000000000000008020000000000000000\n\t00000000000000040802000000000000000000000000000000000000FF6C5700000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000\n\t0000000000FFF3FC0000000000000000000000000000000000000000000000000000000000000000000000000C0000000000000d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t20D7000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF1903000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000\n\t000000FFCF6D0000000000000000000000000000000000000000000000000000000000000000000000000000000400000000\n\t000000000000000000020000000400000000000000000000000000000000FF409B0000000000000000000000000000000000008d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF00D10000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000800000000000000000000000000000000000002000000000000000000000000000000\n\t00FF9A2A00000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000\n\t00000000000000000000000000000000000000000000000000000000FF7BED00000000000000000000000000000000000000\n\t0000000000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000000004d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF5D20000000000000000000000000000000000000000000\n\t0000000000000000000000000000000800000000000000000000000000000000000800000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF5D20\n\t0000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000\n\t000000000800000000000000000000000000000000000000FF2E170000000000000000000000000000000000000000000000\n\t0000000000000000000000000004040000000000000000000000000000000002040000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000002d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000104000000000000000000000000000000000000FFA4B400000000000000000000000000000000000000000000000000\n\t00000000000000000000000A04000000000000000000000000000000000804000000000000000000000000000000000000FF\n\tD934000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000\n\t0000000000000004000000000000000000000000000000000000FFD517000000000000000000000000000000000000000000\n\t000000000000000000000000000000100400000000000000000000000000000000120400000000000000000000000000000000ad8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0895\n\t0000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFD9340000000000000000000000000000000000000000000000\n\t0000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000000000\n\t00FF629F00000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000006d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF913A0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000840000000000000000000000000000\n\t00000004000000000000000000000000000000000000FFD7A500000000000000000000000000000000000000000000000000\n\t00000000000000000000000204000000000000000000000000000000000404000000000000000000000000000000000000FF\n\tC836000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000\n\t0000000000000086000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000ed8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000008000\n\t0004000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF1942\n\t0000000000000000000000000000000000000000000000000000000000000000000000000404000000000000000000000000\n\t000000000004000000000000000000000000000000000000FFEE610000000000000000000000000000000000000000000000\n\t0000000000000000000000000000040000000000000000000000000000000002040000000000000000000000000000000000001d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF961A0000\n\t0000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFADED00000000000000000000000000000000000000000000000000\n\t00000000000000000080010000000000000000000000000000000400000000000000000000000000000000000000000000FF\n\t95F2000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000009d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A8AF00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000\n\t0000000000000000000000000000000000000000FF0E36000000000000000000000000000000000000000000000000000000\n\t0000000000000000010002000000000000000000000000000500000002000000000000000000000000000000000000FF9C86\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000005d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FFBD4F0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000FF8E940000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000\n\t00000000000000000000000000000000000000000000FFA8AF00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000FF00dd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000100000000000000000000000000000000000080000000000000000000000000000000000000FF80ED00000000\n\t0000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFAC4D000000000000000000000000000000000000000000000000000000\n\t0000000000000000000002000000000000000000000000000000000002000000000000000000000000000000000000FF0895\n\t0000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000003d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000400\n\t000000000000000000000000000000000000FFAC4D0000000000000000000000000000000000000000000000000000000000\n\t000000000000000002000000000000000000000000000000000002000000000000000000000000000000000000FFAC4D0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000\n\t00000002000000000000000000000000000000000000FF2D530000000000000000000000000000000000000000000000000000bd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF058600000000000000000000000000000000000000000000000000000000000000\n\t00000000000100000000000000000000000000000000000500000000000000000000000000000000000000FF77CE00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0200000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEE0B007d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000000000\n\t0000000100000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF027A0000000800000000000000000000000000000000000000080000000400\n\t000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000002800000\n\t00000000000000000000000000000000FFC09100000000000000000000000000000000000000000000000000000004000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEC4800000000\n\t0000000000000000000000000000000000000000000000020000000000000000000200000000000000000000000000000000\n\t0002000000000000000000000000000000000000FF054400000010000000000000000000000000000000000000001000000000038040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020800000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC214000000838040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0004A0000000000000000000000000000000000208000000000000000000000000000000000000FF8C4B0000000000000000\n\t0000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF122500000000\n\t000000000000000000000000000000000000000000000000000000000000000002A00000000000000000000000000000000000438040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000088008000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFA140000000000000000000000000000000000000000000010000000000000000000000\n\t0000001002000000000000000000000000000000000002000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFB268000000000000000000000000000000000000000000000000000000000000c38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FFD7A50000000000000000000000000000000000000000000000000000000000000000000000\n\t000204000000000000000000000000000000000404000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFF17600000000000000000000000000000000000000000000000000000000000000\n\t00000000000084080000000000000000000000000000000004000000000000000000000000000000000000FFA8360000000000238040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t04080000000000000000000000000000000004000000000008000000000000000000000000FF7CD400000000000000000000\n\t0000000000000000000000010000000000000000000000000000000000000180000000000000000180000000000000000000\n\t0000000000000000000000000000FFFB2A000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004000000000000000000000000000000020204000000000000000000000000000000000000FF95A6000000000000\n\t000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000002000000a38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000100000080000000000000000000000004000000000000000000000000000000000004000000000008\n\t000000000000000000000000FF80030000000000000000000000000000000000000000000000000000000000000000000000\n\t000000100000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF8DD50000000000000000000000000000000000000000000000000080000000000000638040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF16EF00000000000000000000000000000000000000000000000000000000000000004000000004\n\t00000000400000000400000000000000000000000000000000000000000000000000000000FFD93400000000000000000000\n\t0000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000400000000\n\t0000000000000000000000000000FFD934000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004000000000000000000000000000000000004000000000000000000000000000000000000FF214900000000000000e38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000068000\n\t0000200000008208000000000000000000000000000000000000000000000000000000FF1E35000000000000000000000000\n\t0000000000000000000000000000000000800000000000000004000000000000000000000000000000000004000000000800\n\t000000000000000000000000FF14D20000000000000000000000000000000000000000000000080000000080800000000000\n\t000004000000000000000000000000000000000004000000000800000000000000000000000000FF94670000000000000000\n\t000000000000000000000000000000100000000140000000100000400084000000000000010010000000000000000004000000138040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000400000000000004000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF20A000000000000000000000000000000000000000000000000000000000000000000000000002\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFCB9500000000000000000000000000000000000000000000000000000000000000002800938040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF23CA000000000000000000000000000000000000000000000000000000000000000000000000080000\n\t0000000000000000000000000000000840000000000000000000000000000000000000FF0D45000000000000000000000000\n\t0000000000000000000000000000000000000000000000000020000000000000000000000000000000000008000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF0090000000000000000000538040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFCE440400000000000000000000000000\n\t0000000000000000000000000000000000000000000000200000000000000000000000000000000000080000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF8639000000000000000000000000000000000000000000000000000000000000000000000000100000\n\t0000000000000000000000000000001080000000000000000000000000000000000000FFD9FE000000000000000000000000\n\t0000000000000000000000000000000000000000000000000800000000000000000000000000000000000920000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000338040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF809C0008000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF5D200000000000000000000000000000\n\t0000000000000000000000000000000000000000000008000000000000000000000000000000000008000000000000000000\n\t00000000000000000000FF5D2000000000000000000000000000000000000000000000000000000000000000000000000008\n\t00000000000000000000000000000000000800000000000000000000000000000000000000FF839A0400000000000000000000b38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF5D20000000000000000000000000000000000000000000000000000000000000000000000000080000\n\t0000000000000000000000000000000800000000000000000000000000000000000000FFBBEA000800000000000000000000\n\t000000000000000000000000000000000000000000000000100000000000000000000000000000000000100000000000000000738040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000800000000000000000000000000000000000800000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF809C0008000000000000000000000000000000000000000000000000000000000000000000000000f38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF5F5840080000000000000000000000000000000000000000000000000000000000000000000010000000000000\n\t00000000000000000000201000000000000000000000000000000000000000FFF80640000000000000000000000000000000\n\t0000000000000000000000000000000000040004100000000000000000000000000000010040100000000000000000000000\n\t0000000000000000FF5E7F000000000000000000000000000000000000000000000000000000000000000000000040000000\n\t0000000000000000000000080000000000000000000000000000000000000000000000FF5D20000000000000000000000000000b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010000000000\n\t0000000000000000000000000000000000000000000000000000000000FFB09D000800040000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFA5410000000000000000000000000000000000000000000000000000000000000000000000200000000000\n\t000000000000000000100000000000000000000000000000000000000000000000FFAB700000000000000000000000000000\n\t0000000000000000000000000000000000000002000200000001000000000000000000000000800000000000000000000000008b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000004000000000000000000000000000000000002000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE09400080000000000800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF5E3F000000020000008000000000000000000000000000000000000000000000000000000000000000004b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF85212000000000000000000000000000000000000000000000000000000000000000000000000800000000\n\t000000000000000000000000000800000000000000000000000000000000000000FFB7B8000000000000000000000000000000cb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000001004000000000000000000000000000000000000FF04880008000000000000000000000000000000000000\n\t0000000000000000000000000000000008040000000000000000000000000000000008040000000000000000000000000000\n\t00000000FF27A440000000000000000000000000000000000000000000000000000000000000000000000002040000000000\n\t00000000000000000000000404000000000000000000000000000000000000FF17F500000000000000000000000000000000\n\t0000000000000000000000000000000000000000020000000000000000000000000000000000020000000000000000000000002b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000040600000000000000000000000000000000000600000000000000000000000000000000\n\t0000FFAA25000000000000000000000000000000000000000000000000000000000000000000000000080400000000000000\n\t0000000000000000000C04000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF8279000000000000000000000000000000000000000000000000000000000000000000000000120400000000ab8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFE09A8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFEE6100000000000000000000000000000000000000000000000000000000000000000000000000040000000000\n\t00000000000000000000000204000000000000000000000000000000000000FFF59400000000000000000000000000000000006b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF8E5A00000000000000000000000000000000000000000000\n\t0000000000000000000000000000020400000000000000000000000000000000020400000000000000000000000000000000\n\t0000FF77E8000000000000000000000000000000000000000000000000000000000000000000000000040400000000000000\n\t0000000000000000000404000000000000000000000000000000000000FFF5EF001000000000000000000000000000000000\n\t000000000000000000000000000000000000000600000000000000000000000000000000000600000000000000000000000000eb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000\n\tFF77990008000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000\n\t000000000000000404000000000000000000000000000000000000FFB90F0000000000000000000000000000000000000000\n\t0000000000000000000000000000000002040000000000000000000000000000000000040000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFE0\n\t9A80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFD934000000000000000000000000000000000000009b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFAC4D0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000020000000000000000000000000000000000020000000000000000000000000000005b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000FF8E\n\t3080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000400000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFEE470000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000\n\t000000000000000400000000000000000000000000000000000000FF20A00000000000000000000000000000000000000000003b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000400000000000000000000000000000000000000FF80A18000000000000000000000000000000000000000000000000000\n\t000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000FF80\n\t9C00080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF820B10000000000000000000000000000000000000000000\n\t000000000000000000000000000002000000000000000000000000000000000004000000000000000000000000000000000000bb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAC4D00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000\n\t0000000002000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFE2301000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFFA1D000000\n\t00000000000000000000000000000000000001000000000000100004000000000D0002000000000000000000000000000000\n\t000002000000000000000000000000000000000000FF522E0000000000000000000000000000000000000000000000000000\n\t000000000000000000000038000400000000000000000000020400000088000100000000000000000000000000000000FF78\n\t3000000000000000000000000000000000000000000000800000000000080004000000000B00080002000000000000000000\n\t00000200000000000080000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000fb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFAC4D00000000000000000000000000000000000000000000000000000000\n\t00000000000000000002000000000000000000000000000000000002000000000000000000000000000000000000FF6F6700\n\t0000000000000000000000000000000000000000000000000000000000000000000000083000000000000000000000000000\n\t0000000110000000000000000000000000000000000000FFF7ED000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000078040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000210000000000000000000000000000000000200000000000000000000000000000000000000FFD6BF002000\n\t0000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000400\n\t000040000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80\n\t740000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000878040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (310000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004\n\t00000000000000000000000000000000000000FF64B900200000400400000000000000000000000000000008400001000100\n\t00000000000000158000000800000000000000000000000200000020000000000000000000000000000000000000FFFFC900\n\t0000000000000000000000000000000000000000080000000000000000000000000000020800080000000000000000000000\n\t0000000000000000000000000000000000000000000000FF4EF400000000000000000000000000000000000000000000000000478040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800000400\n\t0020000000000000000000000000000000FF9D90000000000000000000000000080000000000000020000024000000000000\n\t0000000180140000198A98000000000000000000000008000180000020000000000000000000000000000000FF3797000000\n\t0040040000000000000000000000000000000040000100008000000020000000010000001000000000000000000000000000\n\t000000000000000000000000000000000000000000FF009E0000000000000000000000000000000000000000000000028000\n\t000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2E00c78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00040002008400020000000000000000000000008000008C000000000000000000000000000000000000FF2D9F0000000000\n\t0000000000000000000000000000000000000000000000000000000002000000040000000000000000000000000000000004\n\t04000000000000000000000000000000000000FF20A000000000000000000000000000000000000000000000000000000000\n\t00000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000FF050A00\n\t000000000000000000000008000000000000002000002100000000000000000000000000040002800000000000000000000000278040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000002080002000000008000000000000024000400002008800000000000000000000000008600\n\t0000080080000000000000000000000000FFB81A00000000010000000000000000000200000000000000004800C000000000\n\t0000000000000547941C00000000000000000000000000000004000000000000000000000000000000000000FF5A43000000\n\t0000000000000000000000000000000000000000000000000000000000000000000284000200000000000000000000000080\n\t00050C000000000000000000000000000000000000FF9D2D000000000000000000000000000000000000000000000000000000a78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004000000\n\t000000000000000000000000000000FF558C0000000001000000000000000000000000000000020006420040000000000000\n\t000000000006100020088000000000000000000000000086000000080000000000000000000000000000FF3B9C0000000000\n\t0000000000000000000400000000000010060001000001000000000000004005400402000000000000000000000000000000\n\t02000000000000000000000000000000000000FF15AB00000000000000000000000000000000000000000000001000000000\n\t00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000FF6C370000678040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100005100C00\n\t0000000C000020080000000020400480000000000004000000000000000000000000000000000000FFAFD500000000000000\n\t0000000000000000000000000000002E00000000000000000000008000000400040000040000000000000040000000000600\n\t0000000000000000000000000000000000FF539F000000000000000000000000000000000000000000000600000000000000\n\t0000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF539F000000\n\t000000000000000000000000000000000000000600000000000000000000000000000400000000000000000000000000000000e78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000060000000000000002080A0080000008200220080200000020200280200000000000000000\n\t000000000000000000000000000000FFF5160000000000000000000000000000000000000000000806000000000000000000\n\t000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF79300000000000\n\t00000000000000000000000000000000088E0000000002080000800000000000044000000000000000000000000000000000\n\t04000000000000000000000000000000000000FFCA6D0000000000000000000000000000000000000000000506040000000400178040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020000000000\n\t00000000000000000000000000FF1FDC00000000000000000000000000000000000000000004460400000000000000000000\n\t00000800000000000000000000000000000000000000000000000000000000000000000000000000FF0BED00000000000000\n\t0000000000000000000000000000000600000000000000000000000000100000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFCA30000000000000000000000000000000000000000000000600000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFD1000000000978040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFBA5E000000000000000000\n\t00000000000000000000000010160000000000000000000000000008C0000000000000000000000000000000000800000000\n\t000000000000000000000000000000FFF5C70000000000000000000000000000000000000000000006000000000000000000\n\t000000000000000000000000000000000000000000000002000000000000000000000000000000000000FF26E60000000000\n\t000000000000000000000000000000000006000000000000000000000000000002000000000000000000000000000000000000578040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000A0000000000000000000000000000200000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF089500000000000000000000000000000000000000000000000000000000000000000000\n\t00000080000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFCA3000000000000000000000000000000000000000000000060000000000000000d78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FFCA30000000000000000000000000000000000000000000000600000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFD6C6000000000000000000\n\t0000000000000000000000001202000000000000000000000000001000000000000000000000000000000000001000000000\n\t000000000000000000000000000000FFAE650000000000000000000000000000000000000000000400000000000000000000\n\t000000000800000000000000000000000000000000000800000000000000000000000000000000000000FF2D67000000000000378040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001000\n\t000000000000000000000000000000001000000000000000000000000000000000000000FF9DBE0008000000000000000000\n\t0000000000000000000008000000000000000000000000000000000000000000000000000000000000000001000000000000\n\t00000000000000000000000000FF6CB700000000000000000000000000000000000000000000020000000000000000000000\n\t00000880000000000000000000000000000000000800000000000000000000000000000000000000FFBF1000000000000000\n\t000000000000000000000000000000040000000000000000000000000008020000000000000000000000000000000008820000b78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000080000000000000000000000000000008000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF8629000000000000000000000000000000000000000000080000000000000000000000000000\n\t0200000000000000000000000000000000000000000000000000000000000000000000000000FF5D20000000000000000000\n\t0000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000800000000\n\t000000000000000000000000000000FF7B1B000800000400000000000000000000000000000000000000000000000000000000778040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF42CB0000000002000000000000000000000000000000000004000000000000000000000000000C02\n\t000000000000000000000000000000000802000000000000000000000000000000000000FF9F8B0000000000000000000000\n\t0000000000000000000008020000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF196400000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000600000000000000000000000000000000000000FF6E1B0008000000000000f78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000140000000000000000000000000000000000FF7D8C40080000000000000000000000\n\t0000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFD36F400000000000000000000000002000000000000000100208000000000000000000000000\n\t0800000000000000000000000000000000000800000000000000000000000000000000000000FF0B11000000000000000000\n\t0000000000000000000000000006000000000000000200000000000000000000000000000000000000000000000000000000000f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000060000000000000000000000000010000000A0000000000000000000000000001000000000000000000000\n\t000000000000000000FF8DB30008000000000000000000000000000000000000000000000000000000000000000000000400\n\t000200000000000000000000000000000000000000000000000000000000000000000000FF82DA0000000000000000000000\n\t0000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF0CC400000000000000000000000000200000000000000000020800000000000000000000008f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFCA3000000000000000000000000000000000000000000000060000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF354500000000000000000000000000\n\t0000000000000000000600000000000010000000000000020000020004000000000000000000000000000008000000000000\n\t0000000000000000000000FFC8BE000880000000000000000000000000000000000000000600000000000008000000000000\n\t00000000A0020000000000000000000000000000040000000000000000000000000000000000FFBAC5000080000000000000004f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFBCED200000000000000000000000000000\n\t0000000000000006000000000000000000000000000400000000000000000000000000000000000400000000000000000000\n\t000000000000000000FF26D000000000000000000000000000000000000000000002AE000000000000000000000000000002\n\t000000000000000000000000000000000002000000000000000000000000000000000000FFD78B0000000000000000000000\n\t000000000000000000000006000000000000000000000000000800000000000000000000000000000000000800000000000000cf8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000002AE0000000000000000000000000010040000000000000000000000000000000010040000000000000000000000\n\t00000000000000FF178C00080000000000000000000000000000000000000000060000000000000000000000000008000000\n\t00000000000000000000000000000800000000000000000000000000000000000000FF53F300000000000000000000000000\n\t0000000000000000055600000000000000000000000000000400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FFCA0600000000000000000000000000000000000000000002AE00000000000000000000000000002f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFAE4B000000000000000000000000000000000000000000000600000000000000000000000000000400000000\n\t0000000000000000000000000084000000000000000000000000000000000000FFE0F8000000000000000000000000000000\n\t0000000000000006000000000000000000000000000C04000000000000000000000000000000000C04000000000000000000\n\t000000000000000000FF539F0000000000000000000000000000000000000000000006000000000000000000000000000004\n\t000000000000000000000000000000000004000000000000000000000000000000000000FF98DE400000000000000000000000af8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000004000000000000000000000000000000000000FF9F678000000000018000000000000000000000\n\t0000000000060000000000000000000000000000020000000000000000000000000000000000020000000000000000000000\n\t00000000000000FF5A1A00000000000000000000000000000000000000000002AE0000000000000000000000000001000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF1B9100000000000000000000000000\n\t0000000000000000000600000000000000000000000000008400000000000000000000000000000000000400000000000000006f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000002AE00000000000000000000000000000400000000000000000000000000000000040400000000000000000000000000\n\t0000000000FF7F4A000000000001000000000000000000000000000000000600000000000000000000000000000400000000\n\t0000000000000000000000000084000000000000000000000000000000000000FF2A12000000000001800000000000000000\n\t00000000000002AE000000000000000000000000000204000000000000000000000000000000000004000000000000000000\n\t000000000000000000FF42FF001000000001000000000000000000000000000000055600000000000000000000000000000400ef8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF6DE00000000000018000000000000000000000000000000006000000000000000000000000000004000000000000\n\t000000000220000000000004000000000000000000000000000000000000FFFF610008000000018000000000000000000000\n\t0000000000060000000000000000000000000000020000000000000000000000000000000000020000000000000000000000\n\t00000000000000FFBD3C00000000000180000000000000000000000000000000060000000000000000000000000004040000\n\t00000000000000000000000000000204000000000000000000000000000000000000FF248300000000000180000000000000001f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000080400000000000000000000000000000000FF55D280000000000180000000000000000000000000\n\t0000000600000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000\n\t0000000000FF25FC800000000001800000000000000000000000000000184600000000000000000000000000800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFEE67800000000001800000000000000000\n\t0000000000000006000000000000000000000000008000000000000000000000000000000058000000000000000000000000009f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0006000000000000000000000000080000020108008000000000000000000000000000000000000000000000000000000000\n\t000000FFFDB10000000000018000000000000000000000000000000006000000000000000000000000080000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF3E230000000000018000000000000000000000\n\t0000000000460000000000000000000000000000000200080080000000000004400000000000000000000000000000000000\n\t00000000000000FFCD4400000000000180000000000000000000000000000000060000000000000000000000000000003001005f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFC90700000000000180000000000000000000000000000000000000000000000000000000000001000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFF91A80000000000180000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF68B5000000000001800000000000000000000000000000000600000000000000000000000000000050000000\n\t0000000000000000000000000000080200000000000000000000000000000000FFAA4500000000000180000000000000000000df8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FFF6BC0000000000AA800000000000000000000000000000\n\t12AA000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF880B0800000000000000000000000000000000000000000000000000000000000000000000000200000000000000\n\t000000000000000000000400000000000000000000000000000000000000FF2DCE0000000000AA8000000000000000000000\n\t0000000002AA0000000000000000000000000001000000000000000000000000000000000001800000000000000000000000003f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF36358800000000AA8000000000000000000000000000001AAA0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFD52700080000000000000000000000000000000000\n\t0000080400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFC7EC00000000015580000000000000000000000000000005560000000000000000000000000000000000000000bf8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t8029000000000000000000000000000200000000000000000080000000000000000000000000000200000000000000000000\n\t0000000000000002000000000000000000000000000000000000FFDD16000400000000000200000000040000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF17F50000000000000000000000000000000000000000000000000000000000000000000000000200000000000000\n\t000000000000000000000200000000000000000000000000000000000000FF409B0000000000000000000000000000000000007f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000280000000000000000000000000000000000000FF8B120000018018018004010000000010018000000000000006\n\t0074060000000000000000000060004000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF046400000000120000000100000000100100000000000018040000040000000000000000000000000000200000000000\n\t00000000000000000000000000000000000000000000000000000000FFDB97000000800800800000800000000C0080000000\n\t000000030032020000000000000000000020004000000000000000000000000000000000000000000000000000000000000000ff8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000804000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t8557000200800000800000000000020000000000000000000A00200200000000000000000000228080000000000000000000\n\t0000000000000280000000000000000000000000000000000000FFCE88000000601000000001000000001001000000000000\n\t1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF3CA3000000800A00800400800000400800800000000000100A00200200000000000000000100228106004000000000004040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF997C\n\t000001C01A000004000000000018010000000000000006006006000000000000000000800001000000000000000000000000\n\t000008000000000000000000000000000000000000000000FF37E10000018018010000000000000018018000000000000006\n\t0060060000000000000000000040000000000000000000000000000000000004000000000000000000000000000000000000\n\t00FF596300000180000180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFCDFB0000018000018004000000004000000000000000804040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000200000A0000000000000000000000000000000FF6CD0000001A01C0080000000000000120000000000000000060040\n\t06000000000000000001004000000000000000000000000000000008000000000000000000000000000000000000000000FF\n\t5A4D000101A01800010014004000111801800000000010010650680604010004000000001001004001000000000000000040\n\t0100100010100200000000040400000000000000000000000000FF5F56000001801801000000000000001801000000000000\n\t000600680600000000000000000000400200000000000000000000000000000000000200000000000000000000000000000000404040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (990600400640\n\t00002080000000800A4006240088080000000020000020000000000006000000080000000000000000000000000000FFB65B\n\t002001C01803810000020000001000800000000010800642C006000018288200180080000140220088080000000020478120\n\t000010000000980000280400000000000000000000000000FFE15C00210180580080001400400000104C0000000000000006\n\t14C0060401000A02000000100140000100000000000000000000001000000800410000A04400000000000000000000000000\n\t00FFEB0000000181580180000000000000104C8000000000000006004006200000000000000000146100800000000000000000c04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFDE060000\n\t018010018000018000000006008000000000000A060040060000000000000000000065000000000000000000000000000000\n\t00000400000000000000000000000000000000000000FF580000000180100080040180000060000000000000000000060048\n\t06000000000000000000004286000000000000000000000000000000000206000000000000000000000000000000000000FF\n\t4427000001801001800401000000000200800000000000000600400600000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF157500000181100280000102000011000000000000000000204040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF961E000001001820800000000000400801800000000000040608700602\n\t8000000000000000024204000020000000000000000080000000000084028000000000000000000000000000000000FF3126\n\t0000018018118000528100000009418000100001800406216006100040328000000100016000900000040400000000010030\n\t010100000000201C00420400100000000000000000000000FF6091000001401A008000008000000008010000000000001006\n\t006006000000000000000000004006000000000000000000000000000000000006000000000000000000000000000000000000a04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006000000\n\t000000000000002000006000000000000000000000000000000000000000000000000000000000000000000000FFFB480000\n\t0080183000004001000180045180000000000000060060061008002000000000000020040040000400000000000000100101\n\t00000104028000000400000000000000000000000000FF8951000001801801800004000001C0020080001000000002061160\n\t06050840140000000100052400104000000200000000010140000000000000200200240000080000000000000000000000FF\n\tD5E7000001A01A0180001000000000090900000000000000064060060000000100000000001860008000400000000000000000604040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3E9E000400C0\n\t1010000000000001800400000000000000000600744600000000004000011000000600408000000800010010014000000000\n\t0006000400000000000000000000000000000000FF5328000001801001800000000001800001000000000000000600608600\n\t0000000000000000000000004000000400000000000000000000000400000000000000000000000000000000000000FFF1E5\n\t0000008018000000000000018000018000000000000006006006000000000000000000002004006000000000000000000000\n\t000000000004000000000000000000000000000000000000FF429A000001801801800400000001800001800000000000000600e04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (500000000000\n\t000000000000000000000000000000000000FFCE780000018018018000000040018000018000000001001006007006000000\n\t000000000008006000004080000208000000000000100000000200000000000000000000000000000000000000FF3BB70002\n\t00A01000000000000001C0000000000000010010060060060000000004000100000060541004004108000000081000802000\n\t00000004000800000000000000000000000000000000FF9C8800000180120980000020000180000000000000000000060062\n\tA6000000000000000000806000006000000800000000080020000000000000000A00800000000000000000000000000000FF00104040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00000000004000004000000000000000000000000000000000000000000000000000000000000000000000FF49C700000080\n\t1800000000002001800001000000000000000680600600000000004000010000000000600000000000010000010000000000\n\t0000000000000000000000000000000000000000FF141B000001C01801800000000001800001800000000000180600600600\n\t0000000000000000000000000400400000000000100000000000000000000000000000000000000000000000000000FF655F\n\t000000801A00000000000001800001800000000000000600600600000000040001000080602810400001000000001000010000904040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001001801\n\t8000840000018000C08000000000000886006006000000000000000000004000140000000000000000000000000000000000\n\t000000000000000000000000000000000000FFFA00000200201A000000840002518002D0000000000040008740E226000000\n\t0000000000008C4800848000000000000000000000000000000800000000000000000000000000000000000000FFAB3B0002\n\t41201809800040408001D4040400000000000002261060860000000000000000000040002040000000000000000000000000\n\t00000000000001020000000000000000000000000000FF48120002000018000000000000018000000000000000000006807800504040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000008000000\n\t00410000000000000000000000000000FFE1E100000180500080000000800080000180000000000010020031020000000000\n\t00000000182000612000000000000000000000000000000000000000000000000000000000000000000000FF836900000184\n\t0001800020000020200401000000000000000048020000000000000000000000000200400000000000000000000000000000\n\t0002000000020000000000000000000000000000FF701B0000019000018000100000001E040000000000000000002088A000\n\t0000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000FF2DF400d04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000828800000000000000000000000000000000000800000000000000000000000000000000000000FFD171000001085801\n\t80000A0000118A00210000000000000806206106000000000000000000046000026000000000000000000000000000000000\n\t000000008000000000000000000000000000FFA4A4000400C40C02800200000402A10080800000000000000300280A000000\n\t00000000000130300148A000000000000000000000000000001000000000200000000000000000000000000000FFA6C50002\n\t2020020C00040200001C01012A0000000000201220801010000000000000000000C40800028000000000000000000000000000304040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004004000000\n\t0000040020000400000000000000010000000000000000000000000010010000000000000000000000000000000010000000\n\t01000000000000000000000000000000FF91100000AA0880AA0000800000000880000000000000800AA82282A80000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF71CD00020020\n\t4A008002502002008400908000000000000002902802000000000000000000B0280080200000000000000000000000000000\n\t0800000000800000000000000000000000000000FFBDC700020122120000000400000000422500000000000000048040040000b04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF10A8000000002000000010000000400010000000000080000001100000000000000000\n\t0000340000000000000000000000000000000000000000000000000000000000000000000000000000FFE7F90000AA0AA12A\n\t0000AA0000000AA08800000000000012A82A82A8000000000000000000148000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFA33A0003543303540003242002001541440000000000001550CC0550000000\n\t000000000000810800800000000000000000000000000000000800000000800000000000000000000000000000FFBC69000400704040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000280\n\t006000006000000000000000020200000280000000200020006000000000000000000000000000FFD9AD0002002013000000\n\t0500020000524200000000000040048008040000000000000000000288008000000000000000000000000000000008000000\n\t01000000000000000000000000000000FF344500000080080080002080080080080000000000000028020020020000000000\n\t00000000302000002000000000000000000000000000000000000000002000000000000000000000000000FFDE730000AA0A\n\tA02A0000880000008A84C800000000000002A82A92A80000000000000000004000000000000000000000000000000000000000f04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000080000100\n\t0C00901000000000000000220200200200002000000000000000200000201001000000000000000000000000000000000000\n\t2000000000000000000000000000FFBF2F000420401000000400000000400400000000000100100900100000000000000000\n\t0000000000000000000000000000000000000200000000000001000000000000000000000000000000FF6843000400C00800\n\t800400800800C00C000000000001003203003002000020000000000000002800002000000000000000000000000000000800\n\t000001002000000000000000000000000000FFA61E004041801801802001801801801800000000000000601600600600000000084040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000004008\n\t000000000000000000000000FF0EF6000001801800800000801001801800000000000000600600C086000000000000000000\n\t005000008010010000000000000000008000001000000000004010000000000000000000000000FFD9390000018000018000\n\t0000800000000200800000000400000401401100081000200000000000C02100000800000000000000001000000800000000\n\t00000000000000000000000000000000FF993000200180000180200000000000000000000000000000000040000000000000\n\t00000300000000000000000000000000020400000100000000200020000000000000000000000000000000FFC5BB0000009000884040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001048\n\t00000000000000000000000000000000000800000000006000000000000000000000000000FF778700000000590000000080\n\t1951801000000000000000600600600600000000000000000003400032000000000000000000000000000000000000000000\n\t4000000000000000000000000000FF8393000001901801800000809C01901002008000000000600604200600002820002008\n\t0000004800200040080000000000000000000000080800000000004000000000000000000000000000FF5D4A000000001801\n\t000000801001807800000000000004600600E0461100203000000800000051400001A000000000000000000010800000100000484040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000801CA1\n\t80181200000000000062AE2AA2AE00000000000000000034E000046000000000000000000000000000000000000000006000\n\t000000000000000000000000FF336F00000040188000000080184D8018100000000000006006006006000000000000000000\n\t03600024E000000000000000000000000000000000000000006000000000000000000000000000FFF5E60000ABAA982A8000\n\t00801815A0100000000000000062AE2AC2AE0000000000000000002040004180000000000000000000000000000000000000\n\t00006000000000000000000000000000FF3A170000000018010004008018038015540000000000006006006006000000000000c84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060000000\n\t00000000000000000000FF8DEE00002A0AB02A000601801809801C0000000000000062AE2AE2AE0000000000000000002050\n\t04308000000000000000000000000000001004000000006000000000000000000000000000FF336600040182500180040100\n\t1801C01340000000000000600600600600000000000000000000680008600000000000000000000000000000080000000000\n\t6000000000000000000000000000FF327B000154155054000001001901C010C4000000000000655655655600000000000000\n\t0000506004006000000000000000000000000000000004000000006000000000000000000000000000FF57CF0000ABC898AB00284040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000015600400\n\t6000000000000000000000000000000004000000006000000000000000000000000000FF75C5000081801801800000045901\n\t80100000000000000060062860060000000000000000000060000D6000000000000000000000000000000000000000086000\n\t000000000000000000000000FF80F1000000001900000000001B218014000000000000006006006006000000000000000000\n\t10E804126000000000000000000000000000000804000000006000000000000000000000000000FF7E2C000301A010018000\n\t01001805A019340000000000006006006006000000000000000000024000000000000000000000000000000000000000000000a84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (121041019540\n\t0000000000005505564865560000000000000000004500045460000000000000000000000000000000040000005460000000\n\t00000000000000000000FF6F7C00000180180100000400000180000000000000000000061060060000000000000000000000\n\t00006000000000000000000000000000000000000000006000000000000000000000000000FF4AE200002B88982B80000288\n\t180388180000000000002AE2AE0262AE00000000000000000020600020600000000000000000000000000000000000000022\n\tE000000000000000000000000000FFC25A00000004590000014880982984D800000000000000600600E0060000000000000000684040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000000000\n\t0000000000000000FF49A30001AB8AB92B00008A0AA0578AA00080000000002A82AE0762AE0000000000000000002A800024\n\t00000000000000000000000000000000000000002AE000000000000000000000000000FFEE7F0000800019000000A002802B\n\t800000800000000000000602E00600000000000000000008000401600000000000000000000000000000000400000000E000\n\t000000000000000000000000FF9F3600002B8AB82B0000A80AA0818AA00080000000002A82AE2062AE000000000000000000\n\t2A800028E0000000000000000000000000000000000000002AE000000000000000000000000000FF904E000054133854000000e84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000006000\n\t000000000000000000000000000000200000006000000000000000000000000000FF9F0D0000020018010000000000018000\n\t0000000000000001070078060000000000000000000000040060000000000000000000000002000000040000000060000000\n\t00000000000000000000FF306700000180180100004000010180000000000000000000062860060000000000000000010000\n\t00136000000000000000000000000000000000000000006000000000000000000000000000FFD1EF00000000188100000000\n\t0029800000800000000000080600E0060000000000000000000000040000000000000000000000000000000000040000000000184040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000180020B00\n\t0000000000100700680600000000000000000000000000010020000000000000005040000000000000010000600000040000\n\t0000000000000000FF66EA00002580080100000000000180000100000000000A000600600600000000000000000000000000\n\t0000000000000000000000000000000000000000006000000000000000000000000000FFA68C000040000801000000000001\n\t8404018000000000141406026006000000000000000000000001806000000000000000000000000000000000200000006000\n\t000000000000000000000000FF8B7F000001800001000000000001800001800000000000108602700600000000000000000000984040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200000000\n\t000000000000FF0D6C0000000018010000000000018000018000000000000006086006200000208000000080000000200000\n\t000000000000000010080080000008000000006000000000000000000000000000FFC4D90000018818010000000080018000\n\t0500000000000000060060062000000080000000000000003880400000000000000000000000000000000000000060000000\n\t00000000000000000000FF948D00000000180100000000000184000100000000000004060860060000002000000080800000\n\t00000020000000000000000000080480000008000000006000000000000000000000000000FFC16B0000000008010000000000584040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002020000000\n\t000000000000000000000000000000002AA000000000000000000000000000FF87A000008191400100000000002800004800\n\t000000000000010060000000000000000000000000000A000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF7261000001800001800000000080000004000000000000000000000000000000000000000000000000\n\t8000000000000000000000000000000000000000000000000000000000000000000000FFF646000001901801000000008001\n\t800009800000000000000700600600000000000000800000000000810020000000000000004040000000000000008000600000d84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800155000000\n\t0000001557556556000000000000000000000000446000000000000000000000000000000000000001556000000000000000\n\t000000000000FF0D3400002A8888AA8000000000808000AA80000000000002AA2AA2AA00000000000000000000000020A000\n\t0000000000000000000000000000000000002AA000000000000000000000000000FFB59400000000100000000000002A0000\n\t0000000000010010008010000000000000000000000000000880000000000000000000000000000000000000000000000000\n\t00000000000000000000FF0BF200012A8248AA80000000005680008100000000000002AA2AA2AA000000000000000000000000384040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FFC43000010000400000000000002800000200000000000008000000000000000000000000000000021400000000\n\t00000000000000000000000002000000800000000000000000000000000000FFE00600002A88882A8000000000028000A880\n\t000000000002AA2AB2AA00000000000000000000000020A0000000000000000000000000000000000000002AA00000000000\n\t0000000000000000FFA547000000041000000000000000000001000000000100100500100400000000000000000000000014\n\t0000000000000000000000000000000000000000004000000000000000000000000000FF67700000D595315580000000010100b84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (280200200200\n\t0002000002002002002000002003003002002000000000000000000000FFEA5D000000200200000000200000000000000000\n\t0000000000000000000000000000000800000002800000000000000000000000000000000002000000800000000000000000\n\t000000000000FFD6150004000002000002000000000000001000040000000000000000000800000000000801000000000000\n\t000000000000000800800400000100000000000000000000000000000000000000FFBFB20000000200800000000001000000\n\t000000000000000000801000000000000000000000000000000000000000000000000000000000000000000000000000000000784040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008188048000\n\t0020030020028020020000000010020020000030020020020000020000030020020020010020020020020020000000000000\n\t00000000FFE913000001801001801A0180180180180180180180000060060060060060460000000000064060008070060060\n\t06000006000007006006006000006006007006006000000000000000000000FF456C0086002010010010012000010A900000\n\t100000000018018000040010000000000000000000A000000180000400000400100400400400402800400400400400400000\n\t0000000000000000FFFB1900000080080080080080080080080080080080000020020020028020220000000000022020008000f84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF92AC000201800000000000001000000000000001000000000400000000000000000000000400000000000000000000\n\t0000000000800800000000800000800000000000000000000000000000FF3733000000801800001001000800801A00880800\n\t8000002002802002002002000000000802802000802802002002000002000806002202002100002002002002002000000000\n\t000000000000FFE9F70080000000010004006000014000000000000000000000000000000000000000000000000140000000\n\t000000000000000800004800000030000000800004000000000000000000000000FFC110000000800800800A00800860D50C00044040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800006000006\n\t000806806806006400006006006006006000000000000000000000FF06F3000000001D010014028018018018318018018000\n\t0060070040068028040000000000008044A28408040000060000060000060060060060020060060060060060000000000000\n\t00000000FF73DD000001881801001000800809801801801801800000602E0000060000000000000000040440000000840000\n\t06000006000006006006006000006006006006006000000000000000000000FF40E300000180000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000844040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (181180000160\n\t0640700685600020000000812E80622180080480200E00000600020E00604600630020600E04640600600000000000000000\n\t0000FF7D67000000001801201200800C01801C01801801800000600600600600600200000000000484632004000400200600\n\t0006000006006006006200006006006006006000000000000000000000FFDA6E000400081881001100811C09801845801805\n\t800020643E814046002006000000000000004100100084000006000106000806906C16106000016006006016006000000000\n\t000000000000FFD105000001801801001002A61801A01A29801801000040600600400600000200000000080400400000000400444040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF8C9800010008080100110104000190180D8018098000A2400622600E04C0044800000000CC1040040060AE80C106008106\n\t00000780E00690640401605622FC0600E000000000000000000000FF45E9000001881801401400C318018E1C008018058001\n\t2361E60B600E00600208000018000009C50081E0AE80C09600800603818610E00700610006662620E00600E0000000000000\n\t00000000FFEB0A000000001801005040C00841815840801800800000640E0820460040020000000110048040401060060040\n\t06000006040416006236006000206006006016006000000000000000000000FFD7E0000101C01801005240A01821815C118000c44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000060000\n\t07006006006224026006406006006000000000000000000000FFD86500010180090500120180184180580100180100000042\n\t4680601600400400000000000680600400008400200600000600000600600600602402600600600780600000000000000000\n\t0000FF975D00041000080340100101981B809881801801800000402600600E00400080000000000444600400000400200600\n\t0006000806006006006004006006406806006000000000000000000000FF8EC7000401A00C11001001800003C09901801801\n\t800000400600A80600500400000000180000400000600600400600000600000600600600620000600600600600600000000000244040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000680600\n\t000601818000000000018600600018E2A6006006000006000016196007106000006006006006006000000000000000000000\n\tFFB94E000000001811801800200403C21801801801800108640608480E02182200000000000C42600400680E806226000006\n\t00108702608600600420E00E007086006000000000000000000000FF51CD000001E01C11C558244140498058058018158000\n\t00680640400600240500000012000600E00C00600602600610000651001600E006106004126487A860060060000000000000\n\t00000000FFD94C000090001C81C01C00400221C058018018018001006007014006003006000000000005026004006106006000a44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF70\n\tD2000001801800C01001C0140180180000000080000060060060060070060040000000020068040070070040000000060000\n\t06000006006004804006006004000000000000000000000000FFB760000000401800845140801001C1182400000580000060\n\t0608601602604600600014000200C00400E00E00640010000600088600400600600400E10E40608400000000000000000000\n\t0000FF3FB8000401A01010811604814A15A01000000011800010600620700600620600400000001204680A0064C604604000\n\t0006308806044107006002D26206086004000000000000000000000000FFCFD20000018010018018808000419CD82180180000644040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100624000620\n\t4007006000806006006004000000000000000000000000FF417B000000401C01001400801001801000000001800000600610\n\t6006004146000000100000404006000001500028400016408006516806006006006006006006000000000000000000000000\n\tFF7EA40000018018010010008018018018000000018000006006006046004006000000000010006404000000006000000006\n\t000006004006006004006006006004000000000000000000000000FF75BB0000000018008010018000018018000000018000\n\t006006006006006006006000000002004004006006004000000006000006000006006004004006006004000000000000000000e44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (806006006006\n\t005006802000081006804000006006406000001806000006000004806000004806006004000000000000000000000000FF81\n\t0A000001C01A00001000201401001800000001800000600600600600400600200008100E00020080E80658002820000E0280\n\t0608D004006000006046006004000000000000000000000000FFFCE2000000001801201200C0040080180000000180010060\n\t0600600680400600000010000600400600E02684400080000600000600600600600680700E00600600000000000000000000\n\t0000FFECDF000001801801401001800800C0180000000500000060060060268040268000000008072000000160062040008000144040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFCD7600\n\t0200001800401800801001E01800000001800000600600780600600400600000000400000000000000000000000600080600\n\t4004006000006007806004000000000000000000000000FF1C3A000200001C00001400201001801800000004800000600610\n\t6006005106002000000800004000808020084000000006001006002004806000004006006006000000000000000000000000\n\tFF92C0000001801800401C008010018010000000018000006006006006004006000001800000006000000800044000000006\n\t00000600600500600000602E006006000000000000000000000000FF37F4000000001800001800001001201800000001800000944040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000818010011\n\t800000040080480040100000000000000000000000FF3E400000018819820010400150000710840000010000A2604680E006\n\t00E5040040000000C400C0000483900040000000060000060060061060000A6406106006000000000000000000000000FF68\n\t51000200201A92551A408A5211225810000223800020680611602E896A14824000000894A489408B0900914000000C060004\n\t4EB2E806206C30CA7107006806000000000000000000000000FF1D98000041911C0000510441114280190400000180000360\n\t0E00620642612628600000000408400040024040000000090E0000060062141260000164265362264800000000000000000000544040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08881228C00A\n\t48020000000800890880800800888C00000280001020101208220A48C08820041100480000000000000000000000FFD4D200\n\t000180085900820114101280084000012280000024120130023020024020000004132020202A24620020000010020013064A\n\t2002002000002002002022000000000000000000000000FF8CD90000018014004C0080000080404000000015800000000610\n\t00100D00840000000000081040000000006040000008480000012080008C0020200201228211200000000000000000000000\n\tFF798A00000180840001001660802400000A000000000100800040080002003038000000000002000050000004000000000000d44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFD2F2000281\n\t3002412412212150000002402002020000894800814004908AA00000000008088B4900920800809000000004000004800800\n\t004801000004004000800000000000000000000000FF751F00000100183180B8AB12B811A0B842000015800001641600E006\n\t04E21620600000022E08400042630E206000000006000006106006006000406806C06006400000000000000000000000FF7D\n\tFF000400C00880CC0800800E44C40800000520800000304330280B50312310200000100200B0010830230222000008220008\n\t8B2130129430210234030C3952080000000000000000000000FF0E000002202000001273202A24480022002002400000810800344040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (505515505508\n\t80550D50D50550550000000000000000000000FF841000040044240040044464460020000240040000000010010018010092\n\t11000000001140001001111001088000000000001800000800001001801000000801000000000000000000000000FFA95500\n\t002A00008808A0080A00AA0AA0000AA0880000A202A83202A80604080000000000202000003082003002A80002A80002A82A\n\t82A82A80022A82A82A82A82A8000000000000000000000FF36CE000200234A04A00A82800800800B0C000220800000280288\n\t2002C02802802000000D028028028029528C200000000200000280200280288000300280200200000000000000000000000000b44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0AA822000000\n\t00000006312A84002402A82002A80002A80002A92A8AA92A80022A82A92A8AA82A8000000000000000000000FF67FD000080\n\t0304004004000080002004800000D00001010000000000410808000000000408100002008080000000000000000001000001\n\t000002800000000800000000000000000000000000FF873F00002A0880AA0AA0880800AA2AA0A80AA05200012A82A82202A8\n\t2A00A00000000000002A80002002A82202A8000AA80002A82A92A82A82002A82A82A8AA82A8000000000000000000000FFE9\n\t5300025430215415214A52255415402A1542040000540D50C50D509001208000000008A0C50900C40C50C50550000550001500744040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (880000018018\n\t0190181100180180100100000180000060064060560060060060000000060060000064460060200000000000061060060060\n\t00006006106006000000000000000000000000FF16380002012252014012013152010010412002820000004800920004888A\n\t94800000000808800800820800800000000800000804804004804C03005004000005000000000000000000000000FF3D4000\n\t0000800800800842800800800812800020800000200240A0020020420020000001020022001120020CA00000000000000200\n\t2002002000002002802002000000000000000000000000FF5F050001AA0880AA0AA0880300AA2AA0800AA1080000AA82A81100f44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001000000024\n\t0040000040000000000000000000000000FFEAC7000002000021010030010001801805800000808000210A00232200200204\n\t2000040092002000002232002000080000000002106012002000102182082002000000000000000000000000FFAFBF000401\n\t4014404014074014004004004000000001000001001508001200000000000041001000000000001100001000001005001011\n\t001001001001001005000000000000000000000000FF53FA000402400C00C14C40C10C04C00C00C00000808100200B003002\n\t0534020020004001030030000020020030001010000010030030030030014430C3003043000000000000000000000000FF70000c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006046000\n\t0400001802B20100A000C00002000000000600600610648200620E086006000000000000000000000000FFF89E0000008118\n\t0102100080000B91500080000181000261040000060020060860080000000205400000D001400002000000000E1060460061\n\t00106206026006010000000000000000000000FF46890000018100000400020000B40B402000010000800000200400000000\n\t00108010000000450010410200300000000000000010200020100400000000240000010000000000000000000000FF4AE900\n\t0001800000094010010004000000000001800000000620010005400000400040002000000000000000014000000000000008008c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000105180548\n\t10C2840401840800800021800000600400600608E41600E00000010030E8000000262A4000000000000006C1608600690005\n\t6006006486000000000000000000000000FF14B700010010384102D01081003188C800800093800000600400600600604630\n\t6000000008000100028010014000000000000006126016006000306006004046000000000000000000000000FF5CD6000001\n\t801801011004800141840844800001800011602402600600600601600000000820800220040028400000000000000640600E\n\t006000006116306006000000000000000000000000FF260900000100180100101081000180100080016180006AE004004106004c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (556404556556\n\t556556000000000000000000000000FF4CA900002B8418A90A3084848889ACDA008000CB80002AE2AC2AE2AE22620E086000\n\t00021614000020E20000E0000002A80002AEA2E2462AE0802A62AE2AD426000000000000000000000000FF8118000000001A\n\t010010128A4891A0180080004180000060040060060020060060000000261400000160002A60000000000008061160060060\n\t00006006005806000000000000000000000000FF7EDA00032AB01889011250A820C780000080000180002AE2AC2AA2AE3361\n\tC60260000003200260003803865440000002A80002AE0063362AE0000162AE2AE00E000000000000000000000000FF70920000cc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (061060000000\n\t1030E4001101462A4000000000000006086006006000006006004006000000000000000000000000FFFD2E00042A0AB0894A\n\tBC29C01C05AAA80080000180002AE2AE2AA2AE2AE2AE2260000003204270062002060040000002A8000AAE0062AE2AF0062A\n\tE2AE2AEAAE000000000000000000000000FFB327000201C15205201A00B05201800000800001800000600600600600200645\n\t6000000046210900046028006000000000001006106006006800006006004096000000000000000000000000FF0D42000154\n\t555535155920809041B5480000011580005565565565565525565560000004160084045464D0016000000550001556C46556002c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (041801801000\n\t050001911802800001800000600611600600200600600000002600600400E02600E000000000000006006006006004006006\n\t414006000000000000000000000000FFE3100000018058458450430028018230A88000018000006016026006006006006000\n\t0000860AE000006096106000000000000006006006006000006006144006000000000000000000000000FF345F0000000018\n\t03C01001040C43801A00800093800000600600600600600601600000010600680404600E016000000000000006C2E006006A\n\t04006006004006000000000000000000000000FF3228000301A01241001B05A938898008008000218000006006006006006000ac4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (042AE2AE2AE2\n\tAE006000000000000000000000FF658600005413195195415592015590A93000155580005575444425565565505560000005\n\t064120044044064A6000000006000554556556556004556556516556006000000000000000000000FF03A700000100180080\n\t0011804001004954001001800000600605000641400000200000001600600000601600600000000600000400600600600000\n\t6006006006006000000000000000000000FFCB6400002B88D88D8890880840AB8418018000AB80002AE2A63022AE2AA2AE2A\n\tE00000020E3060002A62462260000000000002AE2AE2AE2AE0002AE2AE0042AE000000000000000000000000FFEF18000100006c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000081610\n\t2004044010006000000006001005006006806004007007006006806000000000000000000000FF4E5600012B0AB0AB8AA081\n\t8890AB0C0000001CAB80002AF2AE4002AE2422AE2AE0000002663580042002002AE0000000060002AC2AE2AE2AE0042AE2AE\n\t2AE2AE006000000000000000000000FFC8F4000080001801800001808001800804001001800000600C00E006006002006000\n\t0000360220060AC08E00E000000006000004006006006006006006046006006000000000000000000000FF8CB100002B0AB8\n\tAB8AA0A38A88AB0888000010AB80002AE2AE0862AE0842AA2AE0000002862060042AE3262AE0000000060002AC2AE2AE2AE000ec4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01800000A202\n\t05A01000201C0180004068A61850C64040040060100810022064000060060088000609060011FD0068074060008070470170\n\t07006000000000000000000000FFC7CF00000540104180000104880100000000140180000061450029161030020060000800\n\t01002004004006000800001006000006086026006004007007006806006000000000000000000000FF8E3F00000100100180\n\t002B242A0121004400180180000068060200061400020020000001020460001160C600000000080600000600680600600100\n\t6006006006006000000000000000000000FFF3EB000081001001800001801001044088201201800000600430A00600A00400001c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (606601600600\n\t6000000000000000000000FFCDFC000001411801908880800005841020001201808000600401700601400000620000010600\n\t202800C00028E08000100600081600600600600810700E406026106000000000000000000000FF9C6302004100184180A800\n\t8108010410000010018001406007006006085044006000000006800000000000006000000006008004006007406000006006\n\t806006006000000000000000000000FFB4470400410018018140448000018210000018418001007804001006004020002000\n\t000000202000004007808000000006011006006007006000006006006006006000000000000000000000FF675A0000030018009c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020100002010\n\t00440002000000000600001600600600600000600E206026006000000000000000000000FFBF920000010018018010018018\n\t15005800001E0180000060041440062A42060A64000000021001401500001000000200060000060860264860200260460060\n\t06006000000000000000000000FF961A000001011801911901801009851808001801800028E8040A00060062040860000000\n\t00002080024198430100000006000006006026286030106006006006106000000000000000000000FF06B800000100180180\n\t184580100580B80000184180000060060040566A600602603002000208040008020000000002010600000418604600600002005c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (50828809008E\n\t80001F48AA80002AA0120022AA0024232AA0000006526221002423922020000002AA0007022AE2AA2AA1002AA2AA2AA2AE2A\n\tA000000000000000000000FF390100000100000100C030049102004000002201800000004628000011001000600000003000\n\t4002084008148000000000000090000000000002000000000000000000000000000000000000FFCDB1000001824000020000\n\t0020500000000100000000001A88050000240500000000000080090080048040000000000000000020000000000100000000\n\t000000000000000000000000000000FFAC62000001001801801001801001001828001201810031700401000601400100204000dc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (005004004000\n\t000000000000000000FFA54A0000D5955C01951153D41955955000155D55800155655600E5564CE11648E000000446124201\n\t016516526000001556000D56557557556400557D56557D57556000000000000000000000FFB8C00000AA8888AA8A88809228\n\t2C8888000008AA80002AA8820022AA2AA08A2AA00000008208200050A22222A0000002AA00004AAAB2AA2AA0002AA2AA2AA2\n\tAA2AA000000000000000000000FF7AF30000000000AC00200000A20000100000020000010000000810010012208200000000\n\t90200000520020008000000000000000000001000000800000000000000000000000000000000000FFC66C0000AA8890AA88003c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200900008480\n\tD0100000000800000000801000000400000800001001000000000000000000000000FFFDB300000000000000404002400000\n\t2000000000000080000022000000820040000000000900020008000000800000000000000000000080000080000000000000\n\t0000000000000000000000FFAD4080002A8AA8028888888888AA8A88000AA8AA80002ABAAA4C3AAA22200300200000028323\n\t20002022022220000002AA0002AB2AA2AA2AA0012AA2ABAAA2AA2AA000000000000000000000FF2B29000000023000001054\n\t0102000050000004000001004C4035100500084080000000000004C00000000008000000000400100080480500400100500400bc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800800800C00\n\t8008008000003402022002002002002000002002802000002902002002022002002802002002002000102002002002002000\n\t000000000000000000FFDA2D0000000006000000000000000002000000000000000800800000000000000000000000800002\n\t000800000000000000000800000000000002000800000000000000000000000000000000FFD2220100001000000000004000\n\t0020000400400000000100000000000100000000000100000000504000004400400404000010010000400000500008000000\n\t00040000000000000000000000FF1F8E00010000054802000220000000000000020000000000000100000800B09300000000007c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFA785010000000800A00E18A0080281080480480080000120020620020120020020006328626020004020\n\t020020020030022FA00200A243002000002002042002042000000000000000000000FFA942000040001A01A01801801801A0\n\t1A01801801800000640604600600600600600000600680600180690680680604600600400600600600600010600400600600\n\t6000000000000000000000FF4833000000001000000000200001408000000000000000000480180400000000000000080000\n\t0000800000004004004005804000004000004000004004020004004000000000000000000000FFD767000020000800A00A0000fc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF1B24000000000001000001200000000000\n\t0010010000005000004000004000000000000004800800001001001000001000000000000001000800001000004000000000\n\t000000000000000000FFEB8A000000001000800A00800800C00C008008008000002002002002002002002000002002002028\n\t80200222202202220208280280A002002028002002002002002000000000000000000000FF3F7C0000001004004000000000\n\t050000000000000000000800000000000000000000040000000802000000000000000000200000000400004802000800000000024040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01A05A018012\n\t01800000600600600680680400400000680410000080080001E0060060060020A288680E0062008060020060060060000000\n\t00000000000000FF05E8000100001800001C40840009809801811001800000700E9060060064560040008000010440800C40\n\t5000600602600600288A106016006208006022006806006000000000000000000000FF370200000000180002180180200180\n\t1001821001800002E00600408604600000000000600400000000C00010600600640600202600600600610020600204600620\n\t6000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000824040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000000000\n\t0000000000FF4A71004000041800243015841C01941145802000800008080E00E006006004006000808806D0402011690100\n\t600680604714002400600602600900E042A27006006000000000000000000000FF6574000000105800001021821811E15801\n\t85000000000000161040060062440020000060040C010114680808600604640600200F006002006011007022047006006000\n\t000000000000000000FFF60C0000803119B4401A49819801815811801241800002E10600608613600E104000140000004000\n\t048420016007046006010000116014006080207113114006306000000000000000000000FFBC96000000505940021811A13800424040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008006106006\n\t006006803006007204006000806000004806006000000000000000000000FF7A9C0000004010002010158008018818038048\n\t03800040080E004006020006002000006014896004810006086806006A06003C0E0068868060040069400060461260000000\n\t00000000000000FF0D70018000001800400041841181C05811181043808020006601600602600400400015620900E200844D\n\t0708718E00F25E60438C1070B5186800187002004026026000000000000000000000FFB62000200055191402440181100182\n\t994100100180801000860040061160059000000064042064400840020160160560060B60260160400470080160125540060000c24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1C0180280180\n\t0000001600D20608082600200100682509640420280631720600600600510408630100600400702400400710600000000000\n\t0000000000FFC98D000100001600001001801841E01A01801801800020000680680600004600400080010680400440281004\n\tE006087806000884006084026044006826004006806000000000000000000000FFBABC000000029000001221880901801001\n\t80584180002000062164060102040860010070C500040400A004406406006006000004106006006024006007806006106000\n\t000000000000000000FF29E0000000051000081241D09A01801C01800801800000081740400710140610000000600009600000224040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF687C0000001818018A100320180190D001801820800000021600500600080400000000680604E200866006006006\n\t00610610500440608400E00000E006004006006000000000000000000000FF451D000000021801801001003B418A38018018\n\t48800000000600400601080480208000E0240260040060162C72A61060060040042A600504600408608400408E0060000000\n\t00000000000000FF41130000040038528094312018918018018048050000000016804087800007A13800006006006024A120\n\tC784600611610E554554016000446005A46007005806006000000000000000000000FFC37D0000800018009010010118018000a24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060060060\n\t06006004006006006004006004006002006000000000000000000000FF952400000000000000080100180000180080180180\n\t0000000600600600080600600080000600000400600600600600680700600600600600600400680400600200600000000000\n\t0000000000FF60E8000000002854130053805B01829800001801800000080600600600000480408000480680C0064140060C\n\t6486016006056D040060860560060C6004806112006000000000000000000000FF962D000004040800600001801810001E00\n\t00582D8000000C0600510600000041400000C0420044200060C640602608680EA0605614E00640600040E90400600200600000624040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001A03000000\n\t0286024006000026806200000000064804000802006007006006086810006006806004006022006002806000000000000000\n\t000000FF4D54000000001201811C01C01801001900801844804000150604600600001000450008600200604C804535100116\n\t00604E006143016806006005006804006006006000000000000000000004FF7FDA0000000010018018018018010018008018\n\t0080000000060042860000420060100004820040040060044002060061060860024060060060040060240060020060000000\n\t00000000000000FFE1800000000000000000010018018018008018018000000006006006000006006000004006000004004000e24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF9615000000200001400001A01800C0180180180180000000060040060070041040204400041000008841320460068060\n\t06146516046806006000007802006003006000000000000000000000FFB79800000000000100081180180080180180180180\n\t000110060040860160000040084842848000280002AA20608E00702E1465B720E01600600000600000600200600000000000\n\t0000000000FF3A26000000400801E00281801801401800001A018000000006046006000026506040046000106804504B5284\n\t6026107006006800026006806004886002006206806000000000000000000000FFFF0C000000000801801819801800001A8000124040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020612600600\n\tEC4A30E0060060220262420A6346236000000000000000000000FF7BCF000000401001001801801801801801001801800000\n\t0806004006006002006000000004004000000000000006007806806002006006006000006000006002006000000000000000\n\t000000FF659B000000001001410889801800C01801001841804000900600640600E834004100003006002000004A04100426\n\t00610680601200600E006000007002806206006000000000000000000000FFD1A1000000401001000C01C018000018010018\n\t018000000006046006006001C04000003006802000407004000006106006007002006006006000086001006006806000000000924040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100000100000\n\t2A0010020000000000008C00000010000100000888880881000028111A00000001410108A800000000000000000000000000\n\t00FFE5ED100000010001120811901820081955881800000000040640488600600072000000214C2460000040500002260060\n\t0600E042006006006000A462E2106024046000000000000000000000FF25690000004084A9201A01891AA0341885A91AA080\n\t00C010C6C4409684692A82600090229530C8309008008880AE00608EC468828264B723680030689240E81710600000000000\n\t0000000000FF5CE7000000003405054AA1A41805C15C4100180180000280060842460062014040002100440460022143204000524040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tA9870000002432A024420022008224A2203002C00000818820841208900A00810000A00A10D80808B00A00400500010C40B0\n\t0810080C094388200A0800808500708000000000000000000000FFC1BD000000100901C19000A01900800C0101C824800006\n\t204200300200251A00200110208002A00245A4221C280282301240268280205220600200201282205A082000000000000000\n\t000000FFDE1704000000800800000409C20000008004180180006060801140204060E0000000480020010020084081219040\n\t840008020000A281A0000001000400441281020000000000000000000000FF65E90000000000160021E0200050124202000000d24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002802C0B08A\n\t802C02002800802C0AC12802802000000000000000000000FF76060000002432012452002110003082032042820000801004\n\t8200048108C880000080CC34804902848800800004005004904C248048140049020049248C40008040000000000000000000\n\t00FFF9F60400000B108B0951038818A190188B15580180000460264868064060D649600000402E04C00202E0360060260060\n\t0610644C1060AE0060028364CC286946126000000000000000000000FF860F100000400C00820C50812E10C42820C00C4C80\n\t0128B20303200B083403002000503483503009303283332A8282A23240300200A203A0B00020300202320B4020000000000000324040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00C40D508315\n\t50D40900A10000840CB0C00900D50C20550551551550B00C40D50A90550900D50C40908D50D50000000000000000000000FF\n\tAD5D00080040040844054A420000000000400400000100100100080100108044800000114110900100150100100080000100\n\t1501001010801001000101000001000000000000000000000000FFAF4300080028808A0880880A20AA0000A00A8008000022\n\t82A80802A82A00002200000800002A0000200200AA82A82A82A80300002A80A02A80002A80000402A82A8000000000000000\n\t000000FFC147000000000C40C00A44A00A00A42A10A00A208000903002C12002802A0289200124290280A8008828AA00280200b24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF48F8\n\t0000000AA0800800000282AA4AA8AA0D00C000003382A82A82A82B00102A00001800000200002000002A82A8AA8AA8208000\n\tAA8221AA86002A82102A92A82A8000000000000000000000FF735A0008000000020000000240004000080020300000088000\n\t4800000082280A00005080000A80000001110010000000000200880000410000000000884000000000000000000000000000\n\t00FF4DDF0000000AA0A20920001122AA0AA2AA08208A00002202A82A92A82A02401000004282084402003300282A82A92A8A\n\tA82B00302A84C02A80002A92202A82A82A8000000000000000000000FFEEB40000003543503543523103541343223503040000724040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (031530030030\n\t03002801003143413043002000000000000000000000FFA230000000001821003005801801801003801901800001620E0860\n\t5620601600620004401600600200E20600600604600620610609602600620254600C086006006000000000000000000000FF\n\t114D0000002012052032522020002002002222120000800804800004810910010000015430810A0088081080480400400482\n\t0844000888004800800044800001000000000000000000000000FF0367000000000848830880880800801800808820800010\n\t200200280200244200200024210230200005234200200200200210251200200200200000291200280200200000000000000000f24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (630830404020\n\t6210000400440000000008008240220000020000008100080040000400480110080040000000000000000000000000FFD9C6\n\t000000041844000800800800C060028008048000042112002002002002002080002102102000002402012002012002282000\n\t01A102006000022462002002002000000000000000000000FF319F4008004004214010004004000004000000000000001100\n\t0010080000200000010010090000100000014410010090010210010010010000010016012090010000000000000000000000\n\t00FF97F2400000400C00C00800C00C00804C0080080080000030024030020024220020814030030028000020430030030130000a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFA5710008\n\t800018008008418090009E580180100980404862260C401E00E0002045A800C00C1044406100380862461860260066600060\n\t0018E418046082224016382000000000000000000000FFD0E600008004184480000180001401180180102182000463160040\n\t0600600000C00000600000D10800002001620600602600600202E002007040406002406006006000000000000000000000FF\n\tDB3300080000000002004000002A01009000004004404080000400000400000104000000000304D001008040004040000020\n\t00002C0028000420220000088210000200000000000000000000FFB05F000000000000003005000000000000001901800001008a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C5162AE2AEAA\n\tE0002AE1922AC0042AC000000000000000000000FFEC48000000001840AC0011801A41801854800121800000400641400600\n\t60460860000060C4402800444036086006006006004206002006006800002402004086006000000000000000000000FFA2C7\n\t0000000358048088438010958CD80180100B800000200614400601640E44E00034C0140B600009010000E006006006004128\n\t00400200600000404A00642C000000000000000000000000FFE2FA00000000180082000181102140190980100B800008E046\n\t08400603600640602800E08804600000028050600620E0062040003060AA01600000632214E2064024000000000000000000004a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (552556540436\n\t4C600000A4225142045424B0446556556556556506556550D56204556488556106556000000000000000000000FF56D60000\n\t004A98888C088B8AB8AB903C908AB09380002A82AE42C2AE2A61342140002142A60AE0002B220828E2AE2AE2AE2AC0062AC2\n\tAEAAE0002AC0222AE28C2AC000000000000000000000FFB3A8000000603800820001801809081C0080102180000000060040\n\t0600E08400C0004C608A02600201200008E00600600600402600000600600200002200622E006000000000000000000000FF\n\tD03F200000081A888068810AB801851A848AA04180002AC2AE0042AE2B64821060000442040020000042062262AE2AE2AE2A00ca4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D45100000000\n\t1A21902801A01931235A00001821800000000600600600010621600004008410000444403600600600600600611400400680\n\t6004004106006004004000000000000000000000FFE35000000028388D8000AB8AB8010018A88AB88180002AC2AE2AE2AE2A\n\t00260860000000042010040042062062AE2AE2AE2AE2142AE2AE2AF0042AE2262AE02C2AC000000000000000000004FFD7CD\n\t000800003C42410841C01C0140184080080180000000061060060000060260000820164048000020C0046006006006006044\n\t004000006800004400006046006000000000000000000000FF6BB3400000151D50514155955CA50359549549158000554556002a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1040162AE000\n\t004046006404184000000000000000000000FFF2A4000000001849050895843841001843803801800008000600600600002E\n\t02600005400608000404600E00600600600609601640450600600440440C2D6314404000000000000000000000FF2BC60000\n\t000018058848418018938B5891800801800000000601600601010608E00030404602A1041060C60060060060060065241300\n\t320061040A8126006024034000000000000000000000FF6348000000031804A50001801A0590180580080B80000000060060\n\t0601041604600029443604AC040961060AE006006006006044000002006C0400000C006284004000000000000000000004FF00aa4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AE2A01262A80\n\t0022009020620434628A2AE2AE2AE2AE2AE22602E28C2AE0042862AC2AC2AE286000000000000000000000FF6EC500000015\n\t51119038B59159058CB951B51D5580014C05565565575425325100004104444060044CE54855655655655640E4A444624455\n\t608400600E054156406000000000000000000000FF5030800000001003801001801803815801801801800000000610600600\n\t0012000000110444056000016022006006006006006006206004006000016006004006056000000000000000000000FFC7F3\n\t0000000AB8840000018898010018018A98AB80002282AE2A62AE2A020624600010428E20000020E2062AE2AE2AE2AE226006006a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001041\n\t800A00840A49801801C11C018001080005406006002052000000000000096004008026002002806806002106096104806204\n\t50E044005006006000000000000000000004FFBF750000000AB0408AA8AB91588390188D8E1AAB80001182AC0162AF2B0482\n\t2A80002202203060042802022A82AA2AE2AE2AA33E3062442AE4040462042AC2AE026000000000000000000000FF0D460008\n\t00001021850801841849801805A03801800000800600600600A0060000000200900D608400600000600600600614601400E1\n\t040060044B6304504006036000000000000000000004FF95350000000AB0898AA8AB8218A98218A988B8AB8000A202AE226200ea4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (070160400860\n\t06006006006000000000000000000000FFDC28800900101C00801C41801581801801C01C0180010088008070072040020002\n\t08018A4460000010E003017004907006046403506004846021006007405007006000000000000000000000FFD16200000000\n\t1221800810C00801821801C01C01800100121502680780200C00000000000200000500608810601500608750202080F08600\n\t6005806007806017806000000000000000000000FF25AE00080000110D80080188B80193584580580180002410040B600601\n\t220600000010890A02020002611300700400600600200002603600600002609400600630E000000000000000000000FF5696001a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (401600008048\n\t000002000010000211829000E0060062C2006100256200004002484006026000000000000000000000FFE982800000101800\n\t805881801881833909D05D01800100081100E00600600628042820000600600008840604200A10600601001242700E886111\n\t0460048160A7106200000040000000000000FF94DE8000800018A0821831A018018318018018018000000210026006804006\n\t00000000002400600100008A0008029060872A040248E00400600010600400400E006000000000000000000000FF57F78000\n\t00001900841801801001811801801801800001010000780640600200020840020600000000E0060070040078060060038060009a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018008018\n\t00000003841801D05A09800100400702600688600600028020000E00800009022E04200010600601210A02600E0860800460\n\t02116096006200000020000000000000FFE311000008001800815800000021891951811D0582804840060860070240065100\n\t001000841202A8040002000290006006080202506002426410014120406006046040000000000000000000FF81A200000010\n\t1800801901801933885801801C09828029407609600702600600805000008A0882A80201AE01200001600608600208600202\n\t600000C0A220604E106020000000000000000000FFE0E2000008101800809801801809801821A09803800100C10602600608005a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (440000008000\n\t0000000000000000000000000000FF88B10000000A90AB9008808888AB9000AAAAA8AA80012AA2322AA2AA00244200000000\n\t004220210020200A10A3022AA2AA1020122AA1022AA1000221885022AA2AA000000000000000000000FF88FD000000004001\n\t050008000000000000001C01800000600000600148E4C80000000000000B01000082245401080000000400A00004D0000100\n\t000000420000000000000000000000000000FFA25A8000000000000840440220001340004000000001000108800000040000\n\t0000000003480000000A0080000020000000490210000000000000308420088000000000000000000000000000FFA9B4000000da4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000094\n\t0200000105510010010050042300A4004041004000008004020004004000000000000000000000FF012B9100001559151518\n\t43845D558CB555D55D558001556D4E557557D465060000000004044160004172AE456D5655655650640D5561265560005564\n\t56557557556000000000000000000000FF97010000000A80AA850CA08D48AA8208AA8AA8AA80002AA2222AA2AA20200A0000\n\t0000020230A0002C20024322322AB2AA0022022AA40A2AA0002C225200A2AA2AA000000000000000000000FFC02E00000020\n\t002020409011000000000140040000010000008008000080100000000001280C04000800008800008000000300C000020900003a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (050802412002\n\t24000B4400400400000109010080100001008800000000002803000014008012804800080000000100034000000000000800\n\t0800000000000000000000000000FFFAE0110000000042008004100000000000000000000000000000000080000000000000\n\t0000100000011220000101000000110010000008000000000100000000800000000000000000000000FF5A9D8000000AAC00\n\t8808088088AA8018AA8AA8AA800022222B2AA2AA2A226200000000028220220024200A2022032AB2AA2222A22AA003AAA200\n\t2AA2222AA2AA2AA000000000000000000000FF54E580080020500140420A00000101400140040000010010808010050B010000ba4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (104805800004\n\t004004000000000000000000FF89D9004000400800800800A04C00802A008028008000002002002002002042002028002102\n\t80200010280240200300208200A002102002002000802002002002002002000000000000000000FF94D60000000002000000\n\t0020000000020020000000008000000018000000000000000000000000000008000000000000000000000000002000008000\n\t08000800000000000000000000000000FFAE6501000040020000810000400000000820000400008000000100000000000000\n\t00100110000000400000040000440040000890000000000001080000050800000000000000000000000000FF3E1400000000007a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000002\n\t30000040000000000800000000000000000000000000000800000000800000000000000000FFFE04010000000C0680690080\n\t0800C00C06860A04800006200201208200300240200010311300202041A02204308208200200391200300300200000300205\n\t2003002002000000000000000000FFAA32004000001001809801805E01805809205801800000600600600600604600605000\n\t4105006000106806C0600700600701600690600640600000700C006006006006000000000000000000FFF246000000401001\n\t000600000000000001000200000000000000000400180020000180400400020800000180000400590480418400000580000000fa4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF00080000004004000000000002002000002000010000004000004000004800000000000800\n\t804000000000800000000800000800001000000000800000001001000000800000000000000000FFF25F0000000000018008\n\t0080080080080180080080008020028020820020020020000020020020000028020028822A20220020008020028020000008\n\t02002002002002000000000000000000FFA11C0000000010000000000040000004000000000000800000800000000000000000064040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20844DA68F60\n\t06000000000000000000FF3ECC000000201A01829800D00011805818881801800080623E00204E4160060040010480060260\n\t00800002880006886006E0622C10E00E31600004000280D047146006000000000000000000FFE4CF000000001811801A0580\n\t0103941920C838058000016826016016804C5680400009304454451000280004010600608608694CA1600F00620000090204\n\tE006006006000000000000000000FF1C1B00000000180182D900000001000005811801800000220000600600400400C00800\n\t2016006040100000080006106006006206006006406000102022006106006006000000000000000000FF409B00000000000000864040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004600602000\n\t608282600701642600710600600720700040600204408602E006000000000000000000FFEC13000002420E03A0DA81801001\n\tC10801800001820040280204200600680680600880B100004021C03124080006006006106A0200600640E0000060C0001017\n\t007006000000000000000000FF220F000000000801801885A01315803844A00005800101600601200620E22E00600000300A\n\t286008080004800086006086106087C06006086201907082020006006006000000000000000000FF19B1000010215819D438\n\t01AD04058A10C1A0B901800001604600202600600604C0080A00340442A010200282004680614681610018700694E001420000464040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00009C151218\n\t05801800000001600602000F144004006080020806004000087048006006006106086484005816004000804022006846C068\n\t06000000000000000000FFB01C000002005003813800801801803A00801800000040600602200600600600E0018060060402\n\t04246000006006007807907406004806004004036C2A006006106006000000000000000000FF0D04000010410801841907DD\n\t1585B93D81800019800001601E00200600400600E01018413400438092684212604680E31E01606310606695698002EB0800\n\t4416686006000000000000000000FFBC2D000000040811900801001001001820A0010184000060460020060040040260000100c64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (680600600600\n\t0000000000000000FFFB87000000001009C55801801009841802805800000001700604040E8AE00600400000510010600410\n\t601680648608E026006010504207004025005055002446286006000000000000000004FFC928000000000001A01803E01C01\n\tA018018098000000906806000286006406026000200085084000002004200086116426006020A86006006024824804A06806\n\t006006000000000000000000FFAECD00840826000184101980D80189EA0080D84000008020021800860162061A6080826015\n\t01800440062500040680628608629080750E71E414104015006406106006000000000000000004FFAC89008008005209815800264040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000008060C6\n\t20608628610648E446104086106C20046016406806006000000000000000000000FFE26F00010011F4018068050014010008\n\t40B61A00000000200200000600400400400100548008C1000160A680608600600620610208600608600001F00C00602601E0\n\t06000000000000000000FF2D89008008605001A0880F807005A09C2100184000009868060808070060260840014852180000\n\t8640E0064260070060260060E2004106104416146004402006026006000000000000000000FFC13900008414164980180180\n\t94C1A01811A81A40000004600600040610600600400000000100400000601641620648610609620000610F0064240440042000a64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180180000\n\t1800000000400600000600600400000000000600400400600400600600600600400400400400200400400400600600600000\n\t0000000000000004FF73E7000001800401200001801801A01801801800000100400600000600400400000100000680400280\n\t6004004006006006006006004006006806007006006806006000000000000000000000FF434B008008400841808801811B01\n\t801801001840000008400600040600600400000000000E088004006016836406006026004004004814002004004004806026\n\t046000000000000000000000FFDB96000404040811801809805841811810801800000004500610100610404408000010110600664040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000000000\n\t000000000000FF215E000001018801007801841801801801A01A84002000600600000680400E220020060000000000802004\n\t02600E00E006804004804814000000100030006002006000000000000000000000FF8DB8000001400C11C00001A018018018\n\t0000190000400068060004465061244400401014065003244848829461060070560061060060068044048170468070000060\n\t00000000000000000004FFD99C000001000801801901801801801801801800000000600600000600600E0000000001060020\n\t0800600200604E10E506206006004026004004006006006000006000000000000000000000FFC8740000018000010000018000e64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000464020040\n\t06006006007006002006004000002002007006006200000000000000000000FF8858000001000800A00801C0580180060000\n\t18018000006806003006004006420000028400006020C12806156406006017206106541C0680601000300200600600600000\n\t0000000000000000FFE06D000001401800801801901C01800001D4180580000060060020072040260000000000802862A82C\n\t20870840860072BE0061C7D00026006201802002006006006400000000000000000000FFD4BA000001000A01003801803C01\n\t801C0200B800000000600600000E006004450000050C00000044412404156406006006C0400402620400001400080000680200164040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (881A00001C01\n\t800000400600288600E086000000000000006000020048246326006106ACA00E00222204400031288344E8CA14E000000000\n\t000000000000FFE96A000001600001201801801801A018018018018000004006002007806006000000000800806002002000\n\t804006006006003006000003804002002002006000006000000000000000000000FFDA87000001000011402101CC18018000\n\t020AB80780000060060024461041040000001004060060000040028060461060064060270028160040009120120060060060\n\t00000000000000000000FF9C9F600001000401000001801801A00001801801800180600600200E004004008000000806806000964040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF55B70000105A40100C00020800000102A400004200000004504210A00800000000000B04000002000A00802888\n\t90818000080210000148020000108100010009800000000000000000000000FF42ED000001000801009A0991981188180090\n\t1081800002412600280E00400400000000028002200000000001600620600640204640600210400004244234600602600000\n\t0000000000000000FFCF6A000401200B01201929A89B05A49949281A85800084544692A036CA4A46000000548A908B2A00B0\n\t2D00916016316A0E802C06A46912A04A40842A42886C06206400000000000000000000FF181A0000011442418B3805C2183100564040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (340330380280\n\tA803C8309300385330300140308231312A10A000000000000000000000FFB6D5000040013280203261200220304449280200\n\t0000D40800880800D10860C00000808800C08800A00C00D00009081080008C08A00290810820E008108007810D9200000000\n\t000000000000FF87EC000101840120C20C00800808848D10800800800000220201200200A00200000020004A0D200000220A\n\t022203003002302002162022400100022022822012002000000000000000000000FFB26F0000004000001010800201820200\n\t01005101800000000000E000220280000000400000000010440020001020400318870100001000240200080280488864700000d64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (40A00A008000\n\t802C028820028220020100004414C2A02A00A82802932802002802802802C228028129008020428028028020000000000000\n\t00000000FF8CAD0000012014002012092002422000152002040000800914C30004C088888000010910089008008088B08000\n\t04004004001048810000C04801154D0C94C800004800000000000000000000FF14380000A90238818C102189188994384D00\n\t390180001060C600680610600600000021040600E00840600601601640608E02E42634610602E10012442C046406A4600000\n\t0000000000000000FF58C4000400888C10800800C00C00C08B00D00C20800122320B4120032130424000000010232230010400364040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF7B7B0002003523542145503302C43002C43303520000D50CA0C48D50800230450000310A09008880910C40D08D5155\n\t1550D508B0A00550C30900800900CB0D50D50550000000000000000000FF7DBA000800410400440004420400000442440404\n\t00010290010210000000000000010A1000011003001121120001800000001481001001001003101109440001000000000000\n\t000000000000FF3BC60008000AA0AA0402020A80000640000AA0A800002A8030000AA81802203A0000000000028080020210\n\t2402A82A82A82A82800802A80A00002408002002A82A82A8000000000000000000FF4CEA000200C00A00AB4940C04D08B14D00b64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A2002002002\n\t8022C200200200240010210200A002002000000000000000000000FF2EB60000000800AA0000F00888AA8101000A80A80000\n\t0000402102A92A9AA82A8000000210528400200200201AA82A92A82A80102A82A82A8000230208110AA82A82A80000000000\n\t00000000FFC53E00080000000008000200200800800800200000000000000800002300800000000401402C02002400800000\n\t000000000002000A9000100000308248000000000000000000000000000000FF798A0000000A20AA09210008A0AA4C400808\n\tA0A800003002902802A82A82A82A80002102C10400803302082082A82A82A92A80202A82A82A8200220240000AA82A82A80000764040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080080000030\n\t0200300300300000002120905301308200210200300350311321300310300310311310300344300300300000000000000000\n\t0000FF32B5020151801001809805805001001803801801800000E00600E20605600000800000010400600040644608620601\n\t602608600E206226206000404226006286006000000000000000000000FF4FDF000001215200324009444400080241200204\n\t0000850A208A00048000000000014008CC904A0294080081000100480400080880480480480280C844D20000800000000000\n\t000000000000FFFC03000000840800810804801801A4C892804800800048211200A8020020000000000B000220210001213200f64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFFF220000A8001001000000002080004004000001800000C000006210004000000000000080010000204204080404088140\n\t080208400000500010200220440080000000000000000000000000FF344F0200000038A0808803C004001048058009008000\n\t00200200A10222200000822020000204000000252200200200224A6020020005404000800824000020120820000400000000\n\t00000000FF298D400C0141C54040640008000040040000000000006010000010114090000004010090290010800000800010\n\t01201401009401081221001001001001001201101000000000000000000000FF9075400400C00C00C00C00880900C04C0080000e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020060062001\n\t0642402420020008220024200E006000020000000000000000FFA68A00088100102104082194D80182982181B92191000860\n\t0622600601E00004808002008265E00000040622400611604600269001451C16010000A08800008600600000000000000000\n\t0000FF9FD700008100182100180180981589012180380B802008400400E10600400008800002010208600802410022400200\n\t600600000200400600800800A0AA102106086100000000000000000000FF7E0A00080000000C022000142094000090000014\n\t11404101500100000002001400000000001004104500100100800900000000102280001103100800402A0000100080000000008e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80002262AA2A\n\t02AE40C0100000000002620000002262040062AE2AE2AE0300004141E62040004224062AC0042AE000000000000000000000\n\tFF9CEC2000310400110B420184180580194580000180000060020000062264C000000000008A020B00084004036002006006\n\t41040020C0060D4800002106004516006000000000000000000000FF5BDB00000101500500080180B8A18038119038058000\n\t11600601000608600800000000000048A0000100B63040060060060820D612020C0001005124300020440060000000000000\n\t00000000FFA552000001001815004841C01C81843813801841800020E0AE42000600640000008000000000220020C0100141004e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF2F\n\t65200113295903014155905905915AC395595200005545545505565545500000000005264860044045105505525565565565\n\t5240C45600400440048E5524B6554000000000000000000000FF5A3E0000D12A380300B4AB821915A8DA219100A980002A62\n\tAA2A02AE0D63200000000002842884804C03042902A82AE2AE2860B60824062A608008E08E2AE00C2AE00000000000000000\n\t0000FFB830000041220031280401831829821809800001800000400000000600600000000000001004028012C00400000200\n\t600600600608208634E20004E026006006006000000000000000000000FFBFD40002830818A11000AB8818498E921186C0A900ce4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600610600609\n\t2014026806004014002024004000000000000000000004FFF1360002210310030B4001A01801A01B45801800000000600600\n\t000600600000000000010010E20000602600600600600601600202010428C200112104006114006000000000000000000000\n\tFF62F4000483201A814400AB8098098A90018AB8A800002AE2AE2A82AE2AC2A800000000022623700422C2462AE2AA2AE2AE\n\t2262AA2442240050043222242AE2042AE000000000000000000004FF4FF6000A050112D1820001C8BA018019058018040000\n\t00C00401000600600000000000000802680001004804000000600604640202001400C8000200440025460040000000000000002e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00440C2002AE\n\t2040000000000000042060001061142224002AE2AE006416202096206000186106006004016000000000000000000000FFA7\n\t7C000005840041052801803803809801803802000000412404800604600000000000044C08E00434C0A40122820060064160\n\t5613200602E00400C0860C6204404000000000000000000000FF5A120000418818810010018298C984580182180000004CE4\n\t0608000608C0000000000001000400020064140820280060060A648600245410600022624C2120AC13600000000000000000\n\t0000FF97BE000011903829001201943CC5805811801804000000600600000600600000000000000C0009061041140020020000ae4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0004FF229100\n\t00AA0458AB88B8AA01190182B8AB8A98A880002AE3262202AE2AE0060000000004442A000002600622602E2AE2AE2262C600\n\t42AE2A40042A22A628E2A82AA000000000000000000000FF0B300001540810A39019540018018C1955953D5000002C608CCC\n\t05561560060000000000044160040440205360565565565160265244A6434004402044016112142000000000000000000000\n\tFFC710800000101801841800003823901801801802800000600010000600600600000000001400E0020860CE016406006006\n\t08600604C006004002012006006002002000000000000000000000FFC9E800008980B81B0848AB8858458810AB8898AC0000006e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006084214806\n\t1100001461000A6004002000000000000000000000FFB679000000041C0002D800003803849800805C028000006102848006\n\t8060060000000040048C600434C0A40552860060060A600404600600200401200E016801007000000000000000000004FFD2\n\tCA0000AA09B0AA0018AA1C18118018AA88DAA800002AE23E2102AE2AE00600000000418C2060004164043841062AE2AE21E2\n\t3C5842AE2300042022362462A82AA000000000000000000000FF859100080004D8018498000B190981380180180080000160\n\t2680800620600600000000033414000620C20000608600600602610600C00608400402A2142C62202020000000000000000000ee4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (070000060160\n\t2600008000602600004000400600600780790608600600404414440008608BC16007800000000000000000000000FF048280\n\t0800001C008A98000018018098008004010440806006800C0744602600002010402701002040000611290684708F68640610\n\t48360840004C248A00E903001000000000000000000000FFAB920000100008024A9C00001801801800C01C00800000530400\n\t900600600600804000628600600402410400720690600E006024006006002004016040007046004000000000000000000000\n\tFF74DF0008000000000818000298C9903800821800800100400408080600600600000000622601600000041400202E007007001e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFB289000010\n\t0050018230000238238098A00A1C0904404020070084064060260880000244060B008246808439010610E0060060A020C00A\n\t0000022C2442004100000000000000000000000000FF284F800000001000A01880101801841C0AC00501808000600EA80806\n\t0160060004000020840000282840400048A60062460060041222C01420280062A208EC2E0A4400000000000000000000FF27\n\t06800080081804801A000018018018008000018000006A8600800602E0060081000800840000000060800042060260060064\n\t2408201202220040A002206042004000000000000000000000FF2C53800100105000801800001801809C0080000100004060009e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001402103001\n\t00000300048030010000000000000000000000FF95C5000000001801808000101841811804803C918000082006A0000600E0\n\t261000000260861061402940440040C60160460060040460C01120104062A2086446044200000000000000000000FFCB9800\n\t00000010018000000038838A38A08C1841810040601700804600601605040000400600640002000440801600640600E08030\n\tA0100020000A6002404004004000000000000000000000FFA6D600000000181984D100041881883810803821000029E00610\n\t002600600E02000000600605821200410410C00E00600600E04000640204A042026002214014104000000000000000000000005e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000080000000\n\t00000100000004012012002800008008000002000800000084001200A8000200200000000000000000000000FF40A1000000\n\t0038888E88001C00100AB81C88CC0680002522432AA2AA2AA2AA0000005422022081004024023122AA2AA2AA2AA310042162\n\t0021002AA102002000020000000000000000000000FFCA3400000004000200200000A0020001220020018000040054006000\n\t0000000000004400100002002C40A4150000000000000130410080050000004048300480500000000000000000000000FFBA\n\t0D8000000880400000000200C80000000204C800001081000000000000000000000881400C0100008410000000000000000000de4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5B8008002014\n\t0000040000A02200122000044000008000090010050040040000000040100044028010C80010050050040040440000000040\n\t0200000C20010C024000000000000000000000FFB0C2808000109113921800001001555951951D53800010E107556D575575\n\t5600000052455654E101157026036D575575575560262564564A40002164045561360C6000000000000000000000FF993300\n\t00004CC8AA88A8000009008AA8808A890880002822822AA2AA2AA2AA00000000A2A22D20000AA0022222AA2AA2AA2AA20248\n\tA20A34A0002AA2220AA22228A000000000000000000000FF70EC0800000222200124000B0108000200000400000084024080003e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000000000\n\t0000000000000000000000000000000000FF473F0100000140200000000280C00000400204040000448D2080000000000000\n\t00000C80001000800084101100010010010000100880080080012880100000900C8000000000000000000000FF22E3000000\n\t04000204C0000020024000020000000000100010001000800800000000000000050200AC08A04200000000000001202200A0\n\t120200040120000440400000000000000000000000FF011088000008088888080008584D8AA88C88E8A880004030122AB2AA\n\t2AA2AA0000002022AA202000002112003AAA2AA2AA2AA3120023022020010022022AA002012000000000000000000000FFB000be4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00400C000000\n\t00000000430000500000400C201800004004005004000281804015800004004000000000000000000000FFEC0A000000B008\n\t00A00C00800800800840800200800000200A082C02002082022000000002002080002002C82002002002802802C020020020\n\t0000280A082042002000000000000000000000FF2B2E00000000000000020040000000000000000000008008000000000000\n\t00000000000000000000000000000000000000000000000000000000000000001800000000000000000000000000FF554600\n\t01004003000024000000002000000000000000000800011000000000000000400000000050081C0004044010000000100000007e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001040040\n\t0000040000000001000000000000000000010040100810000020000000040080000000000008000000000000000000028000\n\t0001000004000000000000000000000000FFFDEF000008808B02A00800820800808800800740800000200201289B20206308\n\t200006000200200000240200200240200227A002002002002029003003002002002000000000000000000000FFBC83000001\n\t401A01A01801801801801A410000018000006816106406006906046000000006004000104007506006806007005005C04004\n\t006002007006106046006000000000000000000000FF108A0000011000010040004000004000016000A0000080000000000000fe4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002000016086\n\t00400E106000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF51400000000000\n\t0000100000000000000000000000000010040048000000008040000000000000008008000000000000000040010000000000\n\t01000000000000000000000000000000000000FF96B7000089A00803000A00800800808C0080020080000020020020028020\n\t0200200000000200202800200202242B002002402802002002002028002802002002006000000000000000000000FFA7510000014040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (260060010011\n\t0640C0004C81000060060160061442020030880C200120628E04406E006000000000000000000000FF226100000088490001\n\t08018018014938508002818000086406002006C0600E00E00000000700600001420011610608400600402208220216A00040\n\t641760404608E000000000000000000000FF5175000000A00A00002000841041801A00852000800114600610700410600E00\n\tE000000006114080102A0080600E0840060010035520028120A8006006104486036400000000000000000000FF9950000000\n\t880800000001001001083080800080000000600600604000604600400000000600600000600040600600400640022200228A00814040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001C51414009\n\t801841815C3480000180000160060020040060160060000001040000A214248621744600C00890E10E10640704608200E006\n\t046026006000000000000000000000FF7162000004241A01800113041801A0B054840000000000C00600280200700E004000\n\t0014448820A0000800216206206234212882113A0000608000E007807006006000000000000000000000FF4A470000000018\n\t01804001841A01A11C40820001000000500608200228600600600100100410208000600149610E0048042020034320020060\n\tA9016006086306026400000000000000000000FF0FB80000018028D061880080187580188880A0018000827206002026106000414040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0441E85608E4\n\tB6806000000000000000000004FF7D4C00000185180190000090181100594081040080000420061100070068060060000000\n\t0408420400612604601604600E0040004008234063000060060C68A6006000000000000000000000FF3ED1000004A21801C0\n\t0085801001081C001442400000002804002802106006006000000436106204006007826007C060C6A0080082800A00400482\n\t680600600E006000000000000000000000FF1E2A000021401C01002001841C15C81800882221800000500600298400600600\n\t660000100C4002004982661A6826006C8004706F02600C80600102700700600E006000000000000000000000FF958D00002100c14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600008005400\n\t02040C42062A6486086856004006107C24804004006127C06006406000000000000000000000FF063C000201811401C00801\n\tC01C01C11824808001000094710608800244600600600000000708020500C446216016824006014004214004004284086096\n\t22720E006000000000000000000004FFD4B4000001E01801000801801801811C0080000080004028C600080622E006006000\n\t20180400400001401180610680680400400202A40000600408608641600608E000000000000000000000FF34E9000000821C\n\t01084801091069801484804000000010300600000200E006004000200004416004404480436806004008190C5A80213825C000214040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80200001C018\n\t31A01801805A3080200020060000060211460040000A0855004804144816D0650649724CC8C0061062061260008370060040\n\t06206000000000000000000000FF954400060180B2410118016018298110218181A800009860060000020060060040000200\n\t05064001E0400600600600720428C00600610C03E000026046006006006000000000000000000000FF3E7D0000018210A100\n\t5881811C81C0D80A806001002040604600002200680600600020000541400440001E00F10620C000005C4584C5858C608448\n\tF8468070A7116000000000000000000000FF09B61000A9801009C48800809801801C0080000400000060060108022461260000a14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600200400600\n\t6000000000000000000000FF1ED3000000001801000801001801801801801800800000600600000600000600600000000400\n\t4004004006006006006006006006006006004004006004004006006000000000000000000004FF020A000000001C01000801\n\t001801801801801C008000006806000006000006004000001004004805005006806006006007006806806006806004806006\n\t804006006000000000000000000000FF28AD100230001810240101811881C01A4B8018048000006006010026200006006000\n\t40000400420400440604E00600600000000600E04E0040860861044040A6006000000000000000000000FFD5F300010004B800614040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000006A46004\n\t006206887006006006006802802006804104006008003006006020000000000000000000FFBCB7000004000800C01001001C\n\t81C01800801A0180002020062A080A000086004000A00084A8600601484680600608600E096052802006E240060260000020\n\t06006000000000000000000000FFF8600000002002018018008019018018000018008000C16116540013006146C0E4005405\n\t0E504104406014344006006940121202103006046005146442004006006000000000000000000004FFC7AD00000000000180\n\t1800801801801800001901800000600600000200600600600000000400402400400400400608600C2040020020060060040000e14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000180180180\n\tB880801800000080700600004400600600400000000600400100600400400700600400400200200600600100680200000600\n\t6000000000000000000000FF5AD8000000000800800000801801801A01821801820080200600180500100600400000000404\n\t6000004007107806047801001006006406006080806006002806006040000000000000000000FF51DD000000000800900000\n\t841841811B41801801800000E00600000400600620C00008010C0140A010D02E2A60060460A0028226087406006000086826\n\t000006006000000000000000000000FF9CDE000000000800A01081001A01A03C00849800840000600600004A80002600600000114040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A0A2C6206000\n\t000000000000000000FF516A000084682D10A080400018218B5802081E018000026A4E10044E846807086001010084114000\n\t20603480C206216406026A08080B0E242020026002102006026000000000000000000000FFF74E000200000800A00000001E\n\t01801800001A0180008060060000060060060060000000040040000040040040060060060060000008060020000060028000\n\t06006000000000000000000000FF2A89000204000800880081821821801A20809900800000611600100C0000660044000404\n\t8620E000C8620400500680700540401200200600600080640B002006006000000000000000000000FF3ADB000000400E008000914040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000814000\n\t010092000000002E0028040280120101000000210010200000000000000000000000FF942200008018621209600004007000\n\t40C000000000000000000000000811000280000080001800000001001204008081C0500240001000018021000028408A0003\n\t0000000000000000000000FF547F000014060804868071001801829821041002000000280602648621000E00400000000620\n\t614031620400410E10640600601008080600201032E082002006806000000000000000000000FF7025000010250824CC4205\n\t353A11A01CC1213B4B8000C8E106826886A96A0EC2C000400A06C06880904C04CC50B6086956C8E840A40006812800A1694A00514040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C10CB0CC0C00\n\tC44C10800100200B42300309211308A00000111305312992302300320228340B2A302300A103303020083443202852812000\n\t000000000000000000FFB6F900420020010030020622830835201601E2900000820808840809008200BC0000210F90C48810\n\t040C00200020A00828808800B00D18C008400014408810C1004000000000000000000000FFFBC200000A0094210010018028\n\t008809018808488000002AB240210212200200200000000201200008207A4820834922120024024320022020000020020430\n\t27002000000000000000000000FFDFD8000000000488000100190000000400001020000038C040086220001010010000100000d14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A82A80000000\n\t00000000000000FF626F000200220A30A00A30808D10B02B24A00A228000CA2002802842802802CC200080040344AC00AC28\n\t3300280290200300210AA02C02812800802802012002002000000000000000000000FF70D900022420100124D28534224224\n\t80090002100000810A44C308808008048080000008C9100800010900800804A048A1010C2494C8D4D4090080480488400400\n\t4000000000000000000000FFAD6D00000200520B003053141801815AAD011821800008604600630600600604600009040648\n\t600040E5165061060161460062142C4416016110006004034006006000000000000000000000FFCAC70020104A0880D50C8000314040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8200520280AA\n\t82A82A80200C02082083202202002A82A82A92A82A8000000000000000000000FFD3DE00031035034034030024C24C0D4300\n\t2002000000D300A8C00400D50D50830000001240C00C00010D30D51550108CC8C51140948B30AB0900550D51450550550000\n\t000000000000000000FF1433000C044004004085024004000004004004000001001001001001001001000001000001001001\n\t011010001001001411209801001011111001001001000800000000000000000000000000FF220200088808A0820940002000\n\t0000000400008400000008880902082A82A80000000008000000000002002A82A8028A082A00000000000000002A82A8A20200b14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018019008008\n\t40800000200210202200200200200000280208240002A04A00200200200200A01201210A0824000020020020020000000000\n\t00000000000000FF5AF60000000CC0CC0E00900AA8AACAA95800000400003B02A83786402A82A82A80000002A83400002002\n\t402A82A82A81000003403C02002200002A82A82A8AA82A8000000000000000000000FFF9B300084200201200002A08008040\n\t00280001280000000A001210A80000004800010000880D00032C000000000142000008020820000000000300000008080000\n\t0000000000000000000000FF97E10000B00880880820200AA0AA0AA00200012800002202A82000902A82A82A80000012A82000714040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF5180400400C00C00C30C00800810800C00800800840000300244310300300240200100301302300108240311\n\t3003143443003003013002002881003003003003000000000000000000000000FF9ED5080001909895801001801001141001\n\t801801800009600610600603600600610000C0040041000060A600608640601640402600640600E00050E00E016006000000\n\t000000000000000000FF784E00024422422320542A00040020042420030C000081080480089480080080000080400504C800\n\t884880804805005354CA48C4840840808800804800804004000000000000000000000000FFC7A3000090800800808800A01800f14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (490000080000\n\t000010200100010108120030000088000108000000000000000000000000FF1BAC0000000800820000000000100A00000010\n\t0004000140004861000082040040000100080000800000200101202804002040000104000080000080080000000000000000\n\t00000000000000FFE299080000800808029800C00410440000800800840010201A0220420220023021800020020020000002\n\t0208200202208A002450002002002080282042602042110000000000000000000000FF27AD400C0040840140040000000000\n\t040000000000000810100010010014000000010010010210010800810010410011210010210010000000010010014090050000094040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180184490\n\t0000601604240610C00604600000600604000030600010600600600620400C04201014200004612E10601608800000000000\n\t0000000000FF907A000801811000821003819805893801961802846001E7E600204606405E1066000040041A600001608022\n\tE08618E21601800402032200808202600609E106000080000000000000000000FFEA8000000192100080D0258058119258D4\n\t001800008054600600210600000600610000600600605000610022E1060162060004C60082200090C8006006406046000080\n\t000000000000000000FF23D0000800148040012040004004008154080040090022000002048011002004000000000000005000894040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFEAD0000000881888AB1A8391184180188700799A80002AE2AE37A22E0062AE00600000041010000050230221E2AE\n\t2AE3CE34A2362322A84120002AE0340062AE2A8000000000000000000000FF97EB2002008458008018498918019258418018\n\t01800000600610208648600620C00000222202A8002C20220460060060060020860080001088000064024CE0060000000000\n\t00000000000000FF279B00000181104281200084592D809810929820800000600600200604C00614600000410C3000000161\n\t0810600600602614400C08200224200000610C006006000000000000000000000000FF9BA8000001801020840001401C01C000494040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (440860060060\n\t1600C084086006026802006546046006000000000000000000000000FF8CC5400401D35D491551058D190189594B95594180\n\t0010655640044600655655600000655655600455455455655655614E0A041645655644E20455648640655655000000000000\n\t0000000000FF42870000008A18A88828818038018CBC8982984480002AE2AE2022A64342AE10600000010021080204E20C22\n\t62AE2AE2062062262262AE0860022AE0043172AF2A8000000000000000000000FF73E9000000A01A0080080180584B801E01\n\t801813800022E0060AA10E4B400600200000200200200000600400600600620640E0C61040060040000060320D780780000000c94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801843800010\n\t600600000604E00600600000000000000400000600600600645641404402600610EA04006048046006000000000000000000\n\t000004FF686C000001843821A20A2080194B811821801908800000600610010E404006006000004004004000002002006006\n\t006106104094116006006004006104006006000000000000000000000000FF4512000001A89A8DC88CD1003A01841A8B0AB8\n\t00800022E2AE2282260862AE2AE0000042AC2AD8002AA2AA2AE2AE2AE0060202042062AE3270062AE20428EAAEAA80000000\n\t00000000000004FFF398000C01C0DC0324124DA21A8DC01821881801800000600600001610400624E000006026026000004000294040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFBA7E0000890898808818008038298058190AB80080002AE2AE2B02AE0042AE0020000240040040002002062AE2AE2AE2\n\tAE2340060860860860002AE0042AE2AE000000000000000000000000FFEEC300000500184800988504190180390180184580\n\t0000600600000600600600600000445444C40400002600600600600608403640600600E00400644400600600000000000000\n\t0000000000FF278500002102580202504891180395184380190980000060060100062CE00634C0003080801001400D008E00\n\t6006006006014504056256226104006108006006000000000000000000000000FFD94500020100180200300D531801B4380100a94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600400600400\n\t60B428E10A2B400400600E004006000000000000000000000004FF23020000890AB0AB8820058258D58418888AB90180002A\n\tE2AAAA82AE1462AE0AE0002842082882002AE28E2AE2AC2AE2AC2262AE2AE22622E0042AE2062AE2AE000000000000000000\n\t000000FF92010011531150949488458C990188980495588D80005565515405565165545560004941544004A4504536556556\n\t5565544C6404046222004104556346554556000000000000000000000000FF19848000050000008508219118019138008018\n\t01800000600000000600E00640600001400400010000604600600600600400E006006086006400006056006006000000000000694040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (050000006000\n\t00000601680614C0000B404E0CC10010E0868060040060054C200410E0060940008063060000060000000000000000000000\n\t00FF5FCA0000018018008058818419018038040018280000006004800004D060050060000060040064040460300060000060\n\t0000A0060260B6026204006046003006000000000000000000000004FFA43E0000E98AB88888911B8038238018440AB8D400\n\t002AE2AC2A82AE4262AE2020002443C42440002062002AE2A82AE2AC1022AE2062163060062AE10E2AA2AE00000000000000\n\t0000000000FF2E5E00000182102180408980585584194080182180000060020000060260040060000442000B000402C0060000e94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tA536804041801101800811801801805821011801000180700000000640700000600000400210400000402611600182641605\n\t6106404084006100006046007006000000000000000000000000FFBB3D802001903081A00909801811801821001801006000\n\t70C701000700680280600000400009C40000642680700641E28F10668600E08406600080702601F047000000000000000000\n\t000000FFCCBA00000180B820801001801801801800401801040000E9010000A6116004006000006086006004204006007804\n\t006080002044017006004005086886200007800000000000000000000000FF9096000803801843A410219118099518A8001800194040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20600C044002\n\t012006082220000488202516000000000000000000000000FFB5C00000009018030208018018118038018038008000206047\n\t0B000610600200E00000402408C02040640030E00600E0041040420A20062020003022020AA00E0800000000000000000000\n\t00FF29240000018010218008818018018D18210A1801030000E8028000064960200C60000060020020005261100468840060\n\t024322D640904200E101120000002287028000000400000000000000FF461980002181182180088180180180380120980102\n\t0000E0060000A621680200600000608000240000600001600444600202A0062020000060800000802030460000000000000000994040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001083510000\n\t081000481480001081001003000400400002280001103280A02301080A00802004400A0000000000000000000000000000FF\n\tC80B000000801820040803805801805815C05022800100E0010002062808208C400000600621604050E11000600400600020\n\t249220004600A000020100012006100000000200000000000000FF49B0000000801805002801891801821841801810850040\n\t60261400060120000160002060441440080460002460042160080100420A00062824A0502012522006050000000000000000\n\t000000FF4F5000000080180000290388B80191180B94182A800006403C00021E00600000200020400622600800E00001610000594040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF653C\n\t00000104108202100100405404000040000000010012808000001410080000000000A00A0000000108000880000000000000\n\t000240000200110089028004000000000000000000000000FF1F8B0001C00008899400AA8020220000890408C88000552003\n\t2AA0420122D22020004224025020022823022AA1822AA22244220219250201200048A08240A2AA0000000000000000000000\n\t00FF2E9000002000404114800004010000200011580000012460000063442508068060004002304280000080880000040000\n\t04000008000440208002020008400000000000000000000000000000FF97B580000A0D00040020001100081500422200440000d94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1222A3A22020\n\t2222200028A20222A2AA000000000000000000000000FF477800080104100300100111000011200551000000010010110014\n\t00081001400000100024024000028001004A0100480D080508420010200001148411015004000000000000000000000000FF\n\tDF7F1001518134011159558C9101089155555955800155604F557D56417547B56000556404404500556427D570575574A4CA\n\tE4564D6116556000C46446505D56000000000000000000000000FF579B00000A08A8A880A8AA8248D48408A880288A800000\n\t22A22AA08A2425020AA00004A10A01228050224A2AA02B2AAAA200A0220020221220800021220A22AA00000000000000000000394040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000080000\n\t0010000000000000000100230400468100000800040400841000000001000040000000000000000000000000000000FF4432\n\t08004010021004220011000215000040005400010000A8800800011010148000000050040300000010800228800350080010\n\t008080080200000000100800000000000000000000000000FF1AF40000020540A00000000401000020020000000000000400\n\t0000001000008000000000000880000000A00010000008000000000A04100100000201280000000000000000000000000000\n\t00FFB73480008C900852888CAA8038298058A88AA88080002AA0022AA2AA2222A22020002AA2922120002AA2022AA4822AA000b94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFF1776004\n\t490002410010010001002000000000000000C00404040004800000000000000004000228005800894200000000041C040418\n\t00004088000005805800000000000000000000000000FFB349002000800800A80800A00A80848A00800A0080400520A22020\n\t0200221280290240200203000100248A00200200200280200250A02B082200002042422080002200000000000000000000FF\n\tB0F300000000022000800020000010000000020000004002080300001000008008000000000000008800005000000008808A\n\t0288820000800000000000000000000000000000000000000000FFECC201022000000000020000000000000000412000000000794040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (228A0A288200\n\t0000802042000000002000000000000000000000FF7404000200000000200100200400000210000000004000100000100000\n\t0000100000000110000031000800000080A00820000004000000000090000800000800000000000000000000000000FFF8E6\n\t010016800800A08880800E00E00A08804D00802000200206300280201208300200208A60000009259A95A41A2AA02208208A\n\t08208200200007A00301A000002000000000000000000000FFE871004001001801889C018018019518018018218041837956\n\t40F006106416006106206004030000CA45164C600600608608608C516056106400006046446100006400000000000000000000f94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006206016006\n\t00800000650600800050211400E0000840140061082AA00A00400054600600C080006000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF6B7300000000100000000000000000040100120000008000000000\n\t00004004000000004000000000001000000000805004000004000000000000000800801000000000000000000000000000FF\n\t67CD000401800801409001A00800A00800800800800000200200200200200200280200200200030008200220200212A0020A00054040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (EB4000004000\n\t7851938001899A458604050280098200204216006206006016226200006004028000C280010068060840E44067B82FA12B54\n\t0400C85226108080004000000000000000000000FF9C31080000001A19850001901C01848807800801800098C08E02700622\n\t600600E00000600600000000060410E004000140107400002042000000006486004000006000000000000000000000FF3CC4\n\t100005005801A00005821809810801831A55820021449692600622605642540041685454000105280040708000C404856044\n\t802D021200810060C6104000006000000000000000000000FFA6B1000001001803800001811801000011101881804004400600854040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00680E106C00\n\t81490E120021104000000000000000000000FFD3D80000008091154028A3803421A01811C00A01800000788600600600600F\n\t88604780E40200000020280E00608100082020030E036096427008405006008008004000000000000000000000FF03F30004\n\t11C41883A0000980100000080180030980008040060058060060060028A600F8480003110108088062060270060048069068\n\t0680400801288600C010086000000000000000000000FF3ADE000005801A03800005841010A01A098808C580200260071040\n\t0601604E00600640E5523000002821143068820164160AC002006A86924080242006904000006000000000000000000000FF00454040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1601E18E0824\n\t060002741D0014A04096806080542002280EB82A60B609407C006016017008006000000000000000000004FFE14E00222100\n\t1E01001001801895811C018000018020106446004806046006006006000C060002004421060065060060072861044AC0A490\n\t4200004006842008004000000000000000000000FF38FF000001021801501001811C15801801800B01000010E00600400600\n\t400600600610004790000401680681600004600608600008400400400480600E024020806000000000000000000000FF360D\n\t000050A0D8410128B3803009840C0DA00011800008C09600600600618608611E08639008051106400700EC868000180E000600c54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000421021891\n\t2808038058118818018240018000106006004006006426006015D0010000028008040800688682E31604610408FAB6006404\n\t084406082440004000000000000000000000FF2FEB002031201881010801901C80C01805820A01800048E036804006022006\n\t40600400100100820414480410640004692600E00100400C006205000017053000004000000000000000000004FFB33C0004\n\t008018010319018018018828058A00A18001A3589682614600400E28600600010480000010020608600680612600C0408062\n\t06204004805A06202A00004000000000000000000000FFE968000010C01B014018E191180100A8418808398020024286026000254040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0600602410E0\n\t0710C846026000000000000000000000FF8EC9200400803832100821805A05201811884000A0801020060070060062062000\n\t0854110502408088E00600611601689443100010852E006400006406806286006000000000000000000000FFB8C9000441A1\n\t1F21208029801A13300C098800008000605006006006002006002004000624020400004816106426486C0600C00000600660\n\t6000005006062080004000000000000000000000FF68D600000380B803040001A11814921841808F01808080600600695608\n\t6006A0642402191C8C001500CC17087A0870600628180801440441602400840740A400024000000000000000000000FF488600a54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (608644000000\n\t008000004000600400E2344060440A044800400600A004006006006006006000000000000000000000FFCBD7000000801000\n\t0008018018010018018000008000002006004006006006006000000000004004006006006006006004000000000006006004\n\t006006004006006000000000000000000004FF9075000000801000C00801A018014018018000008000003006004006006006\n\t002000000000000001007006006002006804004004004006006004007006006006006000000000000000000000FF7C992000\n\t02A21A0001080D801C01021A01848200A0008020060060061060468060200000340840040064060068260C6004100108000000654040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008018008819\n\t01A03A01009801800085804004644602408640E146452D204000020060454C650450608C80601088088108008600A0048060\n\t06804806006000000000000000000000FF749E000180A01A009E9B01C03C01801A03800001800008600600C0860362060008\n\tA0000000082000006404026804B0200488480400C006082000806006804806006000000000000000000000FFEDD100000080\n\t1841401801805801045845800201802010612645600640640E00254848020251450C04715052600405631000008010C00690\n\t2004007006006006006000000000000000000004FFF62A00000080180100980180180180180180008180000064160060860400e54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A00000600600\n\t6006006000000000000000000000FF38B8000001801A0080080180B801009809800C01000000600600408620600600200000\n\t60070000004860044070010060130A6A870A6886002000106006006006006000000000000000000000FFCFCC000200801810\n\t200901801C01C01801800A03802004744602600600E0C6254540406004002021846D42086006004006006006803006006000\n\t006006006006006000000000000000000000FF354E000000801A10000C818118018018118048C1802000622E00600620A09E\n\tA2420829628400C2A80260EA28E2260882AE046EAE0C200600E000107006006006006000000000000000000000FF2C55000400154040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80000092712F\n\t22A800106A44C16CA08505494C5335204826A00801036086A0F046A06000000000000000000000FFC9FE0000C3E01C0D0088\n\t05803805955C31800A30800008204608E22600600644C050006200880200A361020870161040048080008002870500082864\n\t1604600608E000000000000000000000FF6C91000201A0180120080180180180180180080080018020060078060040060040\n\t00006000000000006006006002000004000000000006800000006006006006006000000000000000000000FF583F00040180\n\t1840280801801C014458418028A1800000710644400600200E80600000E00640200000640400689C8460020420020020070000954040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000104401000\n\t00021A801A08181000000000200010081461161000081060105000000100010001004A442424430C40400002800000938002\n\t0100000000000000000000000000FF48BF00008402010001A100040050000184000020000000100000102008000000000006\n\t0400000000888601608040000000130000101600000000000808248041200000000000000000000000FF3298000013019881\n\t08080998180100182191880000000908860260060044860004304062060820000460840160A41048C0008040200026000000\n\t016006106006106000000000000000000000FF23EE000209AA9AA1B044A9AC1A81A01A83A88A848000A0848684680EB1688600554040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (406806056096\n\t10E000000000000000000000FFC840000540CD2CC0C10C80D40C20C28D10D10D44800141200300A08302B40300243142344B\n\t403000A5302220335350202B33320304200310300104B083503222402000000000000000000000FFD82400036038424E4002\n\t432222002042002002460000C00C00890700A008008088008009E0010A01600800180E00800A088048B4804980A00800CC00\n\t00810430C90000000000000000000000FF5CD30000018008309008A0800880852800800988800020A20200A00201A0022320\n\t4008200A22A00102217200201A00A81248240204200250200822200240200200A000000000000000000000FF14730000080400d54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (202A00000000\n\t02000A082A80202002002A02280400402800020802A8008000000000000000000000000000FFD3AE000000B44A20A00A00A0\n\t4A10C00A14A00A208000923002043002842802852810803442002B0051200280290280A833002803402C02012800A0280282\n\t2802002000000000000000000000FFF37400025520820A04A4012202822CA2A034A3040000C11004810804A9080090090080\n\t910C004800024940804A1092088480D0848AC8AC824880834004B00004AB4000000000000000000000FF3C1800000B00180B\n\tAA5829801809903803801811800000640600640608608E11600008610408C00000648E10E00600640400415430450620400000354040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0880AA0AA028\n\t0004AA0B000000002A82A82A82A82202A82002202A03200004800300002A82A80A00882003002302200A04002102A8848000\n\t2A8000000000000000000000FF17EE00014024431430A35415401035254424030C0000900D50410D50C40D50D00C50D40A00\n\t000B01290D48D50810D48D10CB0D40C008004509008005505488004D0000000000000000000000FF6A21000A004000000404\n\t0000000444200040054800000000010000010010010411090010090010018810410010012114011090490010814010010800\n\t00401001000000000000000000000000FF3AFD0008800000C00800AA08802000000000004800000102A8B802A80002A8200200b54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0400C8010000\n\t00000000000000000000FF7681000040800800A2280080191084580180084280008028020020020420020021120020020003\n\t0000A00200204200A03250241208A08A50000002A802CC2002000000000000000000000000FF70EA0002860AA2AA48C0AA4A\n\tAD001188AA88C08400012A92A82A92A81102A81302202B02000000004007182A80000000400400803202300100000C12A810\n\t00002A8000000000000000000000FF22C8000A121080000200004004C2000010092000000022000102000008800005008000\n\t80C80000020200000004A0000020000008110288080002349001000000000000000000000000000000FF18220002A80AA2AA00754040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100900100100\n\t10111102A9001221201001101001501001001001081001000000000000000000000000FFAE2B400400800C40C00C00920C10\n\t884820910800800141320308300200210210200200301300100100300300234315345350340B00B283011001043403003003\n\t000000000000000000000000FFEBAE000001001901811801801001001001001801800000600604620640640600628E106104\n\t0000000C40A642600E406106004106224006020080106106086006000000000000000000000000FFB5810000092000000004\n\t002002235002002422100000000004804804A90800B108008088B5000800B448A4800B11320C80855040804800830C00C00000f54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (301480C80840\n\t820000880D200100003000000000104100000000005401085400A01201502160300800000500080A03081200001000801000\n\t00000000000000000000FFAD730000000000A000000000000C000000001801000001000002000040E4061044000060000000\n\t000A00D022000001600C0045004C40004201000C0080000000000000000000000000000000FF8B820000008C0810800800C0\n\t000141043018884080002022120920820C208200200A0924C200000000201208A0022A208208614A00E3C209800000264201\n\t2002040000000000000000000000FFCCCA400C011004004684000A0584082000000000000100100100130011000000008000000d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00200000000\n\t0000000000000000FF07A6000000004943041841C81803C11D55880025900002608640600600600008E20220620220000004\n\t612E0261140060200800021000020C04000A6206046082420000000000000000000000FFBA06000800042080013002813913\n\t801821801913844003608601600600601008638238600614000000400610404649619420434E2D461221000000E006126200\n\t208000000000000000000000FF09DB00000010181000500D025821905801801801808000201608600602600020400200E046\n\t00009230600600000608600420020E20014220009200E04600E206110000000000000000000000FF22B00008000800240280008d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200000004086\n\t002022146000007203206006000400006006006006000000000000000000000000FF3821000058090991A012AB0019C10419\n\t018A800180002002AE3062AE1162AE02C0002B61140100002AA2062A83022062A6A2EA38A262AE3380002AE2AE0062AC2A80\n\t00000000000000000000FF32A5200144044A0590100189184502180B80401580001440060060060460060040040064444408\n\t0000200600004200E00600200210A006080800006006546004000000000000000000000000FFCD7B00000000805103380084\n\t58099139418000A1800001600613600629600048600200E10A0903000040CE00608C14601408008000000200010000600600004d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180030181580\n\t00018000114006006006006006036006000400400D0000400600400401611700400601400400090000400644600600000000\n\t0000000000000000FF5BB1200124954111D55555801B54025835954115800045055655655644655600400654054A15028455\n\t623655029440E22F4B00B60A0554450004554556556556550000000000000000000000FF35300000820A340380B0AB913A15\n\t00BC418AC0D380002442AE22E2AE2262AE4860002A60440C00002AC32E2AA24A2A62203373212A62AE2200002AE2AE0962AE\n\t2A8000000000000000000000FFC711000210000C4380180182DA01009901800041800010400600600608E00620E00400E00400cd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF3D43000003001A01841001D09800D25A238000038000116006006006296006004006008022310B040000C6\n\t0020462043160401540480040C0804004006006006000000000000000000000004FF9E67000051800055A05A018458000098\n\t91800001800000400600600604600628E00200010004000000421600401410E006C88A049000060102000060060060060000\n\t00000000000000000000FF78000006818AA0818890AB101AAA1018018AA0A980002202AE2AE2AE0062AE1640022A02080010\n\t042AE0062AC2840261220000042102AE3010042AE2AE2AE2AE2A8000000000000000000004FF7DC5000A00800041D41400A4002d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000A0060060\n\t06006204444090044006006000006006006404006000000000000000000000FF261700008C0200A989102110188892180188\n\t20AB80002222AE2AE2AE2AE2260842222A00040000020002AE2862CE2AE2062A02042A02060000027E62AE2AE20600000000\n\t0000000000000000FF55A20000241020058010018018048018D1840001800011600600600600600643400E00000400000414\n\t000600600600402600000C00802400000400C00600608E000000000000000000000000FF2E2D000001009801853092935840\n\t915805808001800000200600600600608E0041060085500000002080060320460060960140A400409600000000600600604600ad4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (021951C0A001\n\t800001600600600600600E4A60160122040000060A200409610C0000A6084048104504006006002006004204006000000000\n\t000000000004FF3F9F0000A10818C18AB0C18018AB0019518A00AB80000262AE2AE2AE2AE2262AE0562B22440000002822AC\n\t30E2342AE02E0842040942AE0060042AA2AE2AC124006000000000000000000000FFF2F50001110159150C591580195380B8\n\t03B4015480005465565565575574C601654354015400000441255644640655041045430044C03400600400E5565560D40060\n\t00000000000000000000FF3CAA80000302980400180188180189580580000080001060060060060061060040020000940000006d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF6D5F00082181184180190193580111580580800180002B600600600700608E00440200A13600400212600624A1\n\t040074B64C600434400E006002002806004124006000000000000000000000FF26B7000015921005000A038018038018D1C4\n\t000080000068060060060068060060AE00000400600401200090400600000000C0B000610600600400600600440600600000\n\t0000000000000004FF5AB20000918078980AB83D8558A98618018960AB80004162AE2AE2AEAAEA362AE506AA020400400024\n\t22AA04632E2AE10401424040C2260060042AE2AE2AC01C006000000000000000000000FFA8D700082114184080104182B80100ed4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200710608690\n\t100402009608A00622210010E20604480E006000000000000000000000FF137C900041000001011001801841801811808001\n\t80200060060078070260044040032042062840200062013021230400312034172100064040800C6016006084006000000000\n\t000000000000FF3E008028014001E0001401841807801C01C080018220007006006806807006086006A060540C40104062C7\n\t020002F0E9A80C124620000600600003680E006094006000000000000000000000FF49DB002001A09C02840C01801891035A\n\t01C00001820000700608E80611700608622A82A0060060050861040422008090060868800870260A60050032060470070060001d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4BA000599280\n\t02600E0260068A60080160460060062860A80A640207000C0000060020080020060CA0000800260020162160000000000000\n\t00000000FFBA900000010018800010238438D1001831820023800020E0863160060070224AE246AD40140240002060464084\n\t4404E00648826002804E12208002000622200C006200000000000000000000FFDAFB800009101810840401801801025881C0\n\t0000882008740610401600680400602601610601200000222C006006006235003103202A46000020C0740600400710E00000\n\t0000000000000000FF5440880041011A0585100180190104B80180000080000060060040070CE00600620E806444442050C8009d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFBBC580000004400004200013404013400460000000000000000100018012284D000011055021050001021000003004\n\t60D02A0008020006040100490000000508000000000000000000000000FF82B8000009001812050825803801851815C00202\n\t80405264963060070070200A4202A8E08604E00050402C002000016226016110406206000140402206006006286000000000\n\t000000000000FF0D830000000A194000380180995380180182000184800160060460160C60100060070060045040C8044004\n\t0020140000160862240360560900000A0026420006006200000000000000000000FFE26800000102182200B00180982B00D9005d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00A2320AA202\n\t02222B0022AA0020002C22AA84A0C22AA000000000000000000000FF3F6F00804200A04300300002A0010201104004B00000\n\t0008000000008008090004008100000A04800A90280000080010810204100400001000000008000300000000000000000000\n\t00000000FFBDCF0000C90148968800AB8540800400000AA8AA80002AA2AA2022AA2AB0124422AA8024020D21002020220022\n\t0228825211A2A648A2AA4521000222AA4A04022AA000000000000000000000FF87FB00004210905000800000000C0000D000\n\t1A0180000000000C00000060860000042460000400000A00802A80800060000000042000064880000000002080400000000000dd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A8208001AAA2\n\tAA2AA2AA2AA2222AA0122A22AA2820002820222120A268A0122A32022022AA2820022032AA0022AA2AA00000000000000000\n\t0000FF583D80080100000100100108000509400440040000000048048C100500110100800140000000400011108032008040\n\t5081200104950000100000009004884008004000000000000000000000FF6F61880101D419010D1D5580115580B023555C05\n\t8000557556557D575574C65571475465564140004062864C64A615444648E12448E5564562004D6556306557556000000000\n\t000000000000FFCA3500008A8A08C08AA8AA8008A88009508AA8AA80002AA2AAA0A2AA2AA2421022AA0AA0AA30240024224A003d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFCC5401010020000040000000022000440000400000000000000000000000008000000000000000004100C8E804A0000001\n\t000000401100000000000000000800000000000000000000000000FF81220080100440900280001340001340044005100000\n\t0000000010008008880000B00080000205000100880800100404500009400C00000102000A80002480010000000000000000\n\t00000000FFCC210801002080400002000000000000B00000040000000800000000000000000A010000000100020204000484\n\t00000100010008010000020000001000100000000000000000000000000000FFD8BE8000328808128828AA9018AA9018018A00bd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (470040062850\n\t860CD106806110C16D37107406006000000000000000000000FFB4BF00000100100000100000040000000000000200000000\n\t04000044004005004000020028000001884B0152010000C050004840404820000089845A2480000480400000000000000000\n\t0000FFE87600000080088AC00800840800800A0080080080004122030C221210308220A00200120200000050200200200300\n\t203220202202210280208822A28A102402002000000000000000000000FFD4CF000000200600200000000000000000000000\n\t0000021880C098A1800808000000080880000002000000000400000000080080290000000000000040000000000000000000007d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000200200\n\t20020020020020028000AA1102A840200200200202000280208228E802002000806002802002002000000000000000000000\n\tFF915C0000000004000050000002000000000000001200000000000540000150800000880000000000800000800800300880\n\t000008000001000088000000000020000000000000000000000000FFB3A7010106000800802800800800804A008048048A00\n\t01B0020022A20020AA0020020C00820882A81125DA5DA4022B208200208A08A14280200000244307A0228020000000000000\n\t00000000FF879C000001801B15801801841841801801801801800045650634E49610610E416006080286000002505016006200fd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF9E\n\tCB000000805140801800801009000800801801008010410610E10600600E0060060001040000000060244042444260040804\n\t8E090000006000286006026006006000000000000000000000FF6BF800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000600000000000000600000000000000000000000000000000000000\n\t0000FF0730000000000001000001001000001200001001000000100000000000000080000400000400000100000080100000\n\t7004004000004006000000001000000000000000000000000000000000FFDC5A000001001000A00800800A0080080080080000034040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (692E00200244\n\tA100022000016026806026406000000000000000000000FF4A05000101808201A0980180B083881821881801000022F40680\n\tEC0F10E1970860069016060100021006842402AA8268042D4E284800062000022C601722E20F906040000000000000000000\n\tFF88750000039000B985380182110D9218C180180100008862A6806A0600600E40640601048401008300ED08024106A00A00\n\t02C88280081F00A082006006416416006000000000000000000000FF84CD000012A11401C058008552018208819019050000\n\t44E4460464160161060D61070000040001000920140C00100082D445004624410044E100016026006046206000000000000000834040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (007486006006\n\t00631608603600100411040056808E81600E00E8103164880262060888808CF0B712704F026000000000000000000000FF7F\n\t450000090000858018158414018018018000010000006006006406086406006006140504200010002A8A026C07C10280C460\n\t0224700E043000006006006017086020000000000000000000FF624E00004000300280180182020100380183000000000078\n\t06004006806006006016020904480409A0002610A20020048F0820000068A882000100600608704600600000000000000000\n\t0000FF8FA200001190300082180180000180180180010400810060061241060060072362860080040080001040469060040100434040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFF8B100\n\t0021011000E1581B801801051801990015840010668600620600618699708608000600020400400210700560044200070C08\n\t808640C00420600648EC06006000000000000000000004FF184C00004040300900180180081188180100000080000060B600\n\t4026016006806006000006010004A074444040041060160C401700CC8600E00040600710C006006000000000000000000000\n\tFFD732000000803200001801800C01803801048040800000608600400600600688602600080600000400E844084814000006\n\t00010E000347896084096946024006026000000000000000000000FF162400014800048180180B801061801801800021000000c34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C0C164C80807\n\t404004046406805086126000000000000000000000FF8D130005502408000498018008018018458100008000047806005806\n\t0064161060060005204084942042AC800002406206084314245C1631400584F817A26436006000000000000000000000FF2F\n\tFD000000884A10003801800C01849801800002800002600611402610E00600600600080000800524444448400702014E0B50\n\t05000417104004106006204206006000000000000000000004FFBDB800040110100180180580380180188180000180002460\n\t0629650610600644608608000600040202410280E20482608620C844D0000E0840060C62060060060860000000000000000000234040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060170460060\n\t0600680600600600004420084680608001000000C041200006306004006014002080042000000000000000000000FF253700\n\t00938440318018118018018018458100018000026006006006006C8E50600610734629028C89040E02E41720630610488802\n\t020E84E00004E844432A48002000000000000000000000FF139D000000000A08185801801A01001801800001800000600600\n\t600600608600600608080008000000C1061AE28604E04600440410000602400100662600E007006000000000000000000000\n\tFFD29B000002612A22413809805811901B018120118400506056C0E92600600765600600080000002508090681640E1204A600a34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFA320000001\n\t800001800801801801801801800001802000611600600600600600610605608608040440000200200E416026204004000006\n\t006006006004002000000000000000000000000000FF88180000018018008010018018018018018000018000006006004006\n\t006006006006006006000000000004004000000000004000000006006004004004002000002000000000000000000004FF06\n\tA3000001C01800801001801801801A0180000180000060068060060068060060060060060000048000040048060060070048\n\t04005006806005005004803001002000000000000000000000FF4DCA000041800402A498018018018018018020018000006000634040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AA44E0060060\n\t200660C0000000002000000000000000000000FFCCE1000001C01A00801005801C0380180380000380000160070068070064\n\t070168068064A6400804D00C04554001800006C0008808820608600400C002804000004000000000000000000000FF41F400\n\t0001001809801229A01809801849A04201800020E2A6006806006086036806006886020804200C2419440602E00E04400500\n\t4006006004206004864000000000000000000000000000FFC17F000001800410C00851811811801A118001518100C964460C\n\t610655654E4462571060064480C080004AA060000C05110008B400880680604444448600200000400000000000000000000400e34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010640644700\n\t6116046026000000800C07006400006840C0200280220000600082F423004000004000000000000000000000FF3486000001\n\t80140080180180180B801801800001800000600602000600600600600780608600002910140600280600100720288708F000\n\t086001006003000000004000000000000000000000FF6250000001A01000200803801801801803800003800080F006000007\n\t0074078160060062062002804000034CF00000000000680AC46006806000006000004000002000000000000000000000FF43\n\tE200000180100000080180181180190180402980A008600F0C00070AE00E20E22608F0062887F000000E20E00E286286026800134040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2300020D4318\n\t82AB1300A09A81A44A01A88341800082609692700688600E0C680E087246000C404808448C0808028800020AA5294C089468\n\t10A5294AB04200A04000000000000000000000FF2FFA000121900030000423C05C15801CA1C204038000286A0621622EA26A\n\t4621620600610E00001003031121420640023000C00802188620604008220204C090084000000000000000000000FF6F2D00\n\t0001A00000800001801801801801800001800000600600600600600600600600600600000000000400000600600600400000\n\t0006006000002800000000000000000000000000000000FFAA840000014014000018018118018018C180610180000060060400934040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600204204000\n\t2002040400000000000000000000000000FF701700000002010044800194B800033900011841800000000000422018002009\n\t850659020000050804000000000031600000440447400E080020800000100208880000000000000000000000FFDAF3000080\n\t0800640101A00000420040000201800001600008008000000E08800050800408000002488400090100006000831020080197\n\t220012400410288000100000000000000000000000FFFC7C000027051A1A0010008018018008019C003180000B6886026006\n\t02604600600600602600002022008404464080E54040020020800000600038200A404000004000000000000000000000FFC500534040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08602608E086\n\t08640E00021040000E00E146804106004154204116026010406054026400546000000000000000000000FF6A15000430C0AD\n\t20D48C42D40C00C04C08D04C3080002022032A3002003C0280322A40B002001100031223043202093422B4A4030AB0021030\n\t218C3C0330A001002000000000000000000000FF079F0402102092811842002042882002B020C2020000800A00A808092008\n\t01320A08000890000810810840A00801020821148904900A009008080692E0830880640000000000000000000000FF89DD00\n\t01489048000218468008008408008008008000102C0255640300200300200300200200020000023A02A00B00020B0020DA0000d34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08800880A00A\n\tA0AA0A80040AA08008A0A80000000AA82002A82A82A82A82A8000080000000040200200280888B803B00202302A88400002A\n\t82A83802A82A8000000000000000000000FF4292000204A44A04A00A00A02A44A00A20A00A02800081200280300280280280\n\t2802802C0200080140080210A84204202280A80A90A802402800802802803000802000000000000000000000FFECDD000228\n\t20120920120020030820020A2402000000B450048AD004804004004800004834000C010D08C8820810204808004D05004800\n\t954880000004835000804000000000000000000000FF79F90400858C100D005101805841851881851901800010E00601440600334040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800002000000\n\t220000000000000000000000000000FFC9D00000080880000AA0AC0A00AA0A40020880A800002A8AA82A8AA82A82A82A82A8\n\t0002200002002C84A02080014A82483402C04802A82000002A82A82A82A82A8000000000000000000000FFD1910002143503\n\t083543543501303543403523500000CD0550CD0D50550D51550D50800A88000C00A90D50520C81350410C40A88C40D302909\n\t00D50D50810D50D50000000000000000000000FF6180000C0444050040040040000040043044440200010000010000000010\n\t01001001001110001001001009941520001081009001029001101401001000001000000000000000000000000000FF13890000b34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008048008010\n\t10000A0142CB00C0CA40004C0CD308810C0800884800800800004804000000000000000000000000FF5D87000032810B0480\n\t0840800801814808820840800000280200280200200200200200200200000010204A08208AC4202200203201204201200000\n\t2002802002002000000000000000000000FFBAD20001400860740AA0800944AA89010088A08200002A82A82A82A92A82A82A\n\t82A80002A00000000000000200100880800002102002882702002A82A92A82A82A8000000000000000000000FF93A30008C0\n\t002022000000004400000014000002000000080000000100000000000000002000000000000100804800104000004008000000734040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (504420400000\n\t00001400002000400000010010010050010010890004C1241000001001200021018641041001421141000001000001001001\n\t189001000000000000000000000000FF6585400400C00C00C00840800800900800808800800100322300300300300B082103\n\t01302A541003302343002113003523143403402003442803123003043003002000000000000000000000FF1B7D0000018018\n\t45801801801801001821801801800000E00600411648650620E00620620600002001401654600610C00400E00E0060460061\n\t0000E22620E006006000000000000000000000FFAB8800030024000820020A2522002202C22002080000800004804004805000f34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (102284000880\n\t06406000000000000000000000FFF87F0008000080800CC01008801000000002000000800201001004080000000004000001\n\t001100000000000001300161000402804404460A04880502003202A0028000000000000000000000FF7AED00000100000400\n\t0021801800081800003801800000C0000041100002004082260042040A00400901082800080563043000A000000600000008\n\t8440220000000000000000000000000000FF91D6000000882854800800800C0A000C00808840800000262200200228200208\n\t210212A02A2001001426020620A208042200A20A312022222080022142000002002000100000000000000000FF6385400C00000b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600400\n\t000000000A00602640604C086088100026006000402012040006056000000000000000000000FF6AA8000001805101113041\n\t849401801C01801805000000600600621600600600608400E0040000801302060060A2000304016212102006146100000100\n\t400546016000080000000000000000FFB83D00080001380180103082100180882184B8CB010000600620E006006206086466\n\t00C00410000000E00001E01400000028E10E40648000E400202042048006246000000000000000000000FFDD3D0000010010\n\t4D821000901011810841815911000004450630E00600620008600610410400800000600404600000E0004A60060361200170008b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01C0A8058010\n\t8180B88180100100000040060000060060060060060040040000100062060162440002061000022020060060001062460240\n\t06046000000000000000000000FF6724200241A818018808AB8AA1918AB9418AA0AA00002AE2AE9002AE2AE2AC2AE2AE2AC2\n\tAE000000004204216002088012324A30B202882AE00002018021C006206000000000000000000000FF019E000001851091A4\n\t08018000438018B180100000000060060900060060060060060040040008400061440CE30804630200C00200A00000680010\n\t8440104006106000000000000000000000FF558700013580502500D001801009801805800801000000600644600600600200004b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600602600600\n\t6000000000000000000004FF45A9000C11841C40841801800A05801A01801000800000400601600600600600600600200600\n\t100000210000645200620400E00600E006006800916446144006104000000000000000000000FF40A0000555325490941951\n\t95480B94180D9551548000554556D4E556556556556556552556000004002044406108550140426C8688E516556404456096\n\t514006294000000000000000000000FF5D3D000083A8B093C8C8AB8AB0218AB80B8AA0AB00002AE2AEC202AE2AE2AE2AE2AC\n\t2AC2AC00002000424A3460862AE0A6220320A202AE2AE00044600E20400622E000000000000000000000FF287B400001809200cb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002112000320\n\t00802600622200600C08E10440C04600610405601602E006136000000000000000000000FF03DA000001804841A0180B8008\n\t45823811800000800000600600600600600600600600200200001000010644E2C020004C316054244026006C040162064860\n\t06104000000000000000000004FF2BC3000201A4108C849841801889811A8580000180000060069160060060060060060060\n\t0400080000004C00600E046104004504804006006004106136016006456000000000000000000000FF64280000AB88924488\n\t38818ABA418818618AA0AB80002AE2AE2262AE2AE2AC2AE2AA2AE2AC0010000003141C60040882100300540CC2CE2AF004A2002b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180180B80\n\t182B822001800000600600600600600E00040605601000011005401600601624602400401611004600640001600400600600\n\t0000000000000000000000FF85480000038040C38A98AB8A98358AB85588C0A980000042AE00E2AE2AE0042AE00222200000\n\t000001420E2AE0462AE2A431400402428E2AE0000C60262062AE006000000000000000000000FF5AB1000001812821803801\n\t8018018018A1820005800040400608400600602600601611242000000454410600610C00000402024C084006006004406486\n\t106006404000000000000000000000FF2EF20000D18A080980180180489580181580200080000CE00644600600630E00632600ab4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2242AE2A8000\n\t000000000000000000FF9C67000902089001001C00803941A0088180000380000B600648E0060060CE004026006022000000\n\t32000E00620000000E0044040000060040040040C0084006228000000000000000000004FF52610001200880CB88D8AB8AD9\n\t418C9801A880A380002AE2AE2242AE2AE0C62A808A2862200002002004062AE2A608E1064342A622428E2AE00422622C2AC2\n\tAE2A8000000000000000000000FF2129000048041912935B54D51801B54801D30351800020655604655655640655531652E4\n\t880004A60045265561083304C04240CC4A8556554106294210456556100000000000000000000000FF60F180001004180004006b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (860B00042060\n\t3408843040820600F41714000700000404400E056006000000000000000000000000FF7C990008D284002580080920B89581\n\t101584200980000060060060060061360023260060140003100541240044460060CF04E1270D402600040011500C10400600\n\t0000000000000000000000FF1D9E000001000400045A44041801A020A1D10445800000680608700600620680101611308400\n\t0000086214004108001200304016000006002005026126014807000000000000000000000004FF915E00000508F088888881\n\t2818218A510180049180002AE2AE33E2AE2AE4062AB0462223240000003041402AC0062AE41410420620028E2AA00430630400eb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (803801803801\n\t800001804080600600080600602EB0000400641000841003222840425610000424000600602080220004600A04C004000000\n\t000000000000000000FFF5A7800001905048801801E01801805801880401800000600700000600601600E086006014000208\n\t140406002000020101022086006056006400006084006006000000000000000000000000FF422380080080040AC01D41A058\n\t01C01801C80201804000705E000C1F00760710F286066C0460000001000644218612680140820E82600E0060010068C40070\n\t07000000000000000000000000FF29F0000002800002201C00001801C00001C00001800100700600710790784740120B0030001b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000000000\n\t00000000000000FFDCC100000180C00C819841C01821AA9829801311800040640600620600E00E00E08E0040060002002160\n\tC6006044100606002006200006022200012006002002180000000000000000000000FFBF7700000180204080148980180B80\n\t180188B0A980802062460065061060862860162AC30634000050C0021FE00669E58608030612020600200208A0C402220A00\n\t0000000000000000000000FF7CDB800001801082881A21803801A03883C40405800000E8C680800680700600522680702000\n\t000000203420402204600500B0CE90A15010210002602220C004000040000000000000000000FF692F8000048820008008A1009b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008050000000\n\t048840604004000600C006400000108080008288000000000000000000000000FF5623800020040010000024000094642014\n\t00060000000000002000000000000003200002400000000280C8030020006008400006080026088080020228000020000000\n\t000000000000000000FFE851000000808008801310A03815C048A1B05441800001200600E006006006200A052AC406400000\n\t0060842C000041610600E08600805008208002202640E006000020000000000000000000FF9F79000000800100900C01C018\n\t418C9815E3100381000061460064060160960938D60060460004004040100140000200061062565243000424000820860204005b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (408C88008AA8\n\tAA80002AAAAA222AAA2AA2AA2020AA0222220004001222A222242228AA220222AA2222AB1120800A213200A02A0000000000\n\t00000000000000FF335901042909000804804000014022A0804002000000A000008800010000010110008800000004000084\n\t208400000000C002800040C000040000080208211280000000000000000000000000FFF88000008009098191CC888AA82008\n\tC9008AA8AA80002AA2AA1062AA2AA2AA0F2002B0219A0002624022123920020A828259A2AA32228A4220026024022A040200\n\t0000000000000000000000FF6C4000000C00D0440C4001C018000018A020180180000040000CC0000000004088161560000000db4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF1DD1800000C0088482AC00EAA8358008548888AA80010022AA2322AB2AA2AA18200320221200020020208200\n\tA4220AA4022022AA04228A22200022202200A202000000000000000000000000FFF0BE800A0B04001100020420000A40002A\n\t400400000080080500C805004005081400C1100400010000C00100009004489000000000C0010440020100004C5080000000\n\t000000000000000000FF5A179001038458C1103913955801501801D55D5580000D755744555655755644735624ECC4000110\n\t52408E48E12E53400E5065571045565142024561260A602E000000000000000000000000FFF59A0000A0082822820CA8AAA9003b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200801800000\n\t000000200B00200010000000000000000000000000000000000000000000FF16750000000000200000000100000000000002\n\t000000000020000080000400800000C00000000110801EA86888004010000001000002000405000000010000000000000000\n\t00000000000000FFD3440100004C00401000A400009422A01440020000001490008010000000000293208000300000000C00\n\t302404002002501500014D00401080000003000200C8000000000000000000000000FFA2D610013201401400041000000010\n\t00A004400000014000000880010008004000101500800001100082000801080001000000000000000002000900084800000000bb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5801801C0180\n\t4001615632605654E0C712640604650640000100624600700603400690451701500E050001046D4541640601600000000000\n\t0000000000FF83DB008000000040002000001001001001002001000044580400590000400000400508028000022040411053\n\t800C084001C04800584C00000028004004804000004000000000000000000000FFAB2D000030100800A00C00800810C02800\n\t800800802000A1120820322C204208240204348240000000200200200205200208201308A00203000102234220A402012000\n\t000000000000000000FF500F0000000000002002000000000000000000000000420000440000008080040000000800000000007b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF9A4B000000000800800820808820800820800802800000A00200200200200200280A08208201008000284280200A\n\t22800300A00200A802020280002002000802002000000000000000000000FFEA400080000000000000001000000000000024\n\t0000000400000000100000000000000400200004288000000008000000800000000000010008300000010000000040000000\n\t00000000000000FFA6B8000000000800804820880820800820800C02800002B00200200A00241A00300A42243A0080000025\n\tBB5D200212A08200B10210B183000003002002003062002000000000000000000000FF406E000050101A01801801801811C000fb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000011171100\n\t444C002001120000040115608204420402E000000000000000000000FF551E00000000900100100101580188980180800180\n\t0024620610600E00620400600600000000000000602400400600601400008610000000001000602200410640600000000000\n\t0000000000FF2796000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000006000000006000006000000000000000000000000000000000000000000FFF72D000000001200000000000000000000\n\t001000000000100000000000000400000000000000000080000000080000680400480600400600080080080000000000000000074040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (810001808012\n\t601710600610608402700602700C20040800600600F08E00700E3020460A200000020108E002024306036000000000000000\n\t000000FFABD100000400D024001901841A018818418040098000206A6600E08C00E20420E006C87006100800906880000046\n\t08E12442C086404026040008066823801006216000000000000000000000FFB6470A0080001041203801801A018018218000\n\t01810010685601610411610441600694400600080080612461400600080001400104C2468000000068820040060060000000\n\t00000000000000FFEE5C120490001200005801821801801821800011800000600700680600600404700600600A200408007000874040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF1D8400000000100D801941DC381980199B800403800000600610E0260AE00C08E00E027106A0050A1473AE4061D71860\n\t604060465CE886458000806023248002006000000000000000000000FF091E00008402508180981000180180180380400180\n\t000060C601600605601413600640C00510801000600600600700110008600081610600000304680340000200E00000000000\n\t0000000000FF4059000308040301811849801801801801800401800000608708680600600602600610F10A00828002700221\n\t200E200006102020822C00C00000007002124807006000000000000000000000FFC25000001000000180180085580181180100474040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (208600E03601\n\t4A0600C0062284082A6006402506006000000000000000000004FF7763000010011801891801B01A01847C51801801800010\n\t604610E01640E00441641E08484200024400F00600681700000260891060080600020480E51620E086006000000000000000\n\t000004FF26DE000020020800D01801001801801801801805800000600680E006016406006046004000000000016024014807\n\t046C0600402610400600000000E004010006816000000000000000000000FF6470000008000809801E01A05801801E418018\n\t05800000780600602608600600600E0A401220000000622C00C806400006000000800C06000004006040094006006000000000c74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (838000107446\n\t00683700600041602E80480E008045286206C0711604005600450080C0262D8005D0E90408200201E0000000000000000000\n\t00FF3C6500004221080480180080182980DE95803801800000E026006086206002246006456421A0000080E84024C02F4162\n\t9612404E20520E04000010784F842012006000000000000000000004FF3952000030020801809800881901851941801C0380\n\t0000F00650680720620210622601614640000012604402C00701020600404809400620000C02620C00220200600000000000\n\t0000000004FF9464000000001E01801801801881E09881801A018000016207A0680600600410600610C8822004000C6007C200274040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000004FF\n\tB067000003801801821801801801811A15A09801800001604600600680600620600081240620000409080684600400001610\n\t400120000600C00500F044082006008000000000000000000000FFEF0B000041851835801C01801841805841A01C85810000\n\t6006806146A060168560403400C601080042042E2068C701650603482E03444E526C8010601680200E000000000000000000\n\t000000FFA02A0000002019A9801C0100181180190180DC01808000600600600600600800F01608409000000002698E016096\n\t40600600C006024006000280006006042002006000000000000000000000FFB303000000031A01821801C01C01801831801800a74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (50004E000148\n\t800206046004046016006006000000000000000000000004FF52D10000018018018018010018018018098019018000426006\n\t42640648610604610C00404644004C20602E00E0C604E0060CC0060000060060000062060020060000000000000000000000\n\t04FF939E00000180180180180180180180180180180180000060060060060060060060020020060000040000040040040000\n\t06004000006006004004004004002006000000000000000000000004FFC221000001801A0180180180180180180180180180\n\t000060068068060060068070020010060008000000000008060060060050060060060068040040070020060000000000000000674040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002A622626E1\n\tCE2AE0A62CE02C2A42A620842820C02E0468AF2860A882600F004006046000006006800006000000000000000000000000FF\n\tB5DA000201801801809C01001A01C01A01901801900008600700E006106406006006A0680E04000400600400400504000600\n\t0000006006004004806804004006800000000000000000000000FFAF390002018018C1A01829001801809A21889821800000\n\t640608700600600E0268868448060B000401600418C00600E10208C08600600660400482680C800006800000000000000000\n\t000000FFD234000001801B01801851001D51851941911851804009605611609605603650E02449651610000400700680601400e74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF84EF\n\t000001801841801A80801951C41801800001804081701600648700700602680401481E000000004006026005046006002047\n\t004400046000004406004806000000000000000000000000FF6ED60000018018018118008018018018019000018001086006\n\t0260260060060070060040060002008040020028060008068028000040000260000060060040060000000000000000000000\n\t00FF7DED000001801801901A00801801801801800401900000600680E8060874060068044060060400000048060060040400\n\t04007001000006006000004006800006000000000000000000000000FFC6B7000001801801D01900801801C018898000898000174040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4C9080060060\n\t0800200008E00601C0C6000000000000000000000000FF716F000431A25A81C918B592D8C9AC1C81A0A411800085710E8065\n\t168870B708ECD490D40E000800804800C2884C4208081488008A6800A2288088E80E824206200000000000000000000000FF\n\t2080020005801C2904580180180180182D880341800020600642E0060462062260040441260001002CC34510420600822420\n\t40C001608E10A00022624680C12E120000000000000000000000FF5C71000001801801001A01E01801A01801800001800000\n\t680600600680600780600400480600000080600180000680680000400600600780200000600600080600000000000000000000974040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200282208B00\n\t200200200208200200000000234210212A40000304200208209200A000002002040806010000000000000000000000FF4A89\n\t00010000182012400200010040000A001DA00001000000A000005A02A06010840244580000805240200404010260046A4027\n\t0004064C0000220628020238880000000000000000000000FFCC8A00000E0020080003142002204000600000000001000080\n\t009200000418088028400000000400298010008001206400000196578006230000000100100C000200000000000000000000\n\t00FF733A00002184180589982982188588198188A009800000E0060068060060061060040140860001000040840B400490E100574040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFBC3C0001\n\t21805805833815001881901801901A81800090640600600608640610600600600E00040081608E0AE406804426A0400604E0\n\t1640601000608650E00E010000000000000000000000FFC9CD000402D40D00D00900E00A14840D40C40C0080000030020022\n\t0240300B41382B51344200110950304340310A4830820A30CB303203153001A0B413042242820000000000000000000000FF\n\t9AD10000403043802422802824001002003400000000100C08000C01000800830250908A20000811000800E00A10000A2100\n\t0840000800100891410810C00800240000000000000000000000FF7BB1020001820800801C01808C1886080080080080002200d74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100100100080\n\t1001001211011020800000000000000000000000FF8F3B0008000A80880800000AA0AA0AA0AA0A80AA00002A8AA82A82002A\n\t81102A82A80001800000002A8A082002A8888280220088A282880000002A80802482102A8000000000000000000000FFAF5E\n\t000400A00800A30D10A00A00C00A00A04C00800080200280308300320280280281300200081080210288280200282A802802\n\t002802002801002C2A902802000000000000000000000000FFE2890000012022442032250010012014012000010000005004\n\t80482C804935004000B20C2C00080000084084900022480008CC40880840000800000800844954000000000000000000000000374040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800080000000\n\t0000000000100010100008081000010000B0000001100001000000000080010000000000000000000000000000FF01680000\n\t000880000AA12A2AA0AA0AA0AA0AA0AA00002A82A8AA82A82A82A02A8AA82002080000082A80084802A80A80103284A83202\n\tA80000002A80000802882A8000000000000000000000FF03030002003501522322841543543543543543540000550550550C\n\t28D50A20D50D50CD0A40000000D504C0C50D50350C00D50D50448D50000800D50C28C80B41550000000000000000000000FF\n\t917F000C0042040040040000040000040040040000000000000000000010090000011290C00010000010010510002010010000b74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A86900020121\n\t04004004412012002014002004010000804004804004804915000000808A0C000810000A8D088800224801128A4154482080\n\t48010051008C4800004000000000000000000000FFB569000000820808000814800800800800804800800000280200280200\n\t200200200234200200000000202202200280202A40200200A00200200000222200A132002000000000000000000000FFABE3\n\t0000000861F60AA0800AA0AA4AA0AA0A80AA00012A92A82A92A92A82202A8AA80000A00000002A85402002A90887C0000088\n\t0102890000002A81486402002A8000000000000000000000FFDC60000800004000100050200000000000000000000100100000774040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (63220222E000\n\t00A482468002116000000000000000000000FFA632400C010004004005804404004404000004020001001001001201021001\n\t509010031028001009021021001401230021208401040001401001001021001001000000000000000000000000FF9DCD4004\n\t04800C10400C00C80C82C00D00814C04800100B24300B0430230030134424430524410090432030030034224434020C32020\n\t1304B00100B4C3043013002000000000000000000000FF973400000180180402180180180180180188180180000060062863\n\t062060260260060064060884202860340B604608401600E006006406004040306006016006006000000000000000000000FF00f74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2602600E0040\n\t0408C00602000000400600008420600E08620E016040000000406080088406006000000000000000000000FFD01100080000\n\t0120024004008080004000040008004000040000014008800000000001000000000800020008000000623002000600030602\n\t02D0200048010120000080000000000000000000FFF04D000000001810000000100001040100003800000000000020012040\n\t002012404C00820031004050400814822009620000004600000E00402028020000000C000000000000000000000000FF4725\n\t000002800802020801820886810810888940800000A22208A00200200220220274201212020000224201240240000A012282000f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001801008\n\t000803801801801801000801800000600600600600600600635601600600000008604600E4864060060880460AE0260B0000\n\t0260A2008004006000000000000000000000FF627F0000018010000418018118518018058848018000006006106006116006\n\t00400422601608800000402650E20400000602200000609602048000621244004608E080000000000000000000FF25610008\n\t0180304000880D80382D81581308A80780C000640608600602600E0040060040060280101844062040840604460963884064\n\t280040500060C0080306066000000000000000000000FFEB400000018050800130118058818018018308A981000060060061008f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AF0B64002060\n\tA62042AD006000000000000000000000FFC62440000180100000180180180180180100100180000060060060060060060040\n\t0610400600030000429449200420001010200008E027006200006004084007006000000000000000000000FFB2020002AB8A\n\tA0862AB0898AB8AB8AB8AB0A90AB80002AE2AE2AE2AE2AE2AE2AC4040042AE00000000421C2840660883C422028830628860\n\t60000D66122742AC006000000000000000000000FF57FF200001800040001841801801801801005001800000600600600600\n\t60060040064A400600080025410404400C04602C002006006000802A00416008104006806000000000000000000000FFB4C4004f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E2AE2AE23423\n\t62AE00100422600E2242AC0C800020408820628E3210042AE2AE0062AC006000000000000000000004FF4F6C000A01800800\n\t40084180180180180180180180000060060060060060060060CE0AC00600080010600610420E006006106006006006004804\n\t086006105006006000000000000000000000FF883B0001559549545559539559559559559559558000556556556556556556\n\t5565464465560000044D6046020556110546256350226516448004556556234556006000000000000000000000FFF6A40000\n\tAB8AB0A80ABA8B8AB8AB8AB8AB0AB0AB80002AE2AE2AE2AE2AE2AE2AC0042042AE00000042C32424A0862AE2102284AE22E200cf4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018048000D08\n\t0180180180189182180180000060060060060060060C80A602C0060000820C80820C64CE0460D648444600600610C2060060\n\t160B62C4006000000000000000000000FF8622000001800800001A0580180180180180180180000060060060060060060001\n\t1611600600080408028210E00440048610C440026046888804006006106004806000000000000000000004FF2A2D00020180\n\t1800201821801801801801004801800000600600600600600600600600600600048001604600400602604C04400609600600\n\t0200006006456804006000000000000000000000FFE00A0004AB8AB8AA0AB0898AB8AB8AB8AB0A88AB80002AE2AE2AE2AE2A002f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620655602651\n\t4126550000000000000000000000FFB4D8800001021801881801801801801801811801800000600600600600600001600600\n\t4006000000008146006006206206056006006046026000006006006006000000000000000000000000FFC8390000AB8A9800\n\t0030AB8AB8AB8AB82308B8AB80002AE2AE2AE2AE2AE2AE00010C0842AE00000001022E20600648E34404C08E2AE28E220000\n\t2AE2862460042AE000000000000000000000FF27290000018018000018018018018018010018018000006006006006006006\n\t20040640600600040420000601600420000002400000604600000400604600600C006000000000000000000000FF4810000000af4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2262AE2AE2AE\n\t0000002202A45462AE0EE25620608E2AE2AE0060002AE2062262AE2A8000000000000000000000FF94260000018038018018\n\t01801800801823842801800000600600600600600000620613600600020440000E0160000000040860000060060060040063\n\t0E004416000000000000000000000004FF53380000AB88B8018258AB8AB8AA8AB8AB8A28AB80002AE2AE2AE2AE2AE2A82A62\n\tAE2AE2AE0004802A020E00E2AE08E0863064AE2AE28E28E2042AE32E32E2AE2A8000000000000000000004FF0BA9001155D5\n\t1801953955955955955911B11955800055655655655655655034E04E20455600010614054654635015040C20E55055653655006f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1881C0180180\n\t1C21801C01A00601800100608600632680700700602610700600000D000024016CC84304060060800260AE206004C0644604\n\t4006000000000000000000000000FF6C8B000800209801829801801801801801802001800080680600600600680608E00600\n\t600600000008801414E00620614E006247006006436004006016104006000000000000000000000000FF5FE4000001825801\n\t885801A01A01401C0185100180000060068060060060070070060040060003048000042060000008048D6000006006106404\n\t0060A6016007000000000000000000000004FF18AD0000AAC818018118AB8AB8AB8AB8ABC810AB80002AE2AE2AE2AE2AE2AE00ef4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (14E006006086\n\t040020000400000000000000FFB94C8000108019418018018018008018018008018000806806006487006504086006084884\n\t01010880820412E4460082174561000262C00060900A6406006006000000000000000000000000FF0CC58000016018218018\n\t01E01801C01801E01801800000F00792F80748E2B410780723600600840009000604600000100D2AE0204062060061000060\n\t0E207806000000000000000000000000FF84DF800001A01801801801C01A21C01C01C01C01800080E806E2E01F08E82D61F0\n\t0602E15E50036108050650700620680708662701E00600601134602E226007000000000000000000000000FF0D4B00041180001f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060460460100\n\t001004000464A028002405600000601040614800622E006004000240000000000000000000FF06B600000180188180180D80\n\t1805021881801021848010600E00600600600400600600608600000000020200600600000440600000650620600801620600\n\t6504000200000000000000000000FFC5B8000001C0180988982380980B801809A21003800008610618604640600600604640\n\t606658800000014242E1B60C602608608642609640602000602E00E204000000000000000000000000FFB246000301803801\n\tA45801801D00D13A01909A01820000600600600600680480600F024006000102100004106400406C9422E04620622800E082009f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000021\n\t8000000518000000000000000000000224000000400414000200000000000028246050000206000006000000000000400510\n\t000000000000000000000000FF0F7680002800000000000000011200000040200000000000000000000000900000001500C0\n\t000080000148000280006480000046000026000400000000108040000000000000000000000000FFE0D80001012058018D58\n\t41811D10011809D20801800000601600600600600400600E0041041000800000001160000064941061464460200160001260\n\t06016006020000000200000000000000FFEBF7000000C0191180181180180092590181084580800060061060060060040060005f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (565565568000\n\t00000000000000000000FF21F50000A8AAA8AA8AAAAA8AA8888AA8AAAA08AA80002AAAAA2AA2AA2AA0922AA2AA20A0220000\n\t008002222AA14208A02A2AA0AB2AA2CB2AA0002AA2AA082002000000000000000000000000FF379F08000200000000100000\n\t0012400000042400000100000100080080100000080000100000008000008000052800000000000000000000400100000000\n\t1000000000000000000000000000FFBBA0000006CAA8AA8AA8AB8AAC448AA8AAA848AA80002AA2AA2AA2AA2AA0022AA2AA04\n\t25020005000003022AA4120885022AA08A2AA28A2AA4002AA2AA422542000000000000000000000000FFDC8E00010000180000df4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000008000\n\t0008800028440000800000000041000000000000000000000000000000000000000000FF6EFC800040EAA8AA8AA8AA8AA880\n\t8AA8AA800CAA80012AA2AA2AA2AB2AB233AAB2AA2AB2AA0002000002222AA00208A2AA2AA08BAAA28A2AA001AAA2AA2AA2AA\n\t000000000000000000000000FFA5FB000C002000010012014014002010012104010001004805005005005421005004101010\n\t000000800010004000444000004400804000804001004004050811000000000000000000000000FFE624000289955D55D55D\n\t55F55F21D55D55C919558000557557557556556546D5655655655600020000044F5560063545575565565565575564005575003f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006002003002\n\t006000020000050200000000220000400000001800000000000200008100000020800010820100C000000004000004004000\n\t00000000000000000000FFE74F00000000022C20001000001000020000011000000000005000800000001008008400008004\n\t02028468691200000C40000100040240020002000800000040000000000000000000000000FFF2C108011200020000020040\n\t004A200000042000000080080000100100009000080000080000000000008000028000000000024000000000020000100000\n\t0000000000000000000000000000FF83FB00002000000020000000020000020031020000000000008000000010000000000000bf4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200200200000\n\t0000000000000000FF13E8000450001E09601801801801945941801A13800000610444600600600620740E00640740600252\n\t602E20628604541640735610690622C002457206006406C46000000000000000000000FF949E008000081041001001009021\n\t0090010000010000054C04004101C4400180400D2002800440E0214C0C11008000404C3288008406000040A1804004004004\n\t024000000000000000000000FF9BFA000248000800800800800C00C249208008108000002102222002002002002212002202\n\t24202050200280200204240AA8232210200280A000452002002002042000000000000000000000FF469F0000000000000000007f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000800006000000006000806000000000000000000000000000000000000000000FFF107000000000C00800810800808A008\n\t00800C88800000200280200200200200210200208200240200280A04A4022282220020020220020020020028060020260020\n\t00000000000000000000FFA3C700800000000140000000000020000000000000400101044808000000100C0840A500000401\n\t40040A000001400800084300A8000200000140000000000001020000000000000000000000FF93F600000010080480080081\n\t0840810800800800802000B88300200200300A03A0B200A40202200043A842DA22222AA00200202A00205A0020000030020000ff4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5821881C01B0\n\t0013800004600651680E00600440600680600C00E4B00060064800022004C6B460008C60210024A1006146106C2600600000\n\t0000000000000000FFE9C9000002005809801801801801809801800001800010602600620600600401640600444400600020\n\t602600004204600600642640E000042010006006046006006000000000000000000000FF2796000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000006000000006000006000000000000000000\n\t000000000000000000000000FF8ACB00000000000000000000000000000000100000000008040008000008040008008040040000c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000000000\n\t000000000000FF5EAD000000401800C01801843801811801801001800008600008600E00600400720602420C016348407007\n\tA460020060462044062140000022C0006006007006006000000000000000000000FF66CC008212005808C01945C818058A18\n\t3188504F800012601651602640600420F0060460240060004060A64400260268060B60260360068321082060AE2860060060\n\t00000000000000000000FF83AD0002000038008838018018218418418010018000006626A0E2460060040060060460048060\n\t00006F1E8C0002200A860060180861A601A000406016426226006000000000000000000000FFEBA4010000401801905801920080c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8400E0060142\n\t440001060064000068060A000404608600610788E000000000000000000000FFB37C018010485907C03945C4B86980781181\n\t141D80600069914071048060441060269C6004CAE02082E1275862363E605E5600464040660A60000260C610600608E00000\n\t0000000000000000FFC77300010000184181380180B901E0180182104180000D600001600520600402610700628508E04134\n\t684E046086408206010000030806216080806006006006006000000000000000000000FFD988000082001920809C09E41881\n\t881E43850001800003744000688600603612608600448EA0628008709600E08A0104A62844204240002020018060470860860040c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801A01801801\n\t8000906047A07807806004007A16006144027808086C26806C0484688620480610000E002004236006006006046000000000\n\t000000000004FFC2D0000020001819019801A01841821A0181182580000160271461060060048661460040A4006504016006\n\tA0627C0206260010A801800680206400E1B6026066026000000000000000000004FF31E1000042003801001A05801801821A\n\t09C00821800000640700620600604600600740600600600400610650400000602708E2CF0060060402000060468260060060\n\t00000000000000000000FFEF39000004301801201809801813881845802A018000006446906806006016006026006016046400c0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF2C77000000001881829805C01841C09811C01801880010622608E8060060810060872048A100640438696620E8\n\tA6200006DA022192100780400440E007207007026000000000000000000000FF6F7B000000003E4180581184584994594592\n\t0E21800045600E00600650602200600602621290640C00E816144802016B3600600608E00610600F40608E00600609600000\n\t0000000000000004FF79A4000002403801801C01805801C01801C0880580010164065264860060220062B6A0680202610C01\n\t6206104003000086016A0100681604420502600E807007006000000000000000000004FF26B1000000201801601A01805E010020c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600300400680\n\t6806004006804006006804006001004004806000000000000000000004FF8080200001A03800001805801809841800841825\n\t800040600682600600600280608680720608000680685608E846000107046800124026006004006000004000056000000000\n\t000000000000FF5B0F200001A0184004D81184380190D94190180188010D64061060063060C0800806C2404E02044C516006\n\tC26306A0E80E10E446414007086808236110804004906000000000000000000000FF6A5A000000001D01801803801841C018\n\t1D801803800108605403600600600000600600490003E02100600600620600644600C186204026006000026006406006006000a0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4D9458459001\n\t5460CE0B691614E103090512046D0402600401704D5160448000460224009050060060040470010060060060000000000000\n\t00000004FF804B00000000181000180180180180190180180180400064060064460060242000422060240062342862040060\n\t0032E10208A006024006046004206000004004006000000000000000000004FF529800000180180000180180180180180080\n\t1801800000600600600600600600600600600600000400600600400600000600400000400600600400600000400000600000\n\t0000000000000004FF712C000001801C00001801801801C018018018018000006006006806006006002806006006000004000060c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF400C000000801C000018118018018018098C1821882100629E0AE16629F4202AE02F2A520602D23804F2AE0AE02684\n\t60A40A6A0F080846076008024010004004046000000000000000000000FFE4A2000001001800209801811801811801D05881\n\t814000630600620600610E00A10F0060048072A480612C4CC00491000604081044680608600402400088E006006000000000\n\t000000000000FF177F00000120184A281821881801C2B8238038018000026826006286426884042284104004816004886104\n\t044004006006008816006006006014006000004004006000000000000000000000FF629C000000001C04101841905801855800e0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800002006000\n\t004006000006006002004000004004006000000000000000000000FFD3150000010018400018018058018019008418058000\n\t50620E006897006A0280E00600694480400042682C40E00455680680280604280002E00140400800E0020060000000000000\n\t00000000FF88AC00000100180060180180180180180090180180000060860070260070020000060060050040280071008060\n\t00021003002001400000086001004000006002026000000000000000000000FF7318000000801800011809809801A09801A4\n\t590180A0007006006C0600E109807116005006004500006006D46006088004046008022026006000024800104005006000000010c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (980180000460\n\t0C00640608600010810000414421C0408160040180940065042200464061008A600002400800602E12600000000000000000\n\t0000FFA4AC000241281908501C8980B889D03A2BC21B218000346D0D1074172D6D048C0822C0CAA4CB4800006A088208800B\n\t0940A10840CD680028682080C108806A06086000000000000000000000FFAC24020080C2182402180180180381188190B80B\n\t800001780642E106006040216A0E02601600443203608609002680000C0C409080210E04E0100242003560AE836000000000\n\t000000000000FFA38100000080180000180180180180180180180180000060060060068060040060060060060060020060020090c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF8147000000A80800000808A0880A80088885080080008220020022020021C220240200A08202202000A14210200280802A\n\t40A102102002302000040080322012402000000000000000000000FF5C6B0000004004822800402104001080010802280000\n\t2080C0E080C06000208A121C520209004208000000080040C9600409048E0504860080084000010800000080000000000000\n\t00000000FFD4D600000000000402000020260000000010040000008000000900000280000000000400201804100200004600\n\t209460901000062A8006400020000000448301800000000000000000000000FF98FB0000A1001800001981801811801901820050c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (10405000890C\n\t208B0800814902004000800001004000000000000000000000FF998B00002100180200182181180190180181180180000064\n\t262162260060C600600620610601641080E8A60AE14600C00654610610610652604082601040609650600000000000000000\n\t0000FF4C2E000400A00820500D00800A10C00D12D40840800044300300300340320BAA3B13143423503021003003203012D4\n\t334B00B423453403003011402C010A3802002000000000000000000000FF4B7F0200410200681004000000802822362020C2\n\t0000C80E00020808800E10440020A00C00400800800A8880090002084084082080080884085100961000088088000000000000d0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000100100000\n\t1001001001000001801001001201001001009048C21001101021041000101401001000001001000000000000000000000000\n\tFF03190008000AA08C0AA0AA0AA0AA0AA0AA0A80AA00002A80002A82002A84802A82A80800002A80002A82A8B002300A82A8\n\t2000C82002A80200002A82A82A8AA82A8000000000000000000000FF7980000000A00A42400C00800800C00C00C00A008001\n\t0028B2803103002A02802802002C0280280080280202A802003002842802802802B028008028010020028020000000000000\n\t00000000FF9E030000010012002012012010014014002032010001004C0080482D004850000000C30948800C0200400090090030c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF52\n\t9500080000000000000020040000000000020000000002D00000000000880000005200400002000000000000008200000080\n\t01028000208000000000001001000000000000000000000000FFA1FA0000000AA0D24AA0AA2AA2AA4AA0AA0202AA00002A82\n\t30AA82A82A83202A82A82A82282A80002A82A82A04008882A84104883002A82080002A82A92A82A82A800000000000000000\n\t0000FF59C00000003543303543541541543543543541540000D50800D50D30D50840D51550809490D50800D50D50C28CC051\n\t0D50D40D10500D30920900D50D50D50550550000000000000000000000FFFBCD00080000040000000020020000040000000000b0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400620640E48\n\t400601600000E106026006006000000000000000000000FF84E000000000022520120120100120120124B201000100480080\n\t100500491080080480508C800802800800894A40404804008820C0C840810802800800004804004000000000000000000000\n\tFFA0D70000000008108008008008008008008808008000002092002002002002002002002002002200002002002002022002\n\tB02402102002122000002002802002802000000000000000000000FF5DA20000006AA0800AA4AA0AA2AA0AA0AA5140AA0000\n\t2A83202A82A82A82302A92A82A83202A80002A82A82201888882A80600880302892402002A82A82A82A82A800000000000000070c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02202211200A\n\t28200212240248208200242801259204060214800210250204221200A000082012082002002000110000000000000000FF3E\n\t68400C0040040440040040048040040040040002010016010210010000090011890090210290810092711480292010611800\n\t61004001000001001001001105000000000000000000000000FFA1F3400400400C00C00C00C00D00C00C88C08C0082010030\n\t0310300B28241342305344B1235530C100B00320A40342340B00200300A40314280110301310300300200000000000000000\n\t0000FFB3EB00000004180102182180180580180180180180801460260364060260A611640608600E00621004630600602E0100f0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF499600\n\t0000001801115831821811801821815821880013600640E00600608400402610620E00C30000000000441210612600640620\n\t0090003040020014006006026000000000000000000000FF65090008001000220000001480080040400000C000000A804024\n\t04080880080080400000082300000000000880000160402280260001060000200101002001104400A0000000000000000000\n\tFF093200000000000200000000000200000000000001001000001082000205444942202400105044000200084C0000046210\n\t40040E514006120000008110020080000000000000000000000000FF87AA00000002080182086080080080088880C80480000008c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (012006422000\n\t0008000200060C6286006000000000000000000000FF62C4000014001000001801801801801801801801800000608E002006\n\t00630E4064262C60861040000020C00460124061260A042608804600600030A000206026006000000000000000000000FFC2\n\t1F00000008104402180180B801829801881809800000602600211615600600620621600604400000A2881460020200062020\n\t40020406006000000004216116006140088000000000000000FFBAB20008000018010AB80990380182D80188990D88000060\n\t0614648602609611618608E20640408000000001400A0106861561182042000000181B210418E006586000000000000000000088c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B62AC2AE2AE0\n\tAE00602E0AE2860840002AE22622624648E32620808E20628E2AE00040E0022360462AE000000000000000000000FFCC2040\n\t0000001A0080180180180180180980180180000068060040060062362B40260060060040000062260060160400AE00240088\n\tE006006000006002006CA6006000000000000000000000FF99B80002800AB8018AB8AB8AB8AB8AB8AB8AB8AB80002AE2042A\n\tC2AE2AE4044FE5860062764660022AC2062062860A82163004880062C82A800210000600E40E2AE000000000000000000000\n\tFFD485200040001801801801801801801801801801800000604400400600604400401601600E20C80000401608E04200600E0048c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF1C890000D0\n\t0AB8008AB8AB8AB8AB8AB8058AB8AB80002AE2AE2AA2AE2AE0040062062AE2AE2250002AC2062242280880A63240C820028E\n\t2AB0042AE0062AEA262AE000000000000000000004FF0CBB000804001A010018018018018018018018018000006006002006\n\t006006104006206006016800004114094090046006046026154006002800027000107096006000000000000000000000FF17\n\t60000504155C011559559559559558A19559558000556D5655255655610400649655655654E0045541145543245104064361\n\t10C2055655240455600455700E556000000000000000000000FF9BE00000A80AB8008AB8AB8AB8AB8AB8AB8AB8AB80002AE200c8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001080262C60\n\t0430E002006006006000000000000000000000FF4A7800000004182500180180180180180180180180000060060960060063\n\t140140060060060820400A60040201160060060040060040060160840260A8006006006000000000000000000004FF3D0000\n\t0004001C01001801801801801809801801800000600600600600651402E0C600600610300000601409010624000E00402000\n\t0046006A04006000006086006000000000000000000004FF85AF000028001800801801801801801923801801800000600600\n\t200600602628601600600600C0000041260040000064060942060D000600200400680200600E0060000000000000000000040028c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (65565562062D\n\t655655455014810444E4A4506546110556414510544516242104104402556554556000000000000000000000FF318B800000\n\t001801801801801801801800801801800000600410600600600400600600400001000010610C00E21604600600440600C006\n\t0C200200600E006004006000000000000000000000FF9DC10000000858818AB8AB8AB8AB8AB8AB8AB8AB80002AE28E2262AE\n\t2AE0040042AE2AE2AE00000020622E20823608E2AE0A40EE22028E0160000063122AE2AE2AE000000000000000000000FF9B\n\t1400000000B811801801801801801801801801800000604600600600602434600600600624830400E086100006220006414400a8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (DE0000000AB8\n\t968AB8AB8AB8AB8AB8AB8AB8AB80002AE2AC2462AE2AE2AE2AE2AE2AE2AC22601023422022610808E2AC30428E78428E2100\n\t043861062AC2AC2AE000000000000000000004FF09BA000000001809001801801801801800801801800000609600E0060060\n\tB600600600600020042008600C04C0062400060A400001404608000422C042004004006000000000000000000004FF6D6F00\n\t00000AB8C10AB8AB8AB8AB8AB8AA8AB8AB80002AE2AC20E2AE2AE2AE2AE2AE2AE2AE3202802262242A402628E2AE24C0AE04\n\t42AE2002042364262AC2AC2AE000000000000000000004FF9B790010001299459559559559559559541559558000556446540068c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (061600241900\n\t7087006805006000000000000000000000FFBF41000000401801421E03A01C01881801803C01802100600508728700600600\n\t7806806225026044814000044254409304400200026026206004904046806007806000000000000000000000FFA6E2000800\n\t001801001801801A01801801801801800000600480E00600600400600600600408628A114108104020026804034046046006\n\t14C402004316004006006000000000000000000000FFC6AF000000201848A01801801801A01A01C01C018001006804146006\n\t80700680600600480500E00000500000E28040000408000001404600000402F046004804006000000000000000000004FFCE00e8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006006406\n\t0044011042210B40260CE0022462C40B20561220800060401460420042A2A06210000000000000000000FF5E838000000018\n\t01801803801A0180180180380181208060C680642681640E03740650C22640C0201140260B64560088844520000000102021\n\t00086042004000006000000000000000000000FFA871800000001800801801E01801E01E01E01801808000602600E00602E0\n\t2430E20624C006204001486406306086000006026130002007806080006086006006006000000000000000000000FF801580\n\t0000401800C21C01C01A01A81C01A01C018001007104C0E047626C372471E7105016814019206A4601600626681E0160AE400018c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800180110\n\tB8018018819118C5801901830000E00610600620600204600650650401408020010604000210004400010000600000401000\n\tA024200002006000000000000000000000FFDB570000000018000439058018C5801803801811828000662404610600600600\n\t60060840044440C0002086000182000006144000042106004000002004202006016400000000000000000000FF0BB2000008\n\t00180002980380382388988182982980000060045A610620600612400624609426E008202006400102086406004486440266\n\t02040800A0840A200400E000000000000000000000FF2F0E000000201809B01C81801801841841883B01800000E0060068960098c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04000040211A\n\t0000022AA000000000000000000000FF3E7D00000000004000000000000000000200000000000004000000000000884B4000\n\t10049420C000008200148000446010004046220026200080200500228480000000000000000000000000FFB0F38000000000\n\t1400000000000000012000000000000001300000000002400000004480200A01200201280001100061001084060800060B00\n\t00130020080050000000000000000000000000FFBED900000000181100180180380184180194B841800000602600600E0060\n\t000042060040040842100A802408800222628401004E1064400260200C21061464C6206008000000000000000000FF53DA000058c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (565565565578\n\t0444E0904C654E55605653455640C15652E55640620044624E486956556000000000000000000000FF9F850000000AA8828A\n\tA8AA8AA8AA8AA8808AAAAA8000AAA0822AB2AAAAB2022822AA28A4420220803225223023222AB28A2A22AA08228A10A00002\n\t202200A3232AA000000000000000000000FFA4C0100000000029200200000400400400200000000000000000000000000100\n\t10008005488804000080000000800000000A0201000000110000090100848200000000000000000000000000FF9763000000\n\t0AA8C08AA8AA8AA8AA8AA8588AA8AA80002AA0522AA2AA2AA1420022AA00201250224028201224222208826222208A00A28A00d8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000A000000\n\t0000002000000002000000000000000000000130000000000410008000000008000210000001000200010000020200000508\n\t000020000000000000000000000000FF2BFA8800000AA8808AA8AAEAAEAA8AA8888AA8AA80002AA2AA2ABAAA2AA203AABAAA\n\t2AA08322200022A2222224020AA2AB00208A22228A0CA00022200200A003AAA000000000000000000000FFD5580008000010\n\t1120120140140140140240120100008044000048048050090510048410850104000100000100080048000140014300402041\n\t000884012A5009004000000000000000000000FF086E000000555903555D55B55955D55955D55D55800155655755655755650038c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000A2B4A00A0\n\t02002002000000000000000000FFB9350000000000000000000000000000000000000000800000000080000090010C008000\n\t00000002020020800008000888020000220400900002000800080000000000000000000000000000FF742B00000040000400\n\t200010000010000400400000000001000000100000000000000005000000004100002C840051000050001004044040000100\n\t0040000000000000000000000000000000FFAC7C000000400020400400000000000024400000000080000080000100000000\n\t00000010210805101001000900C02000002C8020100020400000090040540488000000000000000000000000FF22BE00000000b8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (30020E3D1A24\n\t234058342A4DA0400020820032F24025D3002280003002002002002002000000000000000000FFE559004045805901805841\n\t815004115941911901804024600604E10640615645625688C146004000046006057010114096D54507214206104000146554\n\t916006006006000000000000000000FF9E330200000002080080010010002030000080010000804004005800004404004000\n\tA048200A44A8000240700820004000005800244008004001800004088004000000000000000000000000FF48400020448048\n\t808008208128021128C0908880802044200205200240222224302A11212200220000200282200010A80251228301200280200078c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010014002010\n\t0020000100100000008000000000040010008000000040000040000040040000008068000040068040068000000000008000\n\t00000000000000000000000000FF1772000000A00802800800880A0008080280280080000020020020020020020020020828\n\t0250220000204A002000288082D06802026002002280802002002002002002000000000000000000FFFACA04000000001001\n\t0000000200000000000000110050008044010040091080100140004000000800900010020080080000028080000020000000\n\t1020110000000000000000000000000000FF9824000000800A00800C00C00800604800810800888128200222209220208A0000f8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (280310002600\n\t6004000000000000000000FF1858000001001001801101801800151801800001800002640E88E10600615600600620600600\n\t44480840844064800A081613420010C30001002010210200014680E006000000000000000000FFDFCE088021001001081001\n\t801800001809820001800008608600600E4060064060061000A62140000040240040000060060000C640001000001000202A\n\t002406006006000000000000000000FF27960000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000006000000006000006000000000000000000000000000000000000000000FFD2FD00000100100004c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (140080020040\n\t00C84404E08048020C02700040649020A001006482806006816004000000000000000000FF2B550000000000012000018018\n\t00421801840401800000600600E00620624602708420110009004800C00400612000680480A0264922A10020200060028062\n\t86016004000000000000000000FFFB5E0880210010058810818110040958598044D580009D63868D600E006086A072260160\n\t3621410010413420221081610E8808C691084E1000080828EA480146006004000000000000000000FFB33300000100100100\n\t1001801000209801200101800082600E00608600640E8465460808061042000948840060408A0006820A00800846808002000084c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0811B0092000\n\t18008018018A2042680640E0000060060060040420C08C4206007A0020C94000040E00800010040604200600440811200780\n\tD006000000000000000000FF29AC0000010210059A7007893094235853824191800110706F24601600701E40608411602129\n\t03003043042060308161003CEA0680601653200018710F08E206026004000000000000000000FF8EC8000001001001A21001\n\tA03000041883820045800000E10E00600610600600612400600840602040E02C026801300800C064214178C6002000807026\n\t4064C6047004000000000000000000FFE3FB0000000000010000118018304019018000018A2140600700600F0870072060450044c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002016004006\n\t000000000000000004FF5FD6000001801800801A01800A00609882883E03800000780600600080604EC06004012010004000\n\t004046800040406804000A2E000216006400016003806006106006000000000000000004FFFA410000098418608218418008\n\t4202583288184180006061868C60000061062261A4102008D845C04071200814800082181B008051810EBB620638E0C20862\n\t16086006000000000000000004FF624E020008800808840801800802021820C0180180000060060860008064068A60248021\n\t4000400002420610408000F406024086004006422010404500082506004006000000000000000000FF93A70000008408008000c4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0E0064000008\n\t0800400804601400033E400806016000087007006006047606000000000000000000FF9DF40000018098138A1889C0804000\n\t180082B803800120608708600008600E1060070320870AE4A404200080000042080000808088800789600400C08408610602\n\t4006000000000000000000FFE46B000000800851010841882A2810584CE018818480096206016000C460260C629600380640\n\t6200120D46024141C1620F8A4807A2489622E000007806012006006006000000000000000004FF1850020000840801000C41\n\tA0080001591080582580008060060460000065370060070820A620002040228680442000100601025048028600600E0044240024c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A00001200000\n\t0018018000006006006000806806806806804806006800802801006002806006800006004806806000007000006004006004\n\t000000000000000004FFC6B300000180184980184180500100104C0208438100012D060060000C40260460160440040D0004\n\t080106006906209006016200804006204004116082892000006000000000000000000000FFD1B20000018119018519098090\n\t48114000010809840012284608E000C00804906B0690480C20092082025604602E8064068C60460D488E1260000060020060\n\t04007004000000000000000000FFDC1E000001801885901C01D008004098008059298000426026006000006016006006082100a4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060000000\n\t00000000000000FF681E000001801840001911C15C51805854002D518280850326086500516055406526004C040244084048\n\t508164840008460060A0004A07026006146010846004006006000000000000000004FFA5A700000180180000180180180082\n\t180000080180404000164260400064041360064040B408C0400343000860442D600604600600604600600000600000600400\n\t6004000000000000000004FFCEC0000001801801801801800001001000001801800000600600600000200600600600400600\n\t0000002006006002000006000000004006004004006000002000006000000000000000000004FFAF63000001801801801C010064c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600840401205\n\t6006080016006200156806046000007806046006046004000000000000000000FF0489000001801800001801801801800821\n\t84040D8AA060322E2B652708E2002A606662F2AE62E43828420A10E20600602E4868AF406227826000006003506004006004\n\t000000000000000000FF6B14000001801880001C01A00A01801800000901A24080B04634604100443650600E934154004084\n\t48681685600410080E00040114C00604C004806006022096026002000000000000000000FF82E00000058018200018898088\n\t01820A022028A1B000002006006000004006006286854004C8400010600008600028601612001600600600400082680C002000e4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008008018000\n\t0180000020078060060060040060060060060040008040028068060060060000060020060060008060008040048060040000\n\t00000000000000FF2B29000005801800001801804851A05811800201800005610620450740605601680E0210068004000541\n\t4708614285600600680700000100E0009068062C6083006006000000000000000000FFFF86000001801800001E01A00E0180\n\t0801E0040180002060460064060060158870062000CF20628010600000600300000720600120000000600000600280601000\n\t6006000000000000000000FF0599000001801900001A01801801C01801820083842000E00612C0A7007422C0604708F004000014c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008000000000\n\t0000000000FF854A000161867800001801841835A0188180020180000060062042860062081262060203044040002240B600\n\t6582016006200006210608406000006806006006006006000000000000000000FF1B76000285A83AA0229901A8CAA1922A81\n\tA540958000843096B04A8680EA4028688E81690702C80884CC88C0E83200102ECB0820A0AA00C068002A630CC04C462B68C6\n\t000000000000000000FFA79D000021821800001849821801809C01C00001800051640602600E04680C046406B2024D004000\n\tB040220A6A824A03068000880C000E02600000604405411600600E000000000000000000FFB788000001801800001801A0180094c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (910E00820249\n\t480A201C090010C800860800884800E0042890C840000000000000000000FFA60500008080080080080082088080A800818C\n\t00800042200202200A04241280200228208204200044200304A0030000020220020200020020010620800422428021220000\n\t00000000000000FFA22F0000038018259098280100010000018018800000280280000116D350000D048940406002440008C0\n\t4C4800202260C080849F0400063000021006381388902B0408000000000000000000FFC05E0000000000000146900820005E\n\t40100620400000010408090000000140A01101000408008008000100200010906408400067080006000000E10100000000840054c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (130420200100\n\t00000004800800800000004804804811404820AA0900D54000004814000A00904800908800C248C4880000CD488000000000\n\t0000000000FF348D000101805841811A01841801805001911A018000A16C0600610E0AE28604E10624440642420000653604\n\t6006104406C0604E12600620600014608604E00600E226000000000000000000FF69B1000420D20D02D42848F08C148A0D08\n\tC20820800100300310B00340382A9024020831331030012B30022034B2A130430A350200B20314300040B40B503A320A3082\n\t000000000000000000FFC4CE0002003803C026044030800020030030040A000100880110080000802100080014881090080000d4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF87D30004104104204504004044004004044000000000801000001001801801001001101801101001010841001001\n\t841101281001001001101001001101101800001000000000000000000000FF2AE40000A80A80100A80AA1400000AA1340A80\n\tAA00002A8AA82A82A02A82A82A82308A02200800001000080000006A82202280A83202E82200000000002002A80102080000\n\t00000000000000FFAC4E000200A04C08A00A00A10A00A00C08C00A00800000200280280A00200280290A40A10283280080A2\n\t2280280200288290280280A802802800912C0A852002802842000000000000000000FF12E50002022002C4202001142000400034c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (081000000880\n\t380000880402882100003B02682002A8AA82A8000000000000000000FFC22500000400012000000001000000004000040000\n\t010000010000110010000010002488800480010004100C80010000A001000100800000800022080028800042104000000000\n\t0000000000FFB29F0000A20A20880820AA0A80000AA0A80AA4AA00002A82A82A82B02A82A82A82A80402A824000822149025\n\t00002882400282A83082A82200002202102482A8AA82A8000000000000000000FF90A3000350352204354354204200354200\n\t3541540000550D50550D40550550D504C1080450C80840449120C00800130C10D40B30440D10D4080089052884155090050800b4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (803801850000\n\tE00E01600642602E0060060840442060000A608404600640E50600E22E00401608E000206006006006006006000000000000\n\t000000FFFDFA00023422C2032102002002004002012030010000005004004800804804800804804814C00800884104810800\n\tC04400CA0C20AC48008048008110048A5004000804000000000000000000FF70FE000000800820824800800800800804800A\n\t00800000200200200A00200200200240A10203201000A2222A200204290200A00200A04214A0000021020120020020020000\n\t00000000000000FF73ED00008008008C0800AA0AA0000AA0A80A80AA0001AA82A9AA82A02A82A82A82A84B022009000032080074c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFE243000000800800002880800800800800020000808002208A00218220201206202210200202250044A5220020426000\n\t6200208250620200000050201A088492002002010000000000000000FFBF7000000000040000C40040000040040040040000\n\t2100110110840900910108128906110D1080A120104100066100100170810108000100000100150106101108100000000000\n\t0000000000FF78B5000000800C00800D00C00800C00C00C40C00802104300340210B0134030A34D320B21304A94941300340\n\t2003003053042003142403002811043013093103483002000000000000000000FF548100000580190182984184180180180100f4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000244805400\n\t82A813403810100000E08600044660E006000000000000000000FF61F5000001001008021020009810001921810003800000\n\tE0060860CE00600600405600400200502008600200010209600409021602000400500012E08E000016016006000000000000\n\t000000FFA38000000000002804002002A0220900080800040000008300000010050100488028020200080000000000008080\n\t0C62085200060080061202A00400002880C0000020000000000000000000FF7E6E0000038018818218210210010000018038\n\t0002000100004802060204D00000005144C05000080C008022400001629012022E02400E0880084203000000104040000000000cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018000046006\n\t40600E00640600600600800420480020E00400200240600600E0060C20041048008020964140070064060000000000000000\n\t00FF83BF000001001002001000043804005801802001800008E0060B600600E0260060062242A60AE0000A64CE0000960260\n\t0602020621004601000000422610030600414E000000000000000000FFB27800000100100000100000584410B81180200180\n\t0000621600600605610E336006284006286C00226206008022000206220140200022020CC020600630810600604600800000\n\t0000000000FF9F020000010010400010001C18080030A190A019800000610E08602600600600418624440220512008610200008cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t1C7C0000AB0AB0880AB0AB88988B8898A98AA0AB80002262AE2262B620E1162AE2AE04008640C00040650C2AC22E28E2AEA0\n\t608F14628E1440002AC4360042862AC086000000000000000000FF8EB8000001001002001001881901801801800001800000\n\t600600601608600600600604E0064240100065040044C240000602600189600200400000000610C0AE004086000000000000\n\t000000FFB0D00000AA0AA08C0AA0AB8898C98C90A98A80AB80002062AE1062A62A608E2AC2AE09080C0440600460042AA326\n\t0882AE3C64A84162C86240002AE10616406E2AE056000000000000000000FF84CD0000000000200000018018418210058000004cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (44600680E406\n\t1480060060000044A640602E004416000000000000000000FFB4090000AB8AB8C80AB8AB8898818008A80818AB80000062AE\n\t2AE2A00062062AC2AE4842AC0070043260002AE0A20882AE206088A0028A2AF0042AE0460060872AE0860000000000000000\n\t04FFB4B200000080082000080184580180400400180180000960060160001464260040063044301068000960400040040460\n\t0601002600400600C800004006414016804406000000000000000000FFDCA200015495491015495584D83593415215595580\n\t004D65565565404564D6554556084D5009600444E03055400C1505564885504405325540055562962444065562360000000000ccc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060060060\n\t080060064860061560320140040061020060124000060562000880021060044C4006036006414006000000000000000000FF\n\t500C00000080480180084180402180D000005801800000600600600000600605400600608010600000600E04A08604614E08\n\t00460040060260000100060060060A4006000000000000000004FF50AF00000080080380080182402B815000055801800022\n\t600600600052E0A60060062200000AE8140064CE0022100000061200200000220068040000160B6207004026000000000000\n\t000004FF185E0000018018200018018018018C0804001801800009600600600800601600400600C00420600008E000006004002cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004FF3A9E\n\t000551D51B15D51951914111815B503559558000556556556D4055255600655212251241600455244E416112350414454110\n\t4C453052E00443655640C5560D6556000000000000000000FFCD260000098018218518018010018438020018018000006006\n\t00600200200400400204A0280060000000160060060040040040060040040460000CE0061040060060060000000000000000\n\t00FFB5830000AD8AD8C98AB88B88808B8818AC0A98AB80002AE2AE2AE2A02AE2AE0042AE2162022640002AE22228622608E2\n\t0630608E2202AE20E0001042AE2862AE0042AE000000000000000000FFA4580000038018258018018400018218020018018000acc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008560404060\n\t4408600404E006116006006004000000000000000004FF235D0004A1CE188828188B8C988E8898A84A98AB80002AE2AE2AEA\n\tA02AE2AE2AC2AA0063042AC0002AC22420600408C2AC20408E0C408C6160000862AE2242AE2AE2AC000000000000000004FF\n\t2A0C000001801A018058058210438C180000080180000060060060120060064CE0062060220840040020801422400000A400\n\t444000C0000060040060060A4006406006000000000000000004FF427A0000C388B88B8838AC88B0C9889AA80AB8AB80002A\n\tE2AE2AE2B22AE2AE2AE2AE2862002AC0002A82C62AA2CE4AC2AC2AC2AE3142AC1060004062AE22C2AE2AE2AE000000000000006cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F04710F004D6\n\t48476AC636C22544C061C091500020470420C047060496800714406000046006090916206006000000000000000000FF0E1E\n\t000401C01C00409C00821800801C00001C01800000700680700200628704700308600600400500701402C02400C210206020\n\tB0600400600528648E102407406004000000000000000000FFDDED000011809800005840C058208018002058018001006006\n\t006002006804006002C0601480400000400410C23400400410440605420402E0004060060010060060040000000000000000\n\t00FF0616000405C05C24231C01841801C43C02001C01800000680600680B0020070040021560A600400480690C046100444000ecc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF87930004\n\t01C01C20281A00801881805CA182404180200271061068060001268068270021140062008149501085000144023024062422\n\t14000029000486102446C06000000000040000000000FF037A000081803880011800801C0180180181020180000060060062\n\t063100AE0041161024D4006020034108000104104B2A0024002020140000002C0486012416006004000000000000000000FF\n\tA3DA000001801800003801805C21801801E03003822000E00600E40580C0141160A204200F88E000046087C040022A508600\n\t0080000024046000006006020026006002000000000000000000FF2E8B000501C05D00401C61C23821C11C01A12401982080001cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620600611400\n\t0050080096002226406200000000020000000000FFA75E000401C01C48641800083900003801D00009904000600642601601\n\t600650C00600200440E4A000401448005030C04800E0884C600420A100002206302016016000080000000000000000FF1CF9\n\t000401C01808001901063800011A41800009880001610602610404E10628400208600400C000004004012008084004102008\n\t00244400808009800E00200E00621C080000000000000000FFE0FB000001801C8002D8AB08180001980BC88007840020E046\n\t3068AC02640600C00E4060047140A010420425206424402C4080D61801E464200000201624014600E0040000000000000000009cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AA882222022\n\t4022AA10200A22200000A0122426622AA23220A08A0222AA40200014A2AA4022AA2AE210000000000000000000FF426A0004\n\t01C01825A01801C4180180000380180000000000000000061104000540040484441100000444040040800040040804460080\n\t042C80004A0000400000000080000000000000000000FF395200000000000000004000422000060000400000000000000012\n\t280001104800005001000000004800A8128008006088020006500006000000000000130000000050000000000000000000FF\n\tE84A000201A01B00291C52401C00001C93A2C045800024600610702600204400404A10009400600000C4A400048000420020005cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (7C06000555D5\n\t5D15D55E0BC4584D955D519219558001556557D57546A0655755712645644E556001C4704551651615644440E1164D615655\n\t6000547556415556D56406000000000000000000FF45990000AA8AA88A8AA8AC88A8C88AA8A8AAAAAA80002AAAAA2AA22A2A\n\tA2CA10AAAA04242234A00022232228A0022AA22241228A4822AA0420002022AA0A22AA2AA2C2000000000000000000FFAC7C\n\t00040040040020004040848000040001200000008000000008101290000002108800800000000803088000404001080A0200\n\t8002000000000090000C08000008A8000000000000000000FF9B820000AA8AAC888AAA8A8C888E8AA8A8CA88AA80002AA2AA00dcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030200100000\n\t100000051000000440000000000000000000FF89230000000000240002080540100000021000000000800000000008400000\n\t800540020000000002000000000100001000010400000000030002028800000001000088000000000000000000FFB6BE0000\n\tAA8AA8C88AA920900C80EAA8ACE00EAA80002AB2AA2AA2A20022AA2AA00220322A2AA0002BA0022420020AB0022A20CA2820\n\tAA2020002022AA2822AB2AA002000000000000000000FFC02600040040042040040040020000140220020100010048050051\n\t0080100004080120809000000108800500009000008412004083000008800000900400D005005004000000000000000000FF003cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0200209300A0\n\t0A20301344200000200202A00200294300200282240A44220000210302280B002200000000000000000000FFAA3400000000\n\t00000000000000000000000002000000000A004001088000008208000088808802120000208000002008009004000800C000\n\t80024A0800D00400880020000000000000000000FF027A010000000000000000000000000010000040000000080081080000\n\t0000000840001400110100000401B80800000040008070040801800000000810000000000000000000000000000000FF6996\n\t00040040040020010250042200040005200000000008010008000B00000010080911000000010012A89284284004A800004000bcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010000000800\n\t800C00800800C0080282CC40800102200226200B202082002202C9200B40220808204A55A1820030020021D380A502002000\n\t003012003603002000000000000000000000FF443A000000001801901801801951941F558418018020416407545916006116\n\t056006C0C0944C4410006004056007406146894446147336256400506106C47416086400000000000000000000FF26060000\n\t08000008000000000000000001002000000000001000408480C008084010A0C004224021A000647210088800000040000002\n\t8D000228044000100004004040000000000000000000FFBCD80000000008008808008008B08C0AD2820A00802040A00A0A20007cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF061D00000000100100120100100120000000120000008000040000008000040010\n\t00004805004000000804000000000800004806000000000000000001004800000000000000000000000000FFA5F600000000\n\t0800800800800800800A08A00800800002200200481200200200204308220A04200840220280200A08200200200202A00A80\n\t2000002002002002802000000000000000000000FF0FC3000008000010000000000000000004250000000000000041008040\n\t8110080C000000000904A0080808000000000021000801000000000430001000000000000000000000000000000000FF42A800fcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60A640640400\n\t410C08420080608408E01407E40600400800208E80200000E00622660E006050000000000000000000FFAE52000000000040\n\t040021801801811801901A04800102600680600710E156016807509201280302006084916804800106040110917116106003\n\t416106D5685644E000000000000000000000FFFA88000000000001080001801809881821811888900000600600600E046006\n\t006000040050000000106404424526480026210006226246006200006006006006006000000000000000000000FF0CF50000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000002c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018080006\n\t01845815801891811A5180000060050000060A600690E0C710F0A34160A01060118260070060140825008028461401008065\n\t0700648700F000000000000000000000FF3F0500000000184000000180180180180180980388000060074002178160160072\n\t0720752700600010740020634C40600404208608200600200040608608F02620E028000000000000000000FF092800000001\n\t01012B08218018498CD8258018080000C044544440060A600720E0044A80042000804070040368061962A621C01672822688\n\t0210106004004007026000000000000000000000FF657D000000000201200201801801801A01A818800000026806404406000082c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000600100\n\t4487806080000000000000000000FF03CE000000009880800001801801801081800241000000200600000604600601600402\n\t214241200400410404000400600600008080600604600400700A007C06206000000000000000000000FFBE52000000001811\n\t010A21809851805865863A0381808EC44444260610618E10604E52280A082B4016C0A0806804936080A3646700005E100100\n\t70610D00400E207000000000000000000000FFD913000000001801000021E2B803841E0980B80B800131400E003806806016\n\t00609600E01610740040C04E0130040461094C601028000600200800720400409600E000000000000000000000FFEC1A00000042c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3062440A6142\n\t246A04006000800A26546256C04D010042368CC004096888084447206008000000000000000004FF5F9F0000000018018008\n\t8088180180130182020000002200C400209600620600600400A0062021201042048248040063042040068042060840040068\n\t0C10C02E506000000000000000000004FFC39B0000000018018004808818038010818000020000002004002086006006D061\n\t4494214708208449C2040A40440060D00E050010E056204004956106466086086090000000000000000004FFAC7500000000\n\t1C00800001801803841401C0009300000010069000060060060064068020028A240100400410440732600608400600C0064500c2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200380100080\n\t188D801829811809800102C00400600600600600600400A04210A48020401628400E04F02400420600401680440000600400\n\t4017806000000000000000000000FF69FE000000000001821081803803801801809801820000402410620608648700610503\n\t20A2002044C8C08E00000602620000500010C006004085046008414016086000000000000000000000FF31C6000040000100\n\tE01001881841803805945841800030400400402601600E006086207C0A2C72100064060042063060870C40060058960D4244\n\t096404105D16006000000000000000000004FF5302000000000000801001801801821C01841B11800044412400400E0060060022c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006004006006\n\t006000000000000000000004FF0B4F000000000001801A000018018018018018018000806006006006006806006004004806\n\t806000806806006002006006806806007000006804006006006006006000000000000000000004FF42460000200000018218\n\t01001A098058000458410000002002806006016106006086C06082042004006000A0600600200010600000E0000140840064\n\t0C106506806000000000000000000000FF14FA000000002105801881105AC180184B101809040053204680624608280E0060\n\t04854A0A20A08A50ED00906216517544826A06006880126822096006006006106000000000000000000000FFD0FE0000000000a2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2E2860008000\n\t0800684601600480420E80604680608000C000006000806006006000000000000000000000FF46CA00000000180181040180\n\t19518455041240011140CD21544144325064CE08E494C56A0833002E12E50142410E05280000680000E00101602604600600\n\t6007006000000000000000000004FF985B00000000180180000181180180104100000300000024040C410201600644604608\n\t610000008000601600420640454C406016006100006004006006006006006000000000000000000004FF8A18000000000001\n\t80180000180180180080180180000060060060060060060060060000060060040060060060020000060060000060000040040062c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001801801\n\t809800809A01950094480391688A8124AE8460061260040044C8047804D5400408A40102E800006000886200806002007006\n\t046000000000000000000000FF116F000000001800000001801801811C000218410000280A060A60B200E2EE2AE68646C68C\n\t62C0F00EE6BC05C20C22602005602E54E000056420006002006006406000000000000000000000FF11720000000018018002\n\t00801901A01000110001150014300451454201651654600410614080028600604050400CD1440600610080E0001040070060\n\t00806206826000000000000000000000FFDD5E000000001801808000809821A03021082243088002A0AC80D20AA82007006000e2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1204680C2860\n\t00000000000000000000FFE629000000000001800001801801801801001A0000000020060040058040060060060000060060\n\t00806004006002006006006006806000002000006802006005806000000000000000000000FF49E800000000180000000180\n\t1911841904881861804000480640200200600680620600000490400100600CC4410801210440688700600082E00004700200\n\t6206006000000000000000000000FF48C6000600001800000000801901801E00E01A018001804006403A4200600728600520\n\t42C520400000624500600040600400700052F801006000006002006006206000000000000000000000FFA1F10000000018000012c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010121002080\n\t0600008210100100410106820088230000A08008B00200820000000000000000000000FFFE35000000100145802002801801\n\t905A60845816800000602654608420000610600482000208201000E00400602002240602E006486400402200526002406004\n\t016000000000000000000000FF10A6000000200215A4A320A81A81A518A0201A2C0000812C4E90E90694E90642E80E029512\n\tD22820416C24A34A208AAA2F106910086140D12A00206C4228EC44046400000000000000000000FF117700000000C0018000\n\t0380180188380980980080004A6102C0421620600608628790100600E000006884004002203107C360400362080220500D610092c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (202802C02000\n\t842102000000910E108008009B08802809890006C8528C00801000900800C88A200008008009209408108909C08988090002\n\t40000000000000000000FF9025000000000800800800800804800A0080092080006A280200A00204210280200200A0020020\n\t00702182452442212082002003002210082001042633066423202000000000000000000000FF66EB00000004380981198001\n\t1811868318001808000000018C0906000084168402500C5010840000000064220004040058A800BE01804000802800000000\n\t0000480000000000000000000000FFDFB90000000000020000000000000820000080000000048000200008400000828000400052c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (300280200000\n\t0000000000000000FFDA9C00000022220232420020020022200120020A000080880C809001000800004AB090C004894B0082\n\t4320940A48950840014820925000950801004904885000004000000000000000000000FFE8FF000000121901901881801841\n\t84194900190B8000406494006006006206046116044004424000006826106016126126C0600E01601022600001630C006206\n\t216000000000000000000000FF733E020000410C44C08C00C08C14D04A04C4CC00800114A0034B340352B08A903023403D52\n\t09340928330325324320B40B01310220254110B0103430422CB002802020000000000000000000FFFF96040000218200328200d2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D50C80C81280\n\t800C08D10C88D40D10900550830900D50B09110D50D50000000000000000000000FFBB310008004004204025104004004004\n\t0040044400010110010000010010000011210000290894010015010290010211111490410518000010010015418010010008\n\t00000000000000000000FFE5850008000880A80100AA0AA0AA0882AA08A08000000400302002A82A82A82A80002202282200\n\t002408002101002402802300886102A80000022A80000002A82A8000000000000000000000FFDB8A000000200A00A08A00A0\n\t0A00A00800A20A208000CA2A8294300280280280280280288280300091201280A90280300A902C0300A000C02900802C32430032c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A0AA0AA0AA0C\n\tA09000003A02A82202A82A82A8AA80000209800400002A80500082A82104000000882002A92400022A80102A82A82A800000\n\t0000000000000000FF3DD8000800002004020000000000002200024032000000002000000000000000010801001000000201\n\t0028320020000020000020040800280002000040420000000800000000000000000000FF69540000000A81120880000AA0AA\n\t0AA0AA08C08000002202A82A92A82A82A8AA82104C8C004001002A80002802A82800202002882802A82882002A80002A82A8\n\t2A8000000000000000000000FF6D810000003503503043543543543501543103000000C90A80CD0D50D50D50D50C40D40CC000b2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (003002000000\n\t000000000000FFB4FC00002000980192B811801881811801001801900028602600621600620600630E216286206000006244\n\t22608608600400600608611613600000C00408600600E006000000000000000000FF286F0000002222002042102002002002\n\t0120040A0001010800808805000800000800088010D50C00800B24940800941414D10C210B4804800C008049448050048040\n\t04000000000000000000FFBCF7000000000824840884800800800800820840800000200208200200200200234AA022220020\n\t8000201220200200A14202200200200215200000240A002002002002000000000000000000FF6A5100000008C0880C80640A0072c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000A05204001\n\t40140044400086100108050000008000090000008000000000000000000000FFC90B00002000080082280080080480880090\n\t0900880018200200210220202A00A18A08212A00210801211202200200220206200203201209208004202200264200000200\n\t0000000000000000FFCA29400800008000008180000000000400000480000100900100108940020100002100120128100100\n\t9000008208009081018001001001201001081001005001001000000000000000000000FFB831400000000800800800800800\n\t800C00800C80800101300315308304204B45202314305308300915308200A43202B34344210302300340308108304301340300f2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8000C4021801\n\t93201082AE28610620608400C1042A442013E06208607213E20678260010602809601600000214A022036006000086000000\n\t000000000000FF17B6000000000100005800005815800000105901800000045604600648C104000004244016406000106102\n\t2262A600201000604E086006002080002402006446000086000000000000000000FFA13E0008000000000000400000000000\n\t4200204C10800000000204001100200400000004083002080004005000C00000883000860202803005000802800100002000\n\t00000000000000000000FF4E2C00000000180190180900188180100000180000004040200CC4000200064402004281040000000ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00000000FF9AF020000000080004180100080184284402080580000000160061064560040002060941061168000020441020\n\t1224200A00402600600602C800002402806006004006000000000000000000FFF76000000002280200582080180180011180\n\t183180001080060D620610600400604C2260120062000060962360C610A1240060060060062020800020B000610E00000600\n\t0000000000000000FF8EDF0000000008000018D4801801800081821853844001008648640600604403200408612202629000\n\tE20600600600208422610002628650A2000120C2046006400006000000000000000000FF71E900080000008006388A803809008ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60A85564B650\n\t4548556510556006542004550492556556554006000000000000000000FFEEFC0000000A88CC0898C98AB8AB8A802388D821\n\t00002B022CAA62060262AC2A802C00422A22C0002AA00422220A02E2462A808E2AE0061160802AA2012AE2A62AC006000000\n\t000000000000FF46A700000000204402181380180180000202584100002000040860060060040000040AC10200C000006204\n\t006006006006000000006006016200002041006006004006000000000000000000FFA4B600000008C0A80C988B8AA8AB8888\n\t018CA98580002202A621617E4142AC2A84861542202264802AA6040022025062022AC6C82AE0064840002AA1122AE2362AC0004ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C08210008000\n\t0305520001064860060060040960100142000060400060160000040040060060060060000061140060060060060000000000\n\t00000004FF1A250000000898A988D8218AB8AB8AB10088B0A88000200012A002261042AE2AA2AE4062903854062AE2002AE2\n\t260500002A80C82AE0062270062AE2262AE2AE2AE006000000000000000004FFBD0200080000100180380580180180291080\n\t1010800000010600000610600600410420610010488000615010E12600009400600600600604280000404000600600400600\n\t0000000000000000FFBEA520000015111191192115595595403091111480001284C64284CE4565565565560064464441045500cac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF700200000000180180188180080180000080101500000860160080064160064B208600C48602400414C08210C04C00\n\t60040880000060060C600410401400600614E006000000000000000000FFFB9B0000000310058018430008018348B5801021\n\t000000E14600000600600600401614605010E00000401600450410E094026026006006012000246344006006006006000000\n\t000000000004FFCD4400000002300380588D00080180001480100500000860060D001602E006006006226026026904002096\n\t0020823564D4006220006006112C04004004806006006006000000000000000004FF019F0000000018018418018018018010002ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (082016026224\n\t0102AC2AE2AE20000422E2862AC2AE22E2A8000000000000000004FF8FB5000000410555D55903D54D558558C35501428000\n\t44E44C5425560175444362A642200E5100041164D013601444A44448E1305565540820044065165505564445500000000000\n\t00000000FFCA19800000000001801801813801801801800023800001611400000600600600600400209400000400604E0460\n\tC640E10C4260040060060B2000106016004006006000000000000000000000FF9F620000000838A98AB8498AA8AB8800118A\n\tB08100002263062A02AE1A42BE00022420410624400024422222400422623420428E2AE2AE21600005E0042AE2AE2162AE0000aac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400080000861\n\t1400B0060068044460048004860040000068B022608804800008640400600600000500600400500708600000000000000000\n\t0004FF206C0000000A9AA98AB8C9889AAB8A19478B008980002262442B02AE2AEAAE1D62AC2A80462AC00401420241640218\n\t400430608C2AE2AE2000040062442AC2AE3262A8000000000000000004FFBA810008000A4001801811800801881800804010\n\t800010000400A006226004106016116420002002206006202524102104020400006004220006106026000006084000000000\n\t000000000004FFA7DF0000002AA0ABAAB88BAC18AB8CB808AC208980003202042A02AE2AE2AE2062AE2AE4042AA000326306006ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFDE80800800409A00201C01C01C01881C00C218008040447194015016C06C16C260155148052444004250500D408200E306\n\tE86244027006002001056087025106802000000000000000000000FFA68C000000609801801801C0DC01901A01E020248000\n\t1008262A220602600508E40700028E90602500500600500000400904048410680444600520610C8064070000000000000000\n\t00000000FF05FD000800001A05A018038018018058C1808045800000802600000680600680E0060010560060002CC00210C4\n\t424045348480240060040D40005560AC006006008000000000000000000000FFA2E7000000005801801A41C43C018118090000eac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (966461340A00\n\t4400E00A288000502000224086002000000000000000000000FF73F9800000001844001801C00C0180181088180002200040\n\t2630E00E1069140860160044102140011050A6203008032092A1632424600600610080829508203613224000000000000000\n\t0000FF551E800000201800001809813801809820A03844824010702C0B4106526056A0E3154D40040C641021421002204208\n\t602204608508600644200005000C000486802000000000000000000000FFAEB3800000001E00605811801801811840941810\n\t040000500600608608702404608602400640C00804E20010412832A246086005046006006000106007026006002000000000001ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0080A0000708\n\t620628682400E0080024002D414040610600042C4221002400C403600240600000010000604602A020000000000000000000\n\tFF7123000000000400001800405885801891E218200C4002804644C02E02F10C006004142010004400144052480104012030\n\t10840400601201412000240014E116102000000000000000000000FFC0C1000000000008001980003A918998C71218B58800\n\t02850600602600E02410E00400610000422000400808002600200400000440600210402001001040E0060024000000000000\n\t00000000FFA9A400000040040040582220980B00182110B81B80806402844266162274061060000A65900B40C02260420102009ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF39\n\t5E00000048C8A8CAACC8AAA8408AA90C8AA80480006004030022AA2AB0222AA14232208A06214046A00A3C24022222A229A2\n\tAA2AA0120480000822001422AA412000000000000000000000FFE4E9000000041A01801841801831C0182120188800009060\n\t3444600000010E00000010040420C00208044401402000000400000400040022000244810841000002800000000000000000\n\t0000FF092B80000040200440000200068200008400002200000482800880000002000002A800802008014040010004031008\n\t80100200060000C8080100000040120000280000000000000000000000FFCAB300000040024C401C24209C01A81801A13880005ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100C14000080\n\t4800414080550085400804145000000000000000000000FFD256900000731955955915C09D55D55D09F51855000144E55754\n\t755755755755624E4450C444E080557547416446016084526157D564D6446400446456326556444000000000000000000000\n\tFF56C7000000088AAAAAAC8A8AA8808AA8108AC80080000220924922AA2AA2822AA20A2322325020001122A220A08A2A2322\n\t2022AA2AAAA208200000224A00AAAA002000000000000000000000FFCA460000000020000000204C04002000220040800001\n\t000000808800000800000080008810080008000000100088520820008000000000088000088001000000089000000000000000dac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (048000800800\n\t0000010000400010210800000011010000100A09100C0000800108420200080108100800050000000000000000000000FFBE\n\t601000002400000004400C200000000020000800001000000080008010000005081502000080800004400B00804102000002\n\t00000000008000028000400000100000000000000000000000FFABEF810000088EA8EAAC888048AA8AA8A08AA8008000303A\n\tAA2A22AA2AA2AA2AA00230248B2220082AA01A24222200343220A4AA2AA22208200020232203B2AA20200000000000000000\n\t0000FF5F65800800440200200200400414400040400131000109404104080400505000400000490401000000000800004001003ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF3D6E0A\n\t00080008002008028028008A080285284480A008204200A80200240A0020D220228220A000002502112002A421028A22822A\n\t2C422024080020820A20A2002200000000000000000000FF2C8F000000000000200000000000008080000000000001010020\n\t04100081000000008000200804018A0020000000080C20200808008009800002000010000000208000000000000000000000\n\tFF89FD0100002000000000046106000000004001000000200400000400000010800000841100100140000000640000008D00\n\t000430800080580050860400008000000000000000000000000000FF198D01000000200400000240840020020C000144000100bac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008208010800\n\t000882000404000000000000000000000000000000FFE4F4010000018802000800820800800810A00B00800100200A00A4B2\n\tA022030220A304210360B4000AA00245308282B00A40A00300A00210200004200360200260A000000000000000000000FFD6\n\t4D140010401000001805805801951905855845814051412641741600E51700614E0074044960000C7D075160064D6305544D\n\t5655751620400080608615694600E200000000000000000000FF02C902000800100000800040040000000820020308000040\n\t04004008884000205800404B6D800608200AE888820828004420480100424010449104581400580040400000000000000000007ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF295500\n\t0000000000000001200001001400001000000080400000000400000480080500000080500080080000480000080400400080\n\t0004000800000000801000000000000000000000000000FFF332000000000802000802828A00800800A00800080000220A00\n\tA80208200200200200281610A0A008A00200210284A00200300200340220202880200200200200E000000000000000000000\n\tFFFC260400080010000080000000000002000000020000000000000940400408440940000440000012C204D0100210A8029000fac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFEEBF000000\n\t0002002E1001003A21200000A01800000002008708608692608624600600661C60248020601400082D20800401400A416026\n\t20200042600E106006416000000000000000000000FF9C1B000000001000001805801843801C01011D00000004030E0B6106\n\t046A16216116087020820130A254249004B42902202408C612704691000102610F006A06006420000000000000000000FF7B\n\t2000000000100008100100380180984480180000000080260060040060860060042261000060001060060280060201000800\n\t160061162004000160460260C6006000000000000000000000FF409B000000000000000000000000000000000000000000000006c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8230600E2060\n\t0000E2060870060D7000000000000000000000FF3A880000000018002018810010048019428B0CA3800000202E8262068060\n\tD62062CE027AC61281000160A608204EA800222022C181604B8060000062060068350A6000000000000000000000FFA47400\n\t0000001800001005001200801A228109010000002416016006106C1600610E0A60A704622002620C09208408054340B10212\n\tE106116001016046006446006040000000000000000000FF277E040004000010001801805A03108201001200000010A02642\n\t614401600602E006216004002408D84C26420A060640050B402160680A4122002161969A608421E2000000000000000000000086c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (601600710610\n\t600440604244000420600784400610211414400ED06006906000006016406042006000000000000000000000FFCCFE000002\n\t0010000011008018018018A10498C3000010001604780600600C0060048860528062048068040240148248A0810006026006\n\t006004007817A07052006000000000000000000000FFA0B7040000001810003801801800902001100A00000060A28640E546\n\t0161060069460D610F64216906500C52C6C491C0861E68400B6042016000066106206005006E00000000000000000000FF8F\n\t35000000000800003801802A02802205800800000000BAC780E00600682620720C806A0608A01030E2B5015904204806C0740046c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8C0400000010\n\t000018010818408018418358018001004006216086006CB6006106206012B2708003690600220608A005024C050070030060\n\t0408F04E406020206020000000000000000004FF4DE802000000880060180080180188180100300300000020062162061160\n\t1600E50610790600888004654401650580600420C024806002826004086827856214206080000000000000000004FF3AB100\n\t0000028800041420941801052049041C61000000800602610E08E44688E0060860361000600160244270C44166C008940C29\n\tE00209200401600600618C116040000000000000000004FF0B9A000000021400001820801841C0380B40900100000100060200c6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6206016D0845\n\t402E006006006080000000000000000000FF3AD50000000018080218018A78019401E52218010000007006306006406C0600\n\t600480600360641100400701602612E104004434016202006001006006006004006000000000000000000000FFBDBB000000\n\t001800041821841801170605001805002120408E80648680E00600640C2061820960054AE40E41E046C86055EA424C2A7022\n\t0520050AE0060D6400116100000000000000000000FFA37C100000001000001E01011840883A0BA01855800010C04790E446\n\t28620508602681644B0002ACA07547803C0640255401508401600200E48CA062AE006014006100000000000000000004FF0C0026c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006006006\n\t002006006000006006006006006006006004006002006004004006006006006000000000000000000004FFA2130000000018\n\t00001801800001801801801C0180000020060060040060060060068008068060040068060060060068060068040060020068\n\t04004006006006006000000000000000000004FFA71F000000001A0020120183100020220920180180009080460160070060\n\t0690685600201400280624A0128068062060010B0104086042006006884306106016006000000000000000000000FF284610\n\t0000001A08221841900040A000012418558020A0510F206544114006806806C10B24102925082CC2006227036C2C4040244400a6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000180200\n\t18000000038298A1201025882020600EB06A04204A06002006004006602004802822C2EC0608600600610480200A106004AC\n\t4006E26006006000000000000000000000FF72470000002018001018002012018145510050C110414121064564A451641600\n\tAA1620E8C610240000203208C004007130000C4E003006806104407006046006006000000000000000000004FF5847000000\n\t001804001800000003841801009001000014421600600C0460C64A21260C42060020AC00228204401408E404204004002016\n\t006004104006006006006000000000000000000004FF753000000000180000180180100180180180180180000060060060060066c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00E001016006\n\t00600620C000000000000000000000FFA82B00000040180000100020180180020890C849802180A03601680E10500E1500B7\n\t2B6C04106110886C0E04E2040072A00A09410A7082C06048004107006006006040000000000000000000FFB3190000004018\n\t0000180000180180000100EA0580004A608608E4AE0A60A62A82B62AC9841862B80422CA28620C84F2A81402A81461024060\n\t91045006017806406040000000000000000000FF849C0000000018000018000010018058110910498040016456C16054106C\n\t56152546556456203344502492C54C0401653640652E812806016044016086A0700600E000000000000000000000FF14600000e6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1640F31600C0\n\t0434722000400408000422604E20624201005400600A04200E114026006000000000000000000000FFA32E00000000100000\n\t1800200801801001000001000000200600600200600680600600400400600080000000200600600600600000000000600000\n\t0006004006006000000000000000000000FFC1DA0000002018001018002018000058108009078000A1640604620601601600\n\t0017004CC6A06020806806806804027004404002802802106000866006A0E806004000000000000000000000FF058A000000\n\t001800601800000E00803C01800A018000003C06407825806C46801C0600402F007A004270A740700681601420420A00A0020016c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010084040140\n\t70000602000001003000000880088000380808000008104080190000010B0800000001450400000400188000828040000820\n\t100400080000000000000000000000FF8D080000001010480018080418018118288E08010000206006006280024106006206\n\t0840242E0040A0001000A4968061065062A6040016006100106016004A06026000000000000000000000FF3B510000003150\n\t00301A2A020AA1A21A202D0A490000C93096206A84936026806006884A4C808800320308A148D40969068AE886B4090024E8\n\t00C12126A04206CD4000000000000000000000FFADA200000000109000300010BC13909213C00101000002624602E03600630096c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2914280322B3\n\t03002000000000000000000000FF96D900000020400020222022024020020620830C0000C10000A08800500C900089090400\n\t00810920800948890800800810000900610940800800009001618900A00000000000000000000000FF826E01000000A80000\n\t0800814880800810800800800000220242200200B02260340200210210A202102A0200210A30208228201200248A20201264\n\t3086002002002000000000000000000000FF69E200000008000008101788B13918D94000188000000614A000000100420910\n\t00800052000004000040847040200A80690680008200201000088200080C0020408000000000000000000000FFEE660000000056c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2C43002002A4\n\t2C0080202A90280290200300288A803002842800802002802532002000000000000000000000FF15910000002000003102CC\n\t23520224221023254C0001000005004A00800C24000894800080814840CC4904848B28C05090110A4080480088C882000004\n\t800805000000000000000000000000FF855701000001380000185180B00D901849851911800040680640600E006006886116\n\t44680E004540014004016216006106D06406534106006002A06016086006206000000000000000000000FF47DC0000005008\n\t42420C828C0D40C12D04C00C04800103340300300348230B4022030030820AB00010215350308252B24B023113003433083100d6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000480341042\n\tA82002B421024C0000808D505504C0D50D00D50C00D50C48820821400000C48C40900548D40A20D50D50540900D50550D503\n\t10D50000000000000000000000FFB6A000080042800040042055200048041040440200010000010000000000010010010018\n\t080C9010001801051000301290448081000010501401000801001C31800000000000000000000000FF62E000080008200010\n\t02000900880C808008010000002E02A8AA88082A80002A81002A8328190000008610200100428A202300002A82A82000002A\n\t82A82A80002A8000000000000000000000FF90D1000000048A00042800A00A40A00A24A00A00800100B002002142802912800036c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200200240200\n\t2000000000000000000000FFF8B00000001044000AA0A800048408C1400880E000002212A82A82A92A8AA82A82A82A8B0108\n\t04002A82A83002A88000010002102A90C10502002A8AA82A81202A8000000000000000000000FF851F000800012000002480\n\t4400020920000A200000005000010008100000300000480000004004000C8940080008049000000090000001008000001000\n\t001020000000000000000000000000FFDF260000000000000AA08A0000A80300020A809000003282A82A8AA82A92A82A82A8\n\t2A82404000012A82A82002A8848020080A202A83000000002A92A82A80002A8000000000000000000000FF414A000000120200b6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (453443403111\n\t02B402002013403443403003243003042889103003003403002000000000000000000000FF67D00000000000138000D18150\n\t01813821801801840008402620621620610610608E0840141562400040842260861560060061260841161062020263160160\n\t06026000000000000000000000FF43FB0000002C0200200201291052242202202200000088C0050040048000008010008041\n\t44810800004804848800510934434000804A248C4800800004800895004000000000000000000000FFBA1600000000C00080\n\t0004842A00800928840812800000280200280200200200200200200A2422088020020820020222029028D2002012412000000076c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000190300000\n\t380000980002000800403100C00400084440885100802404000944844441002080400000C00000100A040008049001000002\n\t0000000000000000000000FFCDD800000000004A8000A8008900808820900888800020220202200200A00218A02200201208\n\t20205025120020120226020420022E20D2012000002022012202006000510000000000000000FF6A314008004004004E0400\n\t40041800000000051000010010010113092810A100100102132D009089121000000009081001201001001061000089021045\n\t001001000000000000000000000000FFAD5A400000420400C80400D00C00800800808C0080014032031430430CB03325302300f6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006086000\n\t288000000000000000FFF8C40008000000C9868000140869800009103830020010E04E0AE40609402A00E30E0060121EC220\n\t0581001004E60844C62462262822061A60180124962E4216036200000000000000000000FF8FD30000000801118020000018\n\t9182405502D84000A00460060060061240C000200400620200650800004000810E0040863062265422562071000221263163\n\t06026400000000000000000000FF339600080010000000200015000004202204800800C00A04200002000485000000C00004\n\t200000880400201302002080400800000101004000800B0450000108090000000000000000000000FFC9CB00000004000000000ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (262060603A62\n\t260820062AA20632610222204E2AE0001EEAAE2242AE866000000000000000000000FFF1E900000000200188000400580180\n\t00A5801809800032600600644629600600600448610600680000600601202E0000CE00E8AA10250600680020600610400650\n\t6000000000000000000000FF0AE60000000000018540000008AB043808033842000001600600600E04400210600602C0160A\n\tC00001009024028200400610640000A04600600000600600E006016000000000000000000000FFD834000000000001810000\n\t011801001800001800020000E2160B600600420810E22E00404600E02028420C02000228C006006002012106036000106006008ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C3143040004\n\t953955800028E5565564C65565544D65564515504160040C20024145565520C62CEC0E4882A65562040D4D56556557556000\n\t000000000000000000FFC8A50000002C8001C0008A0AA831011912889893800008A2AE2AE11600E2AE2262AE20E296204000\n\t22A2AA34C4422AA2062060102A62162AE000416AAE2B62AE086000000000000000000000FFE8864000000000018000000098\n\t118938A980180180000020060060160060040020040868061260082163561440060022060060200260160060022060060060\n\t06006000000000000000000000FFE9892000002A80018000A80A890198C0018C588180000062AE2AE0C64462AE33E2AE0462004ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060000000\n\t00000000000004FFB6DC000000200001A0000408100100182880180180002420060061460060001160060000040060002022\n\t4201600400000610608410210E006204556806006006806000000000000000000004FF227F0000000AA0018AA0E800B08108\n\tB8008A98AB800004A2AE2AE00E2AE2A82262AE2A0AAC2A700800A08A0862AA2A829620632620A2062AF0040062AE2AE2AE2A\n\tE000000000000000000004FF0C610008000040018B202000000502184080182180002460060064061060040020040810400D\n\t680000200200411600014E04E22401008600680000400600600740E000000000000000000000FF10BF00000035400195411400cec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (408022222238\n\t60044062AE2AE2040062AE2AE0000262AE4362AE2AE000000000000000000000FF9EAF000000000001000005805081911801\n\t801801800000000600600600440400600600A00200620400200201650C0060060060B400400600600408C00610E006006000\n\t000000000000000000FFAD6600000000002300002180003304002480182380000940060060060940C60062940820B034E020\n\t09608E0220464D60060060042D6006006084206006406006006000000000000000000004FF63DD0000000000010000018210\n\t2B840103803801800010400600620600400600600600A0000170001460062420060060560560140440260068040040060060002ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AB8880832AB8\n\t8900002262AE2AE2AE2AE2864262AE2A02082AE48808612620E04E2AE2AE2AC2282A62AC2AE20420C2AE2AC2AE2AE0000000\n\t00000000000004FFEBE8000000001914801D559518CCB11951555955000055655655655645644655640640E44A1162A444E4\n\t44454514156556554200454556556104014556124556556000000000000000000000FF2DD580000000180080180180580182\n\t1851001805000011600600600600600600600600604200600001601402400400600600408001600600600008400600400600\n\t6000000000000000000000FF009F0000000000890000898A800104388C8AB88980002202AE2AE2AE32400C2AA0642222024000aec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000000000\n\t0000000000FF7D36000000000800000004084000C11821801805800103480680680600612640600600001500400420C20289\n\t20021060040000C0816004006004004006800006806000000000000000000004FFCE220000000008AA0000881410AB807801\n\t8AB8C980002002AE2AE2AE2AE25611E2AE2B03242AC00044440C3267042262AC2AC2042062AC2AE0042442AE2A82AE2AE000\n\t000000000000000004FF8F78000800001040801801803800C02001001801000000600600600600608E00610E126100040004\n\t1000960060260060060040A8084004006004344006004006006000000000000000000004FF020C0000000010AA801AAB8098006ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (120006006087\n\t816406006016006207006000007106017004006000000000000000000000FFC279800800001801800C00003C00C01829A018\n\t118000C07026E0742E99F116E074C6C220768180004806E2C1201A00F307146186C0680610660080480700C0050060000000\n\t00000000000000FF4060000000001000841600440000C00101801823800000F00712600702620602700601608002401500D0\n\t8F0060060A600400020008400E006004006806002004006000000000000000000000FF20ED00080000100080102004940194\n\t188DC0184180001060060060068070168C70068081000045100A40C60060D60170070040141248040064010D60060020040000eec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9801C8180308\n\t000362261CE22620642604642E23200614C60000C09A40200210600A08C4141820080860200041060A00A008600000000000\n\t0000000000FFC94A8000080018098010200128004020A0803901804000700700600601640620E8860064560000A12410460D\n\t608E2860260022CA0560464061000062A600A00400E000400000000000000000FF52018000000018018212002A1C00080100\n\tC81835800020610600650702615611604F48029640000845000700E10602608612200220640F106000005006001004006000\n\t000000000000000000FF1D41800000000801600808105C00909849D0180180000061260060AE00782608E117142406300200001ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF01B3000008001001801202000844211048A89805100004422608E20620E02700602E00642A10C140024036006116\n\t20602200800001201250608000E506002000006000200000000000000000FFEAC100000002101180140800D800E25101C058\n\tA1012040401600604600648609640600008220440000C10623600608640C0802CC0420C000E4400C60060AA0801160000000\n\t00000000000000FFD222000000020001018840000801021808809821008020200E0060060060864863064420862840005840\n\t0230206200620000400010208000E2000AE046002058006000000000000000000000FF6FCE000000000001000C1A00182381009ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (294282C00008\n\t400000A4000880000000000800028000004000000000000000000000FF0CDE000000081820891C888C8806806888CAA8C880\n\t002622AA2AA2AA2AA2AA2AA2AA0422560022001221022425422AA0022222224020202AA1000022AE0023002AA00000000000\n\t0000000000FFB515000000000011034005800020211802001820000008C00000000000000100600040404802408001410808\n\t8108000004084014500090000100410000400150000000000000000000000000FF597580000002A082000020022110140040\n\t00000400000000000000000000000000001300802900002802200404400003500080800484000000001200000A8000000000005ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400004000000\n\t9004805004004005000004408004204500A3484100000000500090C004000934804000401004005014804000000000000000\n\t000000FF31D790000014315510973584995551190BF559558000106D57556D5755655755755620641411450120C086106017\n\t5565174254044C6457556400556556504C57556000000000000000000000FFDC1C0000000AA8848C288AC8A8008888888AA8\n\t8880002822AAAAA2AA2AA2AA2AA2AA1023020CA00100320A28A00A2AA2CAA222AA0B22032AA0000AA2AA2AA222AAA0000000\n\t00000000000000FF363C00800000800000400000000040202000000000002400000000000000010000001200A0040000080200dec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFA23A1080001004040040201501005400100000000000000000000000800001001000930110290000280288000040000B\n\t50D08A80100010000000000000148080000000000000000000000000FFE80100000004400002020400204C01012420000000\n\t000A800080080000100000000040000002050101002012809100000002001000810080040000000000001080000000000000\n\t0000000000FF9C8F800000008CA88C88889048008428008AA8AA8001A13AAA2AB2AA2AB2AA2AA2AB012223C0200006200220\n\t22022AB0021120322322222AA0002ABAAA2023222AA000000000000000000000FFE1CB8008000010490014404000A9420044003ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C0880E860420\n\t4820801404008708500500005801004000000000000000000000FF8BCD000040000800900850A00828802AD094A800800024\n\t204200322A2020134CA10200283200200034324300228201208250A2C254288310850000200232230A002000000000000000\n\t000000FF707F00000060060000000020000000000000000000000882880509000500A08018200001008A0480008800040000\n\t0A0208820000000240800000009800000000040000000000000000000000FF465B00000000019811011040A0000001000000\n\t000000000800480000040000000040001000300020C100804000000000408000080400412200007C07C0800010840000000000bec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800200001\n\t000C48000550910110110540100B00248510048A080884000008008000000004100480000008080000000000000000000000\n\t00FF7F3900000000087080082282EC008008089EA800800020280300A12304208A08A08A08A00A4020500820421823220020\n\t8240280200278221000050B543782002002000000000000000000000FFE15700004000180108185180385180555195580180\n\t0024624612E52E036156256106006154506341D4C34702630611610E4D45574A60A64D000080E00754651604400000000000\n\t0000000000FF6C8D020088001111001001010000001000000000080191413400428C4042201000400012A4A482A80242AC02007ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFE07D000000000000000000000200001001001000000000\n\t0000001000000000000000004804004800000000001000000000005005000000000000800800800800000000000000000000\n\t000000FF406D000000001C808888AAA28800A0080880C800800000004020A00280200280202200200A012000902002202042\n\t0420A2006042042022C00000002002002002022000000000000000000000FF32D1040090000201000000000000201080000000fec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4260064043A0\n\t02E10701022000E020026022B42000000000000000000000FF0886000000001A008018118218018018011810018000806006\n\t10600600E2A44860841829008260000260065162030840C6820002016846010000006A00E060060020000000000000000000\n\t00FFFCBB000000001800101801800810C01901811901800024D0440260A610E2D404600C00600602E4112420A704634E0D50\n\t06044A86CA6316140140A46040006C0D082000000000000000000000FFCB5A08000000180000180182180080181180184000\n\t0000400420600E046000106104026048406100082206006006006116100026006006000400016200026024402000000000000001c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A004E026507C\n\t060070260262460024A70034010044A600F0060550C62CE30A0040062080280000069061024A2100000000000000000000FF\n\tA538080000001800801801810881800000C0288080808C401400681604604A02641601628642200882411689600682628608\n\tA428A07C06A800B0510087A86406012100000000000000000000FF1A29080000001C00901809800810C000888108C18000C3\n\t48040C61261460132260060470092124105045260C610E00D03610200250653614810044080600620E102000000000000000\n\t000000FF373E000000001800801801801801841911041001800000652674744E00600500604C0020F000618000604624E4220081c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004FF4242\n\t0000000018008038018808210018018098010000425004046006006106000016204114284000090126306086006007485026\n\t00641601000920704640F002200000000000000000000000FF73A8080000001C00801801C0C8010418018018018000004004\n\t00612600600780080E0158140440044A08161262062040060000064464060000842860060078068000000000000000000000\n\t00FF9E55000000001861819809823801808110BCC907802110F53605E0961C6816007006062006C1AB10A8520600680200CC\n\t26026040026906100000071166406483212000000000000000000000FF9974000000001C01801809C21900E08000810601000041c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D61008164068\n\t06000005406106886002326200000000000000000004FF2767000000401C01C03801B0002180180880084180000070070360\n\tA6446B2C30A14428880D00C40420682E20E00611613720000730640700000D226806426022224000000000000000000004FF\n\t50E0000000201A00A21801801801001801801801800008C0040068A6006A4E42C02611404404812180040E01601610C4A680\n\t45068B494604000402600684624A007800000000000000000004FFE3C2000000001800821801801A01001857009840800008\n\t414401680654600612410E8044840A04844082860C6C6240421608020640402612800400602600E00684600000000000000000c1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (484E10413600\n\t684E216106CB0AC1552A1040C82489600600688E10081620E40C0060002269261060040C6006000000000000000000FFE66C\n\t000000021C01801801A07001801001DC3800000000620600600700600C00200428080400000400200600E1040060060009A6\n\t0071CE060000126A27606002006000000000000000000000FFDF840000002018018018218212018A1841009201800045616F\n\tA0600E38600480A084008465C800EE18A20E046F14C0E00620014605C33710000608600E006CB30040200000000000000000\n\t00FF0A21000040011801801801800501801804820F1188005571060AE14600E24430241502049424C40022712792708434600021c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04FF747E0000\n\t0000180180180180100180180100180180000060060060060060060060060000040000040040040020060060060000060060\n\t06006004002006006000006006000000000000000004FFB432000000001C01001801801A01801A01A01801A0000040060060\n\t07006806806006800804000802004804002806006806004006006806006006006806806004006006000000000000000004FF\n\t8025000000051801001801C018018018010018011000057506C5400650E2061064160000100020A412450C8464072D604640\n\t0826006006006004002216007140206246000000000000000000FF9295000040401801001821A2190192120280DD09A0004800a1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002604600E00\n\t2004010046AA680A886006000000000000000000FF614E00000000199120180182F80180388098A803840102422C50648640\n\t600680680600480000081080420C024000006006094806006F86002000000916986800006006000000000000000000FFBC5C\n\t000000001A01001911C01801C019010149158080006454004146056206546046A004214B410411549502608040E2160040B6\n\t006016006004904426006007006006000000000000000004FF6E7A00000000180100180182980180580080080188002AE084\n\t05600E10615600E41601009000444020404400640004614628400600600600600442400600600400600600000000000000000061c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00500F107016\n\t04702600280600600000EC0900204900600728680180700200200000C00400600E086006000000000000000000FF75DC0000\n\t00001B01001801A00009801800001A08028004C01600600600600650E406486082806088D068264A40008170060220C222E8\n\t0200200080600404E004006006000000000000000000FF8D5D0000000019010018018002018018014019880A802169862A72\n\t0E2BE22EA0F26E20F7EAAA63B800E0C710428021F22E40A9A841600A002000106524016044006006000000000000000000FF\n\t104D000000001801201801801811A01E01480C1195408462340070161060B6D5640648400000080450C48C44C0510070061400e1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C29800000004\n\t5811009803881921001808A510A3800028600631612610E10621600708600644E00802004810010600600681108200E10641\n\t04000150042A254E056006000000000000000000FF636A000000001E01801801801801001801A01201800000600600600600\n\t6006006006006806006002800806000006006006000000006006800002004004002004006006000000000000000000FF0AAC\n\t000000001811801911800201801801081A80000011500481484680E9A6946806002226816000D000C080A000847106402002\n\t00680B0020005C47B4286026006006000000000000000000FFE52F00000000180160180180000180180100180010200062A50011c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0410A0440200\n\t088020600180000000000000000000000000FF7EA10000000200002022800800000842C80000020000201410169108010000\n\t800888120120000020140840130000800020000108908218000000410008180070318B08000000000000000000FF08100000\n\t000019F00018018438B100180000100D80000A48040048060064944062160060068822000000A0000286086006C000060061\n\t0608000020471600200EC26006000000000000000000FF9437000000211B20885931A03A012AB903281209800082E3048264\n\t0E826A260062B6C4ED46102C40C96286A40A4E0CF2CE4A4A0E426A2E880800B04CD680080628640E000000000000000000FF0091c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1200B1520420\n\t2340354215308008309301320205340248310200BD5314308142B003C13112013082000000000000000000FFF25800000020\n\t820D4804043052002022002002000000500000E002100A8840A08820CC80C0800900808408000C08870A810F4A10A3044001\n\t0900840880820800880000000000000000000000FFA6F8000000001800C08C02800804830C00118821800001228000200280\n\t222280340220260294E04100211200212280A00B00200300600230A000000002012202842002000000000000000000FF7D8B\n\t0000000020000040280010401491160E00C1000100D0000850A0D001040400400048042300082A4A04A8400000040030C0C40051c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000A12\n\tA00800A40A00AB0A00CA8A828000902043002002802802103002803222002800902802002802103002802812D02802802800\n\t0028028028CAA42002000000000000000000FFFC320000002012410010012032042022CD2022510000828014000004804810\n\t80480480080080CD00004804800CB0A4500410CB2082400000490088C808000800904004000000000000000000FF33B10000\n\t0000188B0058018010218D18C58918410000406C16C461062862062064161460060040408444441060860060068540361460\n\t0641400000628E106026326006000000000000000000FF5D04000000400C40A00A04D42C12C04808C20C04800108A003082800d1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A80002002A03\n\t282A8020228000000000000000000000FF0E090000001543001541543523102142222022220000500450D50550D50CC04C0C\n\t48D40A00550200CC0D51550C10440D50C50820D20550800800450440D50C48800000000000000000000000FFBE2800000040\n\t002000020043440440000444440200000000010010000010408000010004210A100210800180140080100100904900100100\n\t1002000000001001100000000000000000000000FF46B80000000AA0800AA0AA0880AC0001000500000000200A802A8AA82A\n\t82A02283A82A80C8AA00002282A82A81000182A82200100182A8000100A203A02A8300008000000000000000000000FF71CA0031c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (201201200204\n\t2A2202A00001200200204A002002032012002002002400812012002492152000000000000000000000FF17B70000000AA280\n\t0AA6AA00A0500C809808010000012A92A82A82A9AA8000B00AA8280098210001A012A82A8000AA82A84803002A82A8000001\n\t2312212A8D10201000000000000000000000FF28260000000000542004000000200A00081000880001049080001000000008\n\t8080000081088010800080000000209000000804800010000000010810080000002B0000000000000000000000FF2CDB0000\n\t000AA28A0AA0AA08008008A2A009002800002A82A82A82A82A8308A292A83289002000802202A82A80A8AA82A81402002A8200b1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00400400C00C\n\t40C00800D08C54C20C00904100B4330234430A24035130420B30C30130030232030024033030932420030330030030130230\n\t4B103103003000000000000000000000FF52B900004010400180191184983180180190102184004060863060160160460062\n\t0440620400428000600E00602600624610622600620602C080086486016026004000000000000000000000FF9C1B00000020\n\t00240010012C02A42022444012340000804004004804000AA00A4004808004884882140800804C80005004C0092080080480\n\t4802084904800024804800000000000000000000FFF2AF00000000001080080080081082080082C8808000002802802002000071c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001030040000\n\t8400010000000000000000000000FF7FC30000000840000000280200010B1001101021104020000030830800044C00000420\n\t60240805000043100000064000084A0040010400050100000030000040000000000000000000000000FFB1F1000020000000\n\t80488080880A800908824800820040868800216203201208A0221C215A052500112042502022182022102302022012112000\n\t0023000E2100002000500000000000000000FFAEE70000004004004004004001A44404224004000001001021031101088011\n\t20120002929170D0010211011982010012810000010010010010090A1081049081001000000000000000000000FF8DBA000000f1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (10600C006108\n\t0262800200020060060B6046102006082036482000286000000004002000280000000000000000FFC5030000000000010418\n\t0180190780D8398000019DC000C0842B60165140260060C804604628201830215601601E40641E20621E0C81A62620900060\n\t60082018092000000000000000000000FFB27300000000000100384580182180192190202980000244240061060000060161\n\t00106000312000416006526086006006206506210006012100006306128300102000000000000000000000FF935D00000000\n\t00400280220041400020000C00D204200A0040010010300280090040006000000000020088050106428220000000220000000009c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A2108AB8AB85\n\t1089A2488188810580005042440062AE2AE0C62AE2AA2BE2B62060000420662162262AE2AEA223262AA41622200020621C03\n\t000C2AA2A8000000000000000000FFDDE600000000004C801801B03001804841820003800020C02400600600600600600600\n\t600095680002600600608600600610208E000006002900096006000000002000000000000000000000FF8471000000000101\n\t80180184982509181580515180001260962CE00600644E00600400600800650028A28A0CE0160060060080020024AE092000\n\t0261205124A4002000000000000000000000FF3469000000000021811801805801009801820105800050E0862C60260062CE0089c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006046446114\n\t000000000000000000000000FFCB70000000354128155955B10954B5582D9141518000554554556556556556556552546404\n\tC8010440E10650644E5565568864345564CE550004126556456404550550000000000000000000FFDE020000002AA4828AB8\n\tABA010CB0889298AD029800002620E32E2AE2AC20E2AE2AA2A62A6AD62003024823063262AE2AEAA840AAAE0A622E0802AE3\n\t040862262AA2A8000000000000000000FFD21300000000040280180182100100090182000380000060060060060000060060\n\t0600603605640012042600E10600600643008200400600620020E0040860CA002000000000000000000000FFFA630000002A0049c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (021540040808\n\t0428E28E12E00400600604C00200609604C80404600408640E004000000000000000000004FF73B500000020021080180180\n\t28000018CD801203800000400400600600600600600600608C82410002000400608600600690408880600610220030600601\n\t6044006000000000000000000004FFF2260000000AA0A00AB8AB88C8AA0AB80188808980002AC2AC2AE2AE2AE2AE2AE2AE21\n\t632420D20400003224622E2AE2AE2062242AE22620300400E2AE2260842AE2A8000000000000000004FFFDCF000000000040\n\t801801902800841805800201800001410400600600208600600200600400090001000E04601600600600404000600610080000c9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8AB8AB88B8C9\n\t8818AB8AD8AB80002C62862AE2AE2222AE2AE2222AE55421A0020064042AE2AE2AE2AE28C23200E2AE0160022AE00608E206\n\t006000000000000000000000FF671500000000010D001801821841845801802801800000601600600600E00600600A00422C\n\t0C20042A030C0060040060060040020C600630C00400642E006086014000000000000000000000FFDE5A0000000000418018\n\t01801803809001801801800005602600600608600600610200610400000001602600600600600604410A2060060460020060\n\t844260562A6000000000000000000004FF292B000000000005001801A41801801001843841800000600600600600600600600029c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0630E0061260\n\t06000000000000000004FFBC3E0000000018880AA0AB8898A90898AB9130AB00002AE2AE2AE2AA2AE2AE2AE2062AE0042840\n\t000060162AA2AE2AE2AE3242822262AE24E0042AE20E2262062AE006000000000000000004FFEE1000000000180D15415591\n\t190D131955911155000049644655655653655655654E55600648000422A15255655055655624454040655410600455652E04\n\t654E416006000000000000000000FF90EA00000000180500000180580500380184180100000060060060000060060060A600\n\t62AC00800045204200600600600601403000600600600000604600E046006006000000000000000000FF775000000000000100a9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (71060A400001\n\t620200400600600680408200E00400E00000621610E406136006000000000000000000FF6400000000001845400001841000\n\t241C01C14001000000400400680650600600640680622F0080042A68230060000060060CF41402700612600400614682600E\n\t006006000000000000000004FF0E3C0000000018C88AA0AB8C90880C98AB8208AB80002AC2AC2AE2AC0062AE2AE0362AE006\n\t24000410258A2AE2AE2AE2AE2040203962AE3060042AE1063061B6206006000000000000000004FFD22F0000000018A18000\n\t01823801005801841001000000608E00600600600600600600600002400608600600200000600608C0020D600422600600600069c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (41E11081C808\n\t018010018001826127006009406107007A4784E2060021004020060042200078063200114060060060004060060261060060\n\t06000000000000000000FFA2CF000004201801C04221803089A08C2FC0180581E021601700744080608C41612702E80C9124\n\t9025302300C01E0570168815A001F08E00600001600F0AE016006006000000000000000000FF437800000040180000040180\n\t3008049851900401020040400490700610F43600600E4070B622400500722B01400120690700F04600635441600408629651\n\t6007007006000000000000000000FF66C0000000201800800201805042003801880001800000400400600085600600608E0000e9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (601601400E00\n\t0000000000000000FF01AC000000001800804009808881903803083805848008E21632620411624603E01E02602050600200\n\t041000822641E01643049200442A09400200610E026106004026000000000000000000FFF36B000000001801800201881021\n\tC00809801C01000000415480600A8471050060A64091000424300230A6B0208612652E88304CCA640602820802620608E00E\n\t897006100010000000000000FF53D9000002481801800001811001840801901801000004C0C4006A522062062064862004A4\n\t05241085200600244082608604200420604640000028E406406016006006000000000000000000FF663900000010180160000019c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000080100100\n\t0400060000002200A81082300A0100000000000000088000000000000000000000FF3435000000001800800001889C01C05C\n\t35801401010008421444620000710600E20E22014002624014001000000635628E0060560442420200102260B60060060040\n\t06080008000000000000FF399D0000000018018200018019018018019011038A2000410400612004E40E0860060104001060\n\t9000030048831000600613628620401230410008640612600610404E000000000000000000FFC24500000000180182001180\n\t684180182180509B8A200160460060B400E00E0C634600620008608008424C00004820604600A2061040022104822860A6010099c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000022000020\n\t040000000000008012000008010010000000000082001000009000000010001200000008002A840000000000000000000000\n\t0000000000000000FF4DF30000000AA8930000AA8C92A8CAA89000009880002002102AA4022AA0022AA2AA28A0022A200022\n\t222220208A2AA2AA19A2022220422021002AA2AA2AA2AA2222AA000000000000000000FF4AE0000000000010000000004001\n\t80182189040180001000D000041000044600000004640401400001400C094246000000000000000100008000000000000000\n\t000000000000000000000000FF3B0000000000002000000002000200021202202400000500000000A00008900000000061300059c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2ABAAA000000\n\t000000000000FFAFC9000000001101400401001204400201441304000000410500500000505100500400105400010300400C\n\t8C0000805004020110001008010002804004004004110004000000000000000000FF497700000055588120055594D953D119\n\t559359558000556557556156557556557556557D2D44610123502541655655755640E52E5565560060015575575575565565\n\t56000000000000000000FFC7560000000AA8248000AA88ACA88AAB2491282080002AA2222AA0AA2AA3022AA2AA2CA2822AA0\n\t012AA2A220A2AAAAA2AA2022222B24822A20012AA2AA2AA2AA2222AA000000000000000000FF397C00000000104A0004000000d9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E04400000110\n\t48000000000441041000820000020C08000000000000000000000000000000FF405700000020008000000000004220200000\n\t440000000000010000A08008000000000009308201010C01508000210008000200C000011000020080100100080000000000\n\t0000000000000000FF6837000000000002000200044400040000020000000000000000041000000100080004040000800001\n\t0800110400000000090410000000450000000000000000000000000000000000000000FF19148000000AA8288000AA888C88\n\t88CEAA888CAA80002AA2AA2AA0032AA2AB2AA2AA28A00238220020271226208B2AA2AA2020022AA2220820002AA2AA2AA2AA0039c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001101029000\n\t00000909440448204048440142346A82E800580840C6EDEB0300021080005000010C05210280001004004184044000000000\n\t000000000000FF8BC9000052048908880830800B528D0A249108209000C4200340212304200A10A08234A80228200104300A\n\t2522A2912A22402D42B0A00201000008202220008202A000000000000000000000FF31B00000000000000000000000000000\n\t0800400000008102A80A8008488820000008000080800008C88AA00000000400001000108003000000000002000000018000\n\t00000000000000000000FFED1D0000000501000001100001000005C02040000020001010100100000210010800000020D48400b9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF50FF0400001000000001000020102100010102040440901500010840820100821840AA80500808080200C82C80\n\t20000050000200020001000280800020004100800000000000000000000000FF79370000000D682281280080080A868B0E84\n\t08028220002A8270A902623092222802003D0201A08009240200240298212A0031C200A00306002806243A00200200200000\n\t0000000000000000FF4155000054051911901851801B55951855D15821884024620F48C14F0CE414086106156086D0E1528A\n\tE09484644E956C465045565070860200020A642E40480600E000000000000000000000FF1A130200006000010090010024010079c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00001600608\n\t6086090126146126000000046004108006006000000000000000000000FF4409000000000000000000000000000000000000\n\t0000000000000000000000000000006000000000000000000006000000000000000000000000000000000000000000000000\n\t000000000000FFD0D50000000000000000000010000000000004010000000000000000000800000001006804000800000004\n\t000006000800004800000000000001000000000000800000000000000000000000FF2F570000000008A2802808800C82A00A\n\t280028008000802008002802802002C104000020032222A1302002802802822002002002812802400028002000003002002000f9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (021C5B818000\n\t40E09600624204603EC10A000A690A9260808277C0806A668C6806A4C12006E20E90041104618190A4070060000000000000\n\t00000000FF617E00800000388580180180106180180002180180A0A370470250CB0061451008001060928060008060040060\n\t0080680480001B206C3603800001E11C002806006040000000000000000000FF87FC0100000058C18018018009018018038A\n\t1A1181205460042A208A116C0A004004800886006400106500C274482460244454064160070A008040700440000610600000\n\t0000000000000000FF97110000000098018038018218018418118019010000006084000400046000004404040026046080040005c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF894D000000001001801805801801821881A018010001A0602602685730600641604683604251641200602604010008\n\t002482A301106007208002444106400206006000000000000000000000FF696D000000001801801805800803C05801401C03\n\t8200907805A30C8EA8F00010200292820604600003701600000809022E416C02896086250000206801402006006000000000\n\t000000000000FFE039000000001843805801801901C21A0900181180000860243000260B750088280280004600620008F006\n\t44800E2400A40C2302086086100081444004500006106020000000000000000000FF71AD000000409801801841861101C1180085c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200660224\n\t54582E04E86E22009C28680004611E206000000000000000000004FF3909008000409815801801822001A01AA90019010000\n\t104404902106016C02A0000008688C88600C20E80200008E880026000414085106C004005460148070074060000000000000\n\t00000000FF93870000000018018018418090038018010018010220000004202A060160120840044068848060040060820000\n\t0082000C80001600409604000408E844143886016000000000000000000000FF728900000000100180180184990183588194\n\t5B058020107636016106846006066FA630642224E3880564120200D601058440600965600E10041008F02202208600E000000045c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3801F0002230\n\t162064460860278240040062918D621490F0170C680641600624D08442610604040C4045030B690604600000000000000000\n\t0004FFF18C000000401801841C019008018C181110188190009070072060A600F40625124020600800600824688E90613000\n\t600E444204084106000205044002126086006000000000000000000004FFE171000000001801821A01881001F01801803805\n\t8880404024A438220C600208A002406004447C00126202080C2600040D80412400E016020104806021086006006000000000\n\t000000000004FF3E3600800000986BA01801C21005847A2190181380000650340020028060020C644601E60409638008E15200c5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF9BAA1000002A0001800005841811821343A01C91080080400601614CB0713700688643710AC9084D02AC4200640612E846\n\t12C024342106040508406316016006006000000000000000000000FF1ED7080000201805801801801801D81A09905C010000\n\t80600606E08620700E01E08702E00020612100620210720602602640413C00F02600000000680A0069060060000000000000\n\t00000000FF81A20000000A1801C018818058058219A38058B9010040649694680F14F0868030023069004560850264E20060\n\t2098608E9841048C5006000084006052806006086000000000000000000000FF7ABF0000000018058018058408118018016A0025c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (562160442041\n\t44000004000004106006006006006000000000000000000004FF328000000000000180000180180080180180180180000040\n\t0600600600600600600000600600400000600600600000200600600400200200000400600600600600400000000000000000\n\t0004FF6C95000000000001800001801800C01801001801800000400600600600600600600080600680480400680600680680\n\t2806006804002802000004006006806006006000000000000000000004FF0F64000000400001800081A01801801C09A21841\n\t8000C4489740740680E00604680600640202020410210A04604020611700000501202600000600600614600614400000000000a5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800022255448\n\tA45690A912556CB0016B4004AA1511002000004004400C01680680404480040480600E00400600C000000000000000000000\n\tFF647800000000000180000180000983050D20380B04C0386AE4A6AA6E40280202E80880680080300600000000002680C016\n\t00680480000406000600601E806806804800000000000000000000FF48D2000000000001800001800011840800911C058800\n\t40610451241504A546456006026020002510020CC00200000069040004060041051100054070060060060060000000000000\n\t00000004FF673B000000000001800001800001800850803931810000E2040020860820160062B65160902A204400000001050065c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF12\n\t5F000000000601800001801801800A010038018000A108852A94240082024062A700190400E2914252040400010030060548\n\t0280400700000100600604400600E000000000000000000000FF706A000000000001800001801C01800001801A0100000040\n\t2E0068160060920D601680E24C84202008C02400845004400400000008A0C202042800680600402600640000000000000000\n\t0000FF90AD000000000001800001801C018083038018218A2001C8060460862AE62A2062A62AE0BC0A23E946463487069E20\n\t50A4040A20112186040050306006044047007400000000000000000000FFEABA0000004000018000018004008A0A01A0380100e5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080482680688\n\t4916140890856906CA502E80E000000000000000000000FFBBAA0000004100058000058A8009901883811815800000500720\n\t490610C40408E48000608E0260201378460260418A004C48E2B220C244000020A0624F015206346290000000000000000000\n\tFF7799000000000001800001800001801801A018018000804006006006006804006800006006002000006006006006000007\n\t806000800004000000006006004007806000000000000000000000FFCE0D000000000001800001801C018A09C15119018000\n\t02020490000608090200700680000440600080410C81000600281C40410200400291000018600E00400600600000000000000015c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000002C\n\t3710890101000061208444405800600000360040014000000800200001A0240420028000018390000000000000000000FFD2\n\t7100000004000000810000208010C00250200000001F0020E00000808420CA0010407C081201018000081006060180480100\n\t300001400800090290502105400A0000000000000000000000FFD44C0400000000A982008185D82180108188989100000081\n\tD40000D400000000600000020240600800AA120060060A002602660624C00640001000618608402600600000000000000000\n\t0000FFB71C0000000004B1830521A05B23A15241B45B01800112893408AA562428A8446810880422C9291020240AC16C80810095c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFC33A00\n\t0000020500900500CAAC00CA0C0C884C4C800133210BC030328AB323482003312343C8310001280B08340B02302341303340\n\t34025010080224AB01108300A010000000000000000000FF97460000002183002002003A0440040230004200000080100080\n\t0A00880150209608810840080821001000E28800800800100800800E88120800900A08C40A08B00008000000000000000000\n\tFF2D7100000000000080000080080A802804840804800040500808A00300220210308018208220A080232802042082142002\n\t28A0CA400002000000402002004002402000000000000000000000FF2EA000000000000210002200180148010142004A00000055c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2202200202A8\n\t0000000402001102A82A8000000000000000000000FFE040000000204400800000A30A00A00A00C00B008000902802442912\n\t802D0A802852842812002A0000200280A802882842802812C02802800800933102C12802802800000000000000000000FF77\n\tED000000250401400401202200200232201232000080C84C084C400048008D490480080400084000410C900C00810C881109\n\t00895000000900C048548C4004000000000000000000000000FFDE3404000000800180000180184180390184180180000060\n\t4600400600400E01648C006004046440B04024426006096006906206046126000100506006426C26B060800000000000000000d5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A83212802A82\n\t080880282A82402A80082A83003204A82282A82803282A82A80002002A80282A02A92A9000000000000000000000FFF54000\n\t00001423541541543141541543423543040000C49440B48B48550308C40450D30D405508405504D0C40D10C40900C408A8A3\n\t0550000900100CC0A00550D50800000000000000000000FF0E58000800000400400600404000400404400400000110000180\n\t0049001080420501001090801001801021011001001001041001000001001001001001001000000000000000000000000000\n\tFFED2A0008000800AA0AA0AA0800AA0AA0800AA00000002202800080002A80202002002882A02A84002A8A202200A82300000035c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF1C55000000\n\t000800800000884800800800800800800000200200A0020028024122020020A200221000200A002442082002402152002002\n\t002400002002102002802002000000000000000000FF72D70000004AA0AA0AA0AA1000AA0AA0902AA0AA00004002A8A10200\n\tAA82410210802882012A8400AA80302200883202A80102002A82A80000002A85800102A82A8800000000000000000000FFFE\n\tB700080040800000040002040040000800003000001000880000010010200910800000108000030008001080200802500882\n\t00101001000003208008041000000000000000000000000000FF81370000000AA0AA0AA0AA0284AA0AA0A00AA0AA0000029200b5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010010010600\n\t01001001001029001000000000000000000000FF105D400000400C00C00400800C00C02D10C40C10812101310300B1435430\n\tCB50308251330320B2814530A2222312402013402433403003002801003123083003103002000000000000000000FF257500\n\t0000021801800001801849801823805805020004602408420E00600400E22402600E02601000401409600600612610610610\n\t648600600040600600E0AE006006000000000000000000FFDEBF0000002014014004012502014012320012010000AC880414\n\t4928004154880834840808804800004C84910800810801150801000004804800804C34C290040040000000000000000000000075c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (041010015030\n\t00003161000080000202000202C60A00C04900C0110020148108040400208108000100000000000000000000FFC38A000000\n\t020000000000001820040110082005020002C42812001020000010840002E02C4504002140A8130006400040280040200100\n\t000000000100008080080004000000000000000000FF6E6B0000000010008240048228088008208000008480002440102022\n\t0324820024782422920824481B224210200A00209A00249A0C2300006000312162082000410002000040000000000000FF1C\n\tC74008004004004404000444004424025204090021181491649281081629201090081041101081101400200280000001000200f5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (CC0000000018\n\t0182000180400384380008108980000064060040040162040040C049600201604000C40600220008200A20408242A0440560\n\t0004608600E00C20C006000020000000000000FF80160008000018018180018038038018130410CD84400061D010A0040061\n\t5240408004060668658004008A146000246304104456202004006202006406404004004006000000000000000000FFDA9B00\n\t000000180180400580180180180300100190805260000102141060000844080000960860000800B200612640642600C00608\n\t6106087490116026004106004086000000000000000000FFACDA00080000000002000000000004201012004409404A000800000dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (408E00600000\n\t6006000006006006000000000000000000FF7DB30000000000AB8000AB8C18AB841A018AAA0000002263124084060262202A\n\tE3662883A622600022622423608821640420644220E20A0060002AE2AE8362AA018004000000000000000000FFFB7F000000\n\t200001800001831801901821800828000000E04220020640600000611600000E006840106104006426006044006212146106\n\t006800006006114006004806000000000000000000FF79BA00000000180180000180200182D90C001883800010608E0A60B4\n\t11610E00400002600211600001001610A00612A50A1340C00000400060000060064060004A0004000000000000000000FFE7008dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (14E002006000\n\t00600C097040102108006026006086114014114134006802006007006004104006000000000000000000FF55280000004011\n\t5580015591400B953900955555800024655248255643654255643051643404600452242844611050655611440E2264060064\n\t04556557556556555006000000000000000000FFA3210000000010AB8000AB88B8AB809C098AA88400002A62060860A62062\n\tAE2AE20E2AE22222600222A22432228E2A204A2260802242028060022AE2AE2C22AA242004000000000000000000FF628460\n\t00000010018000018218A1801C49800000000001600602E00608600E00608604600250601000600410622002E00602610009004dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000020180180\n\t000180382182182D801001800002E0060260040CE0360040A00260100960100A604610600008E00601400412404000680400\n\t6006002000002004000000000000000004FFA57D000000001001800001830095801A00801801800000600208A00600610200\n\t601600602444600000A10800C02602400630612440C500806404006006806000000004000000000000000004FF08C9000000\n\t0010AB8000AB88000188B8848AB0AB8000B862AA2022AE2062022AE20628E3840178002123002322882022AA42624E006048\n\t0070062AE2AE2AE2A82A8004000000000000000004FF4896000800401001800001800001903922801031800101604205201600cdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000006006\n\t004106006006000000000000000000FF94C20000000898AB8000AB8818AB8AB8A985192180002AE20604623C2AE00622C286\n\t28E2A02AE10022222220408E0042AE3260040041422AE0802AE2AE002002212184000000000000000000FF0C440000000018\n\t01800001831801801803801005800000602E00610400614E00400E00600000608401208200C00000C00608E42400C0220060\n\t0400600640A022102054000000000000000000FF235800000004580180000180580180180195309100000060864AE0040064\n\t0608402004601000644008600E1462265460060041143442880060040060060C2308052204000000000000000004FF082600002dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (860880840060\n\t000020000860062064000862CC00E02400601000208400200422400E006046000000000000000004FF4DB60000000A30AB80\n\t18AB88B8AB8AB8C18AB88C80002AE2A62162AE2AE3062AC30428E2882AA4081263162CE08E0565042AE2C40562082AA2042A\n\tA2AE32C20E08E2AE000000000000000004FF6039001000115155801955D1595595591088580180005564A620E44655604E44\n\t244E5565485524444524D615613043600042649452E4005560045565541144A6546416000000000000000000FFDE36800000\n\t001001801801801801801812801800800000401604600600605600605604604000200041204600644608604800601400604000adc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (041001801A01\n\tA04001801829025C0000000060C208200200210E0000C40061040024100000462360064C00AD006144006408006200006004\n\t10C4AE8AE006000000000000000000FFD98D000000015401801801830001801803201805000000601201200300200600600E\n\t00601080210024890C1044000104060060163260A0006004006006046006406006000000000000000004FF955B0000000910\n\tAB8018ABAC00AB8AB8810898E900002AE2023222AA2AA2262AA2062AE2202AA1000802040040AE4000002AE20450E1002AE0\n\t062AE2AE2040464462AE000000000000000004FFFE2700000002100180180182180180184380182D800000400E1061060062006dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00806A060029\n\t0E006006000000000000000000FF02A3800000001801805801E05E01849801C0180A850008640612448408E0060A600E28E0\n\t278060800440040A4011000006006404006000002000403006006096006006000000000000000000FFEA2E800000001C81C0\n\t3A01A01C01C01841D83D08804024E1362060570860060AE406067117046441004C0400400604846F40620C01F00000600000\n\tE006083006816006000000000000000000FF9966000000001481A01C01800201A01D05043821080020E04241300220222741\n\t4024006A0420200480008C40C02021001402608E00680000E005016224105806006006000000000000000000FF2DAE00080000edc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (012400E10E28\n\t020066661442400000641604620200600000400010401E002106446006000000000000000000FFDA4F000000000801801801\n\t800001801941041821808020600E02E2364060064002440164060200880CE51601E05E6460860A610000E000034000484046\n\t202026236006000000000000000000FFF274000000001A01881C21801801821D05095804800004E2C008000009028E10A08E\n\t5000820100000040AC30430704024C00610602649020A090002406006086116046500000000000000000FFF2CB8000000018\n\t018018018038018318054019448AA01265100CB34201024680220E3000D22263400040064A60000002042460060060000060001dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000040\n\t0000004400002200005201100880801300000D00400460104000000000300082460000400003500000001080000105403200\n\t00000000000000000000000000FF0916000000001801801801A0180182180100180080014464280500401101060A42545080\n\t0600000000200613620640604400608203600800C008004202006006016046280000000000000000FF94CA00000000180180\n\t1821E0180180380310B8048D200960024005100422060040040000162AE30811214400409004610408640200628042410000\n\t4002206046106006000000000000000000FF05510000000008019018018000018039610018418A2008610430608E02401603009dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (208A00A2AA2A\n\tA2AA000000000000000000FF959C00000000900000000002040040002400000800010000000300000800002A000000000008\n\t0201030000000000080080000080000000C88000201000004000000804000000000000000000FFFB110000000A80AA8AA8AA\n\t8C08AA8AA8810AA8888000C0A4024225124022AA24020028A2A218A2A032A4924E208A32A3022AA0022AA000222000222442\n\t1402AA2AA2AA000000000000000000FF9C870000000000000000002318000000100000000000006420400428400000000088\n\t006004044000100200200006080114000000000000000082100008008000000000000000000000000000FFC0728000000040005dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (28BB8348A000\n\t2022AA2AA08A222213AAA23A2AA00000A0000022020132AA2AA2AA000000000000000000FFD24D0008000012010012012004\n\t01401001001440000085012403404514C0040041340410112144C10140000004200084480041400040010080808010004040\n\t04005004000000000000000000FF25FC100000145D55D55D55915D55955911955B45800055654C50452CC44556016556556C\n\t5684C08850455655655645722655644755600004640012E556546557557556000000000000000000FF4EAB0000000AAAAA8A\n\tAAAAA8A8AA8AA8AC8AA88A800008200A1020020022AA29220228A2A202200022212210A08A2220022AA20A2AA000322000AB00ddc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000008\n\t420000011400006000003008400000404004898000105612885014000402000006A000186008000000000008001000040100\n\t8040000000000000000000FF78C600000004000020020000420040001000002A0001000120020128128000108000000008C0\n\t05100B00000002000000400000000000000002001000D04C0800801000000000000000000000FFB5C3100000014200000000\n\t03000000002000010000000000101100000000004200000400400400000000000000400909100000810000002C0000430000\n\t010000000000000000000000000000FF73B38000000808AA8AA8AAE808AACAA882EAA80080012AA202202202213AAA0022AA003dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (096006507006\n\t000000000000000000FFA0AD008080000000080000021001080001000600200000C28500400401800D824830029000D04888\n\t44C06DA010007A040800140800420C0400A080C084000000814044000000000000000000FFF67B00000A0001120900209008\n\t0082C90CA00884840102A0228AA50324B44A00A24200280200200008200200280201280250220204200A4820000128820120\n\t02483002000000000000000000FF188C00000000000000000000000000002020202000008000000000400808804800008004\n\tA0300001A30420130000540008000000008000020000800000080000800020000000000000000000FF56BA0000000000000000bdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020028402022\n\t02002802003022802802002002802000002002002002802026000000000000000000FF4FAB00800000000000000000000000\n\t000000000010008500C00001004000B02408300308102A41008900204008005408082082100050108004A000000000000000\n\t0000000000000000000000FF4E8E00000000000011800080081890480680090088000220220028DA29208200248A00200200\n\t203000201205A00201ADA220A3C201A462002201012112002402002002000000000000000000FF28F3000014000114310041\n\t901801955F55805945E200456044556347CC62D65175460064C704549010C2040CE2060560D6D0602614E816306000097104007dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801841801881\n\t88A001010840600400020411614441420604020609210008008800600E40C036046426006016006002006002046006026006\n\t000000000000000000FFEAFE0000000000000000000000000000000000000000000000000000000000000000006000000000\n\t000000000006000000006000000000000000000000000000000000000000000000000000FFDDE50000000000004000010000\n\t0000140000000040008000040000000000000000008060040000008048040000060000000060000000000000008000000000\n\t04000000000000000000000000FFC7F500008000000000000084080080080080080C8000202402080004882000001082002800fdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (470860060000\n\t00000000000000FF8E98000000028100302205801805811C298CA80D0443246086000443080EF8E187965060660C60000080\n\t1061600688481600680008605E006000A06282006002006046000000000000000000FF1F5800000005000020020180180180\n\t9851801A0320000069000061860294010C000EA060068060208040044060A080520600E003006906006000D8642A20600602\n\t6006000000000000000000FFFBFF000000000040000001901801809801801815000000601400400002600C0849164010C622\n\t34300500010168C014450611700610E006026000006932D06026906006000000000000000000FF97170000000000000020010003c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600889220219\n\t491604200025625871601708E09160E60F006002016046000000000000000000FF6F9A000000000002122001825801801801\n\t901008808204E08E08E00004245700FA06106082226231326836C4502008320200648000600602C000006086244103006006\n\t000000000000000000FFC3C2000000000000000001CC5811841A018818508003006124124004A2600208200685090A284A20\n\tC360A68248A82C25040360A3896007026009007883C26106056006000000000000000000FF1E220000000000400000018818\n\t41801881801C00808300600C804204806002022006020C82A545100C689601400E2501480C644200E10602400000600214400083c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01841801801C\n\t19808200608021561221180E0A608B006308894040022432665040010006156C8E46E5060C60040060120464874068060000\n\t00000000000000FF7F69000000000002000001801803801909911001C102017084C0400442684800100A4060451004800820\n\t82004016200006006024817006106000006800006102006006000000000000000000FF070800000000000000000180181180\n\t1841801A2180000868040040004068045040AA24E01400000400230280400040310E40600600602610608401600800780702\n\t6006000000000000000000FF2B56000000000162022005D018058519A1841A0484C168F64E04E440800187006026006842900043c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (700600000000\n\t0000000000FF4EAD000000004100000033803841801901901941E003826504214442206144444A0620654C08042008E08710\n\t714690610710705494E02E294021846146005802816006000000000000000000FF8C7D0000000000000000058C18818218D1\n\t88984180020060148080430360208100062461040082A000600E806930516840814404206307004004006004004202206006\n\t000000000000000000FF3CC9000000000000008001801801801825801E4188220060080040268022020CA082026410224000\n\t0220420140860A042E006114806006806000006203806002006006000000000000000000FF05E5000000000002008405B41B00c3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100004086110\n\t0868464000D6006946006045046144006006802004000000000000000000FF6D5C0000000001000A00118018038419019059\n\t418000336907416010D441022160042C680E884A28C0804404E026A262860868060AE81621600000741601600600A0440000\n\t00000000000000FF1DA8000000000000000045805841821801843001800120E000802006006856806C140860400020000431\n\t2202E006A3E22604608500600616600078620E04E002806026000000000000000000FF710C0000000000002A0001C01C0780\n\t3A05821801904209600682601E0A240A88A8AC02604146A00C322502016008047C16364044006086046004806C14066002000023c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180190180181\n\t0001620614650400420004240610620602444000240E00040640000600600600608600600000600200600600200400000000\n\t0000000000FF0EAC000000000000000001801801801801801801800000600600600000400600000000600600600000400600\n\t6000006004000006006006006004006004006006002004000000000000000000FF920E000000000000400001801801801C01\n\t8018018003006806006800004806004804006807006000805006006806806006007006806006006000006006006006002004\n\t000000000000000000FFDA58000000004000000201801801803801801A0180020064060464408040031220A680648603680400a3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF4281000000000000000001C01801801803941841AC0092640642E204104500D04456956D46B46A3400A90E250130\n\t0104A600004600600E046104006040006826206206000000000000000000FFDD0E0000000000000A0001821803AA3881821D\n\t018480AA601603600422400800883681680600680000220E4008060001060060060060860060000060000060068060040000\n\t00000000000000FF65B1000000000000100101921A01905D11A45805C040547127406034D54128C960C6446156A9000000A9\n\t460B0129130A120010C6006006006004446042006806002006000000000000000000FF944D000000000000040001801805850063c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (06808006A00D\n\t0400010200000E80600044600200600620E206000000000000000000FF003C000000000000000001801801E01E0180180180\n\t038460464061070014440030040000C680000030E24E00084011142400600080200600600000422200604600200600000000\n\t0000000000FF6E5A000000000000000001A01801801A01945A419400106C0600620290608452E2570A620622009100308444\n\t0891800086028842024246046080006106106007026044000000000000000000FF0B98000000000000000001801C01801801\n\t807803822000E0EEA0EBAA0062E48F638C2AE2AE2883205024E42A8AAE7A800805602084644600600000652610600605204400e3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (CD18018002A0\n\tF216CA6856256422C4C848D104A68A0C00A32824906908906806810D269404068C6C00842A2A286A0E826826000000000000\n\t000000FF8921000000000000000001821801401841C0588D8000026107816A0208008E90130000600E208088106484006200\n\t22752A02600A40A0AE00600040210200E027A86316000000000000000000FFA6F90000000000000000018018010018018018\n\t0180000060060060020070060000000060068000000020048060060060020000000020068060000020020060060020040000\n\t00000000000000FFB61C000000000000000101901801811813901901800200640612E0069100044028808080020C022101700013c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFACB9000000000000000091820040101820020000000280100800090C41500100011400E0040040414050000100064006\n\t700060042C10000000012000200103010E02D0000000000000000000FF110800000000000000000000000003028208260200\n\t01420001200001A88801408000016BA00106003301100000060A0100056000408820060010000001A8800850000000000000\n\t0000000000FF83AA04000000000004000190590300180980998180002062060B60660005020040C010004E2081900860040C\n\t620E20608600660E00020E08600000201A106006204506000000000000000000FF958D000000000000000281C81A832519130093c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (601610601600\n\t630E41602600600008640C006486006106000000000000000000FF3BA3040000000000040400F02C80C00E00C00828800084\n\t329208B842402D0A0822430822C324352994330341310341352302B0038C2912123009203102492003543252000000000000\n\t000000FF3F090000000000000002004002902002002442500000140480C00000820290300A00A808014808080404A0C00980\n\t910808808901110010800800400A80C00820000828000000000000000000FFACE30000000000000000008808008088009008\n\t08800200A11210A21200302A0B142A002C0206200000A2020020120020020220B20231C2902200122502002C0200200200000053c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8800022A8008\n\t0002900802482003802A82A0200420A20A202200880200002A83202A82A80200022A80280002A82A82A80000000000000000\n\t00FFD6C7000000000000000200C00A00A00A00D00C00800080288200284B02282290281280280202228000201280AC02C02C\n\t02802802802802C02900802C03022802802002000000000000000000FF20AE00000000000000020000140020000124D22300\n\t00004A25354000A0C08483484480081409080010890090084091094880091000000490CA00800904A9480480100000000000\n\t0000000000FFF775000000000000000011801831911801923901800050600640609600C00441610C01600480E00021600E0400d3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t7E6B0000000000000000AA4AA0AA0AA0AA08028800002A82400400400A00880A02A02A82502880880501102A82882200202A\n\t82292A82A82A80802A82082A82A02A92A8000000000000000000FF46C4000000000000000354354354354354332330000055\n\t0C08110C40C00400D20C40D10540411020450550C40950D10A50D50828D50D51510B00550B08D30550D50550000000000000\n\t000000FF06F10008000000004004000004004004004420440003001011491481000001010011001101821800200201001021\n\t111111001100001001001400000120001001000800000000000000000000FF45200008000000000000AA0AA0AA0AA0AA00000033c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9114A8800840\n\t800800804A00804140805025000004000000000000000000FFB3FD000000000000000000800800800800842A008000002082\n\t448202012202002102042002012100A02A0200200200200200211200200200210000281200250A0020020000000000000000\n\t00FFA1F80000000000000000AA2AA0AA0AA0AA0100AA00002A81080800304114406092202882002206011010C82A80882204\n\t002A82002A82A82A80012A92012A80102A8AA8000000000000000000FFD70000080000000000000000000000000000000200\n\t030000C02400801291100080080210091401031010000884000400800004000000000400030000400008000008000000000000b3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010092112010\n\t81109611001280221021001291001000048268231018200011011001001001001001101041009004000000000000000000FF\n\t6402400000000000002000C00C00800C00C54C00800110312321148345314348300214304340314100300A00240212300250\n\t200300300300304100B00300B003013002000000000000000000FFFC390000000000000000818D1841803801801801080043\n\t62060C000E00600603632E20E50E02420024C4A420E00E206086006546206016006000106006206206006006000000000000\n\t000000FF9EB30000000000002002000012002002004890010001004A208008893448D51208088008D488480812C024800A200073c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF073C\n\t000840000008000092000010042000022080024040004040028804052040603040608040001021048001040614003020E010\n\t0C0000100410540280308080000288000000000000000000FFE21B00000000000000000181004100180002200010002000C0\n\t0800040C002804E04810E2084400084443284040060081041062000080080000400000002802000000000000000000000000\n\t00FFBD970000000000000020808A080080280090880080000A200A02820A2120802C20021420C000602014A0124220024921\n\t021020AA21241201200008A00200A432002002000000000000000000FF49744008000000000000004004000004004004000000f3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020004002280\n\t04006000156140006006084356000000000000000000FFB3310000000000000000008018058018038C584080002860060400\n\t444062242064540A60042C640008420E00004010204021620210A24C00E00031610404E216004516000000000000000000FF\n\t431100080000000000012580188380180380992009C00862C60200343C610C18E2840187040A22200540020004B800601400\n\t42160460A412641000E004026006024006000000000000000000FFCA3F000020000008000048801909825801811800140000\n\t650420050401601405608420004400204A40408220810642E102082006006104046002026406506106044006000000000000000bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600002604\n\tE0060060A604604632608028600408402001620E0000010C8006006400006002006006026806000000000000000000FFC7DD\n\t2000000000000000AB8AB88A0AA0AB8AB8AB00002AE2AC2A82A40062262161C22882AE4CE0402B63443322882261060AA402\n\t0022AE2AE0000460062AE2AE516106000000000000000000FFEFC40000000000000000008018010010018018010000006004\n\t00000620610E006042000007026C8000002C00204600E44E404152882006006A8020640E00600642E0060000000000000000\n\t00FFA18700000000000000000180182080080180180080000060060000141360040D621402600420604000C0861100060821008bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF5F9E0008\n\t00000000000001801805001001001801800000600600101450611404640800600480810000400000400610E4160061140440\n\t06006900316092006006046806000000000000000000FF5FA600000000000000015595595515515515595500005565545504\n\t842864A434E00051628400041404C5504445104C60A45504CE4065565560844D64D6556556296556000000000000000000FF\n\t5A4F0000000000000000AB8AB8A80AA0AB8AB8AB80002AE2AE2A82A404E2263060062CE2AE1062003262142244AE2220464A\n\tE0205102AE2AE4000062222AE2AE00622E000000000000000000FF5974400000000000000000801801001001801801800000004bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (63542CC00E00\n\t600000628200600610E006000000000000000000FF9A8B000000000000000000801800000001801801800000600400000212\n\t601412421000600D2002004A000610222008610E400004084006006804086002006006016006000000000000000000FF1FB1\n\t000000000000000001801800000001001801800000600600002420E00640604400612602409000400001600600E224006154\n\t044006006280016152006006486006000000000000000000FFDE280000000000000000AA8AB8AA0AA0AB0AB8AB80002AE2AC\n\t2A8A9E0062B600E4942AE21709D00000C2A82360882220040A820620E2AE2AF0042262062AE2AE027AAE000000000000000000cbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000006006\n\t0060260060000240044860C4046226516046004116050006006000006406006006004006000000000000000000FF281D0000\n\t000000000000AB8AB88A0CA0898AB80980002AE0140000A02AE2062AE2A428E24620200230022222608E2440060AE1040042\n\t262AE0022AE00A2AE2AE2262AE000000000000000000FF11B600000000000000000080180000004180180180000065040000\n\t020060A600400C00610600204408000200600000C416000004004106006004006022006006006006000000000000000000FF\n\tA6D70000000000000000018018200200038018C5800000603400020800601400600002603413000005609610A2460C614620002bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (66CA00000000\n\t0000001800001802004043801801800200602600621200614000608800600400600200000000A00000650600000600008200\n\t4006006046006006004006000000000000000000FF6582000000000000001A018AB8822C00AB8AB8CB80002AE2AE0062282A\n\tE2AC2AE2842AE2AC20600C02E20428208E00650E2AC2462802AA2AC0002AE1062AE2AE2AC2AE000000000000000000FF9E4C\n\t001000000000001D5415593051011195594D80005564860060A255641255644255649054C02425654E52635051603655044E\n\t4D045255600455650E556556554556000000000000000000FF764480000000000000190980181000C001801801800200600400abc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00080602E004\n\t8361070278A6824006000000000000000000FF96F00008000000000018318018A00040018018418001006806006004006000\n\t0061100468041260060540560CC0260C414640414F104006006002006006006006004006000000000000000000FFFEA80000\n\t00000000001D02201C04100401801805800200600400601600600600600600600000E0110849060060004024120040060300\n\t0200600400648E006006005006000000000000000000FF1D960000000000000018458AB8480280AB8AB88980022AE2AC0063\n\tA42AE2AA2AE23228E2A831600420421621628E04A0060AC2062042AE2AE0002AE0762AE2AE2AC2AE000000000000000000FF006bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (342462120080\n\t5244804AC8620000000C42A1000B208404C846002002226008026016526AA6046006000000000000000000FF2A2980000000\n\t00400008804418000000418018018001A2E00600708602644E007A4E2264A200440180602608C08002C00601411600F80300\n\t4010506016206006006006000000000000000000FF4CE4800000000020000C81C01C205084018059059800A2E9540B649459\n\tE026216206106A8206408100120400401E70400204428E80700240600128E006106C0701F006000000000000000000FF73C1\n\t000000000000011C01801820608481C01C0180000072070A40450060044A608400F00D30608400440E42420000432600524600ebc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t001120001803009001883803800040600400602408628008602010620604428000413008000800030A084000008008126400\n\t136006016006006016000000000000000000FF80FB000000000000001281861809501003001801888020E5C4086684206008\n\t14638018E0262240280042403004262204C202408001420009E02000E30600600608600E000000000000000000FFBFAD0000\n\t00000000041C00001800020201A09C81844000744F22601702602224000A04090200600025008803250608A00400C0061020\n\t834043081060072AE506006006400040000000000000FF9084800000000000011801C018002000C180590580000060140170001bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801000000000\n\t00000000000000000000000000000000FF749580000000000000003000020040000A00000000000000300A02080000100061\n\t000260100880000001100080460200D0006080010048048480000000000000010000000000000000000000FF170200000000\n\t0000040200041C01441003009801854000E08C10210C0060244000140501264042A02344000000A64B000E00C08008048621\n\t60C00060060A6086106006200020000000000000FF33FE00000000000000042180180B01100188390588000064442424444C\n\t62940C03440004060040080040404B0210000406124000014014046010026206406406006006000000000000000000FF29F0009bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A28A28A2222A\n\tA2A220200002204228208A3022CA2AA2A22AA0221320802AA2AA2AA2AA2A22AA000000000000000000FF3EF5000000000000\n\t00842220022000000040000000010000000410010003200000A00001000000008800C08082200092200000100A4240800001\n\t000001000000001004000000000000000000FF18E90000000000000CEA448AA8AACAA9208AA8AA80002AA2421020A22AA240\n\t2C820028A2B227200050A30223248A29A2002AA23A2220026024002AA2AA2AA2AA2A02AA000000000000000000FF28CB0000\n\t0000000004010380000180190100000000000001042080040001400460480060040000202C40241042060040000040001042005bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000888\n\t108AACA88888AA8AACAA80002AA2AA212223AAA00228A00228A2022AA00000A0122622AA24A00A0AA2AB0120022AA0032AB2\n\tAB2AB2AA2AA2AA000000000000000000FFF4AF00080000000000050840120040000040100100010045084009408040040041\n\t0C00000008004101440D04004002100400000000431080000100400500480400D004000000000000000000FFC4C610000000\n\t0000125C81D55915F33D55D55955800155755650755655601655441655744E55600924D20550611750608E5564C620411655\n\t6300556556556D56557556000000000000000000FFE1A50000000000000888008AA8AA8AA84C8AA8AA80002AA0020322122A00dbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200000040\n\t0000020000000000000000000000FFEC5200000000000000000404005008001A000300200000080188080025014000004100\n\t08900C00000103D1800010018010000000400400000012000628C40400000000000000000000000000FF6F72000000000000\n\t02043040020004400000000000000000000B0080000088040350041000000000A01110888001020040200000500120000280\n\t801000800000000000000000000000000000FFFB551000000000000041020000042002002004000000801000000810000420\n\t0000000001480000080C0220000000100480000001050210000000000000000800000800000000000000000000FF5DDE8000003bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04454E006507\n\tC8E22A40E4C6204406C260060D430EA9681043400014702F444006006000000000000000000000FFB61C0800000000210010\n\t0020000020522510B0004220A800046340D4A04605D94A002E00C0880B881202010EC020090011CA5A000240880040018044\n\t00004804044000000000000000000000FF825B1080320048C0C8095090C9108408808308D0952010A08220208A08352200A3\n\t02822422402000493002002802A2300202A48240A008A02000123002020002002000000000000000000000FF255700000000\n\t000020000020004020400010220000000000000080400000004C084880080001052B8008404202000000082800081000008500bbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080080080080\n\t0808800829000900A00000280200B01001408000080204200200200082201200600280200A082083222000002AA800200228\n\t6202000000000000000000000000FFB1501000000000400000000004000000040102002420400001220884200C3000081050\n\t0111040548010AA0110820080540800408000310800800000000000000000000000000000000000000FF173C000000000800\n\t818804858C40800A02804800800090300200A80A04280A10244A00200211B821182002642992812AA204208A0020000022A0\n\t00247A0C2802002000000000000000000000FF757D1100540059419019519159518C1B0984D95192C01171071041075040C6007bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (046947006007\n\t08E080000000000000000000FF0D1008000008180180180180100100180300B80400A022401600A40C228004000006000054\n\t2061000062061021062260020804A620600010200020E006120006004000000000000000000000FF72090000000000000000\n\t0000000000000000000000000000000000000000000060000060000000000000000000060000000000000000000000000000\n\t00000000000000000000000000000000FFF5D300000000100000000100000000040000040000000000000000000008000060\n\t00806004004800004800800806000004804000001001000000000000004000000000000000000000000000FF52410000000000fbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A408004C4123\n\t2008650651600E0008A400234200E00108A2000060A5100006114100000000000000000000FF9754000000081821A4184180\n\t1001B5180510B815A0800641060CF00A26E09400600E206014076008B3A106804086287202184408A0600054200232E40402\n\t0016104000000000000000000000FFCA4D000000201801801805A01001A05A63001801A02000600620602690740C00E81600\n\t600408600200002E00600002604000C002886000012002006000000006004000000000000000000000FFF0F7010000001841\n\tC01801801209001801021811100008680648202000015441014748080492F430D528CEA1081010650400880E0960010024000007c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (809800023A21\n\t851A251458750000042446401600A406070A7484A0E144106868142006004146A18CCC2560B8146700146001506004006087\n\t126000000000000000000000FF340B0000000018018098C8221809901821801E01200180280E909001401086026004246204\n\tC4F29000188600E208000114506000206000206048006304286056004000200000000000000000FFBEF30000000038018019\n\t10201B11803801425801848000243730800C0108A6000425820344282A80042C4600CAB004044602A0032C61010020284069\n\t0548E026006000200000000000000000FF3787090000001801801802001811805A0104180BA80048300E00020510022640100087c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (160040060000\n\t00000000000000000000FF91A8000000001801809804021861821A10081809A0801025260040028A630F0868350160400002\n\t911102070A4000000416710026116000202004A07086984037000000000000000000000000FF172200000040180180980000\n\t1801821D04201809810000200608540408040C086426047B0720C14400029400A006081006005054846200C0000440608684\n\t4047012000000000000000000000FF45EA000000003E01841800205AC1805800001801828000288602400800904C8868C601\n\t680880400400E426002000A200060002A6006000000004806006014086842000000000000000000000FFAF870000000018010047c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (64A043000560\n\t104E030088DC680611CC1410E82010400D00601702400700E020000000000000000000FFA822000000081801841822201881\n\t85181174180180002078560164420274342262B6C47A06A00000886B2531122740652FC240942A740041640410602E004006\n\t342100000000000000000000FF3F61000000001801C01802001A11801815011A41800410630701704220F0C4056216046146\n\t0200300AE094800A08807416044104036A0000400410680602400F012000000000000000000000FF3134000000001801A018\n\t00221A09801800089821A20020202600C02622E0264568840060068404064400260C4416440006025B04006001902002086000c7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00201A018418\n\t01041A012000106006806406045002006082846440024004484012A0C1015042144100063162060060140060060061060060\n\t40000000000000000000FF1039000000205804241880081B0591585050580504402060A8896906C0681720F032406916C8C2\n\t1400852200443600408602108604704648E40409612E2060060A6080000000000000000000FFB17A00000000380181984401\n\t1811801A01803A03802005600688284600644604640400600808820C00E00614000600684600401400600108600000E88624\n\t4086416000000000000000000000FFF12C00000000180380188028980B883921201A01A6004AE08610248720600640E905010027c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600000\n\t0000000000000000FF67C5000000001800001800001801880101809811815040603400E08E01604A2264042263004144C000\n\t20A4004406000086000006006406006004106006206006006000000000000000000000FF80E5000000001800001800001801\n\t8018018018010000006006006002004000006000006006004000004000004000006004000006006006004000006006006006\n\t006000000000000000000000FF70340000000018004018000018018018018018010010006002006802806004006000006806\n\t804000800000004006007004000006006006804004006806006007006000000000000000000000FF9D3C000000301800001800a7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A66B906A296\n\t01626685628C0873AE0C6006206540806486786006006000000000000000000000FF17F10000000018802018002010018142\n\t0181184115008564461469201261541564109165063148A500AC20B46A0828224601140741600600600C02610E8060060860\n\t08000000000000000000FFA60B000000001828019A224014418202118038091CA0116202B27024106B0020686000684880C8\n\t04202000926006A020061000060062060060050A601E906006006000000000000000000000FFF959000000001C4A40184408\n\t1811840003905943800104650444644342640608E09480E0100A400822AC1422504040A41700032E086006406000447486000067c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C7190180510\n\t1901040069E8021060048060028080068000060802A282605770422E29A20480600600700680400040660E00600600600000\n\t0000000000000000FF47D6000000001800001800000801801801001E01930000701000E8054068430C085700008200600100\n\tA84600400084200500FC06406007006028807106206006086008000000000000000000FFC0AC000000001900001800000A01\n\t80D80000982000000462420A614812789600640632E200A0E00800640F0AE000006024806106836006004280826806086006\n\t006000000000000000000000FF930F000000001C0000180400084180188800982280005A60B801E2986AE0AE0AF2CE66F2A200e7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (806000000000\n\t000000000000FF90730200002A192052BA40245D15A09A0BC01AA080001068A000632080F025100242810C0350EC008D6402\n\tC268C8822806432286006A86C568004060564A680E206100000000000000000000FFE868000000001800001C001018019038\n\t418C1809800020601521601748609000E01620612882011020200600600100E2A600402E08600E08604008EB060162860860\n\t00000000000000000000FFE6B2000000001800001800001A01E01801E0180180000060058068020060000068060078028000\n\t00002806006006006006004006006806006000006007807806006000000000000000000000FF9BE1000000001804001802100017c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000836060024\n\t620020A204290308300255A010082042007003082080000000000000000000FFD6A800000004190010205598001018211102\n\t002400000804014081084060600160404060A404C08821404104000601040110C0A000000828002000818002810000000000\n\t0000000000000000FF20790000000000000000000260000000000800000000840100200A0028618050640000600800020006\n\t0010330096400241000800800000000402000000080000200000000000000000000000FF894B000000121800015800001981\n\t801821801818000020600080605400E00408882220020633000000680240600616A006A3260E016086026000806A06B060060097c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (881909901889\n\t800008629600600652604600405400604600440040E48C896006006116D342060160061161108060A6106486006000000000\n\t000000000000FFE7EE000000482880414C14C10C00C00C40C00C248000023002542D5300348B29250320340B4B31290C2023\n\t44342B2CB44200212220200324340100320B002002202000000000000000000000FF65040200002042A02A022021020A2082\n\t083002C000009008381414A0900C1880081C800C00880C50D08900000808800910400840C00200800900A00C38800E88C000\n\t00000000000000000000FF5B21000000080800008800800800800842800900800080208300300404200000130200A05240210057c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF41B20008000AA0AA0AA0880880A00AA0042AA0A000000002A82302402202002E83802C82402A0000208D288A80\n\t883200402200102A80001100002A82204102A8810000000000000000000000FF9895000000200800200A40A00C10C0088480\n\t0A10800091280310200290B04300282282288280282108208240280280B002912802002002C0280080288280A8022A200000\n\t0000000000000000FF71B00000002004004012022242034004504012020000A450008140CD00109500480C80083081480084\n\t0C04000C40880D48004CD5004004950C00004814CA5004814000000000000000000000FF388200000004180010182190589100d7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80410D000001\n\t0200001000000000000000001040020000220000000000000000000000FF92170000000AA0AA0AA08C0AA0AA0AA0880AA090\n\t00003202A92400882282A82892A82A80082200001202A8300088A20008088A092A80002282002A82C90802A8341000000000\n\t000000000000FFEEB700000035415435431033433435409015430C0000A40D50CC0400CB0C10D10C00D10890D50820A41008\n\t400D50C40890D50520550000A40C00D50510900D51100000000000000000000000FF85530008004004004004004004004006\n\t420004400001001000100C211010010400010011210890104010010490200811212000A000100110100100100020800101000037c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (430012000000\n\t80100000410C8090050040008010308A091004480492C800880D4CB20104000800800C00000C44CA080080C8000000000000\n\t00000000FF694C000000000800000840A00800800800A008D080001020028122221420020028020420820020008820020020\n\t0200200201203200000015200080211200A002042000000000000000000000FF52090000000AA0AA0AA0C80AA0AA0AA0884A\n\tA00600002382A82B18002002A82A82A82886002081012182A82006A8238400040A00AA80002000002A80000412A828000000\n\t0000000000000000FF167500080000000000002400000000022040002000000880000010900001400000280002000000001000b7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF35D240080000040040804858048040040140403000C108108100128942122111168000100124132900100504421100\n\t1001001001001001009001009019001001001000000000000000000000FFFA76400000000C00450800C42C84C14C00C00820\n\t80810C353300300302343302314214B31310343300320300240300320300302301100150300308B003103023013000000000\n\t000000000000FF6F2D00008000980000380980181190190D001801820020600610E4AE09608620400620600620E00034C084\n\t51400608E00600E10608000800E00000608600E006006000000000000000000000FF90D700000020040020020200040140120077c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (14220E40E006\n\t0862064800000D640002C046104004006000000000000000000000FF9C4A0008000000000200540C00000480000001100CC0\n\t0504A00A00001562001061203060C00204480102000080A61000300001200200000900A04500201082000000000000000000\n\t00000000FF555300000000180002102184500209209000400804004404101080403061083160242CE10C00C0804945005080\n\t061104000000A009001000400010008010C040008000000000000000000000FF19C400008000880000680080080C80090680\n\t0800802000203201040440A1400204120026021B200002200202240A05210001A0020001002C20000024020020020020000100f7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (182C80000040\n\t8600408A00001004600800633620604000605602E20644208600E00600000010200000600600600400600000000000000000\n\t0000FF9A9200000000100002180184388D813903809880090002420644E08620420002600010630E0CE00000021600E14000\n\t200A00E00602008000610000620600E404006040008000000000000000FF2DE100080000100200180580388988382882F810\n\t800039400420008001001C33810000800E20601000618A0A2008346742086346298000006240404006006184006020000000\n\t000000000000FF7D8000000000000400382990180192185084180002202041500802040A4144200450210026406220008002000fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFD763400000000000001801001801803E01001801000000608000380200228600788002609230A08001682E006200144000\n\t054006000000006008004007806006006000000000000000000000FFD1BB0000000AB0000AB8AA0C38AB88F8810AB9408000\n\t2AE14E2AC3142AE2222882002E81024B24002202062160881840042042AE2A82A86620002AC2AE2AE2AE2AE0000000000000\n\t00000000FFB83D20000000000000180101180180184500190180000062420040240020820000C000000200AA001080868860\n\t260144500C400600000000E820004006006006006000000000000000000000FFCD8100000000100000180082180182181180008fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (882002AA3242\n\tAE2A82A82AB0002AE2AEAAC2AE2AE000000000000000000000FF379100080000180000000100400180182380180300040064\n\t1200404400608000600E00604404400001291110002600C4160A600600000001600000400600200600700000000000000000\n\t0000FFD857000000154800154155114155951949955945000055644A55435055200C51644E51642402401414250155015040\n\tC552406556550550556004554556550556556000000000000000000000FF19FC0000000AB0000AB8AA4918AB8A9C890AB808\n\t80002AE0042AB2032AE24E2AE34028E2121020402A622622628E4201202142AE2A82A80828402AC2AF2AE2AE2AE000000000004fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800010610243\n\t40420060040065560260040140204821200080060960860460060000000020C000E00614E00E006000000000000000000000\n\tFF55620000000008000000000000018418C180184980040062D200410A80202000603600633420410814202080002008E006\n\t00E006000000002810006006006006006800000000000000000000FF92770000000018000000000240018018058018040004\n\t0060060044440062020260040260000080000021140042060440020840060000000020000060060060060060000000000000\n\t00000000FFE1390000000AA8000AA0AA2C80AB88BA0D8AB89000002AE0062AC8002AA0CE2CE28028E0000A100060BA042AC000cfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF9F\n\tC2800000021801800150001801801821801883000000411608E00600644600610202604C00C00040400E0062060160360040\n\t06006006006000006006006006004006000000000000000000FFD89D0000000AB8000A80A80A80AB8AB88F8AB98000002262\n\t320863062AE2862AE00428E2A02A000002220A22208E2262262C42AE0000002AA2002262AE0063262AE00000000000000000\n\t0000FF63B1000000000800000000000001801821801821000000E00A00608E00203200600600601000030400A00210222000\n\t600E014006000000002004086006406086006000000000000000000000FFFAED000000001800002002004001801801801813002fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E4062AC2AE00\n\t600644A2102AE2AE3562AE2AC006000000000000000000FF844C00000000380180482400280180182180180180000160260C\n\t60020001000060000060040080000480060244000061160860060060060044400A600628E006004006000000000000000000\n\tFF12890000000898018AC0040A88AB8AB8958AB85180002AE2262060920AE0882AE22828E3042C45080C428630C0AE2A6086\n\t2AE2AE0060060964802AE2AE2062AE2AC006000000000000000000FF4396001000551801950B101519559559119558350000\n\t4C648640E44E5504365364D253654C5463403064C8516130556446408556006006554106416556046456554006000000000000afc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006887006050\n\t20000000621442728C82E00080640600600000600E00F10F006006000004006407807007006006000000000000000000FFFB\n\tAE00080000380180200200400180182A801825800200623608E00440649002655400702414600C4860201340064060CE0060\n\t0600600608008000600610E806004006000000000000000000FFCB97000000531C01800B00000801C01800C0181100000040\n\t0604652000000600600400610C00E08000E108006240126C0680000680600644200880600604600600600600000000000000\n\t0000FFCD420000002058018A82280AD8AB8AB8808AB88180002AE08624644C4AE02628E0042AE20420620003624024608E00006fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFE23980\n\t0000001821815004001A01801C01011885008001408608643405031644844A2312C600802028C24200601000640600C00600\n\t6000002000006206006006006006000000000000000000FFF58F800000001881803C00001841801901109801004000E04614\n\t600200040E026006006027200101A9610813610824E045800006007806406001847006006106004006000000000000000000\n\tFF1167800000403C01C01204001801C0182140780100201E742661E5021561665161C60170072000C08040C20060E63A7424\n\t80008E80660620600113E007046886004006000000000000000000FFBC9C000000403841E10800000401805C20C01883810300efc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (21612E406092\n\t2020002A6002086506106106000000000000000000FF4D9F000002001801839A030018238418C5801801082002602601608E\n\t00E00000602600608820000800001000E02001600000E00E206088202040006000006216086006000000000000000000FFDB\n\tD60000000099818018010A18C1825923901800820008E60626E3025200A83060062A603004022020029215608621E01A0062\n\t060060020A20001A600204600E004086000000000000000000FF7362000000401803C03A000038118018012D593500810060\n\t0F00602450600614000A00020100010005004E4C60061065444050C691600000242040682690E88680600610000000000000001fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000804060\n\t1000610004604C0140002040C40000060005140100000004800100C0000000000000504000000000000000000000FF61A080\n\t000000000011060022C000000000000012000000000000002802612004602800630028023015041034840600004002000000\n\t00485404000004C8000000010000000000000000000000FFBAA1000000201801A01C01405891801801801810050008402642\n\t64043080100000125200200002880004062AE0061061320064060960000C220000602200E006006006080000000000000000\n\tFF26540000046098858450050A1843801881953945882004E2160060C80461202C002200030E200040448142006140406404009fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF3C28000000\n\t0AA8AAA8C8AA8C8AAACAA8888AA90880003022AA2AA2222AA2AA2AA2222AA28220A0200A23024C228A2AA10A2022AA2AA12B\n\t0AA0202AACC22AA2AA0822AA000000000000000000FF184900000040000000420045200000004240002C0002000000000014\n\t02008000100C0010290A0001200128000240000300021000000100088080000001004000800000000000000000000000FF2D\n\t090000000AA8AA8628AA8850AA8AA88E8AA80480020A22AA2AA31008A20028820228A0521620004020520020AA2AA4022C22\n\tAA2AA0024021022AA0122AA2AA4622AE000000000000000000FF1F4B00000020180020180180180000002000012000004080005fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010000201100\n\t91000008000800000000000000000000000000FFF3DC9000000AA8AAEA8888808CAACAA8888AA80A80022AA2ABAAA00A2AA2\n\t8228A30A28A0030220000020022AA08BAAA0420222AB2AA2922024002AA2232AB2AA2AA2AA000000000000000000FF7D2100\n\t0800400001200400401201201020401040000205000400400400000400511400100500020881400000804000402009080400\n\t4400804200004801004004810004000000000000000000FFB86F000000555D55951D55D01955955911D55881800055755655\n\t654631643455444455750441644914D40655611655701651755655644644401155654E55655755755600000000000000000000dfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000001A0020\n\t10000404088902400808000301001080A0000040A08000000000000000000040020200000000000000000000FF0499010000\n\t0000000040040040003B81862802002040400460008000001440010009008480060000500840240140A21300280010420000\n\t180100000300120200000400000000000000000000FFD0EA0000004002000022204A42004000022000800000000800000040\n\t000040020000020300280048150410000400000040300800000010020400000100800001000800000000000000000000FF03\n\t5308000000000000000400000000002000004000080000000005000000100000C00008488104012010C0000040000D100100003fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F10000000818\n\t0191580180194594D135CD581188825168CE15641650655784401641650E49600010680640E01645710E28442602D2000162\n\t00006257026226006006000000000000000000FFFDE702002000002000000002021840100108140102800CC00402C0848480\n\t8C685281B4886C2486690200002C050938844008400040480010422808002402408C44C404000000000000000000FFB03500\n\t000010080091280080094280481082480080004020030C340A3220CB02200230202320200080200280221200281280240280\n\t240081240000204A802002202002000000000000000000FF1F3F00000000000000000000001000064000801031001318880000bfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000000080\n\t0000000000001000000000000000000000FF41BA000000000800800800800810A2888480080084000522AA00500080200140\n\t080210A20210200080308302201210A80208200220A000080080002084084102012206000000000000000000FF54CB040040\n\t00014010000000000020000010020000405000000308840082B008821020004C048A30B00000A90000800000000008804800\n\t004230820000000008000000000000000000000000FF3B47010000000880884804844A00920C00C18818810202208A802803\n\t80200200310A08298248200005A0C280A74246211B80200206A00086200012204205A602003002000000000000000000FF57007fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (826104200886\n\t00005711644032408A04E05080604304600600420080028800688CC06806006006000000000000000000FF8AE10000000018\n\t0180180180380190180180182180001062960441240000240304464002060061000120060064060061020060A60000000020\n\t0024E244004206006006000000000000000000FF61C900000000000000000000000000000000000000000000000000000060\n\t00006000006000000002000000000006000000000000000000000000000000000000000000000000000000000000FFA98300\n\t000000100100100100100100020020040000000010000000000068000060008060000048000040040000070000008040010000ffc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000188180\n\t1840801800281801C158498000006046C04A0400688220088840000611240128701602840EA0100700214400040000629004\n\t594BA05406006106000000000000000000FFC19300000004180188100080330B219811801C01A0000A63C7826CB22B082042\n\tE2260862860068A800A0028060B61872E23860060D1100600000A1E050082006406016000000000000000000FF77B6000000\n\t001901801A00801A01407861985891800100700E40F00E51F00000601610692E00681082088100610056641A526006960000\n\t400000806200106186006106000000000000000000FFD319000000001801901841801815811801A09901C00002602601420800002040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000806006\n\t046506007916000000000000000000FF95160000000410218611AA001000281AB3881D0180024062166CE0020460860768C8\n\t81619644280800601A2C008680028626340C206E28406003016102801006406046000000000000000000FFD3810000000018\n\t238018080019200898C1C01803808212E3261060228000062064082062060820CAA06080B0832000010E5021410071118260\n\t2000405200600602E006000000000000000000FF4505000000001005801800003842001C01801E858321CD68160240248200\n\t02008A20310C2ED420C24061220482408000170024A400400084602000610204148602E0A6000000000000000000FF96400000802040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0200640410E4\n\t2E2A0408084000010C06040446044000012080204101806202082086026006000000000000000000FF1E1900000000480180\n\t0D04820801C00809805809C00000611618400002023F00E0440CE90600024005C1A0000040C38216804240D0208008468418\n\t71F6002006486006000000000000000000FFBC46000000000801800C00800801800911A11809800088680680C824406CC040\n\tE004006806014082206848000006000002C86407807000084050006806006406086006000000000000000000FF1DFF000000\n\t000801800844804805800805881801842800680601440880808400608490684600480080484680000808042200681622A04000402040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004803880900\n\t0800A382088380D921C80000608E01E03620800A40682700646E38000074680101E00808F2070CE04020200000E084027006\n\t100186006006000000000000000000FF36FB100000244A01840210604801809C29821E01A130027C062270020070040B7C86\n\t44708600DB0002E12E086C27006032206227016480004230004002001046106116000080000000000000FF7C660000000008\n\t01800802000841A01D41811841800008610F0064A240108000644682610EA4C0AA00601700622040702A506006492000A040\n\t28004C16000C06226006000000000000000000FF9775000000000001800800820821A018218018C18010006006005514046000c02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000068070020\n\t07006006000000000000000000FFA6CE000000000001800210200001809840829A0180020464870260064100020061062060\n\t9050200440100600621000604200E04680680000E004006206006106006016000000000000000000FF308F0800000440058C\n\t0020204045841885803B21910300600EA9604E007897517416056C208425008B008C88E046936006D06D0EC16C008864A845\n\t6016802026906006000080000000000000FF9059000000200201800220100101801011D83881864100700688600E00608624\n\t604E00E20683000008604600600602641400608C062100E8600020E20A60001E006106000000000000000000FF58C500000000202040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (625632692010\n\t42045008268400201442B140480704E040C56004816006003006006006000000000000000000FF7CDB000000000001800800\n\t000811805801811885835008642648401455640200E10601621004C00000000641049620600200C00E006000006000446406\n\t002006006006000000000000000000FF46E30000000008018000000000018018000018018000006006006006000000006000\n\t006004000004004000006000006002002006006000004004006006006006006006000000000000000000FF61AB0000000008\n\t01800000000001A01801201801A010007006006006006004006000006804800000804004806006806002802806006000804000a02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018000088000\n\t00101821C11091822102E2CE6CE02E2AE22E2AE8EE4A702E02E7680A244C23009E2842AD2060064680202066000060038030\n\t46006406000000000000000000FF8FC6000000000801800800040A01A11AD08C1A059101286416114494C5055492ED001165\n\t5235000C42410EC400C00CE09201000680E04000E014006007026206087006000000000000000000FF403E00000000080180\n\t0A10000A01D0380198BA0BB88029601600440400604080720080608260005024403600002682600200800E00600010E40022\n\t6006006006006006000000000000000000FFA56A000000000041800800000805851B40A05851800042608605512500010E3400602040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000000200\n\t6006000000000000000000FF2A5F0000000000418008008008141D1901A81841A00000604604450480610B001006C1040490\n\t6A00A23028810C8E806086806006A0A00094C000016402022206006006000000000000000000FF321F000000600001E00800\n\t840800611881801C09800048645600400540080302010748028D007089002084021000016002016007000020006200006002\n\t002026086206000000000000000000FF3EA9000000000001800000800000001831C49003910000600632E2960304A608E446\n\t00E04634E0400022064080410A6017006806022000804010806002002006006806000000000000000000FFCB1B000000000000e02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000A802000\n\t0068000861064160260020A62060002A6400326024004000806006000000000000000000FFCAB7000000280B41A80A8CA82A\n\tC1851D05A95A939400826CAE224CA482F025300A00808C4A082C30A86540906800806912A92A2ECC60008C6A80D06B348049\n\t30227246000000000000000000FF5A0C000000000801800400808009081829801A01C00250600601780608628800E0810860\n\t8220E00002F0002460492C402400210600A22040601002600092020209600E000000000000000000FF279200000000080180\n\t0000800001001801801801A0060060060068060008000060000078020060000068008060060040000020060000008060000000102040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08808008408C\n\t0808088C00920010310B0000C000202010010000200204224040200200200208218220210210204000210008249205240A00\n\t2426000000000000000000FF351B0000000018018019418C1801800280004000000028000040101017E11000E40008EC0021\n\t81000E4484000066060400080000C640008000080002005A1200400040000000000000000000FF0F50000000000000000010\n\t00812060803400208400014002308112000066482072000060E000040810123001000E000008449208088020410281010100\n\t0000001A8000000000000000000000FF59E60000000009A584080E802881801900841909800000604622400400008449008000902040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A00000804004\n\t000000000000000000FFF09F000000001801801885821801851801803801804080644640641610650E004004106006004400\n\t43600440613642600640600608602040600000E106226A16086826000000000000000000FF20BE000000440C84C44C50C00C\n\tA0A04D0CF209048C0028208A80A14322B02328A2C3203A230330A908240B03300300B503022083A5221110B48008340B10B0\n\t03403202000000000000000000FFF75A0000002C02002842002002084340025004020C4082148100C524C80800800840D002\n\t00884830A18800E60810A008008008000106101008008008088000B1200A08000000000000000000FF8F200000000008008000502040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010910012411\n\t41001401101080000C20101001001008001429021001001800000000000000000000FF16C40008000180AA16004000008220\n\t00AA0AA0AA00062A82A82102104882082882302882A82A08204800A8220088220128200210200000100000190220160AA8AA\n\t82A8000000000000000000FFA53E000000322A00A00B20A00A48900800A00A00800080280204A80AA0284304280A80280280\n\t2010A0300300AC0288300294208280280000280880290290A002002002000000000000000000FF6EDC00000020020031420A\n\t34C20004D2010002010000004804104944841105004884820000814800848A04900820810C81010854128000AB0800A3481000d02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04200820A200\n\t0000000001001000001040000050001000000000000020110408010400000030050040088000000001040001009000000800\n\t000000000000000000FFB27F0000000A80AA0A80C00A80A80002AA4AA0AA00002A82A92A80B00880082A82202A8AA8240030\n\t1104002A00A8230210A310010200002B00002A80001082A82A82A8000000000000000000FF0C910000003003542003103103\n\t420C01545545540000550551540500950D00D504C0D50D50D510108208A0D40930CD0A00D00C80C40800430808400D504005\n\t50D50550000000000000000000FFD01F0008004004004044104004040102000004000003001000800401200421000101000000302040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060060000\n\t00000000000000FF647A0000002022002002222002401012012012010005005004004844C008090449148400009408308492\n\t05114820810804090004A00804800810804810A44804805004000000000000000000FF03CD00000000080080480080080082\n\t2800800800800000200200250A00240200200200200200A000202002002202082012002CB21220021080000024A211200200\n\t2002000000000000000000FF2F5E0000000AC0AA0A808C0AE08A74C0AA0AA0AA00002A82A8AA90000E91A0289230288AA820\n\t00000800B82300882202E0B201104180002200012A81004002A82A82A8000000000000000000FF594E00080004200000A00200b02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A04008210208\n\t20820C202242204200200001000040200211A002002006000000000000000000FF4696400800000000000040000000400440\n\t400400008108108102D2C84094A1001020021081381028201009620010001001201081001001001001001601005001001000\n\t000000000000000000FFF58C400000020800800800800904D00C80C40C40810110B5034031020131334934324CB10B403028\n\t40340B0820420032134030C300300308900100308B003483043002000000000000000000FFD85D0800000038019038018458\n\t0180380590D801942040604405620E12600604408600622603600011604404430611612404600E0060C6200000406046016000702040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000418258018\n\t0980000060040040045084860485040044445460400140400802060060401040060163144884080060861060064060060800\n\t00000000000000FF482000080000000000000008008000C00210200210402002800000000361160264402060002000882400\n\t005102A62100900080802082201002100C8010240000200000000000000000000000FF504200000004180180180184580388\n\t01420A00000C200004244000002C641651629051643004400001422400442E01048800004800012051000040013400048002\n\t0000000000000000000000FF4A8408000000280088286084088084284080A830800020A0420001645024420200000120020400f02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (680600000000\n\t0000000000FFDACD00000000180101580004580000184584180180A000600008600240011600609000604C04200000410610\n\t64460464800160064020003000800060060960A6006006000000000000000000FF3C98000000001801043800001840001801\n\t90380580002062000060CE006006006000402004000280004000026020134410206126006044000000086016246006006006\n\t000000000000000000FF584700080000180102380190182001580180186190400061440046080460567880C4190224082210\n\t44C13E43211848432009400640608C2000004560E601601E006006080000000000000000FF3DAD000000001800001841841900082040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2B40062A428E\n\t08C28422E2AF4000020002002AE228B2E2A62AE2AE000000000000000000FF48880000000018000018000018000018038018\n\t01C0200060070068020002860060A600282C88810000420600C00000402C106007080006000000006080A0E0060060060000\n\t00000000000000FF82BE00000008D8AB0B58A80858820AB8898898AB80402AE2ACA043040A82062A82022A82862826002A44\n\t2822608860600C3242AE184000C000002AE3A02262162AE2AE000000000000000000FF916620000002380000180200984800\n\t1801803801A00400600404C12C00604600004200400601690001420000C006114026084006834004048C0000601200600E0000882040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B8018AB8AB80\n\t002AE2A82ACAA828808628E22228AA0624100438002C2266882AC40628C2AE2940002A94042AEA108462262AEAAE00000000\n\t0000000000FFE230000800009801821802011815801831815801800000600400C04C00608602600002712604080000615400\n\tE04604604E00400604A0040C8880007000006006006806000000000000000000FFA7F7200000155954955954155913955951\n\t9559558102556554554D50350056556414533506C064044480AC54615055408444C556426004D501045564428864D6557556\n\t000000000000000000FFDDFD0000000C18AB0818A80C18A00AB8838A18ABC0802AE2A9346A022CE22E28E34E28E21431208000482040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFB497000000001803801824001801801801801801805000650C00608220600600610000608E52E08010E0A444E026\n\t0CE006006006092112000202006228006006006006000000000000000000FF358700000000180080180000180180184B8018\n\t01A14000600400600204002C026094002126136C0402610410604000640E006006802002000A0400614220E0060060060000\n\t00000000000000FF0345000000001801801800001821801881801801801000600680400400620600600602601600010000E2\n\t04016006004146044006030000000100006010126096006006000000000000000000FF3B830000000AB8AA8AB8AA0AB8CB8A00c82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (044061501120\n\t0640E5544125540044065562C6552556552556000000000000000000FF1BAA8000000018C380180000180580100180180180\n\t0000605400640620600600604640400200040000200408600400200600600428A02600408000610600200600200600000000\n\t0000000000FF65A40000000AB8A98AB8800AB8AB8AB8AB8AB8AB80022AE0062162160CE2AE2AE20628E2040060000000040C\n\t408E2061062A62AE3602020000002AE0002AE2AE2AE2AE000000000000000000FF567D000000001800801810001801801801\n\t801801810200602614E04E02000400604A04202400020444040C0044000064AE01600600004200008400608000600600600600282040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8AA8AB81102A\n\tE1062A801808E2AE28E78608C2AC40000000205421208C2AA3BC2AE2AC0025860040002AE2362AA2AC2AA2AE000000000000\n\t000000FF4114000800001801801C00001801801001801001804200608400610200000600600C00004820420001202C08E400\n\t2262520A600400200400408400600E002006002006000000000000000000FFB96D0000000AB8098AB8AA0AB8A98AB0AB8AB8\n\tAB80502AE2042AE0A60AE2AE2AE00C0AC2A80AC0802B22842262CC2AE2222AE2AC02600E0044002AE2262AA2AE2AA2AE0000\n\t00000000000000FFEBD1000000355B55D55B54355D53955155955155810055642C526446510556536546550482150086540500a82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF8CCC000000401809C01C08401821C00005905244810588780801014009001600604C12C09000000120E08C45202C0061\n\t0E08703101202C406005006506106106027006000000000000000000FFEA1F000800001905801824001C01800001A0000081\n\t0000640800012420600604602C044000D2808010E0A412A44400600600600431600C00650000600E00700600680600000000\n\t0000000000FFF543000000401C11C01C1040180180020180080180200060A6000200040006006006204804000205442C0C00\n\t2004006004806000042426004004006086002005002006000000000000000000FF3FEC0000004ABA21AAB8804ABCAB8AA0AB00682040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000C41400000\n\t601302A10E2020AA00600601652610C046240000000000000000FF4D96800000001801801810001C00001801905C05908005\n\t60444884001004A010002640421600E0C08028000304842440D000682200E40E000000C06406082087000806000000000000\n\t000000FFBD1D800000001C01841800001C02001009821D018000026084406402040206126006004046082000005446002304\n\t004006416106004006006000256006006007004006000000000000000000FFFDB5800800401A09C21C00401A22001A09A01C\n\t01900109704416608242E14E03E186485426892159104A2620200444404720E006004406004000006086602C07000806000000e82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (811000006016\n\t01004051654010040400400240610822652610441450600010610000610E00E0500860044065062060464000000000000000\n\t00FF8A7D000000401849841ACC0018A004000180989008000060000060060862060060040041061460883160900840840660\n\t00006044012006002000486004266046144006000000000000000000FFF9C5000000081821821822201A0200880D86194902\n\t800061960060EE60808E0060940FC10E0860005BE1162042740860001A61B400206640C00025600400240426000600000000\n\t0000000000FF6AF9800000401C01C01C005218104430838018018003486C140084040060200802460043062360020024500300182040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tDEC6000000401A01A01801801801914000054000008000000400808802600604600800410000421010800C08000400000C00\n\t000C0284002001000000C4220004008000000000000000000000FF8806800000000000000600400400040000100042002000\n\t00A81200004060060060C00060280081000002800500061100C00000801000900800000004081000C00A0000000000000000\n\t000000FFA89D000000201A01A01C08501C0401590D851800030048628000048C0000100000C415421201600000600022C0C4\n\t016000046008042046202100006006014006016006020000000000000000FF3122000000481E11E018800418A8001801801800982040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00F4365572C4\n\t4D4556526401556D56B07D56557D56000000000000000000FFD05B0000000AA8AA8AA8AA8AA8A8C22AAA832A8A80202AA0CA\n\t22220228A28A28A2422AA28A2A2488C0A4C22222AA2AA3122AA2222020821120802AA08200202222A2AA0000000000000000\n\t00FF8ECB10800040020040040040020000000052002000408010401203480200000000002000800085100804490902002800\n\t80001008000000008100800000048001000004000000000000000000FFC9730000000AA8AA8AA8AAAAAAAA8100AA90008881\n\t002AA2022043240CA2E82883102AA2462B20002620323002AA2222422AA23220642202A6002AA04255A60A2022AA0000000000582040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000484\n\t000000000000000000010000081100081000000900100000080B0000500480000000410000500000000000000000000000FF\n\t5FD48000000AA8AA8AA8AA8AA8AA8C28AA80680080032ABE0229208A0AA28A28A2AA0AA24322A0002020222220AA042203AA\n\tA0020022AA0220002AB2AA0022AA0022AA000000000000000000FFFC0F800800400400400400400404501201401220000300\n\t4A0408C02C00000404400400000480000088100501400000000000508412C028440001005211001111101004000000000000\n\t000000FF5826800000555D55D55D55D55D53913D55811913808055611440400651655455455615640CCA600043790444615600d82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFD446\n\t0000000000000000002002000002A400022010484800800204080000080000204B0020100000000010030010040800280000\n\t000000000000000880000000010020000000000000000000FF412901000000400000401000000203830048A0102000040000\n\t4000000019400000001102001014020200A0200080040AA8038000000020000012A000003E10B00000000000000000000000\n\t00FFC93809000040020040040040020005040008008001210000A80000202000200200002001301003000212800082004409\n\t20000D20200000008001001000121000051000000000000000000000FF20E80000000000000000000000000000000280520000382040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A2A128020220\n\t83002020002082142192002002000000000000000000FF4ACD140010101801801D11901801901831C898258902A8F0CE4243\n\t4655754400411634E506C8400281614640F4960C6116CA62AE2A60A6006002844087C060A600E006000000000000000000FF\n\tABDA0A000802800200820202100505010522601240618042080B929800821C42C2682202F822D028668230A60A6069044881\n\t08042040000CC2814A400C340000004040000000000000000000FFBF130A0010080800800888D00C00B00808800A14808000\n\tB03220E8C2AB22C220290F00310AC02800412002002422C9200200255254210202200004300280200200200200000000000000b82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000400080\n\t7006006000000004004001004004004000004005004000000001000000800800800000000004000000000000000000FF3BF1\n\t000000000800800800802800800880A30A08800102A0C2B42802002050080308402002002202082802002002002002002802\n\t40200200202A002082002802002002000000000000000000FF656B1400080400040080040400000400000002020000000210\n\t810D100082818280201104A13490284484214204502800502008000401000885001248082000000000000000000000000000\n\t00FF4EAD010000014800804810C02800A3080098C800C64200B0A200200380200208288284281280200008300399A00A85A100782040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF30490100\n\t00001801015A01801C41805C0184100521000062060404AE80640042801400E04694601082E024CD48060404060848861068\n\t06016228000456804116006804000000000000000000FFCC8A00000000180100180180180188980590908108200060060000\n\t064000000000A408648E01004010640400420E10014600C006006006086000086106124006006106000000000000000000FF\n\tB2FA000000000000000000000000000000000000000000000000000000600600600000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF0AF700000000100100100140000000000000000020000000f82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (500600600410\n\t600020F0364D209608E006000000000000000000FF8414000000001800001801803C41C01801901801090000700022548848\n\t608084080300011629081009200450201014020701600600600211644800708F80600E006006000000000000000000FF2E85\n\t008000001805003801A419018A3A27A2128180204062070010661083062DE0A9406A2641083000620C53C3066100E3084886\n\t1A6004046010041326082024006106000000000000000000FF6703000000001801009801A05801A49841A092038000006986\n\t40000611610610700008E8064208000261B4004066C000020060060460060060008800066260C6006086000000000000000000042040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002000881006\n\t116004100000034094084A082B404000E006806006056806006004806106446152106004000000000000000000FF8D3E0000\n\t00001005003021803909841845A252073D204669000200004067074C60BE4C07024060C0082225026C0000640160401E32F7\n\t84046091007046813024016006000000000000000000FFBCB00000000018010838218418118098018A15414020087001B240\n\t408210060062A600180380640002A94400708040602400400640600208610024E016087004006086000000000000000000FF\n\t2DEC000000001000121003C018018338C1C8D8A1050010E140284000A40000200C020401060264200320950024208002060000842040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FB3C00000000\n\t000180000180188180C001A03801811012E400012D1014780600600E0C01148041040108860C0800000806804887A1620400\n\t6040002026002804006016000000000000000000FF9059000000000C07800801821A1D868069A01821808080600000200140\n\t0216C07B020000849042901004100201880804120160161063042061240A210641A087106006000000000000000000FF76EE\n\t000000002800800C01A21801800009829849C000006111002000006406106C00200041004A0500400740542834E146104806\n\t0070064060050A20060C6090007004000000000000000000FF77B5000000000800840803003E01804081811801800000E02000442040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006014006000\n\t4060266421C4086016000000000000000000FF80BC000000000883822CA1089D85C0D88180341100212A760608200F400807\n\t00E00228601010422420090100000622E03688420622E304006105207807902000106006000000000000000000FF8E300000\n\t00004800810A01821803A01835901855C4900068D783644690614E026281816408484085924226000086086C060040860071\n\t485160068521068A2834446016000000000000000000FFA1F5000000002800800801001801801801835C01A0000B6116016A\n\t960A000E2860944C682000400808D20F300C46A36327115116496800006004003126442008006016000000000000000000FF00c42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060060060\n\t06006006806000005004006006806006006004000006006004006006007006006006000000000000000000FFCCC600000000\n\t0201820201889A03801841801801A0C008600200740690004700608640F2062064465460440060064C60061068848000C630\n\t600600F106806006D46006000000000000000000FF449A00000000C085814081801B0189180DA81A51A4002404B209684600\n\t710EC4F40E1068168C608400C48D28E006816407406C04C4840601600602602610680E006006000000000000000000FFD5E3\n\t000000008001800447841801881901805005000000600604201600600620680E00680002400400808928810680604620400600242040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000001\n\t900040845805911C41D00015C000100414956457340526126556086006826000806884316201054214004209100106006005\n\t006006807004006006000000000000000000FFDD130000000000018000018018418218958089218850230024406086016016\n\t40E00643654E516500486414026088004004414004200006006006026006002004006006000000000000000000FF040A0000\n\t0000080180080180180180180180100180000040000060060000060060060060060060000000040060060060060060040000\n\t06006004006006006006006006000000000000000000FF00AE000000000801800801801801801801C014018010004000006000a42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (065260000060\n\t0680700640E006000000000000000000FF774B000000000001800011C01C01831C09889881A82048E2260AEEA62AE22E32E7\n\t262A66A64AE2D071467E6C878840200A00A0072A0086006041106446146006016006000000000000000000FF768500000000\n\t0801800801C01801C43821A950219000854150416156C50D564168365561561563048460841080001422421014D002001654\n\t600C00608E206884286006000000000000000000FFD533000000000801800A01803A01809823864823850080410020600600\n\t688708680E00E00E006004086044800000002002A0000404001E006004026006106004006006000000000000000000FFBE1E00642040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000600700780\n\t6006006002000006000806000000806004000006006003006806806005806006000000000000000000FF2AA4000000000001\n\t900048841845901D01A85C1185014441170068160070000001060268266A60008209A1046000254405002C12000006006800\n\t0870063A6084006006000000000000000000FFE39C000000000001800001801801829821C01821B000005806006007C00048\n\t48900600710E00602100500000640080440410350204000E0070290062AE806804086006000000000000000000FF11AD0000\n\t00000001800200801801A03C01815C01A00143615740E3360494868064D648E20701648828E20FAA8081942022802856000000e42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001808838809\n\t4A8019418218059C1801840008C112486006200000000006006606206010000A300000064404000081080006060060401464\n\t06014000906886000000000000000000FF8B660000002A0A83A90A91C31CC9A21805B01C318401004442846A068CED09490C\n\t96D0E8070A68080002268808068088410290000410A6816A0082F056904A8C42E086000000000000000000FFCCA600000000\n\t084180082288380181188182588380802A8005286006206006006046026287A062800C90882308264002085060CC10040600\n\t600008628640E024106236000000000000000000FFE6FF00000000080180080180180180180180180180000060040060060000142040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (880001080888\n\t0800800C00000000000000000000FF33A2000000000800800810800800808C00800120824000340200220208259000000218\n\t208200264904350262210200200222201200000200210000600230A400203002000000000000000000FF98D6000000001821\n\t9018850020A010440200200810002140200200001470060974A04280010300000240440C400021C2240010E4080020000010\n\tCA02A0400058038228000000000000000000FF23DB0000000000040400200200004402804200040008120A0020000002700E\n\t60E2482000005001008800800180201001084000000201110002010080000003A0480000000000000000000000FF40FA000000942040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004800880808\n\t28480280481488890883088890C004000904004802525004890835004904000000000000000000FF1EAA0000000118018C18\n\t03801901881805901905900000440450600601600410C00650600610600001414400610610E046404134800416806000D064\n\t0608E426006406000000000000000000FF0F78000000480C42C00CB0D00C4082C820820C008241B0A1130232A30A2A8B2034\n\tC3003403A134B002240B44B023443303083A020011020830D004B00320309350A002000000000000000000FFA36A00000023\n\t02402082003882082100402002820081400804940D408182009001008008000808808188088008408008409804008008811000542040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040440040040\n\t040040240000040000010018110D10014000010014410010D101100100901100100100104100000000150000100005100102\n\t9408000000000000000000000000FFCCF00008001200A801A0240AA0AA2AC0AA0C209400402A82202A03204A82A828820022\n\t82A00000002A88802202302902008302A82A80282A80004002A82001002A8000000000000000000000FF175C000000280A00\n\tA00A04C00A00802A00A08C40808100200A80288280280302294A80280284A840802243002802802822202802000402002A00\n\t813002822D02802C52000000000000000000FF457400000020C2042C03084014012012012412150028004885010810A0000500d42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F082A8500101\n\t2A82A8000000000000000000FFADCC00080003000008400000000004040040C0000100001100000010020840000030010009\n\t3000000083000080000800A0B000000000400000000200000A0050000200000000000000000000FF7E3B0000000AA0A80A80\n\tAA0AA0AA0C80AA0AA0AA01402A82A00002B00A8AA82A80082302001200102801202C02A03285082A8AA82A80402A82010002\n\tA80000202A92A8000000000000000000FF679D0000002043542403303543545101541003400000D50448D50C40910510D30D\n\t00D40D40048840D41048D40D40C40C10020D50550308550A00910D50C10A00D51130000000000000000000FF68C70008004000342040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1400400420E1\n\t080064A400C00620600608403602000000050005640608E006096006000000000000000000FF8AB900000020023420020040\n\t14002212012012010040004804A40810820825044948900800A848028C0814814910920B08804000000800000A0000100481\n\t0888800004000000000000000000FFD85B000000004800800800800800802800800800810000210A08E10600200200240600\n\t600604A00800A2421420020120220020028002000000000A20024A2442002802000000000000000000FF90080000000A8080\n\t0AE0AA0AA0AA0880AA4AA0AA0000AA822040222228828828810232A2AA4000002404802102302000002A8AA92A80B82A800000b42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (82C8008008A6\n\t840814868082802056241701106010200010149102128004200000221A2420020022420020120000C0008000002102002412\n\t00A002000000000000000000FF834740080000010000000040040040242040050C08010090080000C00012C9200200088029\n\t0010210010014000B0380491021109001021031001001100029221001000000000000000000000FF668B4000000008008028\n\t00C40C84C04C52C20C48800101345240208205310B4C24C24D22D314344124B0131221220421034430031111410410514030\n\t12423223003002000000000000000000FFD74A00000008380183180188182180110190D801884004400414401408640400C000742040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (264020C22060\n\t86080000000000000000FFD653000000001805055842811803821835951801880014420800620E0A00300100860264360C60\n\tD000610040202608802414C10600044030002000E046016014486106080000000000000000FF5CC100080000001000002402\n\t800009000011400000000000404A021025604E2061000400C00801500A83200100885104100B00002080002004A002840040\n\t80200A0000008000000000000000FF3F3E0000000018018058010C000000008A082020000000444034001014E02615603040\n\t000054829042C1440B000804400C3001401480000002A8230310480000080000000000000000000000FF1F1100000008288000f42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60C600680022\n\t602004000800401604A00E000000000800002006016102006006000000000000000000FFE99B00000000D801043800801800\n\t00180190D80181002480460B60A644002604609622E0160060400123161141060281401040860000000000000020060C4052\n\t004006000000000000000000FF43FB0000000018010018118418080818018018238000200085007006216006407227007086\n\t00E0000A821002010600020000420E010000000200046086006302046006008000000000000000FF7E570008000018130298\n\t098078098118218058238E000040C055604600660016803619E20E60E0000020462140364000160042865802000801000004000c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AB8AB8AA8AB0\n\tAB8058AB8000121236D1701608E2AE2AF0C700602E2AF02040A0C624C2A022A2A82422360002A82A80012AA2AE2AC20A2AC2\n\tAE000000000000000000FF7A12400000001801001801801801801001801801804010700400620600000600642E20E00E0060\n\t8042024E05000008201600201400000000000000200642E002006006000000000000000000FFFA1A2000000E18AA0898AB8A\n\tB8AB8AB8AB9018AB8120004A842067060C82882884361D66062AE6020C24103042303842062122260002A82A8002AAA2AE20\n\t42422AC2AE000000000000000000FF97D0000000001800001801801801801801821801800008400C00600E00600000020600008c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C00600400600\n\t0000000000000000FF178E0000000AB8AB8AB8258AB8AA0AA8AB8880AB80004002544861A608828E28E00E0060862AF00808\n\t000420222029C2002061440002A82A90002AE2AE08400E2AC2AE000000000000000000FF06D2000800001800809801801800\n\t0008018480018040214100046026206006006006206906006000100004006000002006082086000000000800004006006086\n\t006006000000000000000000FF69A30000001559549558B19559541549558CD155810004C5000D60365505565561061462A6\n\t55600C09610448255044254455620600055055000555455608654E556556000000000000000000FFAF5E0000000938AB0A58004c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006004080004\n\t01201610E4260024040000000002040CA00620408E404006000000000000000000FFA7F00000000018028018018018408258\n\t01805801805022C0120860462060460064260160060060A04164C42C610602608E1120D60000000001400060060CC0060B40\n\t06000000000000000000FF1A5D00000000180080191180180180180182180180A024C15220E20E400006006B263164560068\n\t0001631408A10E02614E0C21260000000000000060060044A6004006000000000000000000FF0B4400000000180180180580\n\t1800001801804801801008680684680604604604600684680600608022002404200000400600E20C0000000008008020064400cc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (590190595580\n\t1155812042E2200161161105165161065061265500042205485064565462264D454600600600014420655611400A51655600\n\t0000000000000000FF0287800000001805801801801841821001941801800005600600600600604600600600E04600000844\n\t80104C6096006446084006006006000208006006004202006006000000000000000000FF895D0000000AB8A98AB8AB8AB884\n\t8818AB8018AB800000602202600608E28E2CE00E0160262AE60003600C0063262060062260160000000004003122AE404626\n\t0042AE000000000000000000FF4795000000001801801801801813810801929001810208628021631602000602610652630E002c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (806006000000\n\t000000000000FFE5E90000000ABAF1CAB80F8AB9218058AA0208AB001000627006600608E28E28E45E0464362A8008020008\n\t0062202141040022AE0060060000001142AE4760422AE2AE000000000000000000FF5AA60008000018038018010018298298\n\t018B5801000210611652644622002600622E02620E0040C01040000360060160960060060060040000000240060260A20460\n\t06000000000000000000FF781A0000002AB8818AB8B18AB80B8898AB80B8AB00B030630650E4CE2AE28E2AE0862860862AC2\n\t801042A000E2262A60162542AE0060040000802442AE08608A2AE2AE000000000000000000FF355E000000555D51D559551500ac2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0108302E8000\n\t0080289760510720608280000005E866006402806806000000000000000000FFAFA0000000401C01C03801411E01C0180008\n\t141514000060A604600604000600600E00E40FA2403480D22C01034100B00400380EA0708C00800500740614600700700600\n\t0000000000000000FF98AB00080000180D801901A01813945A00082001014022E08108604642602602642601600600430241\n\t54C52D010802288E01200600600400010A294806016206007006000000000000000000FFF052000000401C01C01A41801901\n\t8118000080010000886008216316000006006106526B0E00000008000000600090C425542006006007000200024006286132006c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A01881811A83\n\t000004612E006486316500000216246546D0A010202C5200E04910508610642650680200800080611624620708F206040000\n\t000000000000FF1886800000001801803809801801841C41921909034142E1120163364201004104060060CE022408C02003\n\t0360A010441600510E006042100000006A06346302006006000000000000000000FFC8A3800000001801811C01801851801C\n\t41841801808124620020600E0002C60460460C60A608A0013021070400002823060040060060239002001060962160960060\n\t06000000000000000000FFAF70800800401C01C09C11A49C059C1B818079638841016012B3654650623E436526086A0700A400ec2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00000000FF4456000000401E0388B80190180182193580583180484461022060A611642801002E44E51604E0002364044405\n\t1604000410431601600450000002C316006416016006040000000000000000FF54F300000000180388B8038C180182182399\n\t3805802001640020602600602600612600E00E1260C002E01402020601810001404600600020000012C20640E00610640600\n\t0000000000000000FFC2C3000000401801A018018438DD881809801829880020E64210600E12000E20E19605600650626009\n\t658420048663000202C08E00E0900904001C411609601A006006000000000000000000FF54D4800008401C01C41C09C21A01001c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A2BA28A23220\n\t200211A2AA2AA2020000A000C2AA2A22022AA2AA000000000000000000FFC900000000001A01801805000000002000000000\n\t0020000144210310406006006100520308014040004004004000114004500000000050000000040000010010000000000000\n\t000000000000FF4B438000000000004001200000000A804013402C0108000208080040006046026420010000000300000000\n\t020108020550020000000080000400480000000120000000000000000000000000FF6B88000008201A01C418138059119018\n\t0180188188080060560062162401002002060060264063080860A400802648000204600630610400800000600614E0040060009c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (118B5B558001\n\tD5610E01411435655451410450412450608950652E5464475462864C65575564B60000105575565560065575560000000000\n\t00000000FF1A1D0000000AA8AA8AA8208AA8AA92088880C8A880802AA48250A4CA2CA2AA2AA0822820832A23202A23223322\n\t222AA8022222AA2AA28A0004003122AA2120922AAAAA000000000000000000FF69C800800040040040040000000000044000\n\t000000C800042052044000000002022802020800040080100001000900000001000000000000040000100000028000000000\n\t0000000000000000FFE2C00000004AA8AAAAA8088AA8AA8148CA80008480082AA0420600000AA2882884580404302A20002B005c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF5E1A080000000000000400000400000000008000000000114021031020004000010052030900800080814000001010\n\t0A000080000000C0000000000000000000000000000000000000000000FF93F68000000AA8AA8AACAA8AACAA8AA88E8208AA\n\t80202AB00202600608A28A28A00E016027252200273A0320232221B0522A3AAA2AA2020001802AA2AA2AA253AAA2AA000000\n\t000000000000FF38BE8008004004004004924010010004021214000041004010000000000004004000008041010000800800\n\t000081000D280000040040400000C0045004120440004804000000000000000000FFDB3B880000555D55D55955F55955955900dc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80220200A003\n\t502A02002802202000A02800002802002000000000000000000000FF0D1D0000000000000000000003280800020800800000\n\t810128420010800080000020021D201404900400001001000008800508A8C88000000002080A400100018000000000000000\n\t00000000FFA51D00000000000019000410000040008000E0060200000851801000000040010C006081003010000400602280\n\t40440800000441811000010400000000A303A0000000000000000000000000FFD52000800040040040000020000000004008\n\t200000810002080800400400000404200100000A00881000089301010201500000008000080004080008000000D000080000003c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4820C4A04880\n\tC201208200300210280A80200202A00800204A80204245228200200A20200201208000200207316228200000000000000000\n\t0000FFA996000010001801889815801921801C13249803840013040F424516016094D14046436136CA63282150D642F50781\n\t6887286C8C28E006A0600008602522F2A6006000000000000000000000FFE1860200A00000A00000A00030191011A17A5181\n\t0A00A2114422D02C809A8C2E40A01A86290102A11C4E8018088C88802405404400102000002968468C284000000000000000\n\t000000000000FF753600000800080081080A800C00800C10840800800012040200328201201233200708200A80A040D0A30A00bc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF70130000000010010010010000000000000002002000000800000000006006006000000805004000004004004800004000\n\t000000000800000800001000000801004000000000000000000000FFE23A000000000800802810900828A00A0080092480A0\n\t85008A0000040120002088100B210200A00802200A00208300200200322E8020028022800020060020020020000000000000\n\t00000000FFADF00200C00000A00001200040800000C04C020008009008012451480012B1040B40400C481415401002801008\n\t10101520000000408020000848280D08280000A80000000000000000000000FF60EF00000000080097280C8188A0800C0080007c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (462080060368\n\t10C4200200620080E00299EE46006000000000000000000000FFA4F3000000001801210801A01C4195194191183180000004\n\t17500440007210140504B0620C826500B56A3244C006B010462460C401000090E20000F03004608C10622000000000000000\n\t0000FF3A87080000009801001801831801803811005801832031000600000C45004000000C01610401600800000208409602\n\t8106006000000080006000506080006006006000000000000000000000FFB2FA000000000000000000000000000000000000\n\t000000000000000000600600600000000000000000000000000000000000000000000000000000000000000000000000000000fc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (840080004E09\n\t02140804000000A2A2E2CD00E2C900114000310622E8060A729485200200600031690304E81630E000000000000000000000\n\tFF0A8D080000001A00401801801821801E890138A380A0200216A0102582F00802828A08E14C0060805200080AA086086026\n\t207088028100114000886129046116106440000000000000000000FF2CD9000000001801118941A29805B43805BC18018208\n\t45010608600A20002611702000680490E00850E6A200402E02058600E0202024129161002460025065278040000000000000\n\t00000000FF0B36000000009801001801801801AA9A2120190D8000888006006A06806206096040206A44026200000102204000022040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF65\n\t8C000000001800E008148018058418008D184D802000000E04140000000600600402400620000610400600400E4003060060\n\t02106A06206006006002296046106000000000000000000000FFEC1A0000000018C1000943419801901BE1803A0984200401\n\t467361A2B0700E30625E184C04A0311140640C80662E0D0806F4611609618631610004686604603740460000000000000000\n\t0000FF1AA7000000001A81111801801E41801803C03C01E001A0800600704A40120FC0E4864150AE11342000692D0060C610\n\t1007006206024814004000D0F08480628700C000000000000000000000FF67EE000000001840001809401A4180180181182300822040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00610E282A0\n\t688600410028650E026C46804200000000000000000000FF6031000000001801800800201825903811A13801B00180040640\n\t052400600620605630C00D8040C000C08A80005602680600E002906086006080417202816926004000000000000000000000\n\tFF9E9C000000001801800800905813811860021B018D606009670610108600AF9969020444A74A4408444202008006416E7E\n\tB0652208600611E0009060126CE006006000000000000000000000FFFDEB000000021800800800801801801800A218038000\n\t08000F80000400654E0472000040C4148009085406114807080006406846406006006001026102106206004200000000000000422040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (011006006806\n\t00640600F80F005220100000AC4006000006CA604600600204E00662600010E02610E122A04000000000000000000000FFFC\n\t41000000001801820800983C41E81810A11E01A1801A931E286596000C2748662229400208840402418E2082566060A70260\n\t0200682610E005056806806B86004000000000000000000000FFC1F5000000041848C05890841885A21C0182182B92002001\n\t2702E24B01620E246100017090021C880040060A10260164063061062A751600404054750692600601420000000000000000\n\t0000FF18BA000000021800A01800C05C11895C01C05905A2020002074070220000060360D44C6C12410120D3400F0808069200c22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFFB3F00\n\t0000001801A01800801801C01201801801000000200500680200600700600600600680600080680600600680600680000480\n\t4806806001006006006806002000000000000000000000FF54B1000000001811801808101A0182100D221031A2008C0D2E10\n\t604601105620604620608601608408600604602600E3060C0900000406004004206A26806426400200000000000000000000\n\tFFD07800000004384194592004DA0590120180D4858900C020064362960060060CF30F10F456046408C0688E516406946006\n\tC00800A8815683602084E106056006008000000000000000000000FFECAE000000003801C8082000991980180B80B881800200222040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000044004206\n\t004000016026846006002000000000000000000000FFCE52000000001811800844109851805A414011503401454008144849\n\t0A0D0E03654648684608713124ED2634E08602600E4000808012064160004C72A6287006004000000000000000000000FFD4\n\t1000000000180180080002188180100381100381001062A640C28441602650601604E48E40E40008600E0064064062060002\n\t10008006006000006006006006000000000000000000000000FF28B500000000180180180080180180100180180100000020\n\t040060020000060060060060060060000060060060060060060000000000060040000060040060060020000000000000000000a22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (870D6012D000\n\t8600E25604E08E00020880622E0C790E00600E506006446806006001006846842006002000000000000000000000FF261800\n\t00000019018019000018018011089830020A200AE20822EA8A2AE2AE2EE0A609E0AE2884E862E2F61A62D626620E2064E600\n\tE00620E100606046C62006002000000000000000000000FF84D1000000001801800000801C018018018081011000324D4435\n\t4C10510D46316556546D56D100941162864460860860D6510088CC0006004214086006006807806000000000000000000000\n\tFF3939000000001801B800008A7821A0103396588900C020488408402400600600600600620686020008600E00700600600600622040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFDD7F000000\n\t0018018008008018018012008010000000006000006002001006006007806006806000006006006006006006804000000002\n\t802000006006006002000000000000000000000000FF03ED0000000018118018440119118058008180410000220044004004\n\t006020000416446806280000206006416026026807006EBA082000806000156506506006806000000000000000000000FF65\n\t3E000000001801E01800601801801A80A8000100021000244044058114002C00865072468100A008E107C068061070A60170\n\t06006000006288287006A07007006000000000000000000000FF8AD4000000001901A01880001A01E01200E015019002804200e22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (092004603000\n\t10940160728000100000000000000000000000FFD08F0000000059058818008018038098459040811C003000040040040000\n\t1000000600650604000005600600600600600602A94004000000200000601E00431002C050000000000000000000FFBCD000\n\t0000209AC1A24A10B09895A21821A43C21010040088CD44920C860101089168CE826D00800346C0EAB724620E88E4C20B494\n\t4812B2A80000E8AEB16C4084C200000000000000000000FFD204000000001801888820821821B0990B08128A480010424080\n\tEA0604600620622620620E05700000704600610610622600C2002004A000200090680602680210401000000000000000000000122040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4160B9010161\n\t9408808A70810800200818C80580AC0000C00004800890810801080880000800844208000000000000000000FF826E000000\n\t000800800800C28C00800A000408008009002802140004002409000022482002382000022A02012002C03002002492016202\n\t04A003402002092002000400000000000000000000FF9472000000001801848001C000000814B0021461404001016D2A1280\n\t0670061060400400000280108801603208201090A00850241A40084A0000018004840460490100000000000000000000FF50\n\t3900000000000010202004420803420A4020026000C00201009010007806886380220008000101900001008200810649A01200922040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000002002\n\t0420024820100140031500100100800040048D4844820824044820810B0081084044C90C88480488400400402CC04C90C108\n\t40004830000920894000000000000000000000FFC3BF000000001801941801845801815801801101004800C90C4060260060\n\t0401400604611610600808601641640651684600491401440621600008609608E00E256130000000000000000000FFE0B800\n\t0000402D02C00C40800A04D40932AA2E40AC0830204214210B0AA292D032A320344302B08084A142103102022202C0224214\n\t302B0C3010C4B023C23543082400000000000000000000FFDB3B0000002082A02202480802A434010048010800880848904000522040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0900810800D5\n\t0C50D50890A00800000000000000000000FF5B4D00000040040203040040060040060240040000C800000000000100000180\n\t10210010811010010000C9000001129001000120001000001011000101001411001000000000000000000000FFB1B9000000\n\t0AA0A80AA0000AA0AA0AA0000AA0AA00080002A82002100882882C83002004082A00008802202382A8260AA82A8A00010400\n\t4000402A80802A8040100000000000000000000000FFDD2F000000200A00A00B04A00800A00820C00A00A04080280280290A\n\tC0280200288A8C284280280000280280280280A0030020828CA8228A2800802C02802A12A22800000000000000000000FFEC00d22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C82A8288402\n\t2AA23A2B0010590A002012A82282A82A90002502002A80082A82002A82082A8000000000000000000000FFA6380000000000\n\t0000000840000000050800000041480010010210804408000000280900080000202880000000000810000010505000281400\n\t00000080000400048000000000000000000000FFA9B50000000AA0900820A80AA0AA0AA1000AA0AA00010002A83480C8288A\n\tC82A80882A82202400000212002A82A82002A82A84092803482A80002A92482A80C02A8000000000000000000000FFE51700\n\t00003543543543421545543540423543540000800550510420910551510C00C20940D50801040CD0D40D50C08550D504808200322040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000010180180\n\t180180180188190D0C1801840828600C40641608600408602429411408600048609608620608620620611401600610608000\n\t6446006006006006000000000000000000FF849600000020020C0442022012012004814012002008800804894814C2080482\n\t4D48800880008808C4C088920001000804804244948888000800800020800800801000000000000000000000FF12E3000000\n\t00080090880080080080082A80080080C8002002042102002002002006006006802000002022012802082002002912002042\n\t00200000290A002142002002000000000000000000FFE1430000000AA0E06000AC0AA0AA0AA0500AA0AA40080012A920162000b22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080100110130\n\t010000004000000000000000000000FFD21C0000000008008008208408408C080081000882200820100004C001A440001101\n\t00100801211059200A2124020021120120C201A062002000002202382102202042050000000000000000FF6F3A0000000000\n\t0058000240241841840048445001010011210C52242010A12282082200210080010010014012890011010C10052000000080\n\t01121001560799021000000000000000000000FF33BB000000000802C00842C04C00C00C00C00C0090490434430930C240B1\n\t5343250A02242301284100322300308B0230031030034024C201280103310B012003443002000000000000000000FF93D90000722040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8818021E0664\n\t067470004463321865803081065260040A430028309001E0060246060026C2000080000000000000FFC99900000000000102\n\t1901901903940805821809800A00400200400420831000430630608E00F04000E04203600821040600E00005402050310008\n\t622608C00E08A106000100000000000000FF16FF0000000000001240C40040000901240A200002020D04000000004A600600\n\tE0002803100C0040020108246008080200500090000090030210080240010010110010000000000000000000FFAFCD000000\n\t08180380100180000000008A042021108244050825001010600E0861401083001040204004A41060040A448022001400048000f22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000011805\n\t80180194884084992080024A600684480C0460200442060A600602280000600000600400600602610210600004E800006806\n\t0CE0060C6006000000000000000000FF1F14000000001001022849801801805903805811812000432A116126400006006156\n\t40E44E08604000600200600000000608600801429208202000653620604E002000000000000000000000FFC1CA0000000010\n\t010818018458418018C1111881802000402223622E04604600B00700700600690808620220600000000E0460B008440A02AA\n\t0000600604608600000A028000000000000000FF88DA0000000010010048458818838108010058E984221545B222C1881060000a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04556D5654E4\n\tC6A48006000000000000000000FF6F0A0000000AB0AB0A88A18AB8AB8230A1023888800B30420E2AE2A20AE28E2AE12F20E0\n\t2E2420202AE2AC2AE2AA2A82AE2A6AAF2A60C60A60202AE8242A6226A04004000000000000000000FF2C5A00000000000111\n\t1801801801800020081800800B8CC00400600200000602222E03600689200000600400600200000604610788600400600000\n\t6006006016804004000000000000000000FFAA0B0000000AB0AA0818918AB8AB901818181802804A05E0062042000882C828\n\t800600618630A0002AE2A82AE2AC2AE2AE20EA262264322060002AE40601628624E006000000000000000000FF0703000000008a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6126136C0602\n\t0000006002006004006006046A28326046106000006006006106402004000000000000000000FF5D610000000AA8AB8408AB\n\t8AB8AB8AB8110900020012A061422AC04048828E28A80E0060062090082AE2AA2AE2AC2AE2AE20E0D084E30622D0142AE2AE\n\t20E226900006000000000000000000FF0AB400000000180080480580180181180300804500800060A300500C406006007206\n\t12740600C800006006006002000006016004016006416800006116006114092004000000000000000000FF57CB0000001549\n\t54802955955955955885045133012040641355531015055651210650634EC2400C55655655655255055650EA0020E45654C0004a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018008018018\n\t0181184008900000020040221060060000260421061260060100040060060040160160060060100062060160044864461161\n\t06050014000000000000000000FFC217000000005802801801801801803915005801002012E29202600624600600622640E2\n\t4600402000610E0060460A6006006004096046124000056116002026300324000000000000000000FFEADC00000000080090\n\t180180180180183500581100D808E32A806812240026002206A060AE08480000600600400600600608600000610E00480C00\n\t680614600E0C8004000000000000000000FF39E700000000180183280180180180188184892000020460020043200060060400ca2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C2AC00620222\n\t2086000000000000000000FFF43A000000355B51955B55955955903801880150004049003250642631051655030610620655\n\t00445504D655043651655655445054000E35000444608E52624254A4D6000000000000000000FF6CD2000000011803801801\n\t8018009018038858018000002112006026006006004406006406040000000044006046026006004000000006000000006006\n\t15601200244E000000000000000000FFFE740000000A98A98AA8AB8AB8AB8A18010218AE000224400220E2AE08E28E28E00E\n\t00618E2A00002AE2262AE2862462AE2AE2A022608E20600000400622631A000004000000000000000000FFCD1A0000000008002a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (126106004009\n\t00003100000600600400400000002610000400600428613280E00E000000000000000000FF06070000001458919C58AB8AB0\n\tAA8558118018C000002AE2242AC4A808E28E08C00E01604E20C0002AE3842AE38E2862AC2AC3782A83862200002AE2AC4061\n\t423B6226000000000000000000FFD18A000000401C03801C0180180182992D82B801800000228603608A02004600005644E0\n\t3600000000600600008600600200610000834600000408C44400E002002006000000000000000000FFFEFC0000000018A180\n\t98AB8AB8AA80092184989580802AA2262AE1162AE2AE2CC0D64C60962900102AE2162AE2163162AA2AE4042AC22E2A80002A00aa2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9C03C00C02C9\n\t900BB05A009502406B004066224A661E1D4286006806A8C01116C88502700E817067004006006006060000816036C0208300\n\t4006000000000000000000FF1883000000001C01809C01E05205A41823800401804202100400415005008600400600E0D602\n\t608501102E040847007816B16000000096000104027046026206006006000000000000000000FF7C84000000083805C23801\n\t801001801825CC4222000000100C00440442600604422640F24692600000680600604682E006006084004016010000806005\n\t02E406006106000000000000000000FFDBE8000000429C49811A018010018AB8898080080100004084004000000046404106006a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (506002084006\n\t000000000000000000FF486B000000401C01811A8BA009408018018A5C0181001248402A450400649008C406026116202000\n\t11434008700F486800014C028C20880202008A408E00600E222006400500040000000000FFA2B60000000018018018018248\n\t20C258218A9844912024C14004C1104080C044C0564C652E020051004A10A8012603608080400E04620A20028004EA0E04E4\n\t02002006000000000000000000FFEE8F000000401841801805820E40D03009E51832000009422014E00208002620432E3262\n\t0648E020004507281096046087005117026204200401404406112106004006000000000000000000FF2D7F000000201C21A000ea2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (860821400940\n\t0041641600604000E21010005002000002600200600420E006200280020000000000FFDC39000000601F0180DC0D90180902\n\t59018A3890820015004244400010614040404640E25643020800433004000648600800600402428008000808608040C00412\n\t41060C0000000000000000FFBC990000000018018018018C104812380580980002000040061060266B600600408600620602\n\t620000400010000600600800600001820208040801601026E61600E0860A0000000000000000FF4DB6000000001883803C21\n\t8210000898AB805898840010E28E50E00E00802620402629E02608C1A810404C22E20600603051610800012200000040E000001a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (88888A8948AA\n\t814040800254622220C31C2CA2882AA0080100C840200000210208A2AA2AA20220222222208A0000000120486522124062AA\n\t000000000000000000FF7344000000201A018000018020000000000880090002230000040020006026004100120000000000\n\t404284006000000104080014004000000000248020020028430000000000000000000000FFF5E90000000000000000000200\n\t4004C0000240C401221000881001000260060062204082404C80200A80502460000000500480801102400000001005000880\n\t80080000000000000000000000FF81D5000000201A05801AC1801901009829811801808000029201454C0204100944861460009a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4104C0040000\n\t00000000000000FF7487000000155D55B55955931811949955885A898042444404556406156514556304104204494000D064\n\t24517557556516556405404556000000556446446096C0D556000000000000000000FF0E300000000AA8AA8AACAA8B28888A\n\t08AA900800810200A2AA29224208A28A2AA0D24C20120CA0002D28122AA2AAAAB28220A2AA2A23220000000A221208220208\n\t22AA000000000000000000FF0C2D000000400400000000400420002000048020008208810800011040004000005044803100\n\t40100500900210000000408008AC00C0000000000000840002200A0000000000000000000000FF6A760000000AA8AA8AACAA005a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00100A805020\n\t0800800108000200C00010000000000000040250011000000000000000000000FF6ACD000000000000400400020000100000\n\t0402080000050080000000000000400100120000000001400C80040000000000000090128120000002000108010100100000\n\t000000000000000000FF9CD20000004AA8AACAACAA88C904800EAA880C04800220224A2AA06A08A28A0AA00E00618E242001\n\t00300208A2AA2ABA222AB8221422020000002AA2323920022222AA000000000000000000FF59780000002004004012004004\n\t240000010415120042004004044004200044000400000480804041000C440010048050490A1004014010000000400084000100da2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (10100808B10A\n\t42CA00C0248650A2A20CA402C0E28322ED0600200084A08200244214200208281040300A8220008020020030020020000000\n\t00000000000000FF96AB00000000002010000002022202A0A20040080100008001800010000140020800000849C282AA0004\n\t00000810000230010080120800A00002888008000000800000000000000000000000FF8C0B01000000400020000440000001\n\t000003014404600805001204004008000800680004004800004010018A8C400080000000300000000000012004C0A8818080\n\t0000000000000000000000FFDD890000004004000000000041520340000120C400C20800200004804400200002204082400B003a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF71FD01000000480016480088000A082810E80A08C8402A204A30282A08221280204200214202200900210200\n\t245A81A42A002000002022002028202403782102002000000000000000000000FF70DB004094055830501845950332323833\n\t953855CCA0516B06556554957C04D5611704E52C506B0004740400E80E10E40610E12828680680400008E10E216006006000\n\t000000000000000000FF35AC0800000A800208300000200003178B02200000810080200288840081EC2A8EC46A80A8051AF1\n\t014BA53C84408402D4001000040010464280400009101100004000000000000000000000FFB96000411204C808000842890500ba2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006000\n\t000000000000000000000000000000000000000000000000000000000000FF62FE0000000010000000010000000000002010\n\t0100000000000010008060060000000008008000000008040060040000000000000010010000000000048000000000000000\n\t00000000000000FFDFAA000000000800000802A0041200A800908B42AA00953312C020041020010814000002020420008020\n\t02C02002002002802800002002002028802022002002002000000000000000000000FF561710000015000400000010400054\n\t00820442100100A00000848B504094C02289042B0810C0155040044008900000015080080800002002028020001000000000007a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (58A980088080\n\t0200E006044466B070AE400427084006426000306008A008A200600600606805000200A00000A00680659610600000000000\n\t0000000000FFF1EA000000001840001801920040001951C01909C2800AE106C1491040E4881048080C482E80E002A2E81624\n\t8231146046087108802812012402882406001044436000020000000000000000FF6E2000000000188000B809800002009801\n\t813841804000640E10400004004000C0A440C2860460A000650000608000410605600010000202200005210E000004006000\n\t000000000000000000FF0C1B000000000000000000000000000000000000000000000000000000600600000000000000000000fa2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF74D1000000001808103821808000003801851825C0420C410ECAE2A1928C904A20C428700A047480006040C00084\n\t82703600A00000080712200010702B156846006200000000000000000000FF14A50000000019000158118400004018018018\n\t5180221044065078080A6C0028201000652A00E08000E280037A140C60A60121000800070424000C729700624E52E0000200\n\t00000000000000FF8C4600000000184000181194006250B845A0A800A68242708E02C286008006008292A3C946B060308A60\n\t060060021044065E694082A14B002100053102006406016010000000000000000000FFA0060000000018200018018800000000062040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0402600004E8\n\t0610600000600C00000100E00640E242206200000000000000000000FF84A700000000180810184000030020180380B00102\n\t0000400630440000802700400400414400408400680400020004600600600000680400000580640609600214640000000000\n\t0000000000FF4A9F0000000018000059919024C0505899882858A0C001C22604600E90703645F15616600014C0002E618682\n\t6B0000645605000002F0070068080053420060062A6000000000000000000000FF2B110000006018400018018520000018C1\n\tF208028081B444D600E9360204871070022160080142083060272400000860062800A004E1260A70900D601682642640E00800862040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D1004000C101\n\t750E4143468C0416000202A1400600624880610408008602410608645000F02C00402510609221622A20E200000000000000\n\t000000FF1E09000000001800001800000600043E01A8160161100442C6006000126206403010417000445000546084486086\n\t806086202020086C4700210090795280700600E000000000000000000000FFC0120000000018180018404400002318698110\n\t5100402940360179090181769864401E63E02940500268652000060060062105100961060020C50460228460168060000000\n\t00000000000000FF66190000000218000018000000200018098050010000505006204450006006041004004C04104C00007800462040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF1A670000000018024098020000C00418458000100401806026216666806206C0600E00F00000C20804600400E01E0040\n\t0608200000E02E10E00008E413716026016000000000000000000000FF4EFB00000004182008388000006048DAA18060B008\n\t002C70060070062001264E2056086208854004D2700404120603600601032080670400408407680206E00308600000000000\n\t0000000000FF8EA800000000190004184003400C04581384000A054004E50E02C08E00F8964150C320502652710109612584\n\t6826C97807C2610012600748622000624A087006236020000000000000000000FFED0B00000000180000184004000000980100c62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000600600600\n\t6000000004004004006004002006006006000000000000000000FF9F40000000001801C00800000001801801801001800200\n\t6006006004006006806802006006806000006006806006006806806000801004006000806006802006806006000000000000\n\t000000FF1120000000001881849840250011A01C89A01003C80200E806246806C0884612600610640620601400E000000206\n\t236006006800100005404404007024022006006006000000000000000000FFE1F2000000001825904904004105B0D801A430\n\tC1A121546D36006096006B1680E92E20F04E13650308612004E046104806B46CA0028C3480E1220CE006002026D26026000000262040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (098A01227206\n\t00E06402E20600601430600600600800680682600604600600600800060601401108E0801160040060060000000000000000\n\t00FF1093000000001C41C05800000081809C0990900990004365460D68169402A602610044F116A170320A62802A804EC8C0\n\t565072085100048A600600680F002804007006000000000000000000FF68860000000018018018000000238A392184112584\n\tC010601640630641601649622000622604640040600E0065060060860260000000042060000AE08600200400600600000000\n\t0000000000FF74DB00000000180180180000000180180180100180000060060060040000060060020060060060000060060000a62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t9869000000001801800801808101A21801801001B04080622E08605605002615608A0AE22E04E250206AAD0A000680600E02\n\t6840200003006028807002006806806006000000000000000000FF3B49000000001801880809800081841D01C8902384A008\n\tE49E207A8E2068AF6AE26E8FF2E60367202A674C0C66EE2EF0FE2860000C0000086058047042012006006006000000000000\n\t000000FF0E08000000001A01A01800010081801803C01001D040006847536354CD054715651410640ED46056546010900006\n\t0072064C604820000280400608E008A06005006806000000000000000000FF4B1E000000001821900A10000023C2B8A5801000662040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02E216456000\n\t00800A20600003614228600808E02E000000000000000000FFDCBE000000001A01A01001800001801E01801801A000006006\n\t8060040000060060020060060060018060040060060068060060000000000060008060028020000060060000000000000000\n\t00FF0EF0000000001C01804801800001901815A41101820000604694E206906000806121006816E96000006104C16A260070\n\t06046408430002C56000847012B1F004806006000000000000000000FF898E000000001801A00801E00001801883C01601A0\n\t018078062261075003014062040070070061001270040010060444464860000000000060000AE02A0030050060060000000000e62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001004003\n\t000060060010680000A0028001A80240006420018220880010000208300010808008080500800800000000000000000000FF\n\tA22F000000001A21804031804003801881894005800008608600600420000000600420620600602000658C00600642000620\n\t60004401E240600000640242400000600E000000000000000000FFA2E40000002118A1A00201800501D21D21A822C180408A\n\t6A86C86844B1680884EA40B26A2E82E940016A04809346A070261060002A0CA288E800286A0A856C00426006000000000000\n\t000000FFF3750200000018038B342188000381180D821805930000E017006C0400688628600E00608610700030690C00000E00162040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF5F50\n\t0000002401830422041000002003482032001420961400800000810098000010080940C40D10509000858900800808808000\n\t880800888800D80A80808A00280120000000000000000000FF964B020000008800810800800100820820C009008200402002\n\t282002002C4012A10410200200204000200200220200200250200002801205200104200224200882B0060000000000000000\n\t00FFFEC50000000018002080018000800880020200C0088000820801102018E9072C12014204180900810000144060882404\n\t40020000300400000000230030110000840010000000000000000000FFD7D00000000044500A00000800001000001000220000962040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (022A20008888\n\t22C12800C12002912002002002000000000000000000FF44A200000020000120020000000140140120120000808080009008\n\t0082080492092C9409009008C0004A88A2084C89100480C000820914920A009048048208AC004004000000000000000000FF\n\tF005000000001841801801800001901801909021800000690640610601640412611640624E00614040604620650642602600\n\t60100802340960004CE014226106026086000000000000000000FF2EA7000000442908C54C14904500C00D20804C84940154\n\t340300B00310214B00202308310324B41090348B05300301340330200042110324301000340311320280201200000000000000562040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0D50C00C00B1\n\t0510C80D08C00C08D21440D50908910C40B08550300000048A30C10C00CA8D50CA0C00550000000000000000000000FFED90\n\t0008004004004006000004004004006404000081001001001001000801080501001041001801001011041021000000001000\n\t001011121000101801000001801000000000000000000000FF73EC0008000AA0000AA0A80000000AA0AA0A80A800202202A8\n\t3602A02882E82082403002082000002A8020088300020AA88000002003001000820202A8210A002A80000000000000000000\n\t00FF50DB000000200A00A00804A00000C00A00804A04800088280280A80A80200280280280A82284A400802802802882A02000d62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFB20B0000\n\t000AA0000AA0A80000000AA0AA0A208680002AA2AA2AA3000C8A884030E02AA2022AA2002A84004882102A8AA82180002002\n\t202001822208202414102A8000000000000000000000FF4ADF00080000000000020400000000000020000000200000000080\n\tB00208000480000280A00081000002402400100408010480012800000400800000000000A8800000000000000000000000FF\n\t1F990000000AA0000AA0AC0000000AA0AA08C0C800202A82A82A8230288AA80280082A83082A84902A80C00882802A8AA932\n\t00002C83202082012282C82880A02A8000000000000000000000FF89EC0000003542003541502000003543541523540100CD00362040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (210904301300\n\t305141300200B023013000000000000000000000FF79D50000000019098018018418000038CB921001028020422400400600\n\t608400C12621441420C308406006506206006046404000414086424400004016086006006000000000000000000000FF72E2\n\t0000002002002002010004004014002012280140800800800800800044D08C088008C8800903000AA8A20850800004144800\n\t10C800844A008042048C0A84804800000000000000000000FFDC730000000008008008048008000008008108018000006006\n\t00614A42200204600200600600600800200200210200200280200004209210A000112112012032002000000000000000000000b62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1080400A6126\n\t10834000840855009012448C2062C4020010004088404090040250208008100240008000000000000000000000FF77A70000\n\t0000088880080102080410690A822C0008010010012303020020511601034611410500002120020E210208223220200012A4\n\t02202000112002002412002100040000000000000000FF137540080000040040040000040040040040102012200002880110\n\t88349208201408280020001221009100009008041001000001005001001001001000009401001000000000000000000000FF\n\tDCA5400000000C00C00C00800D08440C00C02930804011210A5434D241344A5430120C20421430410D340A02B0AA1034130000762040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (690700080000\n\t10418079058A8900001805828007840015E2CE0A641C19648004600201600660601211615A2880401060064001804044FA20\n\tA10200200E226086046000000000000000000000FF1CF4000000000081809021909842081951024011800000600631610400\n\t014049610222600608E00002600645600000400610000000800249200000A146424306006080000000000000000000FF54DA\n\t0008000000C000812400012000004A002010042054002040022040E406208010008000100008120140006220120000480000\n\t208000100100020120000000040000000000000000000000FFCDF9000000001801000001800088020120100090008051004000f62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006096402500\n\t2AA0462022462AE2A8000000000000000000FFCE19200000000001841805800800001801001921802000600E20E08E406000\n\t02E00400600600688000230600600608E006002001002406022A0000240E032116006000000000000000000000FFA8090000\n\t0000100180580180180000180100D00D80004D61460260240200460860CA4A625632E42000600A2260004260060040000000\n\t2A510100002146106026006000000000000000000000FF705E00000000100180180182180000580180940180212072970260\n\t2420601700600B0071270260020060000804800460160040000801020020000A2016004016006000020000000000000000FF000e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5415053652E2\n\t9434E54E44E2845541165105504C65565500000001545520045504260C44CE556550000000000000000000FF1F640000000A\n\tB0AB8A9CAD8018AA0AB8AB093489810280F447026A064AE2AE50620505602F4060402AA08A2AE2A83362AE2AE00000602610\n\t80002AE29650220E2AF2A8000000000000000000FF0A2F400000000401811805801800001801431021802000624E22E00640\n\t000600602400600608601000220002000000E00600600000620600028000600E40A006006000000000000000000000FF355F\n\t0000000AB2AB8890A98008AA0AB8ABAE18418080546306086206088288206A4400E1860061002AA4220882AE0042AE2AA000008e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001801\n\t081A058018000018010012038034206206306806046006426C0404600608E200000300026006336006004000000006004200\n\t002096046116006000000000000000000000FFFE6C0000000AA8AB0010A98018AA0AB8AB8A110180000460060062AE08828E\n\t8070840060060070022A80600882AE0042AE2A80010000062AF0062AA30608E2262AEAA8000000000000000000FFDC530008\n\t00001801003801000800001801001003802000601651613400600702E894306A06156C000040200060000060060040000045\n\t04040800000006056086006000000000000000000000FF80C200000015495514395100095415595510500B810030E1061065004e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0E0040000462\n\tAE01E2AE2AE000000000000000000000FF1551000000004801801829041000001925041025808013611654600E4000460060\n\t0E13610E10600401002000009604E006004000100204404004004006526006006000000000000000000000FF23D700000000\n\t18438C5883804000001811009001805200602600600402600644610640642640E02000440E4260460060060840000140A612\n\tC000336006006006006000000000000000000000FF768C00000000080183380100000000180101514981009368B683600420\n\t002611602ED17336A2691000400E2000060060060040000002CC004904004046406006006000000000000000000000FF797C00ce2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C2AE01632408\n\t609628600020604028E2062AE2AE0A600200032C24E0002062AE22E2AC2A8004000000000000000000FF0F27000000355955\n\t04DA28150001955905951025804011611612642E5105162064D610630E50602455600E51041604655644E0005402A6146004\n\t516556006556554004000000000000000000FF23D98000000118018010000080018018018030498080026006206006004006\n\t4A600E00640602E00808E2960460360040060160020A0006006000046006106006000004000000000000000000FFA6280000\n\t000A988980910188D0000AB841087099800024620640E2A608E28E1CE2260060060760002A058608E2467842AE22C0002300002e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00001801201A\n\t00008001A01C01809C25808013711650600602400600608413610610600002E0220400060040063060041080041060001260\n\t06104007004004000000000000000000FF4DC40000005E58AB8AB8AA0800018AB8AB893889807020660605E2AE08C28E08E2\n\t2445604E0260002C608208E30E2AE2AE40E00661022630600031E2AE2242AE2A8004000000000000000000FF760100080000\n\t1801901A04000001801811801901808040624600E10402002601600422E02600600200604004008600A00610600000000C21\n\t6000006006326004004004000000000000000000FFB9D50000000018AB8AB8AA1220018AB8AB8C1903801048E0CE0862AC2C00ae2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (408040601640\n\t6002100006000000000000000000FF84A0800800401943A01D01800003C81C39A694319A2004710618641612400645E62610\n\t600E00E04090F0060972A06028660460420E000606400004690620600B090004000000000000000000FF4494000000601802\n\t001C00000001C09C01889901804020E24E01610400C05600608600600602621400748200084004600600600600002C004025\n\t006C4600E015005006000000000000000000FF076000080000B800801000022001801801A218018000006026026004204026\n\t44601640642640E00880740820614000680604600604010E02C000006006016004000006000000000000000000FF9D4A0000006e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60619E09600E\n\t10662800610603600800600602602E0000520080C8286006016000010004000000000000000000FF6567800000001821811A\n\t0180000B94188188B821850040608E2164060140000AE4444060464560012D6D4E2863460220062065041400060040008264\n\t16026082B2E02E200000000000000000FFC13F8000082018A1801881800001A09A01801881800044612E44E2165045281460\n\t042C62A602604814624E0000160210160460420000062041002262B6006002006804000000000000000000FFA5DF80001000\n\t1E01001001800603881845805041850000600622604624428608604E4362AE09600103602E081D0800700F8060001000064000ee2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1A0180124180\n\t2109941841801001880000602E4862040140800C60CC00602600641010E22604614004400600622C02008A00011040620E00\n\t2004084026200000000000000000FF8CCE000000601825811C01808001805901915005840028E50604600402444020600410\n\tE0163560404260162800002860CE0061061000024D0000156006042084410006000000000000000000FF4FAE000000001801\n\t181C0190A005801821801041810008E00603607452400601640640E0060860000061060004102860AE44600400008A2A0000\n\t00E006606000044016000000000000000000FFDAE3000000001803801821880081803805905013890001662608614C2942A6001e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000008A0\n\t088000000000000000000000FF9B200000000AAC009808A88000AA8AA8AA88488800002006000182022AA288088204450048\n\t0204002AA02208A30240A2AA2AA1420002023001C02AA2AA2022C039200A000000000000000000FF1DF10000002018458044\n\t0180000000000000402400201301105400080040060000001301001001420000100460044400000000100000201100020000\n\t00010000024400000000000000000000FF96A580000000011003000200000000000002800001000000200000A00060264400\n\tA84004204084000004804060C81000000005400001100202400000000C00480080A0000000000000000000FFD20800000020009e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040004000280\n\t01005440001020111005004001000500014400004804000915020110000000000000000000FFD033800000755D4D95595180\n\t0555955955955825014015411412455615655420455610430450410955644E537C0613755755630600055644E20155655652\n\t6416A06556000000000000000000FFB6080000000AA8B282A8AC8000AA8AA8AA880902814048A0CA0823022AA2AA0122AA08\n\t20922820C02AB08A2AA2120422AA2AA41200004A2220002AB2AA2AA202202222000000000000000000FFD5ED108000000200\n\t0004040000004000000001000000400240008000400000010000228030000401000100000088001001000030800000100080005e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000402000400\n\t2000000000000020020020000000200000440000400420408510800000400040148000000080000008000201000000120108\n\t008000000000000000000000FFDC3900000020004C0000000000000000000000240100110110540000000040000000130100\n\t1000000000D0020808200800800020000100088000000000010040220000000000000000000000FFAA3D8000000AA8808AAC\n\tA88000AACAAEAA8AA899800020620640E2AA0AA28A1CE2AA00600E0760002AA20208A2C24022AA2AA20A0002222220982ABA\n\tAA2122038C22AA000000000000000000FF5D0E80080040040000020000000140100105004800000200002400500000044A0000de2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080100045800\n\t00040000000000000000FFD555000088000052814902800808400D44800912800042AC320A30CA02700288E8860028020260\n\t80D0320200300202A80204200A01220200A080012282802202282000020000000000000000FF72E100000000000000002002\n\t00000AA0102840203200080000200000010D10200000000C2909003003010080000000000000000000100000000080001000\n\t0000000000000000000000000000FF0A6600000000008038400020000210001012C05040000000008400416C013001062982\n\t0081040000000000288000000000080000C00000080000660000628800000000000000000000000000FF9B15110000000200003e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004044051220\n\t0808A01910020530000048400000000022A00010000004000000000000000000000000FF6352000000000000904804800800\n\t0248008008008560022C13642002402002802C0240200220200000200221208A00228A7A2003002002802280003E03462002\n\t102000000000000000000000FF4849000110000155A0B8A5821A10623F55A539558C0053685734515600C4D4516956026126\n\t14C1488C70060060060160060A600700EA0680E00023628F227206006000000000000000000000FF5D8C0200000000015080\n\t2240200E11B0033210002A81A086880840805C82240A04A12884390002A961450CD1900006102400003C005000904120800800be2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000060000000000000000000000000060060000000000000000000000000000000000000000\n\t00000000000000000000FFB76D00000000000040000100000000020000000120000000048000000000060000000000008040\n\t00000800006006000000000000800800000000800800800000000000000000000000000000FFB32000000000000080882080\n\t2C044C080C242850800082300200200202210081100080200A00204100200280200200200204200200200280428002200200\n\t2002002000000000000000000000FF73530400000000000000000000080100010800000800A100800840A1091C4892014011007e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00610400000\n\t0000000000000000FFBB93000000000001A01801A0180000582020180180002240A2E0440640044742004624411690808084\n\t600660001600600600614600600641400069E802E06126006000000000000000000000FFFABA010000000503841A81801900\n\t249A40103B21A2C2AAE31600300E800000024B0508404640628840E506100106B060471060174170460240A0806420002026\n\t206000000000000000000000FF4A4800000000000988000100180008189202180B900200604611200601010811400C214006\n\t05004008600E016006000006044006046006006000086000152206002000000000000000000000FF687F000000000000000000fe2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (206021807406\n\t00103620402603602628E016006080420006207006346000000000000000000000FF4C35000000080009801805881832001A\n\t04801800A000C060879008858032308A20014CE4AE20720828600602804600609642601690780E0060890268274460062040\n\t00000000000000000000FF7979000000000509D41A018011000458088238228C4000E40E10020C20A540002D000A600ED404\n\t1130E29608E00E50602604603644E0260460C0002427046486206000000000000000000000FF092E0080000000079010C180\n\t08002899828818C984800D404240E04600010E29816E80C0A68000200261064078864060468845C641600624C0009040020800012040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180000B801E9\n\t3C41200400E00C80441488080600100653445400280C20651600600700400608628600604410400401410601620604604000\n\t0000000000000000FF208300000008024D801805801E00001801A51801000184600411411401004600408603404C10220C00\n\t6106021006006206206306006004006004006006046006006800000000000000000000FFFFFF0180000024219218C9867800\n\t18991D8ABA9A988058620A40E64C20A10620684AC06004886020506A0641600E00631600E016007006046611304046984806\n\t025000000000000000000000FF34C1000000002001841B0910184C609801903CC2C48001654A00580420240FCD600A08628400812040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (304080000000\n\t000000000000FFBED5000000000005801C018018000018218A99310805127108A09406826006044014CCC20E88320020E00E\n\t80040C00628600482602E00C004200000106026206004020000000000000000000FF836D000000000605801A01841E00041F\n\t0080189448820A648484E0040423164461468060044D200404600600640E08E28640600604640E02400080480600788E0040\n\t00000000000000000000FFDF56000000000001801801C2181822B85084380000C200620542406D0820EEA038B600602522A5\n\t488362860601060060062060469960268A446000600604E006124000000000000000000000FF818A000000000001803C014800412040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C4807106A064\n\t0601422E00608629440FA2A04408681680E006084106000000000000000000FF222200000002044188590100180850581980\n\t98105C20147A0008289692600680682426600402280408600620620600420620400628680E80E00000460E40E00640400000\n\t0000000000000000FFCFF7000000000021A0780192B820483933E21A0400410B600800020E08660600200408680C08236500\n\t680600010411600610650700E404006004814006206116104000000000000000000000FF216F0000400000058118C5801804\n\t021801A0395545044160C022802641788E22829400DA4700209402628700600600E14E0070C6046C0624402488890600610600c12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001801001801\n\t8000006006002006006006006006004006006000006006000000006006004006006004004000006006004006004006000000\n\t000000000000FF3322000000000001A01801A01801401C010018018010006006002806806006006807004006806000806006\n\t806006006006004006006006004005007007004006004006000000000000000000FFF28A0000200000058818058418010418\n\t0120352380208061068864060461160460D620700610600C1462060000000060864060460400040020060161060061060040\n\t06000000000000000000FFBDEE000000040401810041815E34001A43029001C100A1724E44E8A641620640E406896456046200212040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00000000FF60EF000000000009904021831AA34218192C18098A40846C061868208068868060060040060860040060060060\n\t0602400660400E006080700004006406086806806006000000000000000000FF3A15000000000001A01C01A01841001AA110\n\tB203C0000061568160105060B632620E88E0568462A00062B612842088E406008006040806800000C0700688600600400600\n\t0000000000000000FF4B260000000000118018218218830298050011518B1030E00622654002E40600E12624630611600045\n\t600640608624609604002E000086000004126006006006004006000000000000000000FFAD9000000000000180180180180100a12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (601600040000\n\t7007005006805113806288026006006007014006000000000000000000FF3872000000000401800201A01A01603883011145\n\t90025265361032300A64A609644604624620E29008E0262000204082A6006006008002402040806806006006806026000000\n\t000000000000FF8857000000000001801801809801015EA712F0E180822EE2A720A2886AE20EAAEAAF3BE22E02E2E023E2C6\n\t6862A72DA6C602E006015003002510246807016046414046000000000000000000FF6147000000000001A018818118010218\n\t810083159000C86D56326D5094ED56D5734E244556257B144C6016028220406106086006006110402044006006006006006000612040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (03C230D1C800\n\t00600629600650630E28F94620400700600024642E00000820611608630622614210C02821240214708600E0160000000000\n\t00000000FFADA1000000000001801A01A01A01801801A01001E0000060068060060060060060068040060060000060060078\n\t06006006006006806002004000002002806806004006000000000000000000FFC889000000000001905C01C0180141180140\n\t20058042806016243000A06049006006A8E90680600080605607E006026816880846044802106000146C0680F026A0600600\n\t0000000000000000FFA634000000000001E01901809A01029801080611800300600682208100E0002460960071170260412400e12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF693D000000000002080280202220002140042080100220801800800008900E2582004800101000100005200078961A\n\t0208200000420000020100010000519000478000000000000000000000FFE97E000000000201800011801841181801134003\n\t8AC01460060840AE60600008608634418603600030600608E006040806082C060060022060200047400A208E006406000000\n\t000000000000FF0559000000000141A0582982B951411B09311A058480D36B36824AD680E800846A06904936A2ED00917006\n\t8881008A2426A54056916A0AA24800824888A0AA4EAA7206000000000000000000FF57EC0200000002038C9881801803883A00112040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (34203324A002\n\t00A0034430024030110031234D21130A3202000000000000000000FF7EE902000000048020026124000C2004840002000002\n\t820880240940800010100400800829000841408000D40848C000A0C25280A18AE8404800B20880800000A000000000000000\n\t00000000FFD833000000000400940A0CD0980200081AC80800800209202211400214230000205200200220210300200A0020\n\t0000300290900A00240280000A40A002002016002006000000000000000000FF5CE000000000002002E00002408000800020\n\t902800020002014202000010870211200004404482800F12000160062109000100200C00108880500000082413201842080000912040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A0080028228\n\t0AC0280A812802842802902802822800802802A0200283200288300200282A842800C0290280A80280200200000000000000\n\t0000FF28530000000000013003412C100140104200120000429088008948808C0804808950840948488800804804800804C8\n\t0804814005000C84C94C20910848C40804A30004000000000000000000FFBCD30000000002018A180180584190194D801001\n\t804805600600E10644600414600644621610600014600600E004106106486C0601642C00612030E20600600640E006000000\n\t000000000000FF1F5F000000000000C048548C0C04C00E00B2AC00880910300B34304310210B00B533103123A5313020B48300512040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF109500000000055433420220420035448C5543520040C10D40288448D50510C40C90D40CB0800800D50550911550891550\n\tAA8D50550C088D0C41500C90C50D50410000000000000000000000FFE25900080000000040840054A0004006106004000101\n\t0011000010010810011010010010012010100010012008010900010000010010000010090910010480010400000000000000\n\t00000000FFF9620008000002AA0001480000000AA0C00AA0AA00882402A00602202002E82802002082004000602A82A84A82\n\tA8440AA82202A82A80404000000302001802A8180000000000000000000000FF8BB3000000000000A54A02A14A00C008088000d12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (023320020028\n\t0200000200200020211211200220A000000000000000000000FF90C80000000000AA0460AA0002000AA0880AA08080802AA2\n\t92B182A82322884023222A82AA002000AA82A80C8AA80012A82A92A82A82A82A80000E03202012A818000000000000000000\n\t0000FF5275000800000000000010150000000000000000010008000900108000100010802000800015000000100002000000\n\t0000000000000080000000020020000001020000000000000000000000FF04360000000004AA1000AA0004000AA0A20AA0D2\n\t00202A82412202A82202A80482282A82A8150000AA82A80892A82202A82A82A82A82A82A82004002282802A820800000000000312040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (840220A14B08\n\tB20248314210200200A4420031091434022B348A20320302308B08900B04341100200208B003003000000000000000000000\n\tFFE8560000001120018218018218018018B1941881082202420424401403440E4042840A600428420000609600600400E046\n\t006206000204206000116046006006086000000000000000000000FF7A790000000000013082002D00004012212012240000\n\t8008100C4804880844CC8908800800C88810001004820004800804800004800804000C088148008208008440000000000000\n\t00000000FF57470000000002008208008028008008048008118040006046002002016002006006002006026000002002202000b12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF7C\n\t1600000009002400000400000014800008000415400C00101000100500B60105301202104D048010450054E1162042000244\n\t88110008440200008020110000100000000000000000000000FF57D70000000020008208208208508008AA80248000012010\n\t0022E10528020130100041312100000006204240201000206200210200000200A00828200200200210200000000040000000\n\t0000FF0BBD40080000040400040040040040040142002C01001082A100138000100009005060801005100900100800120000\n\t9001001001001201011001400000001001001000000000000000000000FF6644400000000440800C44C00C00D50C04C0482800712040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200620608604\n\t040A046000106004004006006410080000200000000000FF27EE0008000000018018050018830238098A38898A0034E20E2A\n\tA00811640802628600440608E01009608E1C84001461C602000610008A106060036444096182106048010000000000000000\n\tFF727B00000000000180000104985580980180381184000062260024A00060B442E55608C006146140126116416126006016\n\t0C600600010200E480026014306002006000000000000000000000FFCAE70008000000000000220300000100820000000000\n\t1400C0000240130546208028140408020330010200026346320010300000120200130300110428408000000220090000000000f12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006A482A0\n\t04628846640623E11640E2002AA2AE0880880062AE4002AE24800A80602028624622A2AE0462A8000000000000000000FF3B\n\t7F200000000001911801801805801803820801C02240E3061000080060440060C60063060068000020062464260400070100\n\t06000402056800026106003006056000000000000000000000FFDF4600000000000180480100182180183190B8B580820A60\n\t360460062CE00631641608404E3460200060060060063120065460061200C048600000E05408400628600000000000000000\n\t0000FFFACC0000000000018018410019018439158A1D01880320F10E2AC00F04600308700622509700E4000064260000104000092040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFC89400\n\t0000000155843B559558CD955B5588904B80000C602740454820651200644655454E50600C5545565105304065564AE55610\n\t8482C040044364CE496556556550000000000000000000FFCAA50000000000AB9018ABCAB8B18AB8C980489180C8AA68AE28\n\t722600E2AE90E1263060261364202AA2AE08E28E0AE2AE0A62AE2802908AE00230620E2822AE20E2A8000000000000000000\n\tFFBF6D400000000001901801801801801801824801802801600E02C00608E02209608E006006046100002006020000008006\n\t006006220048046008086006042006006000000000000000000000FF65E90000000000AB821AAB8AB88D8ABA81841801800200892040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (148006208144\n\t094810006086027006007000000000000000000000FF37D40000000000019018018018C90018018218098080A46A06816008\n\t286026AA6006006406006000000006006426090006406006120014846000016016116006006000000000000000000000FFFD\n\t020000000000AB8138AB8AB8018AB8AB801901C10048658632422004628A4460062AE8060170082A82AE0880883662AF0062\n\tAE0002063170002A62262072AE2AE2A8000000000000000000FF508E000800000001835801801801001805911225A00000E4\n\t07014090D0600600700E04520700680000400624604640000601200601004020502005610602E8060868000000000000000000492040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A60822066A62\n\t8E41600E2060060461602A02AE08E08E2822AE0062AE0000041060002AE3262060442AE000000000000000000000FF18B900\n\t00000000019218050218A1801801881001800A01601604004E01602208E14605613610628401000600040000200632600600\n\t000440C08400601600E406006000000000000000000000FF6C0E00000000000180580111381100180182D801804800600621\n\t01060060064262061042064360000040064460260300060140060004AC1462400061061460CE006000000000000000000000\n\tFF899300000000000183180120180580180190A4C3C04000E02E10090702E00200ECAE00412EB4F08000400624000000000600c92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFFA1B000000\n\t0000AB8138AB8AB8AB8AB8AB812055804054E01628220000E28C0264962AC0962862902A62AE2AE28E4062AE0842AC006206\n\t2A80102A82AC2A62062AC000000000000000000000FF10420010000001558219158918119559558020018052016006452502\n\t0165100C612655632650E204556556550530086556326554006536008044550454556506554000000000000000000000FF18\n\t02800000000001880001001801801801800081810200600604A10020604430E0060064460360000160060060061040064460\n\t0400610E00000000000400E126004000000000000000000000FF07170000000000AB8198A90410070AB8AB8019AB808A2A6200292040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001340002\n\t08000006096016002000000000000000000000FF6FD6000000000001844001801801801801921001801801601600204E0160\n\t0408E10600613710640410E006400000006806326005004004000084002006006126004000000000000000000000FFF1F500\n\t00000000AB8C18AB8AB8AB8AB8AB9410AB80002A67E62022543E608C00606E2AE0060060002062AE08E0EE2D62AE0162AC00\n\t42442A85002A82AE2262162AC000000000000000000000FF229F0000000000019038210038A18018018A805581105462B610\n\t204A0A604000641600401600600400600600000042C00600E00400600642028400000600600E00400000000000000000000000a92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (208650642400\n\t64060063060A630000E30620810010E206487322056006000100102002403897007800000000000000000000FF8A7E800000\n\t020281801C2B801903C99910C04A09800050E94602225429E33458E006196087006000D068960260B6067116206806C0E016\n\t00008008220625300E044000000000000000000000FF30A5000000020481801823801811C81821E8920D801000620608A404\n\t00600403602622404E00E005007006040240007006000010000084208004432426106806002000000000000000000000FFE3\n\tC0000800000201809C01801001C0180181300180C0006806152104006244426206004206436110826806026206036006013000692040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0F0000081000\n\t018018810018098A19039AE8C9840000600E1940440A60A400644608403601E0802064060064063042060260940061006900\n\t0027600E00E3A6004000000000000000000000FF3501000000000201801801809821C09800201805830448E0060222AC0060\n\t0C20622600628E5264100C60B602605602712620700250622C000290010406306007016228100000000000000000FFEBCD80\n\t0000008005840401801909801852049803904034633640210C0061142260064564260A6480A8F0162100100163161064C642\n\t601400000040004614E006044000000000000000000000FF0215800000110005821C11E018038018048208418A2003600E2400e92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000004802A\n\t8110300000480000000000000000000000FF0B6F000000000001800081001841841801909895850049601604410420600420\n\t608600410621600004610E00E016024006820000280020000000456006416446006000080000000000000000FF39F6000008\n\t000001801821955883805881825841880004630610402C11633408624611405608604050E046020300486026406104004208\n\t548080004496104106412410000000000000000000FFE5B90000000000018018218A38939138858008218800026286004406\n\t24E20408608666C40604653000E0060082C0086506186000006000028410006086006006206040000000000000000000FF0A00192040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A0000000410\n\t000010000001000000400020000000008A80080000000000008000010001000000000000000000000000FF1EEB0000000000\n\tAA8108008308AA8AA8D08A88AA00002A07E02344023E02AA0000682020000000002AA2AA08A0C80222AA0123222223000000\n\t001021021022AE46A000000000000000000000FF05A100000000000000A00110000000002800500000000100100000840100\n\t04088100090130100000000000446006010000B26004004128000000000240028000000000000000000000000000FFF49D80\n\t000000000012013200C00000000200000000000000000904280000064202000202004305000000000064264800000100880900992040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08000004010A\n\t410010000140120100408000020000000840402000003080000C0440030501005004400404801004C4100401004400000100\n\t0410030005100000000000000000000000FF114A000000000155911955955D55B55B5111580100000140044464D60145560C\n\t412455632450C481557D56136514556D5732705544E5460005005460D64C6556356000000000000000000000FF376F000000\n\t0000AA80082A8428AA8AA8828A8854800054A01222211200A2AA02249220A0922820002AA2AA0AA08B2CA2AA88222A2C220A\n\t00028142A0224022AA012000000000000000000000FF986708000000040002400000000000000304005400005402B000800000592040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8000012A8000\n\t000000000000000000000000000000FF3BF30000000004000B20000000000000420000000002000000090008000200420200\n\t000200430080801000040440000000010228C30000000480090028000000110000000000000000000000FF14ED0800000000\n\t0000040000020000000001400000060100100000000100000881400001301004000000000000000000013208800801080000\n\t00000000130800420000000000000000000000FF040B8000000004AA800CAA8AA8AAEAA888EA09AB80022A62A6323AA26A60\n\tAA41600E2AA0060460002AA2AA28A08A2ABAAA0020020022320000002226822032AA002000000000000000000000FFB6A90000d92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C85007282802\n\t0904C2E910C40D1010C54002888010040040040042A0004064084804404004000000000000000000FF37290280C408C0A090\n\t4D088ACC42810890944A28AD00822D0A4360CF00340282280A206486822000882002842842A0200204280200A20220200000\n\t2803002082002002000000000000000000FFF2C20000006000080002000000081220242000040040400040000000A808C081\n\t0900000000000040000200000000000000800541801800830100000C20020001A00000000000000000000000FF40F9010000\n\t0002000000620000501000042080D40140088440C00C0012840038032001010878800000000008000000000028000020000000392040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000221000004\n\t1501000003140000820202200D04940840280A10401230280110810B11010008000880000508000000001000800340000040\n\t880020800000000000000000000000FF5667010000000180800840808800824800800E00800300288201200202A00236B103\n\t02240200204100200207A002002003782003003002002000182002002022002002000000000000000000FFD4A00501441145\n\t41905B11155C45A33955B45853F5044D65554550D489450684E0564065164960000060060460040060062A62A621620642C0\n\t804AEA05027886006006000000000000000000FF65460020000000310010470A00901036A80101800A412280040A8020644000b92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001060000060\n\t04406006000000000000000000FF6CFF00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000006006000000000000000000000000000000000000000000000000000000000000FFC3C100000000040000\n\t0400001000000000200200000080400000000000400080000100000000000000000000680600000080000080000080000080\n\t0000001000800000000000000000000000FFAFAE000000000000800800800848CA0A20800850A8A004A842A02A0304A90200\n\tA00202A002B02800002002002000002002002002002002002000005003006004006002000000000000000000FF67C900200000792040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (210403604626\n\tE200216006026806006006226006017416822000C044A0586018006406000000000000000000FF0DDA000000000201803800\n\t801A01801824801801042000208400220600040EC8232404700F01602008600608002080E04680604680E117012000064940\n\t506011006006000000000000000000FFE1FB100000010151C05C018018118119202012918142C0E090CD2D03400886042C24\n\t08603600643031620614083003600644E40608600600200901400800688400E006000000000000000000FF0DBB0000000000\n\t01889800081801801808815001800210604000200A0C803608200400600644600000600600E00620400008411600E006342000f92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0B8018B5B050\n\t41843D25800881880000201420584102C400C5400514610E10E2010C608600000000400D10790604620E4320001060020060\n\t1408E206000000000000000000FF1FC6080000002201D01C098D1A218C9803011A01B20400F50881084012422000CC04006A\n\t8E8862A010708611100000E02E4440A6506006022000107003006044897006000000000000000000FF3694100000010141C1\n\t1800801801801901A0BA09820148604849010009410002408408604600600800E40601600E2260271164AF08709631201089\n\t600A207104216006000000000000000000FF85E20000000000098D1A0588580D80981A041881C0C000A00606201EA202266000052040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (401600600001\n\t6806000000000000000000FFE328020000000001801800881801801820C230A1A010404904004044403A0102200200604610\n\t6408046026086007204004846106406306100000801002806880006806000000000000000000FF07EE08008000200184D800\n\tA41B05891800815801A02004C20582408C002800802A1240600600612C00E006108001816046446046506006800004056202\n\t286800006006000000000000000000FF015600008000000BB03CA1811A81803AB13C2CFF85801A21063946809081C002490C\n\tAB644604E00882760600760600600608600603600720A00042F182006046006006000000000000000000FFC263000000000000852040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0279478C60C0\n\t20E106016406086006827086056106526000055056006114047046000000000000000000FFA736020000000001829800A81C\n\t21C01C41D138048000C210422860064D6C160128A50060260A622400708650000021602E246A8E40E02E00400C00480F4068\n\t04006006000000000000000000FF737B000000000001801820821841201A0020180980501340170018040921409129021060\n\t0600602040EA062060060860168060160D6056006148800006A06008006006000000000000000000FF32A6100000000201A5\n\t1A2080198180181D931AADB4000850445401BC8420100A204208700604600CA2E3060000780161464044060260068860A5C000452040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C3003584994\n\t9A09C818A3B15208221104E546D5222211401625714E48414008EC8600680608680480620604809755400002E10701610E12\n\t6020000000000000000000FF0811000000000181D01C01A2182180190102188282336D00435060B200303600244430E00620\n\tE00400600602640600400478410600700600600000200702E865096006000000000000000000FF0EB2100000208221C01C29\n\tA49C01A0980DA81A08D4420193B8266003022346AA280508600E80600708624E00000090E10600620698650F80C086602086\n\t00611401E006000000000000000000FF50C00000000004018838008038139418A5003C20909102000308E21649700E80A35400c52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (026006006000\n\t000000000000000000FF52520000000000018008000018010018018018018000002002006006006006004006006006000004\n\t006006000000006004006006006006004004002002006004006000000000000000000000FF23CC0000000004018008000018\n\t01801801801A0180100020000060068068068040060060060040020068060068068068070060060030060040020020020060\n\t07006000000000000000000000FF019A000000400000202800A01805401A23825811A2028009020060060020024451060060\n\t0682E00420600E028000016006046007106006004104C0602E046006006000000000000000000000FF102E0000000100200000252040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D64364145560\n\tC6B50420006106232006317406002004226102006007006800000000000000000000FF437C0000000001A080784480990480\n\t38058538038A102AE80420640600D20C88100600600E806000006086016006086046E1AA0600000608A0001E200200E80600\n\t6000000000000000000000FFFE23000000000440000A00801801151931C01D4CC30051654E506106A344B450C056A0649620\n\t604432628E9204200A6C0600200EA8E00E80C00480280F40E006007000000000000000000000FFD329000000000008000900\n\t009801803801805800885004600400E04E08400404448609604615649000600640600E00E0060024060000C610400000200600a52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A01601801801\n\tA01A41C02240212500E00620014000C427026036A00401047026000041006006802207802C06000000006205006884006000\n\t000000000000000000FF010D000000000301001802801809401B0D801B0190800200062460D6050A1094401650F487028088\n\t48E48613040000E10E012106092806802080006804A26004806000000000000000000000FFACCE000000000000200C05A01C\n\t93401829A098A980808032AC48EBAEAA008022C3AE28E2A62883A822640E0AEA0E03FA3700350F08888E0001010064046461\n\t04006000000000000000000000FF5370000000000080801800801C00405D15A0194191244460D515605645455434CC56D56400652040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (064560000000\n\t00000000000000FF9942000000000101885808882824001B0188900168002A808708620704604601610600E4070A02880063\n\t060000801264C640804614A34E2CA000000128017122086080000000000000000000FFA9D400000000000080080080080000\n\t1A01801A01000000200400600600600780600600600600000200600600600600600480000600000600000280080100680200\n\t6000000000000000000000FF23C5000000000011801144801001553905841001804280200C88700680004020408680700604\n\t0000906C06607046806806222006602046002000A27094046004006000000000000000000000FF919B000000000601A0000100e52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (401800808808\n\t621E0200101410002401A8000000300004208120808000000000000000000000FFB44B0000000800021A0080000006000028\n\t0000000000080010000000401B084000001804400200014006206064066004C8400B400808100400000F8090490200A20080\n\t000000000000000000FF644A00000000000181B900802828101811A11081910252A20404630600A02206440600E006080400\n\t806006146006806224000426026206382018806020006096446000000000000000000000FF77E9020000100234A49B45A48A\n\t084A3C31805A838002802A3482E82EA8A412C44806946826A0880001702ECA941020E816800406A060068028103488012C6A00152040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (40C00D44C84D\n\t4090034838A32238D222A413223403103A0328340000300335350300320B1124C300204B40300125300300B342A020080000\n\t00000000000000FFA98502000001051040040A3883004002003042020000801008500068810800A088100210301108008008\n\t00838880890800818000819040828800804908820C40085010000000000000000000FF28F5040000000088804C048208008A\n\t280080191488002121E20A201288200210200200200200A28000200200210000A00220280200280241200040204200600280\n\t2000000000000000000000FF8C5D0000000000200400700400410001C40CB04000000004048094003604100100810402016000952040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (82A800000000\n\t0000000000FFB0AF000000000000A00AB0A20C02C00AB0B00C80800280240290A90280280A102802802802803081003002A4\n\t32028CA83280280280280312288084288A802802802000000000000000000000FF516C000000000000000203310310001205\n\t2092220142810088800009014884808910800000800C01005004801044A04880C88804000804C04A0020C805004850004800\n\t000000000000000000FFDC34000000000201921821021803B0181182900B810200E216106206104104096016026056016008\n\t40640600601441604644600683608614C0109040CC40600E026000000000000000000000FF4259040000010510E0C914D00D00552040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A82A82884A8\n\t2A82202A82A92A82A82004000082502A8200AA82A8000000000000000000FFF8EF0000000005543540042802103542103082\n\tCC0080D41230CC0CC8D48C40540C50D50D50D50800D50D50950B30A48B30890D50D50D50820C00840C49550890D505500000\n\t00000000000000FF2D9200080000040040050000040040040044040400010818A10010801200099111090010000010020010\n\t01001001001101000000000001101003400101001150001000000000000000000000FFF81F0008000002AA0AA0000521240A\n\tA00402200800002A01202302202A02302202202A82A82A80002A82A80880880002000602A82A82A80081000802202A82802A00d52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08C880084081\n\t0000A0A208600608210A10210600600600200080200240220200205200200200200211220040290200214200200000000000\n\t0000000000FF8A5A0000002000AA0AA0004AA0AA0AA0500A008A00002502003022830012202282222AA2AAAA80012A82A80E\n\t80882A80102A82A8AA92A82501001412082A8200AA82A8000000000000000000FF32430008000000000004B00040200000C0\n\t0420000048010000000000000100810100000000000480000000400000100000200000000000308000488080000220000000\n\t000000000000000000FFFA4D0000002000AA0AA02A0AA0AA0AA0820920C800A02002082482484082A02202202A82A92A808000352040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF78DC400000400440C40C02C20C00C02C04CCCC008A0040B04205230300B08B4420821421031130031434D2503423\n\t122002003003143503003023103503003003083000000000000000000000FFBD5C0000000000018119210018019118098018\n\t2B814002620420402C28620608E0444042440061004160060160144164060863464160340160000160140560060060000000\n\t00000000000000FFBACA00000000020120024920020140120421220100208A0814850848A508008048088008000008820050\n\t04801025000D00800000000804844902928044804808000800000000000000000000FFAC8D0000000000008008848008008000b52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200062462200\n\tA00001404002001001081400100000A0200000000000000000000000FFD52000000000004000808404000000002200204000\n\t0023400844855050440043002002040031008030015002E0060402081004004A014001000008000001000010000000000000\n\t0000000000FFFEBB00000000000982082080080488A88883880E092010228300140002200200108168104040200003200278\n\t210821A01200202204A21201200000A38A572402142000010000000000000000FFAFE5400800400410400400400400400540\n\t48040102800011340000010490890800000000A140100100920004122108007066108100100960102100100100500100100000752040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A1001842009\n\t028500710604412210524731700600202000E0460C01004260A600600640600A04E000446082206244004000008000000000\n\t000000FFAF4F0008000000098039A09950018AD80180704500002022B20464B612023660422E08618E00A128226006020008\n\t016616182006000402026060206032006004404180180000000000000000FF88980000000000018010000018298418030110\n\t01090040602200E04600A4060140960060362900102C60064064560040040041260200020860900860420AE1041440000000\n\t00000000000000FF553400080008000000000001405000200A1400401220008008048010108090110100008000100080100000f52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF055D0000000000818DC8408810458AB8AB001891800072202040601623622620650E45E57E4861002AE2AE0A80882AE0\n\t5E32E2AC0402AA006500C062AA2AE322AAE000000000000000000000FF9DA620000000021180290383180980180101380180\n\t800970080060861061160060060260060368000060060060460064060060040AA002046A0009600300600600600000000000\n\t0000000000FFFD040000000000438210488048A380180112102B80400024864D623601200215452650630620230000600640\n\t62060040C410600640200250E10024600000610A004000000000000000000000FFFAC7000000080009805840801805911811000d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600610600\n\tE006092004086800084010806C24006000000000000000000000FF85A600000000004190180091191195595515590180024C\n\tE54431635644443602421621630601250455655651011055655655655650E5504D6484944442556494D56000000000000000\n\t000000FF00290000000004B18818898958918AB8AB08D8A3C00000A3570B732622622A22603708680614E4002AE2AE28E4AE\n\t2AE2062262AC2022AA24E00082E2A02AE00AAAE000000000000000000000FF52E54000000004138138AB823823801801801E\n\t05814000001400600610E00609604602602E34400000600600024000600600600000600200600040E0080060260060000000008d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (058100016110\n\t126146006086024026C2ED0E20680400600620042000400400600622A004056B042840D50070120060000000000000000000\n\t00FFB2410000000000C98B1804801801801801200841A0100000062162160D400E50E2960860260325000060060060060060\n\t0610E000106006106000856004006002806000000000000000000000FFEE8A0000000001018438208A98818AB8AB0AA8D980\n\t222A12248468062063224069061060060830042AE2AE0E80882AE2AE2262A80462AE2070040063072AE2A22AE00000000000\n\t0000000000FF9CFD000800000005801804841001801801C4080180A204000400600610410610C80600600600080000600604004d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t0DE80000000000AB8018088018AB8AB8030888A5802000E08242644622E2043260960160460000002AE2AE28E08E30407442\n\tE3041020A62AE00213600C2AE002226000000000000000000000FFF8570000000000019138A08C3801801801043803810000\n\t024020E0A600608C00600630612608A0040060060004000060865060A040640400600440C40400601210E000000000000000\n\t000000FF4B7C0000000000018418048110018018B100081180122A600810640E08604611423605640E246000006006046026\n\t0B640E00600E0CA00E0060001061240062A2006000000000000000000000FF8B0900000000020580188880502B801801001800cd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006086002000\n\t22628600600400200E00620000E006000000000000000000FF884C0000000018AB8830010A10AA8AB8AA80D8AB80500D428E\n\t08600E4860362AC00610628E2560002AE2AE0AE4CE2AE2AE2220880862C62AE0002AA2162AE0882AE0060000000000000000\n\t00FFF95300000000195595380B90515595585095591181203000401060961024124100062265165160045565561105102564\n\t0612A43000E036556004226546552130546006000000000000000000FFDB5880000000180184180181300080180084180180\n\t0040004620612604240000000E44E02608600200600640600600600410A24001601600600200602600242000600600000000002d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (102A40001060\n\t0E0840A000423685740E02E001006006006046006004207011126086004000002147004210006006000000000000000000FF\n\tB3DF000000001C0101584584500180180088180080000000B020E2A604420000200630612680600400600644000000600612\n\t2300016416006004002016002127006806000000000000000000FF0AD20000000018AB09195D8010AB0AB8AA9018AA813000\n\t820007640621C1082AA5C60060062860042AE2AE08E28E2AE2AE00A0206460262AE0002AA3062AA0062AE006000000000000\n\t000000FF084E0008000018018010A1051000801882801821800005430E02E00642E1460242A610600604600600600642002000ad2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFFE51\n\t800000041810801009801001D05925E09811000248380010624E04020620022604620E006001906136480089806004002100\n\t00F806004020004007844002006006000000000000000000FFAC58800800003A00C01801C41081AFB8038C180D12C120A542\n\t4E6006C281C6008006D2682764641080748625644601601601283082700601C0180140468140070070060000000000000000\n\t00FFC024000000003841249801A01484801C00901820830080C01600600680C00815400E00E12700E0040078060000000860\n\tC62A304024680E0A4004003006284003006006000000000000000000FF0E8E000800001801021881889000A0180182D80081006d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (061000200060\n\t26008022186006000006246064080000000000000000FF16AD0000000018898818B1802001889841808083800022E6220862\n\t2608E21844E4B639630607600A00E046146116106106540010406016160002016286190006086004000000000000000000FF\n\tB2628000000C18008080048010038058338A380108020020862360964200864C220E0260873160201468463260064065360C\n\t228800641600400041602E234002826006000000040000000000FF47D5800000021828850000841A05A01A81829843084010\n\t215240643620042610204640641600641010621600844001603600B08001600600404000682622400600600600000000000000ed2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (042010040800\n\t03300A82300504080000800000004062460002900900000000000C81000000000C0428000080000000000000000000FF20C2\n\t0000000C181190190180508594980980808180A02265260CE04625250000E02E0160060C60000A6006106516406024000300\n\t00620E040000016556124002106004000000020000000000FFA9740000040018818098219490098018019040018400106002\n\t40640E1020004C630614648641604041604622002004651604002800604600802020600620C0064060040800000000000000\n\t00FF08E10000020018018018058A808982584584001D92A009600000610600601000600640E0060060122060060002A80260001d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF89440000\n\t0000000202004002000040008000000401010000200280000001000202A01000000002800000000000200000000800000000\n\t001002000000009242C0000000000000000000000000FF03370000000AA88C8408C081000C8AA8AA88888881602A204A0700\n\t003224022025C00000002AA0002AA2AA0AA0C82AA0222220002AA2AA2002003D22AA2101022AE222000000000000000000FF\n\t9FF200000000004208500002800000000100200000800041042080A010800400000030012000000000000000600600000000\n\t0000000000000000050000008100000010000000000000000000FF73ED80000000000004802A1020A4000000040022000001009d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20002AB2AA22\n\t210021BAAA22228BAAA2AA000000000000000000FFFDEA800800001200004000041200401000040000000100051020032100\n\tC044004008448020004002804804020004004088000000004004844302000005024210004000000000000000000000FF6C59\n\t908000555951D0B903915835D5584B913911800045628E104094D4C434504004224515556000557556556515556556236001\n\t55655644E00054655641600E556556000000000000000000FFDD6D0000000AAAA8888892902CD08AA8AA88A8AA80002B2002\n\t08200A22210A2B200210228A2AA0812AAAAA28A28A2AA2422B20002AA2AAA8A0002022AA2800422AA2B20000000000000000005d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100018400421\n\t400000890000210010000000050000000000820000800000208440208000000000800000000000000000000000FF58390100\n\t004000404480100120002004C80400420080140C201004081201300002300504080000810010002400008000000C00008008\n\t000800000C0000090000000000000000000000000000FF81EF10000000000000400202000C00000000400000000101002080\n\tA0010000120000300120800200000000000420000000010000000000008280000000000040000000000000000000000000FF\n\t28138000000AA88A8808B08809A08AAC028C88C88061B0300A426446203A0221A0960160462AA0012AA2AA08A08A2AA2AA2000dd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (520308802000\n\t008000D00802815302C0980811204180A4472C0282000208AC0AC2A87000A842022004420460118480000000400001C40001\n\t0008400485000005400040400000000000000000FF6BC2040000080000940A00A00802810804A42800A0005020821060A242\n\t250B002C02006402812008242002A0288202300200280200A20202200080220A802002202002200000000000000000FF56DC\n\t00000000000000000010022800200000002001400008400282000808008A01002000900A0400000000000008000000000100\n\t200000000000000000000000000020000000000000000000FF4BEF0000000000040020004022800000080C408A0000030B08003d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0020020022A1\n\t002082002800002002000000000000000000FFD08C10802000010801001003240000809008024020814004A80114005000C0\n\t010408A10128041240000400440150000550000000010000000808000000800200000000000000000000000000FF4DAB0000\n\t00000008C20E00802C00840C00E088189A218920020430020C201210280200220288308000200281202B0022AA0028020020\n\t02002080802002003202002002000000000000000000FFB854040000100001941801D05805A0980594584B80405048541545\n\t56546D3412430700448E0D641240600600600D04700702608720600622600080E00E006006806006000000000000000000FF00bd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (460524100400\n\t0040200641010000E00600600600C00408600600604601600000000612601400E004000000000000000000FF6CFF00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000600600000000000000000000\n\t0000000000000000000000000000000000000000FF93FB000000000001400201200000400000000001000000500400400000\n\t4004804004000000004000000000006006800000000000000000004800004000800001000000000000000000000000FF769F\n\t000000000002820800800802000A00A4B400A22010200210200A003202222123002402092088002002002000002002002002007d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000200005\n\t891A00245801A414B9089809A040402004040004822A0011000828791528808000600690600650411400F00600620420E189\n\t840086006444804004000000000000000000FF5C63000000200003901800861801429001200A01880000200C04000C804808\n\t238880006000040040026006000200004004016006006004C0600000012688690C004004000000000000000000FFD9E40000\n\t00000005801A40405801831001001811A94080700E40400E1001005004901423121000080260068402400040444060160564\n\t0604611008044E006045004004000000000000000000FFFDE70000000000018418040010050010A91158218000090100104200fd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (070260000400\n\t0E8C6005006006000000000000000000FF8EAD000000002001805800801800805811001000880028AA1400FA140168058165\n\t11A0001401040200600600000120220200600400600704608200A00610EA84006006000000000000000000FFE07900000011\n\t0001801840001C00801B4100109095000014000043160060AC2460404000028004000070060310A000220200683640602600\n\t600040802704C085106006000000000000000000FF622E000000000001821824205804801801205420A0C088910052424611\n\t688410720002030A02003001600602604601202230600C02E0460260001024170450C4016006000000000000000000FF68D000032040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E0426C00A008\n\t41E4026800826206080140802602086006046084006408002816007204012006000000000000000000FFE7E4000000000000\n\t0019540018058210417430410013006406104006004402100046104002046004046806206006002022006006006107006004\n\tA00206006006006016000000000000000000FF247F0000001081000018000038451012210011010540000000104006004152\n\t28004600408210600408E0060C8000082012046506006846000004C00056006846106006000000000000000000FFA7370000\n\t0000208581385EA59BA28C3D07001010A00288A00C6C81647EE00004628800060008800008E0060071468021020262D4407000832040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002044000439\n\t01891800815002C032290010436306145124A06406A0602600E2062440940060260070261060261060030062068020049440\n\t2600714A30A02E000000000000000000FF1577000000000200001834211C003010A400114100835068270843040064460268\n\t0602700610051011700E00110000600600680103620600222000620F00E802092806080000000000000000FFCA6100000000\n\t0004003A00281801A01713400080323022210400708600C00280050582480048628810EC0E10600680208210E00601620402\n\tE05000208600E486082886080000000000000000FF9364000000000002063A808F18015014090B800069201122446184060000432040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600414680211\n\t0086000006000000000000000000FFCAC900004000D802201911803405811821C219000092810550206916A48C8F406848A2\n\t740604E50508702600604690684690680680620600600400600200102E10D046000000000000000000FF09B9000020200042\n\t001800822C408410B0029000089004280524644402600A1C090C233006004A21087006007006006006066802006002C06000\n\t606046806003402016000000000000000000FF5EF3000000008020009808801C27861008285480040105292D00620D00E082\n\t82248608200EC0E00500E086E000C00061460160A200680425600540790688E102002916000000000000000000FF2D42000000c32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (406444416426\n\t42605440E04E10600600240600E026006084004004004002002004004006000000000000000000FF6C470000000018000018\n\t0180000180080180180000000040000060060000060020020060060060000060060000000060060060060060040060000040\n\t02000004000006000000000000000000FF6D4D000000001800001801800001801A0180180000100040010068060008060028\n\t00806006006004006006807006806807007006806806006004004002800004804006000000000000000000FF5DCD00000000\n\t1800233801930001A0588390D8502800C0080610600680000600000208601720604C0161064001000060060061460060040000232040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180000180100\n\t0411A05800809A0564800444801460A6C00148916D5515651654654C156526250120002046926106404154006A2482680620\n\t200400200E000000000000000000FFB25F010000001804001801000819C01908AB3931001000502602E2060000411060840C\n\t6206106006206106A0600600200600E4068440C463400661C002602004002006000000000000000000FF803C000000001800\n\t001C01400001805201945A45080005004F0C6A072A401004709610710E80F50008620625052021200F12700E10A0048A4801\n\t004806802804804006000000000000000000FF994F000000001800001801800801841049801801053010030641614E00C48000a32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (026027206026\n\t807006000000000000000000FFD21D000000001801801801A01C01601C00C09A01808004240500710700601024308C007096\n\t0062080170060000208020260060060040560052A040600600600700400E000000000000000000FFDD22000000001801801A\n\t01A0101100380000180284000028CE14682640A1400884070B6C062C61201465068D030002208E0868864240870040080060\n\t02806006806006000000000000000000FF3D67000000001801801801A01401001C00009A80A8000B22DD2860AE2BAAA86C62\n\t2C22E0AE28F02808E2AE12E68624A31E0A640F8E8026004110406042006846004006000000000000000000FF687A0000000000632040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (349070428869\n\t0000F10E8A82888040860A62B621420D094D004848A68B28A2A46006000000000000000000FFD88B00000000100180180904\n\t5252803B2C521800A00090680600E00608600602828723648920601022600600000008404E20600600000300400084421620\n\t780208E4B6000000000000000000FFE19D000000001001801801001800801800C01800800880680500600600600600100400\n\t6000806000006006006006804006006806000000004000804002806002004806000000000000000000FF05E9010000001805\n\t801801801801045940801015854801A000006806806800042025006807046500006826306046002006026E4700400491480000e32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A000A0120000\n\t046180090049000908500C0080086850900140050080900001080000000060064001A0800029000708040000000A000280A0\n\t000608000000000000000000FF7A4C00000000000800010808C0821100201201000100010200010720038040208200340401\n\t410400A10008006806000001F410D1050810408000280100400040051020000000000000000000FFA7C50040000010018118\n\t0100382180185080888580082261000860060061064C005C0A624A00601000640608E09E004C0E006C0680C004084050C760\n\t84202102286806000000000000000000FF0E15000000201291C81B41311A81A81A00A0AA958808C2ECACB26C4EC368C7280800132040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0640428E0060\n\t06000000000000000000FF7D82004000420D54F48C20C12E04C08C34850CC28A8181348B08328300B22B00B12B0230322135\n\t0881300315290301200208245202A48322302004B8A30130230B2402000000000000000000FFCCDD0000000402440C024021\n\t020028020B2422000C000080212008008000209208A0000820B00801028880861200810800080A00200804800A8080000881\n\t0810828880000000000000000000FF131B00000000090090080484090C800804C05802900800249252200200240200210200\n\t2100082081002002113100082802022002101002014001004462082402102006000000000000000000FF01FE00000000009100932040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02000800002A\n\t82A80A8088320A202A8808AA80282000002202A8200000020A20000000000000000000FF30F4000000200800A00C00B40840\n\t820A10800A00802020A802812822A22802802802902012012A0000300280240280200A8023220024808A2800902802932A32\n\t08A012000000000000000000FFE37000000000020200135020C11420230520320001000A0B308C090080081054CAC08088C4\n\tA24840005004C00024890904004804804804814A4080C000804900A00904000000000000000000FF0FAF0000000018018019\n\t039418819259011030018000006006416006406106D24006106504106000006406006014206506C4600610601400E010406200532040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C0020140AA0\n\tC84002A400202802480082A80102103095002001091082092A82A82A94A82202282A82292A8020000001220AA82A82202482\n\tA8000000000000000000FF1B860000002001543542102D45041102841343500080100C10890D00A20D50930808CC14490108\n\t01550D50D31510C50540D513085503008A8800900D50CB0D20328550000000000000000000FF86DE00080000040000042049\n\t06C040040031000841010080011010014401410400310A984080100080100100080101010000100000051115100800000100\n\t1011900000000000000000000000FFE0AA0008000002A80AA0420000402C80600A80AA00008100002002080882A00000482200d32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (48048B400400\n\t0000000000000000FFF4A1000000000800800800804940800800920A4A800000A00201600622200288200200622201200000\n\t200200204200A1120020020024480A2000802802002092002802000000000000000000FFA8EE0000000000A80AA102040000\n\t0AA08E24608000000411006422AA1898002008082A2480CC0000AA82A80888883212212A8320AA80806004003302A82A8320\n\t2012A8000000000000000000FFF4A70008000002000000840000084020104000040020C200C0220028090000200500010080\n\t320422000000000040000810000021000028200222428000000008801000000000000000000000FFDD180000000000AA0AA000332040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A10A1001000\n\t0010000A10A9009021009009001041019001011001025000000000000000000000FF2DEC400000000C00D00C44820C52C54C\n\t00C20C50902311301221213243314349350A04335344B0A10034020C30021030CB00312301314900B0010032030434030430\n\t02000000000000000000FFF54200000200980180180180180180185380380184022444060442040864160060062040060862\n\t002C612600642C22600648E00C046000406000126006006006086006000000000000000000FF2EDB00000000020300035133\n\t020D20122000900040A2AA4B308C08008004C80482C080880C224A10004804A4040488080480088C004000810A080880008000b32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200004401\n\t2008010201003025020002810854002001010003041024810000E3161003100000100084A800021010043003022000002000\n\t0000000000000000FF391F00000000000180002404004C008021040020000203048440040004401020000400030041040052\n\t01200C625640000000408C020000008020020200000400100000000000000000000000FFDD00000006008801084800004800\n\t88210280B008820234202312918030A6020226030600321020000026020020404120427820020000A0302000092002428100\n\t002006100000000000000000FF8A2E40080000040040040000040052140859040008230811480000280810A10C908820100900732040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4CE006000000\n\t000000000000FF8E24000000001801801009801911815821800901000030000100700604001221200B4062060C6200006006\n\t00020008440608400011434000602000802C012406106056080000000000000000FF2B7C0008040018018010490758ED8EB9\n\t058258B309082502C204642E01206614E0CE3862260160300160060100000640060000942840106060200005824400040860\n\t0E000000000000000000FF884C000000001821805001001801900801851843100200051648E15608648600630602E0CE0060\n\t4022628600612E414156400100404000106208086006000144006006000000000000000000FFD14B0008000000400000200100f32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060060000\n\t2000200600200222588000400000402E036106046006000000000000000000FFCF0C0000000898A98AB80F8018C9880811A0\n\t08AAA0402B62020963062A22264060CE4462062AE0002AE2AE4880882222AE2AA2AE30000001400091C106326204806AAE00\n\t0000000000000000FFD177000000021800801821829801832945950800000000E00E00608600600610622600600600680000\n\t600604602600200600200208044003480022444E1060D4006006000000000000000000FF2720000000005803801101903825\n\t80180980280181200000C245605601210A2520024D614E00604000600640640610C00600400404C090486020100084012006000b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801901B02401\n\tC01200403008702600000600600400601600600000600604640600A006006000048409046841046000000004016806000000\n\t000000000000FFF2DE000000155955155955833925A03B01940105C02250410E10E15645645615645411644E55600C556556\n\t55051045255655655010845055200D55650050044D48F556000000000000000000FF8D88000000089AAB8AB881888889AAB8\n\t238308AD81002A64832264162AA32A0AAD130962A62AF0422AE2AE08E0CE3222AE2AA2AE2040A048400240425622E2D62A62\n\tAE000000000000000000FF324C600000001801801801880811B49A2380284900800164000060061000062061020261060060008b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00000000FF0875000000001003001801891001801801830A3180821040C68A60460A608E256810C2E10E0060100060062402\n\t200960060060044320C000600800630E10400A557006000000000000000000FF2CAD000000001A010018018458358C180DA0\n\t2005A03202400820E31601000610610410600600600000600600600600200600600410601080280080602401400400600600\n\t0000000000000000FFCD090000000AB8A90AB8AB801881A0B0B1C90081800224C240446C062003220022244062262AF8002A\n\tE2AE0880883222AE2AE2AC0062002AB0002AE0042242A40062AE000000000000000000FFB260000800023801001831845803004b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600640400600\n\t6006144124006000446300006006000006006006000000000000000000FF36CD0000000A90A90898A18C58AB841803088801\n\t801022404600E2160162043842A00462AE2AE2002AE2AE0EE28E2262AE32622421E0002A65E00263262642022AE2AE000000\n\t000000000000FF5DCD0000000050010458058118018A3911800811808210C30022602E08808C00C010086006006004006006\n\t00004000E00600E00408600000E00400608E00C14A006006000000000000000000FF57D20000000010030018118250018098\n\t41822945803200404E086086226046046000456006006120006006406006086006086094042000006400296006104002006000cb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (890408888100\n\t08020630E0862061260260140060060060000060060004000060060081060C600010200022204E00A1020060060000000000\n\t00000000FFCE530000000AA0220AA0AA0810AB8298AB0888A8813222800610600608401615428C00E2AE2AE2882AE2AE08C2\n\t8E2262AE20420E28600009200820A0AE3022AA2AE2AE000000000000000000FF985F00000011435411410C90915591584391\n\t2825804244808C0262261264124165442965565562A455655651013054E55644445040600045600410E40648045655655600\n\t0000000000000000FF790480000000000000000082D001901801800805801200013404644E04E28240604452600600600000002b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF1AEA0008000000D0400001841801040801020A33809200D04E08608722702D02290E45600600620080680400400601\n\t20061062569060002C240843220600A102006006000000000000000000FF1C9900000000040400040180D80111000100A801\n\t804288430522602E08E28400004608600680611000600442442000200682E080006000816080883136040012006006000000\n\t000000000000FFA88A0000000AA1100AA0AB8818AB0070AB0C4881801032440441E3064060442882060062AE2AE0002AE2AC\n\t0CC0CE3B22AE21600027E0000060001424062D02222AE2AE000000000000000000FF9B7B000800020200020040001001801800ab2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (41401028204F\n\t2B20043064000B2000106206416002002006000000000000000000FFD6DB8000000004018000510058018C1003848C0D8002\n\t20A20451622600E121A0320609620D00E00101700E04C0082822260020100060401040000864060020020060060000000000\n\t00000000FF0078800800002201A60409002803809041826AA1800286284D0C6006C0548100284600E1011060009068264040\n\t0606201745200CC061010440010070060801D6406006000000000000000000FF29FB00000000A00040000180180300C89110\n\t08C1852310509000601714600C0A808E20602622632C00604408400000B00710302614E40020E00400600650A00200700600006b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5805800024A2\n\t840060260460C61A60260A60042060800860060045402F429608600602650020404804204640600A01804E41000000000000\n\t0000FF79500000000004018000210018088830E2811837860042242C48E00E4166360560DE4060C814667810600616400601\n\t442600604605614040400000202E286052400026000000000000000000FFA024800000000401D441131218058510018A2A01\n\t008090600022648752600800A00441642112E00040F0A400C4C600A80E0029142962A00540C053628604E202002806208000\n\t000000000000FFE08A8000000100018000210018018A508D90080100C210F0C005644E0A402050350410651021608101601400eb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF00AB80000000040200002000000000802801002800000005102800801300102100004500080002000000C0006006010000\n\t1080900000004A84C01000000B00C0108000000000000000000000FFE3340000000004018001018418118010248400418100\n\t00602801620E0060920060D400E21010645000600404400620428610208600E04000C11048C3060460000000160000000000\n\t00000000FFA4CC0000000000018A204388B803849100900001840050E3065261264864020560042A61464360802961240140\n\t0010404600600E54600022000000201610E208000006000000000000000000FF819100000000000180001100B80090501880001b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A222AAA2AA2\n\tB22AA0002022A05022AA0B22222322AA000000000000000000FFD76E0000000004000000220104000A000100100000C00104\n\tA0108080000000080000000221000008001000200200010000508A0800000028000840C00003000900100400000000000000\n\t0000FF35430000000004A880009E8A88888C108008008100602BA1020183006123321902040004422AA0802AA2022AA6E83B\n\t22AA2222022AA00010200224A2AA4022022222AA000000000000000000FF8C4C000000000001800000002042044004024002\n\t00800040440200280001000200B0080544000020000008004006000000000040000000000000040000204010000000000000009b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (808134A02200\n\tE2162AA2022322AA0479022AA6002AA2AA2AA0EA2232AA00200B2AA0000020080022AA20210221BAAA000000000000000000\n\tFFF64880080000020000000000240200340100101100800010040404490000040050045208808044C1004810000004000805\n\t00480000400002800000C00400010D080804000000000000000000FF6F8F90000000015580011194391380DB3313590B8002\n\t407014424224D5654C446D56294017556081D565561561145465568440A655600004E5001255575064445465560000000000\n\t00000000FF01720000000000AA8000A08C88C88888AA8CA8A280022A342A3020021222222422CA00B00A2AA0002AA3222AA0005b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF7A\n\t3D0001000000044000806060002043080802000400020208000000800008020880010000A000000000000000008000000008\n\t00000000000000A08000000000A00000000000000000000000FFD49F09000000040200002212C04801000204402200201415\n\t1028009000008001000045000900000100000000040000080048012000000010048000100109020008000000000000000000\n\t0000FF7E72000000000000000000000004104000010000000100000002002000005008000008054000008800000000000010\n\t80000484010000002280003280000400B0020000000000000000000000FFE6B88100000004A88000888008C08208A88808C800db2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (680780700600\n\t6020006000A0E006006206006006000000000000000000FFFB2A0A802112000810820A00400102141900B40B08A0A88208E8\n\tCB00000830C243040A180C0243A86A44888445740040A09040040450000042A8000080004800404004400000000000000000\n\tFFB7370A00049008008008008C08408908C4C50940828010282220200A2B24C210243221215208A400212212002002002802\n\t002002022800002000002003002202002002200000000000000000FF74860000000000001002102000000400000020040040\n\t4000000001008000004000001004008001118800000402A88408000800000000400000008000008000008000000000000000003b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (003002802002\n\t08280280000280A802002000042002002000002002000002002000002001002002002002000002000000000000000000FF68\n\t530AC04103001001000C0400000220004104080200110210C094008008408440008C0008820140D001080000400011510008\n\t00000000000428000080000800000004000000000000000000FFE938002000808800800800824C00E00C008048008100C028\n\t0210200208280200246200200219A41000200200200200200A00200200200000210000200200280200200200000000000000\n\t0000FF3BDD140005801801801A899418419519457533430540546A57005816556547147C54496D2E5164101160170060040400bb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF877A00\n\t0001800000000021841011801883809905080005600600800600602400401240408600640000600002600622648404E04600\n\t6000106500006006086084040006000000000000000000FFE41E000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000006000000000000000000000000000000000000000000000000000000000000\n\tFFDDB80000000010010010000002000004010000000000004004004004804004001000004000800000800000000006000000\n\t000800000000000000000004001000000000000000000000000000FFAD62000080800802A00A00A008002000898008049040007b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (054016026000\n\t006240106016107106800006000000000000000000FF20B80000058000040240018A100583D911903C830020442022084062\n\t89240280600620480691620048600420602E00610400402620600008608054412211F503004026000000000000000000FF30\n\t59000001800000300001A1120181180B801029000018204800C8021008A844F00600600608600800688400620080E0F40060\n\t0640600000600001C006016006024046000000000000000000FF8013000001800010020301905001C41809A0502905204075\n\t128C644681228C8944820C54268D604810612048625001600400400E0460010060210840560060060000060000000000000000fb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (830AC0420025\n\tA40AF340084A8E606160006002207006A1E042024046006000806008C47712206012004006000000000000000000FF9F3700\n\t0001801845000001E41C0100141180D001E02022A12032C2020208260D600880752612600021600240F02000608204600600\n\t6001006001006006406406080006000000000000000000FF4FD8000009801820020601013901241801A454358080106A4320\n\t020E2420142058B000402604610009680400E02182602200404600600080600080601200600A084006000000000000000000\n\tFF62DD00000180181008012140B811201901811C018C8024E30604120600EA062A42908A43460360200060440C600644641200072040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF6CEC000001\n\t841821880461841049C03B4101E004100001C2C0404024200C668D60A40866260263100662027A660000618200E0A6186000\n\t22620012E02A20610302E106000000000000000000FF5247000001801808C000010016118058098402010220004801016D44\n\t4A108650600404400611600000640C8060062C6012016146006000006000216056506007804006000000000000000000FFAE\n\tE1000009801810842001009081831801AA00418000084A0600081420E00E40640410401600E0000878048060004460020060\n\t06006000006008086806096086004006000000000000000000FF807D000185867989000201825805205D01C09015812000A000872040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0600610000E0\n\t0188600210600300E046000000000000000000FFB993000001849B30A20485041801908801801049800000000EC971202060\n\t0E15402E10001700620005600210620600600E204086006020046400816523016402A46006000000000000000000FFD61F00\n\t0001801808800401001A00C40811C2150D8A2028004E426B0112E506054007022806A9610808702300602105601700400700\n\t6020006000506102836082006086000000000000000000FF894D000001801821880001801801821801A81891010048449094\n\t4004808806007B4408404624640008602282604600E0028060068060C044640004608202F80205602600000000000000000000472040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (810440600600\n\tE14008600E40600002600600600000600630600600600002800000E40600E206000006000000000000000000FF4B89000000\n\t245B15880009800009805852C05881844048040C48080C94643614700E006C460A620020EA0608620700600E816006006020\n\t0002001060A6007026226006000000000000000000FFA613000001801A43A4814181DB08B008AB91305082202C1207004048\n\t0262268050028000270A600120620600600700600600E106006000006000006002007022016006000000000000000000FF13\n\tD5000001843801882029AC38C3802F41B884808900020020114000080006404482003206206000007016006001506006086000c72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (EA0000000018\n\t018000018000318038C08018C18C0040201440E24402600648E09000402420620840603208600600200600600E0060004000\n\t00004026006006006006000000000000000000FF7D0500000000180080000180000180180080180180000000040060060040\n\t06006006006006006000006002006000006006006006006000000000004006006006000006000000000000000000FFED2F00\n\t0000000800800001A00001C01800801801800000000500680680400600600600680700600100680200600600600680600600\n\t6000000001004006006007006006000000000000000000FF6073000000209A0180C203140003809B0080180188000048440000272040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (608000001000\n\t601E00E817006000000000000000000000FF7C67000000000800800285001401851694C21C0584004424545411403440D645\n\t7446556A44C5655115604400612800042611601700E040000100036006006006000006000000000000000000FFCD2F000000\n\t0048008821812009019A1090801821808000228602600680C80600600080400402610004640401600600000700600E006000\n\t000000E04006006806000006000000000000000000FF56FD000000001801882201020001C4980192D80D80A11565448C010C\n\t50834E844220156B0D0D60401061020464A950A00650600603608008000008400E00E006806006000000000000000000FFD800a72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004006806806\n\t116303004801406805006846800006406006016000500000126046006006006002000000000000000000FF5D87000000000E\n\t00601000A01A01A01081821801800000620D00582000484401720200E84220748000E00400702900040600680600E0000000\n\t8100E006006806806000000000000000000000FFF44F00000000180100900380380101180BC01A059200C4604654C0842A6A\n\t97C4605052600B04E05032602228E08002A0A688E00F00602000000800600E00600E006002000000000000000000FF6B6300\n\t0000001801011001A05E81001829D89883980022202C29D2AD2A0EAC2AD2BA02623A28C2A94A62AA5BE28F2DA1060868070200672040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000023429221\n\t12ADA15A41A825098C9B018000C2280682C057244CA484E82AA04926C160012C6808046A08CA401608608703600024000002\n\t488E086006C8EC2E000000000000000000FFF49F000020001021003201C41883C29805A03851800008E0A720430408800850\n\t440102041602600000E32430608000408604E056906000100001A0C4460170CE046102000000000000000000FF7C6B000000\n\t001000001201801801A018018018018000002004004004000002004002002806006000806804806006004006006006006000\n\t000000004006006006806000000000000000000000FF1F5D0000000048000010808418518350018C5811844011600480400000e72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (500000000002\n\t002902012002000000000000000000FFCF9700000000180580185404400008000A52002800000440208040140042242A0A04\n\t004240024000A000A10101061100000200B00A8000A800000082290080A0008124000000000000000000FF94730000201080\n\t000000020001220781400404900000100480400E083100480005680004100100000880093806DE2810090C08004400000400\n\t00061001080C00560080000000000000000000FF57A40000000000A810F00190185180209128190180000A20042440000841\n\t8400E0161040AE00600000600080600602480680600E016000020000E0644680601608600E000000000000000000FF335D0000172040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (461465064060\n\tA601600000600E88E0C408600600E00E40600004000004650E00650630E006000000000000000000FF4D75000000400C44C1\n\t28C0D40D14D48C80822812800122300B00201354B50340B83314340BA02001C4300200241301208284240384A00050000140\n\t202280202B043282000000000000000000FFF5BB0002002403422103082022802004010022400000A00800108840C08C00D1\n\t0000820801608000060A10001001000980810801000000000000804994000848A00E00000000000000000000FF1777000000\n\t026800800CA003880490080020C804800040A0120230A206200204200264210200200040200202300000200200B40200200000972040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0880AC0AA082\n\t08808800400000400200002A00008002A00000002202200B02A82A80002A8A002A80882A82200402A82A80002A80000002A8\n\tAA82482002A8000000000000000000FFDE1E000000204800A00A00A02C40D00B10C20950800080280240200294288290210A\n\tA02802002000002042802A22802002A0A802002000000000902002002882912002000000000000000000FFAB990002002202\n\t0420023124040242A0453154010000810CA80D080CC0CC310080008110000000000048880048048008941250040040008000\n\t00C34804004844841000000000000000000000FFC02100000014590190180D815841801A319019418000106406D46444004000572040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002308010002\n\t10008000000000000000000000FF51610000AA0A80CC0AA0AA0AA0280AC0AA0A812200003002402802A00302002A82082202\n\tA82A8000AA82002A82A82A8228AA82A82A80002A80002A8A282A84882402A8000000000000000000FF0B7600015435215035\n\t43502423122C82B02404B00000D40C00529548AC0C88C804C1020D51550000550528D50110550540900D5055000055000090\n\t0550550900CC0550000000000000000000FF2F20000000404600400400400402400400404608000103100105181150115100\n\t08C1011001800000800001000001001900001001800001000001000800001001090000000000000000000000FF5AEC0000AA00d72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080490480080\n\t4000004104800204804914000000004000800000000224004A94C04000000000000000000000FFD327000000004804800800\n\t800902840800810800800000A00240210214208200210A00200200200000282A002042002002002802002000000000802012\n\t0020020CA000000000000000000000FFD1A50000AA0880800AA0AA0AA1000880AA00000800002801100002080002002A9220\n\t3282A82A8000AA93502A98882A8220AA82A8AA80002A80002A89802A80600002A8000000000000000000FF38820000000004\n\t0000000208802000000208800400000080C8800000010020028808280000000000801000001441001010208000800000000000372040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010005000004\n\t0042044840240008000810810092D10102A90D92812050010084092010094210410014010010014000010A00016011053010\n\t81001000000000000000000000FF4AA5000410002C00840C00800C10C54C00D24C1095003431031130834C20CB1035334334\n\t5300A00951301308300300300308B0030024110C0001043003003003103000000000000000000000FF31BD00000001180188\n\t98058219431019098018A1800000624602420400620640600408608610600004644602608410600640600E02600000000000\n\t6016236114006000000000000000000000FFDC710000002202312002002002312052004A32C300008414A88D4824C088308000b72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (608605620020\n\t4000000000000000000000FF92780000000000020500820520000440A000005000000002001101204202402102A024048024\n\t8000120020000106010100000100000000000080000400000400080100000000000000000000FF197E000000003801829804\n\t0000B000C0200C0040048002044412402424C00000402C148544000200030240300126000200090010020210000000020080\n\t040000080000000000000000000000FFA750000008008800080880820812890084900988804020210200200A092102322002\n\t10001A18240008200200200048240231200220200010000000210A08A00A400000100000000000000000FFC931000400000400772040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02610A406000\n\t00613600404608E006004006006000000000100006006000128140000000000000000000FF1F1C00000000000100800980D8\n\t2182090184182180000040120040042040240C60400464000060000060061040000062060840060060000800000002060060\n\t00104100080000000000000000FF544E0000000000010878098419A3805800821903884018C00E00600604041803400C40C0\n\t6445600010E2460A03000061060040060060800000001820061AE180064018000000000000000000FF2FEF00000000000512\n\t190580180B80982288180D900000C2860880A000A08420429409409408620002E40604040640E00600C1060061000001000000f72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002982580180\n\t9211801801800004400210401408610280600712E00E00600000600600200008600600200000600000000080500600600602\n\t8000000000000000000000FF5049000000089AA80AB9018218E08B98918AB8AB800022640E00020010E0C2054004E942340F\n\t60002AE2062AC2C82162AE2AA2AC2AE0000000004042AE2AE2AE144000000000000000000000FF6061000000005800001801\n\t90D810801801801801800001428642000008600220408400C006016000006006004006046006002004006000000000234806\n\t006006404C08000000000000000000FF8BE300000002000500014B80180580282B801801800010604210C14C242430154448000f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AE2AA086200\n\t000000000000000000FFEC0F00000000580280000185580004194180180180000060944064C64340124040D4006006006000\n\t006006004206106006002006006000000001026006006002400010000000000000000000FF45CE0002000C1B009519019099\n\t541258A1955955800051655425022020C42E55442C40654655600055652E55453044E5565525565560000000015565565565\n\t52485548000000000000000000FF6DF90000000A98A90AA04B88188D885C038AB8AB80002AE04212C0140063020842001462\n\tA43060002AE2AE2AA08E2462AE2AA2AC2AE00000000008D2AE2AE2AE0102A0000000000000000000FF7EDB00020001184D00008f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C60060000060\n\t0605200600600608E0360060000000000C60060060120A2000000000000000000000FF28F400000004588080185588080080\n\t3801001801800044E00010E14E24603200244C00410E00600000608E00220010E00600600600600000000000680600600242\n\tA140000000000000000000FF712E000000009805802001845001049909801801800010600442400408400600408600E00600\n\t6000006046002006006006002000006000000000006006006002002008000000000000000000FF76930000000858298AD885\n\t8090AB081E278AB8AB80000062AC00430404E2872AE1002A62262AE0002AE2062AA0A82262AE2AA2A82AE000000000AAE2AE004f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (805805001841\n\t001801000000005400408602000600005600410600000000600602E0460060060060D4006000004000006006000016006000\n\t000000000000000000FFFD100000000898AD8000018908898A98890AB8AB80001062A000410424622612000E34400E2AE000\n\t2AE2AE38608E2AE2AE2262842AE0000000002162AE2AE332242000000000000000000000FFBBF000000000180184200100C8\n\t03805825001801800001600020404402601248210611420600600000600600644000600600600000600000000000E0060060\n\t82012000000000000000000000FF09080000000258048898D384084080180100180180003260080B650E096102010224044000cf2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A241E0000000\n\t00000000000000FFF73B000000001A0081090180180502182100180000002040162A401620000640610600600A0060000060\n\t06002000002006006044006000004000122006000004006000000000000000000000FF197C0000000AB882AB08AB08988988\n\t388B0AB8AB00002AC20602C23608800E2AE3062AE2022AE0002AE2AE28228E2AA2AE2364042AE0000040002022AE2A82260A\n\t6000000000000000000000FF9D25000000555B51D4203592595188D915155955000003054401444011055602842E4144C255\n\t200055655645655055655654E48C55600000400040655655044450E000000000000000000000FFC0FB000000001811804001002f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20090A648704\n\t400804400A007281106000100000007006001000005000000000000000000000FFDD66000000025802888001001831805A25\n\t001801000000402609650809400C08E2220070820000000060060844060040020161448060000000004A2006000000104800\n\t000000000000000000FF4ED9000200201A01842801805805831809001801800080080D246040821546000102002045002001\n\t006006802000802002106C1000600080400000B006800012446000000000000000000000FFC9CD0000004898E98000AB8E98\n\tC18D18810AB8AB80002A838450600060054422600A2AE25E2AA0002AE2AE22A0AE2AA2AA3260042AE0000040001522AE2A8300af2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (218018910419\n\t01914050A20128740320210E0440262464430D6140C8650614408842400A04F00280612000208010C0060A88864040000000\n\t00000000000000FFFF85000000003C0100114484010582580D4918018409A2202432522104F88608420002603300C0200060\n\t0648A0000130438160460060004020022060078A0086004000000000000000000000FFFC74000400401A014310A00200CB88\n\t3A43089829934911303501C80B02680624411948340904610140605E80210740A02204702688614120210211680701000640\n\t4800000000000000000000FF3AEF000000401800E20801801811881901021CC9000000420100680E40421640902388E10608006f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (014000000000\n\t0000000000FFE244000000080001041000989949801801801801808000600409401008600022408204A01C40A00820608620\n\t44804240040260040060000040002020A6000052000020000000000000000000FFF73E000000200403481004801883863061\n\t8A1881880004E0940442C2236682114702032120082030046266494206004004086504006020104000482206000022008280\n\t000000000000000000FF976D000000201A4002380A801821801883205A03800004241000E03600202E11502F086282246200\n\t02E0070040062149120060020064000020000050164B0092005000100040000000000000FF1271000000003800209800001800ef2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000028006\n\t080010000084000000004002440000000010010000000000000000000000FFDF280000004244040880280200800D40040000\n\t0000000102881080300003085400000005400000000000001000260081000000100000000080000080000004C00A00000000\n\t00000000000000FFC87F00000040044228580580180D84394592588188000362080061062464940044101060061000400264\n\t0610010601008C026000006200000000506486008002000400080020000000000000FF7B8100000010000140180900980180\n\t180180180380880060861064421060244CC12000E4C203241040E14620000004000410600000604000000200004E2A008201001f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C8888AAC8280\n\t082A2302242402AAA0328AB2922AA0A292A0002AA2AA34208A20322A2AA22A2AA00022A0021022AB0000CA2AA00000000000\n\t0000000000FF848000000020022000000000000000000020000C00000D010100040003003000005023108008800080100000\n\t0001020088000000800000000000200000000288100000000000000000000000FF465B000000288CA8C008068808369008E8\n\t8AA88880002B20022020022A20020022422020022020002AA2AA2122882322222AA2222AA0003A20000D62AE000402200000\n\t000000000000000000FFA33100000000180184388001200800100000002200080040240403040140440141480C8008148000009f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF3C44000000088C208AC8808848AACAA8AA8AA86080012830022AA113202203402202002082242001AAB2AA38208A\n\t2022222AB9032AA0002020000422AA0000022A2000000000000000000000FFE9F90000004002024041100000000200044014\n\t4800080008548910C8800500A01004001408C000010050040002451411000041050040000000024050048000040040000000\n\t00000000000000FF24F6000000555915F51955949955955955D558818000406C2C55782650748615650410644E4060005565\n\t5645633451644755623455600155600008DD56000044456000000000000000000000FF6C150000000AA8A88B08408AA8C080005f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00800290040C\n\t00800080000000000000000800040000000000000000000000000000FF182F00000000000000000000062820800810000000\n\t00500000000000000420C60400008200200000800C0080000008802800000000000000000000000020000000000000000000\n\t0000000000FFA3F600000022421200000405400040000000010A0000010A880008301089485400A834023004800000000005\n\t0200090090800410800000100000081000000008008000000000000000000000FFD204000000000100202048000000000000\n\t20000000088200200003008200010100000080001000000010000000200400000000A000000085000223000000034000000000df2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (955913840105\n\t492690754491692DAAD10C81680E5564514860068060042AE206006084000000200000006004426006006000000000000000\n\t000000FF73920200800000A80822030224424003C16030816940C0CC882848140400AC004CA42004298042A800442C004534\n\t000058000404000000000028004004005004004000000000000000000000FFC2D40000100C08008008908808008A08049049\n\t0882C00223020020C2093002002012002012022200082002002002A028028022020000002000000030020028020020000000\n\t00000000000000FF689A0000000000000000000400000043200480040000208040100410040888508280000000108030400A003f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFFE33000000000800800800800800800801080800A0002020020000420832032422020028020128280422020020000020\n\t02002002000000000000002002002000002000000000000000000000FF507E0201000040A008220410000200008000010028\n\t000880903000050000C8000000200028800A8000004900004000000800000000000000002800000080080000000000000000\n\t0000000000FF5CA1000000002C108008008C4800800800804C00800000280200202208200200214200200200A00102200200\n\t2003802002002002000000000000002002002003002000000000000000000000FFA614000010141801801D11941809B5581500bf2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (65010040CC20\n\t400C000100200000446142007014356300000000000000000000FF33FD000000001831800081801801801021801801822002\n\t440E1060080024024021120120004060A005601604604600400404400010002000000010600200E004006000000000000000\n\t000000FFE41E0000000000000000000000000000000000000000000000000000000000000000000000000000000000000006\n\t000000000000000000000000000000000000000000000000000000000000FF62890000000012000014000012002000000004\n\t0000000050050000000040000000010040008000010000000000068000000000040000000000000000010010010000000000007f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (05800003440E\n\t10600800614354000315412609640008603610610600202220200200004040000010600201600E5464800000000000000000\n\t00FF96E1000100011841810029827811829001AA1A518220240802A06A4658221700F30D0428122460E006E0460262268940\n\t040A40040A00C00000002270B282632504E000000000000000000000FF68410000000019A180025180080580100180182980\n\t8009082240E0243041060060A420400300600000608600600010408C10500804000000000000600304644400600000000000\n\t0000000000FFAE04000000041A01800001AC5800831005B51A4D8080504046816C2020004214A4225408C00964001061460800ff2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t7CC0000000031841911061801801883C01C21A1181000C008A18608614601229086360C09404600100600600600600200300\n\t200600004000018001E0020A6006006000000000000000000000FF91CC000000025813E01001808801883C01D21C21882190\n\t6932806145C0604200040204F02400602804684E00E000002002082002000000000000006082306406026000000000000000\n\t000000FF0F3900000000390C880401811801801881881801914000C2460072000470A3050A0300442680600900600E016000\n\t002002082806000000000000007103206406006000000000000000000000FFA19D000000041C08800481D0180380184380980000a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08208A202004\n\t0000000000400060068060C6106008000000000000000000FF3931000002000001003801812059029F210558258000310014\n\t097084256CCE00420600E82225654808E0268161C001A00201A00408000000002040E0068060260260000000000000000000\n\t00FF2B7300000A000021000B058010810518410018218080024004104824504906A1442E0260C200600010E0460460060020\n\t0200200010000000000009782CC8720D246200000000000000000000FF266000008000010100080180300900190100180180\n\t0000CA04804404004086524906007302006000006806006000013802802000000000000000006008046084006000000000000080a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (808862004040\n\t4024724B01A043046002026200007037026040006106006004000000000020506044107516406010000000000000000000FF\n\t4EED000000101901802C11A01905C008014818419000404010044003926086546096C2F12608E01000600600601600600600\n\t6005000000000001407106516104006000000000000000000000FFA37E000008001A41C00B0580180188080522DD11808013\n\t4D1005480209620754600E20610E03632000720604E000086016206004800000000000806814406805106200000000000000\n\t000000FF3D07000000000001003801A03001501805001889880040628442690600400E0A400640E01240601000620E0060060040a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF7D77\n\t000000015801A00809A01901801000C034218000A00000802000242022022016203006016008006006006000006006006006\n\t00000000000020200428C006006000000000000000000000FF8ACD00000010190BA01801A218058210109110118940116212\n\t0400869003125021008D0924146B0080682700600E8060060060060000000000400120060042862060000000000000000000\n\t00FFF525000000001A63A05801804801800B01009809802000F8010040820070200130020860030060800060070460060060\n\t0600700400000000000000E106006206A06000000000000000000000FF112500000000BA09801801832941820989203E059000c0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060164060000\n\t000000002C6A26AA4006006000000000000000000000FFD66100000000000180180180184481188400182D84003500464940\n\t80008404002000004086236000222202006006102006026006400000000000002006004006006000000000000000000000FF\n\tE0D8000000001801800801801800001000800001800000600200200600600600600400200600600000200200600000600600\n\t6006000000000000002004004004006000000000000000000000FF86BF000000001A01801801801800001400801001800000\n\t68020008068068060070048000070068008028020060068060060070060000000000000020060040040060000000000000000020a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A2AE22C8EA23\n\tE2082E92CEAA50862D60B13AA0B21AE057482106006656208000000110023102004006006000000000000000000000FF5C23\n\t0000000002018008012158000C5E04151801B140806554814516400414492284CC45575062A140C14504E001003417006106\n\t000000000000006000806005006000000000000000000000FFB879000000200181A018210118009238A00018818A40020004\n\t80400000008480200485480600E04001410404600600200600E0060100000000008020240068040060000000000000000000\n\t00FFC2BB000000000401800C21A01A00223820483881A80100028C0260305200B454B2C830604408650010202250E000002000a0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF154C0000\n\t00001800800001011A441110051058058000006000904806107040084844814046846400004C04C070068028060460060000\n\t00000000506C03546806006000000000000000000000FF699E0000000018018010010018000010032018018120802C810040\n\t0300600000D00450408D147D00805005046008003406006006000000000000007002004006006000000000000000000000FF\n\tA98B00000000180000200100BA000A500113180190010000540164C840A408C242A6046246C0E02828A14A88E02020288E80\n\t632E000000000088802083006006006000000000000000000000FFCA86000000001801005401000A000010014018298020280060a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (602600000000\n\t000006640200E00C006000000000000000000000FF5918000000245B02A81229201B02B0120123181380008C3050C34C2303\n\t0C02800804D04B0F0AE000D20A804C6080884306037246000000000000C26902D27204906000000000000000000000FFE05F\n\t000000481840C242018B30286211450838C18000210304086110B0008E3280A0026026206000004024006000024006106016\n\t00000000000010E20200F00D226000000000000000000000FF8AD7000000001801800201801800A010012018018000002806\n\t004002000806000006004006006000804004006806804006006006000000000001802002004804006000000000000000000000e0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01244A002003\n\t003002042022402000002282803000102103002002000000000000002042402000802000000000000000000000FF40770000\n\t00081800113A00012001000420080020000124400000C2844C5048E044C42842040A80000201708800060400000805400000\n\t00000000A04010840200880000000000000000000000FF4E8500000002600006000000018804000000A60400000204200C00\n\t00101000030100110448000000500400A50006081080100208000000000000080180280140220000000000000000000000FF\n\tB8C80000001019A08840111A98360B10010218C9800040E200404036030002040004004094006000000000026806004E06860010a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002A00000000\n\t590180580182B8018C18A9801805800044600400E00621410401415440640600600044E00E00680410600E406A8600000000\n\t000000632C02600E026000000000000000000000FFC49D000000510C40D28C14C80C92C10C00E20AC08001903343AC352B14\n\t2022A2220313305340200110334285200B0424A2123042000000000001843003C13522002000000000000000000000FF3CC2\n\t0000002002002000002002002001822404020000000984B20900A08380089030C20800A00000AD0800001090820850C09000\n\t000000000000008A00030C10040000000000000000000000FF0DC100000001084280082C844800900851000100800018204A0090a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t001041001001000000000000000000000000FFD97600000008A0A80A80AA0880CC0A80A82AA0AA00000002A8210000018000\n\tA202000202002A80002A82A82A8AC8A20220A202A0000000000000AA80002A83402A8000000000000000000000FF1C900000\n\t00240A00800A00A04A02A00A00800A008000152802822C02822C0A10A8D228288300200100200200200210A91201200A0000\n\t00000000002C82802802802000000000000000000000FF9AA800000020020420220024024020220300100100004008040891\n\t28C848C4004804810849004001001000004024800804884004000000000000000834001154804000000000000000000000FF0050a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000100100\n\tC0AC0000000000000800800000090080000888000000000001000028000000000000000000000000000000FFA9A300000008\n\tC0A00C00AA05200C0A80AA2AA0AA00002202202A8280280200B002080482282A80002A82A82A80882292282200C000000000\n\t0000AA82882A82A82A8000000000000000000000FF6C290000003503141543543303103143501541540000440D40C00A30D2\n\t0AC0CC0C10010D28D50000D50550551311440C50D48440000000000000550A80D50C08D50000000000000000000000FF7F59\n\t00000042041260C40050048040400000040000018011010010510480D004914180110100000100180180124110000101080000d0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000200234\n\t2012002023084022002014010000C048308008C0C8088804484881500900400100480480482480C108804B44000000000000\n\t004825004800804000000000000000000000FF91EC00000000080080C8008808248408008008008000152002002012022022\n\t11210228204200200000200200200200280208200A000000000000002512002002002000000000000000000000FFC6D30000\n\t000AA0800A00AA0280400884AA0AA0AA00001102902A8200009200A002005202802A80002A82A82A82882A03203294100000\n\t00000000AA80002A82A82A8000000000000000000000FF4F62000000004020400000004000040002400400000088801012010030a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002000000424\n\t000C2012000000110000000000000000FFEC1100000000002040140A00000040E40040452002A10012910311A10092012090\n\t21241081080109009241031009001001001000000000000001011001001001000000000000000000000000FFDC8D00000000\n\t0800D00C00800810C00D10C00C0894C142B00304343334331340B14300B4834D241100341344301301300B50300200004000\n\t0001003023103003002000000000000000000000FF568E00A00005582184180B801801831845941841800008430648600600\n\tE02608420E3040360060000D6006006006006086004006000000400000006006004006006000000000000000000000FFFA1E00b0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (640612031624\n\t24022D642000600E00600200604400200600000000000000602400000E444000000000000000000000FF7317000000000100\n\t00408A05008C0840218000880040040040200048500010110208000040100140020008000006100000300000000000000000\n\t000020200020040000000000000000000000FFBF090000000218010A18000000090010899240101000034008004404544148\n\t080484008454230280120030010006010108284000000020000000010020004000000000000000000000000000FFE92A00A0\n\t0000A80080000080084087082680488484002821023CA00A00200204204A5E600240200000200220200044201204241201000070a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018108050\n\t0188484B80180384580180005340042B240E0420160024024842B20060000560A600604600E0040040060000000000000060\n\t10130090004000000000000000000000FF1C250000000018018A100580480310380180590580000042040083062220062060\n\t000160440060000060860060002260044A420E008000000000026004420044004000088000000000000000FFA60800000000\n\t18008A1011852910041849809811844000E24450A2861262762120C210821802E30004608600600410603400200600000000\n\t0000006404180006204000000000000000000000FFCC65000000001881803081800820009013811801800003008402602E0000f0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00002AE00202\n\tC2802AE000000000000000000000FF7FBA0000000048888410008C880000180180180180000558A600001200200400A4C000\n\t600600600000602600620000600200600600000000000008E00E004004006000000000000000000000FFCD6B0000000AA081\n\t8A80899118000898898CD8AB80000000BE1028260062362B01A01081462AE0002862162AE6CC2A62AA2AE2AE000000000000\n\t2AE0101042602AE000000000000000000000FF4E27000000000025C00043848900243841801801800000040600610628E106\n\t00A00E04200600600000600E0060020060020060060000000000000062A4404004006000000000000000000000FF72FB00000008a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0440A022C2AE\n\t2AE00020620E2AE0A83A62AA2A82AE0000000000000660402AE2AA2AC000000000000000000000FFCECB0000000218200028\n\t5180500184380180180180005060C60505405041040020020060040060001060860060061060020000060000000000000065\n\t44402016006000000000000000000000FF30FE000000151822012955805955D559558D195580002804165572A02D452C3020\n\t1654E5545560004D648E556130456552550556000000000000406504552556556000000000000000000000FFF34000000008\n\tC08A8A90820208AA089CAB8898AB800005420620201202A2242A2448A5420E2AE00022E2262AE08E22E2AA2AE2AE000000000088a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000285180\n\t1801801801801801800029600640601000800C10A0860C008600600000600600622600610610800600000000000000615200\n\tA00202E000000000000000000000FF987B0000000000000108018A184B801A01011801800053600E09640804008C4AA40690\n\t000600600002E08600640001600600000600000000000010E002002002006000000000000000000000FF1C970000000418A8\n\t00580180D001801805943801800000410400010428C00600600A004004006000106026006006006002000006000000000000\n\t406530006002006000000000000000000000FF2A6000000008B8025A18AB8010818AB8A98058AB80000042242200240042260048a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5565445524B4\n\t034000000000000000000000FF115F00000000B80180B8098000030010018018018000214006010080004002502056002454\n\t006000006006006006006016004006000000000000006006002106004000000000000000000000FF6CA100000003D8A80AD8\n\t118438078098AB8AB8AB80004043040062A02A02A400400E0080062AE0002AE2AE2AE08E2AE2262402AE0000000000002AE2\n\t122A6282106000000000000000000000FF014B0000000038020019038C98B194580100180180000440D41480000000044464\n\t2040022E00600000600600600000601604000600000000000000600200604A484000000000000000000000FF98830000000800c8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (082060042AE0\n\t002AE2AA2AA0AE2AA22E2042AE0000000000002AE58637A4022AC000000000000000000000FFA268000000040003C0080180\n\t209102080180180180000840260800020081260A60802C800600600000600200240000608601600600000000000000600400\n\t0004204000000000000000000000FF96690000000C00538C18818320B10AA8AB8AB8AB80000242AE2A02202A82AE0262002B\n\t40862AE0002AE2AA2AA2AE2AE2A62D62AE0000000000002AE02E20002E2AC000000000000000000000FF8802000000501951\n\tB5094590804110D155955955800004C41644854A54441241242E00232C5560005565565561505564565045560000000000000028a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800A05800C01\n\t803009801C01800100E08700531410614520500620E087006200406455104120003027006006000000000001006004004011\n\t804000000000000000000000FF569D0000004018ABA21803A2C001801001A01801800129600648403512E004524080056086\n\t80600000600400400600208610E006000000000000806024804148004000000000000000000000FF8B690000000038018008\n\t09800031801001801A01800004680604C08600400400442708622E0060010068030024000020060250060000000000000064\n\t16102402004000000000000000000000FFE4780000004A990188B8E59800838AB0AB8AB8AB80001062AE0042142042AC01C100a8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B64864828260\n\t00140400000000000000FF9543000000401901801005800C0180100802182584210A400048E24C5004B0890C420C04161461\n\t28446444CC408604200692400600000000000088610600A006086000000000000000000000FF7E2C000000405801E0000180\n\t084180100382190390A810602020200700A0000A001312120E1360D013600220200010200608580600000000000248610604\n\tE026006000000000000000000000FFFD5B000000203801A01401A00821803001A01C418C09446E001120454424100105CB00\n\t004680E00108F0030520060C2006044806000000000002A0600682200F106000000000000000000000FF3E890000000019010068a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (628E44E41052\n\t62004000364B4006006006000000000002086106084082404010000000000000000000FF2E9D000000201801801041842801\n\t889001851801800000628441204640E00E00602A02604610600008620420422008409600600600000000000000604604400A\n\t244008000000000000000000FFEF8D000000001801C0102102080380300580990183004361440021240560064CE28241E166\n\t20640000601409404600C246026006000000000000086006020042004000000000000000000000FFA1C70000000010018A80\n\t11808931801008021D21800001402132EC8CB002A0400002D00D0E8B641023600400401022300E004006050000100040006400e8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2214304000A0\n\t1180000000081100040040A40001001000140540800000000000400100060000001100000000000000020004800000100000\n\t00000000000000000000FFD9B800000068000040408001000404000180000000000201080104080300100084A00804300000\n\t000001080C0006088000040000000000000000000010110320108000000000000000000000FFA11F000000401A01D0001080\n\t1905885008001841800002400600648408600210208200600600600000E00010040000448604600602800008004000641620\n\t44120040000A0200000000000000FF2693000000001801829000815829811000001901840800C5260C600C01655221244A4D0018a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620455600000\n\t0000000000000000FF9B990000000C08AAAA88928888A88880AA8AA8AA800832A20A2A200221222223208A2A24022AA0002A\n\tA34B2A20AA2222AA2AA2AA0000000000022AA0022422822A2000000000000000000000FF3325000000240400040022008400\n\t20900000000000008000010010808000080802002200010000000000800A00000800010010000000000000010000002B0090\n\t000000000000000000000000FF007D000000028AAACA88088008888800A38AA8AA80002022222B24022C2332322402202100\n\t2AA0002AA2022026AA2222AA2022AA0000000000002AA472220052220000000000000000000000FFCBA900000000380180180098a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000090\n\t140200010000001000000000000002000000408120000000000000000000000000FFCC980000000BCCAAE068B0CC08AA8C08\n\tA28AAEAA80002AA3A23422223022022130030022AA2AA0012AA24220A0AA2222AA2AB2AA0000000000012AA2AA0220422AA0\n\t00000000000000000000FFCC4500000040A20020204004440422500140140100090001208011510800040048400110550040\n\t0100500081000110800480100400000000000300410108C004014000000000000000000000FF653500000050195591190190\n\t3955903955755B55800055745741745642E52444493610ED57556000D56C1640E356C57556556556000000000000556556800058a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (204008804A04\n\t00000000000000108040088040000080C20020000C00000810000400000200080000000000000000808C0800800000000000\n\t0000000000000000FFA65901000000400000000000000204028020228000000008280002D0040200208C0000800800051080\n\t0000288000008000000000010000000040800000000000000000000000000000000000FF3F300000002004000B0002002000\n\t04000820000000000000081000000401280004A04C0000000001000020000000100800000000000000000001000000080408\n\t000000000000000000000000FFA8B200000000200000000843000001200000000000080008008308901100000D081101000000d8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002000000000\n\t000000000000FFA3DB004102015C51801911905AC1A55D15155F159400515557556046556546B57084A06156006341016006\n\t00610684600628604000000000080000620E006006006000000000000000000000FF9EA00A00000A80000800030092057810\n\t4B483001000100402C0255008002210200048500844008300040145504000146A4004000000000000A880140800150000040\n\t00000000000000000000FFAEF100210400CA28800C9090090084480090880C8A00D0A5032228024420831420020020832020\n\tC8013002022082022002402040000000000000003003002802002000000000000000000000FF2F4D000000000000000200000038a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000008000\n\t06000000000000000000000000000000000000000000000000000000000000FF6175000000002828A00800800C00C0080100\n\t080080A089280290280200200A00220200200200280080200200200200200200200000000000100000000200200200200000\n\t0000000000000000FF29DB0C00000A80002100040140001200121044000000C0082882082802024000000010088000004080\n\t0000000001000540000000010000000508001100001000004000000000000000000000FF4933010000000C28908800802A00\n\t800800C0080080A028A00208200280200A64200208200280351000200300200200200200200000000000084000300280300200b8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (843840023801\n\tA04021655653640A0D4312D42012056007221010146006042546016046206000000000000000104800106006006000000000\n\t000000000000FFCD0A00000000200080180180180180180200180B8400046006006082004026006502486106000000006026\n\t00200040601600600000000000000000400A006086006000000000000000000000FF44BE0000000000000000000000000000\n\t0180000000000000000000000000000000000000000000000000000000060000000000000000000000000000000000000000\n\t00000000000000000000FF8BFA000000001200001000000000000001A00000000000000000000000400500400100480000000078a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF673500000000200480000181180180180004180D844005210600650004404E0864041560062240082071060040\n\t80406016216000000000000001906016006106006000000000000000000000FFD784000000000001801801801D0393182384\n\t9805B10020622E28E02208418202A08A2020860040401260060B222608E0B600600000055000000042800608602200600000\n\t0000000000000000FF0A50000000000000801821801805803801813801800000600702604A00F200210802802E0600400048\n\t6926102000166106016000000000000000854006006846006000000000000000000000FF3A1400000000000480184181180100f8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600C00080\n\t6016006000000000000000007804006006006000000000000000000000FF642A00000000112180200183390191394B805811\n\t81000062C6C2684C004822182030A02106602000006006004806006806006000000550000000402007106002006000000000\n\t000000000000FF4341000020005000800001821801843805A498038C0000628702709400700004824140A006002200106006\n\t00500000700600600000000001010000200702E006006000000000000000000000FFF9B0000040022105800001811C018419\n\t200158898221202026A060A000480222B21480F906804C0000600600400600600600600000000000810000680612E80200600004a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01A01881A010\n\t506926006204005800200814044246202001A0E00E0040060260460060000000000008008020060068000060000000000000\n\t00000000FF55C9000400001885800201819927821C01803847800007E0069C614412650008004C53413F0021000060264240\n\t50006006896010000000000004014246006000006000000000000000000000FFFF06000000008809800001801E4984D81184\n\t5801822080401620600C4440210A988000480600400000614604440680E00610600000000800000088240409600400600000\n\t0000000000000000FF0DD1000000040845804001E05801801809A0190180302058060060040040C6406000004006004024000084a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF6C8C000000003A95809C03C81811815801841D2984504062174EE91C9021000503C632190600600480680E40600004\n\t604700600000001008000410104610608A006000000000000000000000FFFA8A0000000908210018A180381595584DA01803\n\t8001826006206100000007106017008206002500407006006406006006006000000410010810A02006006002006000000000\n\t000000000000FFAAB2000000008A01001801C01901801809801C41C0000870C6006441202426A06806A1120620288020E88E\n\t00622801600600E008000000000000013006016802006000000000000000000000FF0059000000001B0180000180180180180044a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002007006006\n\t006000000000000000006007002000000000000000000000000000FFC8DC00020000982880180184180182182BA008018000\n\t00600640681080681600440E20500680608500600E0060000060060160000000000000410060060000880000000000000000\n\t00000000FF02BE000000001C018A98438858159118018018A1E0400D6C0E056100006006104800024206006A004070060062\n\t06006006006000000410110010C06006002000000000000000000000000000FF2C960000001059090A1901821801805801C0\n\t1895802108E00E10600480106E60610601000600680000600600600700600600E0000000000000200020070060020060000000c4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D82988804262\n\t062A611450E2A64CC9504060D000F10040602643240800600600608004800000000000600600600200000000000000000000\n\t0000FF9F0B000000003809900001801841801923841883842000E0D600E0440400080044000B620000604000601600200600\n\t6006006000000000000000006006002000000000000000000000000000FF11E1000000000800801801801801801801801801\n\t8000006006006000000000004004004006006000006006002000006006006000000000000000006006000000000000000000\n\t000000000000FF8D4B000000000800801801801801801C0180180180010068060060000060000048040040060068000060060024a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF50E5000200001001A02001901A0180988988B089C8000063AE2AF23A0AC2A320C2060B468640E1A828616E32225E016006\n\t006080028000000010806006002000000000000000000000000000FFE746000000000800800005C01A25801801835815C540\n\t40604E417545250456214D554C0150154A2C40640604C1000060460160000080400010012060060060220000000000000000\n\t00000000FFEAC6000000200868804001801A21801801921803808010F00600640400080880400C20600056401010600600C0\n\t06006006006000000000000000006006002000000000000000000000000000FFB60B000000021A0080000380180180B8118000a4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060060060\n\t00000000000000002006802004000000000000000000000000FF1653000000044001100005801801C05C44000C4184415460\n\t0700E106C0100234414401405050CA0000600600400000600680600000080000000120600600402200000000000000000000\n\t0000FFD64D000200000001200001881A21801C002208018000006046007C8702400200401408404090505000600600400600\n\t6007006000001000000000006006804002000000000000000000000000FFBE55000000001000800003A0180580180181200B\n\t82C140691640604A20F44A015546A4C28F2260812062A60AA0A800E0260160000080400000080060060020010000000000000064a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800082600600\n\t600E210082804004000000004000006006040040006086006000000000000000406C26414206000000000000000000000000\n\tFF178B000000228028B41A11933A31A35800021911824012744600EA46C2CD0A004884046C80824A00A2EC0E88884744F2A6\n\tA06000000000000880828326C8482E000000000000000000000000FF6C6808000040360280D8818018038819418838038880\n\t21611652608B10702228C85030001611401080600684400800601610600000000000100128200604E306A000000000000000\n\t00000000FF4615000000000201801801801801A01801A01A018000006006806002004002004006000006004000007806804000e4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFA7\n\t9F080000000C01810A00C20B00820801250892920800200300200206224200047A042042002101002B0208200200A0030020\n\t00000000000000082806020002000000000000000000000000FFE7DA00000002180000780808800C00000192000040212080\n\t8862001418400C001004484A084F8208300050430106000A000000000000000004D00000111C05A400000000000000000000\n\t0000FF6B180000001120000800002040005000218806000C811804208882A040001150918093008010000002800000800E00\n\t0060000000000000000100220080208008200000000000000000000000FFC2D700004000023A86988180180388BA0020180D0014a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400480400000\n\t0000000910800B04004810000000000000000000000000FFF616000000011809001801805901941A210A1001800200600641\n\t604E0C640E10601400C10600600008600E206086006006006000000000000308426416116206800000000000000000000000\n\tFF26A5000040480840C34A04A00842804C00810A94B40008320A8034032130222022C35238234B308000232304B043303A42\n\t002000000000001021002003C23082000000000000000000000000FF82E70000002082402004044022602442C02025000008\n\t000A11010C40808C20A84000A00100800801000C08800820F20409280000000000000800848A0000080100000000000000000094a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008001001821\n\t008011481021900801021400000001011001001000000000000000001201400041001440000000000000000000000000FF7D\n\t090008000A80800A80AA0AA2AA0AA2A20AA0AA0008A802A82A82200400203802202A02A83008002A82A82A00A82A82A8AA80\n\t000000000004100108082A80002A8000000000000000000000FF0529000200402A24A00800800800A00810A00800800A04B0\n\t0300208B00B00A812912012002842400802802812802803002002000000000000A00ACA0428034C200000000000000000000\n\t0000FF04210000002002092020010014014010012010010108805004004800AA0C808248048040009108C0805004800C01000054a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF921700\n\t0800000082000000000000400010000200000104800000108808802000000880880081082300000000040000000100000000\n\t0000000082080808000008000000000000000000000000FFDBBD00000008048208A0AA4AA0AA4AA0AA0AA0AA00202A12A82A\n\t8208220A80028288210AA83081102A8AA82202A82A82A82A8000000000000010150B082A80802A8000000000000000000000\n\tFF9B8B0002003522303341545545541543443541540100480D50D50440C00D08A50CC0540550420500550D50CD0950D50D50\n\t550000000000000800C40540D50D40550000000000000000000000FF508C000800430030440000200400000400400600000000d4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (016000000008\n\t250000046006016006000000000000000000000000FF606D000000203104202000001401001211200401004014C00500480C\n\t8044848210D0834004904900804000888C0080100400400000000000091080C004804D04000000000000000000000000FF95\n\tCB000000828A28800800000800800800800800800080200200208200200A0120020820020120080020020020020020028020\n\t0000000000020042285200204A000000000000000000000000FFC8B50000000840000A80AA2AA0AA2AA0A20AA0AA0003200A\n\tA82A83203A8860280200240AA82202012A8AA83200A82A82A92A80000000000001000802802A80102A8000000000000000000034a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (320820820501\n\t220021820020020E000008200200200244201A00A000080000028000010402008016100000000000000000000000FF205A40\n\t080050040000040040240040042040040200A108900100100109D5812410090011116010A13110480E800100100100000000\n\t0020081601021005001001000000000000000000000000FF16AA400000C00C008C0C00404C00C00C80C12C10892104B00B22\n\tB03308305310B2830430430030C1003002092003003103002010100420101001003103503003000000000000000000000000\n\tFFF6C3000081801845801814001801801845801905840050644610608640600420602E50C00614E00022621600600600601600b4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF71CA000001\n\t84100100180801183480392B001801814002622600600E00448A116014082006020102496000204028004006006000000000\n\t00040201408E204006010000000000000000000000FF082C0008800000000500100080C210A0AD84000000804200A0400030\n\t2000104200101000001100800800200000560000800100000000000005100000802802C0000020000000000000000000FF9E\n\t960000000818220C180800000000000180D00808002402104300502002100B42202B01500080000504200000060001000000\n\t10000408200000000080280000000000000000000000000000FFE42F0000808010008008020008000008830108C0820001240074a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000000A\n\tA0100006206006000000000000000000000000FF259A000001801044003800001801801801855801804000600600600E0962\n\t900024A455601608E04000600408C00600400600600000000000000825000612A0B6000000000000000000000000FFED1500\n\t00818010000810040418018118008C180380002860860060A60C600020010240614600600000602400400022410E00600040\n\t0000000090000206016056100040000000000000000000FF6EC40008018210010D7802021908901800091843862009601640\n\t60864942620CA0062020A611006020E00020418600406601600020000000000000200E10C50600800000000000000000000000f4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E2A600E0082A\n\tA0044402062084002AE2AA28E4AE2AA2AE2AE0000000000001482022AE20240E000000000000000000000000FF9CE3000001\n\t8030088008000018008018008C980180200060060060072060810002004C0006000400006002006000002006006000000000\n\t000308008006006086000000000000000000000000FF8D880000018A80908A80AA0AB8AB8AB8A20858AB81802AE2AE2AE2A6\n\tE04106AAA40A1002C62461002AE2AC2062AE2AA2AE2AE000000000000400042AAE042246800000000000000000000000FF84\n\t02400001802008800000001800801811001801C000006006006006044026006000000046046A800060040460000020060060000ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (22400001A41B\n\t058A80AA0AB8AB0ABAA28018ABC0802AE2AE2AE2262460022A805A0042062A90102AE2AA3060A82AA2AE2AE0000000000010\n\t6074C2AE000226000000000000000000000000FFEE3E000801A04A45841800001801001801820801A0200060060060161264\n\t4200012801411608602000600404600600200600600000000000000011700610D106000000000000000000000000FF571B00\n\t0001908821935954155955155954804955808055655655653609623255608000C54E55610455655443655055255655600000\n\t0000000000007556354457000000000000000000000000FF11010000018A908088A0AA0AB8AB8ABCAB8898AB80002AE2AE2A008ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000002040\n\t6006020006000000000000000000000000FF08FF00002100084184C000001891001801801801801000600600600600C03404\n\tE10008E006080000006002016206006006006000000000000008136006110006000000000000000000000000FF75B9000001\n\t002811802000001801801810901001C0200060060060860942940064A05560D6000408006002096200006006006000000000\n\t0000080460060D0096000000000000000000000000FF99570000019298C580000000180180180184D8018010006006006016\n\t046022000004004006000100006002026006002006006000000000000280104806400806000000000000000000000000FF33004ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4104C2450102\n\t5405564160045564964D6350456556556000000000000020416556510556000000000000000000000000FF14318000000338\n\t0400180000180D80180100D80180820060060060060001080004120060060860140060460060060060060060000000000000\n\t08006006010006000000000000000000000000FF55EA0000890A98898018000AB8018AB8A392B8AB80802AE2AE2AE2AE3242\n\t040060142222AE3060222AE2862260AE2A62AE2AE0000000000000020062AE2002AE000000000000000000000000FF68A900\n\t000500380590180000182580180888180180400060060060061040845004280020060360040060361060000160060060000000cca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00AA08188008\n\t00000AB90B8AB8A30830AB80122AE2AE2AE2AA2AC2C61000023002AE20200C2AE2162AA0AE3222AE2AE00000000000000845\n\t62AE4002AE000000000000000000000000FFC408000820000801C00000001829801800031001808200600600600604001608\n\t044401600604204200602600200008600600600000000000000A0A6006020006000000000000000000000000FF261D0000AA\n\t2808B00AA0000AB8218AB8B30A18AB80502AE2AE2AE2AE2A820622812422E2AE2320042AE2862AA2AE22E2AE2AE000000000\n\t0000200862AE0A02AE000000000000000000000000FF43C8000114553935B558001559059559540039558040556556556556002ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (11800008200F\n\t000007000000000000000000000000FFE027000000600800C01C00201E09C21805011001810200604F08703210421612400F\n\t20E206004005007A86104001003006006000280008040000004006006006000000000000000000000000FF34DB0008000008\n\t4884D800001821801801041001810200600680600300505604C5260000061340068060AE00440680A8060060000000000000\n\t0220C00602E006000000000000000000000000FF925700000002B802C00400001901A01811209C0180220070060060020040\n\t06D0000F150806002000006006002000102007006000000000000040126007300007000000000000000000000000FF29E70000aca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A50210482E4\n\t2E0044000470565042C8442016106020000000000510108206006484000000000000000000000000FF6BB880000020000300\n\t1A00001A11A018410A1AA180A044612604743028610A09242404A1165040289260A630440682280700600008000052001002\n\t2806200004000000000000000000000000FFF0D3800104001005801800601803801821001C898A01A87C0640600505308240\n\t7A40000096282000116006402240042007006000000000200008141096217806000000000000000000000000FF1BD3800882\n\t401000401C00401C01C21803549C418040047106AC6404C0A862A1618514304605A05084E846002026802807006000000000006ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (441001520002\n\t00582184985309180580005464060D62A00062920CE0A602A24E00020004601620020600400600600000000000000010004E\n\t406304080000000000000000000000FF9059000000401100890012001823821801081803800008600608E00440208602E026\n\t00000600400000600600400000408600604000000000017000048E24E016410000000000000000000000FF98FA0000000010\n\tA04000080098058038890098119C0012643620600C06240604601E5824C626C02008640600C00600C0060260004000100000\n\t000021260B000E288000000000000000000000FFB9B8800000020001C29000023801809843043801808040620F0464A0A16C00eca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006802AE1020\n\tC2000000000000000000000000FF2FDD000000403804101800000000000001080000000000000000000400448001400814C0\n\t00000000000000000206000000000000000000000010000000490448000000000000000000000000FFB95E80000000000804\n\tC00000000000000182A00000C00000000000080100480000404000001300200000000900061100000000000000000002C002\n\t8000020000000000000000000000000000FFDAC6000000200041A00800049803805881045801890000602E40601003600240\n\t60161060864500201060260900B023410E0C600000000000040000C08610E002000000000000000000000000FFA55C000000001ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (621520655644\n\t60005565564265564575575560000000000004C0427556126086000000000000000000000000FFD8850000000A88008AA800\n\t0AA8AA8AA8AA9088AA80A02AA2AA2AA2A22AA10A2A23020422AA32A0002AA2AA2820AA2222AA2AA0000000000002480022AA\n\t40A40A000000000000000000000000FF7FF20880000000D04000002000004001004000000021000800001000000000148100\n\t049000110011000000008000080800800000000000000010010800408A48000000000000000000000000FF87F60000000A88\n\tF54008000AA8AA8AA8AA8048AA80002AA2AA2AA2B22A24022B22920122AA2020402AA2AA2224AA3222AA2AA0000000000000009ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200000000000\n\t00000080000000010000080000081001013002000094800010800000000000040001000000000000000000000A0C00004405\n\t00000000000000000000000000FF88BB88000004480C8808000AA8AAEAA82A8AAEAA80202AA2AA2AA203A223532020421032\n\tAA2020012ABAAA30A0AA2A22AA2AA0000000000000021022AA00200A000000000000000000000000FFD66B80080040410140\n\t000040100140100044040100008050050050000000448000444810040000010040040480000110048040000000000001000B\n\t4804020900000000000000000000000000FFA4AA800000691801D55800555D55955855955B558101557557D5754E536404C0005ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800100200200\n\t0000000000000000000000FFBD1600000000000000000000002009231000004000008001080100004400C8C4034800188004\n\t01000A0000000010000A08000000000000000002000000800000000000000000000000000000FF6577000200000000000000\n\t00000010002203800800002A00000000408002000C8000048000840002000000000000800000000000000000000100000000\n\t000000000000000000000000000000FF3FFE01000008808444C00040020000000000000000010000008000C01000010882B0\n\t4008000400088000000A00000010008000000000000002C0408800110040000000000000000000000000FFC4AB000000222000dca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04208A603808\n\t002002082002003082000000000000000D08020000002002000000000000000000000000FFC10F000511001B158038818018\n\t3581388570D0B5880081604F046C17A443160570AE0161070360C00C600600600F00600E0000000000000000000000000068\n\t06000000000000000000000000FF27430800010002010000020020011090510416000800548D0411014400C86058040C1046\n\t0410480000400000420840462C400000210020000A20010000000000000000000000000000000000FF9FE700010880091280\n\t490080080C800A00B0490490008122428C24B200200300300208220208A04000200200200220300220000000800000000000003ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100100100000\n\t0000200001000000000000400000400000000000000080080000080000080600000000000000000000000080000000000000\n\t0000000000000000000000FF5703000000800800000800800820A82800808800800080208A80202000200202280280248A02\n\t2008002002082002002002000000000040000008040000003002000000000000000000000000FFE2FC100001000000000004\n\t0040002080050400006800008000801001408480000008000000800000000800000C10001548000000200000000020800000\n\t000000000000000000000000000000FFCA30000000800A00800800800820802802826800800000288A002002202AC210300300bca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (005016000000\n\t000000000000000000FF6F46010001001811801800041809825801D4D005A040104206012147016406C45406156406006821\n\t006004006046227046000000000000010001080000004006000000000000000000000000FFC2300000010018018018000018\n\t018018118010A0000020C02E2822062C004600410E4061260060104061040160101060160400280000000001000000400140\n\t06000000000000000000000000FFE41E00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000006000000000000000000000000000000000000000000000000000000000000FF4EA500000000140000007ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (06006A000060\n\t04006006006006000000000000001008000008006806000000000000000000000000FFBAA900000180000100180004000180\n\t58088028A020400374164028874504840075060C620609600000600400600004702602005000000000008010002000E00E00\n\t0000000000000000000000FF4CE5008001001808801815801A49835815009000A00008407608E32E10203632404620E83614\n\t601AA0610604643E006016000050000500000040860001004004040000000000000000000000FFC38C000001001800001801\n\t801A018018010A1803800024480600601608210618400E00688611662200608600E00028600E00000000000000800204000000fca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801E05809803\n\t825800000080600680200400010484602600600E00600C006004006000006006000000000000000004000000006006000000\n\t000000000000000000FF4ACD180001800506001834000199905820A11980800080601601A1060024C4706C8686600615E400\n\t606006006006006006000850000118E0039020060080E004000000000000000000000000FFE9A6000001800001001E2060A0\n\t41801850800821800000E04600600610200C807107006006007000006106046410006016001000000201000C204400090160\n\t04040000000000000000000000FF6CB9000001880111031880014003901800E4C840000001700600200600024482620600600002a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C0200000000\n\t00000000000000FFCEDE000000800000001801801801801801885E04E200A560C61060A40020448860178B610620E02E1060\n\t0400630601612E000000080000000002000820106884020000000000000000000000FF2DBF000000800010001801C0182180\n\t1801A198A0020030229741241535293483E12620E2668461000060440060800064061200000000010004000407804C607600\n\t0000000000000000000000FF23640000000000000038000018418218018018A1A800006C0680280420620424644640640600\n\t680400621400600620600604000000000000000408000100E004000000000000000000000000FF77EC0000000802080298810082a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E04D00700700\n\t600601E006000000000000000904000001006004000000000000000000000000FF5C990000818018A10058018A1C018C1821\n\tD04804120001209710240E01A1265AE006A0680FC07024006206086000006436000000000000000081148040016904000000\n\t000000000000000000FF300E000601009E0004594A211945835889801800000010681630BC27007106407536086086106900\n\t006006006006006006000000000550200028C00001006004100500000000000000000000FF71CA000001001809001801801C\n\t018018018018000004942026C0A15694640E006C8E0C608604E0B008622E00620020E126080000080000001404001000A2680042a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018004018\n\t0180000048068040068060068020060060060048010060070068060060060000000000000008000060060060000000000000\n\t00000000000000FFB975000000209821A45891AC1803A93840020101C0000040264060160060060400CE4270168060840064\n\t0610600000602600000000000040000000C006807000100500000000000000000000FFF3CC000080201901A01840011949A4\n\t1890201841A200104C8E10E406016506D1640711600610E81400700600680600600600000000055100082C20600600600000\n\t0000000000000000000000FFD98F0000018018000018042018098018018218A08000006A2600204600224600600602E1066000c2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF8DEF000000000003883803801B0188184C502829C00021000728CC4632614C13140534682640281128E05611\n\t6001006016010408140080000000206006006000000000000000000000000000FFA0D7000000000121801801801801829880\n\t01190392C00404B604608E00E0042000D400E0160A2500006086426046106006400000200000008000006006006000000000\n\t000000000000000000FF8BC20000000018018018018018018018000008018000004006006006006006002006006006004000\n\t006006006000006006000000000000000000004006006000000000000000000000000000FF587500000000180180180000180022a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A0680E006000\n\t026426080000000000001A80026006006000000000000000000000000000FFFBC9000000000001801A0000000183980A083C\n\t09C0002AE2261263863AE2A42EF7AD23E0AE0E62A868E0F620E0260C60663080082800800085000460060060000000000000\n\t00000000000000FFCB96000000000001801905801A41905840113CC58500154556814C56416554110054106D56210CAC0060\n\t06806000806406000000000000000000006007006000000000000000000000000000FFF63900000000008380180200188180\n\t1800069803822090408608800F0064048000040861062000440070068060060060460000000000000008040060060060000000a2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180000180100\n\t0080200600600600600680600600680600400000780600600600600600000000000000000000780780600000000000000000\n\t0000000000FF47E30000000000419058000018019019400031419100002016C03046806814082004007006A0A08200601614\n\t6000806016000400040000000802406006006000000000000000000000000000FF8432000000000001801A84001801F03800\n\t001101E00090388F016407007004822204086137022020006046006007006006000000000000000000006006006000000000\n\t000000000000000000FFBBE8000000000001801800000041809840309043848004E4260870CEC8E34C8100CC00E2060064080062a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF6E860000000119238019180018018419142C580100000028C600201602600642610604E046000010006006006010\n\t03620600000000000000001000601EC06200000000000000000000000000FFECB2000040221901A23A88211911A9180A0C1A\n\t3315008D212EA0A42604E906D56AA6A86C068908308160A750E80603724E00000000000000080082600E0060800000000000\n\t00000000000000FF6F7608000000B84D801805803803803800005901000120200612601628600E00600E00E1164042000062\n\t060061000061060000000000000002001161072A6200000000000000000000000000FF4872000000001801801801801E018000e2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008808010008\n\t20000000000000000E00108000B00880000000000000000000000000FF04AE00000000080094080080480080080000020A04\n\t00213032183002202002A0A00300200200A60100A20200200300A00200000000000000000000300200200000000000000000\n\t0000000000FF3D63000000001A0400384785180C4000024000A000004A5000620C40488480004808F00A007C014000018060\n\t00C60004800000000000000100000860800A0400000000000000000000000000FF28C80000000282D803000000A68048A048\n\t52200002C00000080088218100080400000810880000000008200080068000080000000000000000400268000400000000000012a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02B255004090\n\t0804800114304810894000004004800800804885004800005004000000000000000A00000004804828000000000000000000\n\t000000FFF68F000100001803801821821901801842221801800015611600644640E206004816086106486520006006206006\n\t006406000000000000000000006016146200000000000000000000000000FF3B69000000414CA8D34D0CC14804820A881149\n\t0085212022432C2812803002443102A428230430100030830030528130020000000000000114511020034020000000000000\n\t00000000000000FF0AC608032020600020428020030200040001030009009485008402088008008802B000010100082900080092a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF2E3900084040050040050040260000004004040000000000010090010010010000010008000010010000010010010010\n\t00000000000000001001000001001000001000000000000000000000FF44510008800880000AA00808C0AA0AA0A000028000\n\t802202A82A8B200083A02202A82A82A82A80002A82002A82A82A82A800000000000000006000000022000000000000000000\n\t0000000000FF840400004C204A04A00B04A42800A00A04500800800081280280200304280280280280200300282080284B00\n\t2802803002000000000000800800802002912500000000000000000000000000FF97BD0002002202B12002202004012010080052a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80A82A82A800\n\t00000000000000E00008002A82A8000000000000000000000000FF2231000810004000000010020000400000048108008010\n\t00000000000900008810010008000000200000C8000000000000000000000000000200000000000400000000000000000000\n\t000000FFA5D700008C0AC0120AA0320880AA0AA08C00812200402A12A84802A82302A82A82A82A82A82A80102A82A82A82A8\n\t2A82A80000000000000001000010002A82A8000000000000000000000000FFE5DE0001243503523542C43105541543343044\n\t440020C50D50D51448C40C50450550550550D50800D51400D50B50D50D50000000000000800800800000CD0128000000000000d2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (818840006006\n\t00E02614620E1060042060060060002062062160060060860000200200000060000160004060000000000000000000000000\n\t00FF7ECF0000422202022002202004012010001414550080840000841005304800804005004804804888800805004A008010\n\t04000000000000004800800000005000000800000000000000000000FFA1A4000000004920800904842800800840A1280080\n\t2030280250200204200200280200200200200000200200200200200200000000000000200000200080200000000000000000\n\t0000000000FF84F70000880880480AA0080C80AA4AA08A50409001010182A80482A81082A82A92A82A92A92A81002A92A82A0032a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tB5BB0000200088008208008808008008A0808900862200210210204202200221200211010200200013211200200200240204\n\t040000000002000068A220340000040000000000000000000000FF53BC400C0000040000000000044040C4005904C00D032A\n\t12880293010882810010312010A9089281149281240001009000000000000081001011101441001000000000000000000000\n\t000000FFFBC0400440002C00800800908C00C10C40C00C0280013234922C341321210344B4A311355313350300B103002003\n\t01300208000000048144300340300100B000000000000000000000000000FF1D60000000009801821841803801801901801800b2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006016008000\n\t000000004000406618000200000000000000000000000000FF4A6600008000182102380084404184990080B80B8100506316\n\t00604610600E08E08000614644601010E2460060000260060000000000000045000060002404000000000000000000000000\n\t00FFBE100009000000541440400801200900A004C034008004820022041000050810048822041020044020640000000604E0\n\t1000000000000000055002E000400000080000000000000000000000FFB79300000000580000184181384000400000002201\n\t000000004840C84000080C828C108200040000486000028006006100080020040400400008006000008000000000000000000072a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000062860\n\t0600600411600A002006086840006006006000006006000000000000004800006000006000000000000000000000000000FF\n\t2E200000000208000018208000018018008C9845802000600204C00600609644610000600604E20000600600620600600600\n\t0000000000004008006000004000000000000000000000000000FFCBC0000000000814001900810001901840801801802000\n\tE0020C4206006006006000086006006300206086006000016206028200000000004050036000084000120000000000000000\n\t000000FF80260008000018011018D892A10182180084194184202C600E40601609E5666064104564360260C800603600600600f2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFC9B0\n\t0000000AC0AB8AB8320900AB8AB800889889A1202B02AA0242AE2AE2AC08E2A62AE2AE30E2202AE2AE2AE4AE2AE2AE000000\n\t0000000040482AE2A82AF000000000000000000000000000FF7CEA000400004001801810050001801E009118018120140006\n\t4260060060040260000060060060800060060060000060060000000000000040C00060000060000000000000000000000000\n\t00FF93FE0000000890AB8AB8080880AB8AB80000188980802A82AE4142AE2AE2240462222AA2AE2060002AE2AE2AE0AE2AE2\n\tAE000000000000004620AAE2A82AE000000000000000000000000000FF8F4B40020000500180190402200180180080380180000aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00006000006000006000000000000000000000000000FFF81B4000000880AA8AB80988D8AB8AB8018838AB80002062A80042\n\tAE2AE2AC4062AE2AA2AE2C70002AE2AE2AE0A82AE2AE0000000000000070182AE2A82AE000000000000000000000000000FF\n\t4CD1000800001000801901843801801801843825800600600410400600600420601600600602600000600600600600600600\n\t0000000000006000006000006000000000000000000000000000FF8C120000001511549558C5901955955801823955800240\n\tE55409455655655411655655655649600C556556556550556556000000000000006000D56550556000000000000000000000008aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00613200600\n\t610600640000800600608400400600600000400600000000000000C040006000006000000000000000000000000000FF05CF\n\t0000000018058018058058018018148018018080006116200006006006006122080006006040006006006206006006000000\n\t000000084088006000116000000000000000000000000000FFD4CB000000020801801821821801801800811801A0C4086006\n\t04A0060060064460020000060560880040060060000040060000000000000041200060000068000000000000000000000000\n\t00FF4EF300000000400080190580380180180184180180040360045040060060041160060020060060000060060064060060004aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF8F620010\n\t00511914D55B3455595595581415595580404D25461065565565465564464565565560405565565563505565560000000000\n\t005482C055000654E006000004000000000000000000FFCF31800000001800801800003801801804001801800000A0160060\n\t06006006004006006006006000006006006004006006000000000000000500006006006006000006000000000000000000FF\n\tF2120000000AA8A98AB8A98A98AB8AB8A18AB8AB80002262260002AE2AE22E2AE00E3202AE2AE7002AE2AE2AE0AE2AE2AE00\n\t00000000002242002AE000226000000000000000000000000000FF66AE00000000180180180180180180180180180180400800caa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0020000006006006000006000000000000000000FF5D6C0000000140812AA0A82A98AB8AB8800AB0AB80022204062262AE2A\n\tE2AC2AE00E3462AE2AE0002AE2AE2AE0AC2AE2AE0000000000002A82102AE006286006000006000000000000000000FF0B56\n\t000000023820801A00001801801920001801810000200E456006006016004116006006006000006006006000006006000000\n\t000000000010000006006006000004000000000000000000FFE3B70000002A18CA8AB8AA0A98AB8AB8A80AB8AB80A02A20A6\n\t3282AE2AE2AE2AE3362162AE2AE3102AE2AE2AE2AC2AE2AE0000000000002A80402AE00632E0060000060000000000000000002aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (206347106104\n\t117106C1761690600082602E8061048070060000000000781F8000006006106006000006000000000000000000FFBCBA0000\n\t2060C401401400009C01A01810001821800100284640A00602600C00602F0070A640600020708700E0050070060000000000\n\t00000000000007406006000006000000000000000000FFAD4B000800034035000004201A0180184200180180C01004860920\n\t060060040061268B600680650C80600680640480600600000000000000008C00600604E006000006000000000000000000FF\n\t4BB0000000100001201400003801801808001C01800201404E8020068060040074060070060060000060060060040068060000aaa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A4C700000000\n\t0401A01C008C2409801800001885802020420E0200860060840062074D6C1600640020111704600404004600000000000000\n\t84904C6516006006010006000000000000000000FF3C2E800000210041801800800041C4180A0038C3800094452600011623\n\t6444D4E40630E016556400910006546104840806000000000200000000010006A86006000006000000000000000000FF5BB4\n\t802000000001805800E04021D4580400110D9300025A96101C0FA0E2252262060860060362010AE0362A6004026006000000\n\t000400400000009806006006000006000000000000000000FF89DE800020402041C01C10A0A301C83800005C0988C010500F006aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000040\n\t28620E006006008006000000000000000000FF6D7800000840184184200082580992580002090D840048440604A156006306\n\t00622E48E04E006000050356006004000006000000000048010100050106206006000006000000000000000000FF86940000\n\t00401807023A00B018018A38000AE009800009C00600A00E50E2060060060460260060980260060060040060060000000000\n\t28000430000006006006000006000000000000000000FF842400408800182140D8328099038098000000018EC00240A61962\n\t663A611600C1FE0061C602602048E32601E00400600600000000000040000000E006206006000006000000000000000000FF00eaa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AA2AA22A0122\n\tAA2AA2AA2AA0082CA2AA2AA2AA2CA2AA00000000000000000048A2AA2AA2AE0002AA000000000000000000FFFCA100000040\n\t1814001805843800000000022000000228800004800000000000400000000000002000600000000400600000000000000000\n\t0000006000000000000006000000000000000000FF5D0980000000002044C600600000000000090000012202000050000000\n\t0080530000000000000200026000000006046000000000000000000228446000000000000006000000000000000000FFC4EB\n\t000100201801C11442C1180380980011080188C00440B60822060360060141060063060264A0280006036004020026000000001aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000711911\n\tD53D55951D55D558003119558100307556007557556557556557556557556250517556556356516556000000000000000428\n\t555557556556000556000000000000000000FF6EDD0000000888CC8A88AAAC8AAAAAA80008CAAA81200222AA8022AB2AA333\n\t0A2AAA2AA2AA2AA25028A2AA2AA2AA28A2AA0000000000000002080AA2AA2AA2AA0002AA000000000000000000FF410E0800\n\t0002202220040000000000000004200000400480000910000000000000000010008000000208008000000210000000000000\n\t00000000004000000000000000000000000000000000FF3CA80000000EE880C808A88888AA8AA8000400AA80005002AA0522009aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000002080208\n\t00800000000000000000000000000000FF75F500000020000000000000220000000000020000004200000A88008000008010\n\t00000000000040020800800200020000000000000000000000400000000800000000000000000000000000FF04178800000A\n\tA88A8008AAE8C8AA8AA800088CAA80200022AA6422AA2AA2AA2AB2AA2ABAAA2AA00028A2AB2AA0AA28BAAA00000000000000\n\t002008A2AA2AB2AA0002AA000000000000000000FF5EC6000800400000404400202201201000201201000000C004C8100500\n\t4000C00804004804804000001005004000001004000000000000000040004004004004000000000000000000000000FF5D95005aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200200202220\n\t200200282008202200A002002002000000200000200000002002802002802002000000000000000000FF9707000000000000\n\t0000000000002000402003040480000250800200000488100200000430400C10000000200000000000000000000000000001\n\t800000000000000000000000000000000000FF6AAD0000000020300000400400000101000120100100088081420420400020\n\t668000400080111000001111000010001800000000000000040400000000000400000000000000000000000000FF428B0000\n\t000000202CC4000200004000000220000100090800000000000000000000800001000410000000000000000000000000000000daa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004608808\n\t08880C00800B00C00800880000200200208210202200A04201A00211200060220200A2030022220080000000088004584020\n\t2208A082802002000000000000000000FF538F0501141105018C583185581180B92D8D595593404A608E5174961164C64A7A\n\t0600620E206208006027016006007004000000400000400800004006006006006006000000000000000000FFE04202800000\n\t404000000310B1012830010000010200011C4406084D0A581C094A60404148000260100004C05804000084000000000020A0\n\t00A0284005004004001800000000000000000000FF046F02810A088500922848932910814D14B50A509020422002D0A10A91003aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200600000\n\t0000000006000000000000000000FF1838000000000000001000000000000000200200000000000000000000000000080000\n\t0000000801007000000000806000800000000000000800006800000000000006000000000000000000FFC59C000000000208\n\t8808202A02008088000088082080002002802A8220302224A00300200200204000228C80A20C002022010000000028240000\n\t084000088286002002000000000000000000FF77D905000000000000001520B0000820000002003200000000220808040814\n\t080400A00010000200800000000000001484800000000000000080000820004001800000000000000000000000FF16CF000000baa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006856406082\n\t026000006924106006046806000000000000100010008004104046000806000000000000000000FFCE38000000000001201A\n\t01801841801A00A11200B0408960170A0436906106C3610400690604601082000C0060060000260000000000080281004881\n\t04004006800002000000000000000000FFF55B00002000A02100182180188180384090383080002240860080064264160860\n\t00156446116540110444006406000006000000000040000040006024004006000002000000000000000000FFC4F200000000\n\t0000000000000000000000000000000000000000000000000000000000000000000200600000000000600000000000000000007aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000182384100\n\t1005801A129010208142826806846016207106006807A460060440020000860062040000020000000004D00400D340021400\n\t6006802402000000000000000000FFA4F400000000A041801801001141805A21D01040824221611609622E4C600752E00E12\n\t604600682802000E0862040200220000000000080C80084860C4006006002002000000000000000000FF0C550040A0000001\n\t001A25855901815841803888B800186616026446846AEE0060B720E20208C28048EE840070061069060004000000201000A0\n\t046044094036004006000000000000000000FF0277000100000001001801801A018018018691008400026C0600000600704600faa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A0600E406006\n\t007006000000000000000000FFE649022000000001800843021043801800001801100002680604680E80600640604E046806\n\t04600008600600600600610E000000000000020828008016806806806426000000000000000000FF3A0F0000000000018C58\n\t008050298119D18218018048006006E074461C604621F02700680618400088640660600480600A00040019805071810040E0\n\t47077007006026000000000000000000FF8A9D000000000001881800809091803805F21041E100106C170000062060860070\n\t06206006006003406106006205106002000000000280000802040406006016006006000000000000000000FF50A7020000000006a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2600600000C0\n\t0204600600600602708600000800020000028B000205006007002006000000000000000000FF810E00002000000180180900\n\t1801801881813040A00008E00600600620628600604604785200448800600E0060060061060000080000000202A810620680\n\t6006006006000000000000000000FF1C6D080020000001801E08011801A0585314100000400CEC1E4BE0E605E866E8620662\n\t602A024A6004600600780604700600000000000000080006000E206807006006000000000000000000FF1ADA080000002021\n\tC20001101483801A02001403001020600612610E8068161264060070060D68030060060070060060060000000004000000020086a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801801803811\n\tC21A81811401801A01600E00E006046006016007106000004280A1600600680600621400000000000800012000600600601E\n\t006006000000000000000000FFC190000000000049801800931B89C05B41521427A06A08FC072070160274072C6806086820\n\t10511002E0160060060060260000000200002600C9D00206087007026026000000000000000000FF4DA1000000000045801C\n\t01101445801844809009080000604604695710641603644602640000400080600604614600700E0000000001400092000079\n\t04406046002006400000000000000000FF5BEF000000002001841801001203801C10C55441C000226006A06006A2611600600046a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040060060040\n\t06000000000000000000FF317100000000000080120180140180180100080180000040060030060060068030050060068060\n\t00006806000007006006000000000800800000006806006006006006000000000000000000FFC75E00000000004080180190\n\t1821801AA1001831C001004806C0214608500600620400602600600422600604004600642600000000000003000000000400\n\t6046004026000000000000000000FF3B21000000000004001801845885C41805021C03883890405284A816004A16D2604004\n\t7206806500006806001106807006000000040950C00251006D06506007046006400000000000000000FFC88800000000001100c6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600604600000\n\t7006A01206006006000000001000000000006007006806002006000000000000000000FFFB64000000000009C01A03821811\n\t8D1301901005800020455724640704434E304D0E05642611612500611650808E80E906080148108000020004000006106006\n\t000806000000000000000000FF3B48000000000001001821801801801011801101894004400601615628C00602C046286016\n\t00621004E026000246026226000000000000000000006006006006002006000000000000000000FF5EF80000000000000010\n\t01801001801800000001800000600600200600600600200400600600600400600600000600600600000000000000000000000026a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0B001081A00A\n\t85801B138000000016C4200601454ED2400A20E2060464A9D0600E0200A4806A8C280000000880000A200000068070070040\n\t06000000000000000000FFC84E000000000001801085001701880801821AC380000088EA02B24E2CC80E2ACBAE6F632E0AE3\n\tA802E0BE0C89AC02E6B4580088088000020440806006086007006006000000000000000000FFDF9A00000000002120101180\n\t1001801905089515E040906016546506C16557540C5400641654644C516806000C2604610600000000010000100400000600\n\t6827000006000000000000000000FF572F000000000209901101801201A218C90DE84180193940061868860060060000020000a6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (693644100600\n\t0000000000000000FF8EA7000000000000001801801801800201801801800400600600400600600600200680680680600000\n\t6004000006006006000000000000000000006006006006002006000000000000000000FFA74F000000000001501045841011\n\t810A41889A419142042426486066045546004804016887286000000006000004001004000040800000000000006006006007\n\t000000000000000000000000FF5D73000000000001C01001C01201800801C018218022080801007C8644400600432602600E\n\t006000810006000404021004000001000000000000000006006026002000000000000000000000FFB94000000000004100120066a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (820000007000\n\t081000006008000000000200000440006407008001110006000000000000000000FF88D00200000400120218018018158888\n\t01A418A1800004600640400660601650200000620620600040880404094620000600000000000000000000E006A068062060\n\t00000000000000000000FFB9EB020000040294889A51885801A0A2418C58258200816A06834406A8620600280680602E4568\n\t08C08424200406A01016000000000400000820908806216406884C00000000000000000000FFC61F00000000042084388324\n\t18B38C0885A1189180004A602E80400600E0C600222EA365060862A0006015080806006146000000000000000090C000061400e6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (106000400228\n\t20080200880C0080100080080080082C200800800880800604A00600900820000000000000000880B80900804144800E0000\n\t0000000000000000FFA5460000000000A0802000A00200800800A14002800061220200B6020030060021400228021DA47830\n\t202000000400200400000000000000000000404200280A004002000000000000000000FFA9D200000000410110C4093B240A\n\t42144110841000001280241700100807A00006010484E00002000070084010004065800000000000000000280160060A0AA0\n\t4A0006000000000000000000FFDF910000000000086000762002801120A402074000000000480009000088018000015008080016a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (912802000000\n\t000000000000FFF3000000000002242012020230010001222B52290122840000C8800500100500480C804894A44840800085\n\t00000C801404000000000000000840A048A8814004804800000000000000000000FF6E1E0000000040018C1805891A21901A\n\t05801901800020E80610601600640E004006006206016440106C06220C0600608600000000000000040001432600680600C0\n\t06000000000000000000FFA437000000040550804C30A0080AE14C2094C828800112324344AD034020825035222C20230C30\n\t11202002000143503202000000000000001021103002002142283202000000000000000000FF00070000000202402C1080000096a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (10D50450D505\n\t40D10C80000000000000800830910C10450550450D50000000000000000000FF754900080000040042045440040040035000\n\t0640000000000104100100100000151000180100100100000100000104100800000000100000100904100000000100100100\n\t0000000000000000FFABEE0008000000881480A408C0AA0AA00000008200041802A80202A82A82A82A82802A822008800028\n\t8B202A8A202880080000000000000000000A82002A02A82202A8000000000000000000FFAC47000000200400AA4A10A00A00\n\tC00808C008008002C128028028028028028028430020028028108420128001028231420000000000008008108028020000020056a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0AA0200AA082\n\t0000AA82A80202A82A82A92A80012A82402A80402C92A8AA92A82883200000000000000000000A82A9AA8AA80402C8000000\n\t000000000000FF293E0008000000000100000100000004920002880140000000400000001001000020000808090020001000\n\t0010080200500000000000000000002200A0100001100000000000000000000000FFDED40000000000AA0920800AA0AA0AA2\n\t022AA08C00C12A82A82882A82A82A82A80402A82882A80102882A82A82A82882200000000000000000202882A82A8AA82882\n\t88000000000000000000FF8C6F0000002003342043303203543540202AC0420000C50D50930D50D50550550C90D50540C40800d6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020000000000\n\t00000000FFDE6000000010590900192580180180189180191580000060260864360A60C644440600E2862060000060160060\n\t4E00600600000000000000E40000420E000400004006000000000000000000FFBA7C0000000002012002A220020020100500\n\t14110144000000908800800804804A0880505480082080000400000480100C000000000800000820804800000000A1480080\n\t0000000000000000FF95D4000000200800824808800800800B08A00840800000200240200200200200214200210200200802\n\t2802002802042082000000000000002008402002000000122022000000000000000000FFE11A0000004000AA0880000AA0AA0036a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620000041000\n\t6000000000000020408200006406408200000006000000000000000000FF1B310000000828C98548A29C080080088002088A\n\t810002214200201210202424202211A00200200004204C00A000002000000000008108082450000002000000414002000000\n\t400000000000FF544E40080040040240040050044040040044040009012810082010816090011012C9021201221008189081\n\t0110A4199004000000001040021001005009411001000000000000000000000000FF7ED8400100410C04C04C00C00C04C04C\n\t00C00C0094012D351245308300B413013113543053043108013503003502003002000000011010523001003003001001002000b6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2888381B8540\n\t00620A00624602601600214E00628E00609018000400200601018600810000000000610006013E4400484060200000000000\n\t00000000FFA3B30000000018A18258048C102100985304182180000C612208600600E04204A2160060260060200004040020\n\t06000046010000000020006400016006010010016024000000000000000000FFB57A00080400000400002A0000A00B010202\n\t00C012401200005500202164502102A000002000002800648000000014E04000010000004000008000E3064500C00A000600\n\t0000000000000000FF6B3E00008000800000300100104200400800000003000104A01482500C65100D0004280148000100000076a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF7265200000001080C09811401001889803809801800408E08600600004600400C00600600600680000001600410400\n\t0084000000000000006880046007001000254044000000000000000000FFC3630000000018458258C080B8018258300A5801\n\t800044644E00600609600410254E00600600450004608400200E046016000000000000006200006006000000106006000000\n\t000000000000FFF05B000000001805801800801901841881103903880000640A23620E54620440200609628E0061000260C4\n\t0020060A60060000000000800060500004460000800C6002000000200000000000FF8D81000804001881811850801807101800f6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002556557556\n\t000000000000004200510556550550500512000000000000000000FF882E0000000018208A30910818AB8018C01318AB8000\n\t20600E3262A822F2AE2240262AE2AE2AC2802AEAAE0052AC2AE22C0000000000000061014AE2AE2A82A92C42AE0000000000\n\t00000000FF65094000000010208010010010018018C9043801800000628602E0000078060158460060060060000260060058\n\t0400680400000000000000615184000600000004C022000000000000000000FFFB42000000001808881A470F18AB94588180\n\t18AB80001565022AE2A83062AC2244062AE2AE2AC000288A260042242883240000000000000060002882AE2A82A801428800000ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180001060\n\t861260040060060044060060060041000068060000060460060000000000000040200460060000008D004600000000000000\n\t0000FF1E140000000018894ABCAA4AB8AB8A98040038AB8000A2E0062002AC2AEAAE3440162AE2AE2AD6042AE2AE000AAE28\n\tE2AE0000000000000052808882AF2A92A820028A000000000000000000FF94E3000800001314008800003001809812005801\n\t800100604601400600600409010E006006006800006006002006007006000000000000004400006006800800000006000000\n\t000000000000FFB3DF000000001112154954155155955800111955800054E036484556556554400306556556556104516D56008ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF793A00000008104100200010904080180200180180000040844000CC00402600628600600600448404610602A116046086\n\t000000000000004000420006000000012042000000000000000000FF06A70000000318008500240250148018290018018002\n\t08C03608600600600C08202E00600634C00200600E10000600600E00000000000000C1000060060000000820060000000000\n\t00000000FF01F4000000001422800000001000803841021801800200444E0120060040041520D60060060048040060060000\n\t06006806000000000000004010200007001000002002000000000000000000FF6BD200000000180100180000180180188A09004ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AE28E2AE0000\n\t000000062A804808E2AE0060002AE28C006000000000000000FF11D200100005190293011190991195584D95515580004CA4\n\t9030E4545564CC4460065505565544065564D640655655644E00000000000654820A55055000600644E55000400000000000\n\t0000FF4A65800000001810814041801805801803801801800000201022600400610005600400000600400000600601600604\n\t6006000000000006000100206006006006006004006000000000000000FF257000000000388B0800880010808AB8800AB8AB\n\t800022420406E3042AE28622E0042AE2AE00400028E22620222628E2260000000000002A426808E2AE00000022228E00000000cea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000431013\n\t300400701602400600200600400400600680600604600600000000000600000004000000680400C004006000000000000000\n\tFFE5230000000AB8E88CA0888AB8898AB0618AB8AB00002AC04010222C2AE64630C2AE2AA2AE2AC0002EE2AE22E2AE28E2AE\n\t0000000000062A84000CE2AE0060042A42CC006000000000000000FF0E2F0000001038308020230238430018818000018000\n\t00202000600400600408A2D60000060040840060060AE0060060860000000000060001000000000060000860000040000000\n\t00000000FF8C5C0000000AB88288008D0AB8A90AB8898AA8AB80022AA4800163342AE00C2022AE2A82AE2AC28028E2AE2A62002ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF5C\n\t13800000121922C01009869C01C038098218219602312A9042D084D3F6068042B69D64966440400860470060040060040000\n\t10000006440000006006007006004004006000000000000000FFA7BB000000001803A20408001C0061140980544101044250\n\tA002E0AC02702420000720702710E20400600600600600E20E00000000000E10000000000000701400400400600000000000\n\t0000FF314200080000180184004000182200109580000100100048402061068060C308000680600600628000600610600600\n\t6006000000000006000550406006006004004044006000000000000000FFFFA0000000001804800002801A0180100180180100aea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (641E00000000\n\t001E440000086006006006004004006000000000000000FF14F8000000001800801001101C01203C05801C25808030B00001\n\t652C12A14C0240063321460860025400860060040001440200000000060005020060062060A6014084006000000000000000\n\tFF71F880000008588084120110180181188380380190C011205050525440310608C016A028068C4048000046006484010004\n\t000050000046080000080000006816004004006000000000000000FF8665800000045E488030039138018059058218818022\n\t00220008520600609212C4C60061060060101060060065040060040000200000260000000800018060060040040060000000006ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002108036404\n\t0C210004240608E0860060803000040160060000560000000000160000500060064060A6114004006000000000000000FF4D\n\t5F0000000018008048008818C000582580185188402924000060060022160820B602602610600002010C0062260000060000\n\t0000048600000008014000E006004004006000000000000000FF0C140000000018018228018018808010019C188D88000422\n\t000061560162460822A64060160064000060040060261061060400000002860005280000A000E0060E410400600000000000\n\t0000FFDAF100000000181080480D8258208810A1829901802006208802600410605644200E05645E01468000600C00E2060800eea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF2B6D00\n\t00000AA8AACCC8D4CAA9408808AA81808C00002240000021022AA30033A1922202AA18200028A2202AA2382CA32000000000\n\t02AA00051008848A2AE2143222AA2AA000000000000000FF5051000000000001003809801845002000000004000000800034\n\t0408006000080044008000008000046000000100006090000000000000000200026046000080080004006000000000000000\n\tFF2A2380000000000004022400008802800014402000001000000080A0006150000408100000240500006088000000026000\n\t000000000000000150206206000030008006006000000000000000FF217A000000001801A20C08C418001018818118818080001ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000004\n\t000000004000004084000000000000000000000000FF1404000000555921D55911955D01955955A45B55800254600050E556\n\t53600E40DD56436556556200556557556556516556000000001556000500134517556436556356556000000000000000FF26\n\tF70000000AA8AA888880AAA8088A88AA9208C880023220002122022AA02A2224232AA2AA22228028A22A2AA2A228A22A0000\n\t000002AA0000202AA0AA2AA22022A2AA2AA000000000000000FF77AF10000000000C20042400001040000008800000000000\n\t000400000002A40A000010080000008000000400000404000400000000000000002040402000010000000000000000000000009ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200000000\n\t300010000C8000000280020001000000020000000000001000000500040040000080000000000000000000000000FFDC2208\n\t000000002A004022000204000000004000000000800011000004048008000000100000000000000000000000000000000000\n\t0000000000000400800050000200000000000000000000FF01038000000AAC00888C80EAA8EC8AACAA8808AA800023200020\n\t22AA28A00222A2AA2032AA2AA00028A2AA2AA2AA28A2AA0000000002AA00003828A08A2AA2022AA0AA2AA000000000000000\n\tFF2079000800001000400200200004404001405401000000C0000A0050000204005001004804010000040104004004000004005ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF4438010040\n\t084000830800C0090080080CC10A0080020C300204301280A8A280280200210A01200028A08A002082022002000000000022\n\t08200000A002002003003002002000000000000000FF74C30000000000000000002000000001400400500000400CA00008A0\n\t100800020928488020040400800000800000000000000000100000001000000000000000000800000000000000000000FF4B\n\tC80000000000000000000000400003100961100000100008000100320248000400000800100002000000000800000C000000\n\t00000000440512800000000800000001000000000000000000FF57EB0000002003002204100000000002000280000000100000dea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00008001800004004000000000000000000000FF3D6300000000040080082080080A80080080082084000624020022020020\n\t0209200200200A02202004230326294300A00200000000010208255080A062052803202002002000000000000000FFB52701\n\t0040104001851801801881801C554CB84980001468C604602E4D654400608C28F10605600208E08E00400600780400000008\n\t0006006802004006006005004006006000000000000000FF902E0A00800000A9000000021001028101020401020240863C02\n\t410500009504C0E4004054204400C200848841A40400AC0000280002E810502001400002C004004004000000000000000000003ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000600000\n\t0000000000000000006000000000006000000000000000000000006006000000000000006000000000000000FF705E000000\n\t0002000010010000000010014000000001004000000000806000000000000000000000006000000000806800000000000000\n\t001000006006000000800000806000000000000000FF89160000000000008008008008282008888088A8A000002000000A80\n\t0028220822020020020A402200220040000401220200005000022A2A2002004002000000202004002000000000000000FFE6\n\t800C01000000D000004002000524800122400020008890480408048808800001400000104000000018051040000000CC000000bea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (510000000082\n\t01A00043841813801801901819808088680E80C00400E0220060031060460040008060049020060060060000000010040060\n\t00800000004006602444004000000000000000FFCC87000000048001841803C018C3815801C51C0591400264560148060C88\n\t4200609201600640C290108114000407088006000000000006206090100140045006006004000000000000000000FF4B9900\n\t0000000001800009803801801909803881840011600600404400030255642220600E00404000044400004600000600000000\n\t0004006400026006004016002004004000000000000000FF4818000000000000000000000000000000000000000000000000007ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040610612000\n\t0000046004454006802000000000000000FF7DF4000000000023821811811805001821C01003800000600E80C04648100000\n\t612680600600601000000780228400000A008000020826037040200000224005454006006000000000000000FFFB06000000\n\t04000184181184582101391181340582410464260048260800002060C65060162162880084CE100A44090002000000000007\n\t20608810612600580C004C46002000000000000000FFCC29000000000001A05821B01989801801BA1891980000E906004006\n\t036A920EE21A00E026004020986004512006806146000400010415106300826406024007802014000000000000000000FF4000fea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (306CC4026212\n\t006006006204006006810806046006000000010006206904006006006880004804006000000000000000FFCDA90000000006\n\t45800001801803001801003009810000400400400000600400604A0260060060040060065101068060260000000008440460\n\t10800000006000000004802000000000000000FF6570000000000001845811967819019801B03181808002E8160042869060\n\t1404680602600618602080600600040480701200000019101661600946641E586184804016006000000000000000FFF76E00\n\t0000000001E00001E09901001840801003880005308780C347216004007086007806006029106006002004007102008200040001a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000002980\n\t1809801801000201001011C22050420620604E28644280600228E2870A732C0AE20608500602700600000100920F2862A022\n\t00080070028A2C44002000000000000000FF819D000000000011800011801A038018000010498400044004204A3004780400\n\t60C64060860260A000F21608600680608600000080080E006201A2600E004000000446006000000000000000FF9E3F000010\n\t0000418201E1801A61C818F0007081800141458412C00002600418608E11640610601414600E864007007006000000000406\n\t106840000000004000140006002000000000000000FF699900000000040184200180180110190102110180300840040558020081a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (807804016306\n\t456046007814006000000000000000FF2DA9000000000001800003801801800248001015D01000024600620460608708608D\n\t08600600E80003600610450600680400000000020E0E640510E006007003842802006000000000000000FF8C540000100000\n\t89884021809805800230041069808005800610E40488610604E44600680620620E00E0070958060061060000000000070060\n\t8A000800007122002006002000000000000000FF193D000000012045841801841953034001041005D0004441360068060560\n\t5300600200780702600400701642628680611600001052004620F40228630645600A026014006000000000000000FF5B59000041a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020060060060\n\t06006004006006004006006006000000006006006004000000006006002004000000000000000000FFFA9B00000000000100\n\t1801801800000400001801800000600600600200680300600600600680600400600700400600600600080000600680600100\n\t6006007007002004006000000000000000FF48A20000002022058400018418432140080018018100C4600E00600484E00E00\n\t600600700622600C026016420006806006000000506206516110200800006016006004000000000000000000FFE253000000\n\t210351880025811909820000041821C01001650600FC0410692610E10F08600681620400600680500400708E00081002605600c1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080001802001\n\t801828101A204A180780904960060C702E0060044060060060D690600400600666600680600600000000680E00680480605E\n\t006006803002006000000000000000FFC0E8000000080003A0C201A21801021882149831CC810C620708213428600414E40E\n\t11640600680491605700F4464C6086508340006107006000000800005006002002000000000000000000FFAA550000000000\n\t8180000380182980184800180180200060D621620403649400614620608642E02400610600600600600600000000600E0060\n\t00006006004006002002006000000000000000FF4354000000000001001801801800800000001801800000600600200200600021a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000010040\n\t17002006006000000000000000FF599F000000000001000011801800011808041811842080E03602E0821268140060060864\n\t4E0064880062160072AA00654C0000008060060062A8000080006006804002000000000000000000FFA8F4000000000001A0\n\t1801801A00081C02001C01CA0062E2AE22E292AAE28C26E2AE28603E2BE53000EDAE80E3732A60840882A000600700755000\n\t6006007816004002006000000000000000FFAA3C000000000001A00211A01800811810249D359440016556032D4455751400\n\tE5560D6546906804226016006C06007D56000401006006006004800080006006002802000000000000000000FFF85F00000000a1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (628600600600\n\t420380604582E05600600600000000740620E002401080004C2E516144046000000000000000FFD1D3000000000001801801\n\t801801801800201001C002006006002002006002006806006006004002006004006006006006000000807806806002006007\n\t004007006804000000000000000000FFC83C0000000001050118058418008419102198538042206806006802A08800107006\n\t81640700E000101006007002001004400001006107006000006046004006003006000000000000000000FF74640000000000\n\t01A01801801800E01800001921D00100748600743200148184E2CF05610708780144008600600200100400040000600600600061a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020460400102\n\t8A00000205020000000082000000000060604080008602800001000070000000080060480000000000000000000160A60292\n\t00010220006000000000000000FFF76C000000000001800001A41825079840001015800240649641624000008230685E0060\n\t0600440020080444600660000600000000600E206130006216004806942100006000000000000000FF3B4E040000000201A1\n\t5A8190D81121188022B105800340F086842A02A010C301604E426A8F234910C00004807006A0101600000090680E8868288D\n\t0C48A54006003400800000000000000000FF92FF000000000003800001801AA3821812001001800094640721610800640A3200e1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (301300280380\n\t3483042000000000000000FF692D0000000004042003002084002005042000000000AC100104880C810C19021080201000F4\n\tC800800040820D44800800000000000900808C00A20808800028208880800000000000000000FFE231000000000100800800\n\t800D01800808022C80800002200200219000210200302280300203020000200401A00200200400000000200200200008C502\n\t200006004004002000000000000000FFA63D0000000000000198819820400018900084420000010000224400706200080200\n\t800008000088007420100020006500000000080200080008146006441000880400066000000000000000FF41B602000000000011a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002002802A00\n\t802002203002803552000000002C82802C00802802012112883102802000000000000000FFCAE900000000000030A2000010\n\t112020002242010000814014008A4C80100480422C00480510C80280010C01110482100400000000483480482AA44C009240\n\t04015034800000000000000000FF22E9000000000001845841A1180100190000180180000060160162A42960440068060060\n\t0600640000680682648400600600000000608600600012C5062260060AE004006000000000000000FF4AE4000000000704C1\n\t0D00D20B44C28A2C428854800144BA03A4301300350B2820528220034D310100242350B023403342000001003003003309000091a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (435435433233\n\t01541501540000D40CD14D0D50D50C48551410550550D50A00D10550CA0D40D10A88000000000848D50C00930D10510540D4\n\t0D00D50000000000000000FF3DD7000800000400400400400000440644000400000100000080110104102100000080000100\n\t1401000001041001000010000000001001001049001001000000001401400000000000000000FF5A4C0008000000AA0200AA\n\t0AA0A20A80A80880AA00002A02A02A00002882A02A88802A8AA82200002A8A208A02282880000000000000002A80000880A8\n\t200A202202002A8000000000000000FFD23D000000000200A00C00A00A00A00802200A00800880280200288084300A8020020051a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000100C2442\n\t002000000000000000FF22F70000000000AA0200AA0AA6AA0A80024AA0AA00005402A9AA82202882002A8200AA82A82A8000\n\t2892A82002A82883200000000002A82A81800886C82A82B11180002A8000000000000000FF28C60008000000000400000000\n\t0000440020240000000080000000000000810001208008000000000210000080100400400000000003000000482000200408\n\t08008028000000000000000000FFE5FB0000000000AA0CA0AA0AA0AA08C0900AA0AA00000082A82A82282882882A92C8AA8A\n\tA82A80002A82A82882A82A82200000000002A82A80002C80882A82A02400C80A8000000000000000FF0E550000000003543100d1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (530030002030\n\t03003442003002000401441013043041002203001013003002002000000000000000FFCC4F00000004000184180180180580\n\t18010019098C4220600614E40600610420600630620600E1000064160440040060060000000000A620640000402600054600\n\t4046006000000000000000FF9DB800000000040030A20120000020222100120100008200000048008410D500409400400500\n\t080080000488C804800084000000000800804828804820800004A05114800000000000000000FFD4EC000000000000800800\n\t800800800910A00800800028A00200211200200200282200280200220004280202200204200A0000000000020020004420020031a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80300B001800\n\t02805401002000002300002960004800880000404080280062080200000060000000000401000002000060060002A8000400\n\t006000000000000000FF4335000000000000920800000800820831800880800000200A0C0082422182002202082082002090\n\t002400006622002444000200300022032040000002540002006004002010000000000000FF1AA74008000004000004004204\n\t000404005804040A210E92A10012284410291290012292094010502190056010040010000000010010092010210042210010\n\t05001420000000000000000000FF2FED400000000400800C00C42C10800C40C48C4080811134B340315210B04B03348B04B100b1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (460844860060\n\t08000000000000FF43B20008000000019080298A58318D590182584B934000422E01603614020A00628600E0060062200000\n\t1C0064060084061000000000060060006686601480A6060006004000000000000000FF0FC200000000000180800190184180\n\t180984180380000864C610610600450A10E4060B60AE00E04000004400600610000600000000000C10601001600600000641\n\t0006002000000000000000FF8EFC0008000000080000000041100540A011402011401001000905081260001100000C054800\n\t800020E0C0000020086080100000000010100012086006000200510300006000000000000000FFF0850000000200000018010071a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (40022882A622\n\t60022883240000002A82AE2AE620888288220AAE2142360AA000000000000000FF9134200000000023000001800811001801\n\t801801800000600400710400400800600600600608680000000608E502040004000000000006006800046046100006944086\n\t004000000000000000FF19E200000000000990A0018010C1803800841801800000600400624E02610200600600600600C000\n\t02600C00604E00608E00000000000400600020600600800600C016400000000000000000FF48AD0000000000098000298211\n\t01881840891811820200600C04624620200200608600620600641040E48400404601614600000008000400E040080000410500f1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (03931C019559\n\t5580005525564044365325145565565565565560045165560AAD465175560000005505545560009305105505574344441500\n\t00000000000000FFA8450000000001018CA0AB8AA28888D8018A98AB80002AE2AE2AE0342AE2A42AE2AE2AE2AE22C0002CF2\n\t2F2AE92A28E22C0000002A82AE2AE0008AE4AE2C82AE2242262AE000000000000000FF7FD140000000000104000180002080\n\t5A018018018000006006136084002044006006006006006000007807A028120268040000000000060060A040004000000600\n\t408E400000000000000000FF21E70000000000958200AB8AAA430A980188B8AB80002AE2AC2AE4042882202AE2AE2AE2AEA20009a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (685400000000\n\t0000000000FF5DE5000000000001801001801209801800801801800200200614483400600400600600600680400000600600\n\t2016026006000000000006006000806406000806084104406000000000000000FF92300000000000AB8210AB8AB0938A9A00\n\t8AB8AB80002AA2AE00520428A2042AE2AE2AE2AF2AD0002EEAAEA82A2628EAAE0000002A82AE2AF0000A80A82A92AE324204\n\t0A8000000000000000FFD99E000800000021801001801805841C018058018012002006005086006014006006006006886800\n\t006106002406047006000000000006006040206006000807105084006000000000000000FFC95D000000000155915155955D0089a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (28E226002014\n\t2EE2A60000000000162AE00008E08E0002AE2262A40AE000000000000000FF37240000000000A38010018308159410000018\n\t01800020A08E10600404200E00600600600600C5040061161421460060160000000004860062400200400000060160040000\n\t00000000000000FFA04600000000000900100180590100204500180180000860460160960060820060060060063440000460\n\t06212216006006000000000056006110206206000006086014206000000000000000FF435E00000000000110B00180184180\n\t200100180180000060062160860220AA00600600600600500000600602A1060060060000000000060060A0200000000006810049a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (90A88AB8AA80\n\t002042A82AE2AE2AC28A2AE2AE2AE2AE2AE28028E2AE0C822628E2A80000000002AE2AE4402AE0AE0062A82422AC2AC00000\n\t0000000000FFB273001000000001B55355910815509930954155000001440855642855044E5565565565564C650451654600\n\t44065164500000000000465560D0550530006550554556350000000000000000FFA675800000000001801001800881001800\n\t80180180100D4000006000004026006006006006006000026006000106046000000000000006006100006406006000096006\n\t004000000000000000FFF5940000000000418AB0AB8C09208098880AB8AB801006220622622428E2262AE2AE2AE2AE00406000c9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (404000000000\n\t000000FFA1DB000000000001A0040184501584184B80000100000D6000006000004034006007007006006500006006406086\n\t0060000000000000060062084000000040000C4006004000000000000000FF3CC50000000000ABCAA0AB8910218C58858AB8\n\tAB80002062A82AE2A828C2042AE2AE2AE2AE2AE01828E2AE40623E2AE2A80000000002AE2AE03008E08E0042A820E2AE0AC0\n\t00000000000000FF8D2600000000010B801001802841023002801801800028412000608600010200600600600600E0000260\n\t0E2A8146006080000000000306006400000000006000000004000000000000000000FFF0940000000000AB8AD2AB8A284B280029a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060460062\n\t00000000001007046000000000007800004406004000000000000000FF7A8680000000040BA09C01A40004C0DC01843A2991\n\t0102400055E0024041A503600700740600600011600600640600600000018000051E99600040600600600000600600400000\n\t0000000000FF532A00000000000D800401C01001E01A8188045300008A710100650403440CA060260260A620608440608640\n\t4006096000000001000006204400020400006000200044004000000000000000FFB756000800000401800001A09101813801\n\t80040100100060000060060440840060060060060060020260060D400600600000000000000680610602624600600000200400a9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (083807800010\n\t228010641E00C29260604604614E40C00000608400600600600800000000008645400000600E024000082044004000000000\n\t000000FFF071000000000001A31C01C00082801881821C00944040F041006022004028046C0E24E086026100200446206206\n\t000240200000C0080600E43050E406204430028086004010000000000000FFB0C4800000000001801881820000A038018A18\n\t0088A000E08042614252C200016116916C061560805102864062261104000000000004870064002204000040004024060040\n\t00000000000000FFD5D2800000000041C11901800000811801805800802180C00000604A08402584708F08F0060CE00000640069a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF860D000000000001C01D01C02011A31801083843904001200000604C2241224060060460160140100084440060040000\n\t4000000020010600440020621620412042E004004008000000000000FFE1D300000000000192D801140123C8180900180184\n\t8020654800620608400202651620E0A60442C040010400600600020001000000000601600011002008C40010400400400000\n\t0000000000FFF354000000000001803801820001C8190F05982180800020080062042B441200608600602600422800E00440\n\t64060060104080000000060040500000200CC090200104604000000000000000FFF500000000000041A81A8188202D82990100e9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000800200224000000000014000000000000000000000FFABF50000000000AAAA8A8088C8880CC888870150800020\n\t20002AA4042AA2A22AA2AA2AA2AA2203002EA2342021822CA0000000000002AA54200008808A2000006002142AA000000000\n\t000000FFBA0900000000000000585182184244180010812800001000000001080040080000000000000000800061100C8240\n\t006000000000000000480000026046090000110140004000000000000000FF970B8000000000004004022040000020420040\n\t02000004800000024000600000000000000008802000600000000802600000000000000002822840620602000002001000600019a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000000000\n\t0040840001150050050050040042000001040000200000000000000000050000000040001050001040440000000000000000\n\t00FFC036000000000155911D55F15911F5593184593180005060005564CE156515557556D565565560105365560165565560\n\t000000000015565560201143565568004C4556356000000000000000FFA2530000000000AA8AC9108888CA8808AA900A0080\n\t0032A0002AA02A2AA2222AA2AA2AA2AA2AA02028A2222AA21228A0000000000002AA00A2302AA2CA2320000323022AA00000\n\t0000000000FF8F3F0000000000002444000202010000022900020000000000000000200020801000000800004080000000320099a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tA16410000000000022040000004400000404010000003280008000300000C900000080000000000000000004000000000000\n\t0000001000000408000000000000020000000000000000000000FFDDB800000000000000400020400020002010400A000000\n\t0000000000200000000800000000000090040000310000040000000000000000000000040240000000110000200000000000\n\t000000FF2A429000000006AAC888AA8A88CC8AA88880882080000520012AA2820AA2022AA2AB2ABAAA2AA60028A2AA0022AA\n\t28A0000000000002AA2AA03028A08A2AA0002022AA0AA000000000000000FFB25A00080000000120044242020141000040320059a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00029C000610\n\t0600A40C4A08104000000000000004000000000000000000FFEF9D0A0002000000800800900810C028AC8008400500082202\n\t0222420021220420AB202082122100AA200A00280200300B00020802300202208808A0020060060060020000000000000000\n\t00FFC6A800000000000000000000000008000002801000010200000000008280000000000080402000020080000000000008\n\t00800001800000000800000000000000000000000000000000000000FF8C6700000000401000000000820012431008201000\n\t010000E0800000AC08080008000000001000000019010800004000000100001004008400400000000000008004000000000000d9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200402000082\n\t00000100000000420000000040001000000020840555000000900000004200020000020000804200800000000000000000FF\n\t23E3000000004010800800800800A04800802800000020305B00208A00A41208300300A00A20202001234A1834020220236F\n\t00000421020420C0022002022002002002000000000000000000FFD2B1140004000001801801909C09825D5582585004800A\n\t602700604611610604614600E024506100016004087006006006000000007007006088014806006005004004000000000000\n\t000000FF52BC02A022000003001000000001109001110000602102070404C6244412D80050156241040440015490358002240039a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF8F67\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000006000000000006000000000\n\t000000000000006006000000000000000000000000000000FF52B70000000000000000010010000000000000000002804800\n\t0000000000000008008000000000000060008008010060000000008000000000000068060000008000008000000000000000\n\t00FFBA6B00000000000000080080080089088080280800002020048060CE03200208200200A00E28400000220E0020044020\n\t00080400002242082090004002000000000004000000000000000000FF9B6D02A0220000040000000000000000080000000000b9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (064100100045\n\t86806010126006004000102006000000000000000000FFF5F4000000000001041800805A41A01A09C0108000008061050061\n\t060122060060860160020040000A606002C606006006000100004006006000000000004020000006000000000000000000FF\n\t9D09000000000201481801C8180180185380030021404160240064070030C601652620608202C020B2108000D00600000600\n\t000080610F2A6B2800800000404008C016000000000000000000FFC22300000000000100180180180180190190A002000010\n\t64044160061002060060060464120044000000000440060000060000000040060060000460060040000060060000000000000079a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00400602600\n\t61060878060061050060001060070C0034006024200000037006006480050008017017084004000000000000000000FFBA90\n\t000000000243A01804021A01811801A8080000020060058064460048260AE2060AF4060060208814C600A22C200525000000\n\t9360060264C00080502140B6002004000000000000000000FFFD9F00000000000180180000182180194589480001234162C4\n\t4074861160C600E24641610602E0404000860020040008040000800060162A734880E00600400608880C0000000000000000\n\t00FFE6980000000400010A1800A97811845801801202200009401410F006842016006006026308004200016801904106017000f9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF8ED30000\n\t00000001843801800801C01C2182000000020844061260160024140060260068840060000068460234060478060000000060\n\t06206100826006006004402800000000000000000000FF5AE7000000000041801801822801E019018022C0000328400C0878\n\t06002005806006096206006006026047012406826416000000004006507800000120006144000000000000000000000000FF\n\t7F1D0000000000058198180118E78458A182BCA000022860050064061C60D6656466646004806040036506020104C3610D01\n\t0010106D062DE050126086406806806004000000000000000000FF51340000000400018018020018898098419298006003000005a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (044000600642\n\t620800E90624E084202002000000000000000000FFB212200000000001801810001801801801C25000008001420504710680\n\t240C04E04600602500704802604E4464460260070012012060062A6881200020006024020002000000000000000000FF9DBA\n\t000000000021801801C00641803805A00800014200480E80690680600401630604602408610804600E402046007006800A00\n\t20600602E420006026004056026000000000000000000000FF8C8A100000580025831816C00011801A1181C8762022614804\n\t08606E6040440460861A608601E0C000680600300700600600000000680690621042040000480E18500000000000000000000085a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00600E80E40E\n\t926914144140806010096D060000840068548A6C46896106A16911016457006086206000000000000000000000FFD5FC0000\n\t00008001801809880181801801821808208140400701700E00410602600E0060240464008860462166B640642E0100006C66\n\t06006840006007457807116002000000000000000000FF462F10000802000583588280085B805C5780181000021048B62060\n\t8600604E00E48602608412600400628600600E00E28600000102F0A701E0F1801E2800600648C002000000000000000000FF\n\t0792400000000005889841451821E018C18817400003B0400400E20600A28408600789600500721081704600E006247006150045a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (63DB00000000\n\t0000001801801800801801801801800000200400400000600400600600400000600000600600200400600600600600600600\n\t6000000000006006006000000000000000000000FFF059000000000000001801A01800801801801801800000100400500080\n\t6004806006004000006000007006002004806006806806806006806000007006007007007000000000000000000000FFC837\n\t000008248000001849809801801805841801800080200440628600600601680601400100600400600620084404F086006006\n\t006026046A00000100006006006000000000000000000000FF3FFD0000000000041319038C184D8018C188195180801000C500c5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (204804005000\n\t000000006C06006000000000000000000000FFA9DE000000000002021801819800B800118C3881800000420E200080086004\n\t046426006020006100806006004614806407004006106006016260006806007006006000000000000000000000FF55D10200\n\t00000209001809D4390181008591390D9080A8649643214281621428E0C60B6000417000007246D360040860860840B60370\n\t06906000008080006007006000000000000000000000FF7DD7000000002023029801801801800041801821844004E0461022\n\t104A60C400600E2062A014604802E08E00608444E00E00C0060064A6006400006006006006006000000000000000000000FF0025a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0600E087287A\n\t96106310004050801006006005001002002407007806027001001001006206006040000000000000000000FF95A300000000\n\t0200801801A018018058C3901805840050200690B13700644E00602600E02028428100648E81600E0060A280200620600600\n\t60AA000880006006006000000000000000000000FFDE8A000000000000801801821801C01901801825882122A8A60A322E20\n\tE2AF6AE68E2AE0801AD5F802E3BE2A68862AE28A08A0AF0AE2870C715000E186006007806040000000000000000000FFB5F0\n\t000000000000001801801800804045901811F440536457111550016335086156116550406004806C2601400C0070C600440700a5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000009\n\t0C5801821883803811823801800040E8A652C00344EAAE04602E08621040608000E844444807007006006006124004094288\n\t1108402060D6906500000000000000000000FF6B050000000000010018018018018018018018018001006006004000006806\n\t006007806001806000006004804004007006006806004004005000006007006006006000000000000000000000FF93940400\n\t0000405181181190590001015585181585001020070110070460068060060064004040000000268160168000020030068060\n\t46016001006006006006006000000000000000000000FF85EB000000000001801801801800000001801809F02102A43700020065a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (510002020162\n\tA6001080080010000000000000000000FFF97F00000001004A48000000A08204A00000040000030201280000008100200001\n\t110800408000000070004106800064400800000000203801D228610E210028050280000000000000000000FFB2E700000000\n\t0091101841A91841800283801801800080600640E2BE02600650622682630000600010080400600600000600600600420400\n\tC40800600600E006006000000000000000000000FF596B0000000002A5209AA988DA48AD0085D01A038000142A16806AB400\n\t680708EB0644604010E800B00004806D06A09027086886A06C26A06820A40A9084E806A06000000000000000000000FF359000e5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B20B4830C200\n\t294088300141240220304301344348300300300308331302329344B543002810000000000000000000FF0A39000000000500\n\t20832C2200002A404030004000088D0801231104800C00800048000009304800E90004A61040A00800004000A00800000800\n\t868810800551201000000000000000000000FF8B3A000000040020800880C00808800A108408008008200002004002C0620A\n\t0C200200002100800200A00100400201A006002002002002002020004402462002002000000000000000000000FFC6F00000\n\t0000000107200194442410040C0A200200025086801804043480900290812008000904800074200001100060205100800A000015a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00200202800A\n\t00A00A00800A00A22A008002C0AC02802802B1282A802802002C50802800802002842902803083002002C028028028128028\n\t430C304AA42100000000000000000000FF63F100000000024040122822B20040020121100100028A49100040048048010048\n\t0000410009484082011490C80880100C004004930800000800A24A00808880808010000000000000000000FFE7A500000000\n\t000181180190B801801801801801800A22620640429408600604601680600001620010680603648E00600400C00600604E80\n\t6040014006006016056000000000000000000000FF94450000000284A8940CC4840C24CA4854D40840800A08B083893802440095a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80282A80882A\n\t82A03402A8000000000000000000FFDEC30000000003503543002241541543541000000000B10D30550D50900C10550D5055\n\t0B48D50840D50540D40D50D10CD0800000900D50D50830930950C48D08C00550000000000000000000FFF90C000000000000\n\t6004000400000000004000000009001000000001049000001000000000001001000100000001001001000001001001001001\n\t001401001011000000000000000000000000FFD1570000000000880AA0820800AA2AA0AA080000000A0000202A82A8020380\n\t2A82A8AA8000220000288A202002202A82200000000102A82A8020088088200200080220000000000000000000FF19AB00000055a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002002002002\n\t00200000281209200200200200200000200200200000200200600E042000000000000000000000FF20F70000000000AA0AA0\n\t024804AA4AA0AA0C400000082A82A8AA8AA82002A92A82A82A93A12A80002E92B03212A82A82A80000002A82A82A80000880\n\tC82AA2222122A0000000000000000000FFE90200000040000200002C08840040000043240000080200010000002480210000\n\t01000000000000001008010000020000000000420000000000200400080040148000000000000000000000FFDA4700000000\n\t02AA0AA0CC08A0AA0AA2AA08800000002A82A92A92A82802A82A82A92A82282A80102882212282A82C82A80000002A82A82A00d5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4C04C00802C0\n\t0C20C04D02C02C08810100310300344B00220B08B0230034C30528000030030430020030134030010C311345280140240200\n\t2002003000000000000000000000FF2F720000000018898018098C18018C180180180194400160065441042AC02604428622\n\t600E20622043635610602602E00602421020620600420000400E404114006000000000000000000000FF4A83000000001000\n\t201330022201201000431001000000080000400488C800804800804808800808800004800800801005004000804804804828\n\tC44C21001100888010000000000000000000FF7BD5000000000A00800800A10800800A0080280080008020020020020420020035a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A6246450220\n\t2A8028008000000000000000FFEA0704000004402300000380000408010000000000A00000040200000504C0004508420016\n\t00E4402462A8080020046008040408430020100400006016200088000000000000000000000000FF91FA0000000000888009\n\t08880800862002802820984000A0020062862C610A02204210230200200000A41070A00200240020200000208A2264100142\n\t13001101002000000000000000000000FF4D3E00000040044040000042042440040040044802017810F92810290001010890\n\t310010A1220000001005431000189005005001091241108019200000000000001000000000000000000000FFD1C00200004400b5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (06346286106A\n\t4000600C016006106406406000006206002C000C04090072B70AE140010000000000000000FFBA8100000000108080194198\n\tB97990200002D813848029002605800A01620620020600603E4D72802000045060060000060060000060AE0030A001004044\n\t600E006080000000000000000000FF40F400000008108180180382500182802C00184580002C000600400402248E04044E00\n\t604600710848840400600600004600600000615608315000600600E006406010000000000000000000FF9A80000000080000\n\t00802404010210805400405004000482800C02A04080300200084204064360280960000080000860202000000004001000000075a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8AB8AA8AB0B1\n\t8C08AA8AB8AB80000002263004462AC2862AE066226006A2602028823620E826288004A322A845E14649E0002E80880364A6\n\tC16000000000000000000000FF64F400000000184080180080100182080080180180004020060C10B200004E00600E006006\n\t10680004001604620604054C10200040608640680000600600E20614E000000000000000000000FF8EA10000000010008018\n\t0180180B80D001001801800015411601240600600600030611600601600000608410609600600601600012644E0420500064\n\t26306016206000000000000000000000FF1D0200000000100180980180900380300104980188A00044A610254A206046400000f5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (070470460068\n\t00000000000000000000FF165D000000001935955954155911944954155955800044455455244A5525545505565560075560\n\t14516D56D555565564CF4D4550556556556040110110006007086000000000000000000000FF98CD0000000018AC8AB8AA8A\n\tB88188B8AB8AB8AB80000A02A62280062AC22E2AE2862AE0062AE0002AEA26AB600E2AE0542222A808600E02602848E2AE28\n\t610F0A6000000000000000000000FFB886000000001800801800801803801801801801800009200600000200400600600600\n\t680600600000680680600600680400200000600680601024004014E55622E000000000000000000000FFF81000000000188A000da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600400480402\n\t600600C00602600E01600000600600682100042088E8AE82E000000000000000000000FF530C000000001814801800001901\n\t8408008018018000456004082096004004004006006006806010006006104804006086804000006006004008046006206006\n\t106000000000000000000000FF24F60000000018808AB8AA0AB8418908AA8AB8AB8000006AACA23302AAC2AC2AC2AE2AF806\n\t2AF0042CEAAEA202AC28FA262A42A82AE2AFAAF004288488426206206800000000000000000000FF01E00000000018018018\n\t000018238008000018018000415014802896806084006016006807006820006106005546006D071040000064069068008060008da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A81018AB8CB8\n\t818AB8AB800002644421809E32021601C0142AE2AE2AE00028E22602420628E2262260002AE2AE1E600008E08E0060560060\n\t00000000000000000000FF222F00000000180080180009580180180980180180005161261404420000560240060060040040\n\t0400611648E006006086106000006006006004020440006026026000000000000000000000FF250800000004380080180202\n\t1801821825001801800000440C00000610A0843064D60060060060000460060040AE04601601600000600620E0084060064C\n\tE49648E000000000000000000000FFEBAF00000000184080180000184D80D801001801800008400401104200200400000600004da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00600600000\n\t0000000000000000FF574D0000000AA0AD8AA0AD8AB8AB8858A38AB8AA000024A2AE00602602A2AC4862AE2AE2AE2AE0002A\n\tE2AE0D42AE28E2AE2A60002AE2AE23600848E2CE286286286000000000000000000000FF3691000000150155954551855955\n\t91194595595400000261164460C640E54210452655655655600455654C0B44CE5164D6446000556556416010150550526506\n\t52E000000000000000000000FFF664000000000001800001801801851809801800000008200601610E50600200C004006006\n\t00600000600640400600600600E00000600610600000600604602E056000000000000000000000FFBEED00000008D8AA8AB800cda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000026006\n\t49400600600608400000700600E0100062464C649648E000000000000000000000FF2CB5000000000001801401801801809C\n\t0180180000010020040464462060048250070060060060040060060440060060060040000060069060000400000060260260\n\t00000000000000000000FF01EF0000000AA0038AB4898AB0AB8A18818AB8AA00002822AC74E48E0062AC04C2AE2AE2AE2AE0\n\t0028E2AE0042AE2EE2AE22C0002AE2AE2260002CE08E01E006006000000000000000000000FFAD5C00000000000180000380\n\t1001805811801800000030A00608620602200442000600600600600400600620400602600608E00000600600600040000000002da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3851801C09E2\n\t3E20004010604600789748E14200E2060A642600600000600600604410620400200000600604640000000000600600600000\n\t0000000000000000FFCB2C002000002061A80C23B41C21C01C0180391200A081210681740E206482C6702700600600640000\n\t60061160040860040124001E704682600005E00600600E006000000000000000000000FF6C12000000002401840441C01201\n\tA03801801802050022200C10682602201508002E0060864260044D6006024406416006005000006094004000000480006016\n\t00E000000000000000000000FF0D8F0000000000D1A00023A0100180584D801800000003200488600615200430600600600600ada040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (506510010000\n\t000000000000FFA0EB00000000000184120980182B8078898C1828060051206200608E04020230001620610640E000006002\n\t04600602E0060060000063042040080C602600602E29E020000000000000000000FF4254000000000201801C838948018218\n\t05805882000000440C53600680600682644E0064000A041020004600E10408004400280000602E00610000E3164AE2060265\n\t08008000000000000000FFBED7000000000001C01801B22809801C098018C8000004610C09654609642E4162061462400204\n\t0055000608E42441040400A20000602E006200000500006006006000000000000000000000FFDCC6004000000001D0080580006da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000463200100\n\t080060001100000002084C00004060064C8490488000000000000000000000FF61DC00000000000180148381182580395390\n\t1902020000403028601600020640005640640000010000041244608600010611600000600440420000628602E20600604000\n\t0000000000000000FF8B310000000000018010099059018A9801841810000000400000610600208604040604E01013000820\n\t0102006006000006006000016016106000000050106106056000000000000000000000FF5423000000000001801001801891\n\t889821825840000000240205600600208200000602E00E0064801862CA2360061560C608E00000E4440843101100004060D600eda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000400000\n\t0000010100000004000080220000800004020000000000004004000000000001000000000030000420008000000000000000\n\t000000000000FFFEAC0000000000AA8C8AAA9C00AA8AA8AA8AA80000000003222AE2AA01A2024CA00A2AA28828C00028A446\n\t2A02302CA2243360002AA10240203808C08A010000002000000000000000000000FFC8250000000000000210018000000000\n\t0000000000000400080000001200080240000000260260000060080001000260900000000000C00080000264260000200200\n\t00000000000000000000FF83CB00000000000000240003400000000000000000002881000000002000A04002C00000060060001da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF52B1000000000201400400003401001001401200000001500000400404000088C3108040040040000000840040\n\t04000104004001005000088040004000040028050000000000000000000000FFB786000000000155D43D5594595595595595\n\t5800000042644755755648E4570045565565545140005564CC556556556556554001556D5655600055411652450452E00000\n\t0000000000000000FFAAA90000000000AA88A8AA8088AA8AA8AA8AAC00000032324A2AA2AA2822AA8020222AA2AA2AA0002A\n\tA0122AA2A228A2322220002AA24A0220002AA2CA282282282000000000000000000000FF0273000000000400208400008400009da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001000004000\n\t0000050000040810111D00000001000000000040000000000000000000FFAB82000000000200044400020000000000000000\n\t00004400100008000001504000010000200000000000000000000200000800008000000000102200204C0490488000000000\n\t000000000000FF78300000000000002080000140000000004000000000080000800000100000820000000000000002040110\n\t000000000000010000000000000020000000000020020000000000000000000000FF86A50000000004AA8808AA880EAAEAAE\n\tAACAA800000010A2B22AA2AA26A20219A2AB2AA28A2AA00028A2222AA2AA28A2AA2220002AA2AA2AA00008A28A00E0560020005da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800820080021\n\t00D40400C10414432C00500501C00C1442402404040000040000040900600010000410283040000044444040000000000000\n\t00000000FF512200000A108200800B02D008008008000548008400042A1300208A2A208200280222A0020A20800220020000\n\t02803002008020002002022000082002002002002000000000000000000000FF4A6C00000000000000000020000800000400\n\t00D00140000040020000000840000000000000000442001A000000008008000000000000000000020000000002A020000000\n\t0000000000000000FFC9BE0000000000000100000004001A800001000000019004010004000088000000408008400000000000dda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF9279100000000102000200000000000090284000002009000000800000043000080000C81000420000000400000400\n\t0001000000040000001010000001280000004020000000000000000000FF803A000000000260810800800808800808000800\n\t800000200200200200200200200200280200200040200200100B0020EB1100000020127625400A2002282002002000000000\n\t000000000000FF8227000014110001801D059018098B1C04053B2984A0044037046016414824004004244004004280006004\n\t000006006806000000006006006000004006006086006000000000000000000000FFC5E20800000000820000000010010012003da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040006040006\n\t000000100000010000006006004446006000000000000000000000FF8B410000000000000000000000000000000000000000\n\t0000000000000000000000000000060060000060000000000060000000000000000000000060060000000000000000000000\n\t00000000FFCA9400000000000000000000020000000020020000000000010000000040040040040000060060000060000008\n\t00006000000000000000000000006006000000000000000000000000000000FF7697000000000000800A0080080908080000\n\t8810800080220600020200300200282200282400000000200A00002880308C0200200020020120005440020000060020000000bda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010104000A40\n\t062862969884804004201138E603E00004602000001680610608001008201340A14001E04600400E00E00000000000000000\n\t0000FF66A6000000200001801801809801821800020009800004410600E50680000000000010200600600000704000000680\n\t6006108000004000004000000020004006016000000000000000000000FF0DE4000000000001801C00809C01821A40200109\n\t84009004060040061000403200008420000100021000100010060000060100000220464C30020D0D20004016006000000000\n\t000000000000FFC5110000000020210018028018038118000200418100000026514006008100000240002140040000000000007da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFB7D5000000010040849209821801811D42001901E001802106047886006000006136016006506009406006000815026084\n\t0010008064062860204010204C6006006000000000000000000000FFBDB30000000000038218018038818098002038010040\n\t80A0A60041260040800441168050015000081008060002040200040000800462070960100C00002B40062060000000000000\n\t00000000FF2AF7000000004040801005801805809C0000194184800023260040060000203204060A400000000010000E0200\n\t040200040000000240253240000C7506004246006000000000000000000000FF3CFA000000010041801A15851A158419600000fda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (460060060400\n\t0000400500540000100011464607E000000000000000000000FF4AD300000040004180188188183180180004000580004000\n\t0610C00E20600000600600680688600000600610940604640600000000600620700002600600600600600000000000000000\n\t0000FF59E2000000000001001A01E03801841810000001800004800600401610688029620000604601600400605601080600\n\t6806000040D00100000010800400006946806000000000000000000000FFC22600000006000580F805811975807A0A005801\n\t04401A20460260460654640CC026106006006000B4602E6084049870040009302C6097016701356B860176A74060000000000003a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000020404640\n\t788600C302085C0624604780600804600600044782E006030200006107B571290A604604E206086000000000000000000000\n\tFF9E21000000000000051101821840025800020041000040C01600400600040200002008722E026024806806000406026006\n\t22100002480422400102020002F006006000000000000000000000FF76980000000000038A1805001801805E00001E210000\n\t00E08E00640600604000600C00682E00640000600600180600600620080182608E0270200062060440060060000000000000\n\t00000000FFD5EB0000000001A1091C018C1809C4180000780100018060860CE246006C0004604C1074070C624400600608800083a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF3F\n\t230000000000048000498D5810951A81C0140C000120605180608000522410688404604600600A0A60060568160060260080\n\t0601615604643213600692600E086006000000000000000000FFA3F2000000200001861801801808001800401C0900001160\n\t0E00600608402A22400518600600E04088716600000605652600000002682E41600100610601600F00600000000000000000\n\t0000FF741A0000000000050018AD809800009880001807000108E2860C405E40784204608400600608602400708602804E80\n\t668600000880C914004640008280187046006000000000000000000000FF99F70000002080028010018C39001438400100010043a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600444040600\n\t6006446048006006004006006006000000000000000000FF0E21000000000000800001801800801000801000000000400000\n\t6000000004006006006006006004006006006006002006000006004004004000000000006006006004000000000000000000\n\tFF6D1A0000000000008002018018008012018010000000006000006000006004006805007007006000007006006806006006\n\t000006006006806001006006006007006004000000000000000000FF2E28000000008000800101801900A038418090000000\n\t00628028601011411444420640600609600400600600644680200604020F024804104900000C41006406006006000000000000c3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004540D0D550\n\t916556154550546557046A4E01600650E456002205000006200A01000002000000006026006006000000000000000000FFFB\n\tD100000000800190600002181980008B8EA00A00808A6000A0408100708600400480622E0260008060060060060066040000\n\t070068060067A8006806007006006006000000000000000000FFBE82020000000020A11000041801C4091590115004C03440\n\t002D4100526507105000116006006806006926427006D2B0140880860D400401400200000000400600600600000000000000\n\t0000FF391101000001200880100000182190480181500210000042C000423000E05404608C24642E32E20013600610E026000023a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF0FE100\n\t0000000000801801801801800801D508206020A060000264010364060179480040C104180880800600644200000200000600\n\t7806007000000001004246206004000000000000000000FF8509000000000000A00803C01C01845C0080080C0A0100634049\n\t70B00848B602640652421600E2A0006A2E50F01200220A000006806006006020000800006816006006000000000000000000\n\tFFD4E7000000000000880801801801C0180500080002004062A00CF22806C22F0A708E08400629E30002E4F602E00222E01B\n\t2A828698E10700E040006006006416406006000000000000000000FFA0C1000000000001800004001801844020950052144000a3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4A0C06942922\n\tD02A00848900A04307086824000000000000000000FFA56F00000000013180D041021881003003001000000108600040E000\n\t00824208408708E5175160090061021030570131060000062142048340A8480228044026006004000000000000000000FF65\n\t3900000000020080100100180100100100160000000060000060000000020040060060060060008068020020060078060000\n\t06002002802000006006004006006004000000000000000000FF5776050000004250811801C01A41944A22C0014010404060\n\t00047000D00006086000456000800000101004505042104002000006AC4284444800006007004006006004000000000000000063a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002080092350\n\t088890A40350070061104064200000C040F0000900000004000500E00060C6061000400420000000000000000000FF66EE00\n\t0000040002000000100184040002000000000050000010001180920080101800119709600000610002040800620042000028\n\t0300288110236036001000000000000000000000000000FFFE76000000010051821089A3982100A004800000000002600040\n\t640010013610410000600080000820080200202400411600000610002002000800E106204A86006004000000000000000000\n\tFFB0DD000000000204B21295809A29248281B280A0000082E0210A60084A090A034C28C46800000800A0022284AB06B0140600e3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFBB0E000000\n\t028554C84C50C88F08C82C10D420800001032841402208D0A8A2D220CB0D2082003129202102003223413C0A00100320310B\n\t02B02910310B442003403402000000000000000000FF7CE00000001002243842402004081040102413000000008020880800\n\t4804C042024110820830C84084128408CA00880480000200C38890C00A00884800800030884000000000000000000000FF23\n\t2700000000000080893080084081090093002000000020400200000020028400022C20040000001030030020022120062000\n\t0200200210240010020A410006002000000000000000000000FFD7F800000000018900300200001042008008C0C000010D080013a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006082007000\n\t02488288288AA82A8000000000000000000000FF3C40000000400482AA8B50800A24A00A00A02A00000100A0004020008028\n\t8288A002842842042800802002003012842883000002902912842B22A42802802002002002000000000000000000FFD7C300\n\t00000002302022020010002000002313080000840001025000094014404CA409080400488082008400510080001400000482\n\t0840910808804840824005004004000000000000000000FFBA8B000000100001801881A01825851883809820000050600010\n\t600000440C00600480600C88C000146C0400400600610440800610E40648650000C0460168160060060000000000000000000093a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (82A8488000A0\n\t01003202A82A81002C92200002A82A82A80000002880080001082C80882A92A82A8000000000000000000000FF4811000000\n\t20025420A2A01543543542003002A00000C80550441551130CD0481208C90510510A00D11440000C40D10C40800000900B00\n\t800B08950950C08550550000000000000000000000FF6A7D0008000004044004026000004000004404000001000000800800\n\t040040120C110100000014010001100010010010000000010413414C1401001001000000001000000000000000000000FF10\n\t8F0008000001000000000AA0880AA0000C002200002802A80882A8220220060008200288A88202288A2800032028833000000053a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E80000000008\n\t02800802800800800A0080A000000005200000200200200208A0020020028020000228120000020020020020000220524020\n\t00442002002002000000000000000000000000FF5FE60000000000400AA0800AA28C0AA4000B40AA00002102A9AA82A92215\n\t108310482A12892882002882A00002A82882A80000000000800902400884C82A8AA82A8000000000000000000000FF3E0600\n\t08000000000C001220000000000000A00A000002800111000040000100812004104104010204009000001002000000000002\n\t8028048040000200141000000000000000000000000000FFBC210000000000880AA0B00AA4A80AA0000800AA00002C02A82A00d3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000900930100\n\t4281001001001000000000000000000000FF1A26400000400CC0900808C00C00C02C04D00C20804148304111353310B49352\n\t301300301304B00002302300108200300300301105254B05300100220B003003001000000000000000000000FF702B000000\n\t08D80180182380182180184182301510800062902260062040260160862AE2A4004000016006000004006036044000206006\n\t206400004086006006000000000000000000000000FF04D20000000013492002484010444000002012010000884000004004\n\t894B50404CA4810844044880800004001004841000004000B10C0082C94A804A20804004000800000000000000000000FF740033a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (108048048008\n\t020046036040446000200248096028088000000000100000006016200028308028000000000000000000FF83A30000000001\n\t000810310400010000200C502100000805000402C80140D00801101505260060000060000000000060240200002004002001\n\t00006016000000000000000000000000000000FFFC1F00000008202081080284082084680280180E8E800000080820020020\n\t0200A10210201822400000A0E400018600200A00620800A0A2022000440102140106040000000000000000000000FFF14D40\n\t080040840000000044040040040040040104212010212090012812012210012010054090000211010010000010010014010200b3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000010018A\n\t1800081821001009900100000020442000600602000401600604600E00601000204440008E00002E40600000400600610000\n\t0008204036028028000000000000000000FF485E0008000010018308040918998051088C4004114000032000E2160340940C\n\t600600600025020A00000403800601000631600000608C306282488300044606400000000000000000000000FFEBF7000000\n\t001001801800045901841000800010020000800041642608012410608E086020400440224004040424106006006000004094\n\t406400156406104086100000000000000000000000FFD9AE00080000000010000200A04000008002408810C04100802000480073a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0064C0000000\n\t007007000000000000000000000000FF6F742000000018AB88C8818AB889881805B022010000002000226006200444446696\n\t146288A886002A80060000022882260022A8206206206130CC80A8204AAE2A8200000000000000000000FFF40B0000000018\n\t01800841801A21801851810000000002200000600605033420600E80E84004080000441640082A00690E0020000961460168\n\t00226006104006800040000000000000000000FF639D00000000100184281200180504B0850C0000000049400010E0060840\n\t041360465260060060800060C40A848602600400600002401414648800640602C006000110000000000000000000FF47CF0000f3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (061160460070\n\t060068000060861400160071060040002C6506206040006006006006000048000000000000000000FFACEC00000000180190\n\t5913955D30915825900400000055000055600635254655602755751655600455254F5484D655144E0045505240C4446014D3\n\t0550556556550550000000000000000000FFF2BC0000000018AB8A88A38AB88B0A38A1C2800100005060002A60060AC00E00\n\t610620E2AF2AE0802CF22E2113222AE2370022A800E04E0AE20088E2CE2CF2AE2A8280000000000000000000FF035E400000\n\t0018AB830821801803021881C48001000000600000600600001600630E00602700630000380680100200000600200000620E000ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0018C9800805\n\t801A4484B881804000000000480000600608203200624600680604680400210610088E20080E806000316046206034220200\n\t006006000000000000000000000000FFF11E00000000180380C84180180080184D201200000000200000600605630200600E\n\t00602680608004601600800604608600400000620604E200806046004806000000000000000000000000FFABBF0000000018\n\t018A08898AB8888818118AD00000002AA0002AE0062020062AE0862AC28E28F20628AA262202260883260042A803608E1970\n\t820880882AC2AE2A82A8000000000000000000FFC26F000800001801801811801C4081181180540000000310000160064061008ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000044060060\n\t06000006000000000000000000FF1CFE0000000898AB8AA88B8AB9008E98110AA0AA000021E0002AE2AE2AE2022AE2AE00E2\n\t8E28E00028E23600000E08E00E2260005460062AE00008E08E2062AE000000000000000000000000FFFC3000000000580180\n\t080180180000380D800000000000600000600600200200600608602602600400210E00000600040610600021620600600042\n\t0000046006000000000000000000000000FF154F00000004180180084180195280192180000000000A400000600600615200\n\t60062260060060000460060003464460C600E0000C60B600602000624608E006000000000000000000000000FF9099000000004ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000600\n\t60000000040000AE22008E080000006226004000000000004006000004000000000000000000FF06FE0000000AA0AA0D5889\n\t8AB8AA0AB88182100C000022E0002AE2A804640C2AE2AC2A82AE2AE0002AC2AC0002260AC2AE2A80002AE2AE2AE0004AC0CE\n\t2AC2AE000004000000000000000000FF40D0001000154154155910955854111943955154000048600055655054450C554556\n\t4C85565560045504C400040611044645000001611655404055035054E556000006000000000000000000FF4A898000000000\n\t00001801801800001843881000000000600000600040E086006004000006006000004004000096004006000000006006006000cba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000098418018\n\t0000184394588100000360000068011140100040060000260260000040060001160040040900000060060060004240060060\n\t07000006000000000000000000FF093E00000000000112380180180420181180103100001060000060004443208070060060\n\t06006000044004000006444004000000006006004020004220007006000006000000000000000000FFCFC50000000AA0AB00\n\t18CF8AB8A80AB89181D14300003040002AE2A81060402AE2AE2A828E28E00028C2AC00022648C2AC2200002AE2AE2AE04008\n\tC08E2AE2AE000006000000000000000000FFC8DC000000000000001822801800005801801000000004600000600001602400002ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (405000480600\n\t0004000000000000000000FF4931800000100000800001801803801801801814010000610001610002E20228E02602004E42\n\t600808400E01000200400208050004E006006500004000006407400006000000000000000000FF03B4800000002044800001\n\tC81881C1188380900A068004508014EC8092690308701C1100061060400444040400020C4002000000126226386000604006\n\t007006A00006000000000000000000FF1CEE000000002400401880E818800038838098000040486808006029004820005087\n\t00600600E08440C00640040650400C009000006424200000004050007006000006000000000000000000FF561B000800000000aba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (446086406000\n\t04400209000602C00E1500000064040040400040084AC2CE000224000000000000000000FFC9A70000001000450810230238\n\t0B88D8018A108A0A2012C0900066501040480063C00100265363A800400000040600402609000000600402A0880042060044\n\t06208004000000000000000000FF2693000080000021C00000A0188184180580980001002060000061280A60C00140002AE4\n\t1050000002400E4484821040822310000062160040203541064040268A000C000000000000000000FFC50180000000040180\n\t010180180380980180100000204440000C600081628021480514603004005052C41444800044400A10030011600600630200006ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A04000000000\n\t00000A000000001480000000004803502202201400060064C00060A80000080060000000000000A842042000642601000000\n\t0040000000000000000000FF5C77000000000001081C22003C15809805881802000002E0000064000040D000430001642010\n\t005000400A3204860A404E0000000060140501104841060040164B044C000000000000000000FF51A900008000002100B001\n\t0098019058098318200B4000448044E0C048C4000C400010610802030000400200000600C106400000006006002000054408\n\t154286000004000000000000000000FF792000000000000100B001049901843809801930000040620022E01024C2000B600000eba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2CA2AA000282\n\t000000000000000000FFA4240800000004082002004004010000002002200000000001000801000088800000520004000000\n\t000000000000201014000000000000200280400000000804000000000000000000000000FF7B2E000000000088800CCE8AA8\n\tA80AA8AA9008AB80000020002AA00002011200048A00228828C0002AA4060005D62AA3220000002AA0120424802AA08A2002\n\tAA000240000000000000000000FF199800000000000502100180040580000001400100002000000000000080041080042100\n\t26026002004400000440004108000000000400108010004006120000000108000000000000000000FF25E880000000004008001ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A28A0000AA2\n\t320003220AA2220000012AA2AA0020002AA08A2AB2A80002AA000000000000000000FF99C900080000040024440020120100\n\t10014004010000208001004800A14044C1491402000400404000012400000400100400000000414080008000000000500400\n\t000C000000000000000000FFAD2B000000000145953C95955955955955955C0D00005560015560005564445574CC01655455\n\t45105564C400045415654400000055655694E048156536556556000556000000000000000000FF17600000000000AA888888\n\t8AA8AA8AA8AA82A8AA80000A20002AA0000C24020A302248A2AA2AA2802AA00A0000022AA2320000002AA2023120282AA2CA009ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000210022200\n\t2802100000020020000000080000240400000001000001000400000000D009000000008000C0040000801000000020000000\n\t000000000000000000FFBD420800000000244222084004000004000005000000000000800000000110000C20348020020480\n\t4001000000080000800000008000000D0110000200000000000000000000000000000000FF75FA0000000002000000440000\n\t0400000000004C00000000000000000000000000000000000000100000080000802000100000000000004002400000400010\n\t00000000000000000000000000FF1EA8800000000488C888C0CAACA8EAACAA8AA90000002AA0002AA0002ABA222AA08A0022005ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0408E0000000\n\t00000000000000FF73D70A800048B200000008001400264000403410000024001808000001002414C084001C250CC1001404\n\t04081880000228420811000000004020024040004844044000000000000000000000FFB8E210004021280C80090280081081\n\t082003082210005020100000000230820A240A4123020220880B232301208202600620000A00200200280000282200200200\n\t2000000000000000000000FF84FD00000000002000000004000000020A000008040000010044000000804001000000000100\n\t0200000000880000000000000000000000000800A208002002000A8000000000000000000000FF9D7600000000000000000000dba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000220608\n\t200220200202000200202204A000820002000000006000000000000000000000FF68650A800030A200000010200000220200\n\t202400000020100000000000002000880000000040480200000000080000442C0000000000000048020000002A0001000800\n\t000000000000000000FFF16B000000000A00806800800810800800000C0000000030E000000000300A0021020220C2312000\n\t00200200216210210200080200260200A0590020022A2003002000000000000000000000FF3408100040015835801905841A\n\t11C1185415104414005060A02400008C7144416416C161040042100161440961070450040000060061060040004260062072003ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010800081108\n\t08040000C0000000000060000062060040000001001360020060420060060000000000800080400040460040281060000000\n\t00000000000000FF435D00000000000000000000000000000000000000000000000000000000000000000000060060000000\n\t00000000000000000000000000000000000006000000000000000000000000000000FFFB3500000000000100000100000120\n\t0200000000000000000000000100500400080000000700600080400400080000000000000000000000480000080600000000\n\t0800000000000000000000FFE14F000000200A00800800A00200800800200808000000208808000000200A0222028220840000bba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (602000000000\n\t0000000000FFBC2800000010580108583180100102124008488C062002E0100000000068000261060E010602600103400000\n\t40062860060000060428A220A070000807104000016000000000000000000000FFE7DD080000001A21001001801001003202\n\t000A00000004600000000080660800600610402604608008E000006006406006000404004844400800044800004228006040\n\t000000000000000000FFF102080000001831101A41200005242004402880002000600000000010694804608E844021400000\n\t006000016906146006000006042002880488404208044400006000000000000000000000FF00410000000818018018018020007ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (68000000C024\n\t0A20820000660063161EB00081209E01600E006000000000000000000000FF0036000000021800001401821801E098000040\n\t14420010440000000000228000600E04200E01700000A88031408400A00200000684600601108900210110601600E0000000\n\t00000000000000FF6843080000001800001801A4080481280020080800000960C000001000254000600EB070000100000001\n\t004C690701200200000200615600210000C400014006006000000000000000000000FF40BC000000101C08001801804802D0\n\t081001200000000060000000010860A000648E00600120000100200000E12602200200020082400508029044424E0240060800fba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (280011E95000\n\t0000E00000018000204471E01611602700600000000800280680480C0000144155ED00287052600000604600600000000000\n\t0000000000FFF9BC000000023821841E81800801000004000C00000000400000000000200400680600284600600401200800\n\t4006804814000006006006021004042407006400006000000000000000000000FFC422080000093801801801800801040000\n\t08080000000160480000001078041069060860860460149028000460260A4904001800000240000040006401007800006000\n\t000000000000000000FFC66200000002980000519181980582584008080020000063001800100E204208600640206E0268090007a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFF5B2000000401E0180180380D8405050800094080000046010208020000405006106203406406404100140084224\n\t11600600000600682600251010008628500020E000000000000000000000FF412A0000002018018018918018084811121001\n\t1000014060001000010250350A600E80200F0A702002000008C00400600600001490C2040220000082200042000060000000\n\t00000000000000FF9A8D000000001801881809800810084888001C00000041600008000002241402600680300E8A60218200\n\t0030C806A0400400000608681600220000A046007007806000000000000000000000FF38900000000018258A1001C00800000087a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060064060\n\t26000004804006806000106820026086206000000000000000000000FF493B000001C019000090018A0049A21CC0011C1010\n\t01804806208821805406086000907806206C040040C0086C2601600688001600602623634D80608648B00600E00000000000\n\t0000000000FFD9D2000000001801801801891806001C20001C00000080400000000080100408600600200608600146001060\n\t400410602608004E80600610200400203600E006006000000000000000000000FF0E5B000000265885809801821808021808\n\t022840080000600000000000140400600619200E007004210208404004607006000024C040042AB4305028080268C60060000047a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001010014004\n\t41062304C025420E0061404800D604641440C20040642600E006100506006006006020006206002006006000000000000000\n\t000000FF43950000018018000010018000010018000008000000004006000000004006004000006006006000004002006006\n\t006006000004004006004000004000004000006000000000000000000000FF5A5E000001801800001001C00001A018000008\n\t0000000048060008000040060060008060070060048040020068060060068000060068060040000040060000000060000000\n\t00000000000000FFE2E4000001841800001005802001105808045800000004400E00000000400600410040640E106806104400c7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF8A8D000001A01D000018018010010448441540801540011556510450A00556104150D1354F107124006D564D6546C061\n\t3600020020010200400000600800690008E000000000000000000000FF5CD500002180390401300196118197E80818010E04\n\t0038000E108000201087044000A0000650600404400600680690600600000604600602478400600680680000600000000000\n\t0000000000FF029A080001A2182808580180000020082C2130001000C0C4360000110841262972100324060060C000714A88\n\t601600748E030054214006026808006088006006006000000000000000000000FF2B0A00002188B8000010018000018008000027a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600E00602680\n\t0A80284006006840004006000087006000000000000000000000FFC479000001801901001E01C00801C00A002C1000002000\n\t2086480400209014305B100060410010000064C640622600608700100200788620700000400000040608E000000000000000\n\t000000FF4ED9000001801A01401001801800823844215C800D0081344E010030002CA680604048E50E0063280040160B6106\n\t40600E00000600E004006208006010802006006000000000000000000000FF7D7B000001801803001001801800C01A220098\n\t800AA00032A62A00A88BA22E6AF6880AF2AF2A669822C2AE28723E08F28E0A83AE33E00440641880628E802C06006000000000a7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000850106\n\t000000A48A0444C300C260008208002328A6280806D06806000A168128A2D14C00934C288A40502260000000000000000000\n\t00FFBE01000001821800101829B23042901084010040000020445600000008414408600010A5165172880022170002AE02E3\n\t260001040A400E025080C04080A00900006000000000000000000000FF698C00000180180000100180100180100020000000\n\t0000400600000000600400600000180600600000000600000600600600000600200200400000400600000080600000000000\n\t0000000000FF533A100001951950311801900801B00800005C000000051006000400800804004040006001080840006006000067a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t06950000000000A114000040B0400E0002128020000004022000000029082100010020480702638000852C00000802108000\n\t0000040040008040200006001140250100000000000000000000FF26D8000200400000016020154080000080000084000000\n\t0810000000020000800000100A971960118400009004000000200002000200080A0200018106001880C00000000000000000\n\t000000FFB68F010085801808081B0988102B30001000414000002000060000000080842AC2000260000000080122066500A6\n\t45E51600008018800201400008402E204028026000000000000000000000FF70D1040081A01B2C255801A09309854000224100e7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (50600600008E\n\t02654640604011610600602442E080000000000000000000FFB9F0010004800C22D00888C84C409008104008A0000140022A\n\t0000012098A20A210108A84208310010300214330302BCAA00140330300310B0090430435029028020000000000000000000\n\t00FF8B0D00000044030422821002020021A10021200000008044C8000000C40240040800C0814C208C00B24880884900B800\n\t40000818C00D20E008908608C0C20001004000000000000000000000FF9537020400820843800C00800800C0000000081800\n\t004290020000000045029004C0092800004002002013002202002202000502002082102000100202180000802000000000000017a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000008000000\n\t002200402A82A82382882880202001000002002202200002006000080000002002882082002A8000000000000000000000FF\n\tC9D2000000800A0A200A80804A00A20A00200C00000090A00200000080B002002000802042842C00022C4A80A88290A90200\n\t0902822842A02A0080282280280A002000000000000000000000FF6C0400000100120120C2452202422130003240000000C2\n\t400400000088455080500088000480480088C880B24829000010000850910D009508488AC8009440C4004000000000000000\n\t000000FF2F43000001A4190103580185180183190011380A000004600600000004640600642040608C00C4100543162140060097a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF350A\n\t0000000AA08C0AA0AA09408008A00008000000002A80000000002282A0AA82A84C8AA82A80092282A85302302282A0000300\n\t0280002A80002502882A82002A8000000000000000000000FF71150000001542A020C2C25543523142002222000000D41000\n\t000000D48B00550550CC0550510A21110A20A00D08CC0CC0000A48900C80810840D10B10D48D485500000000000000000000\n\t00FFDE8D00080000040040040060040040040045000000010010000000010000108010010008000014008810010011010810\n\t100010091014D1001011001041000151801000000000000000000000FF02740008002AA0A00A0008088088080000108000000057a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000A308308\n\t34800848C2C800804141004800000000000000000000FF3F3300000000080280080081084080080080480080000020020000\n\t0000200200200021200200240000200204240A00200200000240200200200008244200200A002000000000000000000000FF\n\tC1CE0000004AA0C80AA0AA0E00DC0E000002440000002A80000000001012A0AA82A8000A89288000A202A80080022A222A00\n\t00C04802802A81C01000882A9A002A8000000000000000000000FFC61C00080040000C120010000000020000010000000000\n\t80000000000000108000000008010400002400080B00200080080000800300502A041002004000000080000000000000000000d7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (92600000210A\n\tD001201201001009021089001009000000108000001000441009081489000201001021001000000000000000000000FF89E8\n\t420400410C20800C10C10854C04D4AC10D1490012B10020401512A948350300104310B14311144B10B10A00A012002041402\n\t103053103089042003003003083000000000000000000000FF14420000000058018218418218018218010218410000006206\n\t01000000600601620800622420440008400642600600600600004E00628440604000630604602E0060000000000000000000\n\t00FFA25400000020122020020020520220A2012882010000805004000000CAC80C0048008A004484481010C800A808A080890037a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFB3CA0008\n\t000020001000100000901020A000200810000003300000104800204802802000860C60000400800904000000100004000004\n\t08010210100526500200220400000000000000000000FFDF7804000000A00002100904C00D0040C002304000004400000000\n\t804002800000100044465060004B0004054010000000020208000104000422000006000008100000000000000000000000FF\n\tC4B500000000082084080080080082080881880A800010400202800800010208A01006248440420010648228315309340240\n\t00222A2326242000460092020102006040000100000000000000FF9CA6400C0040040000042040402040040240448008010800b7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004400C0D208\n\t62000C040614C082006000000000000000000000FF8453000000001800881000881900841108801809020028400612010000\n\t43062060004004060860000A200600722700F08E0102040040080260002A4028204002226020000080000000000000FF379C\n\t00080800980180101689981692400E86198612002005460A0690500246006500000060058000602126006116386086488006\n\t0060022940A001C40000442208E400000000000000000000FFF4E800001001380104180080180180004080D000000000000E\n\t00000000000608600804010040000000224610E00640620610000400428028435000408608412211600000000000000000000077a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000004A006\n\t00600004000602600810C0860060060864260001262260020060820060200A6026006000000000000000000000FF90A20000\n\tAA0AB8AB9000AB88989188A8000790008000DF22AE000000C22286046000020288A8800080E1862260668968060002062062\n\t52A044082000882042062AE000000000000000000000FF75EC2000000018018A200180180984080000300080002000060000\n\t0011004600600090084004080048601690E00601620600010E14600203484201404600404E806000000000000000000000FF\n\t669900000000180181100082382480100088180100000140060000004040164B60004100060060200204460065162460B60000f7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F76100080000\n\t180180980080188080200080100000008000060000008001062060000100060068004CC81611408612630E0005163068008A\n\t4008006006056114006000000000000000000000FF600F000154155833155955905881904000905800000040055600000040\n\t0556556000D08D56D16004C4642F4462AE40611600041409425055402A55651020650CD56000000000000000000000FF6960\n\t0000AA0ABAAA8440AA8CB8228A980088580080000022AE0000000CA24E08E0002C0ACEAAE022804246226A0EA07026000026\n\t05628220E0202B22AE286246AAE000000000000000000000FFC9884000000018808000008298488298008310008000042006000fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2060A00CE208\n\t0D0246044006006000000000000000000000FF9154000000001A1100180184D81080300004B8010000004006000000004006\n\t00600001084604700000502600600634680E00022604E44800608000004048C106806000000000000000000000FF2B1A0000\n\t000018C380180080182280880180180180008C400600000084C00600600010000680600088401600C3268063060000164060\n\t0280402200240600602C006000000000000000000000FF0EE30000AA0AB8000AB8AB8818848A0800881001800131C2AE0000\n\t013842AE2AE00022028E28F00822E2863B480F05F0260000860869812AD0082AA0880362042AE000000000000000000000FF008fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000160060060\n\t0200000600601010C006006446026006000006006006002440052004006006006006000000000000000000FFBBA40000000A\n\tB8058018AA8AB8AA88180996188180004042AE0000000242AE2AE0002A828E28E0000042AE00600604600600000640610A24\n\t60F021208E2062262AE000000000000000000000FF93A1000000001815005801801800841800011803800004400600000001\n\t400600600000002602610449400630E1260063560000060D640200600000200010E096006000000000000000000000FFF690\n\t0000000018A18D180180180080D0C5905849000030C00600000048400600600000000600624004400604620E34E00600032E004fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001808\n\t00080180100180810900002380000160060000002B60060060020000060060042A400620E00608640600002610642E000300\n\t004040004100006006000000000000000000FFC06D0000000AB8880A88258AB04388A0098AA0C380002162AE0000002862AE\n\t2AE0022A82AE2AE2802242AE2AE08E20E0AE0002AE2AE2AE2AA0900040CC2AC3202AE006000000000000000000FF6D9C0010\n\t00155940152955955155945823815911800014655600000000655655600255055655654401455614633641615600048E0560\n\t0651000452251054E456556006000000000000000000FF8A668000000018000049018010018019058018018000084006000000cfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (248000080860\n\t2C006001806004000000000000000000FF8349000800001841020CCB80109003414100002200000040000000000860060060\n\t0600002602620010600400600E14E0060000060060040000A4046424006010006004000000000000000000FF081F00000020\n\t1D12004801801A2400181580181080000CE00600000084680600680600000600610D00C80600632640615600000600600400\n\t0204086004006086006004000000000000000000FFFD8E0000000AB8440888118AB9100C18418AB89080002462AE00000024\n\tE2AE2AE0062A828E28E0002242AE2AE0061066060002AE2AE2AC2AA00870A48C2AE2362AE004000000000000000000FF61C5002fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04060A604680\n\t00083105284D444630E00600600620002E2060144C21100000040A4046006004000000000000000000FF9CCE800040481801\n\t8008418258120418230159010A000850400001000C020604600302010600609022F80C09600600E04641000605600E102100\n\t002104056006006006000000000000000000FFFCA6800000413BE188CD81803A081019838038810000006000040421000807\n\t106E4262048651640100544E40602610602600818642E00744200000208410E047006006000000000000000000FFC4440004\n\t00003C01089C01C010200000018C000000000460800080202060A680600E082056046044086004006046006086000036084000afa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018010008\n\t0180180B8AA009008089920004620620020000025600600600008E20650010220400E0260061060000060042060421004042\n\t04214120146024000000000000000000FF3D040000000018010008C18AB8C59000831F000184803661C600000058016E0062\n\t9E38066604600000002608620611E10600000610404600220010007C08408800E004000000000000000000FFE69900040040\n\t1C00813A01801800001841801842080008600001008000608602602600000002052008610400610E34611600000624600432\n\t20A835010404C207126004000000000000000000FFAB5D800020089800805801A41800021841801800100000700004848002006fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000412\n\t00080000B0000000000000000000FF118980000000000400000002C0020240CA02805400001101300000000C00000002402A\n\t00060061004A02003400081480000000004400001000100C8006008120000000000000000000000000FF19FA000000001801\n\t001C018CB801800101040002008020408000800008600600648D48042002000000300400C0064C6006000006244004100410\n\t0840D4004000006046000000000000000000FF277800000000180101490180190D95404B9100D00400106200400300006506\n\t04604600011040002000254410653601600E000006006204400020050404544450016006000000000000000000FF6077000000efa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AA02B0822AA\n\t2AA00010220A08208A22A0AA0002AA10222200A0002A22AA2CA2022AA22A000000000000000000FF1FEB0000000000080804\n\t0040002202800021201000000010800000004280010000400040040042800010008000000802000000000008000000100800\n\t00000020004000000000000000000000FF99070000000AA8E88AACAA8808E888080089688000000422020000000022AA2AA5\n\t02C0028828870041712205A0021026020002AA4022123462102102AA2002002AA300000000000000000000FFE71000000000\n\t0001001001800000008001000000000042400000000041000000011000E0260260000080960003204001500000000880C803001fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (ACC0800CAA8A\n\tA8AA880CAA8C288080012AA2820000000022AB2AA2222AA28A28A2002332AA2AA0020022020002AA2AA2ABAAA0000020AA2A\n\tA2022AA2AA000000000000000000FFC203000800201004200200444400040000440021000001100C00000043100500400102\n\tC0040040000248414004400000000000040490804044000040000040D5004004000000000000000000FF52A8100000355905\n\tC3595595591190595590194380005564540000001075565565175565545540004C4556556336456156001556556556554400\n\t25655655650DD56556000000000000000000FF1AD70000000AA888CAA8AA890C8A89292A88088A80005022A20000000832AA009fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020400228488\n\t228000000000000000000000FFE3DE01000000000050000000000000000000A0A00000000018018000000000000000010000\n\t840000000800000000801009500000400400440000000800400000000000000000000000000000FFC68A10000000022C5244\n\t0000000000C00003004000008000500000000B10000001088000200201000010000002083480000010000000000004005484\n\t00000121000000000000000000000000FFCA0400000020000001000000000004040000001200000000000000004000010000\n\t00000000000000088000000120000150000000000000000008000000000008000000000000000000000000FFD0228000004A005fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5611600C4840\n\t100040C400600E000010006001006006004000446006226A8E00E000000000000000000000FF075500200008100000000100\n\t10800020010052110000024A9401401002C0250A40258000E42CC00004440405000000000800400000402000422810440401\n\t4004444000000000000000000000FF64E00001280008A400488288090CA50804840800800001244200220800300280205211\n\t30224A200002202202A002000000002001002002002000282002002002000000000000000000000000FF9202000000000000\n\t00000000000000000060000A0001800000080080000800000000000810000008000B0000001080000000000000000000000000dfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200800A00800\n\t800800800800000002A20200200000208000200200A04002400000200208200200080008400020200220E000400000000006\n\t002000000000000000000000FFA76C0020000000000000002001000040000004000000000080800000048000021040000004\n\t208800004804000000000000000000000020000028800820209000004000000000000000000000FF85360100001008601008\n\t00800800A00800800E00800000A8120120000020C21030020021029020000020020820020000104020000025821CB58021A8\n\t2200A002002000000000000000000000FFCBD300015000194400590590191585180504914380000164460864800060060060003fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (140140060060\n\t00000000000000000000FF982200000000188400188180388180D0C089080500000060060060000460040062062000000000\n\t0000200200600600001000601000600800014012C044104016016000000000000000000000FF44BD00000000000000000000\n\t0000000000000000000000000000000000000000000000000600600000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF0111000000000000001000000000001000000000000000000080000000000000000000\n\t0006006800000800004004000001000000000004005000800800000000000000000000000000000000FFE27200000000080000bfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (680008020010\n\t4026026206810008402081226A005022884AC015015006006000000000000000000000FF22B8000000029880210AC5811811\n\t80F8A6888801908021601600610000E0C41068962CC00602608022240208400439001000640111602C82243000020408510E\n\t016000000000000000000000FF2128000000051800201801801809A018008028038000C16106806001016004006006114006\n\t0460005020020460061000004060084470C680201080402480400600E000000000000000000000FFF282000000001840150A\n\t01841851801C02A22A2100800060060064003061140069070040000805008420221062064080000060800065044A02004044007fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (019E78301818\n\t80828847020110600608600800708640E4160461C730650060E0060040060000000024000661940034209022AEF070461860\n\t00000000000000000000FF460E000000001800410823811B20241220E30801020100600610611000600E1160062864064260\n\t0001620E224006888208002010086806022049006D5700610600E000000000000000000000FF5F9300000000180000088180\n\t188004124020222900000C624621600080600E406406C8622014028180600E24608600040000201000680C04210050000408\n\t5026006000000000000000000000FF31610000000018421508018258C0601000020021000000E1060064003260160062060000ffa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600000\n\t0000000000000000FF3F3000000000184814E80582981400900483090980004DE44E02E20000604406600E0970A600E10409\n\t680400E004818000004000E26060348560202116006826006000000000000000000000FF7BC3000000001812209809801800\n\t013000820849000110600F00E00000640C00600E006806006000A0600481400600000000400004600C008001206046006046\n\t006100000000000000000000FF0D32000000001800001801801A00003A82802E11080002E22E416000006944006006006006\n\t807804006006806086000000004000016000000880406806006006006000000000000000000000FF02FE018000001800060900006040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80600E0E7216\n\t10408600004000400100600610040004A1B6087006806000000000000000000000FFDB06000000001E00604F01801841801F\n\t2194DC1180000064C6C0601000714600644650610720600000604680440F001800004000296034412A880800042040060060\n\t00000000000000000000FF791A000000001802120801801A0982180000844180012462060060100062060860062370070061\n\t0421608640400608000800500008620E040088091424024006006080000000000000000000FF5C2300000000190000080182\n\t9800621801E01803800000780604620820F00608600652612600E00014609430400408003000480008620440200812A4060400806040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (108180080194\n\t1A03800003640650610E00610600603000404600601414000600200000600600000600080641600000614220600600600000\n\t0000000000000000FF97BF000000001800845951901049829D41805A11A000486146816006006046486400D0400700E80080\n\t02468024208A6806800806280894825508816012046007006000000000000000000000FFFFF6000000401800000C21C01A81\n\t821C01C11801800022E01680E0800060062C600E00690640E0000061868041360A00000040000160C402380010280E126006\n\t006000000000000000000000FF37A600000000194002881D88180D80D804000107800108604E08600041605402600600602600406040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000000000\n\t000000000000FFB8980000000D1804821823801011821903841822800001600611600600608E4460000A4306046140000006\n\t01220000640600000620004C204010006002004006006000000000000000000000FF84FA0000000018008018018010010000\n\t0100180180000040060060060060060060000040060060040000060020000060060000060000000000000060000060060060\n\t00000000000000000000FF9F4C000000401800801C01C01001801001C01801A0000040068060060060060060008050060068\n\t02800006802000806806800806000004804002806000006006006000000000000000000000FFD3360000000018008098018000c06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A82A01253A0E\n\tA80666F618828E088024204000C0600A806106446000000000000000000000FF85D7000000001A01801801811A01A40801A8\n\t1800154011655700650608655708641000754600645400200600205000600600010680000000080082408612602E00600000\n\t0000000000000000FF559B0000000838408218238D122128888101301A00008260860A601720600600604000620700600010\n\t084600A00000600600000600020C045100006006006006006000000000000000000000FFE637000000003C00801801901841\n\t914811A05300804034653644634654F24610E310C0C03640E014222516D4214802712615054F09020600600080601200400600206040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (804011811100\n\t000000501600E106006046906000006000000000802D96002800026006041047400806046110006804084006006000000000\n\t000000000000FF3108000000001801801801801801C00801E0100000000044160061062A64072063280040C1200101003004\n\t002050006006080006001004004800047000044106226000000000000000000000FF3A1A000000001800801801C110010204\n\t011011010CC01160A78064068060B6886000806406826448000004080200006A2E0011070000060070004061060060560060\n\t00000000000000000000FF62B4000000001820801801821009820803821F21002028E22621E22E4EE28E62E3E82AD0AE66E100a06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF77FA040000511200909929B13A05A24A23B25A400000324C0612E0062C754600611084E000800820896B0E80A0\n\t0092688600080E0A08CCCCCD00C349149040B7116000000000000000000000FF9453000000021080805801841A01288A1100\n\t9B0D800100E10680602600700E016000486516516000247026202010206246400026010000000020806024A0400620600000\n\t0000000000000000FF435C000000001000801801801201000801001801800000680600600780600600600000580700600200\n\t4006000000006006000006000004004002004000005806006000000000000000000000FF9784000000051805801801A1180100606040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200260200000\n\t200200000200000204A000002000100802006000000000000000000000FFA2AD00000040000100210C4B0001000011021222\n\t00000005C000800100085100800040400700600102428C00840800002100002001811C024170408018090080C00000000000\n\t000000000000FF967600000012800020C00000200400006009800400003402101300218202A0800100028097296020008000\n\t0401403801007000000204A0090400020000000408208000000000000000000000FFCA2E000000041001801A4180190304E9\n\t0B00110800008A400684680630610E046088206800100000086126006000006406000006080000000080144424004806006000e06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C18218038000\n\tA962CE00E00600644600640028688C00C0000068064043001061062000060000064161002064160060068060000000000000\n\t00000000FFC6FF000000400C00C40C44C48D02C20C08D14950800104200394300290388A0C2081002002083001A0B5430420\n\t210034020810020095330434310C3003092403402000000000000000000000FFA9080200000000C02C04A00082002A020030\n\t40100000C01000880000000400100C0088130C00C800610C40804800020280000008800840E00A00A00880A0082408000000\n\t0000000000000000FFFF95000000080000800800840800900800842AC000000190020020020820028020001030000000000000106040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF56610008000AA0000AA0AA0AA0CA00804409008000002A82A82A80002A80402A82A8220A882882800000201A008800\n\t00002A00002A8080000050250220208AA82A8000000000000000000000FF3495000000000800A00A00A00A00B22A20A08A00\n\t8000003002802002802502003000802042842800C12802812020802802010802800802A3288088A892882003002000000000\n\t000000000000FF418C00000020100020120120024020129424424B00000048040040040040548050008900048048000C0508\n\tA04C00000000800004800A28880A48820804845004004000000000000000000000FFBBE3000000141841805881801801885000906040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040288000000\n\t000000000080000500100120140800000000000000000000000000FF58B80000000AA0000A00AA2AA0880AA0020800AA0001\n\t2A82A82A80002A8AA82A82A80212A82A82002202202A82A80000002A00002A82282A80203502A82A8AA8AA80000000000000\n\t00000000FFB2450000001540003543543543103202102441540001550D50550000550510550D50CD1510550880B10910A100\n\t40800800550800D50C50AB0800C00C10C08550D50000000000000000000000FF0D0800080000040040040000042440052041\n\t400000008000010000000008000000013000000010831011090010010010000090010010010014130010010000000000000000506040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C20100000048\n\t048040008040040008048AC044844C82908890800800800800000804805228800892D2880480400400400000000000000000\n\t0000FFC253000000000000000A00800800800904900800800000200200200000200200000220280200200000200200200000\n\t2002108002002002002240002002002800800000000000000000000000FFB34E0000000AA0000140AA0AA0880AA0300404AA\n\t0000AA92A82A80012A8AA82A92A80102892880002302202A82A80020022200002A81802A81000002A82A82A82A8000000000\n\t000000000000FF9D3F00080000000000000000000200A100080400000000000100000100080000000000004100020002022000d06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF7EA04008004400004A040240005840042044240000010010210012210810012010810054412C10291E9101280000000001\n\t001091101089091041001001001005004000000000000000000000FFECDE400000400020450C00D08804C42D40C02C048001\n\t0030930034411030034010830030135034530134030824C048200300140300B0931032030030030030030020000000000000\n\t00000000FF90CE00000008000008180380580188180900180108002AC0240840100061260882260860040140002060062060\n\t00006206008126206226206100006106006006006000000000000000000000FF917A0000000002002AA0002002442002114400306040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100160160000\n\t06006004000000544004004016116000000000000000000000FF11A70008000000000000040220A192014802001004A00901\n\t104000205000000800200003062860000000000803404000A808000000020002804820808840001001000000000000000000\n\t0000FF1E9B00000000000000800100102580001002000008002B001008000000004011004008000604E20040408000050030\n\t040000805009040020C240000000000000000000000000000000000000FF817F0000001A002000080088A8008B6884800806\n\t90000024C20020080020C000020200023C0040000422124020311130020002022020220024801024C010014200200000000000b06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000600600\n\t600000600600000640400604608049000022000010604600000600600E02C450284024050006006000000000000000000000\n\tFF40B10000000000000018010010018838008800A5094008620600602800E00600000600400600640000000C004001047506\n\t10000600640604040800C00C284126406000000000000000000000FF159A00080010000006182104D0438019408C00A00000\n\t27000048000840E18400008600402010022004208450614052624660000600601C0140400245440046062860000000000000\n\t00000000FF4FEB00000000000000182300988382981480000802002000A81000001060241001260062D0400040002104006400706040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFAD\n\t5D40000000004000100180000180800080182280000000000040000060060000070050070463018080032480002062260000\n\t060064460260D0006346007007006000000000000000000000FF06860000000880AA0AB8AA8460B581800418108080002002\n\tA82A82A82AE2AC2A8006984A88AC8400030906C4C00022E00E0002AE0062A40C40D0106204200AAEAAE00000000000000000\n\t0000FFA9EB20000004000000180082000188000002B81080000C8000000000006004000006034040000A000002D608400000\n\t628600000600600440680005608C084006006000000000000000000000FF1F7100000000400000100110900D8258AC80004500f06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60260002AE00\n\t6BA41870002AE0262A82AE2AE000000000000000000000FFBA9800080000000000100101184188003084C010000008000000\n\t000000600400000643400600688024040A10A000CD629700000600608508410000401608E006006000000000000000000000\n\tFF04990000001540921559551559558C415495410800005505505505505565545500065545565160045415560060000C6116\n\t000556006014410400554016556556556000000000000000000000FFC51C0000000AA0AA0AB0AB8801018221008018A28000\n\t2302A82AC2A82AE2AE2A80060052AF28E0000800220000000068260002AE00744E20C20022E3262232AF2AE000000000000000086040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00E136126000\n\t00621600000610400600600213000202200015601600000600604E0840020C4014052006006000000000000000000000FF84\n\tCC000000000002001000001801009800000801000000600600600000600400000600404600680611000202200114E0160000\n\t0600600E028002004314002006006000000000000000000000FF22790000000000900010000018018C400180102980000060\n\t06002000006006000006004806846080000002312000406B06800006006004C0452800600600080680600000000000000000\n\t0000FFD9F90000000AA0200AB8AA0AB8AB8000AA8AB08380002AE2AE2AA2A82AE2AE2A80062AC28E28F2042202AE1060000100886040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF512480\n\t0000000001001805825801825801813801800008600611400000600600000600000600600200000041000600600600000600\n\t6006042008004006046006006000000000000000000000FF248B0000000000000010880018AB8C98C5801883800028620620\n\tE0002AE0860002AE00428E28E0002002222820000060060002AE2AE30600C0102062262822AE2AE000000000000000000000\n\tFFB1A200000000000012100400D801005800009841800004600600600000602400000645402602600400008A00A000406346\n\t000006006086446028016086002006006000000000000000000000FF8CA100000000000000B0200C18018418558C2809000000486040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0002AE2AE2AE\n\t00A0082AC2AE0062AE2AE000000000000000000000FFFC7100080000000112900180980000000100900100000A200E014000\n\t0065260000063020060060040820080C200600620E00000600600E010026088144104006006000000000000000000000FFA1\n\t7D0000000000010AB0A98898AB8888238A1083000022E20E2060002AE2AE0002AE2A82AE2AE0002AA22808200632E0A60002\n\tAE2AE2AE2920202AC2AC28C2AE2AE000000000000000000000FF6B4D000000000001005955943954115091945953800040E5\n\t465400005560140005560525565560044284C24100064B614600055655644652000044641644E5565560000000000000000000c86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (070050000060\n\t040800860960860064C5003406000006006006201306C2502E20044400028E04E007006000000000000000000000FF00CE00\n\t0800000001401809821801A44845020022000015500F12600000600500080600602602600000210751080605601600000600\n\t70068800400040060AE006006000000000000000000000FF8E30000000000001801A43C05800000911811811800000204600\n\t0000806004000006006006006004000456020006506146000006006006440000006006406807006000000000000000000000\n\tFF73DC0000000000010AB8818898AB8899118838D180002023C624C0002AE2AE0002AE2AE28E28E0002A810604000600661600286040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF8DBD800000\n\t120001B01A3180D802000001A288408A004942A680684000E50608048F0064403482200C7306002406006406000896206907\n\t022440104004024406006000000000000000000000FFE7678000000004030C3049815E50048C8D0108A0904000C116000281\n\t02F88780000724224622600010C026102206006206000046106007142110006046007A06006000000000000000000000FF0B\n\tB2800800440001423C81C0180DAA888380089884214048468042C1026406800C162080161160000441070008060060062000\n\t370B7706A9A008104026007007006000000000000000000000FFCDFC000000300001C01C81801800080821C200040000881200a86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060044260900\n\t88004484544006006100000000000000000000FFC19F00000000000180182180380200C82900908100800060060060400062\n\t8408010E0060060460021060262060C640616E00800600622600A2020802942241160D6000000000000000000000FF8EB300\n\t00080000050018018A98E98828D300102D02200062360040080060042082061C61B602610201404610422E02600600040601\n\t4056002102004514094086006080000000000000000000FF63AA800000000401801089801801840401800804800008080600\n\t412100600600010602620810002088648604200628628600000611600610210843604C00445743600000000000000000000000686040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000000\n\t000030402602608080612C0044485001400000004080002040400040800C8000000000000000000000000000FFB29A800000\n\t00000800000000000982C04C02000800001000000D00000002D00000000300060062003100001081000500100000000A0000\n\t0283004A0030000000000000000000000000000000FF4A050000000000018018098B18218A080500000A0400080226004090\n\t00600441040608602000002080600604640414620E00000608C0060004004A8024004226306000000000000000000000FFF0\n\tBD00000800000180192180390A0108D18101200140004006000000006304080016026308080000006526404116006006008000e86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9D0000000001\n\t128028AA8AA82292280888088080002222AA4220002AA08A0002AA00A2AA2AA10000250204A2A230A0A20002AA0A22AA00A2\n\tA02023223022AAAAA000000000000000000000FF2BC010800000000000040020000008000005202800000000004880010000\n\t00000800020000004281000100080000100208000800800001000500088000000000000000000000000000000000FF3D5800\n\t00000000608A08AA8AA8328808848928A2800020A2AA3120002AA4000002AA04228C2880001222022220120026120002AA40\n\t22AE08600011A2002002AE2AE000000000000000000000FFC00400000000010400C00000008180000101000000000440000000186040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000080002100\n\t0000000000000000000000000000000000FFB5908800000000AA8AA8AACAA822810CAA88088880018122ABA020002AA2AA00\n\t12AA30228A28A0002ABA23A222AA002202001AAA2AA2AA2AA20104A2AA2AA2AA2AA000000000000000000000FFE0E2800800\n\t0000000D0401401080011140043035000008C004000001004024001004480004004203450050500000040000000805008004\n\tB24002020014055004804000000000000000000000FFA9F0800000000155955D559559558231559011030000345556046001\n\t55655600055741655455400154E44E456556436146000556557557554020406556557D57556000000000000000000000FFF700986040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000080\n\t8000800000000800000000008000000000000000001000008002400000280A0000000000000000000000FFB23E0000000000\n\t0000000004000040011000420000000010008002000000000000000000000000000000010000004000000001000000008010\n\t000C8040400400400000000000000000000000FFA9DC00800000000000020040008008840002402400003410000D00000000\n\t000010010300200200010000001080000500100000000008000001004A0000000800800000000000000000000000FFD4E400\n\t000000000000000000001004400000800000000080000000008000000000001000000003000001080000005001400000000000586040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (015011004194\n\t18B194580184194594590D8C4010648651420651010600608001601400480109600600654000605000000640600749600000\n\tC22610400E086150000000000000000000FF9265028000000001611001008004000611030041080008C0052440000C800420\n\t400800010C084020000018C0C00010000000002014000000428010C005004040040000000000000000000000FFC0F60500D0\n\t1104208C0950B42804840944CC488482400823022B280233008200200080A00A00200101200A2024C08820500000024A2002\n\t412001002002902002002128000000000000000000FFF5B1000000000200008000000000000010010228100000180000080000d86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800800000\n\t004004004000000000000000000000FF4DCC000000000001800800800A00A00B000028110000002802002802000002002000\n\t00200400000010200200000008200000000200200200210000400020E002002000000000000000000000FFF5710280000000\n\t0000100005020008020824004010404000000008204880004000080000000850200000100140000000000008000400000000\n\t00008000000000000000000000000000000000FFE7AF000000000400800800A00800880800A0082800203120624026222000\n\t0200200100201200200108200280200048200000014202201A00240104204200A402402000000000000000000000FF38E20500386040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (168161002040\n\t804000001468B550640100401000000601620540F029520104002C04504000000000000000000000FF3FEB02000000000180\n\t18018010018010C1005028000004600602000000002600620000620800000000E00400608808600000000000400400600200\n\t0044120000000000000000000000000000FF46BF000000000000000000000001800000000000000000000000000000000000\n\t0000000006006000000000000000000000000000000000000000000000000000000000000000000000000000FF0C28000000\n\t000400000000001001801000401000000000000000000000000000000080000600600080000100000000000000080000000000b86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000481C01801\n\t855005881101445030020004600600000400140600E40000610020000012604E08640000200000000000640400E248106484\n\t023406006080000000000000000000FFE3BD00000000002B8898C5801881813C4BC0904110400D68060AE04204102E806400\n\t082A0E42640040E35000608080490000000610C006A06800300004082114284000000000000000000000FF196B0000000000\n\t11811901801A00005831810201042000E00E8068060000060060803068060460000064842068080868080000040040060064\n\t00038424000000000100000000000000000000FFE7A6000000000543C81801C4D8842818030210000040117016108006000400786040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08D060060000\n\t00000000000000000000000000FFD1CA080000000401C01845807889803C4B421041904104604E1002C60083060860080022\n\t8602640040411200602000010000010602E00601E848016016903004784000000000000000000000FFAC7300000000000180\n\t1801EA1008001013040401800010E09600050E0080060060100020265060020050428060002A200000000408600E08700080\n\t620700208F006000000000000000000000FFE66E000000000001C01881B4120000160140020080010861260C001400008600\n\t60000070411080000068060060004C2000000082006054106140A0E40C083004004000000000000000000000FF9AE202000000f86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600050200E08\n\t6000256002014280004000000487806024006C08006006442104004000000000000000000000FFDAD50000000000E3843801\n\t831020121031811020000086680680600400012618600008700600640002E0D6A4C010064620440206166014047041806026\n\t200206006000000000000000000000FF9D1D000000000105801803881043E011250010420000006007001006000006006000\n\t012806806004086B03405820004020000006006004006004106046000404804000000000000000000000FF96050800000002\n\t0180188180190020D801001400000000600602000402040610620000648602E004006006804820004000000000054024006100046040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (09841A8590B8\n\tA0621805911115008129780780680C0C018E00600000208602E024104462064040224A0048030400F0968260C10060860023\n\t0F006000000000000000000000FF0541000008000001801809801E01811955814431100000E0860070040400060570080038\n\t2730600484400A005A1180613000005620640711641048E004010104084000000000000000000000FF3F3A00000000000180\n\t180180980448BD11C050010000006006026804000006006800A1200F10720020400A004488006000020004086846846A0810\n\t6004020001000000000000000000000000FF17B4000000040001E03801821801835A01883488000000E0060260060200460000846040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400400400480\n\t6000000000000000000000FFF28700000000000180000B801800209A01800001010041602620600E00600800E80620614612\n\t680400405200200642211600005600400684C0A8206106006406006000000000000000000000FF416D000000010009800501\n\tD2D921821B4DC12651100004710E01700602600004680E004406A06824024800040416002046100007016D0610700400E006\n\t48E09688E000000000000000000000FF99DD000010000001801803CA1807801801E01001000012602E26E604100106006000\n\tA0220601680081C00280400000440000040740600600642410600628200400C000000000000000000000FFFBF5000000048000446040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A42262160A0\n\t0B611254E04623289604011602684E046100006006006006006000000000000000000000FF97E00000000000098040838050\n\t01800029800003130004E00640604604E00001621640E00E08640C00420000620600202648800608E00620600048E1060060\n\t06006000000000000000000000FF849100000000000180000180180000180100000100000060060060060060000060060060\n\t06006000004002000006002006000006004006004000004004004004006000000000000000000000FF4F3C00000000000180\n\t000180180180180100000100000060068060060060000060060070068060040048000000060030060000060068060060008000c46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2001A0180198\n\t200080A2E29A8002F0880AE0A86AE6B946E28EAEE2262BE7A80AC2880BE226A2A2BE2A900E0AE0A6027180A0608605614600\n\t6000000000000000000000FF746D000000000221800001F010002041441120900440556500C56D1008600008E0A6C1755740\n\t600C00604AC06106C0092600100420015420100100400600400C006020000000000000000000FFEF62000000080001800003\n\t983049808024090008002008606000650000700000602680600604600600480080600680040600000600610680664600C006\n\t004004006000000000000000000000FFCDDB000000100201C80031841208294301B040B1004048688E95701650654952614600246040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004004006000\n\t000000000000000000FF45B80000000000119001518410418003148002000001406801406400006000506006027011000000\n\t80600240600680002E000106A00816E05040906004026006006000000000000000000000FF74DC600000000001800001B014\n\t00400022D000A882004171000060000862000AE0868055280002880060400060860028060000070030070070000060040060\n\t2E006000000000000000000000FF283500000000004180000180180008430080C00090400A620024E31020680820604640E8\n\t0640E00000480A40E00640110600000600494E00408080600600E086006040000000000000000000FF3FA7000000000001C000a46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (108000006020\n\t0624E26600042600008440000410002000043404400400E000000000000000000000FF6C240000000004A18221158352222D\n\t5C08050230000094E0008C6C31006020006086806000020808A22A068AE846820CAE000A06A26886C0E8B085080488CC240A\n\tE000000000000000000000FF86AA000000000001800001801E00201903604101000020623621600600620828600E4A650750\n\t608011200A206286480006000114014205080200100424424084406000000000000000000000FFBA85000000000001800001\n\t801801801A01000001000080600680600600600000600600600680600080000000600600200600180400600400200000000400646040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800002810940\n\t800040000010280206244200200000200600200000401002600A01210200220200060210200200200044600020A023006000\n\t000000000000000000FFD86600000000000000000000600582641802200000010810006003000008010000800700060260C0\n\t0004040A40802A4000000100008280088600000200520080240000000000000000000000FF075F0000000000000002C26400\n\t4194008400C08000012001311910080000418010081000862865090080004000000400000000180400100401501000000000\n\t00810000000000000000000000FFA640000800000121800009839021889800000008000000E800006020406200086806284C00e46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2082C0000000\n\t00000000000000FF1B95000000000001A0004185380590580B102051800000600C24E0140060000060061068849045000042\n\t06A4604600400600028E2C601604620010C406006016036000000000000000000000FFB197000000000500800680900C20C2\n\t8CA08105040000082282082343402020C0200305340B00304830302301308324350A0010030030033030C92230334A344200\n\t2000000000000000000000FFE1110000000002014203003002002000023103350000020608808810000028600000800B0490\n\t0800980A41000000C04198000800A20800E008888B8840880E508A0000000000000000000000FFC23800000000008080200000146040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (101100100000\n\t1001011000001009001001001049001001000041000000000000000000000000FF8ED00008000000AA2AA0AA10002A080088\n\t0AA00400002A8AA82000880002A82A8000420288A880603082202A00002200000000800402002A8060220200000A00A00000\n\t000000000000000000FF40D8000000000400800200A84A00A04C00C002808000802003032842002001002002802042042A00\n\t882892812802882802000C12C02842802800802892812112102000000000000000000000FF2E880000000004010000012312\n\t802302232002530000804805104A04004800004004A900040048008448000000008140000008408C8888800C0888C824D20800946040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100040020001\n\t0000010008000281000008000000000310400002030300080000004000000000804000880002001000A02212012100000000\n\t00000000000000FF3E970000000000AA4AA0AA0AA0A20AA0AA03208A00002A8AA8220020000AA82A80000102A82A80002A80\n\tC02A80002A00000002802A82A82A81002A82A82A90880B0000000000000000000000FFF3C60000000003545543542502442D\n\t03483542280000550550D00A28000550D50000880510D50800400D40D50800928800000C50910C40D50810C50C1089013014\n\t0000000000000000000000FF220800080000000000000040041040040050040000000000011015080008010000015418010000546040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000000000\n\t0000000000FF59960000000000010012002012802012012212440000804005044800000005004000C0084484480080480000\n\t0800908800000A0480480080082088880080002482C000000000000000000000FFD496000000000000A00800800808800800\n\t892810800000280200A15200000200200014A00200220800210200200200200200012A002002002008002002002912102000\n\t000000000000000000FFB7780008000000AA0AA4AA0AA0220AA0AA0000C000012A82A8290200000AA82A8000000288288400\n\t2A86382A80022200020000402A82A82A80802202A82A8600600000000000000000000000FF9C63000000000000000000004100d46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002002203222\n\t003022200122022022002400002002012012002100400400000000000000FF0C0800000000040042040058418050A4005014\n\t02000102904100108100128122120000128524500100C0010080010000000010010D02112812B91610090010050040000000\n\t00000000000000FF7326400000000420C20C10C00810C2CC20C00C14800112B5134035230011030430402030D350300104A0\n\t03212093002022501103482103103021003013003003002000000000000000000000FFDE1600000000800180180380900180\n\t1109029081810000600415400622020628630008620600E0A02040960062262262060202460062462463002062060060260000346040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (485000100190\n\tA000600001008000000E00608800200400444000204614608613222E00000620E00C1044C820002003012600600000000000\n\t0000000000FF994600080000000004400008000180808400000C010012040000002021041000009000001620644000022002\n\t05400402004480000100480080B0480448040040010010000000000000000000FFA867400000000040000009002011840048\n\t05011100800005202C84204400001000C010002610E14042010C000088444400140500210108020000504404004040000000\n\t000000000000000000FF8263000000008011801802808840980880880000840008214A00200204000240200020254802001000b46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFD0FC00000000000180180180091184283300110100000061160061040000060060000D200604600000224E24E006\n\t30802600024644613400444005402401402E006000000000000000000000FF59D00000000000018018018208820208050250\n\tA9020020E0AE0860442000A620600002208220201000200600700600110621008602600400C00009601000000E0060802002\n\t00000000000000FFD3E10000000000018C18019208C20329280238A5082034E4080880800504A60060000264500180000024\n\t0608644608A0AE04000622604608600000C404184086076070000000000000000000FF92240008000000098858010008019000746040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0648E0060212\n\t2600030652E106546420B2C225204AAEAAE000000000000000000000FF0097000000000001A01801000800002842C0103200\n\t0000603000000000000600600000600202200008E0A680600600002600000642E00600600000600000600600600000000000\n\t0000000000FFD1620000000000AB8018AB0A402208809080115800002AE2002A82022A80062AE2A8216A88AC800086E14604\n\t619E81010E000016006456016008204314214A06AAE000000000000000000000FF41D5000000000401801801012001800000\n\tA01224000000604000004A00000600600000604400484048408610622604048600008E0962062D680010008E0A610600600000f46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80188380002A\n\tE2062AE2062A80062AE2A82AE28A28B0182262062240472A88260002AE0062AE0070002202AE2AE2AE2AE000000000000000\n\t000000FFACD6000800000201C01801040901824804000C03800000600800001000000600600040700600604010E016006C46\n\t50000E0000260060060060080040040C4006006000000000000000000000FF0CFC000000000155C019559549441109100005\n\t018000556500550556550006556550557552D12004C4640F55651655050E000556106554534130550550550D56D560000000\n\t00000000000000FF732F0000000000AB8018AB89082B8888C080100000002AE2C02A83402A80062AF2A81262AEA8F002A062000c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF47B400000000000180188385588990984B00812180000060B61360220000060060000AE0060064403260062D65460002\n\tCE000006006126106208004484404006006000000000000000000000FF0A2000000000040180180180000004004100022180\n\t0000603600612E00000600680000604202280000E04E00F55600049600000600E00600E15090600680000600600000000000\n\t0000000000FF5FC6000000000001801801801909801815801011800000610600600400000600600000680680600088608610\n\t6006000006000006526006526000014004004806806000000000000000000000FF7BFE0000000004ABA018AB0AA8320CA881008c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (051652205600\n\t055655640645642008E406412556556000000000000000000000FF03E1000000000000001801805801845805900801000000\n\t600614602400000600600001000400400000600600002600000600000600600400645011600E082006006000000000000000\n\t000000FF68590008000000AB8AB92188183380188182500180002AE2062062C80002AE2AE00000428E28E0000062AE006046\n\t2000060002AE2AE00600612020403C1242AE2AE000000000000000000000FF11DC0000000000018018118000000240018848\n\t0D800000600600600600000600600020602202210400E00600601612800600000600640E4560800AE0060960060060000000004c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8900002AE25C\n\t22C0860002AE2AE0001E028C28C0102262AE2A80062A85060002AE2AE2AC2AE00064606E0622AE2AE0000000000000000000\n\t00FFD1FF000000000000001805881080041801800829000000608E0161160000060060000A800000000008E00642000600A2\n\t8600000600612E106010226124022006004000000000000000000000FFB6880000000000AA0AB8AB8218A38098C180A8AB00\n\t002AE2862163160002AE2AE0002002AC2AC2802AE2AE2A828E2A802E0002AE2AE2AC2AE08000630420A2AE2AC00000000000\n\t0000000000FF16970010000001541558318538441159538B090500005564465462060005565560002005505505444265561100cc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t7785000000000480001809A0180804400000380000010264A124040610008700602020208408C0040060052002A700200E00\n\t0086206000044300084006000006004000000000000000000000FFE42B00080000040040180180908180202000D840000000\n\t604008022C00080700600040000404440000600600054600028E0000060060048064B4004486401007004000000000000000\n\t000000FFA697000000000000001C019458005500082C18050000806904004006000006006000012044004108116004000016\n\t0020460000060060000060000AE007092006006000000000000000000000FF1C6C0000000000AA0AB8AB91183B9000920418002c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00E406028106\n\t006208456408014034010316006148110000000000000000FFC27680000000000000180188182200000000180080400164C0\n\t4C040600009600E40000201400405010E28C0000870040060000160961444B60504145044020070060000000000000000000\n\t00FFE37A800000084000001E0188100408008000980880201160020020050000060078000002040040280070860000060060\n\t0608000E016026106050014286200007006000000000000000000000FF3087800000082480401C09C01849C220E020980080\n\t01086802102004090816856418000214044000116416040026004006000006106104C160024040068028070060000000000000ac6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400060A05002\n\t8440043640E20000E02C00400000420424010E05611650800608604410E008000204520216434220000000000000000000FF\n\t073B0008200000000218018010081A595981180900800066A606621E20020610E0000060244044000060041000664260062C\n\t00060064060841000820040A00062A4010000000000000000000FF66E1000000000020001801821083903803805811000004\n\tE00600E0220100860460C040418415408800608664040620409E1001064860A400458010220420200600C200000000000000\n\t000000FF30C800000000020000180D8098418000A00358240A41086011300087000036B0620000A01440C200006A048C0096006c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFF484\n\t0000000000000000000010018000000840920000000000100040000000000000004004004000534006000010526040000000\n\t00000C240202000000204000000000000000000000000000FF18108000000000000000000CA09184000204800000000000B0\n\t0302800000000000002C80060064A00004880005408082880000000002801000280900301300001280000000000000000000\n\t00FF473A00000000000000181182104B80180380102200001160100080200000860061000061040140900071040000070064\n\t0600008600610844420210804C008086104080088000000000000000FFCC050000400000200218058099000218018438081500ec6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (56000556D564\n\t06556048444556555556556000000000000000000000FF080F0000000004000AA8AA88893288C8888349480000AAA22A32A1\n\t220002AA2AA0004AA2AA2AA4A000220200028A48202A0012AA2AA31213204B28220A02A2AA292000000000000000000000FF\n\t5FA102000000000020000000000000000002000800000000000200A800000100000000000000040000080000000080828000\n\t0000000110000200011001000800800000000000000000000000FF3C210000000000000AB8AA80482288A8AC90082100002A\n\tA20220200A0002AA2AA0000022AA2AA0021031220000020125020002AA2AA02200A0002263C04062AE242000000000000000001c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (011000001000\n\t0001000000880000200000000000000010000040000001000008000240008001000000000000000000000000000000FFF52A\n\t9000000000004AACAA8AA82A8C888888888080002AA26223A4220002AA2AA0003220AA4AA0002AB2AA0000422A20020012AB\n\t2AB0622AA0023A22AB2AA2AA2AA000000000000000000000FF83A80000000004004014010400000200400004050000804104\n\t00441000100500400000000000000043084800002104000000100500402040040104D0051050050000000000000000000000\n\t00FFCFB3000000000000155B55D558CD915935913B43800155650C484006001D575560014565561561095565560005175460009c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF55530000\n\t0000000000000000000000000008008400000000080001000000000000000000000000000108000000000000000008204000\n\t00000000000008000800088000000000000000000000FFBB050000000000000001000000000000080220000000800C109180\n\t00000020040000001200000000000400040040000840000000000400500010420400C00020400000000000000000000000FF\n\t4052120000000000200000000000044044000024000000000008030000100000000000820000048900080000054081028800\n\t0800000A80000008000000000800000000000000000000000000FF11F0000000000000000400200100000000024010000080005c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006208200216\n\t2820D82D82402182402000000000000000000000FF99CC004010105800145A01001041C01003C0110B800091601600611600\n\t042600600602120604600028E00600600600700600002620602680600005601600682608E000000000000000000000FF974F\n\t0020800010220000010010002010101650A90001025001014000400104004004000041410040000804084000080084000800\n\t004001000080800801000000000000000000000000000000FFCDB20020101028002A2800800820800804A00810800008A002\n\t00280A200482002002040822C2A02028200200200200200200000200204280280000A002002802002000000000000000000000dc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800004800000\n\t000000000804000000004800000000000000000000000001001000804004005000004000000000000000000000FF5C930000\n\t00000000000900800800800800800800A0004420021428020008020220020000028020000822020220020020220000020020\n\t02402128002002002002002000000000000000000000FF1FA20020800000220000100040440400000400C820010000008008\n\t00800800000000000000000000000000500000000100000000100200000800800000000000000000000000000000000000FF\n\t570E000000000800200808802C3A820800C00800800020341203280200006200200200000300200009B00220205A10200200003c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (174300000030\n\t1000001800C00900000801924051800002684600600600000680600E01000690400094612644600700610E00080600E02600\n\t648A92C104C05404004000000000000000000000FFDAE6000000001000001000800801800821000101800801610E00601400\n\t0006006006100016004000006206006006006006000004006088400002000000030014010000000000000000000000FF4299\n\t0000000000000000000000018000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF4079000000000000000200000201800001200000000000080000bc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02600A007410\n\t404504024804004000000000000000000000FF654E00000010180000080040010180020108092180000360B6006006000006\n\t00600E0800061060001424C6026006006096000006006110000088108000040004020000000000000000000000FF06460000\n\t0010110014184085084984083995111580001164060061D600040680602600800E02610000011630600400481610080400E1\n\t26206240804084B0C20E004000000000000000000000FF0A46000000001000001800800A10000811A2300980080060060061\n\t0E00000600604600000604600000200600600601E80600000400600400400002600600606604E000000000000000000000FF007c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060C00160060\n\t46000006006004006006106246106006200005C06000080224000000000004800000000000000000000000FFA75300000010\n\t18001418C0840A09882A01D129758100B2608480690600054E6063260008060261400001160062244E418720000621E10608\n\t618048440C00C807004000000000000000000000FF9641000000001900000880E10848420953402801800145610604E05401\n\t000600640F8003060A600000000602E00400601610000602600C0008101070960B7006006000000000000000000000FFE6F6\n\t0000002018000018000022800000A500080180800060170370060A814600609600148490602000200702E006A0400700000600fc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001800\n\t001801801801801809C81E01800010680681600E00000600600640000E00622104602600600408C006001046006006026220\n\t004004004004044020000000000000000000FFF1A20000004018000A1200A00800200805081851800088641602E006000006\n\t60600600002600A19C13618660600640400E0001060060870261181005E0500004020000000000000000000000FFF6770000\n\t00101800141880804803A00801450001800002F00604600400000E00600600004600E00120600688620400609620000E0465\n\t0E20600002C80C004004004000000000000000000000FF78A0000000001800001000804B00104801820001800000620E006000026040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060069800048\n\t0400C006004000000000000000000000FF650B0000000018000A1520000228689015819801800009E88A0070860000160060\n\t060000268060040070661074049B418600001EA06014604045146416506006006040000000000000000000FFE76D10000000\n\t1900000905C21903800A35C051058841006026B0E00E04804600F50604020C2B621100608E11644400580601100602600788\n\t6A40A94004084006204000000000000000000000FF48C00000001018000000000022040000018210318000046C1600700E00\n\t000600680620000C0062243170060068042040062000C6026204004480016806006006006000000000000000000000FF460600826040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000600680600\n\t0002000800800806006004806000000006006006806000804804004804006000000000000000000000FF88BA080000001080\n\t040A81801902201A00801801800000604600411600004600620600084280020400002610604408608000000D024804506044\n\t016006006006206000000000000000000000FFD5F8000000001800100A45841829889A4584590588208AE106504007048106\n\t016816040A0A44880800088E016404006001008006406806006200D04804094804006000000000000000000000FFD7DA0000\n\t00001800001801801A01801A11C31C01800002601207600500008600610E000006106001006006006004044007000006006000426040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00001808000C\n\t09A20828200212D40A098000006816A060362001060265264201068820840110464A6006007110008126015006A060000000\n\t00016000006000000000000000000000FFC05300000000180400084180580180000180480582001060060060860300062060\n\t16010012050400000016006104006400020416406416026140004104004004006000000000000000000000FF9D7500000000\n\t1000000801000000001800001801800000600600600600000600600600000200000400000600600400600000000400600400\n\t6000006006000006006000000000000000000000FF1E16000000401800000801800401801801401C0180010068060060060000c26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (604100600601\n\t6006006000000000000000000000FF6E13400000001820000801C0080181040E82109182000060812520E826050E7662AE2A\n\t004A4802800090262CE2840172C800812602EBEF027001004084014044006000000000000000000000FFEDA1000000001000\n\t001801800A00240000A143459540556CD000651040005700E306000516802434002355086536026100000228200A1000502D\n\t00000008000800E000000000000000000000FF4ABE200000001040041829000A018000008981038000096560016600008076\n\t006006100E0200000000278C01645C006000000A06046146006000004004004004006000000000000000000000FF0257000000226040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006000002\n\t004000000803806804006000001006006006004000004004004004006000000000000000000000FFFD2F0000000010140408\n\t01844051800000004033800001641401A00000010600600601092685200000220604684602E0000403B8600AA04069490000\n\t00096008006000000000000000000000FF37D8000000001800000A01800800600000A00001E800007224003C5022020622E0\n\t060010070024080000060A640600602000100600600200700000400400502400E000000000000000000000FF3F8C00000000\n\t1000000A01000000028004013109854154E0900220800000D6886306000D0A2000400021568060B400608000000100000C0000a26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180003580510\n\t8821901890804081800000685000688000000622624600012440600014600220640600600000043000028024440024002832\n\t0000026000000000000000000000FF20F70400002098002C0B2DA48A2C221B308C2281800080600080625021142700744600\n\t0AA48D68008D280AC8E826B16000080CB6806B16A36A28A14804A04924006000000000000000000000FF8E9F000000003800\n\t00980120080000980281184380008B6A1223608600009622600620801640600040282200650E026020001004824024004080\n\t0C602E0C0A0E0D6000000000000000000000FF8302000000001800000A01200801801800A01801800000600200600600000600626040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (900C50810810\n\t804000000000000000000000FFD88A020000008800080808800800800802800000800000260200200200840200200200000A\n\t05200040A40300204208210000004A04214A00A008022002002002002000000000000000000000FF2FFB0400000000000010\n\t0300000384010400A42200010A00000600001008600008000482403840002300081883A00210000800000200100302300840\n\t0400402C008000000000000000000000FF22EA0000000000000001B006404182800866040000010110003112280102000004\n\t00200000020000080020000000040020000000000000000100008000480380980000000000000000000000FFFE520000000000e26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04000A008109\n\t00D0C000804950880800000C40800CA0A00A0080094890891084C000000000000000000000FFEECC04000000180000190388\n\t10018A188D001801800000E0A408E48401004600640602000642E000024A060860C600600000040600608E40600010600600\n\t6016006000000000000000000000FFF9ED00000050080040AC08C22C24C00C208CC820800028220B422002101C0340382200\n\t10A310300150B0020034030C210000115302322303348904342B313083082000000000000000000000FF8646000000302000\n\t20820020020C2002603900400000508908C08D00200088C00020000880808800805001000808B08000000B80800C20C0088000126040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000404400500\n\t4A00002000000001000130001000000801000000001001009001001000001001000000001001001051351101111001109001\n\t010000000000000000000000FF131F00080008C0000840C00080AA0200480800AA00002A84202A80200002A82A82A80000B8\n\t200202400AA82A80000002A80000002A80000000A0200200010200680000000000000000000000FF3D6E000000000800204A\n\t10A02A00B00A20810A008001002D02803082800003002002800802922800822002802A02A4A80080088A8028129528008D28\n\t02C42842800000000000000000000000FF1F1F0000004420002482242C1200214305445201000080480D000A14000005004000926040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400002A8B800\n\t00000000000000000000FF78960008000000000000840B409002C49021040000000000408000880008000000000004800002\n\t820A00010000880090000004800000A0148142400220000040080000000000000000000000FF2F840000000AA0000820A010\n\t202A00A0AA2800AA00002A8200AA82A80002A82A82A80002A80A00002082A82A82A82A82A80002A82A848000000042008822\n\t02A8420000000000000000000000FFAF790000001500002C82102002443000021441540000D50890550A20800550D5055080\n\t0820D30800811550550A40B40550800848D50C08C00C008C8910CC0D08848000000000000000000000FFD84300080000000000526040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00641600000\n\t6006046026206406206006016006086000004006026086006000000000000000000000FFD9870000000000000842C0208210\n\t3100010512010001004140805004004005004000000800880900928804804800800004004800800810820890804948908804\n\t048000000000000000000000FFC3370000000000000288089448808048008048008000002802002002000802002000002002\n\t04200000200200200200200200200200250208A2000D2002442002002000000000000000000000FF23510000000AA0000500\n\t120500220200AA2D44AA00002A92082A82A80012A82A82A80002A86087003402A92A82A82AA2A80002A82A8020200410200600d26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (208008048208\n\t040A0000800000200220A02218601240248028240220A00001A00209A60340200200200240200200200000A0520020420020\n\t10000000040000000000FF22354008004000000824004200004804004004A400010216A10010010010090010004006A00210\n\t51001181110000001081201061448080001681014080111001000000000000000000000000FF9474400000420010002C00C0\n\t0840D00C20C84D0080015030234132431030131030001020C20C300101300320240200308310340300249200B14100208200\n\t3003002000000000000000000000FF9F760000000820000C1821845801821881821841804002C0860040060040060064A00200326040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400620418004\n\t0000000000000000FFA145000000040000001001009001881800001003802010008E40002600010E00630000620400600202\n\t610600610640E206006004416102046222000004004006084000000000000000000000FF2446000800000000000100010011\n\t8B00B000011200C04281100005500105000281000000002104300C04002A0000000008000000000400008228208280120280\n\t080000040000000000000000FF4657000000040008021001003021800120002004002029000000020000400010024004C004\n\t1040280000004400444002000802002204100900200000000A8100000000000000000000000000FFF1C70000000C2000000800b26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (116800036046\n\t0063120860060060360C6112036800056004504046004000000000000000000000FF27D40000000C20000010858499118019\n\t25801801800000615604E15600000600600000405640648028401600604025600600610441444450430008012E02E0960060\n\t00000000000000000000FF31490000000000000010098238A800B94180380180002460060064060000063060400060060262\n\t0050E02634E20300601600600400620A0160004003260262A6406008000000020000000000FFC15900080000000000110982\n\t38A404381400317181000900063E01161104060D60200060064360502064A600608600E20600600600E0EE0260100100141000726040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D8AB8C803308\n\t10AB80002A822628822E0002AE2AE2A800028E28A4008142462AE0A8C0E0060064860841242044004C60162060CF2AE00000\n\t0000000000000000FFB8A74000000000000A08010A3000042003003001800000000600800600000600600000020608648004\n\t60860060000A6006006B0648C080004001446236086047806000000000000000000000FF9F2F0000000000000AB821041022\n\t08C1080E10AB80002A83062003060002AE2AE2A8002244066100D042962AE002006006006216406416106120A06644104206\n\t2AC000000000000000000000FF820020000000800000180908300182200000B001800000000610000600000600600000210600f26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004000000000\n\t000000000000FFBF290000000AA0000810AB0910320880408818AB80002AE3062262060042AE2AE2A800207C2A7004084226\n\t2AE2AE0060060060860AE4A22AF000206304054206AAC000000000000000000000FFCDC40008000100000000551010018000\n\t0000B001800000000C0400070040060060000000060068000461060064060C600600604603400405402001408402C4060040\n\t00000000000000000000FFA4F3000000154000014155801944110090131155800055044E4C04CE0005565565500020864560\n\t04C8E45655655621600600703402603255650810C004404316554000000000000000000000FFA15B0000000A40000AA90180000a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040040060060\n\t1601600600608600C1081040200160C6006006006000000000000000000000FF73E800000000000004004590D81180582583\n\t380180001360841260060000060060001482B60060000AC0060064C654600600602E4C424424C0100240160AE00604E00000\n\t0000000000000000FF367C000000000000004001831888003821805801800000609600610E800006006000000006006C8400\n\t408600600654E00600600600421400409008412E02E096006000000000000000000000FFDF98000000000000031001805801\n\t8201148518018000006046116046004006006000000506016000C4C016006006806006006256404004004400056004504046008a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (111954151955\n\t80004461064465565505565560001100005560040C455255648E21655055005640650650401040E44E4C655644E000000000\n\t000000000000FF825680000000000000A001801909801800001801800000601610600600000600600008000008E000000000\n\t006116406000000006006006006020006006006006006000000000000000000000FF661400000000000008A0819219238898\n\t818818AB80002164202162AE2A82AE2AE0002400442AE0026042AE2AE0060062AE2AE6060040140040022863062162AE2860\n\t00000000000000000000FF9CC9000000000000000011801880021811801801800000621000E0060000060060000000060060004a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF63F30000000000000C00AB8AA0238880840AB8AB80002463462062AE0002AE2AE0002202A80060002AC2AE2AE2\n\t061462A82A82AE2AE4162AE0003262AE2AC2AE2AE000000000000000000000FFEFB200080000000000400185180004380000\n\t5801800008603608600600000600600020029000600600C0020060260A60000000860AE02602E0220C400400600608600000\n\t0000000000000000FF06030000000000000800AB8AB8238CB8B00AB8AB800030E20622E2AE2C82AE2AE0002282A82260002A\n\tC2A82AE24600E2A82A82AE2AE0A62AE00822C2AC2AE2AE2AE000000000000000000000FF32140000000000001500D380384C00ca6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (50015A621010\n\t680000018C85645E54614150700F006113006000000000000000000000FFC7F8000000000082402481802004000080001449\n\t82400C004080008620100000702000800B04600400482F046006006000000002406004000001815005805006806000000000\n\t000000000000FF459F000800000000020001000111804254001001800111002015000628000000600000880242E002804006\n\t006086547000000007006506006022005004004006006000000000000000000000FF4D4C00000000000000A0010000000200\n\t00001C0180000261160070060310070070000800001060040040068060360160000000060060360040101160060040060060002a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080052218801\n\t020100030006000810006200000002A0600008C3070965220060481401001060062003084865260442924460000000000000\n\t00000000FF4AB58200000000804000010140000000C000102180204080201402060004010068080500000261000941060060\n\t020860100000242064060520A128710700508B006000000000000000000000FF395582000000000000000100800004004004\n\t1001800101000002020600021102600000044241608010408200620000600800005000600600C00800609620600300600000\n\t0000000000000000FFF54D8008000000020020818000038202000015018001420001500806301009127010040B202060608100aa6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFB2480000000001000800018018D401184000502195404401000004060000A010640000001611400000425622608600\n\t6040120006006096016240004004024104006000000000000000000000FF98BF00000000000006000180188A1C7830001801\n\t82202060061860060000B600600000000E40440001402E12604200E01000000600608C404000004004006004006000000000\n\t000000000000FF66870000000000000800218A9821809880041919848010E20640630610000618606800011409C220004056\n\t60601800600000000605E06450E030014004686004006000000000000000000000FF7EE58000000001000002010000018200006a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AA00A142000\n\t0002A02AA10A10200020220A2023222AE000000000000000000000FF0F150000000000000000810241018200000000000000\n\t00800800000000000000000000042C0002804904240000040100000000100000201481200100001001100000000000000000\n\t00000000FFBB4080000000000000004C00000180000002C00000001200201300000000B00000000001001000000001080005\n\t205400000000000003002002081400A0028000000000000000000000000000FF1C9D0000000000000000210A980180190000\n\t1009800000840004800600000000602800000600002008608600E20E00E0000000820960240001084842A450440C2260000000ea6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5955800044C5\n\t044AD556000484D56000001446296000056C0E557C0621680000010755655611600055655655655655600000000000000000\n\t0000FFCE9E00000000000000002888A8328CC8000A8CAA8000222222232AAA00122A2AA00080128322250004A0022AA33200\n\tA00000022A2AA2122024C82A22A22C222A2AA000000000000000000000FFF33C000000000000400200220000040000000000\n\t00001000480000010000080000000000080405002000808001500A0000800254000000000548000000000800000000000000\n\t000000000000FFE84D0000000000000000008C882A88A8000800AA80003123923022AA0003022AA00000001222A000524102001a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF7F5D1000000000000000000200000200000000000000000140008800000000000000000888010282240020000800010000\n\t00022880000020000A000000000000000000000000000000000000FF60048100000000000000AA88882288C8000AAEAA8000\n\t2022022222AA00026B2AA000000322082002183A43AAA2020020000000022AA2AA4620022AA2AA2AA223AA80000000000000\n\t00000000FFEA208008000000002004844001000000000032010000004004004805000805004000800840888000004C308050\n\t00401001000084004020028000010010008800004000000000000000000000FF080B90000000000000055591594D91180015009a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020022020220\n\t2200280A082000002802802002000000000000000000000000FF50EB00000000000000000000020008010820208004000000\n\t0000020800000001000000000000002202080080000084080000000000000000004002084080000000000000000000000000\n\t0000FF8F250100000002000000000000401423760884100100288000001010C008200001A100040000000000038088000080\n\t1800000000800000001400208040040400000000000000000000000000FFF9BB010000000000000200004088004000000000\n\t0000150008100000000081000000000000240000008108000148540000000100000000108540000000000088000000000000005a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800100300204\n\tA00200206200216200200280200006011A0020020020028020A200308A0025D100A5C21C241A000000000000000000000000\n\tFFF741140104000441801809021001A01523033C8D828001640600720500522600E024406204026002020006004006046206\n\t80700600600E00704100C026006006000000000000000000000000FF170E0024000000010010014012001050111010000000\n\t700018424994004004104104200004000040000510105800000000860845001000100828C442000000000000000000000000\n\t00000000FF4B91140302000020800810C40800800800A40C12810000220A20208200240208200240220282200000080A002000da6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF61\n\t1E00000000000000000000000180020020020100008008008000000000000000000040040040000008000000050000010000\n\t00000800001000801000000004000000000000000000000000FFC5C5000000000000A10A00800800C8088882008C81000020\n\t0200008A20200200200280220200300000000200200200280200200200211200200000A00200200200000000000000000000\n\t0000FF8FBE004000000000200200000040004000200000000020001081100400000000000020000400080000080000400080\n\t0000020140000000000000004800000000000000000000000000000000FFD3D501000000000080880080081885AC449B8882003a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00600610600\n\t4006804042A18004004000000000000000000000000000FF2B15000000000001801804820C10000044000001884090410404\n\t6D4C80804E10610010E04102E4C00008483240060C6A07006006426ACE50708810004400400C000000000000000000000000\n\tFFCB09000000000001801800800821808080044001810000421410E00400000600600000600010600010008000401600E006\n\t006206004006054400202004004000000000000000000000000000FF42990000000000000000000000018000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D04086086812\n\tA42106006400006080A02000000006006002404A0E40408602682E00602802C086007004000000000000000000000000FFF2\n\t64000000000001801804000011810922A0040188C0804C2E096AC200A0460A60800060200D22A000011612608A0064060065\n\t0642632E1172D0884026006016000000000000000000000000FF71BB00000030001184180080080190304112B81180000844\n\tD607654C01400E01603614600001404008006080600080404481400600410422410050000440410400000000000000000000\n\t0000FF4AC1000000200001801C00820820005001211A61800060404600600400400604604608E002006002000000A061628A007a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF0E8B00\n\t000000000188180080080A08400801000382400C600600435600A00780620000600090202422048E20A00620600620620600\n\t4006004000104104004000000000000000000000000000FF60750000001000018C38208028A1A50840C61C01000083C45604\n\t70020C20260A608010E0680802802202CEBAE06002441400430E0860440A6010814626806904800000000000000000000000\n\tFF3A280000000000098038420346A0000800901D11800020688611600228392612E108036090A08280000007046000046044\n\t01601612608C1470A0224047206007000000000000000000000000FFBDAE000000000001801A04828A0C432808808103822000fa6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00508609602C\n\t3072A044C02C004000000000000000000000000000FF2784000000000201801801801821801C01A00111800084408614C487\n\t04600600782600620000000A03080608220611400408480610E02408680A004006006084000000000000000000000000FFC7\n\tF2000000002001851810840830059959994049800002600E8042A600700600600610E05808200420000E0031060CC0060042\n\t06006586046040814016006006000000000000000000000000FFE7EE000000002001801800800801802000400001800028C4\n\t1240404610208600600000E0000A000450101600200E00600400650600600D406B054240440040040000800000000000000000066040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (029060260160\n\t0700600600700000000010000600200610400400440600600400602400C006006004000000000000000000000000FF48C600\n\t0000000001E3189986083800D943A1184B8000A3288280600612710600600630604008000C0402262A220606520C18420E00\n\t6404046090A04006006106000100000000000000000000FF4C8310001000000580384000920380155100590185200108522C\n\t701700E4160060060160014100040A000780A047C8488440C00600603420E211124024114004000000000000000000000000\n\tFF4828000000000401C218000000004410014059018000D022864AF00602700600602600620084000810880608229600400400866040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF5E8A000001\n\t800001801C01401801801C018010008000006806006006806007006800004002004805002007006006006006806806806804\n\t806001006004004004000000000000000000000000FF23D1080049800403801800801A04005813C0180280A048622E20684A\n\t006A0600600000680008400402040602684602640E20600E00400C415020406046106006000000000000000000000000FF87\n\tA4000001800201C258C9831A29809B41825D08840105608704680684600E00680020E00040C80C800046B0E40620610690E8\n\t06806824806B1415600400C006000000000000000000000000FF6488000020000001801C01D81B81A03801821C018000080A00466040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AE12E8240060\n\t85006004004004000000000000000000000000FF61CE008001800003801A00801040040002A01804804094EC060169025462\n\t0E04E01014E52A116048481047026C565470A62CF4068044068040A000E000806006000000000000000000000000FF1ABC04\n\t000180000180392180100588208882580080004060060A620601608620610020600044400402040630E00600601600614E45\n\t614C086400406004004006000000000000000000000000FFECD1000001800001801800001800001801801000800000600600\n\t600600600600600000600200400000200600600600600600600600600400600000600600000400000000000000000000000000c66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (184A03612602\n\t420003684650402000000E48622E4A62AE006006884004820201806006006006000000000000000000000000FF8309400001\n\t800001821C0280180180001320483082007018300C004608728E03C0882CE2A622C038080AB792E26E2E65F70AF20638628C\n\t0C762004E044004006000000000000000000000000FF9A400000018000018018008012000002001306259500050440300493\n\t0571462244400165565162C402080640641650680600600620000E201008006080800004000000000000000000000000FFAB\n\t772000018000018438249812018022000221D9840000825062021E00E066204060024806804004038106006006006006806000266040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A0000018000\n\t01801800A0180180180180100000008060028020060060060068000000060040000000060060060060060078060060040068\n\t00006004004004000000000000000000000000FF13F6050001800405801900001045940110000A0580C0BC08152149824460\n\t0600480000601610E800422006506006806016C0600620080E2048034060A0006006000000000000000000000000FF6F3C00\n\t0001800001801800801000000608020C4A800000020404440700700641402000431600728800280680600700600700600600\n\t3006006008026004004006000000000000000000000000FFAD860000018004018018000018000000013128018C000500480800a66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000021000\n\t0000100000000000000000000000000000FF11DA0000018000018819429050018098001080498000D0082022000800680600\n\t400000660612604000610640E00602602650E106480066080000244010000534000000000000000000000000FFD457040201\n\t800201C8BB50889200201A404A034B8000208541020D0700E026824008A0CA2E806800A0494688E826D06D26CAEA0E886C46\n\t906A80826C84814804000000000000000000000000FF0F9D000001800011801802A018200D5913A15001800114600A41202B\n\t906A1608E1000020870CE0A808220E00721604600E00604620500620800848E00E0C0154000000000000000000000000FF5800666040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (088028420000\n\tA48810C00800200800800A00A00B80A80808A50800B50808830840880800000000000000000000000000FF51F60000018004\n\t08808828800000800AA8000910000000204200200010200280000040208200200010221A00210A1820020420021021120020\n\tC040A00202A002000000000000000000000000FF34E40000000001041000000000019C415040002400002A00010080A08512\n\t0108100000610C0840B849402018006040005802002000060040810018078C404088000000000000000000000000FF083500\n\t00000000000420806000218200060B008000010012905400404011500184880000600481020000800000000000000002000000e66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000100000140\n\t124530129045443500B2CB0000C0480C88C80480C0040040D08008008B08000009090908209408408488048C088083080889\n\t08B0890CC0000000000000000000000000FFA3E00000018000038018810838018A394B82102D80000840AC00453612680E80\n\tE400046006506100206006306106106126046106006006416000436046006106000000000000000000000000FF3FAA000400\n\t800320D20C40808D40C00800F10D00800040A2035430034121422028014032B302305110B10B0030234030135030034B34D3\n\t0A3151083313503412000000000000000000000000FFAB340200000004402002002983402022000422030000818D08000F1400166040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C50850900C50\n\tC90940000000000000000000000000FF07EF0008000000004000204104004000344404000000011009001001000001000041\n\t000001001011001111001011001001001001001001001049101001001008000000000000000000000000FF408E0008000000\n\tAA0AA0001100220840802B004000000C0A402202202202A8AA82002A80000000000002202002800000000102A80502000800\n\t00000200200010000000000000000000000000FF6B53000000800400A00A90A4AA00A00C00800A0080008320A280290A9028\n\t02002000802D52C02A00002802822812A12B12B02802C0A84AC02A40A4280284280A000000000000000000000000FF70560000966040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A82A9B002A82\n\tA82200080002222B23C22AA2AA2AA2A82A82A82A80082202A82A8000000000000000000000000000FF826400080000000040\n\t040200200040004202210C00012810010080008008010000000002C80404000000080A028020023022000040029010020043\n\t0100020400000000000000000000000000FF58120000000000AA0AA00A0821320840800820AA00002204802A82A0220AA82A\n\t82082A82A83284000002202A02002A82A82A82A82A82A82A80802282A82A84A0000000000000000000000000FFEE30000000\n\t0003541540D02402D41303085002000000010510540D484D0550550548D50800D10800000D40C08848930880880D5088082000566040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000023801809\n\t8118A180B80900188104000060140064461060040860100860060162000A000600E00602632620600642612E246410004006\n\t016006000000000000000000000000FF5D8A00000000020140134928820044924140520100009148A500480514C805004100\n\t8000008908008008108008408008008008008008008008A090C800800CC0000000000000000000000000FFD2050000000000\n\t0080080480490080480C84880080000020020020920020020020500020020022000001020120120020020020020020020020\n\t0000200200200A000000000000000000000000FF09180000000004AA0AA50006002A0D04800900AA00013202482A8230310200d66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (081080044C40\n\t00000000000000000000000000FF1B3D00000000000280080880C8A088800080000980000A248200220009000200201800A0\n\t0211A140001222942E828828829423A220A04210225015240211A052000000000000000000000000FF2085400C0000040044\n\t040042000450040040041000016116010810050010010092600010A008100100000110800000000000140000020009102110\n\t4000000000000000000000000000000000FF07FA400400024400D00C00C40800C00C00C00C00904114310308300300B00300\n\tB30000B4B21030130002230022820820020131420924020830C300A002522002000000000000000000000000FF793A00000000366040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000601006\n\t400000011600609E3FE01E206112006206066000402184014004408000000000000000000000FF630F000000000001803801\n\t809085801148001003914021640804E20401401000E000006000214000000406206086206006206002006404006450000020\n\t080004010000000000000000000000FF5FB700080000000000400801010188001002014200A05081300102300402C0130000\n\t0880102002004A0288200000000000000208000008000400200048000000200000000000000000000000FFC9EF0000000440\n\t200C00000010038020080001010A2001001000004000800010010010620C0004080C0000100000020220408000140148448100b66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018818310\n\t09821002801109800004600C14608400400200E00052680600680040842600E00E02E2AE0060060D61440B68210862C60000\n\t06000000000000000000000000FF07B300000000000180184580588180182103382380000960C200E42000600412600000E4\n\tAE52800002011644644640600610600200400E00420045200C2A4094000000000000000000000000FFE57600000000000180\n\t180980383000380104988100000A60C20060400063440460081160040843403410071272070070070A64020060360860000A\n\tA20800602C000000000000000000000000FF2F7600080000000180180186182A1630A00090418E000260006261946440081000766040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (604848055400\n\t0000000000000000000000FF1AC30000AA0000AB8AB8218818238890A088B2A380002C62202472122AC2AE2260004860A610\n\t3040A002064061060160068862AE0840960A425022E024204286000000000000000000000000FF444E4000000000018018B3\n\t80108802300882B04B8000086020026AAA0040060060000070260020000880069061060361060A60064840040C4008006206\n\t006006000000000000000000000000FFE46F0000AA0000AB8AB80D8811220CF088881201800021630430600C2AC2AA306000\n\t0060060460201D00461D608618604622E2AE61660621600800640400C226000000000000000000000000FFBB84200000000000f66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (106006002000\n\t00800E0860868860860060044840062840000062C4004006000000000000000000000000FF60BC0002AA0000AB8AB8098AB0\n\t2A08988188180380002062A63060222AE2AA2AE0002362362AF000A80017C260664068064862AC0262AE0170412AE1060582\n\tAE000000000000000000000000FFEC12000A00000001801891855011801012041009800000600801612000400201600004E4\n\t0C21200000088F00742EC2730E45600402404640400010609412C04C000000000000000000000000FFDE4500015400015595\n\t5801955844111144101281800045649041700455455255600052650455601444054603621608643601655402E55420610055000e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180980000\n\t180180380180000060060060220560060060000062160020040000164160964060061060060140C610401000625601600600\n\t0000000000000000000000FFA49F00000000000180180194589182B8290298AB80000060AE00601610608E00600000614611\n\t22800002A602642604E44E44E0864A40064241202C6104324094000000000000000000000000FFFF82000000000001801821\n\t80190000180B04982180000360160CE88E00600600600000E08E0028080212A6216A0E25642EA360060140060340B0006008\n\t2A6004000000000000000000000000FF3E68000000000001801905801801823841805B118000086006006202006002006000008e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20C2AC000000\n\t000000000000000000FF4EDF0000000001559559558418CC11591390381180005564565564C640E556556007556110546506\n\t0025560160160560565564CE4540485040D0046156496526000000000000000000000000FF8F258000000000018018018019\n\t01801841801801800000608600600E00614600600600600040E0000020060060060060060061060040040040800160061060\n\t04000000000000000000000000FF2A180000000000AB8AB8AB91582388188388180180002AE2062AE2822062262AE0002AE4\n\t0622206000000618600608608600622E00470E04C20001E004004236000000000000000000000000FFE53B00000000000180004e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (508860100020\n\t1649608640600610601600600200600800C254016006000000000000000000000000FF116C0000000000AB8AB8AB8AA0238A\n\tB8900AB8AB80002AE2062AE00E2AC2862AE0072AE20004E0000020065061464861860062262AC2AC2AC0202245040462AC00\n\t0000000000000000000000FFA7BB00080000000180180180180002102183112380000060860060160A600600600600604000\n\tE0000020062464A630648600600610400400C400286206024000000000000000000000000000FF05B40000000000AB8AB8AB\n\t8AB82B8AB0838AB0AB80002AE22E2AE2A62AE20E2AE0062AE2A81062880022CE04E40E12E42E2AE22E2AC2AC2AC4502A602E00ce6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (880001962801\n\t800C010100046206404206006801006008886A8090000002200E64700624E2060074065047D442400008E206007004000000\n\t000000000000000000FFBF28000400000601A0180591000000A000000001800028640401404610400088E208447001026005\n\t002006006C060064460078B60260020C600001500D004000000000000000000000000000FF4C050008000000018018018001\n\t0180002400000180000060160044C60040100060008071002262800022C602642E04E44E44E0860040040044840840843250\n\t04000000000000000000000000FFE89E000000000001801801800010001810001C0180000060C60060060050260060060060002e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000000000\n\t00000000000000FFA7C380000800000190180194011181080014288D008021640E2AC1560AE10000624000E1004021010022\n\t0624611610600600700E00600A20608012C44C406136100100000000000000000000FF900C80040000022180380181000408\n\t880C000801008053600648408E0471200062802268015020000020060462060C602600E04E3160560960A802500500600400\n\t0000000000000000000000FFEEE0800000040041E05801800042000813800801000001608610448F8270C000610188652020\n\t800002200E00600630E00E08E00600C00000C128326406006006000000000000000000000000FF4D6A800800100581C0190100ae6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (641000400E02\n\t610610620E00600E00600200608008022C2040C8080080000000000000000000FFDDAF000000000001081801905890002050\n\t102009820008648E0041021560C040E40000E00000612021424610603602600600620610600608E000400104104004000000\n\t000000000000000000FFAAEC0000000000010018018018040630A980114183000860C604624000602600E006806000002028\n\t20800E40602600600600600600601248E618052086004000000000000000000000000000FF9F910000001400010019058038\n\t4388100180102188200261260160401060063160060062600F820000002608600602621E1067060C40044040006020160840006e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (328A08800C08\n\t8880002AA5622C02042202122AA2422AA00040218222C0024821424821820022AA0020020022083122422020020000000000\n\t00000000000000FF20E500000000002000000000010980002A04004400000001080400280100000000480060003140001000\n\t10410090400000100000100010080000048000040054000000000000000000000000FF032C80000000000000000000400180\n\tC00000A00000000004000081000801280000818000000202400002C00204200482484280004484A02280401000C809048000\n\t0000000000000000000000FFA329000008000001001801821801890100020003904044E00651440A0060000060210062C02B00ee6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF252F800000000355F5595591194590511390D1558001D56556D5654E55643555640C55600150621045655601\n\t60160560565565565560565562204CC556D57156000000000000000000000000FF61960000000000C88AA8AA8CA822888880\n\t88ACAA80002AA00220A22A2AA2A2AAA202AAA0000820002A22CA04A40A12A22A2AA2AA2AA28A20A0202232823224AA000000\n\t000000000000000000FFBB360080000000000002004440000280200000000000000000000000000080000080001000040080\n\t0800002404A0300480000000000280000010004000000400000000000000000000000000FF825600000000008E0AA8AA8A88001e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0002A0020420\n\t048448428000000210000030100000000480000000000000000000000000FF82A80000000000000000000001000100000000\n\t0000000000000001100000100000000000009300000300104100904000001000000000A00000000000000008500000000000\n\t00000000000000FF6C599000000000AA8AACAA8A883A8808A08C08AA80002AA2AA2AA2222AA2022AA24BAAA0002120802820\n\t02182002082082003AAA2AA0022AA20022A2AA2AA002000000000000000000000000FF4B2280080000040140140140010002\n\t304D001400000100401108410400400480409480100004844001400008000000000000000400004012020800501101000000009e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080084084080\n\t80A0220200228308210308000200000240200000000802220240A80200208280280280200080200280200200000000000000\n\t0000000000FF3EA200008000000000000002000000868208A6121400020088440000C50000C00200020000080200000000C0\n\t0100000000000040800800000000400000000000000000000000000000000000FF47D50100000000000000A0000000004148\n\t04050400000D9100008000000000000400050000031000000010800000000000000800010228220800000040000000000000\n\t000000000000000000FFCCAD10800000000040020000200004401202C0000001000000000000000120800120000000000210005e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF6B8C010000002000800800980812A2084AB42840822041266266AA22602062001182010002802000000010002003\n\t80200200200200200280306000305B01A01A000000000000000000000000FFC4070001100500018018B18218018098030350\n\t090B0149700E2268042AE1063000040200064A6000000010A474864160060060460062262270010060060060060000000000\n\t00000000000000FF060B0000000000AA0010000010282001113810650080244D04014D0400420C0004040000008004000000\n\t00080800801000001100000010000200400205004000000000000000000000000000FF94D40000080280008008108008008000de6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000002000000000000000000000000000000000000FF874100000000000100000100000180000000040000\n\t0000100000000000000000000000000480500080000080000400500400400000000000080080080100080000000000000000\n\t0000000000FFDEB4000000000000800800800220804A82C00882044002210100C04000000200020200000200200000000010\n\t2002802002002002002002002000002402002002000000000000000000000000FF73AC0000000040B4000000000204040210\n\t2040010100000004801404000210001000020000808000800000000000000800000000008000000400800000000800000000003e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (389011800004\n\t648284619E00600600000400000600640000004000680204240200240203E006806800004006906006000000000000000000\n\t000000FFD025000000000000801B0580520002181200008000000070C220400688C10614008002009714E0000000000C604F\n\t30612714701288680608E2A8012026006004000000000000000000000000FF0DF402000000008180180100110180580004A0\n\t00000050E00200C4060040464000000000064060000100002061060060064060020265564060004800060060040000000000\n\t00000000000000FF7D6E0000000000000000000000018000000000000000000000000000000000000000000000000000000000be6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFA19C020000000040901801021048510080C00C2582804062120120848040060082000302061460000002000060C02000\n\t0209280620E006286532217007006004000000000000000000000000FFB40A020000000100801805401081802000C0291180\n\t01296022A3680410C1262200800201060162000000200860AA2022C20C200610600609635030C02608600400000000000000\n\t0000000000FF650A0000000000008018818118018618191615118001036B424462461060460C010600014EEA600040904022\n\t40028A2450E0020A0063EE216000002116106406000000000000000000000000FF2DDA000000200001801801A03800001803007e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (500E01620600\n\t614D009131001412016807806004000000000000000000000000FF6170020000000021801801821050100000002130000004\n\t6806404100014006010100008426086000000010046006046086006004400000001888000006006084000000000000000000\n\t000000FFDA8C00000000000080786380180384612090AA0181214A70421C224400E246800802180006046002800008024140\n\t020080510006016846006400016006106086180000000000000000000000FFB757000000000000881803009E022100308488\n\t03822108E28A01240408620702120202010620600120024000400020023000000600708630E02240408E006406000000000000fe6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3002000B6812\n\t20400300700720000400000680630020008013412E0962460061060AE40E00620A0040960060060000000000000000000000\n\t00FFE6EA000000000000E01821825201800005801E0180001560058020000A4806A0000700000642600021008000C4060C68\n\t2600600400020002084000608E106004000000000000000000000000FF51D8000000000000801C01211004006401811C5180\n\t0080701500230020400608080600000600650480804010634642681F40602474008070192100E64688600400000000000000\n\t0000000000FFB821000000400021801C0100140982000020040002000064C7C00C002040060800000000060060000810000400016040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t20A6000000200002811801A01809801801981807800040E40220300200600600118E00000620200000088026402608748600\n\t710602E006006010806006006006000000000000000000000000FFF57C0000000802408098018DB8040C18058038A0002122\n\t754200010B9660060010060000074420041000410848064060064060168060469461080042C7806086000000000000000000\n\t000000FF4DCC000000204440841831821841C53C1143101180000864D2042522316006080045050086042001310808804406\n\t006206086086086286246080926026107806040000000000000000000000FFCA7F000000000200801841803A08201A01211000816040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006006006\n\t006004004000006004006000000000000000000000000000FFEED10000000000018000010010018018018018018000006804\n\t8070000060060068060000068000000000008070060060068060060060048050008068040060000000000000000000000000\n\t00FF2C69000000100001800001801800025801A5182100001060840064812468060060060100060000040000000864060068\n\t86006806886004404104086506086080040000000000000000000000FFCE680000000044258404498CD829891C11A03C9100\n\t4002E034446050116806086034040106A20000310088A060461060061060060562840240000448270060000000000000000000416040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000086406660\n\t4208202608618E0408060024000000008064064068069866A496C004004000006004006800000000000000000000000000FF\n\t9622080000100081801004A01A00300500412801800004900B00F48220604610E85648831755201400010014F03614E42E00\n\tE02C00400E08EA05004006006000000000000000000000000000FFA5C0000000002011801000801801802042080843800050\n\t00820860020CE406206206000006002000100008406106006106406104014024004000106006006000000000000000000000\n\t000000FF50A7000000000001800001001000001801801801800000600400600000600600600600000600000400000000600600c16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF2847\n\t000000000041C00801A00800002040003801824108685208600000202610E08612820613424001000008E006096026840006\n\t0260042A4828007006006000000000000000000000000000FF7B6F000000000041880809800E01880000103801800002690A\n\t09EAA022A54624E44689828E0847080800C000E00E0AE28E24000F0C602C5CC4501064060060000000000000000000000000\n\t00FF82810000000002018000000000000042402041058440110050D26B5248200E11690614044695204411000010E8065160\n\t46406004004006006000806004006800000000000000000000000000FF0EAC0000000002019040120400118020A20602138000216040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0644A0020222\n\t260260480A6C0400E400000000000000000000000000FFE600000000000601801001201001801801A00E0180000060028060\n\t00005806006006000006006000000000006006006006000002002004804000006004006000000000000000000000000000FF\n\tAD4E100000104111805800C408118000001118518000D0014200E200002406006C46440006C56000800830546546C0604601\n\t2006806006806400186006006000000800000000000000000000FFBE07000000000001801800800A00000000080885800000\n\t808242615048230E02722680002700608108100000600740600640380700600600640000420600600000100000000000000000a16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020800028008\n\t00800001800000902300004004400E02806402180102A00000004400980E0000120000000000000000000000000000FF86BA\n\t02000008024180110220000D801911808881800000000004680400052E406206008006C0640000000000E026006006046002\n\t00200620620000401400E200000000000000000000000000FF4A9E020000100021A8D28002424A351A01AAAAA38000801000\n\t884040AC1157046B26408B064268000402808468A6906836806AA2C82886A86B00A06904A260280000000000000000000000\n\t00FF8535000000000081A21013091100401955A00C01800034EC4A84ED0000C2060060020010061160C840000108E20E20F200616040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFE0DB0000\n\t000042A05082000C026033C0041C020400000001001310000008100210402008409C4848030200800808980800808800BC0A\n\t00800800800880800800000000000000000000000000FF9AED0000000000008E6888C3C802840840810902800000802608A4\n\t26B0A00200240200000280A180000080002002002002002002402022022000302042002000000000000000000000000000FF\n\tE65900000000010000100040008180048A42002000014A144140001146020000002040020600002024000010010000816032\n\t41400204C0180460400300200028000000000000000000000000FFA6F300000000040000005010200188002000205000013500e16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (280A80280280\n\t28408D2802802040000000000000000000000000FF137F00000000020120022C02530024021420440C0000804084AC801488\n\t5004004900000800804800000000800808A00890890900910910908808C00800804808000000000000000000000000FF8F47\n\t00000000400182584183100194380980982D800050E0C430600402440E4060862000160D4140000040106006506036126086\n\t546206086010046016006000000000000000000000000000FF41C0000000000140C80D08A84C44C10D42D40C808000023C03\n\t02BC0A303103003242001042203200450201023083023103013043003023243241503143102000000000000000000000000000116040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D08D50C00D50\n\t800C50800D50D50810800800880A00890800D28CC0CD0C50CD0850C00D50D50420000000000000000000000000FFA9C80008\n\t0020040000040040040000000041442000008010014910000000000000D10010015090010000010010491010090111011010\n\t01101011011001001000000000000000000000000000FFBEFE0008000000AA0AA08008402208A2E00A806000002A82000402\n\t202102A80008000002A82A80000000000002104402100002202202202200000002A82A8280000000000000000000000000FF\n\t45FE000000000200A00A00A10A10A00800A00B00800000285280290282B003002452800802802810800800B2A9428D2822C400916040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (765700000000\n\t001C6AA0AA0AA03248848008002000012A82200882A12A92A80002200002A82000000000002AA38220234220022022032022\n\t00202402A82A82A8000000000000000000000000FF85320008000000000000A0000080004004020000000080000000000012\n\t00000000800000000000000000002281400004A00000080000800000000C8000000088000000000000000000000000FFBFE1\n\t0000000000C00AA0AA0AA0A20AA0B20A008A00002A82A80202A82A82A80002000002A80200100000002A82002482002C0228\n\t2282282300404802A82A82A8000000000000000000000000FF14E400000040055435421234825435051030C30C0000550D5000516040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002482503000\n\t003003002000000000000000000000000000FFE7D51000000018018218258098018819018319018140044056246026004006\n\t28600608600600E0400062860060060061060060A640602E00E540006006006000000000000000000000000000FF97720000\n\t0000140500020120020024424302A28500008048048408108048040041150008008008008000048008288208B08B09089009\n\t00900808828800800800000000000000000000000000FF7191000000000920800800800908800810A0081080000021124020\n\t0200200200200200200213201000200200200211200200200201201200A000102002002000000000000000000000000000FF00d16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (005040001000\n\t00108046010020004280400100040000200040200428508000000004000000000000000000000000000000FF7C7A0A000000\n\t200082082010880288080213090700201220300020020122021020020120122420004020009A2C02B02AAA18208A50211200\n\t26800AA402402010000000000000000000000000FF624F44080040040440040240000C40044C400424000120960D0A102140\n\t1401201201000001001000001004040000400050000010000080001020151001000000000000000000000000000000FF5BEE\n\t400000404C20C04C00C00808C30C10C00C40900140B10308300310300300320301202340300000300248210204220250200200316040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000804001001\n\t9C192701184406B8C0007041844000808600201462040600600600400600401000002641645E606006106042002406006020\n\t16605C004000010000000000000000000000FF0AB60000000010018030410C10098918020A908800800A000E002084006126\n\t40E00E00400600408020000600600600602600600200200600644000C080504000000000000000000000000000FF80FB0008\n\t0400008002208004803590004202005005200400002D01500003402100080400800001080000002080400080204080400004\n\t20000100108120120020010000200000000000000000FF14520000000000240020000010018280C00081001080000080400000b16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (160160087142\n\t8C2AC000000000000000000000000000FF125520000000180180480200100980000402080180000CA0840AC08E1040060060\n\t0600200611680000080600620602E086106006006006106800006006004000000000000000000000000000FF78D700000000\n\t1001821809033901841821813831800000404E40200600800600630E00400604450000000222E0CE40645602C10210A0CC24\n\tC48014E044006000000000000000000000000000FF1DE7000000001081801801001800003881801803800000C10653204602\n\t800608600604C08E02400000004708700709700620E0022820CE006100006200046028000000400000000000000000FF428400716040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (455655641700\n\t65565564040020044060362060364164D44D4556556010556550554000000000000000000000000000FF25C10000000018AB\n\t8AB89508B8A38A80AB0C5881800022222D20EAA622C2AE2AE0860022AE32E28000000321608610645612C236226104084500\n\t0263042AE000000000000000000000000000FF53BD4000000018018028050010000000010138018000002005006046054006\n\t0060C68020060061000010020B6286036286146006006004004280006006006000000000000000000000000000FF9DE90000\n\t000018AB8898A008102208E088090AC78000212A04804A362242AE2AE0260022AEA060000000061C601649600660422E226200f16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018018218\n\t03845901A00000891A01800010690E806C4E04E0060064460060040064800000000860860860861040040040040042100060\n\t04004000000000000000000000000000FFF7890000000018AB8830B109102208C08C8018AA80002662262AE1862062AE2AE0\n\t060062AD2A30040000040260261060262042242242AE2AF0842AC2AE2AC000000000000000000000000000FF077500080000\n\t1801801821021011C00000001C0980000810820C2006104006006436006006006800002000006A2682688600610410C24444\n\t4010006054004000000000000000000000000000FF2EFD00000000195593112114594C150150121D54800048954A552A0E5000096040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400008C20421\n\tE000000000000000000000000000FF25C100000000180180D102121800041801823820800000608E02400612400600600610\n\t6046006084040102096096016006004006016004504404246016146000000000000000000000000000FFCF7A000000003801\n\t84082980B88980384B811901800013400601205640C00600600600608611620211000A42644644625612411610654C054088\n\t006124006000000000000000000000000000FF40EC0000000018018080080118100458258258008000014006002006104006\n\t00608E006006016804000002C1721723720E02C11610E004004000006000006000000000000000000000000000FF3914000000896040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A82A82262AE\n\t48E4002A809020E10E22602E2AC22E22E2AC2AC3002AE0AC2AC004000000000000000000000000FFA79D0000001141558058\n\t0C92284C15592990580900004564524064A61165565505504C6D2E4564065525504360364CE45600C4D64D64345245022461\n\t56406006000000000000000000000000FFC88C80000000000188180180180100580182982580000560020560040260060000\n\t00016006006000000040046046116006004106106004004008006004004004000000000000000000000000FF98F30000000E\n\t98AB88180180182388988188180B80002062262942960442AE2AE2AE22E20E32600020022200600608608630C2262260040000496040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0201821C2080\n\t080104000182880B800011600600600612600600000001400400620400242001609601700600400400400600608000601000\n\t6000000000000000000000000000FFE81E0000000AA0AB8558498AB82308808188080180002263062062AE4062AE2A82A832\n\t4AAC2461002A84001064060865862AC2242242AC2AC0082AE6042AC004000000000000000000000000FFB7E7000800000001\n\t8A98C00101000018030498A380000860840A600620600600000000E00600608400200010630600608644400600610400C008\n\t08E206120006000000000000000000000000FF0E730000000AA0AB8018950AB0AB0A98AB083891800028622E3062AE08E2AE00c96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006106006\n\t000000000000000000000000FFEB2D800800180481C11C048008010218A48A30099000A26036006002006802500400046806\n\tB0E0000040102A70469868C700400602E0040E4040106845404004000000000000000000000000FFFE73000000000401E058\n\t00800801120000000003800044642600E0060070020400000840064120240020004468862062078862AC4040060062082040\n\t01800000000000000000000000000000FF313800080000000191390280088900404A00214180008060D60B600640E8020000\n\t000850068CE0800021104A6446C4645600610C114004004200007124004004000000000000000000000000FF44260000000000296040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (005060060260\n\t4000404002614648600600C01200200C084538404004024004000000000000000000000000FF1414800000000441A0190415\n\t0081085810848093880000600608608211641214814004E08600E2C210601000632602628E04600644E0060061020CE21108\n\t6140000100100000000000000000FF6EDD80000000000180380280C8010918008000019100016516056002106822CA020002\n\t700610600000408800600600E22E8A4546406056006020086044504004000000000000000000000000FF4C6E800000000101\n\t801800014001009940943009808000E08622600210604300000040700600600000614008600601608E02600604E02C10408000a96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (803900810843\n\t001800004081820010600600E0A602E4800B00A002710601402080600004622610600E00600222A01600615000C400140120\n\t000100080000000000000000FF2FB800010000000180180494481108D80800802D814000E006142406086020000000016006\n\t04440010400800610E046486256002002006106000046114004004100000000000000000000000FF7CFC0000800000018038\n\t008009010699E504182190A004E44600400600601400000000680600610000600000600E0060062060020020060060001040\n\t86000006080000000000000000000000FF7C8200000000000181180080282B00180700380582000A622642C2260260A4000000696040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004802000000\n\t00000000000000000000FFD8780000000000AA8AA8408248AA88D08088807080002AA0422007022AA2220000002202622520\n\t008020001024020821C2202222222002002008402602102402000000000000000000000000FF1ED300000000000000013000\n\t000100002800008300000000801280C80000000000000000060084000460000100900100001000100000004002A000801451\n\t4004000000000000000000000000FF94DF80000000000000000208A001822004044008000000023000000000008800000010\n\t99081201003100004A04404402500281001085500D0000340140020530000000000000000000000000FF5E0500000000004100e96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (500000000100\n\t00000400401100000001001000C0040110011080000100000000000000000000000000FF565E800000000555D5580D005055\n\t95112915195500015565344A44465564448000005575560165015460004360364CE0165564CE4C65565562105570560570D6\n\t000000000000000000000000FFF0C90000000000AA8AA88C8D08AA8A88C488280080002AA5022AA02A2AA2AA00000032A30A\n\t2823002AA00020A10A22220A54A22A22A20A30A4400A302A42A02A000000000000000000000000FFA9AE0900000004000001\n\t0028008000200200200100000000040040808011080010000048002A00010080000803000002A00000000080000000A0000200196040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4C04C0800420\n\t2004200000008001504000080000D00000000008004485010080004A04404404500001101000000001300011400215300000\n\t00000000000000000000FF0D4200000000000000010010000000001001000000000000000881000000000000000000000000\n\t00000000010090010000000000000000000200000011510000000000000000000000000000FF26608000000000AA8AA84085\n\t082A888882880EAA80002AA202032233AAA2020000002AA2AA0820002A20000020020820822AA22222A2AA2AA0002AA30300\n\t2002000000000000000000000000FF26BB80080000040100100120100000101105108300000040140040010048050008000000996040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (011400000000\n\t0000000000000000FF0E2C000008084802800800A00800804C00840C00800000200200300202200200000200002290200000\n\tA04A08A122122002002002002402402800082012003003000000000000000000000000FFA6B0040000000008000000200002\n\t00002000022804000A80000000000000000002801001000004000C0000000000000000000000000010000900000140800400\n\t800000000000000000000000FFE3900100000000801022A00000000044820C20800000200018000000000980000001828000\n\t00000200000000000010180000008000008008800A0000008090A8000000000000000000000000FF2B66090000000400400000596040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800800804008\n\t000800080000000000000100000000000000800004000000000000000000000000FF180601000000088890088A800C008008\n\t50D9E81000000080130128020021020000424880020020000020030020028020028020020020030030000020020621830000\n\t00000000000000000000FFE9FB04001010591580180180180580504188102182000260060060040478040000861201461060\n\t02046056006146146006006086006C0620608208680600F224000000000000000000000000FFDF5D0800800AB00100C54000\n\t102008152C64511900007140300080040041040084252300010004001158081118008010008000000001901100100001500000d96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF917B000000000000001400000001000000200000000000000480000000000000000000080500480100\n\t0000805004000000004000001000801000000800800000800000000000000000000000FF1CB3000080000080000800800000\n\tA00A008210000000000002002802001006000006808002002002000002002002002802002002002002002002002002002802\n\t000000000000000000000000FF6A761000000CD00901028A00044030200000000100002140200008040000018100000A080000396040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FFE7C6000000001A11801A01881001B10A00001801000080400700621200600000000699800200600000E006\n\t00208200620621A20600400602E04820408601E400000000000000000000000000FF709C0000000018058289104145518409\n\t002141040000080206106106006004000106400806B260A004E00648710E486C074468070061062573103021070048000010\n\t00000000000000000000FF7F96000000083801801840080001000840100000000000000624620630600C0200060000220060\n\t00006026006206036046006206540006106000010004004000000000000000000000000000FF409B0000000000000000000000b96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (810060061081\n\t01004046000206104086126000204017006404000000000000000000000000FF0911000000005001400A20200B45220932C0\n\t18220000002306A0D09630640800048E52010200610801640401280200681400020600210400484040E004A55A04000A0000\n\t0000000000000000FF4F48000000105005000950200A1104010091390400010820060A60862060100400064000420C602000\n\t600608200A29600600200600000648624010C006004204000000000000000000000000FF0B61000000001A5982C90580B0B1\n\t998820301811940011420620604A0C6100110086000002206080066024300300024024822006AA608404408004201600610000796040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008C00B04000\n\t000000002605600604400200000700100332600400400E01600600404600F00008E00604600440E00E204004000000000000\n\t000000000000FFD36F0000001018118218000508018009009001020001000006C06006005202008006100212006014004006\n\t00620600608E00602000000600784002000642C005800400000000000000000000FF73F5000000085007024849829B519028\n\t448638C1858030200707495614600600040600020A0068008564040002009840A40600260860040840000160068071040000\n\t00000000000000000000FFCEA2000000001021200893801803652010803809880140848600400640710E10010E220082007000f96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF002C000000001801828801C01801820000B00009000100408682701620600400008600008A2072840040044CE0\n\t16C5408401600608E11404520001600E006007000000000000000000000000FFA815000000401801800C0200081184180080\n\t1800000001400680680E40500200008680000200420800400422610EA0C004086080006004004A4812600600C00600000000\n\t0000000000000000FFE90A000000001BE1950860140809208C04803C70000100C10600618682400200000680011209610500\n\t460C106086046124006018004514004020205804004806000000000000000000000000FFD43500000000380180180020080100056040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800E1040062C\n\t610608E2B60060868058A6006006007005006806000000000000000000FF1DBB000020001A03848801AC18018098BB9C1803\n\t0200A840C653700480600E00050601800201E8000040040070070A401400602600600400408C00600417F146540000000000\n\t000000000000FFC155000008085801900805941829C00C05C00081000000404629E2060068860002060200220D6016004804\n\t00608600402410610E0044040040101C4006417027800000000000000000000000FFC569000000455801820C558238818232\n\t00851851004004402E0061064D7024010106101C93A0620400C00C10600620410C0963060061040040222070060861062A0000856040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018010000\n\t0000060020060060000060060000000000040000060040060060060060060060060040000060060060060060040000000000\n\t00000000FF9047000000000001800401801801801801801C0100010000060010060068000068068000008000050010060040\n\t06006006006006006006004000006006006004007006000000000000000000FFB73E00000814A201810011B01900003A0180\n\t1890000004000602440650600000600610004030080400000600490680604600600600600680400A28480600600600600400\n\t0000000000000000FF8D84000020000203800223A038518498C5811844022030009600408405612800E806840290800A040000456040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF620B00000002000102200710102080909920080000000BC01602882E0069202060063880188810048002064C642600\n\t60064066C405E206006804006806006004004006000000000000000000FF5D920280004CA001045001201040851205002802\n\t100002402708C40602603054E0A60300401020444003060840A7007496006004006306004021104006006000006006000000\n\t000000000000FFFCAB0000000000010010018010018019011008000040484506044056006000006006400000000406000006\n\t004006406006086114106016014002006006006004006006000000000000000000FFD171000000000001800001801800001800c56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (40400E006006\n\t007006007004205020806006006004004006000000000000000000FF1E8A000000000001800801001A00805001A3180A0500\n\t000016004086006100526246010050000D08110006006446C06B2E50600600620600E9100040060060078040060000000000\n\t00000000FF2DEC000000000001800801C01A00821C01883812082000024600420602600808E4A60200200003202000C60040\n\t862066CE08600E12648E01C110907006006004014006000000000000000000FFE43D00000000000100000180140080581105\n\t09040540080516802D4F10E9505560D6410150102434D10006406456406116506004004024406220A000060060012240060000256040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (220000000000\n\t060120B3506108404086008211416102000AC68AE22E00620624E8020244060060020C4A0680611611011600000000000000\n\t0000FFA149000000000001A01001801800801801800000000000000600200200600000400600000080400200000600400600\n\t6006006002004006004002002806807804000006000000000000000000FFBB4D050000114001801801101000001005001800\n\t000040015610600E006100046006000000002000000006446406006006406046186824006A4038400600600122C006000000\n\t000000000000FF2F65000000000001A01801001200401011000D010041881AC600442608F85000E09620210090202020104700a56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF3A3F02000018004000400205800000041004400000000000114982015002800010002200000000004000000A0000200200\n\t000000228040058050280290080101000006000000000000000000FF7F9E0000000000119010011010109071411221200000\n\t018406022026A2E00002680601008010600000012620602606610E5060020841140860000404060062900100060000000000\n\t00000000FFAF89040000004401B092B1A81290AA3A9120833200008D0826D42C06056200856026AC0080846800200806A068\n\t06CA6956806CA2C968A6A96920A12956D46A24A00806000000000000000000FF5DED000000480003843005849840A118419200656040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030230830C34\n\t8300350302301108B403003892513012000000000000000000FFCA6B0000004003022902084842082C02000002410000C048\n\t00844D808C00402040A4000800800810300C00800808880800A48E20800880A00980800800C0100800C00000000000000000\n\t0000FF60F40000000000010008C0C00180800804080802800000202200200600210800800200200802200000029211A10200\n\t20A200200241260200200010206A062002182002000000000000000000FFE80900000004200002B0310200600390A8218089\n\t00001A40463000580010000010004CC64025C08100000040020040004002018010002000002003800020042460009E00000000e56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00008A0802A3\n\t2A42802108002002802800A02C00800802852842912B028528028D280280AC008D2A428C2022802802000000000000000000\n\tFFD2C80000002204432002080412253042010143250000C1480090490508C840004004000800908802808B48D00D08C40848\n\tC009008008C0AC080AC00888810110004000000000000000000000FFB6610000000200119018498058C10838819018010000\n\t0140560440A400602000680602640012E0000001162061062060264060062960560161400460564464060040060000000000\n\t00000000FF4F29000000100520C0CC00B28C10C5082CE2AD40800130320231340A4A210100200340A02100300828120308B000156040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFA7\n\t1000000015431435453031028C2443502A22400000C00D50100A00540540000550800D50910A00D40D00850900C808B0A90C\n\t48910808C00C08900840CD0490000800000000000000000000FF994D00080000000040401041040040000044440200010090\n\t000010000000110000010014090014010010010C104900100114108105100100104140900100081000100000000000000000\n\t0000FF58AC0008000880880AA0820CE08010008A03011000000002A84001082302000002A80002A84200002A000050001000\n\t00000C0328240248050020400000200200000000000000000000000000FF5476000000004400A00A20A00A08A48A40B00A0800956040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200211200A10\n\tA002002000042002002092002002000000000000000000FFD6610000004AA0AA0102A20EE0AA01048002008000002002A92A\n\t8200AA92400002A80000002A80002A82AA2002022AA2AA2022300202A82A81200002AA2ABB21000000000000000000000000\n\tFFE8BC0008000000200000040000200080040000020000128001048051000008000000000000020000008048000240030400\n\t000000200300100020028290001021000000000000000000000000FF4B390000000AA0AA0A02C40800AA0A20D20880D00000\n\t2C02A82A82C8AA82800002A80000A02A80002A82A82082802A82A82082202802A82A80100A02A82A8220000000000000000000556040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000043003003\n\t003001001001002142083001402202402402202542002102142082023000002002003003002002000000000000000000FF16\n\tD81000000000138219498019250958458A5801010030E20E4A400601600000802042600E0160000060AE0060460860060164\n\t2641624620E230006026046004104006000000000000000000FF599C0000002000014CC0092012012C820020C20500008848\n\t00804804004848800000800A48800800800800940928800800820900A00800800910D1080080000480480000000000000000\n\t0000FF58B400000000000080080080080080482C900850000004A0020021520020800000000021020024000020020120020000d56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF43FE00\n\t004000A01002008401203203102001400500801000260400000080000900400400840000004040A00044202802800000804D\n\t0040008050000040020000010006000000000000000000FFCAEA080000020023000868800080800846820885800000C20A28\n\t201400000000000060200201A410012902302812902C1AC8A202012002102400403403402186042402400000000000000000\n\tFFB2EC40080040040040A4005804004824004805000021200001005001001001101001198028081001000208000000060030\n\t100020000280221200000000001101094000000000000000000000FF02F340004044A440C12C02C0CC08C40C00C10C02804100356040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00600E00E006\n\t00650008720700608002000E200000000000000000FF3CF30009000000219818018C70E290D9818010A00B60240106222046\n\t02C22825000000603E0160002A601600609610641640618618602E04609040200618E000010002000000000000000000FFDE\n\tCC00000000000180102180100C8410458010000C000800361020961541000800000060260C61001461062A60060060260060\n\t06006056086000000006416000000402000000000000000000FF12F60009000000000200000400100A200002000001001200\n\tC808052008008015000004008012008000000824004000802000000800000002000A0800000000000100160000000000000000b56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AE030C062AC0\n\t00200AA809C0060060020066A648241618606641622648402410602804418631E0042042AA000000000000000000FFC1C620\n\t00000000010409018080480010008058000000002006C0222600400004000044400610680080601601208641640E08601622\n\t6006106C000A6006006CC4844002000000000000000000FF389100000000002180383384500489384B841000000000400608\n\tE10C00600011000000600624E00000600642024E04610645610601450C254000416236126008090006000000000000000000\n\tFFD9470000000000418218018811008098018410C4000020400642620400642840000022610400621040F00600312700F00700756040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFB26A000000\n\t0001559111559550C495595581300200004085565024C6555001550D5055600644E0048062C65565260A604E406456556556\n\t55600035651651684CC54556000000000000000000FF3FDA0000000000A90A98C98A30208018A58ABCAA00012AA2AF00108E\n\t2AC0002A0AA82040060A500000710E02010724E28604622E04C48C20C24008222E006D24A4C2AE000000000000000000FFC0\n\t254000000000010028018010108010018A1C4800018A000702900600480080000000400600600000600600000E40E2860AE0\n\t060060060040C8002046046504104006000000000000000000FF97A700000020028F28D8058900800250808892AA00002AA200f56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100040040041\n\t4055654654680E886006000000000000000000FF1F17000000200201811801801905801801A812000000C0400612C8060060\n\t000008000060060068000060860061068868860060060040040040080068168164C6016006000000000000000000FF622400\n\t00004004ABCC30AB8AB0088AB0AB80310200000842AE2042162AE8002A82A82AE0063270000060162AE02600600608E3262A\n\tC2AC2AF0000040060060062262AE000000000000000000FF3E9A000800200201801801801114949011A0100100000000064A\n\t00460050000080010C600641600000604611704600700E906086086026024008217007446014104006000000000000000000000d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (421620600000\n\t00002360060840002AE0064860460260660863200440440C45000040060062262862AE000000000000000000FF21F5000000\n\t000005905001942000045800081800000004C006000026046000000000016346204484006086056296086006006000004514\n\t00400000E01600E10E04E006000000000000000000FFB3CB00000000000184080180188D901803043801000000400628C096\n\t10E00000000010600E02E02000644E40604640E28E4561082D40444542B0326546546006006006000000000000000000FF40\n\tE300000000000182000180004000180004995100000540068020D600600000000080600610E000006A56006A1625624F2261008d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F50000000018\n\tAA0018AB8CD8498AB8818AB851000028C2AE0B42AE2AE0020060002AE2AE2AC3002AE00E20400E20E40E32E22E2AE2AE2AC0\n\t082062C62C62AE22E2AE000000000000000000FF2E9100000000191414B95584580380C1318859550000044D565205464960\n\t020040004C605624444455603602C216436416456446416514404040006506506436496556000000000000000000FF4C2480\n\t0000001800141801801805801803801885000000400600400600600200600000600600401000604605442604602600608600\n\t6006004100056006006006106006000000000000000000FFCF9E0000000000A98098AB8099219098A90098AA00002842AE02004d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000600425608\n\t654654600410C026000000000000000000FFB256000000001800009000801D45000809000021000005400604C00200600000\n\t680000600600648000600681429600600600600000000400608001601600E116006006000000000000000000FF246F000000\n\t0018AA0350AA8239018AB8710AA0030000244AAE4042AA2AE0000060002AE2AE2AC0002AE5063841061061260862202A82AE\n\t2AC44032601601622622628E000000000000000000FF92900008000018200018018890298200038318010000494006012006\n\t02600200400000628609410000628608408608608610600E08600608C0084AE04E04E106026006000000000000000000FF9200cd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (106004007100\n\t04600701400804650640604630608E026006006214084008106406006004014006000000000000000000FFFE2D8008000031\n\t88483883801C2590A80182188005200B308E4000260060040474180269648040000262072048160064468164064760066140\n\t0008620610622C004006000000000000000000FFF9A3000000003810141482801821C0A881020405800000180E0020070060\n\t0000600100600E006004006006006206006006286010080080026000004006207454004006000000000000000000FFAC0F00\n\t0800001800503000911011000903000111800008000650000200600000600000680680400A00654E04704652E48F45611000002d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000180008\n\t180300300182288180800302202072260160062860A600620808611E00408000000608400610E0860A622611611209421000\n\t4226206000000006000000000000000000FF3968800000001000001C0092182348002104194980000A008600220600620420\n\t6100406006A060082860C640620612601600600640600420E05030E00600E084004100108000000000000000FF056C880000\n\t001000021800821813120103002204028081080648000688600402728080600600E0100060860042362062D62B6416206406\n\t126000006006506804014000000000000000000000FFF01D880000001000605801841009040805803900804114010609004600ad6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (548400320540\n\t540120020026000000000000000000FFF9B10000000018001018001030050028090000038420401446012006486046006480\n\t02200E20210900002620620602E0060064062060001060C0084006416100020100080000000000000000FF65FB0000000018\n\t000059440418919109410A2031910014808C1025360165160460404800260060004100060260060860961460260161060160\n\t000064C6086000000000000000000000000000FF050B0000000018000038A10010C9848809892101888000E00E08E0AE00E0\n\t0E42603002602600600010810612600600600600600600E080406490414086086060020006010000000000000000FFAB8A00006d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000000000\n\t004C0289080280000080080480080000008408000440000048048084000000000000000000000000FFF1B60000000A900008\n\tC0AE008812820884140800800048101242E2AA2AA2282AA00005E2724125C133A5020021021221020A222222210210202000\n\tA01201220228628A000000000000000000FFDECD000000000000002000023001000002080044000000000640000400000000\n\t600004000C288000006000500290000000000010010140000008000010008008008006000000000000000000FF6FED800000\n\t0020000400001000C811203005211000002294B00800000001000060003001000402400805480300405084A841010010020800ed6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001000021441\n\t04408440D001000480000004D000044000004014000000004C000C0001000040900420040020040080080020020040010000\n\t000104104000000000000000000000FFC2EE800000155800155925D55D558131558058A3800052FD563042CF556554556000\n\t55455600E00144E036556216436016436456446026556008556506506454554556000000000000000000FF74280000000CA8\n\t00088C888908208C08A880A82A80001002C20922AA2AA2A22AA00028308200200022200B22A00A20A40A30A22A22A20A20A2\n\t102A22C22C222A22A2AA000000000000000000FF43060880000000000010080000004800000A840000000040000100000000001d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002000008004\n\t28000000000000000000000000FFFF0A01000000000000000440040004800015211000000800005201408000000000000280\n\t000002110084480000404284A8530108110500000208000540540100088040000000000000000000FF670500000000000000\n\t0030000000104000000024000000080000800800000800000010100015000000008000029008000000000000000800002000\n\t0010008010000000000000000000000000FF09978800000AA8000AA8808AA8AA8408AA800810800022A2AA043A022AA2A22A\n\tA0002032AA2020802A20022AA0420020420023223221222AA0002AA00200222222228A000000000000000000FF372C800800009d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001587000412\n\t0000000040A008000000000000008002982B0800800124004010000800000000000000000000FFF4B2000000000080904900\n\t8028128A0C00D008C88000102202002802A8200200224250000208200040200000200201230A00200A00280200200000302A\n\t002002002002000000000000000000FF4DDB0000400000220000040800200002020080020041020088048020040000000000\n\t020000000082000020000000000000000000000010000880000880000000000000000000000000000000FF51260000080001\n\t0400020034000010A08010200000004581200407801008810000080080000100000000000000000000000000000000200A80005d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002043000100\n\t0020120021024001004001400140000000000010008400008408000000004000000000000000000002882C00000000240008\n\t00000000000000000000000000FF1C1D000020050204802880C489A081881A90C8208081092002842D029228020030020000\n\t02002000002000802802002002002002002803003000803003802402003802000000000000000000FF88A000005000012388\n\t3881C0303594B083C8B92B802010E48E02400442688400644450000600608040600080600601651600601700604612608020\n\t602E006026806006000000000000000000FF8B2700200002820100040510100060100102260B000104406081C5441040040000dd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600200600400\n\t4000000000000000000000FFD638000000000000000000000000000000000000000000000000000000000000600000000000\n\t0000000000000000000000000000000000000000000000000000000006000000000000000000FFD61A000000000000001000\n\t2000014002000000000000800000000000001000006000800000804800004000800004004004004000000000800800000800\n\t001004004806000000000000000000FFCEA1000000000080A00A00080820880802240A128000120002002002040004802006\n\t00000200A000002000002002002002002002002002002000002000804002802002000000000000000000FF79B30040400000003d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000A6000008\n\t00350080490A830220400006006006386808085000006006006006000000000000000000FF65B60000000000218118010010\n\t09000985A80A0B800000600E80620000004680600088000602000000220000600280200A0028060268860061000060104060\n\t06006006000000000000000000FFB2B0010000000041882A14014211800A010409158000C5400E422A400440860000081001\n\t461402A01023110174A654E00E4B6246A0E086106820926222086104006800000000000000000000FF40D300000000008180\n\t18000A000102280108880180000040260020000040060800420000060000100020004060160062260060060260064164100000bd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2C83800E0900\n\t96018018B180014472042A000600600608608620880620004100252000409000800002000604600E08700100610600600600\n\t4006000000000000000000FF24A1000000000041840A0C880811821011002001800002420454882200400690001621001621\n\t00200020200360000020020220A680680E016400804102006406006800000000000000000000FF6962000000000001808804\n\t892801805C03029201800000C00602200200400610004F00000608032008309040E3423120022AB44641600600E2C004744A\n\tD06102006000000000000000000000FFB099008000404081882809025001120841A108918040A260362061200258A6006100007d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (044124006006\n\t000000000000000000FF2974000000420021B01810810401000101084C81880000C28500050600600E006004000206040000\n\t10200000408602600E086096006408006000046040814044004006000000000000000000FF7BC1000000000201A21C088880\n\t03800801000801800000400E802806806006006026000C8600000600200000E0062060260060060060000062002060000058\n\t00006006000000000000000000FF529601800000444180288180C9839491D1875CA18040A1E80501114681E0060060360002\n\t960100189820181C4008380020418146026006017000A04006006406006006000000000000000000FF52610000000000018000fd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (163100000020\n\t4008D826406286427B01008006004020144203804002006006000000000000000000FFF554000000420001904811C0342100\n\t8905901881882020700604B0030840100060040000060002080060802040060060A600E0088802064B4000044A420AD00200\n\t6006000000000000000000FF0961000000000603800800803A41A01041400E11800002400582C00608600200628400000E01\n\t030000200010440E00600640E00648610004E43000400A084004006006000000000000000000FFEBF3000040000021874A04\n\t80980181123D0708098040C0401C00428607E80200600400080662809008270049628612614F287087006040506B8801440200036040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (845C51A03809\n\tB2B953A00000E840884806886006006086800C0E00800000684008E026206504040206008000004040805002006004006006\n\t000000000000000000FFAC65000000002011800A93D83801801781801883800080E824084686087804606084000006040000\n\t00200000401E006006006000000006004800004860004086004006000000000000000000FF482B00004002000D810A05801A\n\t0180902183FA2180000565040010060060040065040214160200040020000340169860060860204009568040400148100051\n\t06006006000000000000000000FF5B9B000000408101800849C41051A0400DD018118080106404044003014008006004010200836040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060060000\n\t00000000000000FF38A700000000180180180180180100080080180180000040000020060060040060060000060000000060\n\t00006006006004000006000000004000004002004006004006000000000000000000FFA50C000000001801801801C0180140\n\t0800A01801800000400080000680700600600680100600000000600000600700600480000680080080400080400200600600\n\t6006000000000000000000FFE81E0000000318818018C3801801811A25801C01A080106C0002510600E00C00600603000628\n\t0004006800026006086004280946000000004000124402004086004006000000000000000000FFF5BE000000003801801C0100436040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030400608000\n\t6006006106000946006006806000006002007006006006000000000000000000FFA314000000001805878B0F97E8141B00C2\n\t8700E180000240000000025048140060A6A28812C00000086000006C06406C5E02061E056066016000006002006004006006\n\t000000000000000000FFED9C008000001801800801C00801C4121000450D8C808CE009424D06036444B4E8CE410002108000\n\t14613104601610E004221086206006824880005002006006006006000000000000000000FF58CE0000000018018008118008\n\t41801103100001800000604000C0060061060060060C0402000000006000206006006004100006006006404000004002006000c36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20C010008003\n\t4000010060040C42030970068000360202560002010060000060070060040000068070070042000050240060060060000000\n\t00000000000000FF8B94000000001001801901C0180088980894580A01208C684D0048B22048330270060010060001000060\n\t808060060060860000A6006006006022006006007004006006000000000000000000FFCF9D000000001001801A01C8180080\n\t1C20889A0A0A8008E82427C68232C2AA2EE00E0C020E2800000060A022700E08E02408088602E00622C4C000405600700600\n\t6006000000000000000000FF72CD000000001801800B0180082029008894434B8140127050B02152214036006856000C528000236040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6A8000000000\n\t0000000000FF2192000000001881901001801001322804808085000080E128C0212629430F006C950408A208020044400000\n\tE2062070060800441262860070000274540860A6096006000000000000000000FFD187000000001801801001801401000A00\n\t8000010000006000002806004006006004000002000000004000006006006004000004806006004000004004006006006006\n\t000000000000000000FF59B1010000001005800901C00854811290805800000000701020F003107006000006000006010000\n\t846010006406C0640640080640680680600000680C007006006000000000000000000000FF5E1F000000001601E00A01800C00a36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (108000080000\n\t1080004805204A001010021250000094640418E106000000000000000000FFEFF20000003000002440242224540440640001\n\t0400004100305209000801000061102001C02804000100000100004400080000001001800804020002084863200462860000\n\t00000000000000FF13C500000000190180220380000808008080000980000066000CA2806248024004040202061000004E42\n\t0000602602608600000400624645E00006604400600C006000000000000000000000FFB708000000001C1182A0D58D220A21\n\t0350B422510000946A0114A202824002800824400A0AA10808894400CA692692E916020C04A06826B16A80806884806C0E8000636040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (ACA0C10D0280\n\t012030CB44220220300340B0020012230034010CA0010030032A34A200108320344333341344AC039030830C300200000000\n\t0000000000FF5DD40000000412802A04900402025300022A0000000080080081080084080C810A00000400800800800400D6\n\t8D00A80D40800A00800C00A00800811484000810800850000000000000000000FF803B000000400000A00440C90000808900\n\t80280080001C200E00700280000000200C0100020020022020002022820020020200022020220020C0003032002082002002\n\t000000000000000000FFE33D00000000404801810850C1000024081182A300000281C42004701082800060A010102C01E20800e36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF399E000000000A00A00A00C30A8AB00A04A008008000002A28C4210281291280288A000802802800803000902842\n\tC52D52090802802812802842802052812042C02802000000000000000000FF222F0000000014012010432032410082492282\n\t00000103090500C8148C4004800A24000000800820800000A20A80900800C409009088008108088A00840009008288400000\n\t00000000000000FFFA5D000000001841805885801955321805081801800012E20408C14C12688600628E0888861160004064\n\t0055650600600620020610610E00604008602C2262160060D6000000000000000000FFE0650000000C4D00828A30954800C000136040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002A82002803\n\t002482A02A82282A80082A82A82A90302A82A8000000000000000000FFBDAD00000040035435431030428832034C31015400\n\t00CB0800C50450CC0CC0D10C41000D50D50840D508008C0A80D08C20450D40D40CD0C508508A1550D51440810D5000000000\n\t0000000000FFAC8B00000020040048000041040040A000454200000100100100080010900100100180100100100128000100\n\t1149031000001011001101001041001801000C81001000000000000000000000FFB54C0000000000AA0AA08C080000022080\n\t0820AA0000A801500802202102202A80100002A82A80002A80000080580400000002282202A03A00002082002A021818028800936040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (88C000800000\n\t200220A08220A09200201200200200201008200200210201211209000A002002002010002042002012002042000000000000\n\t000000FF2D400000000000AA0002900800AA0C00AA0002AA00002A82A80103510402502C82200002A82A80000000002AA20A\n\t2022503002202202A02A80002A82002A88802A8288000000000000000000FFBBB000000000000000004005004200C0000424\n\t0000000002001008800000080400800000000000000000002080000001080800100080000000002080000001002200000000\n\t00000000000000FFB0250000000000AA0324A20A20AA0802AA0804AA00002A82A84C12002002802882A80002A82A8008028000536040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF66F2000000410C20C40C00D20C12D00C00C50C02800108B10113310308301240340300B0A31028000830020020821420\n\t2231000A112022002888403003003002502002000000000000000000FFE34E00000002180D89581381182180188B8810218B\n\t4042444600604604600601612C00400600E00000630608600620E10600030600620642600010611454600400600600000000\n\t0000000000FFFC3F0000000014002C405225520021420022100100010048050C482C920840840904804800804800A4800480\n\t0820920820020900910810800820800894800444800800000000000000000000FFBCE900000000080080880080080084080000d36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000020012008\n\t000000001000028800000008E000106106000000000000000000FFE42200000000800000300008A0B00010910C1024048012\n\t00000200800040040162500000040160000002800800003000002884000000C0440110280088526000286006000000000000\n\t000000FF424700000002106288880A80090088886291080000602022A045405200240A00208220A002084100082002802D82\n\t9224A20000C2092002002000102006002006002002000000000000000000FFED6F0000004004084204004245024104404094\n\t0008010090050890210B90002010054050A1000000001004000000008618000008008318000000001061019180000000000000336040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018800004004\n\t20210E00C500012006426006000B0009624710700720602608002600E006006C400860061040000860820000000000000000\n\t00FFB2FF0000000018011A10A180984008F00980010506001002000064060440E40C000600401602100000621640646601E0\n\t1E0000060060960271300060A6000000006000000000000000000000FF845800000000180100100102188410182115002100\n\tA002841002E04628400810440600400604100000600600610610648600000600610604700000614601400000000400000000\n\t0000000000FF729D0000000000000000000400420201000200C211000A801000048052800804E4002400080004001100284800b36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t41B20000002890AB8898AB8898A1A8C0852000010000002AAA08A01E2041D42C82240062AE2A80003268060661067C640400\n\t03AE22E2AC01C020644A062AE0042A8288000000000000000000FF333700000000500180180080381580400310C015000000\n\t2000C4250604C21002481480600600084000E00621644600620E000006006006106800026046002414006004000000000000\n\t000000FFE2D10000000418010430018218000410498201218000534004002046084044006086006006000000084006086096\n\t0560C400000610600424401011408E0000C0000026000000000000000000FF23FD0000000018410210A1809800049109800000736040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006036000016\n\t016116006840016010006504006046000000000000000000FF602B00000055595591015510594A149943B221550000551310\n\t52650655551251255300243255000C55700613608600655600055654E4D65560445565405525545505320000000000000000\n\t00FF8C3A0000000CB0AB8CC8AB8A9895880089A800CB00000422AB1220862A420028F22C0062AF2A8020226006D0EA3600E0\n\t840002262A62242A40080852A72AF02C2AE28E000000000000000000FFF0B200000000100180280080980180201100000100\n\t0000204300A02E00482002300400600600000000600640621650E00600000600600600601000700E0020040000020000000000f36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000042849241\n\t56004052002806006310800814006006216206246004000000108014004824004002002006000002000000000000000000FF\n\tB75100000020180183300180180180D8D5B05005800000681400600600010604600200202000000000600690688608600400\n\t0006006004004008004800806806006006000000000000000000FF0E040000000AB8AB8C10AB0E1889C8180101108980002A\n\tE02420E2062ACA0228A2AA0021002A90042AE00602606E84E2AC0002AE2262A42AD0042AC2A82AA2AE2A82AA000000000000\n\t000000FF988A000000401801800001805840031841055001000051100041642601500600608200200200080000E006006007000b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF4F96\n\t0000000898A98880198AB8D38018918AA08D80002060042242AE0062A628E2362062402A80000062AE186006086044000220\n\t22000400400000C2222AE3060CE28E000000000000000000FFC57000000000580584214500182181180B8000018000006404\n\t00400615401604201611600000000405600601611604630400010011000410400404408200204E0200020000000000000000\n\t00FF5B8600000004180180000080181012382180004580000B40D409400640400600608604615000000028600642644640E0\n\t4C0000080004D424C000484012006106406046000000000000000000FF699A00000000180180000001384202180183004180008b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t8000C004004086000026000000000000000000000000FFEDD50000000AA0AB8C088D8AB8918CB8AB0090AB00002062103202\n\tAE31600608C22622E2A02A80002AA2A810E0CE22E2AE0002A02A02A82AC0002AC2AE2AE22E2CE2AC000000000000000000FF\n\tE67300000011411591114595590010D84195510980004D650044455640654E55054243650AD500045525504363164D600E00\n\t055055045054400454C44E550416510550000000000000000000FF3E4200000000000180580180180180180188100180000D\n\t6100014006002156044106006010000000002000246406106006000010008000004000004006006006006004000000000000004b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000400400440\n\t400E40400608C0160000000020000A644640E00600000600E006006000006002006894806024000000000000000000FF9C65\n\t00000000000182103080000102080183020180000B00C40AC00615250204410E004007000005002000217116047006800106\n\t10600600400400400A400006440004000000000000000000FFF6E50000000AA0AB8918408AA0C78888AB8440AB800020024C\n\t2042AE04642648C2363242A42A80002AA2A80060060862AE00022E2262AE2AC0002AC2A20AE32608E28C0000000000000000\n\t00FF14FA0000000400218240018018020218830010410000006028092006136002000006086003000004002000006046006300cb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFDA0C0000\n\t00000081810C2180184100B800831608804040614802408C2540100040060431061400000820400460060062000100060060\n\t8600E010006000011014000004000000000000000000FFC2480000000104C9C41905827A21041890801D00940015E4801040\n\t0420C00000440618301700000108202003E80690EA10808106006016444488104280006824806004000000000000000000FF\n\t94C40000020006098010008400011000C41000400080001000006004004082204006004A070000840060082862868560860A\n\t0206456406006104006502040044400004000000000000000000FF7F1E000000000001C0D882800249002000102000000000002b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000600602644\n\t6000006086406020006184000000000000000000FFEBA8000000010021841801021803045811081871052000623008211400\n\t410400C0860004068401280020081060A600E2B014000E006186484280104006010000000004000000000000000000FF4AAB\n\t000010000401802C08800020020830840082808000109002A3262AE2080040260000870A0400012300016206006002140006\n\t206006226030006010210804086204000000000000000000FFDC890000020000218098C28000000908229480808820340220\n\t14000604200C404406022896080000002008206286146102000506456416054400004000046014200004000000000000000000ab6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (290080000000\n\t0060000401512200000000002A0440408130000000008080480000480100006100006006000000000000000000FFCC5D0000\n\t100000018030000000010008400C0020004000044024200410000001408600080700200000A11000E2060062460A00062061\n\t2610650000600E006020100004000000000000000000FFAB760000000000418018020500431448880001000D000881081020\n\tC442C5540040260001160A00000024000060D615608620000E006006006048006086010000006404000000000000000000FF\n\t1AE800000000000180181300980109B8810018050A0008E0002124040040A000400600000E00045000200000600E0A600220006b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (169A00000000\n\t000000A00000000800022840800000000080C40950000B10000000A000100100000020100010004000000000001000800000\n\t0000000080000000000000000000000000000000FF48CF0000000000AA82888A0EE90008088090309080002202AA02220028\n\t02A22AA2AA2428028020002AA0000020020820020002222222320320000422220AA2262AA2AA000000000000000000FF777B\n\t000000000000104000000112048004088010000009000400005004801400400408C406116000004000010110040404000110\n\t100008008000030010406008006004000000000000000000FF80DE000000000000000020000020004028040022000000000000eb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (22A2222AA000\n\t2AA2220AA22208A0AA000000000000000000FFA16100000000000121204321000120844140D0430000044004154905095000\n\t0000005090310000000010000404001000480000000000000400001000100000C4220000000000000000000000FF46140000\n\t0000015592192D9258C195390312190B0000547414424556C074AE55740F54754F55600104E0004363164D75460005465465\n\t565560005564563564D4536556000000000000000000FF7A650000000000AAAC0888C8082ACA288C820080800030A2AA2022\n\t2A2222AA2AA2AA0022823320002AA00030A0CA22A2820002AA2AA2A228200020A2A22AA20A08A2AA000000000000000000FF001b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000008\n\t20C30400800000000000040800000001000000000008020000400001000008000000000000000000000000FF1CAB00000000\n\t020009200A03205403004000204800001284A00280005010202011000010110000002400002A044040891000000000008800\n\t0000000010200110020400000000000000000000FFCAF4000000000000000000000080004014010004000000081000000004\n\t0508000420810100000002810000010110040040000110100000000002000100000000400000000000000000000000FFCF74\n\t0000000004AA8208A08908048808808A48C080002020002822AA00A0020AA00A2B22222AA000182000002002082212000222009b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01C010001081\n\t01100116800100010155153900000008005558084500050000010000000440000040040404102C48000008000A0850880000\n\t020480028218208000000000000000000000FFF2F3094094140840840800810800800C0CA04C400120800200002522229143\n\t00000028220240200000B4832020CA20A21610200211000211200000A006842002002240000000000000000000FFAB040002\n\t000000001086040000800102A00C808004000000000880000008000008000001100280020000008A0C000200400400018008\n\t40000412000200800000000000000000000000000000FF8DD40002000020000000000A010004010015400A00000800002200005b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020020000020\n\t02802002802000000000000000000000FF73CD00800000000400400000800000000020020000000000004008080000000008\n\t00000000000000004801000001280000000000120000000000020100048208208000000000000000000000FF05E900000600\n\t0922802800840800800C22844852800100080020020200100200006041240200200000200208300200280200280200000290\n\t200041B002003003002000000000000000000000FF2F231001041438418C1803811901009833003043032108020000634600\n\t0144000020D2648F40E00000F506C86146C1643612600611000615620800E006046006006440000000000000000000FF3C9400db6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000620000010\n\t60A60060000060560161060B6026206406010006006400100006006084000030000000000000000000FF4803000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000006000006000000000000000000000FF02390000000000000000000000000014000000010000800000000804001000\n\t001001004004000000000800004000000000004004000000000000005000006804006000000000000000000000FF944E0000\n\t000008208008008008808408A2A88C0580000000000042020000020000000020020020000020060A28020020028020020000003b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04001801809A\n\t29809941081901201020004080004008610208182380800031600E0460000168070002850A60262102020000062062104044\n\t46220006200028000000000000000000FF34C8000000001801801A11A11A21201A0120100000000000201060020000420401\n\t008860B6006000006E06022C4600628E002002008C06066000000106006086006000000000000000000000FFCB4E04000000\n\t1C21811821822020101840100000000090805000202E10000601000042600602600244E00652600600748E14700600000740\n\tE05280444EC4040E406000000000000000000000FFA7F800000000180180180180001000100004005000000000000000060000bb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600040404664\n\t6006806000000000000000000000FF7E20000000101E21805801801CA0801000C0A801000100104100490000100E00000001\n\t6047046080006006000006006006110000000106806008086406008805000000000000000000000000FFBD28000000081813\n\t885C85A00000E01408900885000000000000A0000004120000100061060060810460A7882405006806002880000006886000\n\t084006036006000000000000000000000000FF6FDB040000001C41801801824410801020940A100000108008000050000002\n\t44008004600604600045602E5120270160060A2002001206016029086556000416006000000000000000000000FF8B1D0000007b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010909006206\n\t1861044060C60064440A610E006806020507010054256086000106000000000000000000000000FF121B0002000018058018\n\t0180000002D620000000020000800000000C00000600005100640600600080628601700682624E1060060400060000000049\n\t07006004006000000000000000000000FF2C2C000200001813801901808000005800400000002000000005080C0002060000\n\t00006086106004046046006226006006006106000006800004000806000806000000000000000000000000FFC65900000400\n\t1821901C05809C00C6391090AD0500011988008260080010060600101066268860000161071000241861860806000000861000fb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (188590182180\n\t18491418233094004000400010024104001016021000106306007001C06046086044006006C07106000040C0621000400600\n\t6006007C00000000000000000000FFE898000040001801D01C41801801289C01001000200001042100C10400000E0480A080\n\t600600608400620710608C2163460860060800000160240C8006001006000000000000000000000000FFBE9D0000000018C1\n\t889A01800001881883A01C00000000020001008000000604000000400400F00000600610611431600620600608000E000000\n\t504006006006006000000000000000000000FF64280000400118B980D84180001580309B971860020010014106000000085600076040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006800004\n\t000028000000000000000000FF66DC0000C02D1131811A49801A01901A41885911280004681012600404100684E00054E200\n\t4044022020460C482601600640640600080640024A106006007006006200000000000000000000FFC9AD0000000818058098\n\t09801841A01A01C13800000000000088500000100400006082E00E00620001F00600600400F0060060060000000060200840\n\t06047004006000000000000000000000FFBBE940000003182DE25801821815841841911AA808001201002040300200660080\n\t002060062160044060478364C40060A7C26206000511006094006006821106000028000000000000000000FFAB3B2081420100876040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060002140\n\t0001610608000608600E006016000000406000114006006004006000000000000000000000FFB07200000000000180180180\n\t1801801001001801000000600000200400000600600000600000400400600600400600600600600600000600000400600600\n\t0006000000000000000000000000FF89B7000000001001801801801801801801201801200000600100200600000600600080\n\t6000004000007007005006006007006006001006800000006006006002006000000000000000000000FF50D0010002200001\n\tD21A01821C09841A05801A2100002068004068A400003700600000611000400400200600408600692604610600002600010400476040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (811801801801\n\t21182A104B120000A00010446934400D4E004440116250006116A4640F002916006D568168060000500062AE804806000002\n\t000800000000000000000000FFB9350000000A00018238018891C320119A020AA80000800000002806000006004060006010\n\t08700080E00648090600680642600600051800600008C006006006006800000000000000000000FFFBB00200005418058058\n\t41885201041A01C2C8201400082410056054101356114408C4EC2010402612700604A4464260870D70060480000962068048\n\t06000006000000000000000000000000FFDEC30000000010018A180184981510182388088A0000452000006504000006004000c76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000040060\n\t00000000000000000000FFFB16000000001801E01E018050812018A2D008000000000000C8E4264004820060008860400040\n\t0000640600600600600600600600004E006028005006806006000000000000000000000000FF4E2400000000001180980180\n\t14018096108038AB800020400802609400802800643100E40808693102480E00C08E20754E00E08700000600650000E00600\n\t0006000000000000000000000000FFD3A0000000001001801801805D01A21920C098418A0028420013EE2C09028A88E21842\n\tE22810C0600A608703C2A66A608E086106028A0628E000016006806006006000000000000000000000FF48D500000020081300276040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60A0C3680082\n\t6C94C16AC7086896C06836200886806800C04A86800A84886000000000000000000000FFA4D9000090005909901809801A01\n\t8092052C8009000040E01000601400011408600140F2080060009060240C6006006A4614E2860000060C620004E806106036\n\t026000000000000000000000FF86560000000012018018018018018010010000010000006000806004000806006000006000\n\t004000006004804007806006006006000006806000006006000006000000000000000000000000FF8438040000000C079018\n\t418450511018009058040000050010006904001041006000606000406000206007406006006006416017000906806400004000a76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400494020430\n\t20000012000020010861C1000008000800003B00404001010000800000801001A00A00000001901300100180000867880760\n\t00000000000000000000FFFEFC0000000426002080001000080082080A410000014000000200000001984000000003A82280\n\t00000100008000400200300000000000000000000780006010086000000000000000000000FF6BBF00001010184380190D80\n\t51411051941008080000150000046000000C2600600000E4000060000060041262060060060461C600000600600062400604\n\t6026100000000000000000000000FF873B0000402C9825829C81AC9C95205928202AA40000800000A2EA400000248060008A00676040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620E00E00000\n\t0000000000000000FF57AC000008704A54A22E22C14C12D00E8ACC0D48000009208943310200040320200011224140B00100\n\t3003113103203A0330B08200108310B0090032531031030A2000000000000000000000FFD68C000028400404000280290090\n\t20024240A2250000000000800E00000000004000804800800C00001220810900880C00C18820200800880A00800800800800\n\t800000000000000000000000FF321A0000800A4828C608008208040008008508C0000000801010206C000800000001042000\n\t0120000A200A68202200200A00221A000002002000002052102002002000000000000000000000FFCEEC000000008090484000e76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A80002A8AA8\n\t0800002A82A80881400002A83A00020202A84A80200A8000000000000000000000FF2512000000000A00A00800A20A00B00C\n\t00800A008000802800A0A802000412802000902800002A80802002852D0300280280284A8008028028808128028024128020\n\t00000000000000000000FF131800000000000100100120822322A04503420100000040008A080C0000A40040008548D10008\n\t00000000C04849004000C40C80000800810C00A80800C00880C00000000000000000000000FF226E00000002180180190192\n\t194184582120B805800042600010644600088C00600002610000650080688620400608608604605600000E0060004161060400176040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (40C00AA4820A\n\t202200000000002402800002200000002A82A82A80002A82A82282A82A82A82202400002282300002882A80A82A828800000\n\t0000000000000000FF457F00000055415415455410032030034C5523540000800800810C500002D0800000910910D50800D5\n\t15508108C8D50D50A00800800CC0C50800D30D50950110D30000000000000000000000FFA628000C00600400000200440410\n\t4000080104900001001001091050001101001001001001801001001001001000001001001101001101081001041001401801\n\t020000000000000000000000FFBD700008000AA0AA0AA0AA0920880000882800AA00000000004002A000080000000020020000976040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A00000000000\n\t000000000000FF868A0000000008008008008108048008008408048000002002042002000102002000002002002280002002\n\t05200200200204212A002002002080012002002002022000000000000000000000FF14430000000AA0AA4AA4AA0900840AA2\n\tC068800000000000002802080002100000002A82A82A85022A82A83802AB2A82AA39A2120002A02A85000002AA2A82A80880\n\t00000000000000000000FF089C00080000040040000044400A03400000000000000000001401000008000000004402400002\n\t820000004A04000000000A8408000008000280000000001220000000000000000000000000FF197C0000000AA0AA0AA0AA0800576040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (090010050000\n\t00000000008081008048641020000028781474000000000000000000000000FFBE98400400408C20C00C40C00C08C04C20C0\n\t0C20100130250B00900201100B0820010030031530090034032020C304201251200301201211304800200200300200200000\n\t0000000000000000FF8D910000200058098218018018A193110984100182C004600610600600004401610000E00E40600000\n\t600608400630634600648608628600640000602E046004006000000000000000000000FF991A000200201201201201223248\n\t2010530033490000800800814940000854804800801001004802800804804800804800800800804810800C02AA080080080400d76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080090008084\n\t00200400401000000D0408288420000100400000006000408040000000080010000000100000000410406000016000000000\n\t000000000000FFED4B0000000100400000000000810C20800000400000220200010004008004080080000010080000006400\n\t480020C40200300000100520130410000000006008006000000000000000000000FF12E00000200029188608028008248008\n\t0012081012A010A08208010200002A00800000240236A5000021020028821928AA802E024020020020005431020227021021\n\t00400000000000000000FFBCC7400C005804004004244004084084284004010801090009005000001001004061009001001000376040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FFA73100000000182180980180180114484382103100000860160060220000005060100102044062A00060860070\n\t1610700700700E2060060065000A5006006286086080200000000000000000FFB75A00080000182184982180198182293312\n\t0124028024600E16202E2004B00064880080040060220060064161CE0262263065860060060062A200441640C00421600000\n\t0000000000000000FF7C630000000018898018418038030008010080000CC040602600008E4A812201612000008412600000\n\t6006006006036226206006006006086020404086012004400000000000000000000000FF844B00080000000000000000400000b76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600608C00600\n\t62062A630600600E016200006506400012000000000000000000000000FF3F5D2000000018AB8AB8AB91D8859000A10988C4\n\t80003040042AA8100000142360002AE0061162808863A64461D62AE1661064160062AE2A64003664760AAC42088000000000\n\t000000000000FFADB2000000049801801801801853880001000C22000004E006000448000304806000006006406800416806\n\t01602600608E2AE22600600600690008610E404142006000000000000000000000FF73AF00000008380180180194380104A8\n\t15845011000010600600610200005210E0000000040AE0000460162C441600620600608E006006016200014206000416240000776040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (410002080000\n\t050005001504000106084000006006406D001270060048060068060469460061100968000050060060064060000000000000\n\t00000000FFED6A40000010595595595595595595490310414C00004CE007429404000546554000556006556284C075564464\n\t0E5560B600E04E0064C0446104554056151246330000000000000000000000FF70080000000A58AB8AB8AB8218B182C88B8A\n\t488180002040042AA0400002262260002AE80602600021622E0944062AE2174160060062262260802160862AE08A0AE00000\n\t0000000000000000FF4AA700000002980180180180180100082980080180000040048800D000000F0060008060060060000A00f76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFA9D90000000C1801801801801801000041821435000003600648400400001600600000600600680401480608141600\n\t7236286206006006000A04004AA60004C6000000000000000000000000FFF55F00000000D80180180180180180180B08D800\n\t00001000040048000000860040000060060060000C6006004086006086806156006008006100006016406014046000000000\n\t000000000000FFFBDB0000000018AB8AB8AB8AB8AB8AA881051C80000020000482C2A80002262AC0012AE8062AF2862162AE\n\t22E1662AE00602E8060062A03AF0062AE0060A8104288000000000000000000000FF39070008000118018018018018010008000f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006206006026\n\t006116006000006000004006004004004000000000000000000000FFF0B30000000AB8AB8AB8AB8AB8038418B18A58490000\n\t30400440422000000622E0002262262AE0002AE2AE1004062AE0C600608E2AE2262200003C60064AE20608E0000000000000\n\t00000000FF5E470000000018018018018018018000038018A300000440342541000005061060000060160060040040064400\n\t160060260D600600600600000400601600004E400000000000000000000000FFD1810000000018018018018019298CD80980\n\tB001000008C28408401400003600600009610600600000600610852600641620624600608E0900000544A620610604600000008f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (189500000040\n\t0410600400028E10E00600E0060060000000022360260064861060060060080060000160460000B402000000000000000000\n\t0000FF9A410000008AB0AB0AB8AB8AA8AB8098AB09588100002862AE2862860002262AE0062A62AE2AE0002AE2AA2AE10E2A\n\tE40E22E2262AE2A82AE0002AC2CE2AC2AC2CC000000000000000000000FF7679000000954154155955955128100101931801\n\t000025453404E5540000464460065465565560045505500060965560164564CE556540556004406516150404510000000000\n\t000000000000FF3DBD8000008010010018018018018458018218510000056006016054000006006006016006006000006000004f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF802E000800000A0080180180100114100002900A000032E006082126000016004004906006806000006000086427006456\n\t486446006086080000004526405094404000000000000000000000FF67D5000000801001001C01801001415001801C400000\n\t00600604300400000600400400F0060060008000008160960070060560060060160100000008160040040240000000000000\n\t00000000FF4ED00000008AB0AB0AB8AB8AB8AB9018AB88388400000062AE24A20C0003B62AC0042262AE2AE0002AE2A82260\n\t462AE18610608E2AE2262200002AC0060AC22408C000000000000000000000FF141D0008008000000018018000040120230000cf6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0600E0AE0060\n\t0600E49608E04020400E084226004000000000000000000000FF7571800001100800901801900031431020895021000020E2\n\t4708600001000601629600C0260060C000008200000700621600640600600604642040601615440600400000000000000000\n\t0000FF7F8F800881C89281401C8D80110130B0A084330590800660160C740000000600E00EC0500680600081F080880006C1\n\t6A4701F20600601612600100502602D006004000000000000000000000FF1253000080208C80E01CC9C55001005080001000\n\t00A000608600600400000600402504640600600410080011600608608680688600E48601000C800046004054004000000000002f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (880028608600\n\t60A008800E00630E00600600600000600610204601600600600600600600600000600600422E004000000000000000000000\n\tFFE0CA0000018010030218458070C91610090419C782400063162864080200A628658600628E2060A8100004238086506086\n\t006106086006006430024006224016004208000000000000000000FF5893800001800C20815809C0800440008093504000A0\n\t02600E02600020000600604600400610600000040208203754E00E1260B622604600E2000100060040061040000000000000\n\t00000000FFEDC6800001801001281A018A91080000009090009000416427046002008004006026A54246006120006002002000af6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF3F\n\t7C80011202405400000002002802004A04003200000060060000200000200001001000000001004060A84905200004102004\n\t400000900902C0208520006008006000000000000000000000FF99CB00000100180384180180101100104811112405000462\n\t0640601424012620604200208630612000640600610648610E08601620602600600000800600400608400000000000000000\n\t0000FF1E7500000100180181581581102300908200300088402861161460A011001610641200221600601000000422E01604\n\t600604614614600601642004400624422E004208000000000000000000FF9074000001061841801803805121049023041801006f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A42A30A2222A\n\tA2A22AA24020A2CA2AA2AA2AA000000000000000000000FF0E541000002282A820000028A40000200000000A000000000002\n\t1124000000004008008001000080200080080020800080100000800000010000080040000000000000000000000000000000\n\tFF15520000000409008AA8AA90010010008088800100002AA2AA2AA70000050223822A2222AE2AA3004AA0021420422AA182\n\t02208A2AA2322220001A20022AA2A22AA000000000000000000000FF70500000201101000000001121021120000041000000\n\t006006004090000510100000010000000042006404024010000040090000000000000002004010004000004000000000000000ef6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AA2AB0024A2\n\t0002AA2AA30A2022AA2AA2000ABA232024032AA08200200A2AA2222220090A20020AA2AA0AA000000000000000000000FF34\n\tC080082140440840140140120104100502900500000000000010040010100041100800050044000008A00003010040000401\n\t10804000000100040000000000000000000000000000000000FF70F0808155901801D55B5584190580992D15594180005565\n\t5651600E000D56556446547557556210156C564560965564564564CF55655654648843651655655635600000000000000000\n\t0000FF26E600008A8908228AA8AA82A82A80A8C88828B000002AA2AA2AA02A0000222A222222A2AA2AA0200AA20A40A00A2A001f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF243800\n\t00000A00000000000000800000200200000000000000000040500C0006000000000060000011000000000080000000000000\n\t0000280000080001000000000000000000000000000000FFA01F01000404404040000015210C144032000042000000000012\n\t80000000000001001480000001002000890D0520000010440341000080088280208520000000200000000000000000000000\n\tFF7AC308000010010A0004000000200080000000100000000001400210000000000020000800800010000000000010800440\n\t090000000010000001000010400000000000000000000000000000FF30A48000A880C8048AACAA8008509408808AA8808000009f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (506046000000\n\t006001004000000000006000000000000000000000FF3A0D18000410002260100000151000020044A0090000500808024204\n\t005020044004004004404151020004C04404044404800000200000D41150D0120800008020C000000000000000000000FF68\n\t09100004000800900800800A20800804A80A00800028200200200200200200300280200282200080220A0020022020022820\n\t42000000002800006800000000002000000000000000000000FFA20300000000000002000060000800000000020000000008\n\t000002000000800000000000000000A80018002002000203080000000000008200A820000000180000000000000000000000005f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020002060060\n\t02002002806006002000002006002002002002002002000000002000002000000000006000000000000000000000FF0E6300\n\t0040000024200000200000000240000001000000000804400000102000480400000100400204080000400000000010000040\n\t0000000002004401000080208000000000000000000000FF4D7D100020000800800800800800800820814800800000200318\n\t2042502402042002003002C02000112002002003002002083002000000002000002010060000002000000000000000000000\n\tFF8565000000021801921801801841801C259018010000006006006A0480488600700780400684400080641500400740608F00df6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF3FC1000000\n\t001801821801011829001801801028800010200C0AC406002002106006000006026100006100002116106016006006000000\n\t006000086000000000006000000000000000000000FFDAD50000000000000000000000000000000000000000006006000000\n\t000000000000000000000000006000000000000000000000000000000000000000000000000000000000000000000000FF1D\n\t9700000000000040000100000100100000000000000060068008008000000008000048000000010068040040010000000008\n\t04000000000000000000000000000000000000000000000000FF1C94000000000800800800A00800800A0080080880000020003f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (021000480064\n\t20022000040080026000000000000000000000FFA88C000030049021025805001A41288A01A0140084000860000040860064\n\t46106106800106022088820504420027486006024812100000706000516010000300406000000000000000000000FFE42C00\n\t0000001801801801101A01123C0980100A80000060040043060060060060068008860020002464048C008600600E85680200\n\t0000406040086000018500046000000000000000000000FF75B3000040049841C01841001801432851C01084820002200000\n\t480600681200600610808E80020950800050004600600620600608004800620082600002000000600000000000000000000000bf6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (640682F00616\n\t684629E4260020000069065E1086026006004000200018C06080452400008000066000000000000000000000FF000B000000\n\t000804085802A0BE00808801401801000000600A00780701620600700E006106802000000206000006206006004008200001\n\t106000002010010000006000000000000000000000FF29D2000000003083901801C958099009258030400080042016006206\n\t00480700604E000C16102000407000000006806006006000000280006000822200040000006000000000000000000000FF12\n\t32000000040A00C01821889851800821001D40820002281295700600480E10600611000E80240008830020000E00600640E0007f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (530000000110\n\t1184B80100188500090D819221000100600A70715200600600600600080600200000080200010608649621E2160000000000\n\t00906000000040806000000000000000000000FF3246000000000800001820001808081811A41005000008600E8040020040\n\t06806006006007002204006003840006086107104106000000400214006000000100006000000000000000000000FF106F00\n\t0010604800821800001800005821823201800000620200400202402600610630602E08200440000280090782600600600608\n\t0280000084086000040080206000000000000000000000FFF4540000000415610218009619D096A905821C41050005EA060000ff6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020011600400\n\t4018000241006088000000000000000000FF3C2F000450741401601800001800042801053820000000700E0448001048444A\n\t794681600600200480610400008628620608C006000000556415405420200000006000000000000000000000FF1FB2010000\n\t010010021C4000180005080104190480000068020AC0C80040040060060060060222801000042412A600620E08408E100010\n\t406288084800000080006000000000000000000000FFD98C00840000140108B8010418810288018010A1000000608604E002\n\t00600600600600000602A080886042400C46006006404406080008088080006008000000006000000000000000000000FF130000e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100006140140\n\t0328060860060000060C6026006006046404000800000006006006000400000000000000000000000000FF980C000011B010\n\t15845840809A11A41A43A104030000016886842506000046400200802006406804006004806007487006286844000200D504\n\t0C446446C00000000000000000000000000000FF8D5F00000000108B101820001808000801805D8100000060060028800060\n\t04006206106066282000006106000107007406014006001000006000024010000000006110000000000000000000FF31C400\n\t02000000001A3C00049814100927801C03000010E1820062208070040060070A78060120040010460A0026006006A24226000080e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000100100180\n\t180082180000000D901121084000650602200608820200005054610603600441640641640604608600600400000000600400\n\t6006000000000000000000000000000000FFDB14000001800001801800801801801801800000800000600000200600000200\n\t0000002006000000000006006006006006006004000000000000006006000000000000000000000000000000FFEBE0000401\n\t801001801800801C018018018000000000006806002006800002000001002006000804006006806006006006806804000001\n\t000004006007000000000000000000000000000000FF69FF000021A40101801800801801A05A01A4002100008060110028460040e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (166030506006\n\t400000000000000000000000000000FFB1D900000100080180380180184001020181404184409465500C3556440500000510\n\t00E556116414000146006117507516806806000501006284006006000080000000000000000000000000FF354E0000010020\n\t018018018219E8074209806021000000608E70200600000000000000600640E0042070060062460060860064441000000060\n\t04806006000000000000000000000000000000FF7AD0000001203A01841840801814100001801001000080E02800A2360008\n\t3043050000E00690640004004602600E10E427027006440000046040006006000000000000000000000000000000FF0AFC0000c0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (024300000461\n\t06400000800006017056806046006446000000006000006007000000000000000000000000000000FF538900000180180100\n\t1E00801800000000001C24722011004E00208640000200044880602600040100682600600740600600600600028000628000\n\t6006000000000000000000000000000000FFA4C0000001E0020140180080182180980000A881000004648002A23602030700\n\t008000E30E116110000886006116886D0E0060240000000A6010286007200080000000000000000000000000FF828F000001\n\t801101001800801801801800080985182001E2260BB22E08822E0602E828E0060A630002EA262260060AE2060260442A00010020e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B038CBB15A48\n\tC23A0A20A34120D0488000A008A0802004200C02100108A06C26CC880092888EA8E40E80E886C4EC06000220B0E880D0E846\n\t000400240000000000000000000000FF0B8B0000038298018418838898C188180B0812828000006006234314101106C28000\n\t04C109000088006006026006286206886086000000826229006006000020000000000000000000000000FF11320000018010\n\t0180180080180180180100100080000060000040040008060000008040020000000000060068060060068060040000008060\n\t00006006001800000000000000000000000000FF0AB6000001C008814438408018041140040018008000000000082006001000a0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (021920020000\n\t20020000000000000000000000FF200E0000400100C000A0010400A414000510128000000060068300000000046080804000\n\t00004180006008009409008480680000000200660000008000000200000000000000000000000000FFC54200000208020058\n\t0014000040000002000344000000600620088828024002000000064804800002E000101B010011001002000004000885A000\n\t0060040000010000000000000000000000FF7970000001821839801883881900000121847008800010006600260400040208\n\t000806603640000008600620601650600601E086000000006040206506100000200000000000000000000000FF61370004010060e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080002604600\n\t4000006006106006006006106446000000006000556146020000000000000000000000000000FF56E7000400C04C30AA0C08\n\tC40C00D20C4CCA8A10800151304303220200100200800120BA134C308110340B00248A2824832530120004012432A1803202\n\t100000810000000000000000000000FF87CB0001002082034602004002082082D02980210000800880008800800984810800\n\tA19000A20808900C908A0000281200860C50000020800A08C40000000001000000000000000000000000FF431D0000010468\n\t0000482892A802882808800A128000612002442854000002000000002082186002002002002002002002002002000000002000e0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000AA0880AA0\n\t8C0AA04000000000002A82A82202202102202A8AA82482A84000400A83180882A82A82A80000000000002200002200008000\n\t002A8000000000000000000000FFCBD6000400A20B00800804A00C00A00A209028A080008028028020021009128000009228\n\t02A02A00C02802C42803002802B4281200080080284088A802000000000000000000000000000000FFB3C100000128A24B00\n\t1220201242200294230015000080080090888C84880480000080000094C8408008C0800804804804808D40000000908C0000\n\t0000000000000000000000000000000000FFE6ED000121851801805805901943801901805925000000600620602E0002A4200010e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF20980000004301320AA4804AA0821284AA0AA0B000002A80A88C82A00402082A82A82802A80C\n\t00102A82402A82A82A82A82A82000000002A82002200000010002A8000000000000000000000FF221600020000C084554130\n\t3543503543000C20100000D50D50521540540D48D50D50D00D50930A00950C20808D50D50550AC08C0000800D50C40D40801\n\t000000550000000000000000000000FF4DDA00040000000060024A0004004000004006000001001000401800009140000001\n\t031000401401001101000000001001001080000001001001001001000000000000000000000000000000FFB6C700000000000090e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (810800030800\n\tC00940800000805004800800000000914C10808800804800000000000000000000000000FFB5B90000008088088008288008\n\t00840A0080005080000420024420120000120020021220025022000020020020020020020020B20000020020000020020020\n\t00000000000000000000000000FF42160000003044800AA2800AA0D00040AA0AA08400002884A80002B05202002A82A82002\n\tA80100080A82182AA2A92A82A82AA2500000002200103B20020000002A8000000000000000000000FF35660000002A043000\n\t020400000000000A0082C40000000000808008000000000000010000000000200000520000001000008208000000000000010050e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (050044048000\n\t0400000400000060060100100500100120104100102100100000110100000000008010008020028110100008000101D00100\n\t0000000000000000000000FFBC90020440C20C00C00C22C00C40800C1082040080000120AB40310300124340300300322300\n\t3000013403103003213402002002000113003100002203003001000000000000000000000000FF4F63000001801801801809\n\t805881881841800001000000600615600414000600610E00E08E5061000260460062061261064164862102460060000C6006\n\t004000000000000000000000000000FFAA480004010A322520100520022D28C0002002030000800A0088C8042908A400000400d0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (486300000000\n\t000000000000000000FFE42800000000000800004C10000005000410008200002064160402D00A8488208320000148500400\n\t1060000000900202000000080000000002004882A8080200000000000000000000000000FF29310400000000200000440410\n\t0000004100000000000160D608808002042000409001011000008004E020080C04C48C000080040000340801000002000000\n\t00000000000000000000000000FF4FB800802000080001488880282188080882004184400021026240024800041020265022\n\t02282100002382802042082002A82202048002002101063002400000000000000000000000000000FFB0C8010401420441400030e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (860160000003\n\t0C0AE0000060060860AA00000210602000654E006000000000000000000000000000FFED5400000180180180185180180382\n\t1801000000880040202640400611012450640610400400635008608700610204600700600A02000000630108F2A600600000\n\t0040000000000000000000FF133B00000180181189580192086381006512A0488CC008052400414244042401414600614610\n\tE0280002060A601609E006006786000000006000406006006080000020000000000000000000FF511C000001801801881803\n\t841801800001054092810010400A04440A00000800600640601621600000620614604610620600600600000000600004601600b0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80080B821A00\n\t80400500000020008060000000860070060020468860002000068060000060060A600000000000E001806007802000000000\n\t000000000000000000FFF53C0000CD00188D8AB8AB8AA8858C806188804000002A80AA20622000002600680622220E326000\n\t2AE0542462AA2AE2AE44E00000000222E000506006002000000000000000000000000000FF137F000001101A038018018008\n\t2182008B82032080000040040C6800000D030060060020460868400008260060020060062262020000000068004B60060030\n\t00000000000000000000000000FF6CB400004385582180180180081580580100200A800000640001409600001400600609400070e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFEFD3000401901C01001801801C21814008024501000000600611500100101600600702630E8460000070\n\t86806006006006116506000006016041026846006000800000000000000000000000FF716C0005558C1D5515588595592191\n\t25541505518000552550CD555400144A0060064D64064360041515570B65565565564065560000045460142D653600600000\n\t0000000000000000000000FF3F6000008902B8A98AB8AB8AA88988190288801500002CE2AEA262A80002C600700629284620\n\tF0424AE2045162A82AE2AF0060280000022A700200E28E002000000000000000000000000000FF1C7A00020101180180182900f0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620000644C14\n\t628E00600640641600030600630000E546004000000000000000000000000000FF0902000001821A01801905800A25835840\n\t010010800002200002480680085200600680E09608681000080529600600600649600600000410E80022E546004001000000\n\t000000000000000000FFF52E00000190B8010018298008098000030402410000006406016004000102006806106022016000\n\t206004006006006006806006000006006010086016006000000000000000000000000000FF6F130002AB8058AB0AB8018AA8\n\t81880089082083000028A0A8A862AC000203006006226B17A270100A82AC4262AE2AE2AE0362AE00000422700080680600700008e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018158048018\n\t2100000040040041460000160000000060040001000060060260000060060460040000000000000060460020060000000000\n\t00000000000000FF5F220000898AB8A98AB8AB8AA8AB8A18A800000100002AE0AE3462A200022E0062AE2060420040E00AE4\n\t840460662AE2AE00608600000E2AE0600A60063A4000000000000000000000000000FFF8A300000180180180180180080181\n\t1804000121000000200000600E0001060460060461120160044000044160060060060D604600004400600440601600C00000\n\t0000000000000000000000FF128C00002380180580180180080180580000000C00000064060AC00200000628E0061162262A0088e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFDE1A0000218018018000018018010210210018C1000004000000810600008E00800009601412000400014448\n\t60000060060862540002000000040A6006002006000000000000000000000000FFA0950000AB8AB8AB8AB0AB8898AB0810C8\n\t00188D00002AC0AC2A820E0002262A82A82AE22C2A82082AE2AC40E2A82AE2AE20E3340002A82A828820E28E22A006000000\n\t000000000000000000FFC5E10001139559359541559559559139148018150000510550404456000446540550446304410484\n\t55000E0163105565564560840000C8550504416536452006000000000000000000000000FF7F3800000180180180100180180048e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000082806000\n\t02F016026006000020006024216006014006800000000000000000000000FFA64E000001801801800001813A0184D8228000\n\t0380000042040022A800045400000109621400020020600214608800600620601400001000630000E5460040060000000000\n\t00000000000000FF689E000001801801C01801D0180180181080081100000440040060000000060008000069260000140008\n\t024168408068060B7146000000006014406016094006000000000000000000000000FFA9F90000AB8AB8AB8AB0AB8658AB8C\n\t18808008A1000028C4AC2AE0000001862A82A82261042A80800AE2AA1062002AE2AE1062040002A02AE0001E60063240060000c8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5C2008482000\n\t001240A410E04024912E10010804610750008010E00002600100E00610E00614000000602021600601600600000000000000\n\t0000000000FF13E9002100001801024705811809001000C01828800024441420A0204300A608004021600610000001020E02\n\t7001406006086004000010006000006006006006000000000000000000000000FF12FC0000000118014234A1C85B01C5D800\n\t905800000000424C20200000000700111080E90640011816720F706981207006017404140008606100006006006007000000\n\t000000000000000000FFAFA9008001901801C00A21C81801B01C4180000180000841040C200000100C8000001460010080040028e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF7E110000008258318019018018818438830028418A000042040CC2000A00560802200240861002A010E10C00E000\n\t10600600600600000020E08008608600A046000000000000000000000000FF80CA0000008038018230018158038C18210A88\n\t91000062408424402000020E00004850402E01000808010438602806E01604640C0000400061000060060020060000000000\n\t00000000000000FFC024000000001809400889801841021011401835800008C04C0460880001460200001060061000002001\n\t00006B00507006006126010000006020206046206026200020000000000000000000FF02EC00A100111801001805A018919000a8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (044100000000\n\t00090310000000100000400010010000000000000000000000000000FF110400002000002205000000008401404A04410800\n\t000060060881080000000000000905400000004060A014000000000024000000000000810000854010000000000000000000\n\t0000000000FFA0C70000018018018018118018059018C10A8905800044408C01013000020600001012400600050040E01010\n\t6490206006006126008000006000086026202006000020000000000000000000FFB18D00000184182182580180194180580B\n\t0048098A001142244804001400860A042000412E00003000000021602005600600600E0000004160A02060860120062000000068e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A280880002A\n\tA2AA22222A0002020008002AA0AA0000000AA2C240A800AAA2AA22A002000000AAA00020A28A2A22AA000000000000000000\n\t000000FFC92800004A4000000904000004000002D10800000000000000008000000000800000000200000080000084480000\n\t0008000810000010000000800A0000000004000000000000000000000000FF585B0000C90AA8C91448AA8AA8588A48840989\n\t0680002AA2AA2342220003220000002224020003004AA20A1020002AA2AA1020720000002223001E20022222AA0000000000\n\t00000000000000FF39790000040000001020000000200000000000200000004004000000000108000000000008000080006000e8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF4211800080CAA8AA8008AA8AA8AA8AA82080080080000AA0AA2022320002AA0000002AA0020002000AA2120420002AA2\n\tAA0022AA00000022A6000A20022222AA000000000000000000000000FF99C900000140100120040120140204841100002000\n\t0000000010410000005100080000000000040000001402080080500400150000100080020000004001000400000000000000\n\t0000000000FF5E3C000101955955845D55D559559558058538B380005563564A45460005560000005560D600020055744401\n\t600155755643655600000054E00041653654F556000000000000000000000000FF502300008A8AA88AA088AAAAA8809008A00018e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004003000\n\t0800000000000000000000000000000000000000000000000000FF62F40000A0002200056000000000000000026008000004\n\t82000000400000008000008E0000000000800000000000000000000800000000910000100001000000000000000000000000\n\t000000FF299800000200000001440040000000000A02009000000002000A8000000000000000000048000000000910140001\n\t001000200000000000000100008540100000000000000000000000000000FF36260000304000001400000000000001001120\n\t2400004000000001100000000000000003000000804000404100000000000B000000000010000040001001080000000000000098e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (110000001206\n\t0060060060060060070860064060004471174165045568541004260000008060000060000060000000000000000000000000\n\t00FF05E004014000100100400000111100000004110100000100040040000440250012840440040040010200848018040000\n\t04400020400001000001800001008220000000000000000000000000FFB895040002810840A80800400800800850A0080000\n\t0000080200200202200000280200200220200022308A21228231200230042220000000200000200080200000000000000000\n\t0000000000FF411F0080000002002000002000880000000000800000000000000000000000000000000000000000000000000058e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t7592000000A00801800800200800800800801801800000000600000200600200200600600600600080200200200200308200\n\t0002010000002000002000812000000000000000000000000000FFF1EB000000200000200000200000000000002000000080\n\t0000004000000024000500000000000000000084800804200005000020000000000000000000000240000000000000000000\n\t000000FF652000000080080085480000080080080080080080000407826020420020020020021C2002002001042002002002\n\t202083000002008000112000102000002000000000000000000000000000FFAA41010005813841101800001801801851C03000d8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04622822040E\n\t000000A06080427000006000000000000000000000000000FFDEDD00008000180184A80000180190184500808A000000002E\n\t10640600600600600600610604E00002600630E00820600000002600000000405000C0000060000000000000000000000000\n\t00FF7E1800000000000000000000000000000000000000000000000000000000000000000000000000000060000000000000\n\t00000000000000000000000000000000000000000000000000000000FF4B6900000000000040000000000000000100000100\n\t01000000000000000000004000000000000000006000800804004004000000000001000000000000004000000000000000000038e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000010164060\n\t4600600700200704604600601040000E006040006004421006000001404080016000002000000000000000000000000000FF\n\t3A570000D1065864000802011823809AEB0032080400000026086207116026154406006A06A26000020816B8C20CA0C00040\n\t0704010000506028306900002100000000000000000000000000FFA1D8000001201A0080A800021801881A00A61822000100\n\t0806406006006046806A0608648600E00000688680648403622800082E000000006000026000002000000000000000000000\n\t000000FFEBEF000040041840A0080242184D855891802220000000000600604600600600420712704740600840008E0060A100b8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFE408\n\t0000C09DDA8008784042181182504301D019040100000600E00611620605008610670608E06000700640441682D007400404\n\t080600506000006500600000000000000000000000000000FF0BB2000013801922A09804031801821005001001080100004E\n\t00F80600640610248600600601600020002610C0070540460000060900000060A02A60010001000000000000000000000000\n\t00FF2DCF004004A01C00251822401889803000803081080080002E00600780610600380609610600600024702620F2080070\n\t240000040000800240C0426400000000000000000000000000000000FFAA86000021801800A41800401811843800409100000078e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8F8802840000\n\t0000E008024000006000000000000000000000000000FF438E18002185181800505804184980100830989000000090078040\n\t0400600601000600600608618C6000E608600278E406450044000000686005104000186008020000000000000000000000FF\n\t9C920000A0801C0082100000180382102900192400000001060040268060060008060060060060000061060A480200400200\n\t0006000000106200004000806008040000000000000000000000FFC3CE0020808018008C1000001901801800801900000000\n\t000780400600610600000600E00610600402001600600200600280008600010002600400400000600000000000000000000000f8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001600424600\n\t62060A000601608680608E80040600518E00492600064C008000016006066080006008200000000000000000000000FF75E3\n\t000002801840201800015841B15009009C48008050090604400610610640209693600610602080602608C204004110001804\n\t000309834088007040047140000000000000000000000000FF0188000500841804045800001801801800801A140000000086\n\t20400600600680A00600740600E00400000F0450040452102A810400000000420C0868000068000000000000000000000000\n\t00FFE5C7000201801802001000001811801000009800000001000E20400780600600000680EA0610E010807A1680408203480004e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF023B0000\n\t8108104000900180180180180180000100800068060460060160020060168060060060140000060060140010460068068001\n\t000160048061060840C8400006000000000000000000FF9D7B00205501109102104192D8458B5A0990104100015460060044\n\t07086480B4600615690700692000684684F30480000E006A168082000260A8006046044000000026000000000000000000FF\n\t7FDB000020849888009800001801801040011810000002090680400700F00680010700600610600060600612500600410600\n\t0004000010006020046000086000000020000000000000000000FF6CFA0020888B18004218600E1847C610615818400000800084e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (684610010800\n\t6005406006004000000006000000000000000000FF2ACA040001001089003001801801801881801001008000620600640600\n\tE400400206004506306420006046006004000006006406000000006000006006004000000006000000000000000000FFFFBB\n\t0000010010000010018018018000018010018000000006006006006002006006006000006004000006006004000006006006\n\t000000004004006006004000000006000000000000000000FF00170000010010010010018018018004018018010000000007\n\t00600600700080600600680000680300680680600480000600600600000000400200600600400000000600000000000000000044e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A62BE22E08E\n\t22E3CF4876AE2AE3A000E1BE0A64AC8096A6026226080001006000006146144000000006000000000000000000FF53E20000\n\t00801820801841811801803C0194021194402062D640E4C708650600200A09610201680400000620604600800600E0060000\n\t40004004806006006000000006000000000000000000FF6ABC2200000010022638018A189F805801803001000080680700C0\n\t06006206002002806012016800026206206204020006006006000080804000006006006000000006000000000000000000FF\n\tF8AB002201801A038090018A1881B298338CA2090C404CE1524AE0B624612A03014E0D7026026084C485165265560495460200c4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (68EE004000C0\n\t1930A31C01801801956245911A1180000402060060060060460070420D600400600040100600600680000680680680001000\n\t6000406006006000000006000000000000000000FFF999000001801801801001E01801800401901009002020002E01624600\n\t620600601600600400600000600600620600820700F007000040006000006806004000000006000000000000000000FF965F\n\t000200401200601821809801A01A01C214031400046086C0408E8861060070A221628600E10080008E206044000006006806\n\t0000000060000070A60A6000000006000000000000000000FFFA9E4000010010010410018018018018898210050AA02CF2AE0024e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000004000\n\t00600600600000030E000000000000000000FF78BF000210A2BA8BAA2C29A11B218A0109A052118000480D2488603632EC2E\n\t8CE8C28A6AD0126810890C0E0068AE0A00A6286906000000D168A08C6D46896000000826000000000000000000FFB6C60020\n\tA3881801800801823803800001A910A3800100000C25610600610620221620E0002060000460864B620620020E0162460000\n\t0000621021600E22600000020E000000000000000000FF1E6900000100100100020180180180000180180180000000040060\n\t06006006000007806000006002000806006004000006006006000000006002006006004000000006000000000000000000FF00a4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (070020522222\n\t021420028420000021030020020010168060E2000000042000082012602000000002000000000000000000FFE5FD00000000\n\t3008080000500060100000008020000020122000008108812C50C0248A4E248201501270005187A04A04E800820000000039\n\t84B80081C8050000000000000000000000000000FF7A0F0000200401000000004000000006000421020000400010000860A0\n\t00800401000101008000000072888A0010200A008C0000000000000000020200088000000000000000000000000000FFD7A5\n\t000082809847870829829801A80009890801800090004C40400600600600608220E05020600000E40620604E0000062064060064e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000101021911\n\t8099018018218A1051821801800004C0360060868060B652690601608442602804600640E286210006006106000000156000\n\t0160A6226000000006000000000000000000FFA491000420D00C42CA0C00920800800900C10CA4800050310340204A013803\n\t003003943C4A803101082C9210303210043202342200000100341148300B00A000001102000000000000000000FF5BD80022\n\t092A02102000000424822413402002C800000501808A891803520088100800008C4848088C00148048009108000009000000\n\t00800A00F10020820000000020000000000000000000FF1841000140900880902900800C00A200908008048001084002203000e4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010014030010\n\t01000000001000000000000000000000FFD4610008A80AA0000880000AA0AA0200000000AA00000002A82A8008AA82A8000A\n\tA82A82A82A80000A82A8000240000208000408000000020000088000020000000000000000000000000000FF1CC4000004A0\n\t0A08A00C00C00A00B00A22B20A008000802802802C22000802A82002802802802800C02802A93002500042002A2200000090\n\t2800C02802A12000000802000000000000000000FF22350002014002A222400120120120D309212200000000480100090400\n\t4000848000000004004B008000048448C8848904004900000000A10A80840000880000000000000000000000000000FF3AAA0014e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000800000\n\t0000000080000000290000020848800000000000450000208000400000000000000000000000000000FFE0340000480AA000\n\t08A0000AA0AA0AA1000900D200010002A82A82A82A82A82212A82A82A82A82802A82A82A82482A8A488002A80000002A8080\n\t2A8000228000000000000000000000000000FF8B3C00011415434C3542003541543002023243540000800D50D40D20550D50\n\tAA1550D50D50D50A00D50D50840C90508500000928000000880B008C0800930000000800000000000000000000FFE5B90008\n\t00400448440400400400400404400400000000000100100000100110000100100100100300100100110100080080100000000094e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (502012012004\n\t01401201200308248248000000000080080000480090C004800800800882C010048009148000840048000000008008028008\n\t00880000000800000000000000000000FF434700000400094484480080080080082280090480008020020020028020020028\n\t02002002002400002002002042000852002002000000002300002002052000000002000000000000000000FF30BE0001040A\n\tA10C0880000AA0AA0AA0500C600000000002A82A82A92A82A82302A82A82A82A80000A82A82A82002A83008002AA0000002A\n\t80002AA002300000000002000000000000000000FF6B9B00082020000000000000040002C1280080000000000000008009000054e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200104340200\n\t2000041002100000000000000000FFEEFB400D80418400400412400408400400400400020100100100900100500100108100\n\t1409021300001301019121001115124000000000001088008138000000000000000000000000000000FFB2204024004C0C40\n\tC00C00C40C88C00D00C00C02820100300300300300300B00348B01300B053002003403103033411403032002000210003092\n\t042002202000000002000000000000000000FF33A300000400180100180580184180184B81380180000060060560060860C6\n\t0060260A600608620002602C20640600002600600600004008600008E426006000000006000000000000000000FFD6E8000100d4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (406046016006\n\t00E00000E00000600600000600600600000000628024E1460060A0000006000000000000000000FFC82F0008000240001140\n\t200CA14002002000012800A001008012E0D60800500880000202004D004008E4002A02800802000800002000200003001100\n\tA0088030000200000000000000000000FF36B7002002140000000000000100000113003003000000000000600608014C0002\n\t080C42040840800061542003104100A00080000000100800000C0480200000000000000000000000000000FFB61C00000000\n\t0821800808820820804820908800840010200202200240200240402641A10200A10002200608200640020A082842000220000034e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (580801000180\n\t1801811801951053000001201640E00600608E0540060160AE00608020000000000600000600600E00000008000028648641\n\t0000000286000000000000000000FFC20B00000002180080A003883801809820023889000000A02E2365060A610601400624\n\t648604608010624032630620020600702640804000400100700608C000001206080000000000000000FF0E7000098000D898\n\t86080381194180800E03B841080020612E2062460262D21047A6186066506640000020006006100186106006008000006000\n\t306406006090040006000000000000000000FF9568000000011901880841821801822008081801954050600608600E40620200b4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08F286208000\n\t000286000000000000000000FF2890200242001908841801801801C03800089000000080004B00600680688204C116007886\n\t006000000806806006000806006026000000006000016226004000000036000000000000000000FFCE1E0000460158420018\n\tAB8AB8AB8800AA80018400002002220162AE2AE1042142AE6262062AE2000AE2AC2A8C560002AEAAE08600000003A0004060\n\t06080000000006000000000000000000FFAFCA0000100C19408A5801801801A4200000200000001401028C60060064401050\n\t069060068068000000040062CE000006006246000000206D0003603602400000002E000000000000000000FF364A000140010074e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0E2AEA0E2AF0\n\t840A9AAF2A82AE801AAE2AE1060000002A90041060062AA000000006000000000000000000FFDA19000800081A0490180180\n\t1801804001204A018000803000006806806043124806006106006C0000680200710600080700650E00000024480004605612\n\t600000082E000000000000000000FF3CE2400410155822913955955955948154823955800054A480556556556432484446D5\n\t644ED56284550552557556000557556216000000554304446116556000000306000000000000000000FFCD35000088021910\n\t42B8AB8AB8AB8A98AA13083000002C82B33262AE2AE20E4002AE8CF236AAE0802AE2AE2A80070002AE2AF02600000010228100f4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02B801801801\n\t84D901910021800000208200600600602E00400602E0060160020060A025000600000600640600000002200008E126002000\n\t000446000000000000000000FF0909000050001C4022180180180180B800C93401800002201280400400608E835246806026\n\t806A04000000000006000006006A46000000002B04436A2E002000001356000000000000000000FF7A4C00008400190A0038\n\t01801801840000041001800010A5200060060060461041060040860060004060060008060000068060960000000000008861\n\t06002000000006000000000000000000FF6A620001000AB8000898AB8AB8AB8800AB8010AB8001A028002AEAAFAAF2062050000ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (564920000000\n\t16000000000000000000FF4EF6800000001005004801801801812805805001800000401000600600600E0440060060060060\n\t00006086004000000006006146000000002002006006032000000006000000000000000000FFEC430000000AB8000818AB8A\n\tB8AB8C580000011B800022A2222AE2AE2AE2D60042AE2862AE2240024AE2060802AE0002AE2AE02600000020A00200600628\n\t2000000006000000000000000000FFBF9D000000001894001801801801801833822081800010200A0040040060062D400600\n\t600610600420001600000600000600611600000008200422621602A000000096000000000000000000FF2803000000001820008ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C2AE2AE0000A\n\tE2D64042A80002AE2AE026000000110000746006002000000006000000000000000000FFB716000800000031032801801801\n\t80082115180380001120100060000060862240060260060260060000360A40020000060060060000000820064A6506022000\n\t000546000000000000000000FFCAA80000000AB0490A88AB8AB8AB8A088915188980002A82A02AE2AE2AE24628C2AE2AE2AE\n\t2AE0002AE2060B42AA0002AE2AE20E00000042200000E52E48200000054E000000000000000000FFAEA50000001540851009\n\t55955955908912003841800044454055655055640611455628E5563160041505064145500005565564B600000044A0040160004ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (05C11A82001C\n\t230018018000006C00206201106826027226C8BA0320620408000600E410A0210702600600002800C0040160060060000000\n\t06000000000000000000FF2FDA000800000805044801801800005900111A03800010410000600600622E4360060020020060\n\t0040602E44480000200600640600000014400008E12610E000000446000000000000000000FFFED7000000201131800801A0\n\t1800040A32023801800003400800600100600690480600400700600400080610E000001006006116000000208004026216A2\n\t2000000096000000000000000000FF6AF40000000AB1010888AB8AB8AA0888410018ED80002042202AE2AE2AE1860042AE2A00cce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C48000000640\n\t0000000000000000FF8D3A800000281001800009A0D852000A419018880080100400040430C0600600408E0C805600605048\n\t6316C4641201000600600600000000A000016006000000020006000000000000000000FFFEC58400A0100811000011805E49\n\t840800001088004008400004784020700780608780210A00610824190F204002003006006006000000006000006016004000\n\t000006000000000000000000FF6E79800880407009020101C61A81820A0290120001204050400061970071870048172432C6\n\t9662C0027406044901011086006006000000662000066006800000040006000000000000000000FF2A6E000000400801820C002ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (10420000000E\n\t00600410200600601600040040604052E3464C6210000006400000000000000000FF80340000000018018700218238018018\n\t00001811088020240808608600600608E0C658C0220F420008600E04600600200601600600000000400222E0060040000000\n\t06000000000000000000FFB1AF04004000102300818D8018098AA88980382100004022C04262081260C604446600408650C0\n\t02000006014104480006046006000050000022006036200008000006000000000000000000FF282E80000000091190420581\n\t1800000821131808022008A000210006006C560068162408034060C004048623600A00308701600E4002004060000863060C00ace040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000103390\n\t5085000050000002600600000640000001400600040000600000C41454000000011000000010030042021002800000009000\n\t0000000000000000FF9D0D80000000200A00200000003200010001002000000280000060260000000C80000C000008008020\n\t60001400C0000000000400000000050000088120080000000440000000000000000000FF5AAC000000001945905809801808\n\t08DD01005821804008208044021000724600600E0091024041200A648640E00E00610600600620000000600000600600E080\n\t000006000000000000000000FFDD050000000018118008A582D8000408489298010C8021201008810604609610E106020042006ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000016000000\n\t000000000000FF54E00000002D4840882CAAAAA8888AA88888484080000820002AA48AAAA2AA10A2AAA8A2AA2222800AA2AA\n\t00248A082AAA2AA20A00000022208020A50A28A00000054A000000000000000000FF73EA1000000080000A00000004020204\n\t2000002000000CC0000000000010000000040A51008001000010000000802000008000000000004000005205004080000005\n\t40000000000000000000FF356E0000000008B08A18AA8AA8848AAA40820808800040200028C28A2AEAAA0422AA2432AA22A0\n\t000AA2AE21200200E2AE2AE022000000312000142002242000000002000000000000000000FF44450000001300010080000000ece040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004000000000\n\t10410000000110000000200000220210320000000090000000000000000000FF32EC81000000A8AA8188AA8AA8D2D20800EA\n\tA8A8800020A00028A08A2A82AA2AB2AB2030822AA0000ABAAA2AA2220022ABAAA02200000000208000200204200000000200\n\t0000000000000000FFE0BC80080020010404920120144000040444828C000005400000404080500040100480480110800240\n\t1004541020454805004140000000000402000040000000000000000000000000000000FFC16B800000123D55803555D55901\n\t80BD13B55F138000404000554557557556556D5640C456556400356557557C5614D5565564B6000000156480016036086000001ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000280200000\n\t0000000000000000C00000000040000000000000000800000800000008000000000000000000000800000000000000000000\n\t000000000000FF07020001000284082000060020200002000000081000200000C00100000820180808000000001000000000\n\t000000000000000000001000100000400800000F00000000000000000000000000FF4C271000000400000000000000084125\n\t0000020000000200000204408010000000011110280004800000010010800C08000004000000001282001081200100000004\n\t40000000000000000000FF12710080001002000C420020002008003200000400000800000000000000000008000204000000009ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800000000\n\t00000000FFEE2D00000182100D801801C01801801801005E898080206016804006206026007027406007106000006406546C\n\t06504114010006416106006000006806006946000000000000000000000000FFE1F90000180114210210452040400001AB00\n\t020000000A028C024000205085D0021C80000000400000080000400400400400000000000000000080008002040000000000\n\t0000000000000000FFAE37000410A00C04800800800800800800A04880810000201000200300000020200240200308200000\n\t22024A320228208200800240A082002000002002002126000000000000000000000000FFE19E000000200000200020000000005ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000000100\n\t4004000004000001000000004800005000000000000000000000000000FF7299000000803800000800000A00A00A00800800\n\t900000200220C002006002002006002002006000002002002006002806000002002802002000002002002080040000000000\n\t000000000000FF066F00000000004120020008020020028D000000000002050D040101200104000C08000000001000000000\n\t005000004800000000000100800000000100040004000000080000000000000000FFBCDA00031080280085E87C8868008008\n\t40806800800011A00280A003002062102002002002002000002002002003002002000002002082102000C02002002C02020000dce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01051004A000\n\t0460168000860064060461060C60164861084200060460060000000002860068062360800120464860060400400000000000\n\t00000000FF95F1000101801801801801001021023041000901800000610600000002610601600600E0020460000060060860\n\t06040000000006006006100020546006006016000000000000000000000000FF41F300000000000000000000000000000000\n\t0000000000000000600600000000000000000000000000600000000000000000000000000000000000000000000000000000\n\t0000000000000000FFF957000000000400400400001000001000000401000000000000600600000000080000400400000000003ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF4B09400140820801009801905800855841001900800004600600000E0061060100070160220060084400060270070A\n\t000400030200600652C00015202440A004000020000000000000000000FFA48D000001000218A0580112100180501582180A\n\tA000C04116C060001262060264860040060260000000272870070040000000280440068160B021241000241C020040000000\n\t000000000000FFBDA920000980A8018078210010A1801019809811800080408E0060960060068068068A604A286080006046\n\t40600611C000000052806006804000002804092804000000000000000000000000FFF1A000004984CA11C118210A5101809000bce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0060060028C2\n\t000086006006000004006006006408040000000000000000000000FF189C000201058000015A238028919248010093A08000\n\t49E01600E04602E7D60248061042072060000160070060060272A6000600F540860161000124000000064000000000000000\n\t00000000FFFCD7000000000600001823882900820805601800800188780640780000780621500602DC064070020000060062\n\t0604640600000100788480400A022010010006000040000000000000000000FFE9E6000001842801409C0180180990190100\n\t54008000006046000221206036A0C0560AE00300600041604780720600000400010211480700610004200400800442000000007ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (980082000861\n\t06006027A0600600600603500608EC0002600648600600228600000600400400620034600200600200000000000000000000\n\t0000FF80A5002221818841B018018190011991D4A09822820000600682601800680660600600616288620000000680625600\n\t200604000680400F09400081E006047842000000000000000000000000FFC0A8000100100008A358018000018000008008C5\n\t802000E006046006806006007286884006006004006006016C0600200200000702600E102084007002007000000000000000\n\t000000000000FF3E5B000200802809801801800001000088814021800000612781640033600602622E80600200700420002600fce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF1B5208000000005288980186C00108E055801082804083610780600000E807A0E50601408781608C020087007066007006\n\t0000060442240961A414200208606E000028000000000000000000FF5B520000050001108218018020008000118B28209000\n\t107006416246047116107C960950061060040160260860160040000000074041060220054020320170042200000000000000\n\t00000000FF439E000100080200935801800004000001801080800010680600602040600700600614410600700004000628F0\n\t0E005500020006004006000200402002046004000000000000000000000000FF9D71002221000000A01801825003805000A00002e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060040060000\n\t00006006806004006006007006006006000000000000000000FF25E9200001200009821A8B040A0000120081180188000060\n\t1600640015610650220600E10210600400080600604600400600000000680600600400680E0160C600604600000000000000\n\t0000FF8373280005A05083811A0100AA10091A10841125800012600701604600600200814E10600300681404E12488710E10\n\t4006010000406336346144406446506016046016000000000000000000FF004D00000100220090788B800009804001905800\n\t800060600E40600608601600602600400600610000700400708608600600800600500C2060000032022660864000000000000082e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80000AE04633\n\t60804A602688828E106306106420408486006006145486408000016006007000006806007006006006000000000000000000\n\tFF123C040001881001801809000801011804810111804000601600601601640E400046416042046004046006486006004006\n\t000480006006006004006006006006006006000000000000000000FF6E0B0000010000018018018008000000008008010000\n\t0060060060000060060020060060020000000000060000060040060000000060060060000060060060060060060000000000\n\t00000000FF7967000001801001801801800800000800800001000080600600600600700680000600600200080400600680000042e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF45\n\t4700000180100101180420080083380280918F80201A64A608E08E2AE46E3884AF88608202626020F2C62860064A52862082\n\t80008006806401006006406916006106000000000000000000FF69BA00000100080180180103190000113181005185402561\n\t57456550C561160081564425565123140400060425460165560000000561560060AC00600602E00600600600000000000000\n\t0000FF91EE000001000801A01AED0018141818819060018000606106006006806A0600080684220200300698680700200600\n\t6006000800006006006006806006006106006006000000000000000000FF1D2A0080018410818019010008012452A080080300c2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (580600000000\n\t2006006000006006006006006006000000000000000000FFC7A1050001140901409806A20815818A6090088100002B601664\n\t080602600488340665204638480004002600500600E006000000002006006800806006206106006006000000000000000000\n\tFFDC48000601801601001E00800801801810811821820000E40F00100040600700A12E806886005220026006004406204406\n\t0000000000D68072A9006006006086006006000000000000000000FFE0B2000001000801001A00810900800B0080080B0120\n\t0060A60562B0016ACE80220604225200E8900000068260A60060B600000004800600600000600602E00E00610600000000000022e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (284236000000\n\t22600600640601200E0000000064022000060A600600038040601628600000620660618608600E000000000000000000FFED\n\t170202D5A41D09921A00334B05289A48A083438000AAC4B68008A6AAEC26CA60969328B6880A808888AEC004C68460C60002\n\t80A0692EC8E84084ED0EA46A16AA680E000000000000000000FF0778000001891821C1180880184144388584400980000040\n\t0741601600609601524620220224000900640609000E28E0160010000AA00602748850704608F94600E32600000000000000\n\t0000FFFF34000001801001A01801000801001A0080080180000040070060000060060048060068038000000000078008060000a2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFAF7F00\n\t00C28308010088008108608B09A8802900800000300600400200600210300250220200201001A0A20868A65028020000001A\n\tA00212A00010A0A2022002022202000000000000000000FF01EE000020000048020100025003140003029018000050108800\n\t601F00030868402828413422438010634100C1482080080000000140A8000210280540100228500080000000000000000000\n\tFF6DEB00010008012044000014811000000010000000000008000160270004200009000280C0190008006010510A100408E0\n\t0000000000000100A8000000000000000020000000000000000000FFD7CD000009809801A8581488388100901581002180000062e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000A80940C80\n\tB00A208008C0A90830000000000000000000000000FF535500014994192182190D841901841905801909800020610608C00E\n\t00650650681650E0060940000062D60144162460060000002160561060080060B6006106286006000000000000000000FF90\n\t21000402C14C00A14E40C92C32C90C10D48C40800110201300308208380B00A52300314B2035091530034821430820220001\n\t010A330300B001083403483203003002000000000000000000FF4CF60202143442804104482002042022002402C200008281\n\t00B08980189090838AD4800800C04C008C0808000C00800804000800A40D40800800820818888C002080000000000000000000e2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010010000018\n\t008410010010110010010010010010010088100000010010010A1001341009001011001000000000000000000000FF178900\n\t08200000880AA08C0880A00CA0AC0200AA00002002A82880882A82A82282A81002A82A82000A8000AA82A824020000000000\n\t80281080002A8200000200000000000000000000000000FF8DC0000400A00800A00A00A00A08A20A00A00A00800000280282\n\t2C02800002002802A9280300280080280A003002802042000850A02802842800802812842882802802000000000000000000\n\tFF9C7300031234A4450010422222042002023142000000930804804820804000900004840801004840C00B408050048C888C0012e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF8DB000082C\n\t00802000002000213000400008A0000000000000000001001000090000220000000202200489000000000828000328310220\n\t0402220000482A00A0000000000000000000000000FF37030000880000CC0AA4AA0820900A008810002A00002A82A82880A8\n\t2A82A92002A82A81402A80002A82A82A82A8280A800003202A82A82100080104A02C82A0000000000000000000000000FF6C\n\tAC0003002A41123543103502043103282203540000550D50D30D30550551440D50810D50D50820950840550D515104800008\n\t00840908C08800D50C80810C10800800000000000000000000FF2715000C004C2400400000428440402440452480000100000092e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (164860260060\n\t00006016006006006006000000000000000000FF07E800045120422020000021228420C20031024A0000800800844A208048\n\t04004800800D008048008008008048049041040000C0800800C10A10D00950890800800800000000000000000000FFE84400\n\t010094091000080080083084082484480080000000020020020000004B000200202200200040200200200202204A00001200\n\t200202200003220202210A002002000000000000000000FF34010000460180020AA2AA0A000409008C00008000002A92A82C\n\t84892A82A89102A82A84082A86180A82A82A82A8248A400002102A82AA0824000020022022220020020000000000000000000052e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200600620\n\t640214A1022121000024421025860860060000021DB02300200906360B00332310B002010000000000000000FF1643400C01\n\t400400400400000008000400460000000000100135400120100108101800120100D0000B8081005001001200000000000008\n\t001020000000200000400000000000000000000000FF6F87402400C00C00400C048C0848904D00C108008040001003002023\n\t503403403082143403003040122083113513003002000002012512053050142422402522012002000000000000000000FF1E\n\t7501000184180004380181180184185580180190000000064040060060060C6006016046496000206026026006106226000400d2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D80000098208\n\t0A04180000100A001801004049080000000C40812800E00E00640400210802602800600600604E0060060000060065060064\n\t8008602E02608E08E006010000000000000000FF864500080004002A0100C4108004002014100108088000041045604E0000\n\t300000900004500200000A60100000100100200000000002900905001100304200402100A8000000000000000000FF8ACD00\n\tC00002000002000413002002314D011001080000000015604608020002008014002410002040604014820800002000021020\n\t0280030000100020000100200000000000000000000000FFC8A20000101009000028008008008809008048408060000042100032e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400E24680024\n\t60B61462160460AE000000000000000000FF96F30000C180504200111200180380080113414B000000000600640000600620\n\t600400200004E00020030C08600624600600000420052610E04008E20640E046016406000000000000000000FF0DCD000001\n\t80184000190A0918A180D8210A088500002000260060064260260061044A200000E30015622608E306006036400006005017\n\t5160010372070070074070AE000000000000000000FF10AC0008019069000318480018A81889350388030140200406140086\n\t22E60619E07420244000622800801600E02601600E20000675600620607860618640664E006006180000000000000000FF8C00b2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AF09720E2AE\n\t2AF2A92B60422AE2A430F2AF4A72AE0000042082270260020260070A702702EA06000000000000000000FFF20F4002010050\n\t0000088982480B808810AAA80080000010048060000071460060064060010060000001061260070070060000061440060060\n\t000CE22614EACE00E00E000000000000000000FF375B0000430408C80AB0118AB8880C4AAB95510180002A0AAE2880A82AE4\n\t0E1262AA2AE2A8A060200AE0042462AE80EAAE0000040E0006006040106006016086786006000000000000000000FF8F4F20\n\t0011128A0000082180084002C8018018018000010006040006006B26097002006000106800000046856006106006000006010072e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (06AB8428AA0A\n\tB0099010800008010008AB00002A82AFA8E0882AE0062272AE1060003870000A80042862AE2AE2AE00000420202617701080\n\t6806026006006026000000000000000000FF8AC3000A01A04404000805801800101800001000000010000480604680602604\n\t68060060000068000060170060060160060000061070963168012175364062960060CE000000000000000000FF4C49000155\n\t910D541548258091400C3D4240095400005505565565305564164D655605635044E0145504574165565565560000064164B6\n\t406004406116207006526526000000000000000000FF265700008D0910880AB0A18AB8AB8108AA80003280002292AE2AE28E00f2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (016024436296\n\t0560460D60A6000000000000000000FF63890000418050000D5001840811800804114000000000008E006206006006006006\n\t0940000062C00065000060060060060000CC14230630628008602608629620640E000000000000000000FF60AC000001C492\n\t000000C188402984488C1348000000000006046001006806807006154D080570100000008168060060060000040C208E0070\n\t0003622E296296316896000000000000000000FFC2E700000190000000100583180208884100080100000008060064460062\n\tD6116006406040806000406334046006806806000004012C06C8E008486106806846846406000000000000000000FF599400000ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (545564C25325\n\t505565441504365565565565560000404520564165240160562D6056056016000000000000000000FF752C80000080000183\n\t180580084D845801800841800000200600620600600400601210000000600840600400600600600600000000200600600000\n\t6006506086006006000000000000000000FFEAD400008980100000108B8018818AA8C8020088000000020428E0AE2AE2AE2A\n\tE2262062A82AE0000AE1002AE2AE2AE2AE000204202006026000006006206106006006000000000000000000FFF6A8000003\n\t8B100000002190D043800820001844000000004602600000600600609602600000600420002800600600600600000400A056008ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (890001981889\n\t8008800200C797408180000062AE28E08E2AE2AE2AE2022202A82AE0000AE2262AE2AA2A82AE0002A841A506346000106506\n\t206006506546000000000000000000FF4D8D0008208C20010818058008018018008AA8000000006306006200006004006012\n\t0060000000002000060000040060060002880822860A60004C62860064062862A6000000000000000000FF9BD90000AA8A20\n\t018038A98AC88188988880088B00000062AE2AE0AE2AE2AC2AE2A222E2A82A82800AE32E2A82AC2AE2AE0002A80C202E40E2\n\t8844E02E02E42E02E00E000000000000000000FF9B6A00011281000105593192A95395591580095580000060365561305565004ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8100E1E70260\n\t06006006000000000000000000FF15C300000180000145180B821834094481C20000000000700640E00020610F00602F10A1\n\t0808A504440007003202003006000001106006006004816016806006046006000000000000000000FF4A5B00080080000104\n\tB843915830114009914422000000680602602600680600614710A0000022882060870028020008060000000C630610629010\n\t612608629620640E000000000000000000FF36C900000184C001A01801C40802400041800011800000600600620080600600\n\t680A0008008060000000160060028020060010002020560360004362160560460D60A6000000000000000000FFBB8F0000AA00cae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620620300100\n\t44802000070050A012E90E12000014C00612635032602E006446306026000000000000000000FF79808080010C00A9809901\n\t800814014511014901840001682E04000000600EC1688314200200428044602610401000E006000000900086006000006016\n\t006006026006000000000000000000FFCE2780804012008B005881C08C01801820012801820000644604600181604620F086\n\t021001006000000046086016006006000000404016006000426006046006006006000000000000000000FFF58C8008000000\n\t41C2380BC20821A81811020D018000016A1600640714E8260076234008810660001860068668070168060010002181066061002ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AB8008050108\n\t0002400188182111204462D633044600602620604A10A10800000040003640040001600600000004641654610041610E3564\n\tC6016406400000000000000000FF1C1E000005800021800109001801803801000821808022602E00602601613620640E0880\n\t8808840008E02E28834C14210604000000426E20E45004604628E08E40E006000000000000000000FF86EE00004080000582\n\t00010108018898C100A8898A2000600641640056630600603241003011000800000600040400000600000020001600600044\n\tE086026006026206200000000000000000FF92C380000300010B291883C52C20040000280805800000628632848E2161121000aae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (250220200250\n\t2542000000000000000000FF0B0C00000002110002000400102200204C0000420000004000026006000000000004024D3600\n\t40C00060200040145040000000000080500100004302D00500400D00A0000000000000000000FFB24880004008403400C040\n\t00001000800004400000000000000060260000900000004900000880004062800A00A0050000000000040300100120000000\n\t080290200408000000000000000000FFA1D200000180080195080902584010810180A88D0200006006000108246206106006\n\t20284011008808E00611001000600E08000051600600E00010600600600E146026000000000000000000FF6DC80000018000006ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (516556CAC280\n\t55655742C4145065560000001560560160800160562D6056056016000000000000000000FF94E900008890280A89088A8AA8\n\t9088C8A088A88080002AA2AA2AA08A2AB22B2AA2AA08AA022920202AA212A8228B0822AA00000024A02A40A44044A02A02A4\n\t2A02A00A000000000000000000FFC73E10800000000002000001402020423020128200000300040040000002800000000200\n\t000000100000000810A00088040000002002804A00004C02800004002802A0000000000000000000FF25590000CB00984088\n\t08C80AA8C08A08808880DC80002AA2AA28868A2AE2222AE2AA0020042262020AA04A20E2464122AA0000003825023622021800eae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000024000204\n\t202009408800004A00000000000000300001000000000000800000000011401010000000002000500300004302D00500400D\n\t00A0000000000000000000FF64FC888000CAA8AA88C8AA80888089880080082080000022A828A4CB2A80822A9003A03AAB22\n\t22080AA2AA2832032432AA000000002002202618002002202102002002000000000000000000FFC87E800805049100044001\n\t00000442041242140000000000040040410049008040002208B504450000008084D005020804000000000000000100000000\n\t500080000000000000000000000000FFFB2B80014B955155911955D4190B9419038D58298001487556554116D56057556356001ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002002002022\n\t000000000000000000FF0F0C00020A0000000000000000202000002000000000001808800000000000000000808080000000\n\t000001800000000000000000000000000000800210000000000000000000000000000000FF423C0080000200020020202000\n\t1028800002000000000000000400000000480080100804000000010000000000000008000000001000010000004100012000\n\t00000000500000000000000000FF5A0300013040000000400008403000011404000400010088000204210004010014300B00\n\t01090000200001030010850000000000148300100100080000080290200408000000000000000000FFCB9900000400000004009ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030020000028\n\t0200280200200200080210200200208101200200201221A062000000000000000000FF91F3000003925901841801C0182580\n\tD801801801840000001640404604604640400600ED5654410004655600454605510600004600610700615044600F40600600\n\t6046000000000000000000FFE4940100110A800560404000100110A0012C200000000082AC08400080109003C80010000000\n\t4000000808004800004004000800000000800000004504824008001800000000000000000000FF03BB000400904880820A00\n\t800804804800800A00820000000120202204282240200280224A34208004254A0024C204A1020000420020820020A9242082005ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001000\n\t2002010000000000006006000004000800000000804000006004004800004800000000000000800001000001000004000000\n\t000000000000000000FF1F260000000008008008008008088008010008008000000202228102002802006002003002002000\n\t802002006002002002000002002002002000202002000002002002000000000000000000FFD7190000010B00000000000000\n\t0001260010400000000111540040000008800508080002000040000000100008000048040000000000000001000000000200\n\t00200000280000000000000000FF3AE6000000800800800A00800800800800C00E00800018100230A082802642002802002000dae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (022060068000\n\t00000000000000FF74C30800018458498010D58018418054010059218800400136000006006006102416C423050C00004010\n\t4600008440848600000610630710E041106007416416816416000000000000000000FF20F20000B188188180100100980581\n\t1911101009800000020600000000620E0060C608200420000010610604022402000E00008E01002642610000E04602600620\n\t6046200000000000000000FF41F3000000000000000000000000000000000000000000000000600600000000000000000000\n\t0000006000000000000000000000000000000000000000000000000000000000000000000000FF9F9A000000000000001000003ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C08010E00F00\n\t008710000640030632602880000000620E082010C06424200000000000000000FF014300003184290180092CA01805814009\n\tA89093800040000600000600600208242614608612400080014602010601002600100600612420400100610E834002016024\n\t000000000000000000FFC7F4000081881021809001811825A11001303C100C40100E9E0360000442000030C2303014A00000\n\t2808000C402402400E0000CE08E1041881A018E126A1250A01620EA00000000000000000FFD9AA080401801C09811001A098\n\t01A01081211825000000082604600600680A86200E0022040000000060021042042042C6000806806A04024000066916006200bae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018018814\n\t01800000180F8160008064060C20068042460020040000020020063020060004062A002E00E024906516106016206A860000\n\t00000000000000FFE4BA000409A41001C03821C35865820001C6980784410100060060071441000A21871170360160008060\n\t0600680720600640814600670016812101E02661000003489E800000000000000000FF6478000101800005883A0084180185\n\t0001809411E00050040600600000780000A04E20600600608008800E04708600600600800580600180580000604600628004\n\t4047200000000000000000FF7873000681C51A05900801803801800001801A01800120800600000008448301280EC0FC0600007ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (602600000000\n\t0000000000FF86BD000001205001880011A01E218858418018018000000806006086004407B022268048060060000060C081\n\t208E34A00E0000042060420020408060060000068C6046000000000000000000FFA57D00400501B8018000010618078E3819\n\t869049804004000600600008410600218640400600600440001A00A00600308600002621060246200C6A680780298601E106\n\t080000000000000000FF1FC5000021140043801001C01801809D0180990B800000002E50600610700F80A006004106402000\n\t0060008020060021060000270470120060080A7516C8E206006006080000000000000000FF5CCC000011010801A01241001800fae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (206016006007\n\t00600600040C006002002000006436C9802E006006000000000000000000FFC89400404180002D9080030018298019438234\n\t0980400608D6406100885C064A2C0680608600E00400014E806917446006200084A302A24022048A69864020061061060800\n\t00000000000000FFB501000001A450058440D0921803891841801845808000025600600600450600A02610601794002000E0\n\t0620400648400600022611600249201001720E403106506127800000000000000000FFD6E30000038C004180001040184180\n\t9801C012A5800000100708600000491609202540688640000420000700400708C01600000604003600202500620E112206820006e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080180000180\n\t0000600700600600600000480600600600600000600000680100600600100700600700600000700600600600600600000000\n\t0000000000FF71E1000001801041033088901801808841A01001810000600E00680000620001400720600600600400000100\n\t60000068060000460160060860040B600680612E006046080000000000000000FFF006000005845003001020A238518C0E01\n\t823855800005714600680700F0800440260A610F03602040E000206000306006200896346546C16209006146106006506106\n\t000000000000000000FFF3C1000003801011980005803805821805E00801800000840780600610C0061000062260077060000086e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF1FF20880018A9001001800801C01800C31809A01820040502E1462408071001468CE80640604600C8A0083016801\n\t006006000906026006806004007006006006006006000000000000000000FFC8990400018010010010008018018008018018\n\t01800000600620600600640000400642600E0060004060100060000060060000060060060060002862060060060060060000\n\t00000000000000FF118800000180100100100080180180080180180180000060060060000060000040060060060060040000\n\t00006000006006000006006006006004006006006006006006000000000000000000FFB633000001801001001000A01801800046e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010069400001\n\t06000806006086806041837006006086006046410000000000000000FFB460400001801001440000801C01800801A01C0182\n\t000170068A60260060921041AE2462060060182A608100E00100000600008702610600610040740610651615610600000000\n\t0000000000FF1512000001801801801801801803825B059041059400006557406540156B40856C0600614600632402050200\n\t61400061060000060060460064450D6006406006006826208000000000000000FF83C42A0001801801A01001811801801809\n\t80080180010060060062060060108B400610610E62600000600000600000600600000680600600600008600680600600680600c6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001C00000000\n\t6006006000806000804006006806004000000000006000001806000006006006006000006006006006006006000000000000\n\t000000FF6D23010401951801800800811801820C41C1180180014060564000060A6618096007147106006000000013006000\n\t8020060000060060060060004064060062060AE086000000000000000000FF8F4B000001801001600E00801801800C01881D\n\t01880000654620004000E0808163060060460060100062820060010020078018078060260065002862062860160060060000\n\t00000000000000FFA700000001801C01840000801805804905805803820180E01680630080604204400782610700654082000026e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFC1150002038008818418418098418A18031448280000046036000000A0618404ED061160060840000060062060020060\n\t0600029600648600600000600608602602644E000000000000000000FF6213080005B00A41C95B00C01C01ACAA132B3A8200\n\t00D2615680088E336D20C364470B7206C2489088080A426C00A46036000C8EC96C0E8CE810D268A68C6B2683680E00000000\n\t0000000000FF3543000001832A938018018919138019010018300000016206D160068060081060160060D688400000E34208\n\tE05009210600000602614620600080EA1700E0164862A6000000000000000000FFA7A100020180000100100080180180080100a6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A0087918400\n\t0D00A20A00900808A90C00910900880A80000000000000000000FFEE40040005800800901800880800800801008810800010\n\t300200400310E01600202A00200200200800200E82E13620280A00000200202208A00046A012002002002012000000000000\n\t000000FFA97200000018014F00810135008800100001004000000252000061960200000A42404006201200C000E3E014040C\n\t5040000000085C0008030000000128028688758000000000000000000000FF0C190004000080000140040001001100080820\n\t84000020080809600E090408201010088080250000006000C00000080C600000000081002000400002C000000000002000000066e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (130000000804\n\t824A00934B2C820914914904900C80800A0C80488C920804000D00900890840800804800D109089109500000000000000000\n\t00FF278B000005901805925015951901901801805801000000600608C00E1164C401611628640E08E00000602410600C04E4\n\t060000065461061060004164060062064C6016000000000000000000FFBF23040300C00F40C08D40C00C50C48D00D48C5280\n\t0114211300310200300B04244303300304302110311244350330214200149300340301304104313311308301344200000000\n\t0000000000FF7BD808050022242028229000021224A3802202030000088184B08800800A6081080486481C8008009808108800e6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t03E40008004500004004002002004044004244C8000000080100124100104140101010100108100100110000100000000000\n\t1001009001101001001001501109001000000000000000000000FFF232000A882400AA08A0040AA0AA0A00C8000090000000\n\t02A82884A8110400080000220A202080020A80002002202002A80000280002202880022A82A8020110200200000000000000\n\t000000FFF160000004840A00A40A0C800800A0AA00A28A208000802000802802C02802C0AA2280200A842800C029228B2802\n\t812802000802A52802802A80802802802A42822802000000000000000000FF8BA700002130C0002012C020140120024328220016e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (240AA80002AA\n\t00214A0424002A82AA0922C22AA2AA000000000000000000FF2C2F000C000100000420282002000A80020000040001001000\n\t0200000000001282280010890D02020000208C00010000000002304000800203020000004A02000000000000000000000000\n\t00FF183F0000AA1022AA0A00920AA0AA0A80AA0080040000000AA82A80882A82881302C02302A82480804A82083082A9288A\n\tA80002A84A02102081002A82A80402002A82A8000000000000000000FF6B9300013430235431030015415420231034C32000\n\t00000550D10930C40950A00900CD0440400900D50C90410D48550D50000880928C30C88800D50D50810820D30D30000000000096e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060460040\n\t0600600600620620410600602002E00600608608600600000620610E00600010600E006006006006000000000000000000FF\n\t65C30000012D12002404022012012002002213120000804804844800800908A40A8081480480CC80A008088B480008C00000\n\t0800950C40C30800800800810848800800000000000000000000FF9A6C00020080480080A920800800842800892820800000\n\t000200224200204210A0521020020C2000002122002002822002000002202082102280002002422002002002000000000000\n\t000000FF909D0004AA0000AA0940484AA4AA0880AA10000000010002A82880882A82000000012202A82004000A82412402A80056e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFF5F0\n\t002000801038808800800020940804808000800000200600040200200A00234241201610600000200A012002106002001003\n\t20300300200002300350B483043002400100000000000000FF6323400D014804004004004024000004004014000001005001\n\t4540090010110010010850012014003810112050010010000000000002080010080804082800000000000000000000000000\n\t00FFB7DA400440C88C50C10C00D10C00810C00D40C00810100300B00210B0030430230030830435030004030035030030030\n\t02010002002202003011043003512142402002000000000000000000FF3F320140018018018418018058418018058118018000d6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000064964\n\t8654E0000360660064A644630E0A0000000000000000FF697200000180180991100100004180902000004180001060260A04\n\t0800C20200210654000608601200210610632600600600000600604600604210408610610608624E0A0000000000000000FF\n\t761A000800004080084002008000008048000040054008013014E1560900500082000A012002050800654008054002800808\n\t00002102205404A8510300000008500120000000000000000000FF7F27008140008000040001110000011003140000010000\n\t00284561060000400200002040C0100240056000080100100000008000000080000000800A008000202000000000000000000036e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600604000600\n\t600400400600000610EC0000400600610E80680600004E00E0AE0A6800006046206006306006000000000000000000FFFBED\n\t0000018058318138010010018010238A5005800022E0060062200040520C20040040060060802002940064242A6004000486\n\t22620640E1000065060C613602E336000000000000000000FFE30E0000018058018448210A10018A3000011009800000E406\n\t0060061460AA01203600C05604620010620604E0060B601610100708708700E30822740740704F0070062000800000000000\n\t00FF8EA30008018019018298250B01A180301406918F854000E31601014602628206240E000106006100084046626006006000b6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFE8B80000\n\tAB8238838018AB8AB8AB8ABAA8103888800020E2AE2AE28EAAE2048842ACAAF2AE2A62000AE20CAAE224A56AAC0008A7206A\n\t070064002AF1360269168A6836000000000000000000FF68CF0002018418010208A180180180180008180380008068060062\n\t0000610C00400600780600608020000C00600401600600004E02640E20600000600601600E206006000000000000000000FF\n\tEBAD0000AB8998118058AA8AA8AB8AA88CA018ED80001C62AEA880882AE28421CAACAA82AEA361004AA066AAE01600E2AC00\n\t00060860060062002AE00E01E646006506000000000000000000FF2AAC400001821905121800800801800800011C018000000076e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000600600690\n\t6000006006006426006006000000000000000000FF7B764006ABA890AB8880900AA8AB8100AA821C898001AAEAAE28E2882A\n\tE0062AF2AC2AAAAE2AF0042A81062AE2AE20E2AC00042E9268060070042AEC0680E04E006026000000000000000000FF3D8F\n\t000A01A81041349A01000801801001051A0180008070070060460070D644600600200700680000710400710410600600040E\n\t0CE156356900004206D06006216006000000000000000000FF252A000155913155113005154955943154A2D9518000557557\n\t556150556446556556D52557556404150426D56556CC6D560000862160C614E484554156346506136336000000000000000000f6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02640048E006\n\t00650C006006006004000094006404006514000116106046016004046486106056056046000000000000000000FFC1050000\n\t0182182192180202180180400A801801800000600600600602608610E00412C00600600020620400600400604400022624E2\n\t8E28600048400E00E00620620E000000000000000000FF607000000182380104300A0018018C2000911C2180000060060460\n\t408041460060040040060068840008440068048A6804000A8628E2D6236B0400432E326906ACEA8E000000000000000000FF\n\t82D7000001801001A00A200008018082008038058000006006806006006C0E80600480200680640000630C80600400600400000ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (308B00015591\n\t200D90C93191395595308095108D800055655655653040E4465521025465565540045500965562805565160003560D605641\n\t600444E42E286056056056000000000000000000FFFD8B800001801001800851813801841900841801800000600600600600\n\t610610000200600600400000400400600000600600040610600600600000601652E206006006000000000000000000FFAF66\n\t0000AB8C98018098AC0C98AB88802188B88900002AE2AE28E0AE04422E2260242062AE2AE0020AE0242AE0BC2AE044000006\n\t00600602600200E026276686086086000000000000000000FFC09900000180390D0050000038018401008418258000006006008ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (106046016004\n\t0074C6107056016046000000000000000000FF89AA0000AB8AB0AB89088D8C18AB88183110481180002AE2AE28E28E2AE226\n\t2322AA2562A82AC0000AC2AE2AE2A82AE2AE0000060064061660002AE1062262861E6486000000000000000000FFB71D0008\n\t018000A184080180180180004D002021800000600600600008609400222A00E0060040060004260060200060060000064063\n\t060A6006104086006106486306000000000000000000FF603A0000AB8AB0AB9428818818AB88A8440100A380002AE2AE2AE4\n\tAE2AE2362222AA2862AE2AC0002AC2AE2AE2A82AE2AE0000AE42E12E20E0002AC22600612E40E12E000000000000000000FF004ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (860008060120\n\t1A6FE09C81C0000150274061D90068262082460860CE006020A02846067016066006000000000000000000FFD05500000382\n\t2C83829C01C21E01C0B001021001802100700600E00100644600300210722010600448400608600700602620801600608E00\n\t6025104006006006006006000000000000000000FFB3BD000801800001A3380380980184180A10B045800000600602602600\n\t700E00A00209600000600200400600600400680600022624E28E28600280400E00E00620620E000000000000000000FFB49F\n\t000001801C01800841A23801A15100040309800000700600600000608608200204600100400440500700600280600600011600cee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800411800801\n\t8A880104BC218509000280C1808100610E40820600208708300A10E80610621000C5268562B74069163400062060A6006000\n\t10212E006106406006440000000000000000FFDE1A800001801A01828C0B201801C2980A00280180000070065482209004A6\n\t00A00200600240400041400640684200600600005601600600600880204600608E006006000000000000000000FF00008444\n\t21800021900813001845840800084001900000600654604008208702200380610420600000404700740400700608040610E0\n\t0600601021210E006086006006000000000000000000FFEBFB8028039A3483A80801201C01A038140A020188200071660065002ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060000440\n\t56006006006206200000000000000000FFBD21000011901805800931845821801824104003084004640E0881264260CE2020\n\t4240E21200600000400E0060064160060000060060064165200060064C628620E026048000000000000000FF23300000018A\n\t180391188181180180182280300301200263064864A602242624A0A600600C04604000400E00650600614640000640614620\n\tE08051210608621606E206000000000000000000FFF1A20400418010418028298418478018008810090A0008E10602600020\n\t020E06220220666412402010400610640000E02610000600604600622033A11622600E006026008000000000000000FFF37A00aee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20224062AA2A\n\tE2020021002AA1A22AE0422AA2AE000002002402762100182102202282182482000000000000000000FF9E5A000000020000\n\t00100200000002C411901000000000000002620602C1000080040000040000000044000004A0000000000110140040010080\n\t008480100010050040000000000000000000FF876180000000A00000002000000010000200A0220000000000006026200208\n\t4C00000001282C8500006010000008000000000240208288080400440028028020200208000000000000000000FF57870000\n\t01821801823801801803849300050949040008E00602000000600610E28A10602610640800C54603602E00600E0A00060060006ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (558099559259\n\t55D559558A3C819259558001557D5655411748655600C136556C0CD56400156556556516D575560003560D60560164005164\n\t4E2C6056016056000000000000000000FFFF510002AA82A8AA8AA88C8AAAAA8808CC8088A880002AA2AA2AA08A2422CA0822\n\tAA2AA32A22A2002AA04AAAA4122AA2AA0000AA42A12A00A20022A22202212A42A12A000000000000000000FFF58E01000014\n\t200001040000000020844C01000000008000000002000480000C02010001240000800000000000400040000000004003002A\n\t00800200800001004A0300000000000000000000FF91B40000AB8808AA8AA8890AA8AA8508A086488900002AE2AE28C08A0900eee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04000A802802\n\t8020200208000000000000000000FFF2A4108000100000000000000000080100444000000080000000000002800023103100\n\t0000000000000000000500800800000110140040010082000480100010010040000000000000000000FFAD218004AA800EAA\n\tC208AA8AAEAA820820C808AA80002A82A828A0EA2822AA4030032AB0222AA0006AA2ABAAA0032AA2AA000002002002222000\n\t2020022126820A2082000000000000000000FF700C800A011000010004410012014024001000050001005004004440100000\n\t034000805005100000000400804100804004000400100000000000000010508200000000000000000000000000FF77AC9001001ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000088002122\n\t022000C8208280240340A10240020A002002A08000002002002002002002000000000000000000FFC9520000000000000000\n\t0800028220008000800000000000000000000018000008204100004000808000008098888002280000000000000000002000\n\t00220000000000000000000000000000FFA58C0002000000000000000684400B000800202200000A08410000000000004002\n\t009A0000000002000800080000080000000000000000000000000040019880000080000000000000000000FFE08A00040003\n\t200028A00040000001240A008000000000080002020100000008050000130800050000000000002800000000024020828808009ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0860800D8084\n\t08489F6800880D80800008221A222002002002003002102003002000002002002002002002000902A2B80200000110280381\n\t2002802002000000000000000000FF9356000401881881801809C09801081881809801800012602600400600680600632EA2\n\tE14620608250780480EC8E51610E400416806006200000006006024106006006000000000000000000FF0C7D000001001001\n\t0000010C3185040438004544000002148409D2006200040048051000040E4000000104100004004444000880800801010000\n\t484800C15000800100000000000000000000FF73FB000000900900800800C00A00A00C00800A80800000224000A802202002005ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF24150000000000000002002000000000010012000001000001006006000000000800800000\n\t000000000004000000000000000001004000000001001001000801000000000000000000000000FF520E0000008008008008\n\t00800001A0080080080080000820262240020220060020060020060068000020070030060060020000020028020000000020\n\t42002002002002000000000000000000FF397600000000000000000028251020065010000000008205001102004010002040\n\t00000001120800001000000000000000000000450000000000000800000000800000000000000000000000FFC64E0000008000dee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (262D63564062\n\t0200600010414600E006000206102006010002006006AB6844024204000000000000000000FFAEE2000001805C11A4585180\n\t0100411040800B01800008630600004622600601680F00620684630000600000520E046106000207426456100491406D4650\n\t6406046006000000000000000000FF890B00000D88180180188184C000001111801843000000600600020008402600624630\n\t6006116000006000004006016006000006006006440000116006026006006306000000000000000000FF7F70000000000000\n\t0000000000000000000000000000000000006006000000000000000000000000000000000000000000000000000000000000003ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (803101822841\n\t831100800C01800014ECC701004000500600704680F00600600000680020E03700610608009700002601000000680C840084\n\t000006000000000000000000FFC18B400041CC5C498089118528018290C880090480000864860804A654220710F01602E096\n\t24610000600100722E02608600000640202630000940E20680F424004106000000000000000000FF2D3B004001C01801A030\n\t61811408A0164488883180008050361065000060067066960020368CE5020110010840861064060000048A270C5286C05C64\n\tA4414410000114000000000000000000FFC29420004B8418418318018010908410019118018000806046106106006426D06100bee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060164020060\n\t06000000000000000000FF5E50002009901801E04941C40821C09201801809000004601610608180608E0060060060478060\n\t0400600681600620600600002E006206090004006106006306046806000000000000000000FF8D1300002188181180100180\n\t1809803144866C818000E0404702644600608E06618603202608E9000001870060162061060006243A89444204D80460E400\n\t4000020E06000000000000000000FF1B31000621801801800801C15809C45200E00900800110C30603600000600648644E04\n\t200E12F200008006206026106206080104A2900404190030620EC52008004116000000000000000000FF4704000011801811007ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (24AE00600C00\n\t0041086036106106000084006884009404006004044A02882006000000000000000000FFA0F9000001821821A01043800805\n\t841100928A8980000048060060061060068062060822060160020018268860479061060000040AE804008282006024044082\n\t802106000000000000000000FFAEE80000018318218250338609318390008208EB00000460069E600000C0BE876856006956\n\t02E01400601E2068060260260001060AE106040004026684808006102486000000000000000000FF6AF60000019059098C88\n\t01800C41803001801C05802000400600600601694600680605080604600401000640600E846026000004006004000004146100fee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (7BA19A018618\n\t00800801880000C01684E00628400614F00E10A00700600000010600600600600600001C00621C0200005071240C400205A0\n\t06000000000000000000FF8857000001825811A10011A01A1780580091080100402E400E82620180608601602719302600E0\n\t040100060070060260060000040260050401053860C5020902022486000000000000000000FF69A7100005801C1588110184\n\t3801C05808802B448221004146006006026216127006022006006514230100086006006006000284086144D1100C84620C00\n\t5402102016080000000000000000FF79FB000001911B01D02001A01C81A01900800800000080500600600108600600642F020001e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600600\n\t0000000000000000FF5CEE000000001801001C01801800001800800001800000600600600600600600400700600400280400\n\t0800806000006006000006006006006005006006006806006006000000000000000000FFCEFF000000001210001801821A00\n\t203801804081A04002684600600108630600402600604400200420000600600602600600040690610622600C006C07006006\n\t106016000000000000000000FF1CDA10400C021A03501B05C03804201E09800025B40049688701640622600E01500E82E005\n\t00AC8C028806886006006006000106826446116004846036886406006106080000000000000000FF3F3A00200980180180100081e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004080002\n\t20600200680600000640600600600401E007004006806006000000000000000000FF16B5010000001803001A01901C212010\n\t0508100580C100F03640E4800364460372A70B600602400094001680610604E00608141680720750E0010068060050060070\n\t06000000000000000000FFBBD110400000180100180180180300108100100180004062061260060060860040060060C42100\n\t04000406406006006006000006006006006004206006004006006006000000000000000000FF45F100000000100000180180\n\t18000018008000008000006006006000006006004006006004002000000000006000006006000006006006006000006006000041e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1A2080180440\n\t080994208260272062080B648EA0500400710C02209000100680612609605600000600600622640100600600280600600600\n\t0000000000000000FF456B000000001801001C01801A4080188110081188A024700E20660600E2A602D0A420E2AC04A04002\n\t020E00608606E00608020E20600644E401406006412007006106000000000000000000FF1DDE000000001000801881801910\n\t28168D00000195400061574061101565564062D6826116416314100002046152116C560008060069168070AC046806826006\n\t046806000000000000000000FF3FA808800000100080198188780018100100018390000660060060060060068042064A641400c1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (106406000000\n\t000000000000FF49980000000018010018000018010008018010010000806006006000006006004002806004802000000000\n\t006000006006000006006006006000006007002006006006000000000000000000FFEEB5004000001004801881801C45881C\n\t04181A01800081644715010684680600720482700644E00000100480600400600600080600640650600040600600A0060260\n\t86800000000000000000FF8CFB000000001E01001801E01889801C91201C010080006096000101007026006154006006A062\n\t2008000502600C0264060010078060960060A8246007222006006007000000000000000000FF06F9000000001000801801800021e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (22028001C002\n\t300810000000401A00481000021C0000200180600000000000000000000000FFDCBC080000081801885860301803000A1188\n\tB0418000786416000000A0680640620203E01E00600000200004600000600600008620618600600021628604620608620E00\n\t0000000000000000FF7E390800902A1B098C9A50013A89200943A4D32D000120605680088624E0268B6D02B4E8AEC16820A2\n\t0840106AA10A68060008AEA56C96906800B068C6886D26A4E82E000000000000000000FFA58F000000009825801900121805\n\t10081188100180000C650751601610628E20602200640610608110848820E01021650600000708602640702884E20625201600a1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200200300208\n\t0000811028B08810C002242C8090845000040880C00814800844204900000828840820400860800800980800800800000000\n\t000000000000FF1B17000000020840C08880C00988880903040984800000700600400200600A0221020824020020100161C2\n\t08E08200200200000200200200200800206200A022032022000000000000000000FFFBB700008C1042800000100000051040\n\tE8025010000002028000658E0C910110540000026138004028462C20050D5286800005004082002901100285000340081480\n\t00000000000000000000FFFC0A0000000000062001000A4000050400010022000004090009600603108001002170008040810061e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020000000000\n\t00000000FFAE900000000002002014000452242202012002100000A54004804A00A8C004000800D14000800A008B49248050\n\t04005004000C00A80808000C00800C109008288108C0000000000000000000FF8F7100000410580580180990580384182193\n\t3851800011600608C00600E90614630600600600610040400C0060C48062060002C620610611604811608602610601600600\n\t0000000000000000FFD372040200600C40844CC0A00C80D0C910C00D048001422C9300330B242003C0B01252BA3332304901\n\t35422434133020820010030C30234030810234231130032C3002000000000000000000FF272204040040802826020840A20000e1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8550450D5155\n\t0D50000C808908A0800C00D50880D00CC8D30C00000000000000000000FF247100080000040010C000004440000450420440\n\t00010018010010010200010010010110000010010000018010000000000010011010010010010010010010C1121000000000\n\t000000000000FF22CC0008AA0AA0AA0000AA08829008A0AA0AA10000000002A82884A88002A82A8AA80002A82A8000200200\n\t2202A82A82A80000284400200000002A8030010200220258000000000000000000FF7AEF000200400A00B54800C00808A00A\n\t00A00AA28000880000822802042800802002842803002800802812092802803002000902852D02802800802902C2A90290280011e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (820260300000\n\t2A82A82884880012A82A82A81402A92A80002512002A82A92A92A80002AA2022AA0020002AA2AA4600A20222AA0000000000\n\t00000000FF498400080000040041400000002004400000002000000A10000200000400000000008000000000002C08010800\n\t00000000000028000408000000000220020000000080000000000000000000FFD1220002AA0AA0AA0402AA4A808A2AA00410\n\t810200002A82A82A80A82882A82A82A84002A82A82004802A82A82A82A82A80002A82482A80002002A82A81084102082A800\n\t0000000000000000FF68B50003543541540C01543343023103543542140000C10550D10930C90D50D51550348D50D50C00800091e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFBB790000218018258018140AB811805809801821100004643600400604600610608610600400600002400608610600\n\t600608002608640600E00000E006006106406006000000000000000000FF938D000200001201253000021201000200290303\n\t0000800804844C2000480080080484C804804A0088492C804800804804000800800800800C00800800D10800808800000000\n\t000000000000FF307F0000008008009008000128448008508008088000002000002002B3000200200228200200200002A002\n\t002002002002000002152002002000002002002412502002000000000000000000FF7FAD0000AA0AA0AA4002AA2800882AA10051e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (500004000800\n\t2000C8200020110200800008900210000000000000000000000000FF5BEA0000208008A28008000EA8200008108008008040\n\t06A00A14008200600200A10200E0020020400C241211601A23E0020810031832030020014832022031832030020000000000\n\t00000000FFC98D400C0040040040040040040152040040440100010110055440090010214110050D16050051491050050010\n\t91000000000200000080001000108410500400000000000000000000000000FF94E3400400C00D00C10C00400C40C20C04C0\n\t8C00800100300300230B00302304324320301300B01300300340300322B0024003124020A210340300200300200A0020020000d1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (98028E400162\n\t460083B600620638E2460160C820600801006600608600602600000641620610E08004E0CE29662627619630000000000000\n\t0000FF51A00000010018039058140018818420010010A1900028600E01004000600620E30E00610008E01010201621600600\n\t6006000006106426426130086016102086006206000000000000000000FFED140008001000040400400000900220440200C8\n\t00002880B0206016400020000050110040110080110000420220000000000000210040340248140020050000010410080200\n\t000000000000FF085D00000000000000800A00000808201501204008000042205462060200002A44A042000C0080A00440000031e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF98A140000192184180180000180482004180280480000020060400060060060D28160064C0086800450006006022006006\n\t00000600E046346800306046206006006126000000000000000000FF206700000101188B8018240018218038010219208000\n\t00000600602000600420010600601420E04000012600608C00600600034E44650600E0000465060B61364262160000000000\n\t00000000FFBF7700000102180982184002180188182D029812800002228632620620622600200608600C2061400202060C65\n\t4C01602600100700700700E201217106427047407006400400000000000000FF12BE00081912198988380A0018718800010000b1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08D565560000\n\t964161560260043561164D204648E126000000000000000000FF771C0000018C18A98AB88A0ABCCD88DC8C88D83000002A92\n\tAF2AE08E2AF2AC3292AF2AF00700E8202212A72AF280AAE2AE0012074070B70270008974360A680742610600000000000000\n\t0000FFA472000001801843801800001C0280180CA48A02800000300700620080700500108700700712600080108F00712200\n\t60060002460A6406316000006046006286006206000000000000000000FF1FC30000018038058AB8880ABA8988808B8C9908\n\t80002A8AAEA882882AEAAE802226AAE940826000190A0EAAEA42AAE2AE00004609640E40606000E10E00675609E4560000000071e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800080680680\n\t6046006804006006806802C4680000090680682080600600000600600688680080600604A84E08640E000000000000000000\n\tFF5BF14000018AB8118AB8880AB8A108800308100080002AE2AE28E088AAE2AE2AE22E2AE2AA007001AA820E2AE2082AE2AE\n\t000026826006027010006406202096846036000000000000000000FF70BA00080180D8018018400018010400400018048001\n\t0060060062470060040060060064122A600080001600601000600600011612600611600022600640A0061068060000000000\n\t00000000FFDC720000019559019559521559311541205032A8800055655655613155655655644E556552216014550446556400f1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFC3\n\tF200000380180180180000180502384404500280002160060260000060240160060060460062245100060064120060060002\n\tD60060061060244561061040060C60A6000000000000000000FF5D770000018018018018000018000098000008C080000260\n\t0600640600620C5060060060840061000000060060C000600600000624E50622628008645604E4C620E21600000000000000\n\t0000FF59B40000018018818018020018020018000280A4800000600604620000600400688600600411601000002600610200\n\t6006000A8E48EACE2160102AEB2E086206457086000000000000000000FFD90900000180182B801840001A110443490038080009e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E2AE00002E02\n\tE01602608024612631003602600E000000000000000000FF825A00011395415515580195595291195084D88A000000E55655\n\t61305564064B25565524C25561061265565561065565560002D60D628634630640E2464422462460B6000000000000000000\n\tFFA3C58000018000018018018018048498008418000000016000006406006006100006002000006000004006006006006006\n\t000506106506406410016406002486406146000000000000000000FFAD840000A98AB8AB8AB8000AB8A90818880898088000\n\t0862AE28E0AE2AE0840262AE2AE20E2AE0000202AE2AE0002AE2AE00000608602E00E04000600621410E00600600000000000089e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (016804006440\n\t0068060110060061400062000068060028120068060000D6006006006008C561060020060C6086000000000000000000FF31\n\tF20000AB8AA0AB8AB8018AA9F08A488280504100003862AE28E08E2AE2AE2402AE2AA2402AE0102AE2AE2AA2222AE2AE0000\n\t0648606E11E00018601606200E116406000000000000000000FF313400082180000100180180180082380490184000004C60\n\t060064000060CE00200600201200642040E00600443400600600000620603600E0000C610E08201608E20600000000000000\n\t0000FFF53E0000AB8AA0AB8AB8018AB8008818AC88990A00002462AE2AE0AE2AE2AE2082AE2AA2882AE4802AE2AE2AC2B42A0049e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF445B80\n\t0C09C00401805C01809840801C20A118008000025006006186007006C8100602280080600020F4160077068870061B000682\n\t6406006040A16086042506006006000000000000000000FF7F37000209A00001401A01C10C95800843C01000000108700600\n\t605000710E8A000E32E21040600500702720B04310700602000602600608E004426117006026006006000000000000000000\n\tFF2C08000801800001001801800811808C41D010480000026002026006006006140006000808806108006006002102806006\n\t000406A4E5062A628000645648C4C620E256000000000000000000FFFCE5000001800201801801800804802810853105000000c9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000016286006\n\t016040006086000206206006028000000000000000FF701B8000018000010258018808308048208218318000281086000006\n\t08E006A0201610600203628000ED07108090C068060000060262AE0160B014642610609614E006200200000000000000FF9B\n\t8D808001808041A03801A02B0A800900A8380180008040045500291068064020C648611242604100600E5008A00060060080\n\t0620628648600004E0170C22C6006006000000000000000000FFF2D681000180802102180180580080190090580080000240\n\t424D6001106007002347802082026020436006086006006006000016406086206000006006106006006006000000000000000029e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0041000040E0\n\t0640604C20600604E2D000628609000820604600000630600600600000620624E406486206000000000000000000FF565300\n\t002180000180180308002480410A8058B5100020608612000E0C63160063040864B600600000604E20014010601600000604\n\t64D649654044E026004016046016450000000000000000FF157200002180001980586300101380108B801883080010E0060A\n\t600E00608E0142842162AC00602807600E20402400600600000600600628621030E10632E10601620E000400000000000000\n\tFFA1A80000018000018C180102104082100481380100A010624620E00022631604C43401A40400600004646601400408602E00a9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFA4AB0000AA\n\t8001008AA8C808A0AA8880AA8880AE800022259228808A2AA2AE0222300020022AA0420422AE2022062AA2AA00000248206A\n\t11A002102012450002112402000000000000000000FFE28A0000000001200000040000010040010000010000000400026006\n\t00000040401000044400008000800000410C0000000002D00000004004004502400000000800A0000000000000000000FF38\n\t3680000000001400004004000002000002200000000900280062260000000900802A81100002404A00001480400000000000\n\t002485000C01200801105484C8228210000000000000000000FF2AFD0000018000018C180102000182002184180100A000E20069e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001005000000\n\t00010500004480400140000000000000000000FF263A900555800155D5595590990B909D05955D1580001568565545575575\n\t574D65564C7456556000D5755644C4155575560002D60D628654650040E2C648E2462460B6000000000000000000FFC86500\n\t00AA8004428AA88A8888AA88AAAA8AA8C880003220222AA28A2AA2AA48A2A20D348A2AA4004832AB2A22432AA2AA00002A02\n\tA0122222A024202210203202200A000000000000000000FFBEF6008000400000200000424020022030001040000140030000\n\t40008040010010048081010044080000001050A00050000000002000300080080C000802001008820000000000000000000000e9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004000100089\n\t00004008100002000010001200810010000004002485000401000005101004C0220210000000000000000000FF449D108000\n\t00000020000002001400212000021000000300D00004008000000000000480010000880000008108500000000000D0000000\n\t5004084500404480000800A0000000000000000000FFFB1A8000AA8000AA8AA8AA88AE208888008AA880800000200228A08A\n\t2A82A82222AA0822A32AA1002AA2AB2032022AA2AA00000208202A00A00008200200210A00A002000000000000000000FF2D\n\t4C800801400208401001245000041200001000000100900000404100400482100540084100408100900500D10C80500400050019e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B2100100840A\n\t10812800804800800810844A88884004100210215240204A002002803203082000202082A422820A214A10000204A00204A2\n\tB0002002412002002452000000000000000000FFAA4600002209000008000040000000800000000000000000000000000000\n\t008000008000000000800A0408008030210000400000000000000000000000800000000000000000000000000000FF058D00\n\t0400000000004002188000004420200000000000000114000000000000000028000000000080000000000000020002000080\n\t0000000000000000801000000080000000000000000000FF525400040000000000000000008002040C0000220000500200020099e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0800000000000000000000000000000000FF9AD5000000820C06804800800800840802A00800800100301200A00206200200\n\t3802013002002200002002003003002022000002002002002000002002002402002002000000000000000000FFBDB9400023\n\t85100989580188D801811C09845D119040027006084156406056006006A0740790600028650EC4E506156156500006856007\n\t056550806006416006006456000000000000000000FFABE63001031014000000054010830202E80AB028000000420C204008\n\t000000804820108004004101040001284054604400040001000000800000000000000200000100000000000000000000FF2C0059e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF24180000000010\n\t0000000000000000020000000100000010000060060000050008048008000000000000040010010000040000048000040000\n\t01001000004000000000000000000000000000FF5136000201A21A00A00800800000200800801000A0000064060A80020020\n\t02006002002002006000002003002006002002000002002002002000002002002802002002000000000000000000FFC91A00\n\t00042000002000001000822020B40AC02820010000012040100000008000200000050002000000005040004000200000000000d9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000380000388\n\t1009819101001801801869000080602E0060060C6086006C0600110640600020600680702690602200082280688000402020\n\t6004802086004A06000000000000000000FF707B00000D800005941841A40210001809911C05000000602600008640644750\n\t6106040206006001006C4640632644602E100446006120004240D06414007487406004028000000000000000FFFDCE020001\n\t800801801809800000001881003889000005649620040011408602E046408006006050206006006006006206000006006200\n\t40400000608444600E00620C000000000000000000FF7F7000000000000000000000000000000000000000000000000060060039e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (30D900107004\n\t01104C014006000000000000000000FF086B000401840401801801800A0080180B923A21900120600E4400000860AC00600D\n\t146C0608600190500402688600600A00000A4A5206414080004484008056804006000000000000000000FFE2720200018000\n\t00820821E40888801090909885800002E0062000060164270071262361062060000064470060060A60121004020062202062\n\t0010610D422416004006050000000000000000FF6A5000000990040110100180104100180181381100008062860062802264\n\t046AE344410206006028044404306286F06240000000014014144000D0420440280421480E000000000000000000FFA2BE0000b9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C60560064964\n\t0604601000704600600600600E00100700F020204000006004046004026026000000000000000000FF8356000001800000A0\n\t0001800800815803001000000040680780600022E80600780634E40600600000600608680620600600000610634000400021\n\t6006046006006006000000000000000000FF7C9700000194022330902180180780B831955810800018718600620632F55442\n\t6304806006106003645464E072060060100000900140B404400200CD1E421004004006000000000000000000FFB8AE000001\n\t800022008841801841801020801840E800006016427A000040060464560078060060001060070262861060200000802468000079e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (808002000C01\n\tD21C018012020C182800000260070060004462240060448464861460A904400400E006006006000006004020006028004006\n\t007404806006000000000000000000FF67550006218000A5001001800A008018018030010280886006006086027804206824\n\t0278461060A082400400F846406106000806404804006128004004006404006106000000000000000000FF5BF60180218000\n\tA180101FC1081084B829001041000088602602609000609C12E00420E12600600401C02414600630608E0018060048068040\n\t840140048260061860A6000000000000000000FF7CD5000209810400008001AA082080D84B9410100000846026046006204200f9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (105464060060\n\t06042106000000000000000000FF1ADA000001C020111012A5981805841801801920000003602711600600400400608C8860\n\t0600600000400500E00608E10610002620C2E41260000A4206426004606086000000000000000000FF95AA40A00180008809\n\t2803C11A51841801005C82050008E08608E01000680450E00490620E08600400C004146846926006000006C1400E48420401\n\t4004206804066026000000000000000000FF7E0B200001800043009001841945831510805A10020040600702650790614400\n\t680422E1260060004040A448620E206086080216004007414010204005007405006006000000000000000000FFC7940000090005e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200400600600\n\t0004004004006006006006000006006006004004006006006004002006000000000000000000FF36B8000001800001001801\n\tA018018018000000008000000007006006006006002006806006800800004004806006007006000807006006004000006006\n\t006804002006000000000000000000FF86C6000001A00000005A01801C21801808202008820000200604608000600600000E\n\t0C689608600400E10420700612600600000600E086204404006006026406002026000000000000000000FF7D3F0140018020\n\tC5011B4184190181188020002280004C012600640610712601008620EA2680680040602409621721680600025640621603400085e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00001C118669\n\t43BF428001400180008A000700600600600600080E0067060868000030060060060060060008060060060060000060068070\n\t04802006000000000000000000FF6CA8010041800201801801A0880580012320101580C00C854E32E0A804E44E4004AF0C60\n\t461160040025448360A600704E000486806006804004806006006016006006000000000000000000FFF63F00000180200100\n\t1881900811800001001021900040000600600640600600000641600E2060A800201400600600640600000600600600400000\n\t6006006046002006000000000000000000FF98FA0000018000000018018018018018000000008000002006006000006006000045e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (680600608600\n\t4006000000000000000000FF5E9E000001800200005201B01891809AB2800808912080230F5360A902633620222A00834701\n\t655000680600E126A068B600000600E107806000A0F006036006800016000000000000000000FF6BB4000001800101101001\n\t801B21801944800A3888A02082AE2AE0A622E22E201AE23A04AE20E0A80062AC00E0A640622E001286006006004550416106\n\t406006100106000000000000000000FF6C18000001800020805801900811A1201030A0019140040356D5655004655644050E\n\tA56156016D4C00200681654700655600000681651600600400600602E90400600E000000000000000000FFAC17008001802000c5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (406004890000\n\t00440E12E00600602E00000628628620E00002628724640440C026000000000000000000FF0FD6000001800001001A018010\n\t01801C0100100180000040060060000060060040060060040000000040058060060060060000060060060040000060060060\n\t04000006000000000000000000FF1BB10000418000A0881511910911816045817A050000002006000017006006002006A900\n\t06000000000006044806006006000006006006806000006086206056084086000000000000000000FF705800060180000180\n\t1001E00801800401F11801E00004204600020000600604288302181600000000000400540600640780000600640E0042D0000025e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060A22240000\n\t010E0000000000408820296007008A0806846002008812009020000028000110000000010000020040000060000010808000\n\t0418000000000000000000FF4DAA02032180880188185180C1718800810D1029800000621602000011608600609609602604\n\t000008808604640628600640000638658638E40014E01E006014006186000000000000000000FFEEA40200B1B12309D29821\n\t84A341A4C28D3232918000C260AE82080EAAE126944826946AB6C40890B288A6C06AB6C86A86040AA680684E886890D16856\n\t88E904806B16000000000000000000FF5E6100000580002380380B901209901841009023800010C206D1610600620E00E30600a5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (11304310350A\n\t000000000000000000FF74100004492C021A2050005C000022024020A2D60000801080908840884804000A00801000A84840\n\t800C00908889000A00000A80800808810800880AE0800A44800800000000000000000000FFE82E00048080196494A000C000\n\t0885E810900800800000300600400A00302210200220220200200801622A00300600241A0000220020020020080020022020\n\t00002022000000000000000000FFCD5200000210108002042000028010002102510000002A40080061962200108841001404\n\t0040C1001641000202200001E00304000000600400900201000B0400308200000000000000000000FFEB64000004002000000065e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02802800A22A\n\t028030020028D2800832942A02B12810832882C02882912812000000000000000000FF4D0700000120123228D00102104123\n\t02C02042220001000004804820824C0C0009409000010048088148B0001004804A00000A00C08948840800A80C20800A0C84\n\t08C0000000000000000000FFB0C6000243901101943801905801801815905881800000600608C04600600E00651608EA0608\n\t40C00A400682600610603640020600600604600810600600620E006006000000000000000000FFC83D000100C20C34C00A28\n\tA20B28D34D40C30C4C800120281300311208A00394302302300342301100B2831024020033020110830832C350B40122312B00e5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (152110314208\n\t3143300000550550D50930021080D50890D48550550800881050D50D50550810800840AC8808890810940A00800A20D08C50\n\t000000000000000000FF081F0008004004104122000124044004204004000001000801001041000001001001100001001001\n\t001001001000001000001001001011001001001001141001001000000000000000000000FF3E3B0008AA0800000200AA0880\n\t8C00000008808800002A82A82882886000002A8000220AA82A80000900002A82A82A80400000800000000000000001480E81\n\t20240300000000000000000000FFF40A000200A54C80A00800A02A02B04A0CA40A00800080200284280288A8C2802C1280A00015e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020020020000\n\t00000000000000FF052B0000AA0AA0460484AA2C00900AA0180AA0CC00002A9AA82884882A82A82A82A82202A82A80182A82\n\tA82A82A82A82020003822AA5422A80082AA2AA28A2A82A82AA000000000000000000FF8561000C000B41400A420040042002\n\t012204000400008010000002010882280002200010008000084205000000000003000002900002A024000041000829000800\n\t0000000000000000000000FFF66F0004AA0AA0800800AA4800A00AA0820AA09000002A82A82A80882A92A82A82A82292A82A\n\t80002A82A82A82A82A83280002302A80002A80102A82A82102A82A82A8000000000000000000FFAF7A0001542002142101540095e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (311105300300\n\t3483550002002002002082413000012412103082002002000000000000000000FF7A4712004100380D801801901801803801\n\t8A1801810000601640400600E51643620641628600604040400620E006000006406036006206006200006006406046006006\n\t000000000000000000FF6A540000012002114402010294092002002002000000804004844800804804800800800804804800\n\t804804801004000800000800800948800800800800840800800800000000000000000000FFCD450002008009209028008028\n\t42800924800842800000200000224200200200200210A0020020000020020020020000D200205200220200200000200200200055e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200000090800\n\t00000000000004600600809024C5000A840000028800C000410400D400000040400004002140000002080808800060000000\n\t00000000000000FF306B02000180280B0008000C4980822820830840848001210A0480024066020021022020860021203220\n\t0209208210880220300B043402002201203103202422003002000000000000000000FF90ED400C0040040040040041050008\n\t04C2402000002100500524400900102500102800102908540100500510100400000000000000008000100040800000000000\n\t0000000000000000000000FF6D6E400400C00C80C00C00C40C20940D14C04800802100300301200B0030230030D20C30330800d5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (700600000000\n\t0000000000FFE0F20008039E38098A78420098038C20A08E0045884030610620020604640E1180020764160062006105EE11\n\t600602000E00600600E00608623000E20609E00E0162A6100000000000000000FF6A8500000980191194180C029801900009\n\t88800903000060060A800040608E00012A08608600620000001624610600000608600601620610E080486406106216006326\n\t000000000000000000FF476F00080800008001003000000002800A00010C00A0080000096006028100080048090490208000\n\t00840032010820000010000020000801010834005002000008E000080000000000000000FFD5FA08002000110000000002800035e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (244846A06AAE\n\t2A808600241649600600A000006486146B12216006000000000000000000FF86DC2000002258090210008018018020008058\n\t10800002E00600000680600600012408E03600E801004416006006000006002006036026042C0004640608E0460160060000\n\t00000000000000FF3AF30000010090A480580102580180182080002180000860060462000060064D00120060861462801501\n\t260D400600023600054E40628E48008031602E4461100C62B6000000000000000000FF8D0E00000300380181180100388580\n\tD8C3800081880040E00620620600E0060000020060064161000800060060164C10160030072270160022210370B70460041000b5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (213190013100\n\t00C46D56D56550556D564C28C6556D574CE28440AD56556D5655042E0060060060465562040161161075540064C600000000\n\t0000000000FF99210000AA3032C028B8AB8AD8AB8818A8C8B8098000806AAEA8E08F2AEAAF000004226A0E22628028E80F22\n\t4AAE2A880E00084604680E1302010AE006C162222A6AA6000000000000000000FFECE5400200001020001001801801809802\n\t82B80480000060060060010060060004040060068060000A60070040060000860004CE2AE28E00010022644622600608E006\n\t000000000000000000FFBEF90000AA0818052C98AA8898AB8E808A8E81C78000B06AAEAC84A82AEAAE540F04226A062060000075e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF4CE2000001801220A01800833801802000A00041800080E80680600600680600020610E80600E200006806800806\n\t0008860068860868CE0060008860061060000060C6000000000000000000FF7E6F0002AB8AB8078AB8AA8858AB8800A088A0\n\t8300003362AE28E0882AE2AE2B009E2262AEA0700522E2AE2AA2AE2A802E0060268260062AF0041060268362A84668160000\n\t00000000000000FF5FE2000C0183101080100080180180C205800001800044E00600604600600600A03609614710E8008025\n\t0611000600052600608690634640690040694E006004006016000000000000000000FF1A0F000555B55909B551549319559400f5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AE0B42AE0000\n\t0640650608E50E00600021650601620A2AE146000000000000000000FF892900004182102280102180180180B80080188500\n\t0000600602640000600600000E4060060060040160064040060000160162D600604645608404E20600604200409600000000\n\t0000000000FF78DE00000B81300094D80180180184180092B820800000600600600600600614808613400600610202000600\n\tC0060004C64A600624650608640208612E2AE082006246000000000000000000FFA099000001A01090801001801801849C0A\n\t8218100000106006046240806006810046006006146905100006004006000206006216216206006C8422F30E21600228C416000de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (88A88C80002A\n\tC2AE2AE0AE2AE2AE2A83201142AE2AE2802282AC2C42AE00020E22002E5360262843000260262263042AE00E000000000000\n\t000000FF8D8500015583411200B11195595594295591482200005545565565305565564825485445565560064C0556406556\n\t0004160C005604604650C00604604E4C6546556016000000000000000000FF8AB780000580000100102180180182C8018208\n\t20000000400600600600400600001020400600600000000600600600000610028600628605400000E29610E0560060A60000\n\t00000000000000FF42D000008198108880188B8AB8AB8818AA84181980002AE2AE28E0AE2AE2AE2402260022AE2AE2002862008de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFBFDF000201A0010900101180080180294100081000008048060060000060060030900848070064040930020030068000\n\t160508D600600601408404E0060065060060B6000000000000000000FFC5650000E98AA1570AB0958AA8AB88881100082200\n\t002AC2AE28E68E2AE2AE2A82202442AE2AE0003002AA01A2AE00014621000608E01E2040007060060060062AE40600000000\n\t0000000000FF6FA00008018000200A1823801801808801800880800000400600600000400600A00000C00600628400800414\n\t40060000A600800651600E04428428600600600C006206000000000000000000FFA09E0000898AA0010AB8818AB8AB8808C3004de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (780600010600\n\t000600E006006000106116006206026006000000000000000000FF15DB804C89A00035060201809881828803804C00080100\n\t52060060C6006A06C0500001120700640001100F6074470788060090862A690601454048E08F026106006006000000000000\n\t000000FF44BF000001800020803401848D01841803021A00080030640641648002601708200000414F046004006002022007\n\t08000E00814632600600600401600684600C006006000000000000000000FF14EF0008038000208012238008018218151338\n\t80000000600602602600700680200002C0060060800240033420060014C6080406246D460C620008652E2AE034006206000000cde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0100205A422E\n\t6360002042B61040980840B60062080000042446061803060000060061060B40A00860A62264242C600E2000000000000000\n\t00FF525A800001800100854A0180080388080188890A820000688608000600600604600020000681402208600003012F0100\n\t060C00060AE00600E00A02600E106106042106000000000000000000FF9B8C822401800009002881820A01800C01C2280080\n\t00004026140220336006A040400080A602421000A0000000260000160000260160060044A020600600608E00200600000000\n\t0000000000FF6DD2840511E00000800901801801810C29C008008001807046146001C8FC0600602800040600600980401600002de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t4BA300000180090180184188000582180180388184400062362300000040270261120260C600E04800600000820610800600\n\t00060060060C608010E146106004442306400000000000000000FFB30F0000818000418AD0118020018008818C8851090011\n\t61061000464463161044002062060062000062000200160002061400060D64464160500464160160C4002006000000000000\n\t000000FF4F9D000081800019881805803001905885801825888004E00600E02602600E086200124206006000106204404146\n\t00000600000600622620600000E20644E004106216000000000000000000FF65D200000180002500102B881001822853822800ade040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000A0000000\n\t510008000280080000000004020200000000000000000000FF7AFB0000AA9C49148518AA8880AA8AA8890AA80080001C22AA\n\t28C48A4022AE8120522022AE24208007A2D62062AA00014200000208A01A0020001020020022102AA4020000000000000000\n\t00FF36D000000000508000800000000000100200100300000040000260062000000060440280000004004000240C40000000\n\t100000D0000040010000448400400020006090000000000000000000FFD8AD8000000280320A200002400000004000013000\n\t004500000062260A80003483100800001500001000100100000004C00004002405005203000801480C811000624000000000006de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (012090040040\n\t41001004B204040B1005000100800884145004000001000280000280C000000080901080040000A0000000000000000000FF\n\t55D5800555F5500D913555949D55D13955C339538000556556554516D5755654755445655655640020643445455600041680\n\t005604604655600044644E4C6556516016000000000000000000FF381C0000AA8008208828AA88A8AA8AACA88AA8A8800000\n\t22AA2AA08A0AA2AA0020822022AB28A200C8320220A2AA00020A00002A5320230AA3002222222222A22AA00A000000000000\n\t000000FF2A960880010010A0020000204200020000100000000100100400000000100101000408100000008015008008080400ede040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF56CD\n\t08000000011200000001020048C00000804000008000000204200008010008000000000004000089008C80000002C0000000\n\t2405400001000801280C8000000240000000000000000000FF490F0002004000200202000400000000002004020000000000\n\t0000000000000100000900000000800000100008000000100002D00000000002004484004000000200900000000000000000\n\t00FF10C58080AA8AA80088A8AA8828AA8208AA8A2C8880012ABAA828A0CA2AA2AB2A22AA223AAA2AA0002A32232032AA0000\n\t0200050208A50A2AA0000121020122AA28A142000000000000000000FF68CB80080141100000100142140100040300000400001de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (014008010008\n\t01000140000801005044800000000000000000000000FF68BE000000A00A0080080080082180080580080080000000202120\n\t0200000200000009200000200080220A00200220000200200A002002002080002002003002002000000000000000000000FF\n\t618100000008020012800000000A00800824000000002002000000000218018002002000C800000001008020002805000000\n\t0000000000000020000001000000800000000000000000000000FF2DCE000004000000000000000100000000080000000000\n\t0000500000000000000008000000020002000000000800000000A80000800000800002000001000020000000000000000000009de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (480002420800\n\t4024004001004800000000000000800004000800000000000000000000800000000004000000000000000000000000FF37FF\n\t000004A008008008008009008008008008008001002002002002002002002003002000002000002002002002000002002002\n\t002802002000002002003002002000000000000000000000FF99DA0000018818018A1801A0182B8098058A1A018000006026\n\tC1400600600600700600E0A802600200EC9600780E4280060870160060060060020078060060048060000000000000000000\n\t00FF1D7F000001001000011001001000009010221000000042440402C209844024004C145040000040010040044040440000005de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF57680000\n\t0000000000000000000000000000000000000000000060060000000000000000000000000000000000000000000000000000\n\t00000000000000000000006000000000000000000000FFC73900000000000000000000000000000000040100000000000060\n\t06000000000000000800000000000000800000001000004000004004004000000801000800806000000000000000000000FF\n\t9655000000801000800800C00800011000A00800800004280728800200200200200600200000200200700600700200000200\n\t2002002002002002802002004000002000000000000000000000FF3FA600000000000000100000000000000024000000010000dde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (220491803204\n\t20200060502469C0226800040000000000000000FF9D7D000001A01841921811801881041831C01801800000600604602600\n\t6486406136006000046000406106006046000806002006002082802000026044027008406000000000000000000000FFDFCE\n\t000001901805801801901A20003841931851000050600600002600700614702609610050602002621640600F000046006517\n\t0060460164A0D06006D26144841000000000000000000000FF55CD0000498419118418018018800018018019018000026106\n\t00040020610600600600604000610010600610610605000600600621608600600002420600600C0080000000000000000000003de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A6000006006\n\t206407006200207000086106006406080006000084100000000000006000084202806000020000000000000000FF767E0004\n\t01801001801905809B08821821E01800800101614614008980600600620640620000600000F08600600601028C0005060020\n\t80400000806104904416400000000000000000000000FFFEEF000049D4111508180990184080180980988880000060860002\n\t0600700632700E09610032602104648E08610E05102600210E402002012280486424104847010000000000000000000000FF\n\t2BD20000018008218018418018411378018A593100006E64060260013063064060860060204060813C60062064269000040000bde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (091A00020188\n\t0801001841801800801001801800000010600600E00680603600600614640008600420685641600601000600600400608700\n\tE004004002004804046000000000000000000000FFAE7E0000018018016018018118809010C1803800000000610780622030\n\t680780780640600000600401620600600600011600E40E00610610600400400642414CC06000000000000000000000FFC34D\n\t000001800001801845801801805899A81910000101644600633620710600600680600000680004620600600601040400800C\n\t0100704D800000615020400201E000000000000000000000FF75A3000001800001001881801831E29801881E00E000246006007de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (816006006004\n\t007002C06400006000000000000000000000FF75AA000001810D15449C21841801801805C018008000806087006001206007\n\t1064060261000060042A62264060060000040060840060868162040060A208E000026000000000000000000000FF3B6C0000\n\t0180088DA41A0180180083140582381000200060060060064160060061064061000060101478860060060000040060041064\n\t06406310004002015802006000000000000000000000FFC69A000001AD1861815801841D0082940183B986002068690700E6\n\t0010E02611640608620000678C80640610618600810400610608601610608C004D46104042006000000000000000000000FF00fde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (069160C60000\n\t0E80700E00080E1060460060068C69060068040D4006146004286046445806006006000000000000000000FF3960400009A0\n\t080182180180D801801801C01820000044600EA961060860060068A60070000060000060076170060200040060048A7006CA\n\t60002060021264CE006000000000000000000000FFD112000001840C0920D8A1803901881801C03810000128E20600E02112\n\tE03781610640600010600788619611E00600010C006004806416706006086423086066806020000000000000000000FF01FA\n\t000001810801801811801809831D45881910800002710604608600610603680E0060080060140160461060061001040060140003e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001801\n\t8018018018018018018010000000006006006000006006002006006006000004006006006006006006006004004006006004\n\t006006004004006006000000000000000000FF93C3000000001801801801801C018018018010000000006007006007006006\n\t002006806006000804006006807006807006007007004006006004006006004000806006000000000000000000FF897C2000\n\t00001801841831801811A81881801020000000E00644602004600684812600600600000501608610600600600E0060160048\n\t06006006006006004112006026000000000000000000FF827B000008011811C09881811801A49C45D05110000008650C08600083e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1600602CC160\n\t0600680400E006000000000000000000FF626B0100000218018218038018019E0001981A1880000060250060468068860008\n\t06186106000004006A86006006806806006006064006006004006806005020806006000000000000000000FFEBF500000002\n\t1801801C0180180180040180180000000045264A62100064A610050640601624015400650600600600608600600480700700\n\t6005006006006002006006000000000000000000FF48D500000000180182180B801801800091801800080000600400600600\n\t6006000006056026000004006006016406006406006004004006006004006006004026006006000000000000000000FF853D0043e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600620230E02\n\t421600000800600600E00600600600000400700E007029806006007002000006000000000000000000FF2D5C000000001001\n\tC09821C01805801801C05B5080010064088C62302872A60220070050460000A080600600602600604E000006004006806000\n\t40E00600400200E046410000000000000000FF44F1000000001001801C01801A05811C81801800080000629038642E506206\n\t44028624408E0000A8006006006206006286000005004006006000046006004006006046410000000000000000FFBEDC0000\n\t000018018118418018018000018859508000006546046150846B4600050E00645600014D00680600E046006056006004006800c3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (40015883A8B8\n\t8B843841801801B0A8800000816404516016006C0642700EA0A24601000202642608C08F20724620A40C2064062062020A71\n\t16446005206406000000000000000000FF295B000000001A0180180180180180180180080000000060048060000060060048\n\t06002006000003806006004806006006002004004006006002006006005000006006000000000000000000FF5A8701000000\n\t1401801811C01C01808011881801800000600704040600604610300605504644000000600601700600600600200400680600\n\t6800026006006006000006000000000000000000FFDA5C000000001001801E01801801E0000180180160000060C6000100040023e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000016802\n\t0040706200000000000000000000FF110400202010000600A14002000000000004001000000000000960062C008848028020\n\t8600118001000060020008200000000000600440000200000000000020046030000000000000000000FF1ACA000084081801\n\tA8180B8018018000018029808000206098000040C0680602E80600200600000002600600400641608604661C02E006036000\n\t3A62864CE204000506000000000000000000FFCA24000080321A31821C01A01B03AAA2B5A40A488000B268A8800886526156\n\t88C526802816000C00A86886A4542690E89684688485682E8B6800A0EA4688EAA08008B6000000000000000000FFAA61002000a3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (812003002002\n\t00100894204300300301300340324320320300B211083003003003323512000000000000000000FF2CBD0004004112204012\n\t8020211036814010C2040000008000B0C800001001011024000000800810284000A08880048C508208C0800800800C408108\n\t00800804800080000000000000000000FF27AD000000442280C20800C008828028A28A084080000225020000828070260030\n\t0250300E00020010288640200600200220200200212A08201000A00220208000200A000000000000000000FFB30F00000002\n\t80580000001402600802084000290000880A2000611E820200204009000020000400840A0008062008022841C100140200600063e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4A10800400A0\n\t0800A04A00A00A208000002802842802002000002800803002800C000020030030028028028D280A8128C28A280085280280\n\t2912842802000000000000000000FF48AB0000002012830014014010242202000002080000000000804A0000400400000480\n\t0004800802004805001004000D48C00C80CA0A08A08802C008D0890824800000000000000000000000FFA38F000000009843\n\tA018019218418419018059158000806B1608C00680680640680628640608840000600620620644645602E116146146406040\n\t0160A6446024006006000000000000000000FF8B03000202140810800CA0800E90D00C20EC0C40800100300300315224200300e3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A80202A8200\n\t288000000000000000000000FFEC7A0003543141145543541541143345541542200000550D50D10930551550550D51550800\n\tD50A00550550D50D50800828CB0908C00A108C0800C00C10CD0D20D50800000000000000000000FF56450008000000000000\n\t0000020440000000040000000010010012010000008000000010010014008008010010010010010010010211211410010011\n\t010010C9041000000000000000000000FF761A0008AA0A80202AA0AA0AA0C80880AA0AA0820000AA82A82880A8AA8AA82A82\n\tA82A80002A80002A82A82A82A8000400000420000140000200080240220210288000000000000000000000FFFF1A000200200013e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020000020024\n\t00002002002002002002012002012102102000002142002012002002000000000000000000FF9FEB0000AA1104AA0AA4AA4A\n\tA6808AA0AAAAA0CA00002A82A82880882A82A82A82A82A80002A80012A82A82A82A80022AA2402A83102022026002AA4122A\n\t82002A8002000000000000000000FFFFDA00080002044000000040040000000040008C000080000004020080000100000000\n\t00000000008008000000000001000000200A8000410200130080000000000000000000000000000000FF8CB60000AA4220AA\n\t4AA0AA0AA0B00AA4AA4AA08C0000AA82A82A80A82A92A92A92A92A80002A80002A8AA82A82A80002A82882A82002082100000093e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C00C00C00840\n\tD50800C44800800104300300A003043043003003003013003001013003003042402002002402002012403000002103003002\n\t082002000000000000000000FFF8051040458018118018259438010038D1009801800010604604400600608600600E206006\n\t20600024600620620614E10608E006046486006000126406046006046006000000000000000000FF60040000002142010012\n\t0120100420020000122000000048008448208040040040008050048048008048050050048008008C08008C0848848800800A\n\t108008A4800800000000000000000000FF5CDB0000008C0800A00800800851800801800800800080200200220200080280080053e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001302460\n\t80000000000000000000FF87E508014400100800000210402000102000000100001200245060060001200000004000080000\n\t004000004002002C0100000204000100000000000100C04800106000000000000000000000FFB96300200880080080182082\n\t8C8008AC88008800800004204250C00200600200600200600600200002240200206690284208A1820632436124410A320241\n\t2200023002400000000000000000FFB231400C10400400400400410100420000422000000100500152000102100500100918\n\t100120100100D005005000008018000100000008001000000018420404000000000000000000000000FF8DAF400500C00C0000d3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600610010\n\t62060061170872360060820250070060410D700600A02A023106000000000000000000FF2EE40008018518118098A1801801\n\t88287F8638A90A0054E28610850E42600600610A00600600608020608600600600600601E60641618E586000206426426200\n\t480026080000000000000000FFFBF6000001801803841941801801801901801803152001632E410000026086026002016086\n\t0060404060860060460060060060060060560363104060C6046482104026300000000000000000FFDEBA00080005000C0400\n\t0200200000008000000200C02800100064864000880C00800101000000400800000000880004080000002080000400880B030033e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AB8AB8298A08\n\t05889907800011E0062884882AE2AE8462AE2262AE0060022AE2AE2262AE0062060042121840660060020064160903042880\n\t06000000000000000000FFA2E400000100180180180180190180281580182180000C64268400068060064168068160060068\n\t0000600600E00628608600610204400620680004E0AE22285604402E000000000000000000FF733900000180300180180180\n\t18038088A182589100002061160064200060060C60020860060060000060060860060360364AC04840849612E00050640601\n\t2080006506000000000000000000FF676C000001801801809805803C01883C018058B1000000600600600E0060160860120000b3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600C0468CE00\n\t0000000000000000FFC0C240000115595595595595580194988995592000005564575561505565574D655545655600600455\n\t6556556556496516496556556146136004286016556226552456000000000000000000FFE0ED000001C890ABCAB8AB8AB901\n\t8C0A898A9808800122740E2AE08F2AF2AE08F2AE2362AE0070012AF2AF2A72AF41600622C420028016806000036946000246\n\t28E206000000000000000000FF9B5A200001601801E0180180194380084380180A8001806086006001007806007006006006\n\t00600180780780780602604602600000041620600004E4A6001084002006000000000000000000FF5B440000018E90AB8AB80073e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000006006\n\t00600608708604C00600234629700020620E006046043236000000000000000000FFCAED000001801001801801801801842A\n\t418458210000006816006006006006916004096006006800006006006006C164160040060020068060000868860063160060\n\t86000000000000000000FF17FE000001AAB0ABAAB8AB8ABAB188C8838898830000AAE20628E4882AEAAE2262AC3262AE0070\n\t00AAEAAEAAEAAE0260262842AE2AE80E02700082E026AAE01428A106000000000000000000FFF13A00080100580180180180\n\t1C35C1384180584000000060A7006046006007406005106806006000006006016006146D361061062034864CE8014860075200f3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B8018AA8018A\n\tB88A00002AE2AE28E08E2AE2AE2AE2262AE2AE2AE0002AE2AE2AE2AE0066064341062421060062002061061060062CE40600\n\t0000000000000000FF4BDB000109021001801801801835800895801800000000600602600000600600608600600600624400\n\t600600600600600600404600A04E00E02400628604604C0020D6000000000000000000FF9F47000001805001801801801901\n\t800841801840000000600600622600600600600E00600600610000600600600652E13630C50E0C23064A60800D604E48E484\n\t026406000000000000000000FF5ED600000100100180180180180DA0080980181000000060A6846440806006006806807006000be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000006000000\n\t000000000000FF9EE40000AA0AA8AB8AB8AB8AB80B88980B8AB88080002AE2AE2AE2AE2AE2AE2AE2262AE2AE2AE1102AE2AE\n\t2AE2AE22E20E2AC20A02602602600002602628C2282AC02E000000000000000000FF04C90001020089559559559558159558\n\t15955953000055655655613055655655645655655655604455655655655645603600441241204E2CE28404E24E4564125100\n\tD6000000000000000000FFAEEA80000000080180180180180182380180185180000060060060060040060060060060060060\n\t0000600600600600604600408228E096516510016496026006004306000000000000000000FF0CA20000339C90AB8AB8AB8A008be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030060060060\n\t0652E53600612AC0430648608A0D604E04C110004406000000000000000000FF99A5000400001801A01C0180183590129580\n\t1A0100010060020064000060070060860060060042080068070068060060070040060C104F04E0000062861060020440D600\n\t0000000000000000FFC7670000AA0AA8AB8AB8AB8AB9418011418AB88580002AE2AE28E08E2AE2AE2AE3362AE2AE2AC4002A\n\tE2AE2AE2AE1061062AC24200C40600620070600620632628C006000000000000000000FFA89C0008200048018018018018A1\n\t8018A180180000000060060062000060060061060060060063000060060060060860860C40421022060060202860060040C4004be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801801801800\n\t800000640650628100C02600704E00780600400000E20600600600600600600014650600E10010601644640A004006000000\n\t000000000000FFBFF6880C02008001C01DA1A039099A5C09A09C018000A07206006007006827007027006046804040807207\n\t10761650600F00C0108BF2871860A0016406006286004006000000000000000000FF7F26100042009C018018458018058210\n\t09909C01000020680205600080700700680600630610400500700620700603621700E0060000064060240060060041040040\n\t06000000000000000000FFED44000800000801801801A01901853041C01855800000600602602600480600600F006006804100cbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00000000FF3BC1000000000801883801801825805881881821820002E28605E18020608E02601E00640600E00000600E4060\n\t0604600600400002E28600E0081A648600C01002400E000000000000000000FFAAB2800000001001821803A0180181180382\n\tB80A88A008600208022602600600688650E0060040501064061462160060970060042060062C612000E21622608E00C02640\n\t8000000000000000FFC795800020001201801803841901801801901A0180000060025004008168068060060060C608404080\n\tE80608681649640600400C00600621600000E00E226002004006000000000000000000FFC076800000000001E01E01C45811002be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000052\n\t83302000200803004803000D0528080000006200000000000000000000FF95D40000000018018A38038018418019018D1821\n\t00C01370824001000040960461062860060160000861060A600E00600E0060060D200604E02004E10601430C0C4026008000\n\t000000000000FF25CB0000000018018018018058018898458038819200406202090426046006006006016086006100006426\n\t0064260060060060062061064062880060164C404001400E200000000000000000FFE8DD0000000018018018018038018818\n\t2180189580002060022060064060060060160060860060D00060B600602600610600600408641E106200106406084224084000abe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A02004040000\n\t0011100000000008008040000048000004008000040010040800800008082102000000080800000003040000000000000000\n\t00000000FF62750000000A80AA8AB8AA8AA9400891400AA9A880002AEAAA28C4AA0022AE2AA2AE2AA2AE2220402AE2AA2AE2\n\tAA1021020AA24232240200200070200231C3802AA482000000000000000000FFDDBB00000000000000000000003404009400\n\t0004000000000602620604000000000000000001000000000000000000000000010801004804804000000002003000405000\n\t0000000000000000FFC61280000000400000000000010000404000000000000000000060064880000000000000000802C000006be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF4C8280080020140140140120100024100040142A000100500000404090100480400480480480000100480500500400\n\t004030900000009051000001049100400C000100000000000000000000FF0D28808000125955D55B55D55815155815555949\n\t8001D57046554516557557556557557556556111557557D5655645643655612608604E2CE50044E24ED560245560D6000000\n\t000000000000FF22870000002CA8AA8AA8AAAAA80AA8A80A8AA80080002AA2AA2AA08B22A2AA2AA2AAAAA2AB2AA4802AB2AA\n\t2AA2AA22A20A04228A22A0220222A00220222222222AA02A000000000000000000FFF0AF0000000092004000000000A0000000ebe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800280820000\n\t000000100480880000080800000220000000000000000000000000FF35CF0000001400000000002001000000400000820000\n\t8014A00204000010008000010000000002890010008000005283300004800003004803002D04280000004004000000000000\n\t00000000FF133A08800000400020000000003400009420004000000000080000000000000000000008000000000000000000\n\t000000000000204300480480080000800004100000D0000000000000000000FFAAAD900000008EAA8AAEAA8AA8018AA8018A\n\tA80880002AA40228A0EA2AA2AA2ABAA82A82AA2AA0002AA2AA2ABAAA0020022AA40A0C21020020000021022AA0B20AA40200001be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000040\n\t0538400000002410020C08400000054040100040410000480004000000010050450090100080000000400400000000000000\n\t0000FF81AC000000C00800880800C00801800800800C10800000240300200200A000002800002000200020022A8200280240\n\t2002020482003002002000002002002002002002000000000000000000FF6851000000202008000100000000020008100200\n\t0000000028080000000088000001800000000282C00008A08810008000000000000800200282000000000000000000000000\n\t000000000000FF7CDD0002801002000402000000000002220000000000800001000000000000080200400000000000800000009be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF0630000000000000004001000000000001000000200000050100400000002400040C080000000000000000000001000000\n\t000000000000004800800000000000000000000000000000000000FFFD9D000000900800840800800800800A008008008000\n\t00228252200200200200218200200000000000260300300200280200001A1634030020000020030020020020020000000000\n\t00000000FF5D53000481803C01881C81C01801841A4B081809800100624E004006016096007A06006000200000046D160142\n\t17C36006000506806007004001006007006446006006000000000000000000FF20F900000100001100200100100000000100005be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040060064000\n\t2000010400610020600E406024006006000000000000000000FF7F7000000000000000000000000000000000000000000000\n\t0000600600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFC4F9000000000000000000000000000400000001000000000000600600000000000000000000000000080100080000\n\t0000000005000801000800800000800004000000000000000000000000FF4980000001800800800800800800800800000800\n\tA00000600602000200200200280220600000000000200200200200200200000200200200200000200200200200200200000000dbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000140610651\n\t6240406007004006006000000228804004805007106084240014116004016000046204004004006006000000000000000000\n\tFF9D69000181A08801841881801801801931807001800000600600E00600600602700600600000000000620600401602E826\n\t10000400408484600020E00E017006006006000000000000000000FFDE7D0002019098018818018039058C40019010150000\n\t00641601040600600602600600600000000100640702600453653602080100E00408E0290164060060860060060000000000\n\t00000000FF507B00000180190380390184180180004180100180000060060000000040060061060060000004500060060064003be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFA8\n\t72000001801803809001821821811801001800920000610E0160004540060060060060000000000840064000060860061201\n\t04016006026020446006104016006006000000000000000000FFA708000001801041801801801C0180040301180088000060\n\t16040000007006805806006000000000106004300487806004000080C0601604602090200400681600700600000000000000\n\t0000FFD9F8000401801801925001845903944501101804800100621600000600600600610600600000000000600602121630\n\t740E0C004000C0020AE0A800200640E0C6006006000000000000000000FF01EB0000019C0087841901811841811C0984500900bbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (609C00000000\n\t000600210100411C406006006046000000000000000000FF15D4000001D01901805001801A01800254001800000000600600\n\t6006004006006306116000000000414406006206086306001000026003B02000004006804006006806000000000000000000\n\tFF25160006018008018010018018018000000098400001806407A06020006106006006006000000006026A86006D06006006\n\t200000200812802006884006806006006006000000000000000000FFA3810000019410418499018318018018050458200200\n\t46626614600602F086604F86006000000000625284160807066004280014107006016000A020040840060060060000000000007be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006046006006\n\t80E006005406246000000008805C0414600610608401020650610A848000016004044016006006000000000000000000FF2D\n\tD4000001800041803001805801805D008898208001006006006000016006084A1608610000000800400400EC860464040082\n\t06800082208280006084404004006046000000000000000000FF0E450000018000418018018058118001002A184000008078\n\t8780600601600600400E00600000040800400400E80620600400820000610680A22800400401400600600600000000000000\n\t0000FFA306000001880081801981A0194195C4002118000000186086006600006E0614408600610000020020E2148061668400fbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF534A00\n\t0001901805801C0084182D809801809903A00000610D206006006006406826006006000008C06A0404690690600640821040\n\t6006016000006006404004006006000000000000000000FF6C7E00000180100380181B80180BC01800901802000004668600\n\t600684400600402F406000000000A04004106006006104000006006016000000006004004015006006000000000000000000\n\tFF3046000001801201801201C21951941C548C9800000002600EA06080027006244006016000000004004015806287506804\n\t20000F840006100054006804214006006006000000000000000000FFFEB200000188100180180180184181180080190080200007e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006002\n\t000000006006004006006006000000000000000000FF62850000018018018018008018018018010018018000006006006000\n\t006006006006006006000000006004006006006006000000004004006000006006002006006006000000000000000000FFE2\n\t86000001801801801800801801801C0180180180000060060060060060060060070060060000000068048068070070060000\n\t00806006006000007006002007006006000000000000000000FF425B000001801C01801804801801A01801001801A0200060\n\t4600610000E006006A16046006000004806004006406006006000000104104046004816006026006006006000000000000000087e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (068CE1500465\n\t56806287006106020494806800006007006D06000000804002000284806006002006006006000000000000000000FF956000\n\t218100180380188000180195C140981001800000600504E006086006006606006016020000A2608080604601600600000000\n\t6102100000006006000806007006000000000000000000FFD1D4000001001805821800001801800000001501800000608E50\n\tE54080632700690E0B612602054054710C0360060A754E0080B1054800000001006006006004006006000000000000000000\n\tFF14B0004001001801901884001881800000829001840002620600600E0860060060264060060100080164244064060060060047e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF8E60000001\n\t801801C010010018018000008010018000007006008050006486007026006086020480806026006004006006020000006002\n\t001280006006006004006006000000000000000000FF66E9000001801801801001001801801A0101180184000264050C6100\n\t8460360060060A6006000011006083006007806506000000006002004000006006004007006806000000000000000000FFC9\n\t59000001801C018010010018818018A1829A01820004708E2A62AE0062860070EF3CE0AE0082A800E36E22E2260AE2AE0480\n\tA882E002004000006006004806006006000000000000000000FFC0A2000001001C01801E000018018004000112018400007400c7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80CB6216810D\n\t0088E956B0C806816816000000000000000000FF303A0000058C18098018C5841801A21A42091009800000E00ED060060160\n\t8E00601020600600000028600380601682E2060000080070C6324000206006045496306306000000000000000000FFF16700\n\t0001801801801801A01801A01A00A01001800000600600600000780600600000600600000000600600600600600600000000\n\t6806004000006006804006006006000000000000000000FFE71E000001801801D41005401801944000201B018000046C0600\n\t0006006046006A860460060000001060020060040060060000008071001008000060068068070060060000000000000000000027e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (601E22802000\n\t8029000000000000008228720408800070000000020440004280000400260000000000000000000000000000FFB3C9000002\n\t2006080001440000000024F00804200001008008296047180001000201010200200000000480000000920108008000008808\n\t2C8400408020580108000000000000000000000000FF85ED0000019018438018018198A98201019013018000806284000100\n\t816286886002B8600600000001600200600604E0060000002142A600000024618E000014006006000000000000000000FF58\n\t74000211805805C09C09C0DAA9A8430920112580000C6A8682088E2C6A2628EC22096C06210800816B52D26906106836010200a7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (7F0004008208\n\t30D00E90C10C40C14880C00880800000300300313201200200B00201200200100150B40332B0028230020005010C30034834\n\t01233003003493003002000000000000000000FF58F90002082A60102010BA20204031400A20028800000840009248808050\n\t0CB1480000C004008800FC0804890800000A00000E80800804D20800880800800C80A88880000000000000000000FF5B2600\n\t0000A4080080800100080080080100880180000020020000020030020020020030020000020020120421828820020001081C\n\t200200200201200200A24200220A000000000000000000FF01E60000000104001004001205000C04000000060001021000000067e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (022022000022\n\t00004000002A82A8000000000000000000FFD8C3000200A028008A0A00800A00A00840A00A208000002002842802D02800D4\n\t2002000002000800B02D42913002002902800000902912902840802932A22C0A802802000000000000000000FFAF6F000200\n\t2B120120500140120021420524030B0000004000804A2080480480400080400400084085080C8408C8004C40000910A28805\n\t008800888A00888920804804000000000000000000FFF67100000188B801801843081901921849101805800080680608C006\n\t10600610680610600600000004600C00630610612E000000016224046000006306526026006006000000000000000000FF9F00e7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A92A82A82A8\n\t2A80000000002A82A82282A82A82A80003280882082A80082082A82A82A82A82A8000000000000000000FF448B0003543501\n\t540281545543543085343102100000550550D50930D01550840D515500000008008808A0C90C40550A88800450908CC0CC88\n\t40D488A88B0C80D50D50000000000000000000FFAD0400040004220000000000040044240040040000000000010010000000\n\t01001000800001001011001001000001801000001001041001001001081001001001001000000000000000000000FF58E400\n\t00AA0000AA1080AA2AA0AA0A428808E0400000AA8AA82880880382A8008AA82A80000000004400002002002A8048000220000017e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000084280080\n\t0000800800800A00800840800080080200200280200000280080000000000000200200200200200200211002230200201020\n\t2002002002002002000000000000000000FF2F870000AA1802AA0AA2AA2AA0AA8B00A80AA08800012A92A82886892A82A82A\n\t82A92A80000000002AA2A83222A82A82AA0002006001402A00000622AA2A82A82A82A8000000000000000000FF2260000000\n\t0022000024000000000400000400840001001000000200020000488000000000000020010208020088800000000080420010\n\t000000000200000048000000000000000000000000FFC2310000AA2102AA0AA2AA2AA0AA0800AA0AA0AC00002A82A82A80A80097e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000320\n\t000004000000000000000000000000FF0D0D000410C00D00C00504C00842800C00800C008001003083002403003113093203\n\t0030110008082132C3403003042003002100023003002800302202003003003002000000000000000000FFD49B0000018018\n\t0180004181180182581100180180000060465440061160060060061062400000000060041061060060060060004060061060\n\t00006026006004006006000000000000000000FF7DF500020120800100000100120021400520020200000040048448200008\n\t04800004004000800808800804890004804800004820890850810800910800800804804804000000000000000000FF21F7000057e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (084001081000\n\t080004100000800901100C0280000080000440310220300200100000030000000000000000000000FF849900000800000000\n\t010000800C004000000001000000008000608611008010C20000000000000001000420008085000000000004080088000048\n\t0080004800800800000000000000000000FF1C3A000001800890844003800D6082091C000840800040602648000200200600\n\t20060860200000008022B6882042082802112480212002002001003052052402402012000000000000000000FFE613000580\n\t400400400420400010180401000400000100100122430100100900100100120900000820100100100411000100000000001800d7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801001810001\n\t801C01801914081021808000600640640630600E04620600600000080100608900E02604708608E28000600404480141702E\n\t102202306016000000000000000000FFEBBA0000018018018080418A181190600108300982C010E006048006086606426316\n\t0260900010000062622063161060060060000061C612700810E006606006086006000000000000000000FF8AB90000018218\n\t11844001941921810041825011840021628601000004400600600614610000140800620050640600620600600001420620F4\n\t50006406056004056006000000000000000000FF233B000000040000000020000008088040040000004008028004620622000037e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000461260C00\n\t02006006000000000000000000FF2A0900028F8AB8ABA8E2C98AB8718802009818AB8000AAE826A884A8AAEAAEAAEAC6AAEA\n\tA80000007062A2316B162AE00E006000606004230060306756060C022AE2AE000000000000000000FF6EB900004180180182\n\t0021801909810090005801800000630602020600600600602600600000080000681208600600648600600009650400C80000\n\t6026112406006006000000000000000000FF45C7000001801001800005801805825824831001800000600E00600000600600\n\t60160060000000200AE0020360CE00602600600004604810000012E10E2020D0006006000000000000000000FFE04C00000100b7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (610E00600080\n\t0841006800C0600600608E006000136452006800807006117042006006000000000000000000FF8178000555955155B54355\n\t95580191014415595580005565565561305565565564CE55655000000449650012E55655608600600055554744601421640E\n\t207556556556000000000000000000FF772D0000898AB8AB88828B8ABA838A9CB38038AB80012AF0C6A8E08F2AF2AE2AF207\n\t2AE2A800000002E2AA0262262AEC260060000060802A000043600620010E2AE2AE000000000000000000FF366B0000018018\n\t01800001801941821C11001801800100700700600100500700700700700000000802700A40700600625600600000681080C00077e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018000058018\n\t09815804001A0180000060060460000060060060060060010008140073293060060062060060000040020C281520E4162960\n\t06006006000000000000000000FF8672000201801001800201801A0182023180180180008068068062468068060069168060\n\t0000000049600200600600688600600000609200A000086086006806006006000000000000000000FFC3570000AB8AB0AB8A\n\tA0A98AB8B78840810AB8AB80002AE2AE28E4882AE2AE2AE2262AE2A800100482604002E2AE2AE02E0060002AC22630300412\n\t68260362AA2AE2AE000000000000000000FF6B6D000441801001840001801801802000829C0180000064160460460040060000f7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E11611625400\n\t6006000000000000000000FF90B20000AB8818AB8000AB8AB82188D8218898AB80002AE2AE28E08E0042AE2AE2AE2AE00000\n\t00000860221062AE2AE0062AE0002062022420000160060C60262AE2AE000000000000000000FF683E000001841801800001\n\t801811801811001801800000600602640002600600600600600000000421620201600600600600600008C10A10A004046446\n\t036012006006000000000000000000FF774C0000018138018000018018838459028258018000006006006026296006006006\n\t0060000000000260884A60060064CE00600002602204200049610E206302006006000000000000000000FFD2FC0000018018000fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000006004\n\t4A634A006000006086000006200100106004486006206026006006000000000000000000FF7B8D0000AB8AB8AB8000AA0AB9\n\t4B8A18C50AB8AB80002AE2AE2AE4AE2AE2AE2AE2AE2AE00000600040E2AA20E2A82AE22E2A80062AA0260060004262262260\n\t822AE2AE000000000000000000FFC61700015595395580015495581594990193595580005565565565305365565565565560\n\t000060040160024365505564565500060CC4344160040464CE08E50A556556000000000000000000FF78AE00000180180180\n\t000000180180B80180180100000060060060060060060060060060000060000060020C600000600600000600648642600000008fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000188380\n\t4003801001800000600602642600600600680680600000400002E0004A60000064CE00000000630648600049610E04601200\n\t6006000000000000000000FF7257000001801801800400001C11840011801001800100700600600000680600200600600000\n\t6004206004016000806006001004000040026004046446097320806806000000000000000000FF4FCA0000AB8AB8AB8000AA\n\t0AB8218880B18AB0AB80002AE2AE28E08E2AE2AE2AE2AE2AE0000060001C62A80062A82AE1062A80042AA01E11E000106006\n\t2060062AE2AE000000000000000000FF5FEC00000180180180000080194180184D0018018000006006006000006006006006004fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006006\n\t000000000000000000FFB13C000001801881800101801801815841800801800040604600600000608781600704610000C000\n\t006002006001906006000100322103000000016026000002007806000000000000000000FFA3EF000405801A01800209461A\n\t1180B823840C018000B868060064664070064068068260005C64000465C2006000C1600600148009200600014000E00E0010\n\t07006806000000000000000000FF455C000101C01C01800010605801840003801601800100608655600100700600200600F2\n\t28004004086004006400006006000000004200306004086016006007006006000000000000000000FF1080000401801A018000cfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000040000060\n\t0C10E00002C00600000420C402082200006006002002006416000000000000000000FF969000000580180188000108180980\n\t1821029801880000618677620000E0060060062164500060000062C00060807140060000044F64061200C000624602A00A00\n\t6006000000000000000000FF383C000001C01801828001A51801820015100A018100C0E20E000006D0702604234690700000\n\t400000604608625008604654020000431220A00009608E50220730620E000000000000000000FF4AF3000101801B01800101\n\t803811840001040801800000602600040040610620A0060061002564000C6206006400006006000200006106A02100106006002fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00008202400C\n\t00208000000000000060060000000000000000005200000280804A00000404A8000088410110508000490108010080000000\n\t000000000000000000FF8A32000001801801800001801809800125029C018800206096420000316007022006406000004000\n\t0060060063404060062A0200000010206100006016546014086006000000000000000000FF39700000018019018280219319\n\t01850009085805854008622600041604643600224608600000400000635601601015604600000035210614E2000965060164\n\t06406006000000000000000000FF908A000001801881900021001881809880003803822009602600600E02620E002106006000afe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D2AAA2AA0000\n\t00000000000000FF0A750000010000000004010001400000A00400000000004804020000000000A400010040000000004A02\n\t00000000000080000020080280000000480001000080001000000000000000000000FFF5490000AA8AA8AA8000408AA82089\n\t08C10C880680002AA2AA28C0AA2AE2AEAAA2AE2AA00041C0001C221A00200028210200033208220200200010200210240E2A\n\tA2AA000000000000000000FF90AC000000000000000002000010008040020451800000000002640600000000600000000000\n\t00002000400100000100000000040400200240000404404C4440000000000000000000000000FFBF050000000000000000C8006fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A00008224A10\n\t20002AA0020002022820133420000120022020C32AA2AA000000000000000000FF66B7000401001201000403201000022011\n\t00024000008050040040400048050010050040000840000010400C08010000008000000200200C0000008111000004805004\n\t000000000000000000FF7854000355D55D558001555558159518159159558001556556514516557557107D57556000556000\n\t01608E436000D564560015164560464160000464CF55620C557556000000000000000000FFF2A50000AA8AAAAA800088AAA9\n\t4A88088288AC888000AAA2AA2AA28A2AAAAA2AA2AA2AA00002200040B28220A80032A22A80022230A48A20A00042222222A000efe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020020000020\n\t200000000008000000020000000200C800000000004002000A1A01280000201C408004010080000000400008200000000000\n\t00000000000000FF93C300000040000000000000008203400200400000000000000004200000008810008000000000000280\n\t404A00000004A8001040000010148000490109050050800800000000000000000000FF824B00000000020000000240001000\n\t00B0000400000080000004000000080044800000000000000220010001000000000000011003032100000204044010020000\n\t0000000000000000000000FF56110006AA8AA8AA8000A88AA8208848008A8CAA80002ABAA828A0CBAAA2AA0122A82AA0002A001fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (680600000000\n\t0000000000FFD1BB000000000405001101000205004000005000000000023022C00080400404440810400000000000440010\n\t140050080040000410400D014000804004800010004004000000000000000000FF47F1000020000200800800800800C00800\n\t840A0080400028020020020020000000020020000000000020020020020020820020002800A0802000002002000000002002\n\t000000000000000000FF296600000000004200400000000000000800020200000088000000000000000A000000000008002A\n\t000000000000000000000800800000000022000000800808000000000000000000000000FF74370000000000000000800000009fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (202002002802\n\t802002002A06002A02000000802002000000002002000000000000000000FFE67400000000000000000100000C0004102000\n\t000000100C400440000040000040100040000000000040000000000000000000010040040040000040000000000010000000\n\t00000000000000FF07C8000000000000800800800A0AA00C0880080080000820024120020020020020028020000080000020\n\t0200200200280200204300301201800101A043001000002002000000000000000000FF7BF100004000002180380180180180\n\t1811821823802000E0068040070260060860060040001000280060060260060060860060042040A400602100400600002000005fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (408480180180\n\t000060002000001060060860060040100100000060060060020060060061420020C402000000410600000000601600000000\n\t0000000000FF7F70000000000000000000000000000000000000000000000000600600000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF4903000000000000000000000000000000\n\t2000000000000800006006000000000004000000000000000004000000000004004004004001000000000000800800000000\n\t000000000000000000FF703C000000000000800800000800800800801800800000200300000200200600200220000000800000dfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF21F8000100000001A518015C1011889A200019090000044826446410A86226106854286008400000006410126002\n\t40E482402902012103004010094046800040006086500000000000000000FF27BF2000000000018018010438018018028018\n\t81800040600600600606600600601610600020800002600284E00609210200308412481202600080460601880000E0060000\n\t00000000000000FFBEBB000000000001A05801081901B0024184190980000C754700044F406246446C064544004803520462\n\t8609640708000600600502400400000210400F00000000E106000000000000000000FFE7DA00000800200180182180580181003fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060020060\n\t10400101080008020011006006001000006007000000000000000000FF9328000000000001811A41101009801C04C0180A08\n\t0000600208E42001600610603540200020000000601010600240620000002001114084048021704E0012A000600620000000\n\t0000000000FF3D4F00000000002180180100380180804190180380200141061080410C600700600650020000000000600240\n\t6002806008000040A0004208028020600E000D00006007000000000000000000FF5D66400010002001805A41421B01802081\n\t821801800034630620042E00600634640E0484001004D000630308640600400200202010012B80200000608E00000000601600bfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (841801800000\n\t401610600000621601602700000000000428600611E002206C064060820020002140040150066800D0C06006000000000000\n\t000000FF10CA0000100100C18018C3021001C0000580180100000460030060068064068064C4000000000000106406006802\n\t406806006002003102204001006806800000006006000000000000000000FF67C00000800000018018010018018100218118\n\t018020006006C46000047806007906100000000004006006202800006806006004D050121060048040068000000060060800\n\t00000000000000FFE0AA000000000041841821045401801B82B09908080005416700601610E0060060850024000000000064007fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t04FFD8AA000000000001805801041011A01809801A02000004400700622E8060162060050060000800000060068022000072\n\t060072C0480C04124120902006001400026006000000000000000000FFA8DC00000800000180180140100180994180180800\n\t0002400680620000700600F405006000000004006A461020000062060060010003051140040020A600080028600600000000\n\t0000000000FFBE05000080080005801801201021810000801809000000400600620600680610600400000000000840602680\n\t6002006006007084004C00144000004146100100107806000000000000000000FF26210000000844218018A1001A1986414200ffe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (220600680600\n\t648490040801240400C804006206006006000000000000000004FF4E1D0100002A0001C21A01001C01843901801801800042\n\t000411644610608604E0C400200010000200410600201691640E007040C40002922102884004007107047006000000000000\n\t000004FFCFAD000000020001C21800001001821880C01E00000000404300E01688608650E0B4006000000000006C86440000\n\t08700E00600001018A00404000A006001080007006000000000000000004FF4728008100094105801804041641E078008418\n\t0000002040361860000060169A710C006000000014206206A2080800E00640680102880304E205012006000051806006000000001040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018000000004\n\t2060060060060064044040004000005140060460060060060060020000060200000040060060060060060000000000000000\n\t04FF48BB00000000000180180100180180180180180180000000040060000060060060040060000000040040060020060060\n\t06006000002000000004004006006000006006000000000000000004FF3BA4000000000001801801001801C01801C0180180\n\t0000000500600600600600600500600000000000400680280700600600600000480300000100400600600400600600000000\n\t0000000004FFD518000000400201803A01041811801811801A03800000000400600000600F0060040060000000044040060000801040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tEFBA000000000001801801901801840421801809940020414780E100026516006026004000000516006006002006006C5600\n\t780480400480644E000206006004006006000000000000000004FFA26F000000000021823801001A019DA051AAB809800080\n\t000600600E0660060060041040000000000040063060060064061C6000002006006000040006006800006006000000000000\n\t000004FF5892000000000001809803A01801802083889A09800002495415644828708608614E8484A0110106006016A0E546\n\t40F10640600B000C05000007000006006206006006000000000000000004FFA92E0000000000A18A3801001801800001823800401040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006406042005\n\t004004A42000044206002406006006000000000000000000FF2009600000000001801801801E01A00401801801E000A04004\n\t0081000060060060060000000000000060060048060060060000000028070024080050060028060062060000000000000000\n\t00FFB0AB000000000001801803301801821A2180180992008080AE02600000752E08622C8060000004890040068050060064\n\t4E001001000006000021004086026002006116000000000000000000FFE991000000000001801805001C0180182980180180\n\t008100BC0EE2260870461864BC22E2A020808020480E00C2A620E086200008001A064000010041060468060065160000000000c01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00A24C468308\n\t4E0262360B68A68240000288408868AE8268C6896A1684E4CAA04812050801000A0689680CA06846040000000000000000FF\n\tBD5500000000001180190188D841801921D01CC1800010D09650608640E10600620E416000000200A3620648420E4268C650\n\t2804150320486080AC894E245204106106000000000000000000FF4B2B000000000001801801001801A01801801801000000\n\t0005806000006006006004006000000000004006804006006806002000000002006000000006004000006006000000000000\n\t000000FF1970000000000101911805801801840305801801800004400640000642710600640610400010000011680694400600201040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF354D\n\t0000000084000000221004600400201800210000080000006016A088C88680000000000002000884900400C02001202AC200\n\t944000080010684588020040480080000000000000000000FF02F30000001800000000800002000002102000000000000048\n\t09E00E8008008800081000000000006002001A02001C02800108004880802000000000004000000000000000000000000000\n\t00FF81D10400000000099218118398898121C980591180002562260000204062060060060000000080000060260060060060\n\t06006012002018808000030026316004006006020000000000000000FFB170000000108401CA1A2BC2190BB2A00D80DA018000a01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (165264440542\n\t06AB40004A404600E106206006000000000000000000FFEF5C0400000C44A0D20C08C30844C50830A14CC080014034030030\n\t9280280282300340200000150120312B0A314B04310300A910303852003009013503303243003002000000000000000000FF\n\tF54000000004414024020C2C20043A82024032440000D2CD80B24880020000004B80A20000020900820940800918818C18D0\n\t14E8215061134880908A40000704A00820000000000000000000FFD37D000000000000880900800C12800A00C18880800000\n\t001200010284682680202240C00000042000200A20202202200204310482260344200004600208A00800200200000000000000601040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00202880A82A\n\t82A82A80A02000000000022A80002100007801C01800200A02100000000002A80000002A82A8000000000000000000FFAED8\n\t000000400000A00B0493280080CAA4A002028000A02A12802802802000002402852000000D0080283280AC42802852852A08\n\t808892830A02D02802002802802802800000000000000000FFD2D600000000020140123020100122020900129000008CC900\n\t824C00004004004810904000000800000B00940910848A00A00104C0404048490102C8000000048048040000000000000000\n\t00FF4907000000000001801885881A11901901881815800014E14E08C006426026006106086000000000806406006006116400e01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFE4150000\n\t000000AA0AA0AA2AA0AA0AA0080AA08400002A84002A82882A8AA8AA82A82200000002802A82082400280282082080400082\n\t882204002A02A80000002A82A8000000000000000000FF7BD10000002001541542C41101541040143543000000940B10D50D\n\t30D50550550490C10000000D00D50850CC0AB0850810C30808010C40CB0800C10D51000800D50D50800000000000000000FF\n\tF71D000800400000000000200600400042000410000100100100104100080080080100000000100000100110150128114114\n\t0011000001011001011001801001001000000000000000000000FFC4AC0008000002AA0AA0000000AA2900000AA02000000000101040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0100C0414080\n\t4900800800804804800804004000000000000000FFCBB9000000000800800810800A00804812800810800000202200244200\n\t200200200001200000050000201220200200211201220A00800A0D220010A002002002002002002000000000000000FF7172\n\t0000000000AA4AA0802AA0AA0805806AA0C000002A81582880882A8AA8AA9AA83300018000022A83420B8282282202201D20\n\t5E1A403001022202A80000002A82A8000000000000000000FF661500080000040040000824440044054000002A0000410020\n\t0000000008008010200C00000000000002800000000002000002C0AA01000004820A0000000000000000000000000000000000901040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (440001061005\n\t00100500000100100102801000004000800000000001C000061000108700005241010001000000000000000000FFB82A4000\n\t00400C00C00D00C00C50C00C90C14C00800100300300204301300B00300300200100100101200201200214204A0031030030\n\t4300300100B003001003003003002000000000000000FF09EC00000000180180180181580580180190180180200060041140\n\t0600600601600600612020008802600604601620E10600601654420E00C480006006006414006006006000000000000000FF\n\t1DB90000004010012010440010012312210002420000800A848448008000040040048800000008020009208008488488208C00501040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (95D200084000\n\t000000200200000401004808C01004200080005062161201280000082160000000000000004000082000000000000000C024\n\t00901202B0208200016000000000000000000000FF86F700000000000000000002802800000010C000002000000044600601\n\t0008010000006140200000000000054008540110004810AC0C5080820080090080004000E800000000000000000000FF869B\n\t00001000101000088084280010000C800802800002204208C02200200200600210200001018800280A002822912C22042082\n\t40200210608009200204010C002002002000000000000000FF6314400800400400400400440402400480400404000104100500d01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04012A046100\n\t004080106024006006006000000000000000FF37600000000018010018018018010010018098020800006082206006406406\n\t00600E08600000800000700600300F407006022006202000026000024554446014016016006000000000000000FF7CCF0008\n\t0000180102198185F8080060059058030C400062820000862062060260A640600000000A00600600678610640E00600019E6\n\t5A01E07200400400200C00602E006000000000000000FFBAA2000028001809043803801814088029801009000000E4460805\n\t081400CE04614600E000000090006006206006016016006000000100306100114004008284006046006000000000000000FF00301040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060060060\n\t0611600000008080400601000E40620608000402080682410000600510A94A006006006000000000000000FFC51A20000020\n\t10AB8AB9F18AB8AA8E08ABAAB90580000D6432A88088AAEAAEAAE846A0600080010000600620244616621604031804861620\n\tE000AAE20621A3822AE2AE006000000000000000FFF9510000000010018018118018008048018018D58000436C0204000600\n\t600600642E0560000008000562060820AE08E00E023041506004086C00006056822012006006006000000000000000FF16F2\n\t000000001801001803001801009001801801000000010A0064200040060061060860000004805040AE0484064060C628A10600b01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800001801\n\t8018010018008108018018418000A820020062460060060065060060000008001148060860068065060068061110C700A801\n\t006004045040006006006000000000000004FF5D1840000020195595595595595494C955955B558000106552D56110D56D56\n\tD56D56A4600080040555644E1264C604604E4564D648F555512405336554425200556556006000000000000004FFB8AB0000\n\t002010AB8AB8050AB8AB8838ABAAB8118000000142AAE08EAAEAAEAAE816AAE0000002002244B62289162170464882442020\n\t063243002AE32C30220A2AE2AE006000000000000000FF3BC5000000001001801E01001801801801C01A018000A21002006400701040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A0860000120\n\t4630C08C006006006000000000000000FFCBF100000000180180180100180184180180180180001120020460200040060060\n\t06154000000C8400400604640705684602F45204000011290442E006104094004006006000000000000000FF55CB00000020\n\t1801801801001800814801A018018000242002806006806806806806C060000000000044D650E0C608608608610650211604\n\t6400906002026442006006006000000000000004FF409B0000000018AB8AB8AB8AB8AA8808AB8AB8AB80018162AA28E2C82A\n\tE2AE2AE2AE0060000010062AE90640680E31630E207007008A24A070060062AE20E8022AE2AE006000000000000004FF30B000f01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00600600600\n\t6000006000000106006006006006104014512114006000402000106016006006000000000000000000FF6A2A0000000A98A9\n\t8AB8210AB8C98A98AB805889800001210028E0AE03C2AE2AE2AE2AE00000000001400600600600600644631608802220E000\n\t2262140062062AE2AE2AE000000000000000FF212F0000000058018018030018058058018138218000122082026400106006\n\t00600600400000000444C01654601600E00601604E002480042004106110046026004006006000000000000000FFED3E0000\n\t000018058019090018418018018C1803800020A22A0060062060060060060060000000001044C6016346346356326106226000081040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000418200018\n\t22001801801801801840000000000400600002600600600600600000600040002610212612E12600C00208008C12A0000920\n\t04086086006006000000000000000000FF06F70000000AB8AA0AB8AA0AB8A38838AB8AB82200003302A42AE0AE1062AE2AE2\n\tAE2AE0000060002A820E34A30E30630E24440000222005600008220C22E2262AE2AE2A8000000000000000FF9A5400000011\n\t5912155910155915935955951915000032042C5565303065565565565560000060040C049643241640641608442444A22040\n\t60044424C0456456556556550000000000000000FF90A680000000180000180000181181180180191100000000040060060000881040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400520200400\n\t6007006806000000000000000000FFB2550008000010000018000018458120018018C000004C00D402602680600600600600\n\t60000060000004C601634634635602521424E00400400008A914116006006006000000000000000000FF8642000000001000\n\t401800001A01800001C01804000000820600620032F00680700600600000600080001614601600F006116123084114404000\n\t002424026116806006000000000000000000FFC8DA0000000AB0AA0AB8AA0AB8898E00AB8AB809000000001428E48E4462AE\n\t2AE2AE2AE0000060002A80462060460560462141400462205AC0002721442063262AE2AE2A8000000000000000FF2F98000800481040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00600E402010\n\t0060104000060060264A6096806404046004092000D00002206006002006000000000000000000FFB3678000000038004039\n\t04021831801821C01C05000001050454630000F80780600E00600800600800000600400624600600440300401400E0001040\n\t02442002007006000000000000000000FFFBC9800800021C20401882029D2D803801D018011000060004006086806A068070\n\t06006000106001109006274006117007004910A06000006400004802022007007006000000000000000000FF626200010002\n\t1620021840411C01802401801800000040000601600100620600600640600000600441080640604600610F80600442C0000800c81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180000180008\n\t9801809821811800008008000602624606400E00E2160262000060000000064C608601600602600400022200E1000824140B\n\t6014006016100000000000000000FFB8780000000018200018000218018A1801903805080000020009600000420600600620\n\t60003062001880062360060162260041140120160A640802200400600C00E006000000000000000000FF2A85800000001802\n\t001800003C41804083B29801020020000E2100A720608602601601201004600000045600620610E006006004CD4100002080\n\t20028A00E0071428AE080000000000000000FFF2E7800080003A00425820201905800221801C01080020828654040001600600281040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008008030008\n\t006000000000000000000000FF9E0380000002200000000000000000A00000000000000C0108006026008000000000006000\n\t0001000004C00003403403500484205001000004800A0100100100006000000000000000000000FF92000000000018000018\n\t0002184192C045925800080000240610000040428602600640201002620011002E0060060862260060023301061020001041\n\t040040001320C6000000000000000000FF6D0B000000001824001800093801800081801801048050000E44828600400E0162\n\t0604A2004060000004061064860060060460000024220520102440040C4004002006000000000000000000FFBD5E0000000000a81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AA2AA0002AA1\n\t2000020220A30A30230A22A2A022A2A032208022A2AA30A2AA2AA2AA000000000000000000FF627C00800000100020000000\n\t00000002000010010000000030020200000804800000020000004308000020A301201281200000B40800080402000900B010\n\t02A0000800000000000000000000FFE7D90000000880000AA8000AA8AA8A08AA8AA8AA800000602228C28A3A22AA2AE2AE2A\n\tA0002AA40000004A2420420520420820100022342BA4202022222022222AA2AA000000000000000000FF2089000000000000\n\t000000000000000000000001000021440002600600000000000000600000024200000014801000800040011005001000000200681040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0AA8000AAEAA\n\t888CAACAA48080002AA00228A08A2AA2A82AB2AA28A001AAA0000000020020020020022AA2022A220200200020222A202002\n\t28A2AA000000000000000000FF4B268008000010004010002010010204010010010000214040004040001004804804000000\n\t004000000110880000000001100004100004000020080000040000000805000000000000000000FFC1BA9000001558005558\n\t0055595594D9559558D30001554286514156557557556556516000556000000496086416406416D5640645632650E1084464\n\t06436016557556800000000000000000FFE1730000000AA8000AA8002AA8AA8928AA8AA8AA80000C248A2AA48A2322AA2AAA00e81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tA0208000000000000000FF856700000000000002000000800600000000000000008000010000000000000A00000000000000\n\t00008000000800680000000800000000808000140000000000000000000000000000000000FF29A700000000000040000020\n\t000004220020021000010005400202200010008008000000000001100004C00483403403500000900100104A048804808010\n\t0000000800000000000000000000FF58B7100000000000000000000000000000000042000000000800000000000000000004\n\t00000002000000105000100080000000400000C00080000800000304B0040000000000000000000000FFB6768080000AA80000181040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6C1441608001\n\t02B600605651405600688E00410700C0A020C006800006007825A00000000000000000FF0B3C000000101101040001001225\n\t0080100010010000004A00084800000684424000000804044440000000001100040800801001004000004400005004000014\n\t000904010000000000000000FF7E6D000100000800A00C00400800800800D040009000002002002002002052000002002002\n\t0021000002A280200282600200208A800802000040413002000012002002800000000000000000FFAE6E0000000A40800002\n\t440000000020080000020300000410400040008280200080000208228220000010000150810028000000000900000280000000981040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018008018008\n\t0080180080000020020000020020020060020028000020000000020020020020020020020020020060000020040000020020\n\t04000000000000000000FF329C00000000000000000000100060000040000100000044000040000005040410000000040000\n\t02000000000000804000000000804000880002824001000000000001000000000000000000FF5A7F000000000800A0080080\n\t0DC4810800C00800800000200210200200200200200300280300200000000280200240280280200200300208200010200200\n\t0002002002000000000000000000FFD9F9000080025801801823C09C01805801C838058C8100741640504600E0AE1269060000581040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010680001400\n\t0000000000000000FFE3DB000000005801800801801811808000041805800008600400000000200600610608000400600000\n\t000604640620220630620450014400E000202004000016000104000000000000000000FFF77F000000000000000000000000\n\t0000000000000000000000006006000000000000006000000000000000000000000000000000000000000000000000000000\n\t006000000000000000000000FF714E0000000000000000000002000000000000000000000005006006004000000000806000\n\t800000000000004000800000001001000801000000800000000000006800000000000000000000FF31C7000000000800800800d81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006010000046\n\t04240E12E02E00600635702A0004804340460001060000C2000000000000000000FF8357000002001801800009A01841A518\n\t01001805800000604E106000016046846804006016006000840A541000A48028040850B61020000400280020040801060068\n\t0C000000000000000000FF1327000000003801800001809A01881803023A1381000070A64062060060060960A60860066060\n\t000180860020063022062062068128900E800000208400000E007044000000000000000000FF1A0A000002001C11800815C0\n\t9801A8000410384180000261560002060060071070260008040060090014A700614F02B0560061440440051022A882A1241000381040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3801A0380180\n\t180580000060060060060170074070040060022060000001041000040040044041E501118E0820000241462A000600600200\n\t0000000000000000FFB877000000001901801801841A21C53801801801800000610620600002600614600400600220600002\n\t002C0000040040040040040004470460000054065400A6006002000000000000000000FFA3C10000000018819418018A1C03\n\t800000801801800000688E4000000430064970060008000060000001068420060060864168062522228100008044A6000046\n\t800002000000000000000000FFE57A000000001C09801803801809810000901C4980800C600640000600600601600600080000b81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (007842000000\n\t000000000000FF557D000000001941821801901A01900028801A858000E0E156006740202006086116006000006000400806\n\t8C610611601614600C011F870060A00CE906400306007202000000000000000000FFE992000000001801801885A51C018020\n\t4004194180000060060060064260460062040068800060040280041062040020040040570020228100040068060004460065\n\t00000000000000000000FF3A09000000001801AA1801A0580580000000180180000060360860000060268160060060100060\n\t04000006026006002106016016D46812110004046006000006006000000000000000000000FFF94C180000001801C018019000781040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000440C60\n\t04006044005C2E13220810800C006006420106006106000000000000000000FFA5F200000000190182180180B801A2580140\n\t180180005070074460A600600604600C00710600600404010500600402200C0840040150C400200400602600000600600500\n\t0000000000000004FF75150100000418A1A01883C8B80180180120182180000068268061200460460064D400700600620025\n\t00040064CC13200C0A50A400004D0160008260C6000026006045000000000000000004FFE9DF008000041801841E01A05801\n\tA00008801801800084E00600600600600610602400600000620000082400603402604400450590001610212091602600000600f81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801801801801\n\t8000806004226000006006006006006016002006006006806006006006080000100140404006006006046006006006006000\n\t000000000000FFCF6B000000001900001833A11801A01801A018018000D0402581614602400603688E007002002004046106\n\t046006826006001052852411004014006046006006006004006000000000000000FFA336000000001801A01823805DE38458\n\t01801801800000602600E00602200600E08400710F606000000005126004006014004006682000A700000068060180060060\n\t07000000000000000000FFA0FF000000001801A01A09841C01905A01841C058000046116006000006006006004006106006000041040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060020000000\n\t00000000FF2F21000000001800001801801801800800001801800000640400600601608600648600608402E0040164060064\n\t06006006000080400006000004006006006006006006002000000000000000FF5B6100000000180000180180180180180180\n\t1801800000600400600000600600600600600600200000600600600600600600000600600200200000600600600600600400\n\t4000000000000000FFF449000000001800201801C01801C01A01C01801800000600400600600600600680600600680200400\n\t6006006006806006000001000802000004006006006006007006804000000000000000FFA79B000000001800021C01801A0500841040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E21608620640\n\tE086008200201002000150006006006006006016012000000000000000FF2973000000001800001A01A01881800880401801\n\t800000681600641000650602E016006D44006444006006006046006546000000800204804204006006806006006826200000\n\t000000000000FFFF92000000001800141C01801A0194EB40051801800000400442600E00402600600600607478E404006806\n\t006006106006060886102814064004106006006006006006000000000000000000FF0387000000021800201801C018018088\n\t0000380180000068AE13612880602700603609700000604010610610600680E086008403006007002000007006806006807000441040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (81005C018001\n\t00684600000600700602E0068000140460001061060060063060060010001002100040009060070060068000060020000000\n\t00000000FF3A40000000001800001801801A0100080100180180000070060004010060060060060011000060880060060060\n\t460060070000070020008042A800600600600600002620A000000000000000FF45B3000000001800601C01801801000801C0\n\t1801800100C00C00E11000450680600E00624400644000600E00600780652600000200600200200000680700600700601600\n\t2000000000000000FF2D5F000000001800001801801A05000821C29801800001628C29E1A700E0860062AE08E0840063300000c41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000000\n\t0000FF4415000000021800413C81A09A2484024D2A192D80008B6916800906CD6026486496A00836826B408C6926C1683688\n\tE8B60202200084020C0880104284886A16A00826D0C000000000000000FF21B7000000081800121A05821D00902481A0D801\n\t800020642650601680600602602600648640E0102072060C6206A46A06801110B4090040C00042400C006107006496044000\n\t000000000000FF2EBE000000001800001801801800800201801A018000006004006000006806006006807007804000006006\n\t006006006806000802002800804000804004006006006004004000000000000000FF7C37000000041800541801801883140D00241040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00A01A21A002\n\t00106B01744701408200120400200A042002004000000000000000FF94490000002000000022800000C00000044800000000\n\t08000000618E5810211000180460200005A80000004601001200905000005402800200002204900000004060040000000000\n\t00000000FF8C2900000028000002000000000040218A40208200002080002860060490010308000064000202002000002000\n\t00000228000800A808009084000008000000000061506C8000000000000000FF44000000000318000C1801821824A0400106\n\t1B01800044406E000010024806C86206200242004010426406186066086006010406026002402040C840040862062002040200a41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1A418000C060\n\t46084006016806C8600604642E00610044640604601601600630020404422424E040A0600E00600620602642400000000000\n\t0000FFE026000000200900500D008C0E40904402A0088280010C300341351334200200A01320300300320910308348314310\n\t3032010052D12012901201002C03003003023513002000000000000000FFCBC9000000000200201103348400201241008424\n\t0001100880900C00A1000020488080081C808800140820800A00800840820A950088112C0800805008000880800CA8000000\n\t000000000000FF2B20000000200900108800A019029E0020801C49800002220241400200200600302640208020200208238200641040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF08910008000AA0AA0920AA0AA0AA0880842AA0AA0000AA80002880882A8AA8AA88002883A02A8000000010000020320020\n\t020200200220290200A202200002A8288280000000000000000000FF4A6D000000200800200200000A00C00A008002008000\n\t002C82842802802000000500842812802800802D12C52D0A8829028080308108800028000028828028028228528020000000\n\t00000000FFD2510000000014002512014010002252350010010000000830804A2080000400484C800804800C200008408808\n\t00808C08C809040C480C034820114014004804800800004000000000000000FFCDD40000000098000218018018838419410400e41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000280000090\n\t30808000000020000080000000000040000000000000000000FF93980000002AA0AA0A82AA0AA4AA0820A00AA4AA00002A92\n\tA82A84A80082A82A82A82882A02A82080002A82A82A82802A82A82A89002000080102282A80002A82882A000000000000000\n\t0000FFBF8900000035415412035415435434C3503543540001550820D50930D50550551308D50C20D50C40800C40D10CA8C0\n\t0AB0AA0500540D514A0A00D50C50800D50D30C90800000000000000000FF0DB4000800000000000000600000428012400000\n\t0001000001001001121001001001021001001001001001001001001001001800401089D4140100100100100100100000000000141040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000080400084\n\t4820900804804804800804804C108008008C0800888800800804D048008C4800004800804804800804004000000000000000\n\tFFF0BB000000000800040200800000808808800A008000002802002002232000002002022112002000002002012002002002\n\t00200000804A412010812002002002002112002000000000000000FF28EC0000002AA0AA48C0AA0AA2AA0800800AA0AA0000\n\t2A82A82882884002A82A82A82882302A80000022AA2022AA2722AA2A82A80702C00002003A02A80002A82E82300000000000\n\t00000000FF3A060000000000004020004000000000000000000000000308000200001001000040000010000000000100040000941040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF04\n\tAA00000040040040040040050040040140140000010010015402110A10810850041810050814000000000800002001400000\n\t10014018401000044001001010001001000000000000000000FFD40C0000004A0C00400C00C10C00C00C00C00C0080010432\n\t0300A00312330348300200300308300000254240240215240200300300300315100101300300340201300300200000000000\n\t0000FF120F000000001800001889801805801801001801800000600600630600600600641643630400600000600608E00620\n\t60161060041044C6006020086006006006006006004000000000000000FF9B1000000000000020300020100022504520100000541040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600640640000\n\t8410482000024016006016004042406000000000000000FFC70D000100000000000141800044022020100042000000022000\n\tE1064302C01080000060000001080000000280000002080000800302205500200A0006000000406040400000000000000000\n\tFFD9A30000000A0000000089810002000000000001000002020414E00E00020020000824E500000200000400408400000410\n\t080810888B20910000848806000200006000000000000000000000FF99DE0000000008000018008118808018048048008000\n\t006002204082002006002212002540142000802DB2802912CEA8A200201600200222402008001200200A00A504044000000000d41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (446410006000\n\t28E00600600600600600602024E0260260B64B60C600408600002008C0000040960060060062960C6000000000000000FFA7\n\tD900000000102000180180184A841821081801880002E40210200E0060160060460024461060110072CF02F0070274160060\n\t06524020054020414006006006242506046000000000000000FF1127000100001022001901811808805805061805080002E0\n\t0629010E40604E00603600010404600000602660660658600638631028018800000030C00600600E02000600600000000000\n\t0000FF1FD3000000001004001821801800801801005821800000602640400004C48610E0060040040060800060060061160000341040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF1ACF00\n\t0000001800001801801821005825801800800100600000220000600600680604320A00E0001060A62B600F0562C600400844\n\t2086082008006006006006042004000000000000000000FFB10B0000000AB8002AB8ABAAB8C92CF8C12ABAAA800048644228\n\t80880642AE2AE2AE2E822008E0005066863C600680625600606200A2862000003262262AE2AE288140240000000000000000\n\tFFE613000000001800001C01801C23001C0500180080008168A284444600680680600600491024680008600E00E20600600E\n\t006C12CA600E040821116006006006044044010000000000000000FF6545000000001000001801801800821831001801000000b41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000202226\n\t2070092AE2AE2AE2AE2AA2A8220000000000000004FF388D000000001800001A01A01A03A01800A01A000000006086006046\n\t0060060070060061000D684000600640600610640600500750A946445040006806006006006004000000000000000000FF2C\n\t780000001558003559559559159519109559540000556D56D52150556D56D575565121405460144562160062C628600E0072\n\tC711645644C0045565565565565125544D0000000000000000FF3C7F0000000AB8002AB8AB8AB88908988D8AB8AA000112E0\n\t08ACE28E48EAAEAAE2AE28E22A40600304E956816CB723688600428802220F09000222E2AE2AE2AE2AF20CA880000000000000741040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4E0060060960\n\t0600600600600E0062C032E02E43653634E12E20410011010804410008600600600600600610E000000000000000FF60EA00\n\t0000001800001C01001C4180384500180080008060068420400068068060060220A6007000C4620630600620620600490092\n\t1000906000007004006006002006816000000000000000FFB430000000001800201801A01805A41800A01A00000000600600\n\t600600600600600600620010601001681600624608688600425001211604C800006006006006006804100000000000000000\n\tFFE6700000000AB8000ABCABCABC89C89C88CABCAA00002AE2AE28A2882AC2AE2AEAAE28A00822F0000860A682E88E82E02E00f41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFE3AB000000\n\t001800001801801805801800001801800000000600400400200600600600401600610040620610600602604600400400000A\n\t002000006006006006004046100000000000000000FF8E080000000C98000AB8AB8AB8898AB8838AB80000002AE00628E0AE\n\t1042AE2AE2AE28E2062AE00000660608600604600600C2122302203840002262AE2AE2AE28E23A226000000000000000FF49\n\t5300000000180000180100182580184180191400000064060222004260060060060421260060040060860060060064061440\n\t52004000014444016004006006042106006000000000000000FF8C9800000004380000180180180180180900182080000061000c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (421022242540\n\t102AE2AE2AE2AE2AC002220000000000000000FF17E100000000180000180180182180180200192180000004260002000260\n\t060060060000160064040C60A60460A6286086000026100002002004086006004006000084000000000000000000FF18B700\n\t00000AB8000AB8AB8AB8898AB88C0AB8AB80002A82CE2AC4AC2AE2AE2AE2AE2CC2A62AE41004E00E24E20E00E20E2AC21622\n\t83202822802AE2AE2AE2AE2CC28C228000000000000000FF3053001000113800155955955915955950155815800055011655\n\t01302125565565565504C65560C42160164964160164362CC5044404C824A54444E556554556550446550000000000000000008c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400400680501\n\t700609402000E40400620600600602E00E006400416414004004106007006116105000000000000000000000FFB3BC000000\n\t001C00001C01801A41800004001821800000210E00420400600400600600410880628832E02E43653634E12E0060C8456096\n\t104110006006006806004480110000000000000000FFAE50000000201800001801A01805800000001C058000000026044045\n\t00200480600402400000600400608700600600640600600208200604C404006006006006004052000000000000000000FFB2\n\tA80000000AB8000AB8AB8AB8C98AA0E80AB88980002A820628C08C2AA2AC2AE2AE28C2202AE0001063460861465061062AE3004c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8E8000000098\n\t00005C80001809800000001801800040010610C30440600401680600400040620000640600608610621600248008200E0000\n\t0044E000007006105002000000000000000000FFBF91800000009840005C0184180980180000180180000020061440440030\n\t04106006004002006000046006106506006006006002002006000000446006007006004002000000000000000000FFE70880\n\t0002401A20011A01C2FB81801810401C01804100100603453540300480600640C002D8600002600708627610640600614230\n\tA204000000016006006806004002000000000000000000FF5C59000002401800401901C11801800000601C018000C028864000cc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000200050\n\t41100060A6004024400000000000000000FF927A000000001800001801800001801800041801820020629620408420240605\n\t800601400640629000622622E0063060860060042AC11057A1000840060060A6004184010010000000000000FF1FD7000000\n\t001800011821800023801810023801804000C00640401402220610000650404601600000608600603E056026026044004082\n\t082000104086006116004004000000000000000000FF9E1D000080401800201880291901800004501A01882008202E094004\n\t017084A2600600C00020600800601600630614640610250000244C20008820640890600600402A210008000000000000FFE4002c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (110100050000\n\t004020000000000080000000400000000008000108080080090046006000004120000000000000000000FF7E3F8000000000\n\t0000000185200002800014C00000003480000060064400000800500060000004803280284305301483280901200082400002\n\t00000006006000006010000000000000000000FFE929000000001800001900110843800004081001800000E0064140040040\n\t8620200600400400650000610E00628622622608208600044200200800420008600600400C000000000000000000FF835600\n\t010000180000184000090180000000580192404865261041042520060020060040040060000064262560560061060424064C00ac1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000AA8000A\n\tA8AA8808AACA2800108AAA80000822AA2AA2AA02B3222AA0222AA2322AA08004A00A24A20A22A20A2AA22222A12A23240022\n\t22AB2AA2AA2AA22A000000000000000000FF8371080000000000000001000001040000200001000108880400000000000100\n\t08000000840002000C00A00400A0080080480110000000080480004020000800000090000000000000000000FF5792000000\n\t0AA8000AB8A20848AA8808000408AA80004122AA2AA2AA00222A2022922AA2882AA4001023420821421021022222023A6002\n\t22A10032028A2AA2AA2AA204000000000000000000FF24610000000000000000098000000040000000000000004000004004006c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100080000040\n\t000000000000000000000000000000FF59F58800004AA8006AA8A28888AA8908000AA8AA8001A23AAA0AA0AA0022AA2222AA\n\t0AA2232AA00000260208200200200208222A2003222220002AA28A2AA2AA0AA222000000000000000000FF789D0000000010\n\t002010014480012100004022010001020804000000284809000C800001050040004002001000000000400001080044001000\n\t00014001001004000104000000000000000000FFB453000000155800355955335D55905800155D55800044655655655632C5\n\t564D6556556454D5610021601649641645643605644652C44E456000556516557556556444000000000000000000FF8A140000ec1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (288803000000\n\t00000000080400001A00800200001800000000200000000000000000001800000000000000000000FFA76800800000000000\n\t000020000000020000000000000000000000000000808200080000000000000000000000008A882800000000000000000000\n\t0000000000000000000000000000000000FF79D000000000000000000800020000800000000000000880002002002A000011\n\t0000400010000480328128430530148328200080120010010200000000001000400108000000000000000000FF2C9C000000\n\t4000000000000240000240000002000000000000000000010000000000000081000000000000000000400000030000010080001c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001801\n\t001001801801A01803800000E00600600600610E08608E006026000000086206006086226056000807006004204000006006\n\t006000000006000000000000000000FF0AE10100000000000090011030014814210011010000040004020000100444040404\n\t004004000000000000000404111400100440001005004000004000000000000004000000000000000000FF08600000000000\n\t0000000080080020080080080000008020028020020020000020000020220000000020028020822020060802428030010000\n\t00002002002000000002000000000000000000FFF37300000000000000000028000000000000008200000280008000001002009c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000008060060\n\t00000000000000000000000000FFBE0E00000000000000180000180080180100080080000020020020020020060020060020\n\t02000000002002002002002002001002002006006000004002002000000002000000000000000000FF78A500000000000000\n\t0001004001100000400001000000000400000000100080000000000000000000010000000100000400000000180180000000\n\t0000000000000000000000000000000000FFF1B4000000000000010800800C00800840800800800080200204300200300201\n\tA002002002000000002082803003002002000003002002062000003002002000000002000000000000000000FFC27B000000005c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200E00600640\n\t04208462060860A6507106020001014003002108004000006000000006000000000000000000FFF14A000000000000001800\n\t0038A9801841845801800040640E00600040C00614200600600608010010600640E0160160060000D000400400400000C080\n\t00E000000406000000000000000000FF1FF10000000000000000018000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000006006000000000000000000000000000FF59CE0000000000\n\t000000018004000000000000000000004000000800000001000000000000000000000000005000000000000004800004004000dc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018400049\n\t51801821C05C018000407216002006046026105016116016100240005A862021479060260201288160021022900060000100\n\t00010406000000000000000000FFEA79000000000000001901800001949851881C8180000240A6006C062060060230060060\n\t06010090126006001106246086000004804000850000044006080000000086020000000000000000FF3DF300000000000000\n\t1801800801A11A01821901800004600680600600E00620200611681620000008690608A00E86E04600000400500016040000\n\tC886100000010106040000000000000000FFDED3000000000000001840000801801801C818018000007146007006026046C0003c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E84600600000\n\t0006000000000000000000FF2044000000000000001C019A000381180180180180000C500600200704600600600740600600\n\t000010400400100700401E0000050A7000000060006806806000001006000000000000000000FFFE71000000000000041801\n\t804821801ED18018018000286006086204086006206006006006008028004804000106044006000084106480450200006007\n\t006000000006000000000000000000FFED380000000000000D1800012041811B018118018000245026906006144006B15006\n\t406806000020804084003806006806000100007B04404400016040000000001006000000000000000000FF6459000000000000bc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006007800000\n\t0040241064060C6006000001906420C20100106006006000000006000000000000000000FFAB3E0000000000002018019424\n\t41801A01011901800008C8270041064040060061860062864000041044144062060061061800200968000000C50060860060\n\t00008006000000000000000000FF1245000000000000001801800801C0182304180580000060D600400400E0060068160065\n\t0601000000410401611601643601004000610410C20000710E006000010106000000000000000000FFAC2C00000000060010\n\t9B018508058A1801009801800000604780400680780609600680600600000400410600600600600600000004600380200404007c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (988994A0C380\n\t1804851905800008510600610645600E08E006006A06410006906C3400611613600600100600516080002700600622600000\n\t0106000000000000000000FF4E1C000000000140401C41C40011C49800801801800000408600600600600600600600600600\n\t001000610400611600600610040654400A832290806026006000000016000000000000000000FFF343000000000000001C01\n\tA00001A01940805841800020401600620600600700600E0060060000040060C62960060462CE00900600C4044B4224086016\n\t006000000006000000000000000000FF656F000000000000001801804001801901005841800050C00600440604600680600600fc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000000006\n\t000000000000000000FF77B0000000000080001825800A058111018018018000806006004806006006006006007006006004\n\t006006004916006806100406100555010044046006446000000016000000000000000000FFC1CE0000000000400138118448\n\t098216018018018000886086004084006016806006006004006011006146004807046006000806C5000002029000E0460060\n\t00000006000000000000000000FFBFF4000000000000043D03990101801AE080180180000040060070840040061160060064\n\t0600000000600400600700700600000600D28000000002E01E006000000006000000000000000000FF3C7B0000000000000200021040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (048360A40565\n\t0E08641608E086030824917000006004004006006000000006000000000000000000FF3BBF00000000000000180180080180\n\t1001001803800000600640408600600600640600600600600048600640400600640600000000600200400000400600600000\n\t0006000000000000000000FFFC4E000000000000001801800801801000801801800000600600400400600600600600600600\n\t6004006006004006006006000006000000000004006006006000000006000000000000000000FFC06B000000000000001C01\n\t800801801001801801800000600680400600600700600600600600600200680600400600600600100300100000000300600600821040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800801C01001\n\t801C01802020608EB2448600E00E7862261AE20600E0A020E00E28420E88E28602802288E040004000006006006000000406\n\t000000000010000000FFB0C5000000000000001A01801801801901001C018000006006006006006006026006006006806004\n\t006006007006006006000084006906020405804006006040000006000000000000000000FFEEF4000000000000003C01A008\n\t01801C01001803800000600600600600602606600E0060060060000860060040070060060000006060010020000040060060\n\t00000006000000000000000000FF79A1000000000000403881803881A8B02900188180204260AE04C20621602EC8602E0B6400421040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000060000\n\t00000000000000FF2AFE00000000000000190000590191585180190180000470460164074060062A60060060060460010465\n\t06006007006006000087006004024000006000000000000006000000000000000000FF3AEF00000000060000180000180180\n\t1101801801800180600680400600600700600600600400600000600600600600780600100200600000400000600000000000\n\t0006000000000000000000FFEC92000000000000001C01800801801A01801801800000600608640600700680600608600600\n\t60000060060048068060060000068060C0804400006006006020000406000000000010000000FF9C0500000000000040180100c21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (604000640610\n\t6086006206000126000348804000216000006000200006000000000000000000FF7E5A0000000000A0409800209C09A81A01\n\t923A89800002E28EA06896116296206810C86C0EA06800C46816807086CD6A86000930A40022006800206C00D06010200826\n\t000000000000000000FF5E22000000000000003B45C458C585590580180380002860060B624602680690E52000610610E020\n\t09634648600E00604E001C0601030E53404000600600000000010E000000000000000000FFBF4E0000000000000018018008\n\t01801001E018018000006806004004806006006000006006006002806006004006006006000002001801806002006006000000221040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00800800000A\n\t0980000A601220200A00A88E80E28228220200200060202220200A4020020002020030040000010004020020080000020000\n\t00000000000000FFC5DE000000000000100401916202008400002040000000018008C1A040084008041800000C0005200000\n\t804000000204E0000080120020080460000206406000000008000000000000000000FF2F310000000001000404A58000C006\n\t04800000000000008000440000060800C400000000800000000281180C0000000108000018458C1117000084010628610000\n\t0020000000000000000000FFB9E500000000002000DA00001111801841AA18818000806A0E1062449060062160000060042000a21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080400000000\n\t0000000000FF7EDA000000000000301A230C1803A01941A01A4180000868165060C624600640620600600600608040611610\n\t6006556126000006546124096200026106006100000006000000000000000000FF57CF000000000080432800C0AF28CA0800\n\tC00800800100310302320B10284204B81300300300324100320344350300320200150B00AA0884104080B203402000001002\n\t000000000000000000FF4C0200000000008021104224802D5821032002020000B00804820C10884200801020800800088800\n\t880A00800D00BD8800000C00A0108120C801004800800000000880000000000000000000FF5860000000000000002801020800621040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001001020000\n\t001000000800800C48341002801041040000001000000000000000000000FF0E900008000000000AA2A20040AA0AA0880AA0\n\tAA0000800AA82200000902A82902A82A82A80000002200104002A82082A80002A02302184080002202882888000002A80000\n\t00000000000000FF0347000000000000200010A08A00200A42A00A000000402002882912C00000808802802802802A008128\n\t02B0280292280200000200A000822800112842842000800802000000000000000000FFF80F00000000000000100132200100\n\t020100100100008CC004810C2082C004844000804800004900884D30849004801000000808900144284B000048008000000000e21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000400040000\n\t000900000902000008000800000000000004000000A010100112000000009000000001048008000000000000000000000000\n\t0000000000FF46D20000000000000AA0AA0C80AA0AA0A80AA0AA00002A82A84003202A8AA82202A82A82A80002002A82A830\n\t8AA82A82A80012512A90800105012A82882880000002A8000000000000000000FF75E20000000000003541542C8354354330\n\t3541540000C40D50C40950CC0550C41550D50D50800900D50C00830550408D500014415413208A0801448D30D50800800D50\n\t000000000000000000FF935B000800000400400000402000000000400400000100100111100100080100100000100100100300121040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFCB130000000004002000112102002002000000010000004805008848800004800804004804804802804800808004\n\t8008000000A4004144280D02004800800004004804000000000000000000FFE3A6000000000000000A00884800800844A00A\n\t0000008000021423020020000820000020020024000020021228020060020000000000008220000020220020020020020000\n\t00000000000000FFB1160000000000000AA4A20204AA4AA48C0AA0AA00002A82A82400102A8AA83382A82A82A80001802A82\n\tAA2002A92AA2AA000B08AA8A09008000AA82882A80000002A8000000000000000000FFC4DE0008000000000004000000000000921040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (12012302A008\n\t420005062B000E0220000002521020C0002002000000000000000000FF74EA40080000040040041540044040040040044000\n\t0101500140040100100521100500100100100100001800000000800000000014400000100022440000000400100000000000\n\t0000000000FF77AA400000000400408D20C20D00C00C00C00C00800100328308A00300300320300300300310300304200200\n\t3042542002101023001003003003002002003003003002000000000000000000FFE95E000000000000005801001801801801\n\t801801800000604600601600601600600600620600600000E2060063060140060001144040B424600044600600610600600600521040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801025800000\n\t60060C400048010600614620600600600022600610601600E0160000020A2100000100006040006004006006000000000000\n\t000000FFA6F70008000000000001459000200A204180002000000000000800203001002500080000000000404400200A0010\n\t0100002A00003400B0240228100006006000000000000000000000000000FFED5F0000000000000101358201000000018000\n\t4000000103000882000000000040000004001000000282000049401200000808CC800940C040008000060068008000000000\n\t00000000000000FFACD5000000000000006810000820800800800801810000202624200A04200A00A002502002002000002800d21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFF4550000000000000010019208010A900180100180000060060842160060060021060060060062000060464000065062\n\t2E000342092008104300006046020004006006000000000000000000FFBB5B00000000000000180188180580580180100180\n\t8028600600602602600644600600600600600000702E00A0070070062C028401000014444000600E08004400604600000000\n\t0000000000FF030100080000000000594001980380184180100380002860060060060020060160B610618600604001E00604\n\t670600604E018004404650498090106000006004006026000000000000000000FF0ECE0000000000000018120010218A180100321040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (82AE31700600\n\t022022020A2C41002A628E28E0060062AE000000000000000000FF36C2000000000000001001901801001091801801800000\n\t70060060070070060069060060060065000060060000060262D600024800000A0AC400006006006806006006000000000000\n\t000000FFCDA22000000000002AB8B2000AABA03AC98AB2AB8000AAEAAE60E004AAEAAE2AA3262AE0162AE5802AE2164C22AE\n\t00E086000910A20066818000A262882880060062AE000000000000000000FF2437000000000400001A080138018018238010\n\t0180000060060460A600600600600E0064CE00680000608E052006047006000010004486240800116000000006006006000000b21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AB80002AE2AE\n\t2AE2AC2AE2AE2AAA262AE2AE2AF0042AE9062AE2AE00702E0002232221232810052AE28E28E0060062AE0000000000000000\n\t00FFF1F4000800000000401401855C01455401801C01800100600600614E00600600700E0061060068000065061060068465\n\t2E001003112906800C0080E046026006006006000000000000000000FFBE9E400000000000555D55815D55D55C45955D5580\n\t015565565565565565565574565565565560045564565565565160060011044D422640010455655653700600655600000000\n\t0000000000FF99870000000000000AB0A3B008AB08108D8AB8AB80002AF2AF0B64062AF2AF2AA2262AE2462AE0002AE8460000721040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t1DD700000000000012900180C80B00B001801001800000600615610600600600200600600600600000624E0CE0062064D600\n\t030020C08010E000100046046086006006000000000000000000FFCE34000000000000001211812801001021001001800000\n\t600600400600600600210600600600690400604600600620EA06000808008408036B06000006006006006006000000000000\n\t000000FF14BC000000000000201001B20A01201295801A018000806806806006006806802016006006006200006496006006\n\t946086000104900882800000806046026006006006000000000000000000FF913D0000000004000AB8A38408AB8AB8018AB800f21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (52645600048A\n\t4324D0552004556556536450550556000000000000000000FF4FE68000000000018010018808018018018018018000006000\n\t00608408400601600200000600600200414602600604E00600011200A04210200000E0260060000000060000000000000000\n\t00FFFDE00000000000000110A38008210010AB8818AB80002AE2AE0042644462AE2AA2AE2AE2AE2AE0022AE0064062AE02E0\n\t0600002008022022600222028E28E3262AE2AE000000000000000000FF6CC90000000000000050098C090114100105580180\n\t0000600640601654E00600200600600600600400610620600610600600001004001000600400800600601600600600000000000a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002AE2A82AE4\n\t062062AE1062AA2A82AE2AE0002AC0063062AE02610600002040021020200022428E2EE2A82A82AE000000000000000000FF\n\tD854000800000001841001884821801801851801800000600000E20600E00600600600000600600400600608600600E08600\n\t0046106006002006006006006000000006000000000000000000FFD42E0000000000018AB0AB8308AB8AB8AB8AB8AB80002A\n\tE2A82AE0362362AE2462AE2A82AE2AE0002AC20E20E2AE28622E0002460A228422A00032628E28E2A82A82AE000000000000\n\t000000FF784C00000000000190515584891594B95590395580005565505461161065565565525505565560045544B6056556008a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFC072\n\t000000000001A41805801C01A01801C01C018000086003006007007006016807000886006005046406006006016006000000\n\t2000100A6004404106006000000006000000000000000000FF146A000800000001801809932A01801801A01A018000006002\n\t00600400400628600700000600600000424E08E0062064D600030005095204E0000140460060000010060000000000000000\n\t00FFFD9B00000000000180100180180180180180180180010070000065360B680603600600000600600400410682680610E8\n\t06000810284002902004084006006000000006000000000000000000FFD4C60000000000018AB0A38048AB8AB8AB8AB8AB80004a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (161480001002\n\t80002000046120000000000006000000000000000000FF9B52800000008081881140001B13801800001841800000700080E0\n\t06806007016006000006006000844006002286046006080008420002022000006300000000000006000000000000000000FF\n\t9268800000010001F019518008898018018018418001017502096004044007106006101807C06000004006001D0604600610\n\t0000144002002000006006006400001806000000000000000000FFC6BF800800000101C21003800A05C01861A01A01800108\n\tF08040600602680608700708080620600000420700100600E80600101008080900200000640600620000100600000000000000ca1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600600\n\t6006002006000006016000046426506106106016000006082004000000006000006000000006000000000000000000FFF9F1\n\t0000000000018018118418858018018018018000006016046006106046000016000006006000026036002016206006000002\n\t20A45000C002006006000000000006000000000000000000FFE11F0000000000018090118208038818298018018000006404\n\t78600608600600008600010600E00200600E20008608620600000200202A18420A4060060000000000060000000000000000\n\t00FF5E39800000100001801810001821801800401C018000C0600A0260060270260260170000060060000064060C20160060002a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFBB540000\n\t0000000000800980000000001180000000000001340000002000000480040000000000004001002D40001080000001001004\n\t50110100010006006000000000000000000000000000FF51278000000000000A00018A000000000180000000000002000002\n\tD01400000800000000000003001482480000002404B0000008010000000400080046046000000000000000000000000000FF\n\t859000000000000180180000100180182000180180002060064860040240060421060000060060000060060260062062060A\n\t8006216106110410026140006000000006000000000000000000FF3D2800000008000181180000192190181000180180000000aa1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C2C54443440\n\t4400556556556000001D56000000000000000000FF8A270000000000AA8308AA8008AA8AA8A28AA8AA8000AAAB0A2AA0CA0A\n\t2AAA2A22AA0002AA2AA50002220B1522AA2A222A0002B22A2032A224802222CA2AA0000002AA000000000000000000FF95E2\n\t1000000000010000000480000010010000010000004000000000000005080200801001000001000000110800008080000104\n\t01010012C080004000000001000000000000000000000000FF00BF0000000000AA8068A300A8AB8AA8B28AA8AA80002AA002\n\t2AE00240A2AA2022AA0002AA2AA0001120020022AA00010200022223648632200032028A28A0000002AA0000000000000000006a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t1004000010000001000001010B00001000000001104B0100100000000040040000000000000000000000000000FFB9398100\n\t000000AA8AA8A2904CAA0AA8A28AACAA00002AA2232AA2AA2AA2A82220120002AA2AA0002AA0032422AA00E0020002000002\n\t002200002AA28A28A0000002AA000000000000000000FF2D4480080000000110000115400100100100140100008048400042\n\t00008804810801001005004003400140A0100400800000100400410481400200C000000001001004000000000000000000FF\n\tFC2D800000000555955955001955D55955555B5580015575565565565575564578C60015575565005564B64075565444560000ea1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0D4F00000000\n\t00000806000000020000240020100100020880000001AA80200A80208000002802A800000000000014002804100000000043\n\t02A8000000000000000884000000000000000000FFA1C5008000008000020000400000002000000000000000000000000000\n\t0000000000000000000000000000000601008000000000000000080000008000000000000018000000000000000000FF9130\n\t08000000020000000809420040000820020000000008810000000008000090D00000008004000002480008002404B0000040\n\t000048008500000000000000000800000000000000000000FF1A2A0080000000000000000400000000000000000000800010001a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (182002002000\n\t002802002000002010082000000000000000FFD0BD00000180980182300100320380B88182B88808A180608E00602E08E28E\n\t88E0060042000860A002008600408700E2080268050070078260A000E006006000004080004000000000000000FF67970100\n\t02000001101001001000200445001000000005000100400444404404404400400040441000000541044014484000D0044100\n\t00510410004000110000004010004000000000000000FF002E000000800800804800804800810C8085088010410130128020\n\t50000512000000802400002000040082C16143002400002000C12802802000002802112000003000002000000000000000FF009a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000010\n\t00000000000000000000004001000000000000000000000000000006006000000000000000000000000000FF32A800000080\n\t0801000801200800800800201000000000200200200600600700200300000000200000000200240200400001080400200200\n\t2800004002002000002000100000000000000000FFD735000004000000001400001000000001200000000100000000400000\n\t0000004004804000000000000000405000001000000000000001000800000000000000004000004000000000000000FF2049\n\t000000800800000C00800800A008008008000000002002002002002002003002002000002000000002203002003800002000005a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001805801\n\t0088000509019018005018400020086416416946517207006006004000006000120116000857016001006502810102006000\n\t006880006000007000006000000000000001FFA2BA00000180180100181000180382182A0058000000006086006406006106\n\t106106204000016000000006208006486080006000006006006100006000006000006000006000000000000000FFBF290000\n\t0180000000000180000000000180000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000006006000000000000000000000000000FF5FAF0000018010000000018002000000018000000000000004000000da1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010060000068\n\t00000000206040004000000000000000FF11EE000001805A01800808020905841954101840000000641300F3460060872060\n\t360020000060001000164040D6043880006502006104006000006900000010006000204000000000000000FFA9B1000001E0\n\t1801008001800005281011801800002000440520640628EA0600600600500010600012008610011200E00080682008A40A1A\n\t6080006006000000006801006000000000000000FF67E300000180180100080180E801C01B0180380000000860E400601E00\n\t60064860D620400000E0000000668081022C680000704010601695E000006006000010006000406000000000000000FFD322003a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600640680600\n\t2100006004000006100004006000404006404006004004004006006000002820000000000000000000FF5411000001C63809\n\t8C00018880012030018018000001004400606407607246007006002000816008000006604077007000006200002401106000\n\t006006006000007000004000000000000000FFB4C4000001803809880511808003C039018018000000004002026006026206\n\t02600600200910600A100006004107006000006400006004007802006806006000406000004000000000000000FF57E80000\n\t01C018818409080048010013000018000000006002026006047046226006002890016000000006004806002000407000A02000ba1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018010000\n\t01908001201001801000000000400010600640600600601704000000E0008080060144042460400040040000021040000040\n\t0E006000002000000000000000000000FF130800C001801C014508098888510F149981103810000460200064160068060864\n\t660001403E600010019680401C086100004064244006004001004006006000863000000000000000000000FF322800000180\n\t1A01000011A00001901923C0104400002040C004610600E00610600640201040600400020720400510621000C80C40020301\n\t4004004006006000002001000000000000000000FF6B8D000001801881000C01B04801801811801000000080600000600680007a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600080600600\n\t6000000800002000000000000000FF6F14004001001801052001E0804101100D811004100000410210610601700600640640\n\t7140006004110017C04806004020004800046806016004006816006001802000002000000000000000FFF54A000011A05805\n\t010003800401031005801000000002400100600600601600E487004000006004000016104016004000114052032C02806004\n\t006006006000002800002000000000000001FF1D2D000001001801000401A00209401441801000000042400284620E206006\n\t00601604500801600100020600CC072442D0015008006406106001006006006000002000002000000000000000FFA7A2008000fa1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (806007000006\n\t006004006007006804002006005004002806000004006006006000806006000000000000000000FF536F0000080010052008\n\t0180080100080380180000000068060060060060060060060000060060040060161060140020060060060164870020040068\n\t06000000004806000000000000000000FFFA48000001E05001012E0D808881050811801800000004680600600400600E80E4\n\t06000126006004006006006007002026116016086006800005006006006000006006000000000000000000FF25B8000001A0\n\t100100020980608100120180100000000040000060060060060061070060A00060000000060048078040000048400C68868000061040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100100380180\n\t18038008A9823820000002600655612C10600604600E48002600600104600F48688500600708400C00400500400100480600\n\t0001006006000000000000000000FF9B75000001801001000809880801000801801800000000600600600600600600600600\n\t00060860041060060060460860064040040000040A4004004006006000006006000000000000000000FF181C000000001001\n\t0008018008010000018018000000006006006006006006006006000006006000006006006004002006004004006006002000\n\t006006000000004006000000000000000000FF9E5E000001801401000801C00801000401801800000000600600600600600600861040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (806006020000\n\t006006000000010000000000FF1E6F000001801801800801800A0100081180180000000260062AE0A6086006026446280026\n\t0061000A600E206086C828063C480C402006044140007006006001006016040000010000000000FF289D000200001601001C\n\t0190580181460191380005400062560065560164560061160005560164540061068064440065560069061041441144140040\n\t06040000006086000000000000000000FF3737000001819001010801800801180001C0180000000060060060060060060060\n\t0E001006086006006006006024006006007006000004086006004006006000006006000000000000000000FF00CD0004000200461040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000060060\n\t00006006006802002006006002002006806000006006000001806806000000000000000000FF43AB000000041801815C1010\n\t1805800550445C4000000060060060170060060060060000060060000060061068070010060060062060068CE00000600000\n\t600000700E020000000000000000FF5F7E000201801C01801800105A01800C00003800008000781600600C00782600621600\n\t02860060800060060064060020060A60860021260244A0006000000000006086000000000000000000FFFE99000400001801\n\t800A0180080100C809B11C00022000622700652700E217006126000856016448806106006046A0254E00400408600680600800c61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (181000001103\n\t845002181884000040602680602480E02681610E00800600600000611E00E3000020064C4004086006204000806000000020\n\t406206000000000000000000FFF242040220333221355A00201AA1AA04020298800000906046026C1648EA2644704E048846\n\t94680080EAD6C8E230800A168C4A24930C040068A0046880806040B06A86000000000000000000FF04B30000018010090019\n\t4589380B800881905820000041628E90614602608E8164864000862060800060060271005300A70068860060A65540080060\n\t06206000016046540000000000000000FF36B4000000001401000A01800801000801A018000000006006006006006006006000261040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008000008880\n\t04810000000000000000FF31AD000020921000002A00000800801840429800000000680A00600308200E0064060400A20820\n\t00002682102840164002032402072002806000044002002000202002020000000000000000FFA8D002000180A01800020184\n\tA00013000580002000002803410010080011012292304200002200100000204900904805C080138040800004018000058600\n\t60000060C0000000000000000000FFCA480000018040000280A599007C000181A02000000110088100008000100010000020\n\t00000001400000000008012182000000300003A0818448420006606000116020780000000000000000FFA96C00000184110100a61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0004804C4000\n\t4800800905004000000050800880914800004800800001010004810000000000000000FF8DE6000001933801841823011841\n\t84114188380400000060068060068060061160064200060060400061162060262CE006426A0E04610644C010A26306006000\n\t08E002288000000000000000FFECE3000400C00488510800D40C8AC92C04800800000028214A203102002103003292001003\n\t00311120320311231200354B80B103413412003321003003402001403042000000000000000000FF48130002002902212500\n\t4320028028020120400000008088144A0301224280000080800000800880408800A20C28800038000000800C10CA0830800800661040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004224004004\n\t0040020000000010090010000010000000011010010010010010010010110000018000011011080014010010010000010010\n\t01000000000000000001FF85CC0008AA0880880020A20400000000A20A80000000800010AA82A8AA82A82A82A82000002A80\n\t000002A82A82202380002A0800080220220220A20288288000000000220000000000000000FF6A74000200A22C00AC0810A0\n\t0A80A20C10C048000000410820002802000800801000130802002800802802802812902802012482A2A81280280011282282\n\t2801542800900000000000000001FFED1D0002002012452102012CA2542934012010000000924B140048000048048048048000e61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80002B00002A\n\t0000000000000000FF46310008000AA002112400002000008010002000000000044100000000100100000002000000022200\n\t00000010810010000090C0100110000022080000020000120000000000000000000000FFB4360000AA0AA0AA0A80AA0800AA\n\t0AA0AA0AA00000012A82A02A82A92A82A92A92A82280002A80000002A84C02A02880002A8228208240AA80082A82A8288000\n\t2A00002A8000000000000000FFC1320003542003502401542902D232234435040000012D0900550D51550550550D50510800\n\t550800800D50D50450540000D40210A30C40D50A00C48D30D10800C10800D50000000000000000FFBC93000C00400400404200161040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006106\n\t31601622401400400400600600400000600600600600C002006000000000000000FFBC3C0002002012012400112042002002\n\t012010010000004890804800004804004004808804800C00800800930905044800804084A28A100048008048408400050048\n\t04814000000000000000FF8C7F00000080000008C8008D080080081080080000008000020020028000000000001000020000\n\t0800200200204A112006002810082142002010002002002002012002002000000000000000FF66160000AA0AA0AA0006A201\n\t00AA0AA0A20AA00000002A82202A82A82A82A8AA8AA82200002A84100002AA2122002410022A9320040000AA82002A82882C00961040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (880080480100\n\t180480800060122160020060860220025400022800100028028020126A480001241411211200600044000200200200240004\n\t4000000000000000FFC1C3400988401401440504480400400400400401000100100100100100100100500506100110100100\n\t1000000200018000000000000000001000444000001001005004000000000000000000FF7ED8400000C00C00C00C00C00C22\n\tC00C02C00C00800100300308B003003003003003001003401001003402003203102103003080002003043001002002003003\n\t003001002000000000000000FF574C000009801001903851089801801801801801808000600640600600608604600600004600561040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002006004000\n\t000000000000FFBB8F000009810905801004021001801829021801800000600E006004006006406006000026400400006006\n\t08640604E006004000010146016410022004014086002406046000000000000000FF772E0008099080000800218240200000\n\t3185000000000000000200000402402000500005400004000060000904001500200000000004200004300000060061000060\n\t40000000000000000000FF21CA00000180000008011380002400000380000000000000041080000000000000000000200000\n\t00006500510810800110800900004000820000C40006006000016000800000000000000000FFC80D0000008009048229310000d61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00006046A562\n\t8620222601214003020E014800016044022007003006000000000000000000FF20B900000002282593080193180C12500980\n\t1801800000600600600E0060060060060000060000000064960860260A809610000A2041464A604008600600000600600600\n\t6000000000000000FFC28100000188280190380180D840803800801803808000620604E0060064860460062A00060000B020\n\t700700611628104601041200420E10604020E002002006006026004000000000000000FFD275000800002819803952009801\n\t81980001180180800062060060060460C60260560005062000A02060060160860060060040001600040EA00000A00000E00600361040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00B0A3CAB801\n\t80002AE2AEAAE2462AE2AE2AEAAE0002AE2A90022AE32E4962A6A8D04628AAC010404E22D00232628E28E0062AE2AE806000\n\t000000000000FF198C400000401C01F01801E018000012088018018000006006006006806006806006800006000000006086\n\t0C600600600600213022400600C000006002004006006006004000000000000000FFAB4F0001AB88D88D9508A2005B809418\n\tB20AB80180002AE2AEAAE0242AE2AE2AEAAE0002AE2A80202AE00604600E042406262A10480006004000A262882880062AA2\n\tAE806000000000000000FF2C90200000201A01805A10003840A11801001C018000007006006486006006006006000006000800b61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (068060000000\n\t00000000FF09BD00002A0AA8AB8008A38418AB905AA28ABC0180002AF2AE2AEAACAAE2AEAAE2AE8002AE2A90002AE006C062\n\t2E2262062AA00C2002AC2238002AC28A28C0072AF2AE004000000000000000FF70C0000801800821801C0184180340140180\n\t1801800080600600711700680700600700000600004000700680600E00611600200604848510204101404604600600600600\n\t6000000000000000FF8EE5000154154955853D5590BD55C31D449558018000556556D56557556557556D5700055655000C55\n\t625681654E556336552C06088554542015554532554006556556804000000000000000FF644000002BCA9C898048B388982800761040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400641600602\n\t610600A000106206012084006042004006006006454000000000000000FF3A4900000182C801820801809801001001801801\n\t800000600600600E0060060060060000060004000063460A60062960360820300160D6086240096006006006006006086000\n\t000000000000FF50F1000000200A018B0A11921801213000A018018001006006006006007006006006000006000800004A46\n\t34608691680E002000026006012010006022004006006006004000000000000000FF528A00010180080180280180B8011410\n\t118018018000006006806006006006006806000006000008006096016006006146002B24108004906000804006046006006000f61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (541559540000\n\t5565565540965565545565560045560060845564864B65563563564D24445560165464C444E5505105505565561540000000\n\t00000000FFC89980010184180100100180180400000100180000000060060040040060040060060040060061000061261460\n\t060064060420800C6006006100006044004000006006004000000000000000FF91D50000AB8000AB88A8A38138190030A38A\n\tB8AB80002AE2AE2AE0A42AE2AE2AE2AE0002AE0000E02AE04E0062AE00620622238022600622600022628E2EE2AE2AE2AE00\n\t6000000000000000FF8E3C0000001008018008098C1945131008801801800000600600640600600600600600000600000400000e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF793300002B88F8AB1610A38AB8880AB0A30AB8AA00002AE2AE2AC2AE2AE2AC2AE2AE0062AE0060802AE01E0062AC26\n\t42063162B42002AC16E00024628C28C2A828E2AE400000000000000000FFBD770008800C18010AB0018C1900121000001800\n\t000000600600442600600400600600400600640000600E0060060040060020100062C6014000086000000000006006204000\n\t000000000000FF622200002B8898AB00D0AB8AB8B00AB0AB0AB8AA00002AE2AE2AC2AE2AE2AC2AE2AE0042AE0064082AE206\n\t20E2AE28C0AE20222420E2AE21420828E28C2AC2A82AE2AE0AC000000000000000FFE72E0000540159550011558038440131008e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006004616506\n\t14420400400001000004A004004000006006006000000000000000FFC7F40000440018051018458018008030010018000001\n\t0060020068078070070070060870A78060040060060061040C60060064042000800840040160040040000170060000000000\n\t00000000FF8F8400080180180108580980184000101100180000000060060040060068060060060060060064000063460A60\n\t04096036106000050000306210016024004000026006080000000000000000FF3BF000010044180101100180180480100100\n\t1800000000680300600400600500700600600600601000680741600400410605600808000400608014600404400000600645004e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180008008868\n\t0200E0268C600602E80600680700600000210608640450620600610403001021442850201400C00000000602200000000000\n\t0000FF1C10800045801801901010020808801001001800000002600B00600408680480E00600600610E00000208600632410\n\t6106006000000008014000422004004000040804002000000000000000FF3D58800000001801811809840852001001601800\n\t000008700F00C006006006006006006006006001806056016444006006004000004010000000402004004000046006006000\n\t000000000000FF7A1F800801C01801805003800820003001001800000004700698480710680501700600600711600004692F00ce1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF43A300000000180100384402180080108B001800000010600200620E10600600640600410E00600000200608602C002006\n\t006016110008404400144104004000000006006000000000000000FF71C20000018018850438918308008110031018000000\n\t00600201624E00608614620600408E00600800610600602C4264660061060442440140500060040140000060060420000000\n\t00000000FFCA1E00000000180501504380282400B001001802002010600601400600622C0860061041460060800460060160\n\t0405640E14600A4841A4184080026084004000016006002000000000000000FF12DC80000010184382185000880080109109002e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A230C2002022\n\tB02A23221540422022AA2AA0002880022AE000000000000000FFDE070000018940000000098500000C200100000000000000\n\t0650820400020800000010000000000000600001001012010000801000408C00000013000400400002611000000000000000\n\t0000FF7E2D80008184004413400190214C00800180000000000000000401280000C00000000100000003200063402A000000\n\t00300C0000010000330320000006006000006440000000000000000000FF675C000001901141001900003041803801009802\n\t082000700200600404632E0160060040060060900020060064040C200E00600200030010408020400C00400000000600600000ae1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000557906D5\n\t7556556557D565565575575565085564864B65564063544460964D7556406500546556156800554556554000000000000000\n\tFFE16100002A82ACA80CC8AA8A29088508AA8AA80000012AA2AA0A24022AA0222AAAAA22A2AA2AA2802AA20220A2222220AA\n\t2AA220A2A2222022803022AA2AA0002AA2322A2000000000000000FF73DD0081000000000000010240010810000002000000\n\t0004280000010048000000000008000000000000080008000B00000882240000001000100100002000000040000000000000\n\t00000000FF1E2500012A90088D0008A20108009040AA8AB80000002AEAAA4021422AA5022AE2AE3242AA2AA0022AA01A0022006e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF49\n\t7800000000000000000004808C1000000000000000000C000008000000008000000008000000000400000100001101000004\n\t10000110108000000400000000000000050000000000000000FFC38F90802A8AA8AA8AA8A288286480482A8AA80000012AA0\n\t222AA2AB2A82AA2A92A82AA2AA2AA00028A04A0022AA202206222003A0220225200022A0AA0AA00028A2AA20200000000000\n\t0000FFBA25800800000201000001000025001000401400000100500080801100481100480400480400402000012014109000\n\tC40000008490001000400004800000100000410000C000000000000000FF6B59800055955955955955111911049955F5580000ee1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600081220001\n\t2002002010000002000000002000802000000000000000FF2F740000000000000000A0000000000002000000000002028022\n\t82A82A80A820000000000000000000022004840000002000000800000000000000000000000000000C800000000000000000\n\tFF251C0000002004000000020000000002800000000000000000800000000000000000000000000000080081000001000000\n\t000000001008800000000000000000800000000000000000000000FF60041000800000000000080000000540804000000001\n\t0000880000008000000008000000008003100003402A00000400300881201510400403081000004000000200000800000000001e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000002002002\n\t002003002000002002002000002002002802002000802802802802002000000002000000802802002000000000000000FFBF\n\t1F000001C01001801F05001801801801800000000000008700E88F08E08E20600000680680600000600502EA0420782400E0\n\t0C80600780400800000600000000400A006000000000000000FFB91C00000000100120104100000100110500000004000404\n\t04444444444044004000004004004000100544004804000804000C0481081000400000000400000000480400000000000000\n\t0000FFF783000000800C00800C00A00800800800800000020000000000000100000000000000200200200000200300200220009e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF87D400\n\t0001800400000001800000000000000000000000000000000000000100000000000000000080600100000080000000100080\n\t0001000000000000000000006000000000000000000000FF0EE8000000800801001800000800801801000000000000000600\n\t2006002002002000003003004000002006000002001000002002002802002000000004000000000002002000000000000000\n\tFF9ECF0000000010000004010000010000000000000000000000005000004004004000000000000000800000001004004004\n\t000804000000000000000000000000004004000000000000000002FFA979000000800A00200800A00800800A008000000000005e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (184826004002\n\t31A000000124040000086006006000000000000000FF2722000000000C01111800101801809C018000000008000006046506\n\t006016006000406007404300800A0200700214000400403080680600028A020004000010000006006000000000000000FF7D\n\tA2000001880801041800001001801801800000000800000608E04641600640600000600600404000014200E00A0020120020\n\t02102006204002000044400000100006006000000000000002FF2E7200000180000000000180000000000000000000000000\n\t000000000000000000000000000000000060000000000000000000000000000000000000000000000060000000000000000000de1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (068068060060\n\t0600600100600600600000080700700420200228600308490000200000000600000000040600E000000000000000FFDF7F00\n\t000000180182180008B801C1180180000000000001161562B62060160060804060060062200002A70A608442000180501310\n\t4000802488040006020010000006006000000000000000FF6B23000004000801089803800801C81801800000000000000600\n\t6006006006006000006386A04080216002006924082001006406004042086000000084200001006006006000000040000000\n\tFF6CC1000001C98807401805815C01901801800000000000111760701600E006206100006506004000406002F4E14C40080C003e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFCCE7000002\n\t001801001E01801A018018010000000000001806006006806807807800006106004000006000004004407804204004005882\n\t006000000006000000006406004000000000000000FFA638000001C01801801801800C018018018000000000000006006007\n\t007006006000006006006000816007006004002001004001006047006000000006000000006006006000000000000000FF68\n\tBE00000040180180180180180180180182000000000000060060060060060060000060060060010060060068840020000862\n\t0210600600600000000600000000600600E000000020000000FFD863000001A01A01A01800000A018018018400000000000800be1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020261070060\n\t00020006020000006006004000000000000000FFCBDF000001845A0100380180080180180100000000000800060060061460\n\t06046080086106086110406005804080087054004052006006806000000006000000006006004000000000000000FFE82000\n\t0000081A0121BA01804899845A01000000000008001620680600620600600002600680608020601D084C7004640000618200\n\t77470660000C0006040000007006004000000000000000FF12E3000001901811001901881901911C05000000000000000640\n\t6006006506016000846006204201006100124004007002006006024002006000100406000001006006004000000000000000007e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600600\n\t6000007006806000007806005006003501046002004802006000000006000000006006004000000000000002FFDFAE000080\n\t005801401901800C01805801800000000000000600700614610681600000600610600000610600D006302001004070804042\n\t006000080406000000006006004000000000000000FFA6370000018218010018018008018018018000000000000006006106\n\t08600600600000600600400000E00200000410348002510A02680600E000000006000000006006004000000000000008FF54\n\t64000000021809001801902C01929805800000000000000E00600600600602610008608620420800680204030C022252807000fe1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (81000401C018\n\t01801401800001C0100100000000000000060060060060060040000000060008000070060070060060068040000048000060\n\t00000000000000006006000000000000000002FFD776000000001C01A0100180000180100100000000000000060060860060\n\t07004000000006000000006006816006906806004000844000006000000000000000006806000000000000000002FFD0F200\n\t0281801B01A01001800001801601000000000000000600600610600600400000100600080000E006006006A060060060D000\n\t400101600010000000000180600600000000000000000AFF742C000001C41081001E01800801C01A0080000000000000060000011040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (280400600000\n\t0000000000006044000000000000000000FF7037000000001801801801C000A1809801020000000011028622400E00622612\n\tC50008000E00009088680700700E00610E007004C02024006000010000000000006004020000000000000000FF8FA6000001\n\t8018018010098200018010010000000000000006004406006006004000000006000000006206406006406006404004002004\n\t006000000000000000006004000000000000000000FFB1460000000018018010018000018010010000000000000006006006\n\t006006004000000006000000006006006006006006006000004000006000000000000000006006000000000000000000FF1100811040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006026000\n\t000006000000007807006802006002006000002000006008000000000001006004000000000000000000FF7C94000401A018\n\t01801001800001801001800000000008808600421600600648E28008000E00008908600620680A80788A2048012024230060\n\t00008800000000006804020000000000000000FF0CF9000000001E01801801A00841801E0101000000000400060040060060\n\t060240000000060000000060060060060060060048060020050A601000800000000000600C000000000000000000FF92AF00\n\t020180180181100982082180900100000000000002060040060062060240000000060000000060060060062068460060060000411040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020000100100\n\t1001800001801001800000000000000600600600780600600000080600000000600600400400600680600380400000600000\n\t0000000000006004000000000000000000FF9DF5000000401801811800000901801801840000000000000644401600604600\n\t6000001006000000000407006004006042804000003202026000000000000000000044000000000000000000FF41DB000001\n\t8018018018000000018018018000000000000006004006006006206000000006000000000006006804006802006800003000\n\t08600000800000000000080C000000000000000000FF10AA000000001801801401800C21801001808000000004000600400E00c11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0E8000000000\n\t0000002860A0000000000000000000FF895D000005801001101A0001B8018E19458000000000200086006A06A06006316000\n\t200206480000180A061044421C6004482000004000406000000048000000000004000000000000000000FF416C0002282492\n\t012A1800204C01B21D518000000000400AA6A065062C6236A06000400836080000900246814202ACEA04C8D0A8A95012C060\n\t00000080000000800844000000000000000000FF1364000201803083003B45950B2980580180000000000000061160060060\n\t0610E200000206410000206917004146806016044202005322156000200808000000D06504000000000000000000FF87360000211040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (254004008008\n\t00808000A00804049380220058850D94C08B98A00000001000000000100810800000000000000002FFA8D200000080000000\n\t0C01080821800800000000000000012610200208600A00400000000200000000202200301600240202200004204400200020\n\t0080000000804202000000000000000002FF1A6C000001808180480001864480100000000000000000100108908002100008\n\t0000000000000000016409400025018A00208268280420010000000110000000806400000000000000000000FF0A01000001\n\t822000040025900100000098000000000000100020100000180000820000002820000000708000080040010010000001000000a11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (201201200011\n\t20320140044100000000000008048008040048040040008008048100008408048000CC800880A090AC80880C004000000088\n\t000000804800800000000000000000FFE5C5000001801801841A230210018C19138000000000000006006006806006316000\n\t0000062000000062060862AC2862AE00E0C402E2B4A36000000048000000084006000000000000000000FFBEBB000404C80C\n\t80D00800D14CC0C00C20800000000040010310210300210380220000100200000111200322280304B0034A32112030010020\n\t0000090000000000340A000000000000000002FFA7770002283012030224C22010482022210000000000400200000104800300611040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000005480000\n\t00550D50540000000000000000FF9EEB00040044040000000043440000060400000000000000000000010000008010000010\n\t01000001000000001001011001001021101041010001000000000001001000000000000000000002FFF63400002A0220880A\n\tA2A20982AA0AA0C80000000000000AA82A82A8AA8AA82A80002A82A8280000288A202A02000C8010080040280280A0000000\n\t02200000002882A82A0000000000000000FFC6A3000200B10A42A00800A20800C00802800000000100000080280000000000\n\t2000000802040000802112812802A22C53042C00842840152000000000000000842802008000000000000000FFF70800030000e11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80002A82A82A\n\t8000288211A5020022AD501402800583180000000002A80000002882A82A8000000000000002FF8855000000052000000008\n\t0204000000000000000000000001001000000000000000000000100000001000808080088080100080140040048000000000\n\t000000800000008000000000000002FF698F00012A08A0AA0AA4AA0000AA0AA03000000000000002A82A82A82A82A82A8000\n\t2A82A82A80002A82A02802C82A00002103082002002A00000012A80000002A82A82A8000000000000000FF05B10003542803\n\t543545442821543545140000000000800D50550550D51551550000550D50450000D50550540C50C00C40C30C11410C90C80000111040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (019019550018\n\t01801801800000000000610600600600600600600000008600000240E00604C11620604610400604400E0040200100400000\n\t00006006000000000000000000FFEB9200028020520120001124840120120100000000000048048048040040048050000008\n\t048000008000C408480090004900D0310050A0CC4000800800000000844800000000000000000000FF215700000080080080\n\t0A008808008008D4800000000000000000000080000000000000000200000204201204A1520022822C000232000201200000\n\t0000000000002002000000000000000000FF37F000002A0A80AA4AA0A21020AA4AA10000000000000012A92A92A82A9AA92A00911040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000000000\n\t6800000000000000000002FFC4D20000028111100008B6000851801801004000000000600200200200200600604000000200\n\t0000002102002082A0208211C10220A522500030018100000000004002000000000000000002FF06890001AC400401400409\n\t4004004004000000000001001095005005005001001000000000400000180004608060000000000200004048000001000020\n\t000001000000000000000000000002FF4D20000000C00C00C00C00C10D20C00C00800000000100B003003083003013003001\n\t001003000000003003003002003103011213413003002001001000000001003002000000000000000000FFB225000029801800511040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000006000012\n\t00800602400E00E1C4002710002018006020000000000000000004000000000000000000FFFECE0000018050010011400018\n\t2981180180000000000060060060060060561160000000060000000043060140060460141000020325003060000081000000\n\t00004004000000000000000000FF18A300000180400400214180000000000200000000000000000000000000282000000000\n\t00000010006400210000020030000010148040008000000000000000006000088000000000000000FF877300000180000008\n\t00018080C00000000000000000008010000080000008000000800900C000004168008208080008409008108208008000000000d11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B810001C01A5\n\t1A05000000000000600610E00600600601600000000600000000400601620E00610220A00408040600000000000000000004\n\t510C000000000000000000FFD66B0000000450210808018C3001881801800000000000600600600600600600600000000600\n\t00020460061040C40AE04404004A0120B4002000000000000000006004000000000000000000FFFD22000001811155005815\n\t8018018018018020000000006006006006006006406000000006000000012006444015016004010000102024012028000000\n\t000000002004110000000000000000FFA0BF000000181021001800001801809805800000000000600601E00600600608E04000311040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000552554\n\t000000000000000000FF8EF400012B8AB88B8808AB8830AB8B18A800000000000072AF2372AF2AF2AF2AE0000002AE000000\n\t28F2AE22F02602E22312132D2A92022AC0000010000000012CE226000000000000000000FFD3A8000080201E01800A01A210\n\t01801801000000000000780780780780780780600000000600000004300600708F3070830418970100120040000000000000\n\t01802006000000000000000000FFE2C60000AB8898898018A20098AB8038AD00000000000062AE2262AE2AE2AE2A60000002\n\tAE8000002C8AAE226D16E06A1AC80286A201162A8000000000000000288234000000000000000000FF35B2000000001803A200b11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (068000020068\n\t0600280C0960128C4094906802006000000000000000006004000000000000000004FFAB190000AA2ABAAB8ABEA3801CAB8A\n\tB8AB0000000000006AAEAAEAAEAAEAAEAAE0000002AE0000002AA2AE2AA204A462A2104A262262222AE000000000000000A8\n\tB2AC000000000000000004FF3E82000001C01C21C2AA01831201C05C01000000000100600610600600600600680000000700\n\t0000006006102005106102014006006046006000000000000000006104000000000000000000FF4C9A000054555955D55955\n\tB15955D55D55000000000000655655655655655655600000055700000051255655244400E45241644454654655600000000000711040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (925001801803\n\t000000000000600600600600600600600000000600000002200600600614601440002401200400E000000000000000022148\n\t000000000000000000FFC3D00000018218018008018090018018410000000000006006006006006006006000000006000000\n\t00600610E09240E10402A48C082088106000000000000000006000000000000000000000FF8CF2000000001801A008119414\n\t01A01A0100000000008060060060060060060070000000060000020020060060C204600421000600A0880060000008000000\n\t00042000000000000000000000FFDF440000018018018008018150018018010000000000006006006006006006006000000000f11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002CC2A60000\n\t00000000000000FF152A00005413095180195581515595591580000000005505565565565565565560060005560060005105\n\t505464B25364460101125404525460000060060000005504C6000000000000000000FF72EE00000180000182380180100180\n\t1809800000000000000600600600600600600600000600600000400000600204600611001000200204E00000600600000000\n\t4016000000000000000000FFAE730000AB88B88D8AA8A38410AB8AB88900000000002AE2AE2AE2AE2AE2AE2AE0000002AE00\n\t000028E2AE2262260062240C000622232423600000000000000028E210000000000000000000FF9CA600000000184580080900091040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200000400000\n\tE142146006012010002102084000006006000000044016000000000000000000FF177600002B8AA8AB9018A38AB0AB8AB901\n\t80000000002A82AE2AE2AE2AE2AE2AE0060002AE00200028C2A82363520062362A232632834A30400000600600000028C226\n\t000000000000000000FF884A0001000028018AB8019010018018218000000000000006006006006006006006000006004000\n\t02000000E00600608E30022000A002004000006006000000000006000000000000000000FF1CBA0000AB8AA8AB8098AB8AB0\n\tAB8AB82380000000002A82AE2AE2AE2AE2AE2AE0060002AE0060002AC2A82A620628E326220222230212206000006006000000891040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01C018018000\n\t0000000010068070070070070060070008060020100040000061500060045820A24100020060000060060000000050060000\n\t00000000000000FFF3438000C0000801901801801C0180180180000000000010060070078070060060060010060020000050\n\t0000700600610E002146004002004000206006000000004806000000000000000000FFD5CF00000180080180180980100180\n\t1851800000000000000680600600600600600600080600000004400010600E40E09600210010602203400000600600000000\n\t4086000000000000000000FF9D8E000100000801B33801801A01A0190580000000000010060068060070068060070000060000491040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (420600000000\n\t0000000000FFCB5F0000000058018018820098018018018000000000000C0602720700610603600600000640200008400000\n\t6000556102092102014200024040006006000000004006000000000000000000FFDA5F000141803809901804001A01801801\n\t00000000000200062060060068060062060008060020080048000070A8006310202010206023006000006006000000404006\n\t000000000000000000FF2C040000040018018019458010018018018000000000040006286006006006006406000006000000\n\t004000106000046406002008102043004000086006000000404006000000000000000000FFE888000001805811C01881801400c91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00410000600C\n\t15614611400009208E000020006004000000004016000000000000000000FFE4250000000008400219000118058018018000\n\t0000080000060463060060860460060000060064000040000160042060040040060000061101000060040000080040060000\n\t00000000000000FF73F9000001880808021815801801801801800000000000000600608600600601600E0000064062001040\n\t8000E00A00602200410608048E04000000600400000800440E000000000000000000FF4A8B00000400082000184980100382\n\t180180000000080000061060060A60062860060000060040000040001060000460020040001120060880805060040000000000291040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A90080000000\n\t000002AA2AE2AE2AE2AE2AA2AE0002AA4020002AA0002AA5020020002220864160261220002AA2240000002AA2AA00000000\n\t0000000000FFE3F6000001912002000009900000000141000000000000000000000000000000000000000011000000400000\n\t0210100100100240088400100000000010000000004000000000000000000000FF0E85000001820000000001812000000014\n\t00000000000000000000000000000000000000004200000060000000C0448428010010240090208000000100000000006000\n\t000000000000000000FF7F8A000001904810001800001801841801800000000000040600600614600650601600000600600000a91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFB905000155931113D55955155B55D559558000000000001D5755655655755755655600155654C00055600055640E\n\t5565144D424444454C546001556556000000157552000000000000000000FF4DC200002A80888A8AA8AA8088AACAA84A8000\n\t0000080002AA2AB2AA2AAAAAAAA2AA0012AA0320002AA0002AA0222AA22A23204A04220A20A0002AA2AA0000002AA2AA0000\n\t00000000000000FFE58B00000000202100100000000100100000000000010000048000008000000040000000000040000010\n\t00000020000024004088088000000000000000000000200004000000000000000000FF513E0001AA9458A80AA8A30648AA8A00691040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001204480\n\t880100200A0088010001000000000000200800000000000000000000FF50E400000004000000000000020000000000000000\n\t0000080000000000000000100000000010000000000100000810004000048801000010000000000000000000000000000000\n\t0000000000FFA5E800002A88A0888AA0A28AACAA8AACAA80000000080002A82A92A92A82A82A92A80002AA2220000AA0012A\n\tA3020022022A00002002202320002AA2AA0000000AA2A8000000000000000000FF332B000000001021001001100201201000\n\t000000000900100500500500480480400400100410400000080000401000010410430410414404000000400400000000000400e91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0800000000000000000000000002002000002802002802082002510882802043020000002002000000000000000000000000\n\t000000FFD42C0000000000000000000000000000000000000000000000000209A20000000000000000000000220A90000800\n\t000000000000000800800000000000000000000204000000000000000000FF0F7F0000000000020000000000000000000000\n\t0000000000000000000000000000000000000000000000008000010008000000000000000000000000000000000000000000\n\t00000008000000FF32020000800000224000080000002004000000000000000001000800801001000000001000010000200000191040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFDCBC00000080080080000080080000000000000000000000000000020020000000000000020020018020030020028020\n\t02000002000002002000003002000000000002000000000000000000FF453000000180180580000100180000000000000000\n\t0000000000000E006000000000000006006000224A0D00600608600728D00780600602400000600600000000000200000000\n\t0000000000FF218E000000001001000001001000000000000000000000100000040444400000000000000400000080410400\n\t4000805004804100004840004000004004000000000404000000000010000000FFE16800000080080080000080080000000000991040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000002FF098F000001800000000001800000000000000000000000\n\t0000000000000000000000000000004000800801000000000000001000000000800000000000000000000000000000000000\n\t000002FF46920000008010000000010018000000000000000000000000000002002000000000000002002000006004006002\n\t806002004002804002006000002006000000000002000000000000000000FF4F440000000006010000000000000000000000\n\t000000000000000004004000000000000000000000000000000000000001800800000000800000001000000000000004000000591040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000600600000000000000640600002600404E0060261060044040020060060000060060000000000060000000000000000\n\t00FF396500020000100100040040180A00000000000000000400000001460060000000000000461064000064474064064172\n\t474A4944911456D14200007006000000000006000000000000000000FFFA6F00000180100101204000180000000000000000\n\t0000000000000600600000000000000600400004400601600402601600601422000400410010600600000000000600000000\n\t0000000000FF824A00000180000000000180000000000000000000000000000000000000000000000000000000000000000000d91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t9197000201801801800000001804000000000000000000000000000600600000000000100600400000200100600600600600\n\t2014006805002000006006000000000006000000000000000002FFE154000000001A0180C600409814000000000000000004\n\t0000000007006000000000000006106401002C4002640600F04630188C256407312000087006000000000006000000000000\n\t000000FF5ED200000040102100000982188000002000000000000000000000A7006000000000000026206001007804A06003\n\tA0628E82422408202C006280006006000000000006000000000000000000FFD9AD000001981041000031851900000040000000391040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (026106112217\n\t0A4004102000006006000000000006010000000000000000FFB66A0000002018018000018018000000000000000000000000\n\t00000600600000000000000600600080200000600600600600000F0040060020000060078000000000060000000000000000\n\t00FF7902000001C0180180040180180000000000000000000000000000060060000000000010060060010020030060060060\n\t07000004005006E00000006006000000000006000000000000000000FF2C2B00000000180180000180180200000000000000\n\t000000000000060060000000000000060060000000020060060060070008050050040000000060060000000000060000000000b91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0600600000000000000600600142640604E00E0462A62B3404B4120C000000006006000000000006008000000000000000FF\n\tD649000001805801800101801800000000000000000000000000800600600800000000000600600044240000601600600604\n\t080600C21600000000600600000000000E000000000000000000FF5ABC000400001807880401901810000080000000000000\n\t0078000206006000000000000106074000002000206207007447C0014E404004080000006006000000000006000000000000\n\t000000FF2779000001D01A01904011841800000100000000000000000008050610600000020000000600600000080045640600791040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF0295\n\t0000098018018000018018000000000000000000000000000006006000000000000006004001004007006006006006000005\n\t800205002000006006040000000006000000000000000000FFBAF00000001018818040118018000000000000000000000000\n\t1109061060100004000001060160002060060060060060070009440110060020000060060000000000160000000000000000\n\t00FF993000000180180180000180180000000000000008000000000000060060000000000000060060010060060060060060\n\t06000004000006000000006006020000000006000000000000000000FFBBB00000000038018001018A18080000000000000000f91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000000000\n\t04000000006000000000006006000000000000000000FF3F6B00020180180180040180000000000000000000000000000000\n\t00000000000000000006006001004007006006006003004802000001000000006000000000006006000000000000000000FF\n\tA82D000000001C01800001800000000000000000080000000000100000000000000000000600600000680600600680680200\n\t4002800000000000006000000000006806000000000000000000FF64D6000011801301800001800000000000000000000000\n\t000000000000000000000000000600600040680600600600600400000000020400000000600000000000680600000000000000051040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000006006000000004006086816064000004806004002000006000000000006006000000000000000002FF14A0\n\t00000000180180A0018020000000200000000080000000020000000000000200200006006000803214406006006004000C24\n\t016804002000006000020000006006000000000000000002FF8FAE0000018018018000018000000000000000000000000000\n\t0000000000000000000200060060000020840060860060020040060060000020000060000000000060060000000000000000\n\t00FF37960000000018018000018000000000000000000000000000000000000000000000000006006000004006006006006000851040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20FF7EA20000\n\t0000180180000180000000000000000000000000000000000000000000000018060060008020040060060044140008200068\n\t44002400006000000020006006000000000000000000FFDF7D00000180180180000180000000000000000000800000000000\n\t0000000000000000000600600000280C206006004002004A2280E800002000446000020000006406000000000010000040FF\n\t7CE9000000001801800001800000000000000000000000000000000000000000000000100600600000000400600600641200\n\t404600604000240008E008000040006006000000000000000000FFF43C00000180180180800180200000002000000000000000451040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (601310040200\n\t4000006000000000006106000000000000000000FF115C000000200801000201800000000000000000000000000000000000\n\t0000000000000006006000004007806807806804002000000006004000006000000000006006000000000000000000FFE7E9\n\t0000004018018044000000000000000000000000000000040000000000000400440006006000002504007006014002004002\n\t806000002000006800000000006006000000000008000000FF6BF40000018018018000000000000000000000000000000000\n\t0000000000000000000000060060000020040060060048050008000068040020002AF008000000006206000000000000000000c51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000008000008000000000200080041800200060000000000000000000000000000000000000000000FFABB70000\n\t018E282104220208000000000000000000000000000001000100000000000000A60060000040062060060060040020000102\n\t06004000006000080000006026000000000000000000FFCD390002102C0A2110000810000000000000000000000000000002\n\t00200000000000000906886000B2C826C26886D268228AE482A4884B12C000A8E0C808800080E846000000000000000000FF\n\t8A5D0000018128810021438000000000000000000000000000000000000000000000010826036000005C0610E0370161128000251040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (944000020020\n\t12000004D50000000000000000000000000000000001200000000000008800810000A00A04838910978920000D0880080C82\n\t0000A00820008000008884000000000040000002FF6A9B000000800801000000000000000000000000000000000000020000\n\t000000000000000200200044442000608300440280C08608300000E00008A008000000006002000000000000000002FF342B\n\t000049808080080009A0000000000000000000000000000010000000000000000000000A00001A000008002808001CDB0250\n\t4684004C0000000080000000000000000000000000000002FFA507000001800000000021800000000000000000000000000000a51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A2A42040000\n\t802800000000002000000000000800000000FF04E50002002052010000012000000000000000000000000000000000000000\n\t000000000804AA4000894904804A84804800C4C80500080D094000804800000000004804000000000000000000FF7B020000\n\t41841001840021000000000000000000000000000000000000000000000000000600E00022420600E08E02E00640600C24E0\n\t06224000006000000000006002000000000040000000FF9A72000400C00C0080061480000000000000000000000000000009\n\t00810000000000001003002001083003003002103512130523002441002001002000000001003002000000000000000000FF00651040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (505500000000\n\t00800D50C40000B10440D50420550D50050CC0D21028510000D50D50000000000550000000000800000000FFC36300040000\n\t0400000600000000000000000000000000000000000180000000000100100100000100010100110180100110000100100010\n\t0001001001000001000000000000000000000000FF405900002A0880880000A20AA00000000000000000000000000002A82A\n\t80000000000002A80080000002102A80082A82A80802302084802000002A82A80000000002A8000000000000000000FFCDED\n\t000300A20A44A000108000000000000000000000000000000000000000000000800802802000C4204A80204200280280288800e51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00002A0AA0AA\n\t0000A20AA00000000000000000000000000012A82A80000000000002A82A80002202202A80602A82A8221AA82202A8220000\n\t2A82A80000000002A8000000000000000000FFC16C0000000000004004100000000000000000000000000000000001000000\n\t000000000000108000040080000091000000A80000008100040000000000000000000000000000000000000000FFBFBD0000\n\tAA0AA0AA0000AA0AA00000000000000000000000000002A82A80000000000002A82A80002B02282A82082A82A82302A82A82\n\tA82280002A82A80000000002A8000000000000000000FFD7DE0003543343520001441540000000000000000000000000000500151040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030000010030\n\t03000001001000000000000002000000FF3F4700000980180180180180000000000000000000000000000000000060000000\n\t0040600608601000440810600000400600E046006204000000006006000000000000000000000006000002FF167400030000\n\t1201001211000000000000000000000000000000080000400000000080480480400080400080481080480088400108880408\n\t8000804804800000800000000000000000000002FFCDB0000000800800800000800000000000000000000000000000000080\n\t0000000000002002002000112110002500000002012002002000000000002002000000000000000000000002000000FF88BF00951040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000A0\n\t0800800008800A00800800B20A00840800888800800000800800800000800800000000000000000000FF4B7D000000800010\n\t001800010000040000000000000000000000000000200004000000200200200001250801608000608201C022402006000010\n\t002006000000000000000000000002000000FF0AB00001E84014014005014000000000000000000000000000001001004000\n\t000000000000080000004000080100540160040280110260000000000000000000000000000000000000000000FFE7540000\n\t00C00C00C00C00C080000000000000000000000000001001002000000001003003002001003001003001003403001283003000551040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (011010210038\n\t0000200000000000000000000000000000000060100000000060060061200060000060004060160800340220000000000060\n\t06000018000000000000000006000000FFE0C700000080110108580100C00002000000000000000000000280000960000202\n\t00006006006000004200006000006086410204042542020000016006000000000000000000000006000002FF355700000190\n\t01000A000180000000000000000000000000000500001100100002000000000001000000000000002001104004100882A044\n\t0000010000000000000000000000000000000000FF863C00000180000000010181000000000000000000000000000000000000d51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00002AE00600\n\t00002A82A8000000000006000000FF43DB000001151A05801811000000000000000000000000000000000000600000000000\n\t6006006000002108006000090406014132004014110000006006000000000000000000000006000000FF6D05000080001021\n\t001801800000000000000000000000000000000000600000000000600600600014C00000600000608E084400110082000000\n\t006006000000000000000000000006000000FF15D50000018010510418008000000000000000000000000000000000006000\n\t00000000600600602001610000E000006006084020510000400008006006000000000000000000000006000000FF9191000000351040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006556\n\t556000CD2D505565505504063464CA54CB144C8000557007000000550550000000000006000000FF202700012B80DC898018\n\tAB80000000000000000000000000000008008060000000000062AE2AE000A02AA0AAE2A8A20316A2108F22EA20A200002AE0\n\t060000002A82A8000000000006000000FFED73000100201C0180180080000000000000000000000000000008008060000000\n\t00006006006000002000006000000136008007006822000000006806800000001800000000000006000000FFAC1100002A84\n\t3889801AA200000000000000000000000000000000000060000000000062AE2AE000A52A202AE2A8230066224402A243362200b51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180180180\n\t00000000000000000000000000000000006000000000006006006000802800806000800406C0208E90641080800000600600\n\t0000000000000000000006000000FFD4CD0000AA2898ABA01AA2A00000000000000000000000000000080080600000000000\n\t62AE2AE0002A22A82AE2A82A802600222622E8222200002AE806000000AA82A8000000000006000002FFBD68000001D01845\n\tC01C01A000000000000000000000000000000000006000000000006006006000082008006000100006116022104006110000\n\t007006000001000000000000000006000000FFCE3E000054555955801B54800000000000000000000000000000080080600000751040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AE2AE000000\n\t000000000000000224000002FF7FBB0000000058038018088000000000000000000000000000000000006000000000006006\n\t00600049600000600001211400C110010100000000006006000000000000000000000004000000FF9A0E0000818218018018\n\t0180000000000000000000000000000000000060000000000060060060000260000060001020040800040824000000000060\n\t06000000000000000000000114000002FF4079000000045A0180181080000000000000000000000000000000000060000000\n\t0000600600600000E00000600000208C0C8804002102080000006006000000000000000000000004000000FFE50F0000018000f51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002AE2AE2AE0\n\t002A40002AE0062282AC2902802282000000002AE2AE0060000060000000000002A8000020FF14FE00005413411195415400\n\t0000000000000000000000000000000655600000000055655655600001600055200654C54C5504D650008600000055655600\n\t6000006000000000000540000000FF32D1000001000001800009000000000000000000000000000000000600600000000000\n\t6006006000016000006006004004004012080156000000006006006000006000000000000000000000FF938A00002B8898ED\n\t8AB8A380000000000000000000000000000000002AE0000000002AE2AE2AE0000460002AE00022222422422027006A000000000d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800009400000\n\t00000000000000000000000010070060000000000060070060001020008020069160060A6010104044000000006806006000\n\t006800000000000000000000FFDF3C0001AB0AA0AB8AA0A300000000000000000000000000000000062AE0000000002AE2AE\n\t2AE0002220002AA0063262AE2422602242040000002AE2AE0060000060000000000002A8000020FFE6C60001000000018000\n\t0000000000000000000000000000000000060060000000000060060060002840000020060040040040000002100000000060\n\t06006000006000000000000008000000FFF36300002B0AA0AB8AA0A300000000000000000000000000000000062AE0000000008d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060010060\n\t00000000000000000002FF5A3900002100000108000140000000000000000000000000000010070060000000000068068062\n\t00002021006007004A0600200008C00400000081E806006000007000000000000000000000FF16A900004100400180000100\n\t0000000000000000000000000000000600600000000000700604620000002000200601531214204651410600000100600600\n\t6000007000000000000000000000FFE325000001000001800001000000000000000000000000000000000600600000000000\n\t700600600001000000200600080600E08201410E000000806006006000006000000000000000000000FFECED000001000001004d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600000\n\t40A80040260163041AC00200A026000200006006006000006000000000000000000000FFC393000001000109000001000000\n\t000000000000000000000004000608604001000000600680600000240080200600600620222E004086050000916026006000\n\t806100000000000000000002FFD81C0000010020010000010000000000000000000000000000000006006000000000006816\n\t12600000200000601600680E04614240430E000000006006006000006800000000000000000002FFB1790000010000011000\n\t010000000000000000000000000000000006006000000000006017106000002001007816000006006100004214000000006000cd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010040000040\n\t0000000000000000000000060060200000000060060060001142000000A60042040AC4400821042082000060460060001160\n\t00000000000000000000FFC15100000100000180000100800000000000000000000000000200060260000080000060060260\n\t0000400000020600800440008022201412000000600610E100006000000000000000000002FF4E9C00000100011180000100\n\t8000000000000000000000000000000612600000000000600602600008C15000428600A19C0000962B204E28000011600608\n\tE08008E100000000000000000002FF83E6000001000001800001002000002000000000000000000000000600600000000000002d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000000\n\t0000000000000000FFCB790000AA8000E90000AA80000000000000000000000000000002AE2AE0000000002AA2AA2AA00021\n\t00003262AA2042223222063A02020000002AA2AA2AA0002AE000000000000000000040FF9380000001000002000001000000\n\t0000000000000000000000000000000000000000000000000000120000110000020010110010008110000000000000000000\n\t000000000000000000000022FF4D780000018000000000018000000000000000000000000000000000000000000000000000\n\t000000008000000000088080000120000020000000000000000000000000000000000000000002FF7496000001000001800000ad1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004000004000\n\t81400400400000000C004010000001005004004000004000000000000000000000FFA0840000D58001558001558000000000\n\t000000000000000000000556556000000000556557D560005540004355564540160C62045465560000005575575560005560\n\t00000000000000000000FF8D930000AA8000888000AA80000000000000000000000000000002AB2AA000000000AAA2AA2AA0\n\t00322000A222AA2AA2AA22A2A22283220000002AA2AA2AA0002AA000000000000000000000FFB25700000000000040000000\n\t000000000000000000000000000000000000000000000008000000000040000800000802A020808800400000000100080400006d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000008010008000001080002A800042802000050800010800000000000080000080000000\n\t0000000000000002FFF2D2000080000000000000000000000000000000000000000000100100000000000000000000000000\n\t0000000800000410440000088020000001000800000000000000000000000000000000FF376B00002A8000AA80002A800000\n\t00000000000000000000000012A92A80000000012AB2AA2AA0002220000022AA08208208A0602322020000012AA2AA2AA001\n\t2AA000000000000000000000FF850D000000000003400000000000000000000000000000000000000480400000000080500500ed1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF8A3A0000000000000000000200000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF34FE0000200000200000000000200000\n\t0000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF281C00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000008000000000FF69A900000000000000010000001d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000008\n\t00000000000000000000000000000000800000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF96D8000020000020000000020020000000000000080000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000008000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFF8900000000000000000000002000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFAE5A0000000000000000000000002000\n\t0000000000000000000000000000000000000000000000000000000008000000000000000000000000000000008000000000\n\t00000000000000000000FF165100000000000000000000020020000000000000000000000000000000000000000000000000005d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FFE52100000000020000000000000000000000000000000000000000000000000000000000000000000401000000\n\t00000000400410050400000000000000000000000000000000000028000000FF35EB00000000000000000000000000000000\n\t0000000000000000000000001000000000000010000000004000000000000101010040000000000000802000000010000000\n\t0000000000000000FF8218000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000100000000000000000000000000000000100000000000000000000000050000000FF409B00000000000000000000000000dd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF80E2000000000200000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFD29F0000000000000000000000000000000000000000000000000000000010000000000000080000000040\n\t080000000000000100400000000000000080000000100000000000000000000000FFA6300000000000000000000000000000\n\t000000000000000000000000000000000000000000000000020080000000000000A082080282000000000080200000000000003d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000080000000000000200800000000001000000000200000000001100000800000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000bd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFE986000000000000000000000020000000000000000000000000000000000000000000000000000000000000002008\n\t0000000000000000000000000000000000000000000000000000000020FFDDB6000000000000000000000040000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000\n\t000000000020FF9D780000000000000000400000000000000000000000000000000000000000000000000000000000080000\n\t010000100000060088000000000000400000000008100000000000000000000000FF6EDF0000000000000000000000000000007d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000800\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF008D00000000000000004000000000000000000000000000000100000000000000401000000000000000000100\n\t00000000000000000100000000400000000000100000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF241F000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000\n\t000000000000FF241F000000000000000000000000000000000000000000000000000000000000000000000000000000000000031040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008028000000\n\tFF21BA0000020000200000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000008000000000000000000FF617B0000020000000000000000000000000000000000\n\t0000000000000000000000000000000080002000000000000200004000000000000800000000000000000000080000000000\n\t00000000FF209C00000000002000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000831040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000001000000000000000000010020008000000000FF223F00000000000000000000000000000000000000200000\n\t0800000000001000000800000000000000000000000000008000000000002800002000000000000800000800000000000000\n\t0000FF1910000000000000000000000000000000000000000000000000000000000000001000000000000000000000000002\n\t0000200000000000080000000000000000000000000000000000000000FFB8EB000000000000000000000000000000000000\n\t004000001000000000001000000000000000040000000000000000010000800000005000004000000000001000000801004000431040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000008\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF68DC0000000000000000000000000000000000000000\n\t0000000000000000000000000000000100004000000000000000000080000000000000008000000000000000000000000000\n\t28000000FFE4430000000000000000000000000000000000000000000000000000000000000000000000000400000000000000c31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF10\n\t8200000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000\n\t00008000000000000000000000000000000000010000000000FF164000000200000000000000000000000004000000000000\n\t0000000000000000000000000000000001000000800000000040000000000000000000000000000000000000000000006000\n\t0008FF2868000084000020000000000024000000000000000000000000000000000000000000000000000000000000000000\n\t00000000002880000000000000000000000000000000000004C0000000FF4B6F00000000000000000000000000000000000000231040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (005044000000\n\t0000000000000000000000000000000000010000000000FF74D7000080000020000000000000000000000000000000000000\n\t0000000000000000000000000000000000100000000010000000280000000000000000000000000000000000000000000000\n\tFFF9960000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040\n\t000000000000000000000000000000000000000000000080000000FFC2CD0000000000000000000000600000000000000000\n\t000000000000000000000000000000000000400000000400000000040000050000000000000000000000000000000000000200a31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF3DA700000000000000000000002000000004000000000000\n\t0000000000000000000000000000000020000000000000000000000004800000000000000000000000000000000000004000\n\t0000FFDC0D00000000000000000000000000000000000000000000000000000000000000000000000000000080001004000000631040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF9C8600\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF9C86000000000000000000000000000000000000000000e31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000131040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000001000000000080001001000009000000000000000000000000000000200001001000000000FF59E900\n\t0000000000000000040000000000000000000000000000000000000000000000000000020001000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000931040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFE807000010\n\t0000000000000200000000000000000000000000000000000000000000000000000000800000000100000800800008800000\n\t000000000000000000000000400000800800000000FF99A90004000004000000000004000000000000000000000000000000\n\t000000000000000000000200008000900000000000800000C00000000000000000000000400000000000800800000040FF80\n\t6A00000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFBC500000080004000000000000000000000000000000000000531040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010000000000\n\t00000400000000200000000001041000000020FF786D00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000008000020000400000000000000000000000000000000000000000000FF5A1C00\n\t0000000000000000000040000000000000000000000000000000000000000000000000000000000008002000800000004020\n\t0080020020000008400000000000080000000010000000FFE03C000000000000000000000040000000000000000000000000\n\t000000000000000000000000000000000000004001000001040000030002004000020840000000000010000004001000000000d31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000680000000000000000400000000000000000000000000000000000420200000000FF7331000000\n\t0002000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000040000\n\t000000000000000000000000000000000040000000FF08B90000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000040000000000300000280000000000000000000000000000000000280100000000FF04\n\tBE0004000004000000000004000000000000000000000000000000000000000000000000000000000001000000000009010200331040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFAB3700000000040000000000040000000000000000000000000000000000\n\t000000000000000000000000000200000000000000000A00000000000000000000000000000000000004A0000000FF806A00\n\t0000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFA99B00000000000000000000000000000000000000000000000000b31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFED83000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000004000000000004000004000\n\t000000004000000000000000000000000000000004FF18DC0002000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000800000000004C00000000000000000000000000000000000000000A0000000000FF4000731040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000200000080000000000200000200000000000000000000000000000FFACC00000080000\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000\n\t00000000020000000000000000000000000000FF380A00008000000000000000009000000000000000000000000000000000\n\t00000000000000000000000000280000000000000000200000000000000000000000000000000000000000000200FFF8EB00\n\t040000020000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000f31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000A000000000000024020000020000000000000\n\t00000000000000000000000802C0000000FF6A1F000108000000000000000110000000001000001000000000000000000000\n\t0000000000000000004000400000000004100000004000000000000000020000000000000000000000000400FFA56C000000\n\t00000000000000000000000000000000000000000000000000000000000000000000004000000000000000800C0000080000\n\t000000000000000000000000000000200000000000FFFC130000000001180000000000000000000000000000000000000000000b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000A0100000000FF96830000000000000000000000000000000000000000000000000000000000000000\n\t000000000000040000000000000000000000400000000000000000000000000000000000000400000000FFCB8E0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000400000000\n\t00000000000000000000000000240020000000FF3E9100000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000080000000000400000280000000000200000400000000000000000000000000000FFFF1700008b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000100000000100000000000000000000000000000000000010000000000000000FF9A8800000000000000\n\t0000002000000000000000000000000000000000000000000000008000000000000000008000002008000000000000000000\n\t0000000000000000008000000000000000FF22B3000000000000000000002000000000000000000000000000000000000000\n\t0000000100000000000000400000000020000000000000000000000000000000000000000000000000000001FFE529000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000800000000000004A05200000A0000004b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0020000000000000000000000000000000000000000000000000000000000000000020000020000000000080000008000000\n\t000000000000000000000000000000FF093C0000000000000000000000000000000000000000000000000000000000000008\n\t000000000000000000000000000000010008000000200000000020000000000000000000000000000010FF3FDA0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000\n\t00000000000000000000000000000000000000FF43CF0000000000000000000000000000000000000000000000000000000000cb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF3D7D00000000000000000000200000000000000000000000000000000000000000000000\n\t00000000000000000020000020000000000100000008000000000000000000000000040000000008FF882000000000800000\n\t2000000000000000000000000000000000000000000000000800000000000000000000008000000000805000042840008000\n\t0020000000000000080000000020000000FF2B73000000008000002000000000000000000000000000000000000000000000\n\t0000000000000000000000000080000000000020000228000080000000000000000000080000038020000000FF0680000000002b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000100000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ab1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFB4BF00000000008000000000000000000010000008000000000000000000000000000000\n\t00000000200000000000000400000000500000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF8003000000000000000000000000000000000000000000000000000000000000006b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008000000008\n\t0000000080000000080000FFBFD8000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000200000000300000000000000000000000000000000000000000000000FF1A11000000000080000000\n\t0000000000001000000800000000000000000000000000000000000000200000000000000080000000000000000000000000\n\t000000000000000000000000000000FF54450000000000180000000000000000000000000000000000000000000000000000\n\t000000000000080000000000000100000000000000000000000000000000000000000000000000000000FF409B000000000000eb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF4CFE0000004000000004000000\n\t0040000000041004000010000000010000000010000000010000000010000000010000000010000000010000000010000000\n\t01000000001000000001000000FF706A00000000000000000000000000000000000004000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFE75600000002000000\n\t0020000000020000000020000000008000000008000000008000000008000000008000000008000000008000000008000000001b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010000000010\n\t0000000100000000040000000040000000040000000040000000040000000040000000040000000040000000040000000040\n\t0000000400000000400000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF9D2F000000008000000008\n\t0000000080000004180000000020000000020000000020000000020000000020000000020000000020000000020000000020\n\t000000020000000020000000020000FF247C0000000000000000000000000000000006100000000000000000000000000000009b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001001001000\n\t000000000000000000FF81D90000000000000000000000000000000004000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF989A2000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF8A9000000000000000000000000000000000002000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF7EFF00000010000000005b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000010000000\n\t00000000000000000000000000001000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFE8E1400400400400400400\n\t400400400400400000000100100100100100100000000100100100100100000100100100100100100100100100100100100100db1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF4BA34004004004004004004004\n\t0040040040040000010010010010010010010010010010010010010010010010010010010010010010010010010010010010\n\t01001000000000000000000000FF7BDD40000000000000000000000000000040000000000000000000000000000000000000003b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF6D0000000000000000000000000000000000000000000000000000000000000000000000000000000010\n\t01001001001001001000000000000000000000000000000000000000000000000000FF4BA340040040040040040040040040\n\t0400400400000100100100100100100100100100100100100100100100100100100100100100100100100100100100100100\n\t1000000000000000000000FF4BA3400400400400400400400400400400400400000100100100100100100100100100100100\n\t1001001001001001001001001001001001001001001001001001001000000000000000000000FF409B00000000000000000000bb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000100100100\n\t1001001001001001001001000001001001000001001000000001001000000000FF0B88000400400400400400400400400400\n\t0000000001001001001001001001001000000000000000000000000000000000000000000000000001000000000001000000\n\t000000000000000000FF87A25004004004004004004004004004004004000001001001001001001001001001001001001001\n\t001001001001001001001001001001001001001001001001001000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C0800000004\n\t0000000000000000000000000000000000000000015010000100000015015012015100000000000002000000000000000000\n\t01501501000000FFDB9240040040040040040040040040040040040000010010010010010010010010010010010010010010\n\t01001001001001001001001001001001001001001001001001000000000000000000FFA85400000000000000000000000000\n\t0000000000000000000000000000000000000000000000000100100100100100100100100100100100000100100100100100\n\t1001000000000000000000FF41A200000000000000000000000000000000000000000000000000000000000000010010010000fb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000003140\n\t1400000008FF742E00000810E2080001000000081000000003080000000400000000400000000400000000400001A00C1002\n\t0000401A01820411A20000400000000430000000400000000421821820410000FFBFE10000101A4190000000000010180000\n\t00002000000000000000000000000000000000000000000000900A00000800000A00900A0000000000000010000000000000\n\t0000800A00A0690000FF78362000101C40100000000000101C00000000000000000000000000000000000000000000000000\n\t4000100C0000000400CD02104C0000000000000210000000000000000000CC0CC0410000FF05BB00000C080348000000000000071040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D01080004001\n\t040D00C05040D04001000000001000000001000000001080C04C05080000FF99170000020904000000000000020800000000\n\t100000000000000000000000000000000000000000000000014000040000019A400140000000000082000000000000000000\n\t00004001A00000FFE58E00000601810600000800000600800000021800000000200000000200000000200000000200004008\n\t20068000060400469060468000020000008020008000020000000020460461020008FF0DC600002000C22200000000002000\n\t000000020C00000000000000000000000000000000000000014008000080000014014000014080000000000000300080000000871040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000800B4D001800000000006F11110000000000000143FFFFFFFFFFFFFF\n\tFFFFFFFFFFFFB03D000000060002000020000000060000000020000000008000000008000000008000000008000008008001\n\t00000800800901800900000800000001800000000800000000800B00B0080000FFC1D600000D03404C00000000000D000000\n\t04000404000000000000000000000000000000000000003000D0050000000300054010350000000000000010000000000000\n\t0000D00500540D0000FFA41A0000004380C1000400000000400000040410040000100000000100000000100000000100000000471040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c71040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000271040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a71040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000671040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e71040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000171040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000971040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000571040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000800B4D000400000000006FEF700000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d71040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000371040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b71040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000771040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f71040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800B4D001400\n\t000000006FD39500000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000af1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ef1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000df1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bf1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000800B4D000C00000000006FF5C900007f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ff1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000809040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000409040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c09040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000209040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a09040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000609040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000800B4D001C00000000006FC0BB00000000000000000000000000000000e09040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000109040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000909040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000509040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d09040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000309040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b09040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000709040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f09040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000800B4D000200000000006FE6E7000000000000000000000000000000000000000000000000000000000000089040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000889040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000489040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c89040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000289040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a89040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000689040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e89040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000189040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800B4D001200\n\t000000006F7EC80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000989040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000589040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d89040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000389040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b89040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000789040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f89040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000049040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000849040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000800B4D000A00000000006F589400000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000449040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c49040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000249040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a49040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000649040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e49040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000149040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000949040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000549040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000800B4D001A00000000006F6DE6000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d49040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000349040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b49040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000749040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f49040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cc9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000800B4D000600000000006F4BBA0000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000800B4D001600000000006F77\n\t5F00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fc9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000029040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000829040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000429040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c29040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000229040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a29040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000800B4D000E00000000006F510300000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000629040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e29040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000129040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000929040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000529040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d29040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000329040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b29040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000729040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000800B4D001E00000000006F6471000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f29040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aa9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800B4D00\n\t0100000000006F422D0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000da9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000069040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000800B4D001100000000006F88670000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000869040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000469040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c69040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000269040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a69040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000669040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e69040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000169040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000969040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000800B4D000900000000006FAE3B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000569040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d69040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000369040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b69040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000769040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f69040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000800B4D001900000000006F9B49000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ce9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000800B4D00050000000000\n\t6FBD150000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000be9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000019040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000819040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000419040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c19040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000219040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000800B4D001500000000006F81F00000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a19040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000619040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e19040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000119040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000919040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000519040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d19040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000319040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b19040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000800B4D000D00000000006FA7AC00000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000719040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f19040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000099040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000899040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000499040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c99040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000299040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a99040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000699040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000800B\n\t4D001D00000000006F92DE000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e99040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000199040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000999040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000599040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d99040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000399040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b99040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000799040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f99040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6FB482000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000059040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000800B4D0003000000000000859040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000459040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c59040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000259040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a59040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000659040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e59040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000159040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000959040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000800B4D001300000000006F2CAD000000000000000000000000559040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d59040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000359040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b59040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000759040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f59040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000800B4D000B00000000006F0AF10000000000000000000000000000000000000000000000000000cd9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ad9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ed9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dd9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (EFF7FBFDFEFF\n\t7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7\n\tFBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7F\n\tBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FB\n\tFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFE00800B\n\t4D001B00000000006F3F83000000000000000000000000000000000000000000000000000000000000000000000000000000003d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF7FBFDFEFF7\n\tFBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7F\n\tBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FB\n\tFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBF\n\tDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFD\n\tFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDF00bd9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F7FBFDFEFF7F\n\tBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FB\n\tFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBF\n\tDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFD\n\tFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDF\n\tEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFE007d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (7FBFDFEFF7FB\n\tFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBF\n\tDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFD\n\tFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDF\n\tEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFE\n\tFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEF00fd9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FBFDFEFF7FBF\n\tDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFD\n\tFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDF\n\tEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFE\n\tFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEF\n\tF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF00039040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (BFDFEFF7FBFD\n\tFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDF\n\tEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFE\n\tFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEF\n\tF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF\n\t7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF700839040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0CF2ED55BE95\n\tEDA3D2A914A83316954AE440695A0760104FEC006B003E386E1D01C3F532A956AA4084940507A83824081D205805810BCC7E\n\t0C679C1E6001BB3060EA7594DF48030004E4200C114844E11024283B040FDBAFF3A3FD4C0015BC428C021379A60821838663\n\t914901A44E04374883A7731104A645018449248A0800066CA11C46754211C8E41203C94421128054004DA21941D0612DF688\n\t42048201326B9120581E2E86AA244A0D84004038006FC0C020C2060E955203532018C8001A0659C1C6192084FF499902A626\n\tA9055CAB792B01430579CD9E00603FDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7F00439040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000F001820100800000000000000000C06030180C06030000804000080\n\t40000000000000180BA61084384236AA1D2A5272017CEE222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE\n\t222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE222EC22D86C361B0723\n\t91C8E48D46A351A271389C4ED86C361B072391C8E48D46A351A271389C4ED86C361B072391C8E48D46A351A271389C4ED86C\n\t361B072391C8E48D46A351A271389C4E207F83DE0FF201552AAA150000000001540AAA0500000002024102A4310C1D8C159900c39040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000239040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001002000806\n\t028006004000810000000186001833018301800C18CC6000180C060000060C1C000000300000000C0603000A801001800006\n\t000060000001400C0000C0000618000000000018000000000000180C00000000000000180C06000000001800000000003603\n\t00600000000000300001800000000000000000000C0000000000600040000000000000000000000000100007182018C81000\n\t078C0018C1E0380008140037838000E2000804488000000000180000000000018000800B4D000700000000006FAD97000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a39040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C10231808F60\n\t00184081E230000318008188000230003047A3180080623006C061820600011B0180081800004C004000788C0000C6002062\n\t00008C003C180081800046C00002180080000C00300100D8008180C0040C4000060020003000231800118000188D80000400\n\t046006008C6602062300003040C004801808860200000180000600060881C0014080043E8100004000060C00200040A00000\n\t00036602000000630840830000C00CA660CC660060000600001B0840C01000000005402C00000002018321028DC6E35000DC\n\t0001C3811803418CD80000000186000000000001000000CC79821F83C1000018000000000CC660004000600F11E00000010000639040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000300000180\n\t00600001BC000000003040000602000C00103180006000110080000000000008040280003000800000180300002000081008\n\t004800000100205000000AC07800180001800000C000000030103000608100280000000001C0000001800C0400000CC18031\n\t062301A00003001800000000001840001800000218020002301A0006000000C00C2000006488418A000800120C00000020DE\n\t000060C0000001A200000003C0600C06030180E1D338708F66021F83851A0D06834180DD080470CD1CF31C38C70E31C239C6\n\t2C0000066301020C46C0600206080000C004001E3206002062300003040C004C0618206030010311800018218008003F010000e39040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4301980C010C\n\tC46000000066000400000C0400004000000006000018006038180018000002007003000C0180C41801548F0600000000000D\n\t8603600301000000C000B80000198C058000548E0600000000720860C0400000030100000480000084002000000000040080\n\t0030000060006000000300000C1CE004000000000001802C00000000300000000C1800180000180C50AA0000000000000040\n\tA005B00000C6000018000008018000700000000600000C0000F000000003C00000000100001830000000183064204000C000\n\t001820002000000100E0000060000030000C000020000E60001000000200000850220442044201100040201C40800301800300139040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02C600018009\n\t040C0120860C0010086020700010088710000000000000000000000000000000000000200000400000000700000080002800\n\t00801200400041000403C500A040A0180000002118218000002006000000086080060300008000000000600C000001800000\n\t0C06000000C000000603060C0000000000000000000000000000003800020000005030180C6008000000003000000000C000\n\t00000000E000008100060000063018000000C10000040001820180201A000033010218008000080000018C0048C100000008\n\t118000002003010000000C000020130040006600010C81008000C00600C003005B0C600C0000010030603186300600D0000000939040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (319800003001\n\t80000001800018000600000331980C0600000000000000000000000000600000000600000000003060800100000000000066\n\t300500000E34000C1C0860000060C41A0904000000060C00000C10000600806FE040C01030000004008000E0000260330000\n\t0000C06600002000000000CC00B07938C000C0008004001980000001800C000004000000A07801000C0000C1800018200000\n\t1F081000F000004400000E00682442200630018F0560200000040A0003000880000100821400100884408C18804000000025\n\t00005430000201032002000080450C8000010001400A14000700200000040000000100A540C0000010300000C0033004001800539040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1FE576727DEA\n\t2538124A24252109280C2218004117CBFDE03F2924928106000400051A140800B103C47E0467941FA010AB3120A65700DD6E\n\t81101416B9040405E2948B1080BE0D28C008A010A044880032100201002810881028540A2320318680050F000831D00196E0\n\t65001864824AE416971A2CC4EF764200240E49200562D1088D361054199AE0C3000C10A004998C82760048943941A25FA916\n\t6A6D14424004080001C02042371E34CC4BC0C0B9C4F216219840A119B004CF38060000007B10DCFC69BDC9E20559AC4E1164\n\t88000000000000000000000300000060330180000000603186000180D80C00000000C000001060000000000000000000000000d39040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000C00B921D61A25AE832D85C0E436625830920C209B4566135888D24A201000000000001F89E15AE1046B\n\t783845AB4653010E876921DA42D3C0B4F0D243B490E78169E05A876921DA42D3C0B4F0D243B490E78169E05A876921DA42D3\n\tC0B4F0D243B490E78169E05A876921DA42D3C0B4F0D243B490E78169E05A0055155FE0055155FE0055155FE0055155FEAA00\n\t3FCAAAA003FCAAAA003FCAAAA003FCAA557F80154557F80154557F80154557F80154FF2AAA800FF2AAA800FF2AAA800FF2AA\n\tA80008392484027048000000000000000000000000000A880552AA09AA543118874897429086577EB7DE8DF7F3FDDEFC6B8C00339040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b39040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000140012\n\t20000201200010090003D00900580004086000C083C202486600000218000060017800001CD3C9C4E22020C819A092418592\n\t30EA03400D54C0C60081C6085018D86983F80C00A431284CE621B215320804341446E502C0D80011018000618049604A1523\n\t4100040204D8AB001D08A4831A1C1200000007803041A87027138E400000010110040103040000000000800402000E040200\n\t60801000D00000080000000009CE472538000000800B4D001700000000006F6E9C0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000739040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (158000000000\n\t204AC205041000000020208240000024801001000000000008068224100B00000560000000000812A890000002C004000000\n\t100501122848200000136000008000000000000E444BA02E02002C0120000008000000000809E44000440004020000200001\n\t480800001000000000461001200000000260101C482000000000000080000781000392241000510088203000000000203200\n\t080412804000140F008C3040000001000000000008018E2833A00000020001008022000048040A0000AA13039004E1F8B174\n\t8F31804A2070100000BA472815029033D5820C50BC404994CB80001B52AA0040420A005A9438B4C0A00400004C270103006000f39040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60218ACC043C\n\t01C91080252230410100071100C042C05100480000822456045484104ED48801E00366311B89A320000001018100008450C5\n\t1003710081C8A66AA01E222620190210118026013A0A4D0EA1E84100F80100000000000840800400018207F02054004F2710\n\t0005B124082C100080000040C0A4721112808803380C0021083048804180B800000000058434D001B81478049009C4E08000\n\t00000000000000000002000C0040000000000000000001000000000010208408210021040838088542002008048040000400\n\t000081C88914200400000020000000081488841000002000000100000001005044AA000000002112080000100900402C0000000b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (899CE8005B30\n\t000000000003F190CC000C000C078081206D80C0062000018460240000041C184E1148C8040C4700C060000001E0C00030C0\n\t080410240000040814E074C0D0D20A0200018C30483CB8000F00190000003012CA6888000C206BF85EC0422CC1001002C100\n\t800100000001809D1800000D0383005344E040420342E4416040020020080287139249900021001A2110C044660669900263\n\tD18019A67B099E12400108A056340E0C00E0D14028221C018446A5C08244400500A31827402008000952008623023A0C8EE0\n\t3E005022368900E6100132C3208440C1C6080104198250000060A90209508000028122860902800741010048442129028D26008b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (014007000081\n\t61342005BA0C3EB103AC826B003ACC2680D7A031EBC086FD190B07CF14180C0A2C0A00C20504984000046A090088000105D6\n\t02501C964000700118CA108214072110000602142EC78034084D84705D3841EB836AEDE6487C00DDC8B540285C327C00100F\n\t33000C6402048E080002301400204880C2004202A130E84830000004896018910890080C1081A402801630000004000D2021\n\t1029006D8662E9800473009700015004002A40201001266001E01C652800808002E84000012E410806008C0020782A024004\n\t822C1CF045A080280610300080640891420112294AC90809C42020416114A2348C828820020114AA042B81C00000E04CDC00004b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8488160A2510\n\tE84820DD832470050C801E0541E000C0005C1C040813ACB703801E203E000867239088540000000000008100002152080040\n\t800134180C1218D44942D30080034C0312C002818DE460280D89AD300200640040AA9007047A8854C80E8280000000887A28\n\t10A09F02816009C215550180CBE5122902AD0034100000920C12A830A6952533D004002C650888272421E082100208004CC0\n\t00058422010A400F0380C406000032158001809C840C003481A000031980010610418C00103580C0760C000E065831980008\n\t2A06ABC000C8024020028402004009284542000201000380E42201A002088002A0008050208C08050100002000000000004000cb9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9C5572880A03\n\t966BFDD43F3B914BAF12E81DEE552A17C8ADD2A98D348D4B8D5765559955EA456204DFA443A330E01D0EB54E27168914AE47\n\t399310A330AB38A8C40BBC50EF11A319FEDC21BF5A6CF629843C8D3A8F4BE7402B7DA0757B914E25D2E158BA7162B54A2C72\n\tE9702E550ABDCBA75389F5BA113E914B8113A974A854260D462F560854AAF422B44B86D20974AA1D3B954803520330E6511A\n\t914AA512A9508A453A0558A513F854AE572315400510E11CBEF33FBF41EDD2A84188004020042B21DA18E0EF169B0F40E130\n\t3C402201101800D6402D7C216D0297EB62600D6203020006C0000001900005AE518D93780C10C0180A010007438870A51134002b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010018080000\n\t0000000000000000000000000000000000000000000000000000000000040C728854AA510B9DCB871239740C002AAA9FEFF5\n\t51540055003FD54AA7F800AAAA7F800AA55003FD54FF5515400002AAA9FEFF5515400002AAA9FEAA7F800AA55003FD545500\n\t3FD54AA7F800AA002AAA9FEFF551540000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000143FB5546021E0000000402A\n\t8540040001000040208540000954685619BD53ED43EB09AE5C7997DFA4F3ABF0DEFE299D5E2577293C1A537695066552615400ab9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6001512C8418\n\t01620C289045C14720F06006020018003060017802041CCACA92128424C85B8CCD2B25293D0CC3198F8D64C7C201962000AA\n\tD86A31F80D1E933489932A0148E85C23080AC10CE510C1188404001020E5D8103A00420904EC01B02D4E36783C0703259BE8\n\t1CD86C361780B181F5E05555110103425905487406050009C00000C0E10181002C300209A4C81D3151831402351A8D16BFDE\n\t05F150000000800B4D000F00000000006FD17C00000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eb9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F8C026840080\n\t19A05012C04600660006076098505013602C446001F800C03328B004001060EC04B001800EC10028B4B8C060135060266220\n\t003F00231DA040A030060C660D070C0468016003603609E402081D020067839800D401B488017601040006C3608E82001600\n\t61011A840C031800184D800300764401800280039B00000020000860B40170023323B0494805005CA621220F958010994006\n\t4064361B0780000C4A511510D002C200119E032011C901010008201807095601F19815DE076793D8E4C00361B01C28849408\n\t1043C19C5C639EC6851288959010290806A9C638740E3C798CC06002001156500003186D86C36100000A3301800098049888001b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (230205310009\n\t00004282084012EB14020B0788188FF03801E0032633DE80066130600305990C6832B0C0C8000D00D0256660510832671005\n\t650003C024136603110C00EBC030C72118CC663718C01E4B1189498B25921150405410808F01F12C980410301B04B138349C\n\t000291898006780440031FB0D9C1F180F1A0D86C02CA2871D3B432547304C00A9211C558C46408000C0301800032300CC90A\n\t10780C36070B88C8426101AC604B5110D424F508C096060001446300003C1AB0518059800462B408145000180001F879800D\n\t403B488810000D98F4000FC2CC006800EC110A160003F0000D02355800CE013140CD80B1118007E00300CCA2F00884CE8011009b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3D88244E2009\n\t81A1404DC0C126100000007824000F061404A840D0C5060E7903C86633183DE8700804C9E4010024800C06290201A1C0F1D6\n\t40121F89A6B01B3CF82B0E9808E8C601C480C418B41B0C047B3826407810402100E8D0200060361B0D81801D180C001D0B8F\n\t060348E2791A9B44E54231858400210305859529280200203754A596D014E0C72B930B4FA38011EE632CBC0F4C17A9280674\n\t2E1C1881F7FB00241D6B855689D290D4184A1997DA2294A2091A431FAC0647063BDCA6E9593000AC37AB856A58178AC604D2\n\tF8E5EA00020C0980300020200F0403C088346A342A13000001C741A9446A55291D568D4668658ACD04BCC98152A1142A304F005b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5D8CD5E335D8\n\tC53E31CF8C73E1C18EFC081D186634180CE60D0E004A0D17B8C40A547A1F49821011058E007E3C1E830071003EC32183DF8F\n\t01E3406E04040D5FE01618CD80704E34C1E3C0384DA6C07800D1EC57E0C09C306C8E006D340B04600C01BF000000403C2012\n\t1980464242003DF8D02030418221990C1A300880D90DC0010D0280023C086630180C86110804880FC660CCE0C7668C026CC0\n\t080DE0000030C801022340E8DC200C40804060CC0600008CC00006A10C78007A88060CC1820C18D06680006C0200311A0D60\n\t02C603110A2400CC5814000E20683D1202060C41835401C482010A28406D86C2C15628082A0A084198F000633188C1A2B19800db9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (063F5A3548E0\n\t37CB2198FC1C0887A333833170283E000E2A5050140260000D86C4F0103C400012000000001810080454010428C1E14CC6CD\n\t180307E4C28B8580E0603F19EF30018018000202020310D84066D8260006836690EC18300002C68044481440200103000340\n\t0341800F003F4027068814200019BC8083378B00842F6718882512000482596A2852ECC00005A8A40598082547A0DD064031\n\tB0C600058140180C010C01E0000315983D1630C18C40437580CC663CCA0E061831D832180C06C3F069C018006008DE0700F1\n\tDC78DD0E00060B000171E08F00934201C00201A000108049A00009C04000680105047081818607461000E1162319D8CD5E33003b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (402000A804A8\n\t4420114881500114004000150004000100A2440A9548A402A044221008944A251229140855021542254228508A4528954A25\n\t422910A851089048A45288548A540A954A8052A940AA5122844AA540A944A245288448A152A054AA1528950AA512A9102215\n\t2281022112215488450A854AA440A9548805008502A010A9502A142A814A80120044A21502954825502110A0500A914A2550\n\tA9540A452A800A21402900024000800A8552A0500060001843018BE1E0F51EB31E02C060142423010C0DABD6780D121B108C\n\t1E6886E00C62130620012603198C0EC019BCC40F347800A0940FBB4002078BCC9E715D90C68E3782355A4C678005EE779BCC00bb9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000408A0108840021528850A2042A00400553FCAA557FAA800AA00155FEFF2A80154FF2A\n\t80154AA00155FE557FAA80000553FCAA557FAA80000553FCAAFF2A80154AA00155FEAA00155FEFF2A8015400553FCAA557FA\n\tA800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000028550A940AA010000000000000000000005000140000000002A1\n\t00AA012A954A85520954A0002800480140014002500A804A8152014020000201082412090408140A0140A050001400042200007b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000180C0000000000000000000000fb9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0800800C0883\n\t40000000007856040D1FAAF150400AF96628C00000A8384082109E504EF7708DE6885004D86025786C04C2762705E2013040\n\t0E0801028442E5A1F8783251331F62E19100F082410B100A81004014B810950CE72010CD9A00551541803043B0E2AA551DC0\n\t4290580828C00600002C000000A03000004080160300004800320180100280B4F507AA814552A8018000800B4D001F000000\n\t00006F3B7A000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000079040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000D8D54995C\n\t1C1300008620000001520E04BD0000310040060000240D4912001400E0000080200101C0000C0016C2A842BA18100E100402\n\t0000000D8000581548478728114400000300003481A8081041010004C002A8822210101601000A8004290090160550004000\n\t0C048E52840001400012200002241702000019200001E30100502CB0021C530CA11A0100E2042A8AAFF01001F4A57F10CC82\n\t00002D9C4507900881301B38081B018C080404214880010102020A102955FEC41180862D0002094602401B84000440110093\n\t450B074C01805050140A300001000811FC5F04800A6FF002A982402A220086000008380C201402001419006ED1080408042000879040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20021002800E\n\t01000281800327130800003888344D07805500A0600812024180110060100504520000154022600104882300118000000180\n\t2441159FAEF208600C490980000334580028807C9FC88210181044800CAC0AA490980002E44A80044E800000280005800661\n\t11A00D40557F820B0DB010813E046180080FA3FA442820181A8764C602A0421D10800F0B2078500415019908007182A068C9\n\t4123120C941860840658300A4000600018006000860002DB95085727300C000000B00003480A808902000C60400002058000\n\t0240D413010C4000C20028203040000C8010688C00031880008005482812D419030AE11110A006254180C60040210180001000479040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000600800\n\t1300381FEC2678DC860C6701C66A82B0C5E0202220C100010008001000AA0BC9A020C0808004A2800004008C08032E290842\n\t415000005001230AA00600441200401800A8B00004080E002A8AAFF3A03C80452AA542C50400181420000018000261058000\n\t0081000A9751FD8A082010CA0004284102A250000189542185406905028B807001AC02800123540422D2000C825010000000\n\t006018481018430D4412C8B4410AA812488512806068041094001000C41E00182A40E202004188020204008C008820000508\n\t00400B32D215A2061200080514212428450808100441325000220400884000212180822C29820700090108814A82C948100100c79040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00CC00344000\n\t0018A0000C00000140000001140200001003207800A8080C17CE81006A011C7C00814105F0A0200630460D01820200108410\n\t400C0180409010181A0600C06D02C0087A756E380400C000000470158D400F12023C2081000040010100208EC860800C0000\n\t00043C004E88000E40080098400230020A82100C44001002804C1260C4080462800380021000003202000800000290680C01\n\t0500008000C40800210C400001410C00046504000000A10C08C04201082400013140CA6202400900010860DC4002880A5410\n\t218200000D8000010B000008602EC9600552C51600002A014510010918567E80C00283808C22200E28180801508D80D006A800279040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8402E8003415\n\t1E00108EA7F85426F00820054C50103028405000006080580000005420848800017026590F80028C408935C050208C058C30\n\t0185420053B30400004080660810041066A288601C200032060084D01540A319081440208000500008B28000001800000100\n\t0000000000411426271888251002800A0C21884248008844E43C058DC8640208558CB02B0E42430401795214008005811089\n\t04823006B1028C00214000640614C2240098401835002C02031228C0181021004800061940280011001A21000020BE4540A0\n\t0000C0031C10001608400011E02040C914001728060020000004000660040000180C06030180C06030180C660019800060C000a79040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C87C0819C307\n\t10CC40070602906C200210263000005C6E30993C0C4C7F310003200020884120840025100301D07470A8D82CA6784C1C8B44\n\t0401CC000239600250008C6F97C38002A347830000E0B2307E731F175E0E37196400016511870335710006B8460CC6E37070\n\tF9E6C040105C849202D8322C402009A60018002493181045CD005A109C881A0089CD25202442842602400310600800A25522\n\t094E06E09048000020008281020804440000040181800400B411048EA0A068ACD0205180D90E80200022C30100050A82B3F5\n\t9600000C410C0469288C30402DC180260174E04002101280460165884E0600920680A80440047A0208C0000004801C20280000679040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000400A530801380418302030018366498D389C31B246CC91B270C6634E0D992634E0D992C91B270C69C31B246C36649\n\t8D389C31B246C366498D38634E0D992C91B270C6C91B270C6634E0D992366498D389C31B246C000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000142AB54A6553E944AAA2150000000001502AA815000000000224082E00091689068108400850B291\n\t60A24AA194AA4129D463254128D4925809054494592896825A020402D42AA9782A6820DEED3608E1428D20360908B250C9FE00e79040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000200180000000000000000000000000000000000000000000000000000179040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2E1545A2AA94\n\t10FE6680400005BB31E000003EDD4EF6603DE6000008DE6101B83C10B07D8F01E0000000180000000000C501FC580000031F\n\t63D18300C80000020000000080D239002205430658CC1C00000001883000A060000000006006480148C00600026800000146\n\t2300004180107B1000C4001300022040000000783FDFEFF7F8008000800B4D000080000000006F8DED000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000979040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000028002B08\n\t000100000A400000000006003C10600000080001034000080000180000003C040600000280001015000000000080058018A0\n\t00000500000002C0003040000000C00001023212001000000800000001900000000000060004801804001B00000064000000\n\t36420006120000800F06E05C0E00063E490C20820002800500000000100800000000906100002104C2011C4901F1833C783B\n\t000A9000000021060900000000040000002004004F6300208018000020000442202000116008C24000000040000430800006\n\t882406001C00126AA2A9558002102804020090291044412018008618080600180A1000021041002004020600000001F8280600579040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080004082020\n\tC40180000001D800080000800003C000000000001000200660000000000019800000000000100000064798F01ECB19800383\n\t10180000000000060000100000000980000C81800000086000C008000001E0000380000001E01404000002028D706080984D\n\t40800000000270D20C040911094183B0003F1000C3081040281402010F48035162EC18EB40031060451021040231A54A6100\n\t401C0A402000020000028000004DA0020000401000020020000B0408006010000000800010018003003FC020400021E01F00\n\t00080031D8DC0002280000800000E000FC0B81080010407006B041804200002B00800100000004001000562700004A00006000d79040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (840C3822C060\n\t000071FC107C0CCAE40083CD80280380000C0180F1A48006000001001B3C10336E0009800000000030118000000400884400\n\t40000001C0183410CC1000000007E23D80090000000F00001000180800080002391000002913000040000000070030C00000\n\t000000000011410500400000C3060000C01003A406000000C00007800008003010000000187040400880000400080000001E\n\t100800C00000028008210004100344280C08004000000041804300044084008050220F080200800002018003000000000120\n\t04400108940000400150000006004C08002121000069110200001800800000010180100320061007800E010000018083061300379040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000730C580D0100060C0070809800000C06400600000630020D01820000000030600C0180C00001000C0000C06F80\n\t00005CB26400000C0000C00040038C002400403D00F0000000000000301EFC418007820003307C001980812E401A0040C006\n\t30000007800C00201400000CF660CC000067800780061800003306001800000000780C018F0000C000CC1800618CC0030000\n\t0C000C600C000001E30C18C06603006C00003000806380400100000000C0000018000020108230060CC000001B0000006000\n\t40000000CC24020000000F0002011800000A034027B30C5C201A0010000000CDE0D267B300200063CC002C00800002A300F500b79040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200000000410\n\t003C788020000020C0600000000000038800000C0200040200208008C1A030000C018C3000C08000780000000000E0400000\n\t0000000000EC1A001002068080000000C01180000001C0040000003800000010080007000040800008000028412888262000\n\t001A00003418A80180CDFC7C058700000000018400000D0603101001F03C6183018331990DE631063F17E80063C180CC043C\n\tC60F0190C4183F000406023078C018006000C60000000000000000100300004800000610000040013C00001E00C00001E000\n\t60C0180C07E8060000600066000663326000180C06030180C06030180C660019800063C000CC02301000461800000C20000000779040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100311E63200\n\t0BC062321B31780C10001100210928108010009100314229103C0008DC0C6463805C470D00940000518080823420940CB621\n\t31421046095C4426728066F81931C6603798CCA6036BB351033112080008400000000210C990384120C083021209F0205C89\n\t898080181124731132C7A3247AB19A0A4A08C84F25181D76A0602300080160084AF11FB389EF01F161600040000080000000\n\t000019800000000030203D01800442E0322D8000008048000000000003000002202000010000000C800C00780198301DA980\n\t800602A154A01C30020047811088C404030007B7D208000858221060000000000C0420044000003160001E0000800003004200f79040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1020C0002240\n\t800087169E1A4786921C5AD23C0B50E2D43B48F02D43B48F0D23C0B50E786921C5A87169E1A4786921C5A87169E1A42D43B4\n\t8F0D23C0B50ED23C0B50E2D43B48F087169E1A4786921C5A0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C64A252\n\t09C040000000000000000200000000000A080550AA9C3898082BC78BC7930060DC7813D988F033F19EFC1195DE6936383DFC\n\t83680807E48069241AAA6A0604235613FDB83F0D0290892600E1DA483423088051434DFE4C7E0C19E30798CC60A04609946C000f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000300180000000000000000000000000000000000000000000000000000000000000000060085902116B2008f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (31E000003058\n\t0DF6602DC6400A0CDE6301E0300030798703E000000008C001800000D603FC780000031E63D183009E000000000000000826\n\t3C0100000300600C080000000180300000600000000060043008488000000664000300C61000000180327B0C80E200011DCB\n\t3018000000603FDFEFF7F8000000800B4D001080000000006FFED90000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180026003C18\n\t30000058002080C000040000000000003C06031800018000183D800000000040078039E200000F000000038000306D031600\n\t40000086311A001803009800000301B0C00000000002000780180C001B0000006000000032000002100000814F0680D06800\n\t46304C0C0092000280020000000000080000000048E30000110A851501480020813848116080900000000186010000000004\n\t02A954C400809CE140608000000000000442200000002A0F056000000180000610C00C04002154AA0D000A6552A95406C000\n\t320101019009088C001008AC840000428C0014082020A8108808040204000000009804001D0AC552A8940CFE6600C00103FB00cf9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180001800000\n\tC00008004000000040C600000000000018E000000100080000000540801002C500800182001000000000001E600008000003\n\t1980000C40000006006000C00C30000006C00003000C01E02C00000001970F306080188E002000000001F020040205000040\n\t815000346E00DD0730783C1E0F0785D80050E1DC38F72082084084108010CD01B0006100600006C060000600000080000017\n\tB0060000003000000004000F06180000300002018000100080030033C0608000F1E00F2000180011F87C0001780000800000\n\t4000FC0983000010604006F060008600005B018003000000080010007E2F00001E000000000024000F18002100001E800000002f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C80182895036\n\t0600000C0162E9E6000400000001122804A36600150020000000B011000000200000200040000002C0000816CE0000000007\n\tA03D00090000000F100020002408000800044A2C508A50230000800000402B0130C0000000000000002A800A001000008200\n\t0403086003180600000200000780011000502000000010A024805180400C00080000301E20110060000060000030000C0000\n\tA8300C100090000002800003180A85480562A1540F50300D000000000000000200000140084002112800008002A040000402\n\t90040042108000302214009010010000000A0180A0033006A007801E0300000180030623104000100140E81800000040780000af9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (281800060C00\n\t78019800000C06000600000630060F0180000000003060040180C18001800C0600C06FC000007EF366080100000000000001\n\t8C000C00203C44F2000000020000100E3C6180078000033060001980000000180100C00600000003800C00100800000CF660\n\tCC0000678007800618000033060018000000007800018F0000C000CC1800618CC00300000C000C600C000001E30C18006603\n\t006C00000000406580800100690420C4000019803020108210020C5800001901980C618CC0600000CC66000600000F000000\n\t18000000060437FA0C16231400100002028980F047AA0080006A894431020000000600FD060E7032C0600000A1B0137008D8006f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (402800001000\n\t80078C00000402000680C06CF008D19830000C01803000F08000783300000000C06600000000000000D01820100186008000\n\t0000C01980000001800C000000300000000800000F0000C1800018000020070888243000001A00000F00E20502A95E78038F\n\t00002002010002000C040A100000E0AC6503180AA5530D64A0603E05E32142819488002E850BE1008000EA450CC400205001\n\t500B6600C7800000000600000011830000C000004632806A60413400001E00460001E00140CC100C836C0610006000740006\n\t0AA34000000C00030000C00030000C600018000003C000C002300000461800000C20000000000030000000000060006A286800ef9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AA303A313A1\n\t11A84E498C42EF13E331A8DC31944A645229046A452B04CBAF006B75E0C56E115A6552A250AE532296CE6457E9702A570ABE\n\t4A65130BDCA6312E915E8112E9DC6E54270F47A3D26854AEDC22B44B81501974BA1D2F97C049700130E2511B934AAD36A950\n\t8865680D40A516E875BA3526B5C00F31A114FEF32FB5C1E572A8B0380060000180000000000019800000000000203D010408\n\t81C0201C80000180D80C0000000043000006600000010008000C000C00780118300923008006000C10300810020046811088\n\t4404010001121000000018000000000008000C40200540000011A0081E00000000030046E000000008E01818300000000060001f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (198CC6361B0D\n\t86C9C4E27138361B0D86C9C4E27138C964B2592633198CC69C4E27138361B0D86C633198CC6C964B2592633198CC6C964B25\n\t929C4E27138361B0D86C00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000343FB5546021E0200008402A854000000900\n\t02402085400009D5E8D4181542A542B9002A7479A7DAE4F2ABF0FEFF29975E2E77A83C0A413294022D4233540C5D36800A81\n\tB65BFDCE3F7BB34FAC10F834E077261DC0E560EB855485328552A55489982ACF62044E24C2E1F1A01D0BB7CA25138B14FAC7009f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000201F8000000\n\t000000000000000000000000000000000000000000000542A954AA552A8004D2985CEA511FB74B87106B5C18C964B2592633005f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (DE6301E03000\n\t30798F07E000000018C001800000F603FC780000031E63F183019E0000000000000000063C0000000300000C0000000001C0\n\t300000600000000060004008100C04000660000000420200008180006B1000C0000101833000000000603FDFEFF7F8000000\n\t800B4D000880000000006F021B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000df9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800000800\n\t00003C06071000038000102D0000000000800780216400000B0000000200003040020000C000000632100008020008000002\n\t01B0C00000000004000280180C001B000000600000003442000422002001EF0740E874024630940C01120004800400000000\n\t00080000000091610100AC940A600290002103385033618C000000000186030020000000000000C000009867006000100000\n\t0001000000280000000C0404008051801426840A2D51002800001C00146AA552A806C008300002019001100C000210AC8000\n\t0044880010902200A0110800000100000000009800000C150AA5502864F56780C00307FB31E0000030D80FF6603DE6C01E0C003f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00C700000000\n\t000019E0000001800C0000000200000000C800000183001800000000001E6000180000031980000CA0100106006000C00C30\n\t000046C00103000C01E00C00000002960F306080180C010000000002F04004020A00008102A0203B5400D10A3070381C0E07\n\t0F9000F1C3A8709A41831060C618C0180200B018600060300E806000C400000300000067801E000000F000000030000F0600\n\t0C00F00000078000000000010033C040000041E01E0000000011787C00005800000000006000EC0D82100010006004F06100\n\t40000038018002100000080008005E1F000096000040000018001F180011000016800000100016003D1870000098001101C000bf9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C00600000300\n\t0000000366000000004000003001800000000000000000000002C2004816CC0000000007E03C800E0000000F000000000000\n\t00000010004C00000003000000000000030180C00084000010000030C10300400000C3040C0609C003700600000280000780\n\t0000001020000000302020010180800C00100000301E00000080000040000024000800000080080000000000000000831810\n\t0000006000000F00301800000300000300030000000000000000300000000000000000000000000000000060000020000000\n\t000000000180000300060007801E0300000180030603000000000000C01800000200280008000080000040000000F8003000007f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000063006\n\t0F018000000800B0602C0182C18001800C1600C16FC000007EF366000000000200000001AC000C00003C00F0000000000400\n\t301E3C6180078000033060001980000000180000C00600000007800D00301800000CF660CD00006780078006180800330620\n\t18020000007800018F0100C000CC1800618CC00304400C000C710C000001E30C18006603006C00000000C06780C203107B0C\n\t60CC080019803060318630060CD880001B11BA0D619DC0E00001CCEE000600100F00000018000000020037F80C6611100008\n\t000040C180F3078C00C0C0680C003D020000000600FD860E6033C0600000C1A0216000CD8C00800C003C0200000C0060C1E600ff9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0B00C2ACF409\n\t619850200D09A132A8F48000781300000100C0260040000000000064183008B24600C0000002C01980000201800C00080030\n\t0000000800000F0000C1800018000020030888241000001A0420A750A00000001E50048300000000000000000F0000100000\n\t780C2001180000030C2000603401A00000218000000C000300000000C0000CC00000000000036600CFC00209402E45021551\n\tA30140C000000630006040033C00001E00C60001E00000C0000C0060060000600000000600060000000C00030000C0003000\n\t0C600018000003C000C004300000A61800000C1000000000003000000000006200600000001000060C10F0011800000C040000005040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (422950A05128\n\t9448A45288540A5508954A0052A940825420944AA542A144A2450A9448A112A054AA150A940A251221402255229502255288\n\t40A8450A84422400A954A801009408A012A95428042A814A80102100821102854824508014A25008814A25402950A8042280\n\t0A21400854021002800A05528150006000018000020040021980000000400060BF018C1983C0603DE6200180D80C01000000\n\tC300000660000000100C000C000C20780018301803008006000C003018300600E7833198CC00000000000000000018000000\n\t006000000C0600000000000080001E00010000030066700000000C70081C38006000002040380000000000078C00000D020000805040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (349A4D269349\n\tA4D269349A4D269349A48743A1D0E8743A1D0E8743A1D0E8743A1D0E2D168B45A2D168B45A2D168B45A2D168B45A00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000020550A940AA010000000000000000000004000100000000002A000AA102A950A\n\t85120840A8000001480450010000502A80480052015022500205402440091028400A00420050005000440294402400A01028\n\t5420004885528954881008104005108840AA440A9448A00200442A0028144A251029048A55221102211229108A5108914A2100405040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000201F80000000000000000000000000000000000\n\t00000000000000000000000000000004008110A944221520010220428810783C1E0F0783C1E0F0783C1E0F0783C1E0F0D26900c05040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A6C24A55365\n\t92A1A4B4112D918485915998CA4932A68D8D549244B26538AA1549932A592A000000172520E2A954552A954C4823C9B94C4E\n\t5CA592C4254328B65E52AD8B2E52F9ED2C6A0D2A5D4AA05800000048154AA552AAA8D400800B4D001880000000006F81CC00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000205040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C21149E4908A\n\t13000F25632AE5328752390422913240CE65491ECA49A00000D2965310520EE4F155EAD64B11C4C00420492264553552E656\n\t8968D06933198C2995310D74E930394C46F33265B29B332993069149ED74691D00000007EAB4AA552A9B94C933D3E4F2797D\n\t2A4F4AA2F1E9CC9972A64942D598288AA97238D96AC4800000662CA78AA550D06D4AAE159111C552AAAD74192BA55CA2D65A\n\t09D4963CA78B2D530BE8AA55749544C0000000D26A4B198CC9A4D2A54A66352BCA06A351A952A56F0AD58BD2124964A65329\n\t8B4FC53AA8D4AA2B1A4AA552AA95F4A608954F21A2A964B2C548AA4AA1A48AD1246C2A1492499350690E992C954AA520AA5D00a05040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (961280000644\n\tD299D27914BAD4C9932A5554662A954CE0A529654C974D098007916BADD2564A9654C6B331592EED6C97888C452994140000\n\t364AE5A4AA4CAA1554BB8CC552A96534255319948A74F99CBCE532A78AC9E7CBA5D2E974AA4FCEA73A65CE594F1E53C794F3\n\t9CF2F62DA55329A5B3A4F24825079246201240CE554B1B9348752390422913240CE6534879249243A91C82114898809E2A95\n\t83CA44C390CAE520A28925E4B39842294CA1D486801390AA9972950841E5239132653487926A43C920941E4928812402F155\n\t2CE6108A53287521A004E42A964D41E49248F24845098805E4AA95E89A038A4D21E492490EA43400920672A9995A7948249C00605040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (7752C880654F\n\t0A400594A9993C69251654A9921264AE7A13000000033198D8762AA552C5945168B4464B294CA66128A57CFF2B19958592A9\n\t54EA725290816B52822D682C059C56C105B8B016495B04124640595052964B2D558AC28229B4960C9652C964CA55363A648B\n\t596421689000394A2883CB71602DB2424919016690593124B700155EA8E363416C4E393756E3B6EB65BAA574394EA2600180\n\tB2A93B258D455491A12C64249594C5233018EA662B1704C5949894B296252999CAD2491108692AAC5329C4819452EA52AA0C\n\tADF15A916C5E3D16CF6EA3229994713903800F432954CC552C958AA652CA58B2995B154AA5D5C95D2CA933198CE6A0FAC0D400e05040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2B36CD6B64AA\n\t44B2E67B268DA557E2AD3269532654E59333553466333A94AA6532694C9E4999C64A873A512CA433168CA265999CD4324CAA\n\t592A41312D3478132644E002C2A9B29B4B154D2962C225EAE712A592EE53490DB49942B54D07672024CC3832A643A662AA24\n\t4E962CA25129974980EC661D2602CE54A9A12C9133A18CA642B26000604A995149A569A534A62D1553C0952290D29A532A5C\n\tC5513110AA954B9552A00001A4AAA95F155AA6624A1932000020120BD32848A29E49168CAAA4F3A93C990C9454CA674969FE\n\tE552968AA554AA94D299239984C000024142DE23118C86A6D168FEE752958AA954AB9CB24A750012A593C8D9EECA2D024E8A00105040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A9752AAB3299\n\t96CB15FA5932DD7F16804000426552DA0D9E54CA62AAD4B6994C8D956BF4B365D4AF52A41540F28AA5ACA658B654CB16C898\n\t40A4239E9D49135155B6B21627152E76EB748A922CA5D7AD36AA6C4E270031134CE2A955D2C56E27992DD6E954E8ED64AC48\n\tEBB3903CBE52740791A5F2513092E06F96C3AA428099F49F2E0A4BCB51602D2E65531557A973E148AA954C98172565519812\n\t614CA9520614CB258A950494D22504B8253099389A4CCDD3AB2DF4C27D309F4C27D309F4C21D32C74CB5D191963A7D2F4D6E\n\tB3D0AD76625B1ED74F67DBE934AE7EAF97C563D175F67229154D29B5C898B0552C998A4554C8252C653329562A52DAECB6DA00905040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9513A752C874\n\tBA592AB24A23D1F9DDAEFD799FCAA612AB719ED567955FAF438155AA122B9CCBA362FB5498B42095C8AD621B3C7AF57B9D0A\n\t845223F5BAD73A85D8C8D2AB55E05002914AED40AA54B6153A11482767A894BA652D8547E516A914AAF433BE18E571AB05AA\n\t9626969CAAE55BFDF6572AB95D49A5F09D309534A48CC9A33298AA392C864EE567B26D324653218AA0200000B805449A5489\n\tB34994CCA84C9994C2A4D264CA9A4C985346749198CC6632A14C8592CA083299532650C984A324C828331C82A89551992AEA\n\t35AA8AE552AA55329A138010079752A54E6E3F2A952A674B9DCEA62B155326C5B3259C034B29D2A477F16D3C5A34898F29E200505040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60E48D139C9B\n\t0D83909D1A8D139C9B0D83909D1A2746B60E4726C2344E2746B60E4726C2344EBB5DAED76442211088EE773B9DC110884422\n\tBB5DAED76442211088EE773B9DC110884422BB5DAED76442211088EE773B9DC110884422BB5DAED76442211088EE773B9DC1\n\t108844220C2FBD546001F8000000402A83400400014000502003440000DC781D089DD1ADC1B9480ADB7B1BDF0470BBF4EEFD\n\t28B55E85B6B91C365246B5054957D254907544B80BA226C9FDF8DF2AB14AAF12F865EA5D2AB7D0AF53B9B8CA792D094DC553\n\t1265CA912BB902A516F9F1B8D513B7DEAF47810CFAD74BBB5CEBC4FBCC2A41239D9DAD25ABE5EE5C79970E6F329B488A0D2B00d05040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000E00D9C844F348BCD447351BCD42C050B08A22179089E0A17980926C21289C4E2713\n\t89C60416A17CFAD52F85DA042248DCB4D83909D1A8D139C9B0D83909D1A8D139C9B0726C2344E2746B60E4726C2344E2746B00305040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0B2003211E14\n\t48005280002089460A4105088304D0A0541108844ACA430144820000001201061A4098D02000070D100201EC3028001405A7\n\t7208C0812010902000904422111A8000000000010000800B4D000480000000006FCB6B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b05040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5826820AC072\n\t40D030801A2506A2022111AE38062184A503800020000422490442E0900E890890000CA03B8008124CA200C0704B10080248\n\t90C22844688CC6246E96062C621B4008922011088140305C00000004010344884D86C32204D8244182001872210CDA2542A9\n\t45245324104824412110888C719817E2D301941C140AA6428CD668440A62749B8161622844A2000000000406100406000000\n\t8924422111A4C41C23518313084C9CC862105C8846A210264E3A040820748890284D261314845000458A1406240060000100\n\t08181180808345F381E40A0100D543111170E8D516894E030400809070738B85EA01508014D4098008A825421C402202A34300705040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2018002A0100\n\t00100500180000011012488C32191426080000800810000052400119082400724880442200DC0F0050C55C4C099440800003\n\t80680E26A309A4D18B31600F67181FA300984C26130984DA204068CC18F31830C60C318031868C0300064310E84D04D14098\n\t0EA80220D030001C30448180E820AC07240D0308049980E8200C074105603821A260002E0C01D12035040B6B105A4201C024\n\tAC13130603A8408034042007235A0600E830468049980E8484135502603A04024D11000070092B04C4C180EA10200D013812\n\t0601A98504D120821A22000048BA242C01D24603A880301D4211068180006086823A880125603A09A2412411106014010C4600f05040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (688100020021\n\t0C188024110884466271A04C220108A7322044284D18055A0040181C8811002340A0600000209027310884C620101A540835\n\tC9A740695020C7268D0E2CC0A3E4AA052283C284138904A8401AB04A84009830E2102380C2AC40992488102E910C80D2A040\n\t6C9130B2088D222204C24D08800A0450A814A29442810824120110881728901244822311824748034A21018904600529BC02\n\t04528874A0510E950A2C10A13182046894400164922090120005040240A3308A512B81500200A82490A44A08028050080000\n\tD048040224D078001A0001804000C00104083020B00060008020000000041920102955880C0404422CD1A13426D321854B8300085040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2954E4C20499\n\t810A4048A842814C00494082C980106500A240054048345009440911C1920361000019908040804200C0940E188101178844\n\t44343C00000487214414490B1A4B01A632444826070A928892C1091845019804499549443869731148C322B245128C2A9901\n\t21A2F25058264C97116885409488C427A0C22700BB1C681D020000852261318E312681C820024341984C000C846442200C66\n\t420280000804A0604011088446847671806E341A045A801321144033338D89A1C03800820F2F004000000039AC2344B30101\n\t1088C484356C265BAC418800200D27000000005104C68100054823548144300470048221900940208012908884322140624400885040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A902011208CC\n\t243018B4C300D00040080013164AA5534908AA5505090A2040190802582B118920201120024946210A2630A00042510A0842\n\t458211103C35518E0244101184920908974881001000884E528348044223885200010893E7448901C2200A0C024290AA552C\n\t11220840058521600A6572144485A2A9540000000000878488D0004010310200D2232084021002C680210048B60E213C44EE\n\t10004862366B0010244490440001201402A440A9102A442A8100005003200A002A1190844488548080242540009081504240\n\t01010AA384009028841A00028010B025C2000020468000210870800C168000A50905487550091205D14195C859049902E7A200485040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2910AA452215\n\t4A25422154AA5522954AA112895422552A9542A5502954A8452A9502A442A9548A5408950A2402A914824028804A80000140\n\t221522144A25428014A2102A9142A510A114AA452A054A2510091002400080020552A9544346084380002954A0A85D828A22\n\t4020644226411C198310406564444101930A00C990CCC820065641008845025E2A008326003A6930503927438013019D3471\n\t333404A1C18A2110C82506922A653044480224088926506159204546200D41402020541442814120000000E4300404422C30\n\t204C98806A110264C09920B24800800C08000908A0440696406CD080D4C8350B0000000000D00004403203056000A46C460000c85040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9DC442211088\n\t442211088EE773B9DCBB5DAED761108844225F0517C145F0517C14F5503D540F5503D540A07AA81EAA07AA81EA0A2F828BE0\n\tA2F828BE0A2F828BE0A2F828BEA07AA81EAA07AA81EAF5503D540F5503D5405F0517C145F0517C14285502940AA000000000\n\t0000020000000010000400020000028950A8002895488552885420002800480550015000502A804A80520100201002010825\n\t12090420142A0100A05200040051009500050028040A1528100AA1108040000500050000022100AA5528954A8400A1542A10\n\t2A954AA5122950AA552A954AA552A95488152A950A2512A95488512A944AA55229448A052A910AA5522114AA4522944AA55200285040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000E001BC1E6517914CA6A351008009151880020178BC940A30080DE67354001FE555500110AA552295428052A91022052\n\t8014110884422BB5DAED76EE773B9DC442211088442211088EE773B9DCBB5DAED76110884422110884422BB5DAED76EE773B00a85040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (211E224F8442\n\t011D000A2F829BA1F079C89E44221047482141A9401954911041600000180A1289810F0078A1042A24A5054AA7C014BEFA40\n\t9108844220000000800B4D001480000000006F6FD00000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000685040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A4B808181631\n\t8601A6F0311148866100D4002591393063500150860448385E181998878CC51808D4A810290642A102209042023C91429520\n\t985430553092E026027082140892944820B2A05028551A05A5A258A94458782202CF56E9E420D95BBD5FEFF47A5C04220416\n\t8004265B7D62FF778CDDE330892852DD0980540FD7F9FC94C71EB7C38C10422020115484146C24B808105A41088C686231A1\n\t42110D398121A04168D0A0469E5FC983381DEEA350A84AA2B222345CDA208E4884422290CAD22A110E0C300050B0F4223E40\n\t85C2A8140640020001E941FB68261400804021F68B4DA243243102008038C41A440004082083A988200000950024528A24A800e85040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (072800428502\n\tBC101448871CC3F3911D0EF84423C76F3100C1949701220000800A3C88D478094C8442202114915108546A24408894A01002\n\t8068A542A150A8541A0529A512214408450A114284528850020E2450086112A0503B13329180915200EC4441069143231A89\n\t989810200EC24143291A895918D44CC4C28000CA220099463472804AA01E398105A41289DAA4462C8C602052802089500480\n\t4CA31A881021143291AD6140EC4CCA4702550002D11104A276A9118B23180814A0080244CDA27328503B13280000A48BD022\n\t8F7926072CA462246463150A90076220C9FA2847A6546EC4C0A0762650008D047122A110B249A89989810200EC24411A89C800185040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (11C07E4014A0\n\t1FEC82FBFCBC63432E064EE12261045F0B1C1B41808904A83E3006DDCE00F2B946FE5D1C1C6CE51BF9747C71B3986275F00D\n\tC6827FA807C2B6597DFEDE46865C4CA5C24D1E997C2A17E6E5C18C523C7831D9EA37F2E9187B6789DDC38771119EE31D9106\n\t8FF3E875E6361FB75E6FF66B75B8BC7EBD068631488010581D24C2CFC419A10CA804008C43179A0CF2B701B787E195108810\n\tBE05A984ADC1C8CDE659289B1108E480857EFD5E0F4428A77A8DC41E3F8147EFF399CDEA1D1F96814A010114464524118282\n\t10C81C3285708448810549090EF91B85C063547BEC2E821017C14204528850085023C6880103453C1022910408A70075CCD700985040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9FC6AB32200D\n\tA2C06798DFED950A4184F103834E804760C8FCEA4CB61FAD32B8E4B21F7B260C20A0C1A020814114012C205A7CE0F27E309E\n\t270340FC9CCC622443A635B8204CAB22321B0330227DAAD3062FDEA987E8BC2E627FB2D8470780ED0C5D19358C2230322C52\n\t2000000E602540A114A2000453E0850284508A510A1E05111000001042001009701080005D4104422201EBD9120A2FA2900F\n\t1001548A8D44A986052668A596886C8154461101258CA00887C82504A1C058D809988445F05220D8871B1D4241A0312482A3\n\t6004CA281603DD98374D081944C1E3DCAE5C2B020E043003D0686547AA00478648ED161811145488801320802A513092E02100585040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (44B48C66005E\n\t0FF60101FA7F50841BC98203318C322A13002FC6428C50F0218FD86C03505116FB5F23CD0F262B34688F0C20D488002B3D0E\n\t63053809EFA02045DA7407B7DF8DC6E10084FC1E834CCEB0BBA81E0E7F37DEA0D1F8FC785B2583DB0F2073CC90C9079EC9EF\n\t03EB7D8E7139845D8C31E90822914488070432D008104904281004844221E8911C04D1A1042021108D1E82448CD1A1FDAA77\n\t6ABDDFEFD3FB7DFEFD7F974AA5F6A985FEFF331E0EC050FBFDFE273B07954A37D9DD1EEA743F9BA43150317C3E21044CA863\n\t408410450809484114A8200421191C0A8A12634484CD013307CD340370B87359B3C68C02A844387C78101025C13B008E140100d85040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C8E49688C866\n\t2120008582247094E22C6023D060F62850A28523231403860005708E07008080C06801406213934AA576A96114C53A1D5108\n\t2548EDE0714A35C4ED05A128E0AB3D2B81418001E4720C06131E0317D110B64708915BC477A2C10A4C08214AA8620A4C00F0\n\t00130220078331983351200000A2F82810F11E8C1EACF061C024092A05940612D91420590296516436E884446200350E6050\n\t20548A54422212CCD41BF4EA5E319FD881D6D00808372C840241108A4510897129500284D1A144591E968D0A354301C42209\n\t845923F79A211428690DD880355128BE43149DCF8CF089312A2A10081ECFC0001D00CD01871E4A5042216203058612C400A200385040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (140A05028140\n\tA0502814552ABFDFE00002A954552ABFDFE00002A954552ABFDFE00002A954552ABFDFE00002A954FF7F954AAAA5500000FF\n\t7F954AAAA5500000FF7F954AAAA5500000FF7F954AAAA550000018002800400351552AAA150000000001542AAA1500000000\n\t0064486800AB404B405B016E8C558295E8A7D2A8E4AB0128154725D32938336C0306E03178099E04701B00030558A9166A10\n\tA00964220040123456120062A1432DE02C7F0C19E0F19BC1604F480A0480A40020E80210098804110A1530B03730C5E025F8\n\t21524B70108542150010068420034000E42A246808322BD564D5A3AD86B879A210450291750E0A52B9824C9279A028014A3100b85040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000C001804000278BC5E2F179B\n\tCDE05029148A05151A88020001001E4F0542A8000000001A8FB3B124AE3421AC8881223AA1945F2F97CBE5F2F97CBE5F2F97\n\tCBE5F2F97CBEF57ABD5EAF57ABD5EAF57ABD5EAF57ABD5EAA05028140A05028140A05028140A050281400A05028140A0502800785040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A28025BEA07A\n\tA205088141A9442A55AE9002A00000108A5729806A8050A1242A452AC540A7817D540A00281EAA07A8000000800B4D000C80\n\t000000006F555800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f85040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400088429512\n\tE950A22D238446044BA8542811288508B4108954A0142A1540A113209059112891C7E5205D542A741FCAA893F1514CDF219A\n\t90082752A05028552A054AA4508944485022054AA552A84098572A954AA05154522204168060044AE92669552B8D23319995\n\t2A951F20540AB551A8CA8155229F085142A900D645821847F2A8A448EA44888C28A252A14612152A8742A130A950A1452A95\n\t4A8552E934A251289D4FE3599452AA390ACB00F2D2BD54A0550A010080C0F04C0F670143CE16F17CA81544815007C6005560\n\tBC250080CF00B00044144D0088A481601506CF52BC4C64867864769450199D2E265A1C3E2121BFCAED43131002FF2AA9552F00045040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (525914A84402\n\t844A2160A0F05514A20143A41A28C4A62E255B40F2D00D14A25138944A14308894A010A68048A542A150A8542A054AA51221\n\t4408450A114284528850221C0A1108A4B2A0D02615269142A4A209D4A0400A914A65128952A841208C40F14269148A332894\n\t4A95410814AA7A80134A2052801EA014AA800FA4028952A844999442A52281AC8350088108A51289700A1426914AA3409854\n\t9A44AA8A00A7528100A254AA11266510A948A06B00C549A45268D02655108146A1EAB1448A532A0549A452294CA20B25104E\n\tA500815068452A94499541A04CAA210A5500E052A110A65128952A841208C40F402A914022A8A4529A510A914564283CAC9A00845040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2944AAA542A1\n\tFE5528B9954641E9615E28500A954A2151A944AA553A544BA512A954E9512E954265510956AA4128154AA6D2A974BE458652\n\tC96542891496522A154EA541092AAA5A2A954A2552A912EA5509954255539974A2153DD50AA1526954281526954AA4DA6172\n\tAD552A850424A88854A834A89540A450A9042274039543A71289D8EE791A94C194D28432AA1526554A8350B954D5341A1060\n\tA5118956AA56AA8148A5528954BA75228D4AA1328954EB151614AA050251449414254A4A22A2A8A8865089540D9158892CAA\n\t113B8E42A452A854A2601554A204528950A8541A9548D14194AADA079681C885416154BA4410852A854169503214161542A100445040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8140A20D0284\n\tC5554A8954AA4D2A154A2552A9742A532A084A51C2A9508920B59D480252AD40AA5628964A8540A934884A2CC54A255080CC\n\tAA5620D5022442AD4CA2242AD5698550A854A25522914A85A0A91CAA112984622450292A2241A80D489520A114A255358742\n\t051288508A512A154ED4002844A211220105514A61105634A0D2C0E152A004FF2AA95049B1E2E9148A45028405F32B588A78\n\t4E02946A27E2954AA0488D5F0A80296030680D189825552A20B646513A4222A6529452A230B650626502A9902A5428900883\n\t52A954A945281C0AA552A9D4C7551805208400891428148E8D400112214422611FCAA290D3985422002A104D8553E9F4624300c45040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (954A9502A57C\n\tA05522144AA421094CA8410A954A02C9BD04AA5522950AE4C2E5C88A34208A8AA542A94C4252A8134AA60A0D14AC05269528\n\t85530004A8351255CAA152A9948A552E9540A150A8D4AA4D12850AE6529932AA252AC14A8552A9042A5117D50B215200BEBA\n\t0008950A25508040A94120104A8412015020000E8101815281108A152A804B916288548A552A0548A552A0548A552A954AA5\n\t538954AA552ADD45A152A9542A550A954A2552A914AA542A9548211125542A4017D562A54208507E7C829005F15881140A11\n\t289508174A99CC9A1122554A6442A05002512A85AC2779D0D0A040A152CA8172D954292F28C8C3B6899076854528954AA41200245040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (7000062FD607\n\tC408C1808F20309707301A008E624D0D8800100100E0A211B3186F7781E954C77E1F106214C0C19E00183C000C23A32580FF\n\t4FBD49E013129592F703805506615275D46A2D265748E14A851C8C322A9CCEA5118820A8442204C22572A9362654BA820FC2\n\tAA9590A6550A954AA1498842AE5C08944B65326054A6452A894AE55048221110A8944D9241A934AB4CAE544AA512A9D4AA71\n\t0A9006A550858CD54AA6CDA3D340F5108A211551428552A144EA149A950A1542A93299411F9022A512815416412B90002550\n\t29740A0DAA8548A2F821749A04048D4AA55209108A550E8B85515220BCC904860B46275261AA14441694AAA40A2154AA409400a45040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (EFF7FBFDFE55\n\t2A954AA552A954AAAA552A954AA552A954000000000000000000FF7FBFDFEFF7FBFDFE552A954AA552A954AAAA552A954AA5\n\t52A9540000000000000000000864A65209C048000000000000000000000000000A880550AADC58C600001040005B097E247E\n\tB3DEE8F7DBFC26FD19979FC736A93C08112601022010380D08003017004107C0FD9A7F43235C4437000C18424D88008A10A3\n\tF5FEF47E8419A0F08BC1200E240B0248B52A21FC6114878040301A30F6A806B281E211FA1190081D08814A01420110BC0108\n\tC040016151708B502BD100050321C08864220E4C26133D600A3E03D64841082060A0780FC180B39A381C2001225402A5000800645040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000F001BC1E2F128948A65329148A2512894CA45028148A4502814\n\t140A001000000000000F8383B1000E3461A28E0C26028416FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA8\n\t00FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF7FBFDF00e45040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (108506014013\n\t8004480289002F042B8808C0280C1004028154AA5502954AA552A8000000800B4D001C80000000006FDA5500000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000145040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800800006020\n\t080120635840834281C88CC660CC6620640F0608201B0840C230154AA555402CAA552A92018364020DC6A30000DC0003C381\n\t1803038CDA0254880986020000092A400154AACC618A1FC7C218605CA60480000CC660004022600F106662C859801430870A\n\t2D561280AE554095080552A95586801C33118101800C0CCC60000CAC061A0002041C10042034A090080E0603000A903001E0\n\t002E204AA552A815000C2215C827265A84A6000B8C588400A2046821389D048117980C3821581C4E064020D03C2128054305\n\t370B08E0462C26082A32402184514284042150B01C844C6100400216001002552A95504843800000552A954081410220081000945040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A04E08006040\n\t20000081080552A9C4204E0601000050A914684522010C01430904824120804A840228448A710A14428510A114A264290542\n\t6200810426906801048042A05482550E21060010293480412005482C5610102834008149A4020900AA042AB3010050091588\n\t4C28040A044061308041180080A012A114A80123844A8040291400C5618102E0909941A0080A010A05522154784C20104600\n\t202804A8452A3C580040A010465008100AA440A81C02302090580040A0D00205009506A412A93040130A01098402088CA010\n\t2015426546288C620202A348041200D484051A288E0002A9558420062580A881E155CA94083808055089902A81003542E80000545040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (548A0401A501\n\t29948025302404B1130604C09012C24C080688904AF4008041268482410000008234220000241060606009098928213100AA\n\t4104800C09812024C48210220128204B44489A481542A96328558C100384508400884822020001588402AB1510030003C000\n\t85302444210938808041116802220500480884212110826809830034022010422A804020142A200000010018A3C04A807080\n\t41130900322A98340103970AA0527954985529950AA4D28850A23112354AA5D0094528A9231111E0000801801C20954AA450\n\t801082A10090010302385400442A9558E50039454C971C100AAA10090006500A94D4CEB2215036C52883022D10400CA0552A00d45040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018C81820040\n\tD000380805570800603018154820C40000100C01880180841800403304081808000140184C238C4400C44000102041800042\n\t0150001088050C000080430000C26602100C040030AAC50F05C363001B0C600C2815420530683586300600C085520355BA1D\n\t0A1DC0E552A928EE02101542AC40886002552A8546A0045910EC340400180A0010000823311D0180C0194008CF06140AA550\n\tA82D862269A3080552A8D40860480619AC01814082CC06150AA150E01064C0201550070209101010111410A283524880851A\n\t100AA00000000000081440A212A048B0D020154AA5544221800C00201042200000141A1120100202310C00202C22000522A900345040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A0957281802\n\tB241548696328F406430C044A6344183458944B00082402A834381C29154021840854BA1108A1CC2002E39822DC0214D0044\n\t06101A074298403845081C4A031429CC00C142900F098329642E65131541A20009D0AA1500B14005C00330A0421880C6A421\n\t8B4020122801008050A1406202021040E11620601C12070481C12070481C12070601C1807200300E20000D000682A1100200\n\t04134D26C04914A61A2D908420810420042215482100010022552881088550894048050603C0003100004000780C100001E0\n\tC1600C06080002F7000046030783060B00000C46800400D840803B3180340820006010087418CC781000833002301803110000b45040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (885603D4AA6D\n\t3A955825D22331A6510E914EA512EB54AA5D2A05D8A712B854AAC72E97C7E712A11CEEF537BE58EF77BBC0480060100D2A61\n\t483180640C988D40A0011862B351B98000C26131E6416180D98F00008000580386066542A9558248088001A000020C1E3111\n\t000084012008022418214E04812371BA9D0000D82400804042120400006210A83108400200C08110000006C060800A0552A8\n\t546630219542AF37020C1E2E60000060C6183018042A15462E14224C38540E02C2EEF161C058703111082102A9F42A0362B3\n\t07084660C8661E1902CA855288CC04305838C100C2A814A019199C150CC1904C54B30009400582D8092C0C4204C1C840990800745040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (72391C8E4D86\n\tC361B0271389C4E8D46A351AD86C361B072391C8E48D46A351A271389C4ED86C361B072391C8E48D46A351A271389C4E143F\n\tBD546021F8000000402A8540040001000040200544000B54A8541995C2A5C2A910AAF97B1FDF2C72ABF44EFE28B5DEADF708\n\t1C52425A94054D42C354145456800AA2B6B9FDAC1F6F908EEF03B815E24F1ABFD88572EAD8D4D94A8952C5631294CAD13A04\n\t4BA4C2F951B8D70B9F5A2D128B1DEE756A91C8A110A9143E4E46B448A530A134AE7468974A2452B95DAA8566954AED73E95C\n\tE27D3B935A2753ABDCFE5533B75A2436F3503AF74EBF5AADD489FCEE136B915B81D2E975BC5422968AAD925874EE5766974A00f45040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000C01FA8544A25128944A25128944A25028144A25128944A25128944A20000000000000018C76885D\n\tFA512A9F5A8512795C88C964B2592633198CC69C4E27138361B0D86CC964B2592633198CC69C4E27138361B0D86CC964B259\n\t2633198CC69C4E27138361B0D86CC964B2592633198CC69C4E27138361B0D86C72391C8E4D86C361B0271389C4E8D46A351A000c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030080C00018\n\t00000000000000000000000000000000800B4D000280000000006F0CA9000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1000AC8608C0\n\tE814081E406004005848031000000005512000000002000324020DC020020004000043810053038C0009C3DA85CE0027125C\n\t64E0D00000C0001618070282D440794BB9840000000440D0001C1005D6B854001430870A2150628000004000408000000006\n\t401CB00000018800000C000040AC40100000402400008042A05008000013108A801001C00000200000000001001C2200CA06\n\t061845C4600B089984112164CA553A9D4A821712083201181C8E0C446094385528854229362B10E244288440083209018055\n\t00040AA400A059804C4C004000540020260000000A4153B000000000000800051220008010100608101201422828080A0B60004c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C0820C061000\n\t4120500870830082000084020100804004050844100104300408010200420840A000800864010240C603603600050000001C\n\t00060206236002301A00028001CC06236000301B001180D00014003800331B0000AA01848C069400228062301A00188D8005\n\t00020004004190000D800200C0C068360000C3180D80D800100020014000188C068006236001400080013C180D800040C603\n\t0001400280005CA2301B00182D8000C06C0028000000E00070206301841180D0018C060002801C000600806836002301A000\n\t28001C400019810100000022002815002980400140800A39008000A004080008A000445068008E006811092140000840800000cc5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4E04A1027944\n\tE03822860017B9F1AA944B0803C4A051C42A962486428164A04460010A2214E284E01800212812080204F2898029040094E0\n\t053B00887047804604D0E001A2403184480410C0542214092158A04003001003220380050411400C64223182050331088866\n\t2910408194900432166211C0003188CCE6010013020114000188102A84D80386B89CC21203064A80722A18040D3300000000\n\t7800180001800000C0000000301030000000015928A12211018014F87D800C02000001000001002460204883201800000000\n\t0018004039450C801801000A06820406080014D0CC82215000094804022110091C00000020068000E02060C5000200000000002c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (603038000085\n\tC0B9C0220D6B854B805239B4027710911861503804900E019C18A4C289D1A2050B9D468050E86CA841639D9A20528B1C2089\n\t6E1D00AC62A07800C02698C263105B4C600C0880010030603186340610D080002301980C011DC2E0000100EE022400000C02\n\t202020000000060050184062310681580A11A81000030A9D4184C29900000F2601000000015D8610610300800000C088042A\n\t25598C03A040800C0E00400000E81062F10000180306084028042A0048834441F07E00108040004000000004000000000000\n\t0004E0020000000000518C1C0020104541201014020120000210204C00002A1000E04000000044038014E700509C449E513100ac5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6D20C044BE35\n\t0B83C50C0001408E04000F098080100088112884C32110894CA0000430088CC2210020400F00120300391C1A11081C088700\n\t81D808902894062750E01C2865131540254208C0000008300220C2033002081801C6008180042A0008100020000004605002\n\t81084116292D504B741697A5A5E9697A5A5E939504E140D89CA842005600570278C24B2C98164B4580D9242C16AB11A00300\n\t4448400000060042601040000210000000000490402E97C1247500016034700C100481E8E0C00C06080AC4F5181426430702\n\t4406002048EC00220090C0407265227904855341003030388E7014092A62687010DA00100D083500D480E240B04080060044006c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A21502950225\n\t50085480500A914A2550A954A2442A800A21400940025002900AA51021500060041608A0F14420D83BB25C20D0A03C60B731\n\tA10004806235C64541A5D9AE00408046C029150C600000010034220083221030081C750000038500400006083805160180AB\n\tB1DC6E008D900C0180318840000446420061F4A60306169B204000000C847105018000000066340300000E35034C1C4A6200\n\t42E1C49870BA0D00000E0D020A0C90000E0102EEC3C1C020703001082102A8C40042603304815450C8EE5D149280000001DC\n\t22705A39C220C00040000C1B9D4E8CF3984DBAF322000020C05801865C2A95C9A1021810200017080824B06001A2710E0C0000ec5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A003FCAA557F\n\t80154557F80154557F80154557F80154FF2AAA800FF2AAA800FF2AAA800FF2AAA800285502940AA000000000000000000000\n\t005000140000000002A000AA002A904A8052085428012001480550010000102A804A005201502244020540215001140A500A\n\t0042805000100050229500250088142A5528004AA142A8542840081040211281408A540A0548A5520044A215089048211229\n\t10A851228542255221548A5528854A2542211488410A8040A55209508A542A9548A542A944A85522144A2510A1140A552894\n\t48A552A050A254209148A51288542241229502A550A95428442A9442A440A144880502950AA41289502A4408910080500140001c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000D001A8D\n\t40A05028140A05028140A05028140A05028140A05028140A00100000000000140AA010294000012A050A2052A9005F50029E\n\tA5F50029EA5F50029EA5F50029EAF505280BEF505280BEF505280BEF505280BE0A7A97D400A7A97D400A7A97D400A7A97D40\n\tA02FBD414A02FBD414A02FBD414A02FBD4140055155FE0055155FE0055155FE0055155FEAA003FCAAAA003FCAAAA003FCAAA009c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A954AA55000\n\t0000800B4D001280000000006FC0690000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000C0B452A95\n\t4AA0024154AA5528944380002D9008050200002403284053078C040B66CA85F6037B329DEFE452A954C00014984737D23D64\n\tFF57BB85E221102900FF140C8407F6F85C003C7F8DDE63F0102150AA152A140AA552A8468259389448059021442C0129C5EC\n\t21020810E2603A51E9C3F071782010170460204001D02A5102950AA550A812DE2ABFDA6FF7FB5DE4BF3EBC9EE1C388707804\n\t7BBF01E275FBF86C3779BF1FE3F7F9F99E441C001FAF37BBCDF81166910AAF36A9319EF36290008555F279E6CF3780C00336\n\t18DD1AAA552A9A6DF6580000AA552A8542A040884420452A864280000006824D22834FC0032954C834A191022542A954AA4500dc5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800020402010\n\t08040A0000A10200403001020040841080100051AA9060800021962B613C914205522918AA4708170BC110B15E085122918E\n\tA703C914B05E08858AF04288543255339E42245889D02C17AC85082470B15E20582F0442855089500A1188854F21108100EA\n\t743C9100C658AD84F245281502A412A91C2C5788160BC110A15422543E994F205009962B412885482553FC72B05E22184F24\n\t52E17822152A9148C553F87CCB4580058AF0432C5682512A990A87522160BC410B15E0851229182A45321148A552A8000F48\n\t1F48620012A8142A1930140AA3E2895800500A950B0373E9FE8079309167F508A10428052A154E0782C0F80A022E18042320003c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (408241280782\n\t8780FC1882440200002420C160411F0A11E821E28154837933DC0A01E02984C3180A01E0A07B05C0F007AA074FF5F83DF6F2\n\t078CD98CF198FC66BE1D03D98A0553281023670B80408410A084200230810001130804220108C0008400001082642B802817\n\t9BFD7EA755229148345341FE305F2A9D4BA57A89D6DA37318F83F669FC7AC707A89540207800180001800000C0000000B000\n\t30150A2453C178FB6733198752DAF5D00E512A954020000000007002C00B04180000A8552A9D0AA07BCDDCE81D2815488700\n\t2C16A8553CDDCEC663F110031C201763B1400D44AA5502064841F229542C0000150AA550E910AE573084480400016423002800bc5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (CAC758AD46BF\n\t78341D6F357AA1D08A55BE9F83E27ABDFE9163ABD7EBC7F8A850EF5FBE97CAC7E3A80C6B773D982C26722954CA1632C46320\n\t1B0C600C5D2A940AB0F03986300620C1CAA51389982C540CD06AA550886600502A854E8170B914AA553A8743321A6562BF41\n\t2B194530B09C00A31D2E5B8CE31B04002F3F2A554AA552FDBEB062A3144AA550C8C6C22603598ED3E005802C2F2A954AA1E0\n\t30E6F7052A854B261BF0A81718AA19C0C003D12A6A11AA154A01522000A215299348A1400140CA502A954AA143F1962C0020\n\t104D01F80014020120000212617C00006C2F814A7552A9140E118A81EF21023D403C05331E0E0500F014C3780C060287FAF1007c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A0553F9FC325\n\t52A9DC1C618CC7E3319A0CC63F07A3570C802BE180447F9CDA6F03F8DD3E1E181C0B4F9621FC10F061BE9E6FC7FBFC78EF17\n\t3FDC6F305AE954AA4532976AE5133950A21D08C74A21D0A07EA25DBA1062A542A0643007A8854336617DAA5F6A9FDFE7D3F9\n\tFDFE7D7F975AA5D6AACCFEBF130F85C84643FDFA2B3180974B27DAD914AE762F95A820530D5C0C452A954A84428444AA550A\n\t914AA552A1102A7E1FD2A21192840442753E99CC35FAD8C48C5F3CDE85F2A8843E33660010462563F81848638C0028002004\n\t18F033BCCBE12102B83CFE61A207C0076BF978DA09B00FECF2BBF4A0CA57A8144AA7128080385D2A954FE652BCD8AA5FAC9F00fc5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (26B8DDF4080D\n\t3F800F01E10180A4252A49462532C15800601007A1D7D9353E7A5B10C8C0B12214727B4DA0480005E23D86030197D88C01D2\n\t81C6EB6500006AA552A804BD770C180C3062C01C00080105C081C0440A1818949608C18BB1DCEE018DC045128890AC600288\n\t82AA2571FD3281773FCFE260000018045029954AA552A866B0502A854CB0326DD8E17F200468E058B0588E542A9F4FB778AC\n\t44A81E2207ECC113C060F860A319E3B7FACD54A8753B1DCAF000D066B30004154AA570DC60301831D384C5532950AA7F805F\n\tCCF7BA4DFEF33082804A251830543E72A7C1E2F5DA8914320728C86E3542A992FF7F9CC96B8190CC1E737DA3C00E854389D400025040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000030551A942AA2B1552AAA150000000001542AAA1500000000009408850817\n\tCB27C32A05C0A0532A9524A002A5F4AB310294C9A5B22940225A02050820D20512285C0D0042A49AA97E2A13120128202091\n\tD6F834A151ECE063D9FED86088D980261000C0A264084FC886C20044221B08D249301A391A084C811C8114811C088804B49D\n\t2525C12C8A704085CC240272C86E054200D18B805030C0862021844E7760994CB22700864050633076AA1C0C9609B618D800\n\t0207224001109B01D600058B04422060E1D4CC06298583621080684A061AD16CA01010008207939FA537F88430E24A0FC08600825040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000030018080000000000000000000000000000\n\t00000000000000000000000000000000000C0181100C64222CA00000224A880EC9318D938364E324C69C1B18D926364A706C\n\tC9318D938364E324C69C1B18D926364A706CC9318D938364E324C69C1B18D926364A706CC9318D938364E324C69C1B18D926\n\t364A706C0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000425040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006F3C\n\t3000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c25040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (900300002D90\n\t08250200002003084053058C0002851009D6025428514A80000000C0001498471550A824A6152210A000001400A5152C8406\n\tA4D058002845089442A150280000042A0000000000464018B09040059801842C000284ACC1120060824020854284A2904802\n\t00171320000001D0000100000000008024AC5500D4080618B982807580580717B984F2595D2E5501E200045C0E182CD60C80\n\t23283899348544423653116477513B5EE035F20180A60798154BF34AA4008C70008000660030060000001442A4C000000000\n\t00050800408844064420960020020004025020840A80032954C8552291002000000000000000000000000000800B4D000A8000225040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (403841021040\n\t841080108201000968A050A1160A7028804280020010004608974A8000B854800120010C06C28804B8540005C2A400080022\n\t00331440005081802C052800002260B05480592A0002A0008000001180000A20008900C06A288000A45829C0A2012A000000\n\t1000982C1520164A8000A80020003C18AA2010A1160A500080002002AD54B81410182A2012D15000148010008002B0548B01\n\t0A0582A4022C14A00100110006022170A8000B854800120010004022000000000044A9282A89410008000002103000400550\n\tA490825500000A0552A954807120914AA4100114205028054C0693F0E825132BC84633A0A00C06040000000002800000000800a25040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02A52088E049\n\t152A154AA540080002542A944A0552A904AA140A9540A5528550A01500840AA150A944A005089108A110A844AA1502990000\n\t0300541B5483500A24526894AA5232840A85528910AA51209102A5420854AA722644442512A9542A00221000250289542A55\n\t2A980BA5528954A245229502A452A8548A05000000047AA918AA51AA1548E510A144B2043A800000428150AA4522178AA550\n\tA9802C0080000204108010884C0091033258A9002000001800805A8954801C00000484C00906080028D54E8442A110021420\n\t1542A1402C0000000A072A657005348A000004000000C08C0E072800060400816423112880082040201008040A0000A1022000625040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A11AC1502E4\n\t52A954A245AA954A8550A850AA552E954A8543A814AA772A904C24502800E04F29C343141B8C600C15000000316031C63806\n\t20C140000321DC0E002EC16000026576025000100C00402000000010060195FB88747A47A999451128640053579D8BE4E69A\n\t84002F570280000001ADAE60729300200000E0B481340A5FCE57A285002C5700800001602164EA040015432412A1502A5500\n\t11028552A854801108000A81522110690302140004008000C20000000004A2A98C8E552A954A8552B954B20522814A92215C\n\t0000522A80C0A0000000084D80954A0052A944AA5522940AA502A954A2502A8502A552F954A95528154AA552A854AA250A8500e25040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (21121D442A0D\n\t2695088052A100885528944B0550A9542A102C154AA44AA810A0412A964A8552A850AA152A944A0010C0000000381440C503\n\tB0002A5800C602A1800054021028014200000070A2050A004226428854AA552A054AA552A054AA552A954AA5528954AA150A\n\t8D489642A9542A5100954A2558A914AA742A9140201209340800000400844008500004000000000001140056AB8544211288\n\t2496752E914925D2B9448C57289402E5781C5663468152CA256288B280650848C0406958A2B15528954220023058AE6B220D\n\t455552B950AA11201548A552A940CA55280040074168C0BA5D00050AC452A950AA55A895CA8558A944BB52285D4A2550015000125040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (47BC89E0A491\n\t21680060300D66A5526D50AA55349B40A1422876B753969089416139D6AA55AADD4EA55A8944C650AAC5600000015029442A\n\t15482541881AAA108213CA4120881424592A0E02815371BA9D512A910A25102150810508854A0061A94402472A9540800281\n\t9404302A814000000166B80000000CB1316CD8926D228366E158A0508A0000160E64D20D04021621056CC512C840B8510211\n\t422550C900A860378B25A452D9766A150680000022DC3C301C31CAC8C0010010085D959548A5D2AD54A24118004000182804\n\tAC4D1AD5C9A3380440284718884931400102AA552C916A811089567A538380080412895400002B150220100190284108854200925040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000003864A25209C040000000000000000000000000000A080550A9BC187C0083C703C7121074E07AAFDE6CF143F5\n\tBEFD51895EE3F6E13C80100A01000C149B00802406030060B6A3FDA23F0081000A10004918347A90186B01EB51FE506180DF\n\t80160000007102020024E4C210421C133094280102081407410007E027E020508E40000600160010660850330400A0100860\n\t00368AC40880208040EF0123C4623100BD1AC321280468C1188010520520910A810229003111228100000320708424088586\n\tC4002C4438010D860086088DF8570E2A0880A00900022313B357873778A53812460ED1E13100FDF2026C3B800E21832902F400525040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000180800000000000000000000000000000000000000000000000000000000\n\t0000000C09E1188C642024380408062BA88A78438B5A4D216A1CF0873C3485A2D691E10E873C3485A2D691E10E78438B5A4D\n\t216A1CF02D691E10E873C3485AD216A1CF078438B5A4D216A1CF078438B5A42D691E10E873C3485A00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d25040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000325040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000800B4D001A80000000006F1DFF0000000000000000b25040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000725040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f25040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aa5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000800B4D000680000000006FC289000000000000000000000000000000000000000000006a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000da5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000800B4D001680000000006FFE6C000000000000000000000000000000000000000000000000000000000000000000000000fa5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000065040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000865040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000465040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c65040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000265040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a65040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000665040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e65040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000800B4D000E80000000006FD8\n\t300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000165040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000965040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000565040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d65040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000365040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b65040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000765040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f65040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000800B4D001E80000000006FED4200000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ce5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000800B4D000180000000006FCB1E000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000be5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000015040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000815040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000415040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800B4D00\n\t1180000000006F01540000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c15040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000215040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a15040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000615040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e15040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000115040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000915040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000515040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d15040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000800B4D000980000000006F27080000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000315040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b15040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000715040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f15040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000095040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000895040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000495040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c95040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000295040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000800B4D001980000000006F127A00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a95040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000695040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e95040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000195040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000995040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000595040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d95040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000395040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b95040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000800B4D000580000000006F3426000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000795040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f95040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000055040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000855040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000455040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c55040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000255040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a55040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000655040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000800B4D00158000000000\n\t6F08C30000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e55040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000155040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000955040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000555040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d55040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000355040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b55040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000755040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f55040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000800B4D000D80000000006F2E9F0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ad5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ed5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000800B4D001D80000000006F1BED00000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dd5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bd5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000035040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000835040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 1624 TDI (FFFFFFFF0000007A3DB1000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000435040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSIR\t8\tTDI\t(FF);\nRUNTEST IDLE    100 TCK;\n\nSIR\t8\tTDI\t(26);\nRUNTEST IDLE    2 TCK   2.00E-03 SEC;\n\nSIR\t8\tTDI\t(FF);\nRUNTEST IDLE    2 TCK   1.00E-03 SEC;\n\nSIR\t8\tTDI\t(79);\nSDR\t24\tTDI\t(000000);\nRUNTEST IDLE    2 TCK   1.00E-01 SEC;\n\n//END\r\n"
  },
  {
    "path": "demo/litex_with_dram.svf",
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 (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000800B4D001580000000006F08C300000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000800B4D000D80000000006F2E9F0000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000800B4D001D80000000006F1BED000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000);\nSDR\t8000\tTDI  (00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000);\nSDR\t1784\tTDI  (FFFFFFFF0000007A3DB100000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000);\n\nSIR\t8\tTDI  (FF);\nRUNTEST\tIDLE\t100 TCK\t1.00E-02 SEC;\n\nSIR\t8\tTDI  (C0);\nRUNTEST\tIDLE\t2 TCK\t1.00E-03 SEC;\nSDR\t32\tTDI  (00000000)\n\t\t\tTDO  (00000000)\n\t\t\tMASK (FFFFFFFF);\n\nSIR\t8\tTDI  (26);\nRUNTEST\tIDLE\t2 TCK\t2.00E-01 SEC;\n\nSIR\t8\tTDI  (FF);\nRUNTEST\tIDLE\t2 TCK\t1.00E-03 SEC;\n\nSIR\t8\tTDI  (3C);\nSDR\t32\tTDI  (00000000)\n\t\t\tTDO  (00000100)\n\t\t\tMASK (00002100);\n"
  },
  {
    "path": "demo/litex_with_dram_flash.svf",
    "content": "//ULX2S / ULX3S JTAG programmer v 3.0.92 (built Sep 19 2020 14:37:22)\n//START\r\nSTATE IDLE;\nSTATE RESET;\nSTATE IDLE;\n\nSIR\t8\tTDI\t(E0);\nSDR\t32\tTDI\t(00000000)\n\tTDO\t(41111043)\n\tMASK\t(FFFFFFFF);\n\nSIR\t8\tTDI\t(1C);\nSDR\t510\tTDI\t(3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);\n\nSIR\t8\tTDI\t(C6);\nSDR\t8\tTDI\t(00);\nRUNTEST IDLE    2 TCK;\n\nSIR\t8\tTDI\t(0e);\nSDR\t8\tTDI\t(01);\nRUNTEST IDLE\t32 TCK 1.00E-01 SEC;\n\nSIR\t8\tTDI\t(3C);\nSDR\t32\tTDI\t(00000000)\n\tTDO\t(00000000)\n\tMASK\t(0000B000);\n\nSTATE RESET;\nSTATE IDLE;\nSIR\t8\tTDI(FF);\nRUNTEST IDLE\t32 TCK;\nSIR\t8\tTDI(3A);\nSDR\t16\tTDI(68FE);\nRUNTEST IDLE\t32 TCK;\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000001B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000801B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000401B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000c01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000201B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000a01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000601B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000e01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000101B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000901B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000501B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(20);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFAF26000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000051B889410000006200000802000000\n\t44C208888200000047000000DCFFFFFFFFCDBDFFFFFF008C1CCC82E24282C26CB462AC4CB4AAACA26232045C2E4E860A00FF00000040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000800040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000400040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000200040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000a00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000e00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF4A910000000000000000000000000000001800100040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000900040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000d00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000700040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000880040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000480040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000280040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000a80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000680040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000e80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FFD3590000000000000000000000000000000000000010000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000180040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000980040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000580040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF8C9600000000000000\n\t0000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFC495000000000000000000000000040000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8C9600000000d80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC4950000000000\n\t000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000380040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000b80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000780040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF835F00000000000000000000000000000000000010000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF2179000000000000000000000000000000000000080000000000000000000000000000040040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000840040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000440040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000200000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000c40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF20E4000000000000000000000000200000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF20E400000000000000000000240040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000640040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000e40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000140040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000940040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000540040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000340040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000b40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000740040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000f40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000cc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000006c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000009c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF005c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000003c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00bc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000fc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000020040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF211A00000000\n\t000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000820040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF211A000000000000\n\t0000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000420040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000c20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000220040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000a20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000620040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000120040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000920040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000520040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000d20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000320040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000720040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000f20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000008a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000004a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000002a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000aa0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000001a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000da0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000007a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000060040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000860040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000460040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000260040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000a60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000400000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000660040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF80ED0000000000000000000000000000000000000000000000000000000000e60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80ED00000000160040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000960040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000560040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000d60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000360040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000b60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000760040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000008e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF8DC200000000000000000000000000000000000000000000000000000000000000000000000000000002\n\t00000000000000000000000000000000000000000000000000000000000000000000FF8DC200000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000ce0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000002e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000006e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000ee0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000009e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000005e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000be0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000010040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000810040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000410040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000c10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000210040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000610040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00e10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000910040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00510040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000310040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000b10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000710040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000f10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000090040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000890040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000490040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000c90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000290040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000a90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000690040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000190040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000990040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000590040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000d90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000390040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000790040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000000000000000000000f90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000850040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000450040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000250040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000a50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000650040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFA6DA000000000000000000000000000000000000000000000000\n\t0000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFA6DA0000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFA6DA000000000000000000000000000000000000000000150040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FFA6DA0000000000000000000000000000000000000000000000000000\n\t000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000FFA6\n\tDA00000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFA6DA00000000000000000000000000000000000000000000\n\t000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000950040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000550040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000d50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000350040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF807400000000000000000000000000000000000000000000000000000000\n\t00000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000750040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8074000000\n\t0000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF81460000000000000000000000000000000000000000000000000000\n\t000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000FF4000f50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000800000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF3647000000000000000000000000000000000000000000000000000000000000\n\t0000000000041000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF80740000000000000000000000000000000000000000000000000000008d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFBB1A00000000000000000000000000000000000000000000000000000000\n\t00000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000FF814600004d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE04F0000000000\n\t000000000000000000000000000000000000000000000000000000000000000A000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000002d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF060E00000000000000000000000000000000000000000000000000000000000000000000\n\t00000A04000000000000000000000000000000000000000000000000000000000000000000000000FFC6E100000000000000\n\t0000000000000000000000000000000000000000000000000000000000020400000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000ad0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0406000000000000000000000000000000000000000000000000000000000000000000000000FF6635000000000000000000\n\t0000000000000000000000000000000000000000000000000000000804000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF073C0000000000\n\t0000000000000000000000000000000000000000000000000000000000000012040000000000000000000000000000000000006d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFA6DA00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFB58D00000000000000000000000000000000000000000000000000000000000000ed0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FFC6E1000000000000000000000000000000000000000000000000000000000000000000000000\n\t0204000000000000000000000000000000000000000000000000000000000000000000000000FF66AC000000000000000000\n\t0000000000000000000000000000000000000000000000000000000404000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF75FB0000000000000000000000000000000000000000000000000000000000000000\n\t000000000006000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000001d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000004\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF66AC0000000000000000000000\n\t0000000000000000000000000000000000000000000000000004040000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFA6DA00000000000000000000000000000000000000000000000000000000000000000000\n\t00000004000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFA6DA0000000000000000000000000000000000000000000000000000000000000000005d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF93BA00000000000000000000000000000000000000000000000000000000000000000000\n\t00000002000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000dd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000002000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF80ED0000000000000000000000000000000000000000000000000000000000000000000000000400\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF80ED0000000000000000000000\n\t0000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF20A00000000000000000000000000000000000000000000000000000000000000000000000bd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000007d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF93BA000000000000000000000000000000\n\t0000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF20A00000000000000000000000\n\t000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000fd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000030040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFF23B000000000000000000000000000000020000000000000000000000000000000000000000000200000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF211A0000000000000000000000000000000200000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF93BA000000000000000000000000830040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000430040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF20A0000000000000000000000000000000\n\t0000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF20A0000000000000000000000000000000000000000000000000000000000000000000000000020000c30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000230040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FFA6DA00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF20A0000000000000000000000000000000000000000000000000000000000000000000000000020000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFA6DA000000000000000000000000000000\n\t000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000a30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000040004000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF75FB0000000000000000000000000000000000000000000000000000000000000000000000000006000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFC6E10000000000000000000000000000000000\n\t0000000000000000000000000000000000000002040000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF5D5B0000000000000000000000000000000000000000000000000000000000000000000000020004000000630040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF727100000000000000000000000000000000180000000000000000000000000000000000000000060000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF471100000000000000000000000000000000180000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF11DB00000000000000000000000000000000e30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF7271000000000000000000000000000000001800000000\n\t0000000000000000000000000000000006000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFA1500000000000000000000000000000000018000000000000000000000000000000000000000004000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFA1500000000000000000000000000000000018\n\t000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000130040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000080800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFA15000000000000000000000000000000000180000000000000000000000000000000000000000040000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF124A00000000000000000000000000000000180000\n\t0000020002000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF840E00000000000000000000000000000000180000000004000400000000000000100800000000040000000000930040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t4711000000000000000000000000000000001800000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF4711000000000000000000000000000000001800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF47110000000000000000000000000000000018000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFE474000000000000000000000000000000001800530040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF5FE70000000000000000000000000000002018000000000000\n\t0000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFD70D00000000000000000000000000000000180000000000000000000000000000000000000001000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF943000000000000000000000000000000000180000\n\t000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000d30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t0895000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF4711000000000000000000000000000000001800000000000000000000000000000000000000000000000000000000330040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF4711\n\t0000000000000000000000000000000018000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFB3F00000000000000000000000000000004008000000000000\n\t0000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF807400000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF821C0000000000000000000000000000000008000000b30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FFD08700000000000000000000000000000000000000000000000000\n\t00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t42F3000000000000000000000000000000000800000000000000000000000000000000000000080000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFDE56000000000000000000000000000000001000000000\n\t000000000000000000000000000000088200000000000000000000000000000000000000000000000000000000000000000000730040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80ED\n\t0000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF80740000000000000000000000000000000000000000000000\n\t0000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF81460000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000f30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF53550000\n\t0000000000000000000000000000000000000000000000000000000000000000000008020000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF20A000000000000000000000000000000000000000000000000000\n\t00000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FFB0AA000000000000000000000000000000400000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF7045\n\t0000000000000000000000000000004000000000000000000000000000000000000000000800000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF8E7A0000000000000000000000000000000000000000000000\n\t0000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000008b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF8E7A00000000000000000000000000000000000000000000000000\n\t00000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF8146000000000000000000000000000000000000000000000000cb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF80ED0000000000000000000000000000000000000000000000000000000000\n\t000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000FF16440000\n\t000000000000000000000000000AA00000000000000000000000000000000000000000020000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF807400000000000000000000000000000000000000000000000000\n\t00000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000FF002b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000001004000000000000000000000000000000000000000000000000000000000000000000000000FF807400000000\n\t0000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFED25000000000000000000000000000000154000000000000000000000\n\t0000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000FFC565\n\t0000000000000000000000000000000AA000000000000000000000000000000000000000000000000000000000000000000000ab0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFA6430000000000000000000000000000000000000000000000000000000000\n\t000000000000000C04000000000000000000000000000000000000000000000000000000000000000000000000FFA6DA0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFE2F90000000000000000000000000000000AA00000000000000000006b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF93BA00000000000000000000000000000000000000000000000000000000000000\n\t00000000000002000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFEED4000000000000000000000000000000000000000000000000000000\n\t0000000000000000000084000000000000000000000000000000000000000000000000000000000000000000000000FFA6DA00eb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000004000000000000000000000000000000000000000000000000000000000000000000000000FF36C6000000000000\n\t0000000000000000000000000000000000000000000000000000000000000104000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFC6E10000000000000000000000000000000000000000000000000000000000\n\t000000000000000204000000000000000000000000000000000000000000000000000000000000000000000000FFA6DA0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000001b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000002000040000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF93BA00000000000000000000000000000000000000000000000000000000000000\n\t00000000000002000000000000000000000000000000000000000000000000000000000000000000000000FF66AC00000000\n\t0000000000000000000000000000000000000000000000000000000000000000040400000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFA6DA000000000000000000000000000000000000000000000000000000009b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF2086000000000000000000000000000000200000000000000000000000000000000000\n\t0000200000000000000000000000000000000000000000000000000000000000000000000000000000FFB0AA000000000000\n\t0000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF43230000000000000000000000000000000000000000000000000000000000\n\t000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000FF1EDE0000005b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000003b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFD08700000000000000000000000000000000000000000000000000000000000000\n\t00000000000100000000000000000000000000000000000000000000000000000000000000000000000000FF08950000000000bb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF20A0000000000000\n\t0000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000007b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF20A00000000000000000\n\t0000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000fb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FFC0DA00000000000000000000000000400000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFC0DA000000000000000000000000004000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF93BA00000000000000070040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF68AE000000000000000000000000\n\t0000000000000000000000000000000000000000000000000280000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF68AE0000000000000000\n\t000000000000000000000000000000000000000000000000000000000280000000000000000000000000000000000000000000870040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF80ED00000000000000000000000000000000000000000000000000000000000000000000000004\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000470040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF81F2000000000000000000000000000000000000000000000000000000000000000000000800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF20A0000000000000000000000000\n\t0000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF93BA0000000000000000000000000000000000000000000000000000000000000000000000\n\t000002000000000000000000000000000000000000000000000000000000000000000000000000FF81F2000000000000000000c70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000006000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000270040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000048000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF75FB000000000000000000000000000000000000000000000000000000000000000000000000000600\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF75FB000000000000000000000000000000000000000000000000000000000000000000000000a70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FFA6CD0080000000000000000000000000000000000000000000000000000000000000000000000404000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFE5E700000000000000000000000000000000000000000000000000000000000000000000000001\n\t06000000000000000000000000000000000000000000000000000000000000000000000000FFC8E30000000000000000000000670040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF66BB00800000000000000000000000000000\n\t0000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000010000000000000000000000006000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFA6DA0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000170040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFA6DA00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF8A6F00000000000000000000000000970040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFBF0F000000000000000000000000000000000000\n\t0000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000570040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF807400000000000000000000000000000000000000000000000000000000000000000000000008000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000d70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF93BA000000000000000000000000000000000000\n\t0000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000370040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF814600000000000000000000000000000000000000000000000000000000000000000000000010000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF807400000000000000000000000000000000\n\t000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000b70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF5D20000000000000000000000000000000000000\n\t0000000000000000000000000000000000000800000000000000000000000000000000000800000000000000000000000000\n\t000000000000FF8074000000000000000000000000000000000000000000000000000000000000000000000000080000000000770040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF5D2000000000000000000000000000000000000000000000000000000000000000000000000008000000000000\n\t00000000000000000000000800000000000000000000000000000000000000FF7BED0000000000000000000000000000000000f70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF5D2000000000000000000000000000000000000000000000\n\t0000000000000000000000000000080000000000000000000000000000000000080000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF5D200000000000000000000000000000000000000000\n\t0000000000000000000000000000000008000000000000000000000000000000000008000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000008f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF7B\n\tED00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000\n\t00000000001000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000004f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000800000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF80740000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF81460000000000000000000000000000000000000000\n\t000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000cf0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF5D20000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000002f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFE24200\n\t0000000000000000000000000000000000000000000000000000000000000000000000100400000000000000000000000000\n\t0000001004000000000000000000000000000000000000FF8074000000000000000000000000000000000000000000000000\n\t0000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFD9340000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000\n\t000000000000000004000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000af0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000004000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF19\n\tDB00000000000000000000000000000000000000000000000000000000000000000000000008040000000000000000000000\n\t00000000000004000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFD934000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000ef0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFD9340000000000000000000000000000000000000000000000000000\n\t000000000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFD93400000000000000000000000000000000000000000000001f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFD93400000000000000000000000000000000000000000000000000000000\n\t00000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFD934000000000000000000000000000000000000000000000000\n\t0000000000000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000009f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFDA9A0000000000000000000000000000000000000000000000000000\n\t000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000FFDA\n\t9A00000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000005f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000df0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40003f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bf0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000200\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000007f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FFAC4D0000000000000000000000000000000000000000000000000000000000000000\n\t000000000002000000000000000000000000000000000002000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAC4D0000ff0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF41A9000000000000000000000000000000000000000000000000000000000000\n\t0000000000001800000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9DCF0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000808040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF243500000000000000000000000000000000000000000000000000000000000000000000\n\t00000482000000000000000000000000000000000002000000000000000000000000000000000000FF211A00000000000000\n\t0000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9DCF00000000408040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0200000000000000000000000000000000000000000000000000000000000000000000000000FF73BE000000000000000000\n\t0000000000000400000000000000000000000000000000000000000300000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000840000000000000000000000000000000000040000000000\n\t00000000000000000000000000FFC8E300000000000000000000000000000000000000000000000000000000000000000000\n\t00000480000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF20A000000000000000000000000000000000000000000000000000000000000000208040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FFB90F000000000000000000000000000000000000000000000000000000000000000000000000\n\t0204000000000000000000000000000000000004000000000000000000000000000000000000FF0126000000000000000000\n\t0000000000000000000000000000000000000000000000000000000184000000000000000000000000000000000004000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF913A000000000000a08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFD9340000000000000000000000\n\t0000000000000000000000000000000000000000000000000000040000000000000000000000000000000000040000000000\n\t00000000000000000000000000FFEE7F00000060000000000000000000000000000000000000000000000000000000000000\n\t00000004000000000000000000000000000000000204000000000000000000000000000000000000FFB90F00000000000000\n\t000000000000000000000000000000000000000000000000000000000002040000000000000000000000000000000000040000608040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FFD934000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004000000000000000000000000000000000004000000000000000000000000000000000000FF9B18000000000000000000\n\t0000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000202000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000e08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FFB3050000000000000000000000000000000000000000000000100000000500000000100000000506\n\t000000100000000110000000000000000006000000000000000000000000000000000000FFD9340000000000000000000000\n\t0000000000000000000000000000000000000000000000000000040000000000000000000000000000000000040000000000\n\t00000000000000000000000000FFD93400000000000000000000000000000000000000000000000000000000000000000000\n\t00000004000000000000000000000000000000000004000000000000000000000000000000000000FFD9340000000000000000108040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFE90B00000000000000000000000000\n\t0000000000000000000000000000000000000008000000028000000008000000008800000000000000000000000000000000\n\t0000000000000000000000FF35E2000000000000000000000000000000000000000000000000000000000000000000000000\n\t0006000000000000000000000000000000000006000000000000000000000000000000000000FFEA79000000000000000000\n\t000000000000000000000000000008000000020000000000000000000000000000000000000000000000000000000000000000908040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFC0980000000000000000000000000000000000000000000000000000000100000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000508040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF625500000000000000000000000000\n\t0000000000000000000000000000000000000000000000080000000000000000000000000000000000082000000000000000\n\t0000000000000000000000FF649C000000000000000000000000000000000000000000000000000000000000000000000000\n\t0040000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000d08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000000000\n\t0000000000000000000000000800000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFCDEC0000000000000000000000000000000000000000000000000000000000000000000000000020\n\t000000000000000000000000000000000020000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000308040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000009000000000000000000000000000000000009000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF7BED00000000000000000000000000\n\t0000000000000000000000000000000000000000000000100000000000000000000000000000000000100000000000000000\n\t0000000000000000000000FF5D2000000000000000000000000000000000000000000000000000000000000000000000000000b08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF7BED000000000000000000000000000000000000000000000000000000000000000000000000100000000000\n\t0000000000000000000000001000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFB1F60000000000000000000000000000000000000000000000000000000000000000000000000802\n\t000000000000000000000000000000000802000000000000000000000000000000000000FF7697000000000000000000000000708040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000002000000000000000000000000000000000000FF6B2C0000000000000000000000000000000000\n\t0000000000000000000000000000000000000001000000000000000000000000000000000001000000000000000000000000\n\t00000000000000FF17F500000000000000000000000000000000000000000000000000000000000000000000000002000000\n\t00000000000000000000000000000200000000000000000000000000000000000000FF5D2000000000000000000000000000\n\t000000000000000000000000000000000000000000000008000000000000000000000000000000000008000000000000000000f08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000020000020000000000000000000000000000000000001000000000000000000000000000000\n\t0000000000FF1F2A0000000000000000000000000000000000000000000000000000000000000000000000000C0200000000\n\t0000000000000000000000000C02000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF7F6C000000000000000000000000000000000000000000000000000000000000000000000000000000088040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF80030000000000000000000000000000000000000000000000000000000000000000000000000000100000000000\n\t000000000000000000000000000000000000000000000000000000000000FFC3E90000000000000000000000000000000000\n\t0000000000000000000000000000000000002010000000000000000000000000000000000010000000000000000000000000\n\t00000000000000FF7BED00000000000000000000000000000000000000000000000000000000000000000000000010000000\n\t00000000000000000000000000001000000000000000000000000000000000000000FF9FBA0000000000000000000000000000888040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000002000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFCEC8000000000000000000000000000000\n\t000000000000000000000000000000000040000000000000000000000000000000000000000000800000000000000000000000488040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000900000000000000000000000000000000000800000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFAC4D0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000020000000000000000000000000000000000020000000000000000000000\n\t00000000000000FF7B3D0000000000000000000000000000000000000000000000000000000000000000000000000002100600c88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF17F500000000000000000000000000000000000000\n\t0000000000000000000000000000000000020000000000000000000000000000000000020000000000000000000000000000\n\t0000000000FFBD4F000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000080000000000000000000000000000000000000FFCD3C00000000000000000000000000000000288040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000200000000000000000000000000000000000000FF0E94000000000000000000000000000000000000000000\n\t0000000000000000000000000000001006000000000000000000000000000000001006000000000000000000000000000000\n\t000000FF76970000000000000000000000000000000000000000000000000000000000000000000000000900000000000000\n\t000000000000000000000900000000000000000000000000000000000000FFD9340000000000000000000000000000000000\n\t000000000000000000000000000000000000000004000000000000000000000000000000000004000000000000000000000000a88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFC48F00000000000000000000000000000000000000\n\t0000000000000000000000000000000000080400000000000000000000000000000000080400000000000000000000000000\n\t0000000000FF17F500000000000000000000000000000000000000000000000000000000000000000000000002000000000000688040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tD934000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000\n\t0000000000000004000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFD934000000000000000000000000000000000000e88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000004000000000000000000000000000000000000FFD9340000000000000000000000000000000000000000000000\n\t0000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000000000\n\t00FF35E200000000000000000000000000000000000000000000000000000000000000000000000000060000000000000000\n\t00000000000000000006000000000000000000000000000000000000FFD93400000000000000000000000000000000000000\n\t000000000000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000188040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000FF\n\t4FDF000000000000000000000000000000000000000000000000000000000000000000000020000400000000000000000000\n\t0000080000000004000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFD934000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000988040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFD1F90000000000000000000000000000000000000000000000\n\t0000000000000000000000002000000000000000000000000000000000004000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF69FD0000000000000000000000000000000000000000588040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF1D45000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000d88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000100000000000000000000000000000000000100000000000000000000000000000000000000FF1997\n\t0000000000000000000000000000000000000000000000000000000000000000000000000082000000000000000000000000\n\t000000000082000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000388040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tB7B8000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000\n\t0000000000000200000000000000000000000000000000000000FF6B2C00000000000000000000000000000000000000000000b88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0400000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80A1\n\t8000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000788040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000440000000080000000000000000000000000000000000000000000000000000000000000000000FFAC4D0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000\n\t00000002000000000000000000000000000000000000FFFCCC00000000000000000000000000000000000000000000000000\n\t00000000000000000000000050000000000000000000000000000000000050000000000000000000000000000000000000FF\n\t2E3100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFC791000000000000000000000000000000000000000000000000000000\n\t0000000000000000440000000000000000000000000000000000000000000000000000000000000000000000000000FF8636\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000\n\t000000000000000000000000000000000000000000000000FF04C6000000000000000000000000000000000000000000000000048040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF80740000000000000000000000000000000000000000000000000000000000\n\t000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000FFBEB10000\n\t0000000000000000000000000000000000000000000000000000000000000000000000280000000000000000000000000000\n\t00000028000000000000000000000000000000000000FF6CA200000000000000000000000000000000000000000000000000\n\t00000000000000000000000802000000000000000000000000000000000002000000000000000000000000000000000000FF00848040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF2E31000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000448040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF77CE0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000200000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000c48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000002000000\n\t00000000000000000000000000000000FF17D500000000000000000000000000000000000000000000000000000000000000\n\t00000000008004000000000000000000000000000000000004000000000000000000000000000000000000FF8E7A00000000\n\t0000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00248040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000204000200000000000000000000000000000204000000000000000000000000000000000000FF3FDA000000000000\n\t0000000000000000000000000000000000000000000000000000000000000104000200000000000000000000000000000104\n\t000000000000000000000000000000000000FFDEEC0000000000000000000000000000000000000000000000000000000000\n\t0000000000000000A4000000000000000000000000000000000084000000000000000000000000000000000000FFA5F70000\n\t000000000000000000000000000000000000000000000000000000000000000000000220000000000000000000000000000000a48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFD93400000000000000000000000000000000000000000000000000000000000000\n\t00000000000004000000000000000000000000000000000004000000000000000000000000000000000000FFD93400000000\n\t0000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000\n\t0004000000000000000000000000000000000000FF430300000000000000000000000000000000000000000000000000000000648040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000400000000\n\t0000000000000000000000000000FF0460000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004000000000000000000000000000000000804000000000000000000000000000000000000FF35E2000000000000\n\t0000000000000000000000000000000000000000000000000000000000000006000000000000000000000000000000000006\n\t000000000000000000000000000000000000FF9DCF0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000FF409B000000e48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200000000\n\t000004000000000000000000000000000000000004000000000000000000000000000000000000FF5DEA0000000000000000\n\t00000000000000000000000000050004000000001000051008000000000C0005081000000000200004001000000000040000\n\t00000000000000000000000000000000FFD93400000000000000000000000000000000000000000000000000000000000000\n\t00000000000004000000000000000000000000000000000004000000000000000000000000000000000000FFD93400000000\n\t000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000148040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFE7C2000000000000000000000000000000000000000000000000000000000000008808\n\t0000000008000288080000000020000200080000000000000000000000000000000000000000000000FFD934000000000000\n\t0000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000004\n\t000000000000000000000000000000000000FF707D000000000000000000000000000000000000000000008000000000000800948040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF66AC0000000000000000\n\t0000000000000000000000000004000400000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000548040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF152E000000000000000000000000000000000000000000000000000000000000000000\n\t0000000880000000000000000000000000000000000800000000000000000000000000000000000000FF2C83000000000000\n\t000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000003200d48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000800000000000000000000000000000000000820000000000000\n\t000000000000000000000000FFF54C0000000000000000000000000000000000000000000000000000000000000000000000\n\t000012000000000000000000000000000000000002000000000000000000000000000000000000FFD34E0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000C00000000000000000000000000000000000080000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000348040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF0A5D00000000000000000000000000000000000000000000000000000000000000000000000008\n\t02000000000000000000000000000000000902000000000000000000000000000000000000FFAC4D00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000200000000\n\t0000000000000000000000000000FFD36B000000000000000000000000000000000000000000000000000000000000000000\n\t0000001048000000000000000000000000000000001000000000000000000000000000000000000000FF625500000000000000b48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000080000\n\t0000000000000000000000000000000900000000000000000000000000000000000000FFD540000800000000000000000000\n\t0000000000000000000000000000000000000000000000001000000000000000000000000000000000001400000000000000\n\t000000000000000000000000FF809C0008000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF152E0000000000000000\n\t000000000000000000000000000000000000000000000000000000000880000000000000000000000000000000000800000000748040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFC89200080000000000000000000000000000000000000000000000000000000000000000000000\n\t80000000000000000000000000000000000000000000000000000000000000000000000000FF20A000000000000000000000\n\t0000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFE68B00000000000000000000000000000000000000000000000000000000000000000000f48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FFD1A0000000000000000000000000000000000000000000000000000000000000008000000000000200\n\t0000000000000000000020000000000002000000000000000000000000000000000000FF3D1B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000A00000000000000000000000000000000000800000000000000\n\t000000000000000000000000FF77CE0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000200000000000000000000000000000000000000FF409B0000000000000000000c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000040000000100000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFEADA40080000000000000000000000000000000000000000000000000000000000000000800000\n\t00000000000000000000000000000080000000000000000000000000000000000000000000FFA6BE40000000000000000000\n\t0000000000000000000000000000000000000000000000010000080000000000000000000000000000008010080000000000008c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000018000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF7BED000000000000000000000000000000000000000000000000000000000000000000000000100000\n\t0000000000000000000000000000001000000000000000000000000000000000000000FF1962000800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000\n\t000000000000000000000000FF11190000000000000000000000000000000000000000000000000000000000000100000000004c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF5D200000000000000000000000000000000000000000000000000000000000000000000000000800000000\n\t000000000000000000000000000800000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF196100000010000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000080000000000000000000000000000000000FF404A0008000800000000000000cc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000000000\n\t00000000000000000000000404000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF744C200000000000000000000000000000000000000000000000000000000000000000000000000200\n\t0000000000000000000000000000000002000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000004000000000000000000000000000000000004000000000000000000000000\n\t000000000000FF12434000000000000000000000000000000000000000000000000000000000000000000000001004000000\n\t000000000000000000000000001004000000000000000000000000000000000000FF9D270008000000000000000000000000\n\t0000000000000000000000000000000000000000000008000000000000000000000000000000000008000000000000000000\n\t00000000000000000000FFD7A50000000000000000000000000000000000000000000000000000000000000000000000000200ac8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FFD93400000000000000000000000000000000000000000000000000000000000000000000000000040000000000\n\t00000000000000000000000004000000000000000000000000000000000000FFD93400000000000000000000000000000000\n\t0000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000000000\n\t0000000000000000FF33AC0000000000000000000000000000000000000000000000000000000000000000000000000C0400\n\t0000000000000000000000000000000A04000000000000000000000000000000000000FFD934000000000000000000000000006c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000004000000000000000000000000000000000000FF1939001000000000000000000000000000000000\n\t0000000000000000000000000000000000000004000000000000000000000000000000000004000000000000000000000000\n\t000000000000FFE09A8000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFF5410000000000000000000000000000\n\t000000000000000000000000000000000000000000000080000000000000000000000000000000000080000000000000000000ec8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000004040000000000000000000000000000000002040000000000000000000000000000\n\t00000000FFB79E00000000000000000000000000000000000000000000000000000000000000000000000000040000000000\n\t00000000000000000000000404000000000000000000000000000000000000FF6CEE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000008400000000000000000000000000000000008400000000000000000000\n\t0000000000000000FFB90F000000000000000000000000000000000000000000000000000000000000000000000000020400001c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF33CC800000000000000000000000000000000000000000000000000000000000000000000002800000000000000000\n\t0000000000000400000000000000000000000000000000000000000000FFAFA2000000000000000000000000000000000000\n\t0000000000000000000000000000000000000004000000000000000000000080000000000004000000000000000000000000\n\t000000000000FF809C0008000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF2E170000000000000000000000000000009c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000100000000000000000000000000000000000000000000000000FF99690000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000804000000000000000000000000\n\t00000000FF06AC80000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000400000000000000000000000000000000000000000000FFD5FA80000000000000000000000000000000\n\t0000000000000000000000000000000000000002800000000000000000000000000000000000000000000000000000000000005c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF3364000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000\n\t000000000000FFADB7000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF6B2C0000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000\n\t000000000000000100000000000000000000000000000000000000FFD0870000000000000000000000000000000000000000\n\t0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF1D4E80000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000080000000000000000000000000000000000000FF609D00000000000000000000000000000000003c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF80ED00000000000000000000000000000000000000000000\n\t0000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFE230100000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000bc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000400000000000000000000000000000000000200000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF269B8800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF809C00080000000000000000000000000000000000000000000000000000000000000000000000000000000000007c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF3F\n\t5100000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFB7B800000000000000000000000000000000000000fc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFBF0F0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000828040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF6B2C0000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000\n\t000000000000000100000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000428040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFF54100000000000000000000000000000000000000000000\n\t000000000000000000000000000000800000000000000000000000000000000000800000000000000000000000000000000000c28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000FFD93400\n\t0000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000\n\t0000000004000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000228040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFAE4F000000\n\t0000000000000000000000000000000000000000000000000000000000000000000084000000000000000000000000000000\n\t000024000000000000000000000000000000000000FFAE4F0000000000000000000000000000000000000000000000000000\n\t000000000000000000000084000000000000000000000000000000000024000000000000000000000000000000000000FFD7\n\tD200000000000000000000000000000000000000000000000000000000000000000000000000040800000000000000000000\n\t00000000000404000000000000000000000000000000000000FF20D70000000000000000000000000000000000000000000000a28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000004\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3B0400\n\t0000000000000000000000000000000000000000000000000000000000000000000000000608000000000000000000000000\n\t0000000406000000000000000000000000000000000000FF6860000000000000000000000000000000000000000000000000\n\t180000000000000000000000000400000000000000000000000000000000040400000000000000000000000000000000000000628040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF35E2000000\n\t0000000000000000000000000000000000000000000000000000000000000000000006000000000000000000000000000000\n\t000006000000000000000000000000000000000000FFB9780000000000000000000000000000000000000000000000000000\n\t000000000000000000000004080000000000000000000000000000000004000000000000000000000000000000000000FF2E\n\t310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFD85C00000000000000000000000000000000000000000000000000000002\n\t00000100000100000404000100000100000010000100000000000004000000000000000000000000000000000000FFD93400\n\t0000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000\n\t0000000004000000000000000000000000000000000000FFD93400000000000000000000000000000000000000000000000000128040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF96E1000000\n\t0000000000000000000000000000000000000000000000000200000000000000000200000080000080000008000080000000\n\t000000000000000000000000000000000000000000FFD9340000000000000000000000000000000000000000000000000000\n\t000000000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF4000928040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAC4D0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000\n\t02000000000000000000000000000000000000FF6D0B00000000000000000000000000000000000000000000000000000000\n\t00000100000100000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000528040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000800\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2E7D000000\n\t0000000000000000000000000000000000000000000000000000000000000000000808000000000000000000000000000000\n\t000808000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000d28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001000000000\n\t000000000000000000000000000000FF5D200000000000000000000000000000000000000000000000000000000000000000\n\t000000000800000000000000000000000000000000000800000000000000000000000000000000000000FFD0870000000000\n\t0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF33C60000328040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000800000000000000000000000000000000000800000000000000000000000000000000000000FFE8FA00000000000000\n\t0000000000000000000000000000000000000000000000000000000000088000000000000000000000000000000000088000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEBF1000000\n\t000000000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000b28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000800000000\n\t000000000000000000000000000000FF973B0000000000000000000000000000000000000000000000000000000000000000\n\t000000001002000000000000000000000000000000001002000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF5D200000000000000000000000000000000000000000000000000000000000728040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF6B2C00000000000000\n\t0000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000010000\n\t0000000000000000000000000000000000FF4E0A000000000000000000000000000000000000000000000000000000000000\n\t0000000000000200000000000000000000000000000000000400000000000000000000000000000000000000FF5D2000000000f28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t1002000000000000000000000000000000001002000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFB1F60000000000000000000000000000000000000000000000000000000000000000\n\t000000000802000000000000000000000000000000000802000000000000000000000000000000000000FFB7B80000000000\n\t0000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000002000a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF009700000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000400000000000000000000000000000000FF7BED00000000000000\n\t0000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000100000\n\t0000000000000000000000000000000000FF973B000000000000000000000000000000000000000000000000000000000000008a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000004a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF5D200000000000000000000000\n\t0000000000000000000000000000000000000000000000000008000000000000000000000000000000000008000000000000\n\t00000000000000000000000000FFF54100000000000000000000000000000000000000000000000000000000000000000000\n\t00000080000000000000000000000000000000000080000000000000000000000000000000000000FF609D00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FFF541000000000000000000000000000000000000000000000000000000000000000000000000\n\t0080000000000000000000000000000000000080000000000000000000000000000000000000FF17F5000000000000000000\n\t0000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000200000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000002a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF17F50000000000000000000000000000000000000000000000000000000000000000000000000200\n\t000000000000000000000000000000000200000000000000000000000000000000000000FFE2420000000000000000000000\n\t0000000000000000000000000000000000000000000000000010040000000000000000000000000000000010040000000000\n\t00000000000000000000000000FF5D2000000000000000000000000000000000000000000000000000000000000000000000\n\t00000800000000000000000000000000000000000800000000000000000000000000000000000000FFD9340000000000000000aa8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000020000\n\t00000000000000000000000000000002000000000000000000000000000000000000FFD93400000000000000000000000000\n\t0000000000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FF7F6C000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000002000000000000000000000000000000000000FF17AE000000000000000000\n\t0000000000000000000000000000000000000000000000000000000806000000000000000000000000000000000804000000006a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000004000000000000000000000000000000000004000000000000000000\n\t000000000000000000FFD9340000000000000000000000000000000000000000000000000000000000000000000000000004\n\t000000000000000000000000000000000004000000000000000000000000000000000000FF7F6C0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000\n\t00000000000000000000000000FFAC4D0000000000000000000000000000000000000000000000000000000000000000000000ea8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFD93400000000000000000000000000000000000000000000000000000000000000000000000000040000\n\t00000000000000000000000000000004000000000000000000000000000000000000FFD93400000000000000000000000000\n\t0000000000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FFD934000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004000000000000000000000000000000000004000000000000000000000000000000000000FFD934000000000000000000001a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFF230000000000000000000000000000000\n\t0000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF43730000000000000000000000000000000000000000000000000000000000000000000080000004\n\t000000000000000000000000000080000004000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000020000000000000000000000000001000000020000000000000000000000\n\t00000000000000FF035D00000000000000000000000000000000000000000000000000000000000000000000000000000001\n\t10000000000000000000000000000000000010000000000000000000000000000000FF961A00000000000000000000000000\n\t0000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFF230000000000000000000000000000000000000000000000000020000000000000000000000005a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF035D000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000110000000000000000000000000000000000010000000000000\n\t000000000000000000FF7F6C0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000002000000000000000000000000000000000000FF35C1000000000000000000000000da8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000400000000000000000000000000000000000000FFFB300000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000\n\t00000000000000FFBD4F00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000080000000000000000000000000000000000000FFD08700000000000000000000000000\n\t0000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000003a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000008200000000000000000000000000000000000200000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFEE47000000000000000000000000000000000000000000000000000000000000000000000000040000ba8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF2E310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000400000000000000000000000000000000000000FF20A00000000000000000000000000000000000\n\t0000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFE44300000000000000000000000000007a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF789C00000000000000000000000000000000000000\n\t0000000000000000010000000000000020000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF805A010000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF7E700100000000000000000000000000000000000000000000000000000000000000000000000028000000000000\n\t000000000000000000000028000000000000000000000000000000000000FF1C450000000000000000000000000000000000\n\t0000000000000000000001000000000000004000020000000000000000000000000000000000020000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000068040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFBEB1000000000000000000000000000000000000000000000000000000000000000000000000002800000000\n\t0000000000000000000000000028000000000000000000000000000000000000FF409B00000000000000000000000000000000868040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000468040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000020000000000000000000000000000000000020000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000c68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t17F5000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000\n\t0000000000000200000000000000000000000000000000000000FFD934000000000000000000000000000000000000000000\n\t0000000000000000000000000000000004000000000000000000000000000000000004000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFAC4D000000000000000000000000000000000000268040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000004000000000000000000000000000000000000FFAA230000000000000000000000000000000000000000000000\n\t00000000000000000000000000020C0000000000000000000000000000000802840000000000000000000000000000000000\n\t00FFFD4D000000000000000000000000000000000000000000000000000000000000000000000000000C0000000000000000\n\t00000000000000080084000000000000000000000000000000000000FFD93400000000000000000000000000000000000000\n\t000000000000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000a68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000800000000000000000000000000000000000800000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFD934000000000000000000000000000000000000000000\n\t0000000000000000000000000000000004000000000000000000000000000000000004000000000000000000000000000000\n\t000000FFD934000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000668040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFD934\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000\n\t000000000004000000000000000000000000000000000000FFC48F0000000000000000000000000000000000000000000000\n\t0000000000000000000000000008040000000000000000000000000000000008040000000000000000000000000000000000\n\t00FF35E200000000000000000000000000000000000000000000000000000000000000000000000000060000000000000000\n\t00000000000000000006000000000000000000000000000000000000FF5D200000000000000000000000000000000000000000e68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000004000000000000000000000000000000000000FFB5E600000000000000000000000000000000000000000000000000\n\t00000020000000000000200006000000000000000000000000000000000006000000000000000000000000000000000000FF\n\t4613000000000000000000000000000000000000000000000010000000044000000010008040044400000010010040044000\n\t0000100000000004000000000000000000000000000000000000FFE761000000000000000000000000000000000000000000\n\t000000004000000000000000000000000400000000000000000000000000000000000400000000000000000000000000000000168040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF982F0000000000000000000000000000000000000000000000\n\t0000000000000000000800800002200000000800802002200000000800000000000000000000000000000000000000000000\n\t00FFD9340000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000968040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t6B09000000000000000000000000000000000000000000000010004000040000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000568040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FFDF7C000000000000000000000000000000000000000000000000000000\n\t0000000000000000000200000000000000000000000000000000000008000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF38CB0000000000000000000000000000000000000000000000\n\t000000000000000000000000000AA0000000000000000000000000000000000808000000000000000000000000000000000000d68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000001100000000000000000000000000000000001100000000000000000000000000000000000000FF757B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000009500000000000000000000000000000\n\t00000940000000000000000000000000000000000000FF80AA00400000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tBA9700000000000000000000000000000000000000000000000000000000000000000000000000A00000000000000000000000368040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (CD3C00000000\n\t0000000000000000000000000000000000000000000000000000000000000000090000000000000000000000000000000000\n\t0800000000000000000000000000000000000000FFA0F4000000000000000000000000000000000000000000000000000000\n\t0000000000000000000800000000000000000000000000000000000880000000000000000000000000000000000000FF8346\n\t0040000000000000000000000000000000000000000000000000000000000000000000000050000000000000000000000000\n\t000000000040000000000000000000000000000000000000FF505A000000000000000000000000000000000000000000000000b68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000200\n\t000000000000000000000000000000000000FF76970000000000000000000000000000000000000000000000000000000000\n\t000000000000000900000000000000000000000000000000000900000000000000000000000000000000000000FFBBEA0008\n\t0000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000\n\t00001000000000000000000000000000000000000000FF809C00080000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00768040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000400000000000000000000000000000000000400000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF6C4A000800000000000000000000000000000000000000000000000000\n\t0000000000000000000002000000000000000000000000000000000002000000000000000000000000000000000000FF17F5\n\t000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000f68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000000\n\t0000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000800\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5D200000\n\t0000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000\n\t00000800000000000000000000000000000000000000FFEE4700000000000000000000000000000000000000000000000000000e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF709D400800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAD21008e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFACD2000800000000\n\t0000000000000000000000000000000000000000000000000000000000000002100000000000000000000000000000000002\n\t000000000000000000000000000000000000FF7BED0000000000000000000000000000000000000000000000000000000000\n\t000000000000001000000000000000000000000000000000001000000000000000000000000000000000000000FFE0D00008\n\t0000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000004e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF5D2000000000000000000000000000000000000000000000000000000000000000\n\t00000000000800000000000000000000000000000000000800000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000ce8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080200000000\n\t0000000000000000000000000000FF2E17000000000000000000000000000000000000000000000000000000000000000000\n\t0000000404000000000000000000000000000000000204000000000000000000000000000000000000FFAC4D000000000000\n\t0000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000002\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF989A2000002e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000C04000000000000000000000000000000000A04000000000000000000000000000000000000FFD9340000000000000000\n\t0000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000040000\n\t00000000000000000000000000000000FFFE9540000000000000000000000000000000000000000000000000000000000000\n\t00000000001006000000000000000000000000000000001006000000000000000000000000000000000000FF71F100080000\n\t000000000000000000000000000000000000000000000000000000000000000008020000000000000000000000000000000000ae8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFD934000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004000000000000000000000000000000000004000000000000000000000000000000000000FF629F000000000000\n\t0000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000104\n\t000000000000000000000000000000000000FF33AC0000000000000000000000000000000000000000000000000000000000006e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FFB90F0000000000000000000000000000000000000000000000000000000000000000000000\n\t000204000000000000000000000000000000000004000000000000000000000000000000000000FFD9340000000000000000\n\t0000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000040000\n\t00000000000000000000000000000000FF8E3080000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000400000000000000000000000000000000000000FF08950000000000ee8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF2E1700000000000000000000\n\t0000000000000000000000000000000000000000000000000000040400000000000000000000000000000000020400000000\n\t0000000000000000000000000000FF35E2000000000000000000000000000000000000000000000000000000000000000000\n\t0000000006000000000000000000000000000000000006000000000000000000000000000000000000FFACE9000800000000\n\t0000000000000000000000000000000000000000000000000000000000000084000000000000000000000000000000000084001e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000210000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF54708008000000000000000000000000000000000000000000000000000000000000000000\n\t208000000000000000000000000000000000660000000000000000000000000000000000000000FF50530000000000000000\n\t0000000000000000000000000000000000000000000000000000200000040000000000000000000000000000800000040000\n\t00000000000000000000000000000000FF809C00080000000000000000000000000000000000000000000000000000000000009e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF125600000000000000000000000000000000000000000000000000000000000000000000400000\n\t00000000000000000000000000000100000000000000000000000000000000000000000000FFDC2980001000000000000000\n\t0000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000008000000\n\t0000000000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF855F800000000000005e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000008000\n\t0000000000000000000000000000000100000000000000000000000000000000000000FF859A000010000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFF3FC0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000100000de8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFAC4D00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000200000000\n\t0000000000000000000000000000FF133F800000000000000000000000000000000000000000000000000000000000000000003e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF209D800800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFDBB8900000000000000000000000\n\t0000000000000000000000000000000000000000000000000400000000000000000000000000000000000200000000000000\n\t000000000000000000000000FFF5410000000000000000000000000000000000000000000000000000000000000000000000\n\t000080000000000000000000000000000000000080000000000000000000000000000000000000FF80FA008000000000000000be8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFB1D80880000000000000000000000000\n\t0000000000000000000000000000000000000000000004000000000000000000000000000000000002000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000002\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF7C7E000000000000000000000000000000000000000000020002000000000000000000000000000000\n\t0000000000000000000000000000000000400000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000fe8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF211A0000000000000000000000000000000200000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFE95300000000000000000000000000000000000000000004000400000000000000000000000000\n\t00000000000000000000000000000000000000400000000000000000000000000000000000FF81190006000000000000000000018040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000002000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000818040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF7B8D0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000480000880000000000000000000000002203200000080000000000\n\t00000000000000000000FF368D0000000000000000000000000000000000000008000000000000000000000000000000000000418040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF3209000000000000000000000000000000000000000000000000000000000000000000000000002800\n\t0088000000000000000000000000420420000008000000000000000000000000000000FFBD4F00000000000000000000000000c18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000404000000000000000000000000000000000000FF20A0000000000000000000000000000000000000\n\t0000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFD9340000000000000000000000000000000000000000000000000000000000000000000000000004000000\n\t000000000000000000000000000004000000000000000000000000000000000000FF06E40000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000180000000000000000000218040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000\n\t00000000FFB90F00000000000000000000000000000000000000000000000000000000000000000000000002040000000000\n\t00000000000000000000000004000000000000000000000000000000000000FFD93400000000000000000000000000000000\n\t0000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000000000\n\t0000000000000000FFB79E00000000000000000000000000000000000000000000000000000000000000000000000000040000a18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFB79E0000000000000000000000000000000000000000000000000000000000000000000000000004000000\n\t000000000000000000000000000404000000000000000000000000000000000000FFD934000000000000000000000000000000618040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000000\n\t000000000000000004000000000000000000000000000000000000FFD9340000000000000000000000000000000000000000\n\t0000000000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000\n\t00000000FFD93400000000000000000000000000000000000000000000000000000000000000000000000000040000000000\n\t00000000000000000000000004000000000000000000000000000000000000FFD93400000000000000000000000000000000\n\t000000000000000000000000000000000000000000040000000000000000000000000000000000040000000000000000000000e18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000400000000000000000000000000000000000400000000000000000000000000000000\n\t0000FF52A3000000000000000000000000000000000000000000020002000000000000000000000000000000000000000002\n\t0000000000000000000000000000000000000000000000000000000000FF189C000000000000000000000000000000000000\n\t000000050004000000001000051008000000000C000508000000040020000508400000000004000000000000000000000000\n\t000000000000FFA675000000000000000000000000000000000000000000000000000000000000000000000000000400000000118040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF632600000000000000000000000000000000000000000000000000000000000000880800000000080002882000\n\t00000020000288200000000000000000000000000000000000000000000000FFD9340000000000000000000000000000000000918040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000810000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF520A000000000000000000000000000000000000\n\t000000010000000000001000040000000000000000000000000000000000000000000000000000000000000000000000000000518040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFE29B0000000000000000000000000000000000000000000000000000000000000000000000000800000000000000d18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF7B\n\tED00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000\n\t00000000001000000000000000000000000000000000000000FF5D2000000000000000000000000000000000000000000000\n\t0000000000000000000000000000080000000000000000000000000000000000080000000000000000000000000000000000\n\t0000FFBF47000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000008000000000000000000000000000000000000FF409B00000000000000000000000000000000000000318040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000002000000000000000000000000000000000000FF5D20000000000000000000000000000000000000000000000000\n\t0000000000000000000000000800000000000000000000000000000000000800000000000000000000000000000000000000\n\tFF76970000000000000000000000000000000000000000000000000000000000000000000000000900000000000000000000\n\t000000000000000900000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000400000000000000000000000000000000000400000000000000000000000000000000000000FF5D\n\t2000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000\n\t00000000000800000000000000000000000000000000000000FF7BED00000000000000000000000000000000000000000000\n\t0000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000000000000\n\t0000FFAC4D00000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000718040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF77CE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000200000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF19970000000000000000000000000000000000000000000000000000000000000000000000000082000000000000000000\n\t000000000000000082000000000000000000000000000000000000FFEE47000000000000000000000000000000000000000000f18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t001000000000000000000000000000000000000000FF7BED0000000000000000000000000000000000000000000000000000\n\t000000000000000000001000000000000000000000000000000000001000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF9D5600000000000000000000000000000000000000000000\n\t00000000000000000000000000000C000000000000000000000000000000000008000000000000000000000000000000000000098040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF0097000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000\n\tFF7BED000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000898040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFA3CA000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000\n\t000000000200000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAC\n\t4D00000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000\n\t00000000000002000000000000000000000000000000000000FF83CC0000000000000000000000000000000000000000000000498040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000002\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5D2000\n\t0000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000\n\t0000000800000000000000000000000000000000000000FF2D53000000000000000000000000000000000000000000000000\n\t000000000000000000000000010000000000000000000000000000000000008000000000000000000000000000000000000000c98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000800000000000000000000000000000000000800000000000000000000000000000000000000FFD934000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000\n\t000004000000000000000000000000000000000000FF2D530000000000000000000000000000000000000000000000000000\n\t000000000000000000000100000000000000000000000000000000000080000000000000000000000000000000000000FF17\n\tF50000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000298040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (250000000000\n\t000000000000000000000000000000000000000000000000000000000000000804000000000000000000000000000000000C\n\t04000000000000000000000000000000000000FF20A000000000000000000000000000000000000000000000000000000000\n\t00000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000FFE24200\n\t0000000000000000000000000000000000000000000000000000000000000000000000100400000000000000000000000000\n\t0000001004000000000000000000000000000000000000FF5D2000000000000000000000000000000000000000000000000000a98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFAC4D000000000000000000000000000000000000000000000000000000000000\n\t0000000000000002000000000000000000000000000000000002000000000000000000000000000000000000FFD934000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000\n\t000004000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAA00698040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000006000000000000000000000000000000000006000000000000000000000000000000000000FFD9340000000000\n\t0000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000\n\t04000000000000000000000000000000000000FFD93400000000000000000000000000000000000000000000000000000000\n\t00000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000200\n\t0000000000000000000000000000000000FFD934000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FFD934000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000\n\t000004000000000000000000000000000000000000FF35E2000000000000000000000000000000000000000000000000000000198040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF51AE00000000000000000000000000000000000000000000000000000000\n\t00000000000000020004000000000000000000000000000200000004000000000000000000000000000000000000FFAC4D0000998040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFD96500000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008\n\t0000000000000000000000000000000000FFE89B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000080000000000000000000000000000000FFC801000000\n\t000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000020000598040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000\n\t000000000000000000000000000000FFE89B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000080000000000000000000000000000000FFD9650000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00080000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000d98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF80ED00000000000000000000000000000000000000000000000000000000000000000000\n\t00000400000000000000000000000000000000000000000000000000000000000000000000000000FF089500000000000000\n\t0000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBD4F00000000398040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0002000000000000000000000000000000000402000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF6B2C0000000000\n\t000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000100b98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000\n\t00000000000000000000000000FF77CE00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000200000000000000000000000000000000000000FF20A000000000000000\n\t0000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF62E680000000000000000000000000000000000000000000000000000000000000798040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FFAC21000000000000000000000000000000000000000000000000000000000000000000000000\n\t0208000000000000000000000000000000000000000000000000000000000000000000000000FF62FA004000000000000000\n\t0000000040000000000000000000000000000000000100000480000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF7F6C000000000000f98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF0C6C0000000000000000000000\n\t0000000000000000000000000000000000000000000000000004080000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFB5AC00400000000000\n\t000000000000400000000000000000000000000000000001000005000000020000000000000000000000000000000000020000058040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000010000000000000000000000000000000000010000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000858040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FFF5410000000000000000000000000000000000000000000000000000000000000000000000000080\n\t000000000000000000000000000000000080000000000000000000000000000000000000FF5B010020000000000000000000\n\t0000000000000000000000000000000000000000000000000000020000000000000000000000000000000002020000000000\n\t00000000000000000000000000FFEE2800200000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000400000000000000000000000000000000000000FF6B2C0000000000000000458040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000404000000000000000000000000000000000004000000000000000000\n\t000000000000000000FF80FA0080000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFD9340000000000000000000000\n\t0000000000000000000000000000000000000000000000000000040000000000000000000000000000000000040000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000258040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFD93400000000000000000000000000000000000000000000000000000000000000000000000000040000\n\t00000000000000000000000000000004000000000000000000000000000000000000FF194200000000000000000000000000\n\t0000000000000000000000000000000000000000000000040400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FF35E2000000000000000000000000000000000000000000000000000000000000000000000000\n\t0006000000000000000000000000000000000006000000000000000000000000000000000000FFD92300800000000000000000a58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000400000000\n\t0000000000000000000000000004000000000000000000000000000000000000FFD087000000000000000000000000000000\n\t0000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF515B0080000000000000000000\n\t000000000000000000000000000000000000000000000000000084000000000000000000000000000000000004000000000000658040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000060000000000000000000000000000000000060000000000000000000000\n\t00000000000000FFD93400000000000000000000000000000000000000000000000000000000000000000000000000040000\n\t00000000000000000000000000000004000000000000000000000000000000000000FFD93400000000000000000000000000\n\t0000000000000000000000000000000000000000000000000400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FF195500800000000000000000000000000000000000000000000000000000000000000000000000e58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFD934000000000000000000000000000000000000000000000000000000000000000000000000000400000000\n\t0000000000000000000000000004000000000000000000000000000000000000FFCFA6000000000000000000000000000000\n\t0000000000000000000000000000000020000080000004000000000000000000000000000000000004000000000000000000\n\t000000000000000000FF1D530000000000000000000000000000000000000000000000000400000000000040000110000004\n\t000040000120000000000080000000000004000000000000000000000000000000000000FF35E2000000000000000000000000158040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF4F6900000000000000000000000000\n\t000000000000000000000000000000000000000000080000000000200000A00000000000800000000000000000000000000000958040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000008D000000000000000000000000000000000080000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF65CE000000000000000000000000000000000000000000000000040000000000000000000000000000558040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF08950000000000000000000000000000000000000000000000000000000000000000000000000080000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFAC4D0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000020000000000000000000000000000000000020000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF68280000000000000000000000000000d58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF843100000000000000000000000000000000000000\n\t0000000000000000000000000000000000100000000000000000000000000000000000100800000000000000000000000000\n\t0000000000FFEF22000000000000000000000000000000000000000000000000000000000000000000000000082000000000\n\t0000000000000000000000000800000000000000000000000000000000000000FF73A1000000000000000000000000000000\n\t000000000000000000000000000000000000000000000800000000000000000000000000000000001000000000000000000000358040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000180000000000000000000000000000000\n\t000000FF5D200000000000000000000000000000000000000000000000000000000000000000000000000800000000000000\n\t000000000000000000000800000000000000000000000000000000000000FF152E0000000000000000000000000000000000\n\t0000000000000000000000000000000000000008800000000000000000000000000000000008000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000b58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF20A000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF5D2000000000000000000000000000000000000000\n\t0000000000000000000000000000000000080000000000000000000000000000000000080000000000000000000000000000\n\t0000000000FF7BED000000000000000000000000000000000000000000000000000000000000000000000000100000000000\n\t0000000000000000000000001000000000000000000000000000000000000000FF06E400000000000000000000000000000000758040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000C00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF2E310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000400000000000000000000000000000000000000FF3C510000000000000000000000000000000000\n\t000000000000000000000000000000000000000102000000000000000000000000000000000002000000000000000000000000f58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF9B6000000000000000000000000000000000000000000000000000000000000000000000000008020000000000000000\n\t00000000000000040802000000000000000000000000000000000000FF6C5700000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000\n\t0000000000FFF3FC0000000000000000000000000000000000000000000000000000000000000000000000000C0000000000000d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t20D7000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF1903000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000\n\t000000FFCF6D0000000000000000000000000000000000000000000000000000000000000000000000000000000400000000\n\t000000000000000000020000000400000000000000000000000000000000FF409B0000000000000000000000000000000000008d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF00D10000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000800000000000000000000000000000000000002000000000000000000000000000000\n\t00FF9A2A00000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000\n\t00000000000000000000000000000000000000000000000000000000FF7BED00000000000000000000000000000000000000\n\t0000000000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000000004d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF5D20000000000000000000000000000000000000000000\n\t0000000000000000000000000000000800000000000000000000000000000000000800000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF5D20\n\t0000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000\n\t000000000800000000000000000000000000000000000000FF2E170000000000000000000000000000000000000000000000\n\t0000000000000000000000000004040000000000000000000000000000000002040000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000002d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000104000000000000000000000000000000000000FFA4B400000000000000000000000000000000000000000000000000\n\t00000000000000000000000A04000000000000000000000000000000000804000000000000000000000000000000000000FF\n\tD934000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000\n\t0000000000000004000000000000000000000000000000000000FFD517000000000000000000000000000000000000000000\n\t000000000000000000000000000000100400000000000000000000000000000000120400000000000000000000000000000000ad8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0895\n\t0000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFD9340000000000000000000000000000000000000000000000\n\t0000000000000000000000000000040000000000000000000000000000000000040000000000000000000000000000000000\n\t00FF629F00000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000006d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF913A0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000840000000000000000000000000000\n\t00000004000000000000000000000000000000000000FFD7A500000000000000000000000000000000000000000000000000\n\t00000000000000000000000204000000000000000000000000000000000404000000000000000000000000000000000000FF\n\tC836000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000\n\t0000000000000086000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000ed8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000008000\n\t0004000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF1942\n\t0000000000000000000000000000000000000000000000000000000000000000000000000404000000000000000000000000\n\t000000000004000000000000000000000000000000000000FFEE610000000000000000000000000000000000000000000000\n\t0000000000000000000000000000040000000000000000000000000000000002040000000000000000000000000000000000001d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF961A0000\n\t0000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFADED00000000000000000000000000000000000000000000000000\n\t00000000000000000080010000000000000000000000000000000400000000000000000000000000000000000000000000FF\n\t95F2000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000009d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A8AF00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000\n\t0000000000000000000000000000000000000000FF0E36000000000000000000000000000000000000000000000000000000\n\t0000000000000000010002000000000000000000000000000500000002000000000000000000000000000000000000FF9C86\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000005d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FFBD4F0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000FF8E940000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000\n\t00000000000000000000000000000000000000000000FFA8AF00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000FF00dd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000100000000000000000000000000000000000080000000000000000000000000000000000000FF80ED00000000\n\t0000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFAC4D000000000000000000000000000000000000000000000000000000\n\t0000000000000000000002000000000000000000000000000000000002000000000000000000000000000000000000FF0895\n\t0000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000003d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000400\n\t000000000000000000000000000000000000FFAC4D0000000000000000000000000000000000000000000000000000000000\n\t000000000000000002000000000000000000000000000000000002000000000000000000000000000000000000FFAC4D0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000\n\t00000002000000000000000000000000000000000000FF2D530000000000000000000000000000000000000000000000000000bd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF058600000000000000000000000000000000000000000000000000000000000000\n\t00000000000100000000000000000000000000000000000500000000000000000000000000000000000000FF77CE00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0200000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEE0B007d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000000000\n\t0000000100000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF027A0000000800000000000000000000000000000000000000080000000400\n\t000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000002800000\n\t00000000000000000000000000000000FFC09100000000000000000000000000000000000000000000000000000004000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEC4800000000\n\t0000000000000000000000000000000000000000000000020000000000000000000200000000000000000000000000000000\n\t0002000000000000000000000000000000000000FF054400000010000000000000000000000000000000000000001000000000038040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020800000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC214000000838040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0004A0000000000000000000000000000000000208000000000000000000000000000000000000FF8C4B0000000000000000\n\t0000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF122500000000\n\t000000000000000000000000000000000000000000000000000000000000000002A00000000000000000000000000000000000438040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000088008000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFA140000000000000000000000000000000000000000000010000000000000000000000\n\t0000001002000000000000000000000000000000000002000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFB268000000000000000000000000000000000000000000000000000000000000c38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FFD7A50000000000000000000000000000000000000000000000000000000000000000000000\n\t000204000000000000000000000000000000000404000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFF17600000000000000000000000000000000000000000000000000000000000000\n\t00000000000084080000000000000000000000000000000004000000000000000000000000000000000000FFA8360000000000238040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t04080000000000000000000000000000000004000000000008000000000000000000000000FF7CD400000000000000000000\n\t0000000000000000000000010000000000000000000000000000000000000180000000000000000180000000000000000000\n\t0000000000000000000000000000FFFB2A000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004000000000000000000000000000000020204000000000000000000000000000000000000FF95A6000000000000\n\t000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000002000000a38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000100000080000000000000000000000004000000000000000000000000000000000004000000000008\n\t000000000000000000000000FF80030000000000000000000000000000000000000000000000000000000000000000000000\n\t000000100000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF8DD50000000000000000000000000000000000000000000000000080000000000000638040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF16EF00000000000000000000000000000000000000000000000000000000000000004000000004\n\t00000000400000000400000000000000000000000000000000000000000000000000000000FFD93400000000000000000000\n\t0000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000400000000\n\t0000000000000000000000000000FFD934000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004000000000000000000000000000000000004000000000000000000000000000000000000FF214900000000000000e38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000068000\n\t0000200000008208000000000000000000000000000000000000000000000000000000FF1E35000000000000000000000000\n\t0000000000000000000000000000000000800000000000000004000000000000000000000000000000000004000000000800\n\t000000000000000000000000FF14D20000000000000000000000000000000000000000000000080000000080800000000000\n\t000004000000000000000000000000000000000004000000000800000000000000000000000000FF94670000000000000000\n\t000000000000000000000000000000100000000140000000100000400084000000000000010010000000000000000004000000138040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000400000000000004000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF20A000000000000000000000000000000000000000000000000000000000000000000000000002\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFCB9500000000000000000000000000000000000000000000000000000000000000002800938040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF23CA000000000000000000000000000000000000000000000000000000000000000000000000080000\n\t0000000000000000000000000000000840000000000000000000000000000000000000FF0D45000000000000000000000000\n\t0000000000000000000000000000000000000000000000000020000000000000000000000000000000000008000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF0090000000000000000000538040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFCE440400000000000000000000000000\n\t0000000000000000000000000000000000000000000000200000000000000000000000000000000000080000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF8639000000000000000000000000000000000000000000000000000000000000000000000000100000\n\t0000000000000000000000000000001080000000000000000000000000000000000000FFD9FE000000000000000000000000\n\t0000000000000000000000000000000000000000000000000800000000000000000000000000000000000920000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000338040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF809C0008000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF5D200000000000000000000000000000\n\t0000000000000000000000000000000000000000000008000000000000000000000000000000000008000000000000000000\n\t00000000000000000000FF5D2000000000000000000000000000000000000000000000000000000000000000000000000008\n\t00000000000000000000000000000000000800000000000000000000000000000000000000FF839A0400000000000000000000b38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF5D20000000000000000000000000000000000000000000000000000000000000000000000000080000\n\t0000000000000000000000000000000800000000000000000000000000000000000000FFBBEA000800000000000000000000\n\t000000000000000000000000000000000000000000000000100000000000000000000000000000000000100000000000000000738040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000800000000000000000000000000000000000800000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF809C0008000000000000000000000000000000000000000000000000000000000000000000000000f38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF5F5840080000000000000000000000000000000000000000000000000000000000000000000010000000000000\n\t00000000000000000000201000000000000000000000000000000000000000FFF80640000000000000000000000000000000\n\t0000000000000000000000000000000000040004100000000000000000000000000000010040100000000000000000000000\n\t0000000000000000FF5E7F000000000000000000000000000000000000000000000000000000000000000000000040000000\n\t0000000000000000000000080000000000000000000000000000000000000000000000FF5D20000000000000000000000000000b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010000000000\n\t0000000000000000000000000000000000000000000000000000000000FFB09D000800040000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFA5410000000000000000000000000000000000000000000000000000000000000000000000200000000000\n\t000000000000000000100000000000000000000000000000000000000000000000FFAB700000000000000000000000000000\n\t0000000000000000000000000000000000000002000200000001000000000000000000000000800000000000000000000000008b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000004000000000000000000000000000000000002000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE09400080000000000800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF5E3F000000020000008000000000000000000000000000000000000000000000000000000000000000004b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF85212000000000000000000000000000000000000000000000000000000000000000000000000800000000\n\t000000000000000000000000000800000000000000000000000000000000000000FFB7B8000000000000000000000000000000cb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000001004000000000000000000000000000000000000FF04880008000000000000000000000000000000000000\n\t0000000000000000000000000000000008040000000000000000000000000000000008040000000000000000000000000000\n\t00000000FF27A440000000000000000000000000000000000000000000000000000000000000000000000002040000000000\n\t00000000000000000000000404000000000000000000000000000000000000FF17F500000000000000000000000000000000\n\t0000000000000000000000000000000000000000020000000000000000000000000000000000020000000000000000000000002b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000040600000000000000000000000000000000000600000000000000000000000000000000\n\t0000FFAA25000000000000000000000000000000000000000000000000000000000000000000000000080400000000000000\n\t0000000000000000000C04000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF8279000000000000000000000000000000000000000000000000000000000000000000000000120400000000ab8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFE09A8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFEE6100000000000000000000000000000000000000000000000000000000000000000000000000040000000000\n\t00000000000000000000000204000000000000000000000000000000000000FFF59400000000000000000000000000000000006b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF8E5A00000000000000000000000000000000000000000000\n\t0000000000000000000000000000020400000000000000000000000000000000020400000000000000000000000000000000\n\t0000FF77E8000000000000000000000000000000000000000000000000000000000000000000000000040400000000000000\n\t0000000000000000000404000000000000000000000000000000000000FFF5EF001000000000000000000000000000000000\n\t000000000000000000000000000000000000000600000000000000000000000000000000000600000000000000000000000000eb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000004000000000000000000000000000000000004000000000000000000000000000000000000\n\tFF77990008000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000\n\t000000000000000404000000000000000000000000000000000000FFB90F0000000000000000000000000000000000000000\n\t0000000000000000000000000000000002040000000000000000000000000000000000040000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFE0\n\t9A80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFD934000000000000000000000000000000000000009b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFAC4D0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000020000000000000000000000000000000000020000000000000000000000000000005b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000FF8E\n\t3080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000400000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFEE470000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000\n\t000000000000000400000000000000000000000000000000000000FF20A00000000000000000000000000000000000000000003b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000400000000000000000000000000000000000000FF80A18000000000000000000000000000000000000000000000000000\n\t000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000FF80\n\t9C00080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF820B10000000000000000000000000000000000000000000\n\t000000000000000000000000000002000000000000000000000000000000000004000000000000000000000000000000000000bb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAC4D00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000\n\t0000000002000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFE2301000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFFA1D000000\n\t00000000000000000000000000000000000001000000000000100004000000000D0002000000000000000000000000000000\n\t000002000000000000000000000000000000000000FF522E0000000000000000000000000000000000000000000000000000\n\t000000000000000000000038000400000000000000000000020400000088000100000000000000000000000000000000FF78\n\t3000000000000000000000000000000000000000000000800000000000080004000000000B00080002000000000000000000\n\t00000200000000000080000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000fb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFAC4D00000000000000000000000000000000000000000000000000000000\n\t00000000000000000002000000000000000000000000000000000002000000000000000000000000000000000000FF6F6700\n\t0000000000000000000000000000000000000000000000000000000000000000000000083000000000000000000000000000\n\t0000000110000000000000000000000000000000000000FFF7ED000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000078040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000210000000000000000000000000000000000200000000000000000000000000000000000000FFD6BF002000\n\t0000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000400\n\t000040000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80\n\t740000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000878040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (310000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004\n\t00000000000000000000000000000000000000FF64B900200000400400000000000000000000000000000008400001000100\n\t00000000000000158000000800000000000000000000000200000020000000000000000000000000000000000000FFFFC900\n\t0000000000000000000000000000000000000000080000000000000000000000000000020800080000000000000000000000\n\t0000000000000000000000000000000000000000000000FF4EF400000000000000000000000000000000000000000000000000478040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800000400\n\t0020000000000000000000000000000000FF9D90000000000000000000000000080000000000000020000024000000000000\n\t0000000180140000198A98000000000000000000000008000180000020000000000000000000000000000000FF3797000000\n\t0040040000000000000000000000000000000040000100008000000020000000010000001000000000000000000000000000\n\t000000000000000000000000000000000000000000FF009E0000000000000000000000000000000000000000000000028000\n\t000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2E00c78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00040002008400020000000000000000000000008000008C000000000000000000000000000000000000FF2D9F0000000000\n\t0000000000000000000000000000000000000000000000000000000002000000040000000000000000000000000000000004\n\t04000000000000000000000000000000000000FF20A000000000000000000000000000000000000000000000000000000000\n\t00000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000FF050A00\n\t000000000000000000000008000000000000002000002100000000000000000000000000040002800000000000000000000000278040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000002080002000000008000000000000024000400002008800000000000000000000000008600\n\t0000080080000000000000000000000000FFB81A00000000010000000000000000000200000000000000004800C000000000\n\t0000000000000547941C00000000000000000000000000000004000000000000000000000000000000000000FF5A43000000\n\t0000000000000000000000000000000000000000000000000000000000000000000284000200000000000000000000000080\n\t00050C000000000000000000000000000000000000FF9D2D000000000000000000000000000000000000000000000000000000a78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004000000\n\t000000000000000000000000000000FF558C0000000001000000000000000000000000000000020006420040000000000000\n\t000000000006100020088000000000000000000000000086000000080000000000000000000000000000FF3B9C0000000000\n\t0000000000000000000400000000000010060001000001000000000000004005400402000000000000000000000000000000\n\t02000000000000000000000000000000000000FF15AB00000000000000000000000000000000000000000000001000000000\n\t00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000FF6C370000678040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100005100C00\n\t0000000C000020080000000020400480000000000004000000000000000000000000000000000000FFAFD500000000000000\n\t0000000000000000000000000000002E00000000000000000000008000000400040000040000000000000040000000000600\n\t0000000000000000000000000000000000FF539F000000000000000000000000000000000000000000000600000000000000\n\t0000000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF539F000000\n\t000000000000000000000000000000000000000600000000000000000000000000000400000000000000000000000000000000e78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000060000000000000002080A0080000008200220080200000020200280200000000000000000\n\t000000000000000000000000000000FFF5160000000000000000000000000000000000000000000806000000000000000000\n\t000000000004000000000000000000000000000000000004000000000000000000000000000000000000FF79300000000000\n\t00000000000000000000000000000000088E0000000002080000800000000000044000000000000000000000000000000000\n\t04000000000000000000000000000000000000FFCA6D0000000000000000000000000000000000000000000506040000000400178040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020000000000\n\t00000000000000000000000000FF1FDC00000000000000000000000000000000000000000004460400000000000000000000\n\t00000800000000000000000000000000000000000000000000000000000000000000000000000000FF0BED00000000000000\n\t0000000000000000000000000000000600000000000000000000000000100000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFCA30000000000000000000000000000000000000000000000600000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFD1000000000978040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFBA5E000000000000000000\n\t00000000000000000000000010160000000000000000000000000008C0000000000000000000000000000000000800000000\n\t000000000000000000000000000000FFF5C70000000000000000000000000000000000000000000006000000000000000000\n\t000000000000000000000000000000000000000000000002000000000000000000000000000000000000FF26E60000000000\n\t000000000000000000000000000000000006000000000000000000000000000002000000000000000000000000000000000000578040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000A0000000000000000000000000000200000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF089500000000000000000000000000000000000000000000000000000000000000000000\n\t00000080000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFCA3000000000000000000000000000000000000000000000060000000000000000d78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FFCA30000000000000000000000000000000000000000000000600000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFD6C6000000000000000000\n\t0000000000000000000000001202000000000000000000000000001000000000000000000000000000000000001000000000\n\t000000000000000000000000000000FFAE650000000000000000000000000000000000000000000400000000000000000000\n\t000000000800000000000000000000000000000000000800000000000000000000000000000000000000FF2D67000000000000378040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001000\n\t000000000000000000000000000000001000000000000000000000000000000000000000FF9DBE0008000000000000000000\n\t0000000000000000000008000000000000000000000000000000000000000000000000000000000000000001000000000000\n\t00000000000000000000000000FF6CB700000000000000000000000000000000000000000000020000000000000000000000\n\t00000880000000000000000000000000000000000800000000000000000000000000000000000000FFBF1000000000000000\n\t000000000000000000000000000000040000000000000000000000000008020000000000000000000000000000000008820000b78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000080000000000000000000000000000008000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF8629000000000000000000000000000000000000000000080000000000000000000000000000\n\t0200000000000000000000000000000000000000000000000000000000000000000000000000FF5D20000000000000000000\n\t0000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000800000000\n\t000000000000000000000000000000FF7B1B000800000400000000000000000000000000000000000000000000000000000000778040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF42CB0000000002000000000000000000000000000000000004000000000000000000000000000C02\n\t000000000000000000000000000000000802000000000000000000000000000000000000FF9F8B0000000000000000000000\n\t0000000000000000000008020000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF196400000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000600000000000000000000000000000000000000FF6E1B0008000000000000f78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000140000000000000000000000000000000000FF7D8C40080000000000000000000000\n\t0000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFD36F400000000000000000000000002000000000000000100208000000000000000000000000\n\t0800000000000000000000000000000000000800000000000000000000000000000000000000FF0B11000000000000000000\n\t0000000000000000000000000006000000000000000200000000000000000000000000000000000000000000000000000000000f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000060000000000000000000000000010000000A0000000000000000000000000001000000000000000000000\n\t000000000000000000FF8DB30008000000000000000000000000000000000000000000000000000000000000000000000400\n\t000200000000000000000000000000000000000000000000000000000000000000000000FF82DA0000000000000000000000\n\t0000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF0CC400000000000000000000000000200000000000000000020800000000000000000000008f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFCA3000000000000000000000000000000000000000000000060000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF354500000000000000000000000000\n\t0000000000000000000600000000000010000000000000020000020004000000000000000000000000000008000000000000\n\t0000000000000000000000FFC8BE000880000000000000000000000000000000000000000600000000000008000000000000\n\t00000000A0020000000000000000000000000000040000000000000000000000000000000000FFBAC5000080000000000000004f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFBCED200000000000000000000000000000\n\t0000000000000006000000000000000000000000000400000000000000000000000000000000000400000000000000000000\n\t000000000000000000FF26D000000000000000000000000000000000000000000002AE000000000000000000000000000002\n\t000000000000000000000000000000000002000000000000000000000000000000000000FFD78B0000000000000000000000\n\t000000000000000000000006000000000000000000000000000800000000000000000000000000000000000800000000000000cf8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000002AE0000000000000000000000000010040000000000000000000000000000000010040000000000000000000000\n\t00000000000000FF178C00080000000000000000000000000000000000000000060000000000000000000000000008000000\n\t00000000000000000000000000000800000000000000000000000000000000000000FF53F300000000000000000000000000\n\t0000000000000000055600000000000000000000000000000400000000000000000000000000000000000400000000000000\n\t0000000000000000000000FFCA0600000000000000000000000000000000000000000002AE00000000000000000000000000002f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFAE4B000000000000000000000000000000000000000000000600000000000000000000000000000400000000\n\t0000000000000000000000000084000000000000000000000000000000000000FFE0F8000000000000000000000000000000\n\t0000000000000006000000000000000000000000000C04000000000000000000000000000000000C04000000000000000000\n\t000000000000000000FF539F0000000000000000000000000000000000000000000006000000000000000000000000000004\n\t000000000000000000000000000000000004000000000000000000000000000000000000FF98DE400000000000000000000000af8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000004000000000000000000000000000000000000FF9F678000000000018000000000000000000000\n\t0000000000060000000000000000000000000000020000000000000000000000000000000000020000000000000000000000\n\t00000000000000FF5A1A00000000000000000000000000000000000000000002AE0000000000000000000000000001000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF1B9100000000000000000000000000\n\t0000000000000000000600000000000000000000000000008400000000000000000000000000000000000400000000000000006f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000002AE00000000000000000000000000000400000000000000000000000000000000040400000000000000000000000000\n\t0000000000FF7F4A000000000001000000000000000000000000000000000600000000000000000000000000000400000000\n\t0000000000000000000000000084000000000000000000000000000000000000FF2A12000000000001800000000000000000\n\t00000000000002AE000000000000000000000000000204000000000000000000000000000000000004000000000000000000\n\t000000000000000000FF42FF001000000001000000000000000000000000000000055600000000000000000000000000000400ef8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF6DE00000000000018000000000000000000000000000000006000000000000000000000000000004000000000000\n\t000000000220000000000004000000000000000000000000000000000000FFFF610008000000018000000000000000000000\n\t0000000000060000000000000000000000000000020000000000000000000000000000000000020000000000000000000000\n\t00000000000000FFBD3C00000000000180000000000000000000000000000000060000000000000000000000000004040000\n\t00000000000000000000000000000204000000000000000000000000000000000000FF248300000000000180000000000000001f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000080400000000000000000000000000000000FF55D280000000000180000000000000000000000000\n\t0000000600000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000\n\t0000000000FF25FC800000000001800000000000000000000000000000184600000000000000000000000000800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFEE67800000000001800000000000000000\n\t0000000000000006000000000000000000000000008000000000000000000000000000000058000000000000000000000000009f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0006000000000000000000000000080000020108008000000000000000000000000000000000000000000000000000000000\n\t000000FFFDB10000000000018000000000000000000000000000000006000000000000000000000000080000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF3E230000000000018000000000000000000000\n\t0000000000460000000000000000000000000000000200080080000000000004400000000000000000000000000000000000\n\t00000000000000FFCD4400000000000180000000000000000000000000000000060000000000000000000000000000003001005f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFC90700000000000180000000000000000000000000000000000000000000000000000000000001000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFF91A80000000000180000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF68B5000000000001800000000000000000000000000000000600000000000000000000000000000050000000\n\t0000000000000000000000000000080200000000000000000000000000000000FFAA4500000000000180000000000000000000df8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FFF6BC0000000000AA800000000000000000000000000000\n\t12AA000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF880B0800000000000000000000000000000000000000000000000000000000000000000000000200000000000000\n\t000000000000000000000400000000000000000000000000000000000000FF2DCE0000000000AA8000000000000000000000\n\t0000000002AA0000000000000000000000000001000000000000000000000000000000000001800000000000000000000000003f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF36358800000000AA8000000000000000000000000000001AAA0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFD52700080000000000000000000000000000000000\n\t0000080400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFC7EC00000000015580000000000000000000000000000005560000000000000000000000000000000000000000bf8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t8029000000000000000000000000000200000000000000000080000000000000000000000000000200000000000000000000\n\t0000000000000002000000000000000000000000000000000000FFDD16000400000000000200000000040000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF17F50000000000000000000000000000000000000000000000000000000000000000000000000200000000000000\n\t000000000000000000000200000000000000000000000000000000000000FF409B0000000000000000000000000000000000007f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000280000000000000000000000000000000000000FF8B120000018018018004010000000010018000000000000006\n\t0074060000000000000000000060004000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF046400000000120000000100000000100100000000000018040000040000000000000000000000000000200000000000\n\t00000000000000000000000000000000000000000000000000000000FFDB97000000800800800000800000000C0080000000\n\t000000030032020000000000000000000020004000000000000000000000000000000000000000000000000000000000000000ff8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000804000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t8557000200800000800000000000020000000000000000000A00200200000000000000000000228080000000000000000000\n\t0000000000000280000000000000000000000000000000000000FFCE88000000601000000001000000001001000000000000\n\t1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF3CA3000000800A00800400800000400800800000000000100A00200200000000000000000100228106004000000000004040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF997C\n\t000001C01A000004000000000018010000000000000006006006000000000000000000800001000000000000000000000000\n\t000008000000000000000000000000000000000000000000FF37E10000018018010000000000000018018000000000000006\n\t0060060000000000000000000040000000000000000000000000000000000004000000000000000000000000000000000000\n\t00FF596300000180000180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFCDFB0000018000018004000000004000000000000000804040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000200000A0000000000000000000000000000000FF6CD0000001A01C0080000000000000120000000000000000060040\n\t06000000000000000001004000000000000000000000000000000008000000000000000000000000000000000000000000FF\n\t5A4D000101A01800010014004000111801800000000010010650680604010004000000001001004001000000000000000040\n\t0100100010100200000000040400000000000000000000000000FF5F56000001801801000000000000001801000000000000\n\t000600680600000000000000000000400200000000000000000000000000000000000200000000000000000000000000000000404040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (990600400640\n\t00002080000000800A4006240088080000000020000020000000000006000000080000000000000000000000000000FFB65B\n\t002001C01803810000020000001000800000000010800642C006000018288200180080000140220088080000000020478120\n\t000010000000980000280400000000000000000000000000FFE15C00210180580080001400400000104C0000000000000006\n\t14C0060401000A02000000100140000100000000000000000000001000000800410000A04400000000000000000000000000\n\t00FFEB0000000181580180000000000000104C8000000000000006004006200000000000000000146100800000000000000000c04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFDE060000\n\t018010018000018000000006008000000000000A060040060000000000000000000065000000000000000000000000000000\n\t00000400000000000000000000000000000000000000FF580000000180100080040180000060000000000000000000060048\n\t06000000000000000000004286000000000000000000000000000000000206000000000000000000000000000000000000FF\n\t4427000001801001800401000000000200800000000000000600400600000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF157500000181100280000102000011000000000000000000204040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF961E000001001820800000000000400801800000000000040608700602\n\t8000000000000000024204000020000000000000000080000000000084028000000000000000000000000000000000FF3126\n\t0000018018118000528100000009418000100001800406216006100040328000000100016000900000040400000000010030\n\t010100000000201C00420400100000000000000000000000FF6091000001401A008000008000000008010000000000001006\n\t006006000000000000000000004006000000000000000000000000000000000006000000000000000000000000000000000000a04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006000000\n\t000000000000002000006000000000000000000000000000000000000000000000000000000000000000000000FFFB480000\n\t0080183000004001000180045180000000000000060060061008002000000000000020040040000400000000000000100101\n\t00000104028000000400000000000000000000000000FF8951000001801801800004000001C0020080001000000002061160\n\t06050840140000000100052400104000000200000000010140000000000000200200240000080000000000000000000000FF\n\tD5E7000001A01A0180001000000000090900000000000000064060060000000100000000001860008000400000000000000000604040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3E9E000400C0\n\t1010000000000001800400000000000000000600744600000000004000011000000600408000000800010010014000000000\n\t0006000400000000000000000000000000000000FF5328000001801001800000000001800001000000000000000600608600\n\t0000000000000000000000004000000400000000000000000000000400000000000000000000000000000000000000FFF1E5\n\t0000008018000000000000018000018000000000000006006006000000000000000000002004006000000000000000000000\n\t000000000004000000000000000000000000000000000000FF429A000001801801800400000001800001800000000000000600e04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (500000000000\n\t000000000000000000000000000000000000FFCE780000018018018000000040018000018000000001001006007006000000\n\t000000000008006000004080000208000000000000100000000200000000000000000000000000000000000000FF3BB70002\n\t00A01000000000000001C0000000000000010010060060060000000004000100000060541004004108000000081000802000\n\t00000004000800000000000000000000000000000000FF9C8800000180120980000020000180000000000000000000060062\n\tA6000000000000000000806000006000000800000000080020000000000000000A00800000000000000000000000000000FF00104040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00000000004000004000000000000000000000000000000000000000000000000000000000000000000000FF49C700000080\n\t1800000000002001800001000000000000000680600600000000004000010000000000600000000000010000010000000000\n\t0000000000000000000000000000000000000000FF141B000001C01801800000000001800001800000000000180600600600\n\t0000000000000000000000000400400000000000100000000000000000000000000000000000000000000000000000FF655F\n\t000000801A00000000000001800001800000000000000600600600000000040001000080602810400001000000001000010000904040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001001801\n\t8000840000018000C08000000000000886006006000000000000000000004000140000000000000000000000000000000000\n\t000000000000000000000000000000000000FFFA00000200201A000000840002518002D0000000000040008740E226000000\n\t0000000000008C4800848000000000000000000000000000000800000000000000000000000000000000000000FFAB3B0002\n\t41201809800040408001D4040400000000000002261060860000000000000000000040002040000000000000000000000000\n\t00000000000001020000000000000000000000000000FF48120002000018000000000000018000000000000000000006807800504040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000008000000\n\t00410000000000000000000000000000FFE1E100000180500080000000800080000180000000000010020031020000000000\n\t00000000182000612000000000000000000000000000000000000000000000000000000000000000000000FF836900000184\n\t0001800020000020200401000000000000000048020000000000000000000000000200400000000000000000000000000000\n\t0002000000020000000000000000000000000000FF701B0000019000018000100000001E040000000000000000002088A000\n\t0000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000FF2DF400d04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000828800000000000000000000000000000000000800000000000000000000000000000000000000FFD171000001085801\n\t80000A0000118A00210000000000000806206106000000000000000000046000026000000000000000000000000000000000\n\t000000008000000000000000000000000000FFA4A4000400C40C02800200000402A10080800000000000000300280A000000\n\t00000000000130300148A000000000000000000000000000001000000000200000000000000000000000000000FFA6C50002\n\t2020020C00040200001C01012A0000000000201220801010000000000000000000C40800028000000000000000000000000000304040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004004000000\n\t0000040020000400000000000000010000000000000000000000000010010000000000000000000000000000000010000000\n\t01000000000000000000000000000000FF91100000AA0880AA0000800000000880000000000000800AA82282A80000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF71CD00020020\n\t4A008002502002008400908000000000000002902802000000000000000000B0280080200000000000000000000000000000\n\t0800000000800000000000000000000000000000FFBDC700020122120000000400000000422500000000000000048040040000b04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF10A8000000002000000010000000400010000000000080000001100000000000000000\n\t0000340000000000000000000000000000000000000000000000000000000000000000000000000000FFE7F90000AA0AA12A\n\t0000AA0000000AA08800000000000012A82A82A8000000000000000000148000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFA33A0003543303540003242002001541440000000000001550CC0550000000\n\t000000000000810800800000000000000000000000000000000800000000800000000000000000000000000000FFBC69000400704040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000280\n\t006000006000000000000000020200000280000000200020006000000000000000000000000000FFD9AD0002002013000000\n\t0500020000524200000000000040048008040000000000000000000288008000000000000000000000000000000008000000\n\t01000000000000000000000000000000FF344500000080080080002080080080080000000000000028020020020000000000\n\t00000000302000002000000000000000000000000000000000000000002000000000000000000000000000FFDE730000AA0A\n\tA02A0000880000008A84C800000000000002A82A92A80000000000000000004000000000000000000000000000000000000000f04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000080000100\n\t0C00901000000000000000220200200200002000000000000000200000201001000000000000000000000000000000000000\n\t2000000000000000000000000000FFBF2F000420401000000400000000400400000000000100100900100000000000000000\n\t0000000000000000000000000000000000000200000000000001000000000000000000000000000000FF6843000400C00800\n\t800400800800C00C000000000001003203003002000020000000000000002800002000000000000000000000000000000800\n\t000001002000000000000000000000000000FFA61E004041801801802001801801801800000000000000601600600600000000084040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000004008\n\t000000000000000000000000FF0EF6000001801800800000801001801800000000000000600600C086000000000000000000\n\t005000008010010000000000000000008000001000000000004010000000000000000000000000FFD9390000018000018000\n\t0000800000000200800000000400000401401100081000200000000000C02100000800000000000000001000000800000000\n\t00000000000000000000000000000000FF993000200180000180200000000000000000000000000000000040000000000000\n\t00000300000000000000000000000000020400000100000000200020000000000000000000000000000000FFC5BB0000009000884040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001048\n\t00000000000000000000000000000000000800000000006000000000000000000000000000FF778700000000590000000080\n\t1951801000000000000000600600600600000000000000000003400032000000000000000000000000000000000000000000\n\t4000000000000000000000000000FF8393000001901801800000809C01901002008000000000600604200600002820002008\n\t0000004800200040080000000000000000000000080800000000004000000000000000000000000000FF5D4A000000001801\n\t000000801001807800000000000004600600E0461100203000000800000051400001A000000000000000000010800000100000484040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000801CA1\n\t80181200000000000062AE2AA2AE00000000000000000034E000046000000000000000000000000000000000000000006000\n\t000000000000000000000000FF336F00000040188000000080184D8018100000000000006006006006000000000000000000\n\t03600024E000000000000000000000000000000000000000006000000000000000000000000000FFF5E60000ABAA982A8000\n\t00801815A0100000000000000062AE2AC2AE0000000000000000002040004180000000000000000000000000000000000000\n\t00006000000000000000000000000000FF3A170000000018010004008018038015540000000000006006006006000000000000c84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060000000\n\t00000000000000000000FF8DEE00002A0AB02A000601801809801C0000000000000062AE2AE2AE0000000000000000002050\n\t04308000000000000000000000000000001004000000006000000000000000000000000000FF336600040182500180040100\n\t1801C01340000000000000600600600600000000000000000000680008600000000000000000000000000000080000000000\n\t6000000000000000000000000000FF327B000154155054000001001901C010C4000000000000655655655600000000000000\n\t0000506004006000000000000000000000000000000004000000006000000000000000000000000000FF57CF0000ABC898AB00284040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000015600400\n\t6000000000000000000000000000000004000000006000000000000000000000000000FF75C5000081801801800000045901\n\t80100000000000000060062860060000000000000000000060000D6000000000000000000000000000000000000000086000\n\t000000000000000000000000FF80F1000000001900000000001B218014000000000000006006006006000000000000000000\n\t10E804126000000000000000000000000000000804000000006000000000000000000000000000FF7E2C000301A010018000\n\t01001805A019340000000000006006006006000000000000000000024000000000000000000000000000000000000000000000a84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (121041019540\n\t0000000000005505564865560000000000000000004500045460000000000000000000000000000000040000005460000000\n\t00000000000000000000FF6F7C00000180180100000400000180000000000000000000061060060000000000000000000000\n\t00006000000000000000000000000000000000000000006000000000000000000000000000FF4AE200002B88982B80000288\n\t180388180000000000002AE2AE0262AE00000000000000000020600020600000000000000000000000000000000000000022\n\tE000000000000000000000000000FFC25A00000004590000014880982984D800000000000000600600E0060000000000000000684040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000000000\n\t0000000000000000FF49A30001AB8AB92B00008A0AA0578AA00080000000002A82AE0762AE0000000000000000002A800024\n\t00000000000000000000000000000000000000002AE000000000000000000000000000FFEE7F0000800019000000A002802B\n\t800000800000000000000602E00600000000000000000008000401600000000000000000000000000000000400000000E000\n\t000000000000000000000000FF9F3600002B8AB82B0000A80AA0818AA00080000000002A82AE2062AE000000000000000000\n\t2A800028E0000000000000000000000000000000000000002AE000000000000000000000000000FF904E000054133854000000e84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000006000\n\t000000000000000000000000000000200000006000000000000000000000000000FF9F0D0000020018010000000000018000\n\t0000000000000001070078060000000000000000000000040060000000000000000000000002000000040000000060000000\n\t00000000000000000000FF306700000180180100004000010180000000000000000000062860060000000000000000010000\n\t00136000000000000000000000000000000000000000006000000000000000000000000000FFD1EF00000000188100000000\n\t0029800000800000000000080600E0060000000000000000000000040000000000000000000000000000000000040000000000184040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000180020B00\n\t0000000000100700680600000000000000000000000000010020000000000000005040000000000000010000600000040000\n\t0000000000000000FF66EA00002580080100000000000180000100000000000A000600600600000000000000000000000000\n\t0000000000000000000000000000000000000000006000000000000000000000000000FFA68C000040000801000000000001\n\t8404018000000000141406026006000000000000000000000001806000000000000000000000000000000000200000006000\n\t000000000000000000000000FF8B7F000001800001000000000001800001800000000000108602700600000000000000000000984040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200000000\n\t000000000000FF0D6C0000000018010000000000018000018000000000000006086006200000208000000080000000200000\n\t000000000000000010080080000008000000006000000000000000000000000000FFC4D90000018818010000000080018000\n\t0500000000000000060060062000000080000000000000003880400000000000000000000000000000000000000060000000\n\t00000000000000000000FF948D00000000180100000000000184000100000000000004060860060000002000000080800000\n\t00000020000000000000000000080480000008000000006000000000000000000000000000FFC16B0000000008010000000000584040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002020000000\n\t000000000000000000000000000000002AA000000000000000000000000000FF87A000008191400100000000002800004800\n\t000000000000010060000000000000000000000000000A000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF7261000001800001800000000080000004000000000000000000000000000000000000000000000000\n\t8000000000000000000000000000000000000000000000000000000000000000000000FFF646000001901801000000008001\n\t800009800000000000000700600600000000000000800000000000810020000000000000004040000000000000008000600000d84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800155000000\n\t0000001557556556000000000000000000000000446000000000000000000000000000000000000001556000000000000000\n\t000000000000FF0D3400002A8888AA8000000000808000AA80000000000002AA2AA2AA00000000000000000000000020A000\n\t0000000000000000000000000000000000002AA000000000000000000000000000FFB59400000000100000000000002A0000\n\t0000000000010010008010000000000000000000000000000880000000000000000000000000000000000000000000000000\n\t00000000000000000000FF0BF200012A8248AA80000000005680008100000000000002AA2AA2AA000000000000000000000000384040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FFC43000010000400000000000002800000200000000000008000000000000000000000000000000021400000000\n\t00000000000000000000000002000000800000000000000000000000000000FFE00600002A88882A8000000000028000A880\n\t000000000002AA2AB2AA00000000000000000000000020A0000000000000000000000000000000000000002AA00000000000\n\t0000000000000000FFA547000000041000000000000000000001000000000100100500100400000000000000000000000014\n\t0000000000000000000000000000000000000000004000000000000000000000000000FF67700000D595315580000000010100b84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (280200200200\n\t0002000002002002002000002003003002002000000000000000000000FFEA5D000000200200000000200000000000000000\n\t0000000000000000000000000000000800000002800000000000000000000000000000000002000000800000000000000000\n\t000000000000FFD6150004000002000002000000000000001000040000000000000000000800000000000801000000000000\n\t000000000000000800800400000100000000000000000000000000000000000000FFBFB20000000200800000000001000000\n\t000000000000000000801000000000000000000000000000000000000000000000000000000000000000000000000000000000784040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008188048000\n\t0020030020028020020000000010020020000030020020020000020000030020020020010020020020020020000000000000\n\t00000000FFE913000001801001801A0180180180180180180180000060060060060060460000000000064060008070060060\n\t06000006000007006006006000006006007006006000000000000000000000FF456C0086002010010010012000010A900000\n\t100000000018018000040010000000000000000000A000000180000400000400100400400400402800400400400400400000\n\t0000000000000000FFFB1900000080080080080080080080080080080080000020020020028020220000000000022020008000f84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF92AC000201800000000000001000000000000001000000000400000000000000000000000400000000000000000000\n\t0000000000800800000000800000800000000000000000000000000000FF3733000000801800001001000800801A00880800\n\t8000002002802002002002000000000802802000802802002002000002000806002202002100002002002002002000000000\n\t000000000000FFE9F70080000000010004006000014000000000000000000000000000000000000000000000000140000000\n\t000000000000000800004800000030000000800004000000000000000000000000FFC110000000800800800A00800860D50C00044040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800006000006\n\t000806806806006400006006006006006000000000000000000000FF06F3000000001D010014028018018018318018018000\n\t0060070040068028040000000000008044A28408040000060000060000060060060060020060060060060060000000000000\n\t00000000FF73DD000001881801001000800809801801801801800000602E0000060000000000000000040440000000840000\n\t06000006000006006006006000006006006006006000000000000000000000FF40E300000180000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000844040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (181180000160\n\t0640700685600020000000812E80622180080480200E00000600020E00604600630020600E04640600600000000000000000\n\t0000FF7D67000000001801201200800C01801C01801801800000600600600600600200000000000484632004000400200600\n\t0006000006006006006200006006006006006000000000000000000000FFDA6E000400081881001100811C09801845801805\n\t800020643E814046002006000000000000004100100084000006000106000806906C16106000016006006016006000000000\n\t000000000000FFD105000001801801001002A61801A01A29801801000040600600400600000200000000080400400000000400444040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF8C9800010008080100110104000190180D8018098000A2400622600E04C0044800000000CC1040040060AE80C106008106\n\t00000780E00690640401605622FC0600E000000000000000000000FF45E9000001881801401400C318018E1C008018058001\n\t2361E60B600E00600208000018000009C50081E0AE80C09600800603818610E00700610006662620E00600E0000000000000\n\t00000000FFEB0A000000001801005040C00841815840801800800000640E0820460040020000000110048040401060060040\n\t06000006040416006236006000206006006016006000000000000000000000FFD7E0000101C01801005240A01821815C118000c44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000060000\n\t07006006006224026006406006006000000000000000000000FFD86500010180090500120180184180580100180100000042\n\t4680601600400400000000000680600400008400200600000600000600600600602402600600600780600000000000000000\n\t0000FF975D00041000080340100101981B809881801801800000402600600E00400080000000000444600400000400200600\n\t0006000806006006006004006006406806006000000000000000000000FF8EC7000401A00C11001001800003C09901801801\n\t800000400600A80600500400000000180000400000600600400600000600000600600600620000600600600600600000000000244040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000680600\n\t000601818000000000018600600018E2A6006006000006000016196007106000006006006006006000000000000000000000\n\tFFB94E000000001811801800200403C21801801801800108640608480E02182200000000000C42600400680E806226000006\n\t00108702608600600420E00E007086006000000000000000000000FF51CD000001E01C11C558244140498058058018158000\n\t00680640400600240500000012000600E00C00600602600610000651001600E006106004126487A860060060000000000000\n\t00000000FFD94C000090001C81C01C00400221C058018018018001006007014006003006000000000005026004006106006000a44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF70\n\tD2000001801800C01001C0140180180000000080000060060060060070060040000000020068040070070040000000060000\n\t06000006006004804006006004000000000000000000000000FFB760000000401800845140801001C1182400000580000060\n\t0608601602604600600014000200C00400E00E00640010000600088600400600600400E10E40608400000000000000000000\n\t0000FF3FB8000401A01010811604814A15A01000000011800010600620700600620600400000001204680A0064C604604000\n\t0006308806044107006002D26206086004000000000000000000000000FFCFD20000018010018018808000419CD82180180000644040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100624000620\n\t4007006000806006006004000000000000000000000000FF417B000000401C01001400801001801000000001800000600610\n\t6006004146000000100000404006000001500028400016408006516806006006006006006006000000000000000000000000\n\tFF7EA40000018018010010008018018018000000018000006006006046004006000000000010006404000000006000000006\n\t000006004006006004006006006004000000000000000000000000FF75BB0000000018008010018000018018000000018000\n\t006006006006006006006000000002004004006006004000000006000006000006006004004006006004000000000000000000e44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (806006006006\n\t005006802000081006804000006006406000001806000006000004806000004806006004000000000000000000000000FF81\n\t0A000001C01A00001000201401001800000001800000600600600600400600200008100E00020080E80658002820000E0280\n\t0608D004006000006046006004000000000000000000000000FFFCE2000000001801201200C0040080180000000180010060\n\t0600600680400600000010000600400600E02684400080000600000600600600600680700E00600600000000000000000000\n\t0000FFECDF000001801801401001800800C0180000000500000060060060268040268000000008072000000160062040008000144040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFCD7600\n\t0200001800401800801001E01800000001800000600600780600600400600000000400000000000000000000000600080600\n\t4004006000006007806004000000000000000000000000FF1C3A000200001C00001400201001801800000004800000600610\n\t6006005106002000000800004000808020084000000006001006002004806000004006006006000000000000000000000000\n\tFF92C0000001801800401C008010018010000000018000006006006006004006000001800000006000000800044000000006\n\t00000600600500600000602E006006000000000000000000000000FF37F4000000001800001800001001201800000001800000944040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000818010011\n\t800000040080480040100000000000000000000000FF3E400000018819820010400150000710840000010000A2604680E006\n\t00E5040040000000C400C0000483900040000000060000060060061060000A6406106006000000000000000000000000FF68\n\t51000200201A92551A408A5211225810000223800020680611602E896A14824000000894A489408B0900914000000C060004\n\t4EB2E806206C30CA7107006806000000000000000000000000FF1D98000041911C0000510441114280190400000180000360\n\t0E00620642612628600000000408400040024040000000090E0000060062141260000164265362264800000000000000000000544040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08881228C00A\n\t48020000000800890880800800888C00000280001020101208220A48C08820041100480000000000000000000000FFD4D200\n\t000180085900820114101280084000012280000024120130023020024020000004132020202A24620020000010020013064A\n\t2002002000002002002022000000000000000000000000FF8CD90000018014004C0080000080404000000015800000000610\n\t00100D00840000000000081040000000006040000008480000012080008C0020200201228211200000000000000000000000\n\tFF798A00000180840001001660802400000A000000000100800040080002003038000000000002000050000004000000000000d44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFD2F2000281\n\t3002412412212150000002402002020000894800814004908AA00000000008088B4900920800809000000004000004800800\n\t004801000004004000800000000000000000000000FF751F00000100183180B8AB12B811A0B842000015800001641600E006\n\t04E21620600000022E08400042630E206000000006000006106006006000406806C06006400000000000000000000000FF7D\n\tFF000400C00880CC0800800E44C40800000520800000304330280B50312310200000100200B0010830230222000008220008\n\t8B2130129430210234030C3952080000000000000000000000FF0E000002202000001273202A24480022002002400000810800344040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (505515505508\n\t80550D50D50550550000000000000000000000FF841000040044240040044464460020000240040000000010010018010092\n\t11000000001140001001111001088000000000001800000800001001801000000801000000000000000000000000FFA95500\n\t002A00008808A0080A00AA0AA0000AA0880000A202A83202A80604080000000000202000003082003002A80002A80002A82A\n\t82A82A80022A82A82A82A82A8000000000000000000000FF36CE000200234A04A00A82800800800B0C000220800000280288\n\t2002C02802802000000D028028028029528C200000000200000280200280288000300280200200000000000000000000000000b44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0AA822000000\n\t00000006312A84002402A82002A80002A80002A92A8AA92A80022A82A92A8AA82A8000000000000000000000FF67FD000080\n\t0304004004000080002004800000D00001010000000000410808000000000408100002008080000000000000000001000001\n\t000002800000000800000000000000000000000000FF873F00002A0880AA0AA0880800AA2AA0A80AA05200012A82A82202A8\n\t2A00A00000000000002A80002002A82202A8000AA80002A82A92A82A82002A82A82A8AA82A8000000000000000000000FFE9\n\t5300025430215415214A52255415402A1542040000540D50C50D509001208000000008A0C50900C40C50C50550000550001500744040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (880000018018\n\t0190181100180180100100000180000060064060560060060060000000060060000064460060200000000000061060060060\n\t00006006106006000000000000000000000000FF16380002012252014012013152010010412002820000004800920004888A\n\t94800000000808800800820800800000000800000804804004804C03005004000005000000000000000000000000FF3D4000\n\t0000800800800842800800800812800020800000200240A0020020420020000001020022001120020CA00000000000000200\n\t2002002000002002802002000000000000000000000000FF5F050001AA0880AA0AA0880300AA2AA0800AA1080000AA82A81100f44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001000000024\n\t0040000040000000000000000000000000FFEAC7000002000021010030010001801805800000808000210A00232200200204\n\t2000040092002000002232002000080000000002106012002000102182082002000000000000000000000000FFAFBF000401\n\t4014404014074014004004004000000001000001001508001200000000000041001000000000001100001000001005001011\n\t001001001001001005000000000000000000000000FF53FA000402400C00C14C40C10C04C00C00C00000808100200B003002\n\t0534020020004001030030000020020030001010000010030030030030014430C3003043000000000000000000000000FF70000c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006046000\n\t0400001802B20100A000C00002000000000600600610648200620E086006000000000000000000000000FFF89E0000008118\n\t0102100080000B91500080000181000261040000060020060860080000000205400000D001400002000000000E1060460061\n\t00106206026006010000000000000000000000FF46890000018100000400020000B40B402000010000800000200400000000\n\t00108010000000450010410200300000000000000010200020100400000000240000010000000000000000000000FF4AE900\n\t0001800000094010010004000000000001800000000620010005400000400040002000000000000000014000000000000008008c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000105180548\n\t10C2840401840800800021800000600400600608E41600E00000010030E8000000262A4000000000000006C1608600690005\n\t6006006486000000000000000000000000FF14B700010010384102D01081003188C800800093800000600400600600604630\n\t6000000008000100028010014000000000000006126016006000306006004046000000000000000000000000FF5CD6000001\n\t801801011004800141840844800001800011602402600600600601600000000820800220040028400000000000000640600E\n\t006000006116306006000000000000000000000000FF260900000100180100101081000180100080016180006AE004004106004c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (556404556556\n\t556556000000000000000000000000FF4CA900002B8418A90A3084848889ACDA008000CB80002AE2AC2AE2AE22620E086000\n\t00021614000020E20000E0000002A80002AEA2E2462AE0802A62AE2AD426000000000000000000000000FF8118000000001A\n\t010010128A4891A0180080004180000060040060060020060060000000261400000160002A60000000000008061160060060\n\t00006006005806000000000000000000000000FF7EDA00032AB01889011250A820C780000080000180002AE2AC2AA2AE3361\n\tC60260000003200260003803865440000002A80002AE0063362AE0000162AE2AE00E000000000000000000000000FF70920000cc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (061060000000\n\t1030E4001101462A4000000000000006086006006000006006004006000000000000000000000000FFFD2E00042A0AB0894A\n\tBC29C01C05AAA80080000180002AE2AE2AA2AE2AE2AE2260000003204270062002060040000002A8000AAE0062AE2AF0062A\n\tE2AE2AEAAE000000000000000000000000FFB327000201C15205201A00B05201800000800001800000600600600600200645\n\t6000000046210900046028006000000000001006106006006800006006004096000000000000000000000000FF0D42000154\n\t555535155920809041B5480000011580005565565565565525565560000004160084045464D0016000000550001556C46556002c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (041801801000\n\t050001911802800001800000600611600600200600600000002600600400E02600E000000000000006006006006004006006\n\t414006000000000000000000000000FFE3100000018058458450430028018230A88000018000006016026006006006006000\n\t0000860AE000006096106000000000000006006006006000006006144006000000000000000000000000FF345F0000000018\n\t03C01001040C43801A00800093800000600600600600600601600000010600680404600E016000000000000006C2E006006A\n\t04006006004006000000000000000000000000FF3228000301A01241001B05A938898008008000218000006006006006006000ac4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (042AE2AE2AE2\n\tAE006000000000000000000000FF658600005413195195415592015590A93000155580005575444425565565505560000005\n\t064120044044064A6000000006000554556556556004556556516556006000000000000000000000FF03A700000100180080\n\t0011804001004954001001800000600605000641400000200000001600600000601600600000000600000400600600600000\n\t6006006006006000000000000000000000FFCB6400002B88D88D8890880840AB8418018000AB80002AE2A63022AE2AA2AE2A\n\tE00000020E3060002A62462260000000000002AE2AE2AE2AE0002AE2AE0042AE000000000000000000000000FFEF18000100006c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000081610\n\t2004044010006000000006001005006006806004007007006006806000000000000000000000FF4E5600012B0AB0AB8AA081\n\t8890AB0C0000001CAB80002AF2AE4002AE2422AE2AE0000002663580042002002AE0000000060002AC2AE2AE2AE0042AE2AE\n\t2AE2AE006000000000000000000000FFC8F4000080001801800001808001800804001001800000600C00E006006002006000\n\t0000360220060AC08E00E000000006000004006006006006006006046006006000000000000000000000FF8CB100002B0AB8\n\tAB8AA0A38A88AB0888000010AB80002AE2AE0862AE0842AA2AE0000002862060042AE3262AE0000000060002AC2AE2AE2AE000ec4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01800000A202\n\t05A01000201C0180004068A61850C64040040060100810022064000060060088000609060011FD0068074060008070470170\n\t07006000000000000000000000FFC7CF00000540104180000104880100000000140180000061450029161030020060000800\n\t01002004004006000800001006000006086026006004007007006806006000000000000000000000FF8E3F00000100100180\n\t002B242A0121004400180180000068060200061400020020000001020460001160C600000000080600000600680600600100\n\t6006006006006000000000000000000000FFF3EB000081001001800001801001044088201201800000600430A00600A00400001c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (606601600600\n\t6000000000000000000000FFCDFC000001411801908880800005841020001201808000600401700601400000620000010600\n\t202800C00028E08000100600081600600600600810700E406026106000000000000000000000FF9C6302004100184180A800\n\t8108010410000010018001406007006006085044006000000006800000000000006000000006008004006007406000006006\n\t806006006000000000000000000000FFB4470400410018018140448000018210000018418001007804001006004020002000\n\t000000202000004007808000000006011006006007006000006006006006006000000000000000000000FF675A0000030018009c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020100002010\n\t00440002000000000600001600600600600000600E206026006000000000000000000000FFBF920000010018018010018018\n\t15005800001E0180000060041440062A42060A64000000021001401500001000000200060000060860264860200260460060\n\t06006000000000000000000000FF961A000001011801911901801009851808001801800028E8040A00060062040860000000\n\t00002080024198430100000006000006006026286030106006006006106000000000000000000000FF06B800000100180180\n\t184580100580B80000184180000060060040566A600602603002000208040008020000000002010600000418604600600002005c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (50828809008E\n\t80001F48AA80002AA0120022AA0024232AA0000006526221002423922020000002AA0007022AE2AA2AA1002AA2AA2AA2AE2A\n\tA000000000000000000000FF390100000100000100C030049102004000002201800000004628000011001000600000003000\n\t4002084008148000000000000090000000000002000000000000000000000000000000000000FFCDB1000001824000020000\n\t0020500000000100000000001A88050000240500000000000080090080048040000000000000000020000000000100000000\n\t000000000000000000000000000000FFAC62000001001801801001801001001828001201810031700401000601400100204000dc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (005004004000\n\t000000000000000000FFA54A0000D5955C01951153D41955955000155D55800155655600E5564CE11648E000000446124201\n\t016516526000001556000D56557557556400557D56557D57556000000000000000000000FFB8C00000AA8888AA8A88809228\n\t2C8888000008AA80002AA8820022AA2AA08A2AA00000008208200050A22222A0000002AA00004AAAB2AA2AA0002AA2AA2AA2\n\tAA2AA000000000000000000000FF7AF30000000000AC00200000A20000100000020000010000000810010012208200000000\n\t90200000520020008000000000000000000001000000800000000000000000000000000000000000FFC66C0000AA8890AA88003c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200900008480\n\tD0100000000800000000801000000400000800001001000000000000000000000000FFFDB300000000000000404002400000\n\t2000000000000080000022000000820040000000000900020008000000800000000000000000000080000080000000000000\n\t0000000000000000000000FFAD4080002A8AA8028888888888AA8A88000AA8AA80002ABAAA4C3AAA22200300200000028323\n\t20002022022220000002AA0002AB2AA2AA2AA0012AA2ABAAA2AA2AA000000000000000000000FF2B29000000023000001054\n\t0102000050000004000001004C4035100500084080000000000004C00000000008000000000400100080480500400100500400bc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800800800C00\n\t8008008000003402022002002002002000002002802000002902002002022002002802002002002000102002002002002000\n\t000000000000000000FFDA2D0000000006000000000000000002000000000000000800800000000000000000000000800002\n\t000800000000000000000800000000000002000800000000000000000000000000000000FFD2220100001000000000004000\n\t0020000400400000000100000000000100000000000100000000504000004400400404000010010000400000500008000000\n\t00040000000000000000000000FF1F8E00010000054802000220000000000000020000000000000100000800B09300000000007c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFA785010000000800A00E18A0080281080480480080000120020620020120020020006328626020004020\n\t020020020030022FA00200A243002000002002042002042000000000000000000000FFA942000040001A01A01801801801A0\n\t1A01801801800000640604600600600600600000600680600180690680680604600600400600600600600010600400600600\n\t6000000000000000000000FF4833000000001000000000200001408000000000000000000480180400000000000000080000\n\t0000800000004004004005804000004000004000004004020004004000000000000000000000FFD767000020000800A00A0000fc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF1B24000000000001000001200000000000\n\t0010010000005000004000004000000000000004800800001001001000001000000000000001000800001000004000000000\n\t000000000000000000FFEB8A000000001000800A00800800C00C008008008000002002002002002002002000002002002028\n\t80200222202202220208280280A002002028002002002002002000000000000000000000FF3F7C0000001004004000000000\n\t050000000000000000000800000000000000000000040000000802000000000000000000200000000400004802000800000000024040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01A05A018012\n\t01800000600600600680680400400000680410000080080001E0060060060020A288680E0062008060020060060060000000\n\t00000000000000FF05E8000100001800001C40840009809801811001800000700E9060060064560040008000010440800C40\n\t5000600602600600288A106016006208006022006806006000000000000000000000FF370200000000180002180180200180\n\t1001821001800002E00600408604600000000000600400000000C00010600600640600202600600600610020600204600620\n\t6000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000824040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000000000\n\t0000000000FF4A71004000041800243015841C01941145802000800008080E00E006006004006000808806D0402011690100\n\t600680604714002400600602600900E042A27006006000000000000000000000FF6574000000105800001021821811E15801\n\t85000000000000161040060062440020000060040C010114680808600604640600200F006002006011007022047006006000\n\t000000000000000000FFF60C0000803119B4401A49819801815811801241800002E10600608613600E104000140000004000\n\t048420016007046006010000116014006080207113114006306000000000000000000000FFBC96000000505940021811A13800424040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008006106006\n\t006006803006007204006000806000004806006000000000000000000000FF7A9C0000004010002010158008018818038048\n\t03800040080E004006020006002000006014896004810006086806006A06003C0E0068868060040069400060461260000000\n\t00000000000000FF0D70018000001800400041841181C05811181043808020006601600602600400400015620900E200844D\n\t0708718E00F25E60438C1070B5186800187002004026026000000000000000000000FFB62000200055191402440181100182\n\t994100100180801000860040061160059000000064042064400840020160160560060B60260160400470080160125540060000c24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1C0180280180\n\t0000001600D20608082600200100682509640420280631720600600600510408630100600400702400400710600000000000\n\t0000000000FFC98D000100001600001001801841E01A01801801800020000680680600004600400080010680400440281004\n\tE006087806000884006084026044006826004006806000000000000000000000FFBABC000000029000001221880901801001\n\t80584180002000062164060102040860010070C500040400A004406406006006000004106006006024006007806006106000\n\t000000000000000000FF29E0000000051000081241D09A01801C01800801800000081740400710140610000000600009600000224040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF687C0000001818018A100320180190D001801820800000021600500600080400000000680604E200866006006006\n\t00610610500440608400E00000E006004006006000000000000000000000FF451D000000021801801001003B418A38018018\n\t48800000000600400601080480208000E0240260040060162C72A61060060040042A600504600408608400408E0060000000\n\t00000000000000FF41130000040038528094312018918018018048050000000016804087800007A13800006006006024A120\n\tC784600611610E554554016000446005A46007005806006000000000000000000000FFC37D0000800018009010010118018000a24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060060060\n\t06006004006006006004006004006002006000000000000000000000FF952400000000000000080100180000180080180180\n\t0000000600600600080600600080000600000400600600600600680700600600600600600400680400600200600000000000\n\t0000000000FF60E8000000002854130053805B01829800001801800000080600600600000480408000480680C0064140060C\n\t6486016006056D040060860560060C6004806112006000000000000000000000FF962D000004040800600001801810001E00\n\t00582D8000000C0600510600000041400000C0420044200060C640602608680EA0605614E00640600040E90400600200600000624040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001A03000000\n\t0286024006000026806200000000064804000802006007006006086810006006806004006022006002806000000000000000\n\t000000FF4D54000000001201811C01C01801001900801844804000150604600600001000450008600200604C804535100116\n\t00604E006143016806006005006804006006006000000000000000000004FF7FDA0000000010018018018018010018008018\n\t0080000000060042860000420060100004820040040060044002060061060860024060060060040060240060020060000000\n\t00000000000000FFE1800000000000000000010018018018008018018000000006006006000006006000004006000004004000e24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF9615000000200001400001A01800C0180180180180000000060040060070041040204400041000008841320460068060\n\t06146516046806006000007802006003006000000000000000000000FFB79800000000000100081180180080180180180180\n\t000110060040860160000040084842848000280002AA20608E00702E1465B720E01600600000600000600200600000000000\n\t0000000000FF3A26000000400801E00281801801401800001A018000000006046006000026506040046000106804504B5284\n\t6026107006006800026006806004886002006206806000000000000000000000FFFF0C000000000801801819801800001A8000124040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020612600600\n\tEC4A30E0060060220262420A6346236000000000000000000000FF7BCF000000401001001801801801801801001801800000\n\t0806004006006002006000000004004000000000000006007806806002006006006000006000006002006000000000000000\n\t000000FF659B000000001001410889801800C01801001841804000900600640600E834004100003006002000004A04100426\n\t00610680601200600E006000007002806206006000000000000000000000FFD1A1000000401001000C01C018000018010018\n\t018000000006046006006001C04000003006802000407004000006106006007002006006006000086001006006806000000000924040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100000100000\n\t2A0010020000000000008C00000010000100000888880881000028111A00000001410108A800000000000000000000000000\n\t00FFE5ED100000010001120811901820081955881800000000040640488600600072000000214C2460000040500002260060\n\t0600E042006006006000A462E2106024046000000000000000000000FF25690000004084A9201A01891AA0341885A91AA080\n\t00C010C6C4409684692A82600090229530C8309008008880AE00608EC468828264B723680030689240E81710600000000000\n\t0000000000FF5CE7000000003405054AA1A41805C15C4100180180000280060842460062014040002100440460022143204000524040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tA9870000002432A024420022008224A2203002C00000818820841208900A00810000A00A10D80808B00A00400500010C40B0\n\t0810080C094388200A0800808500708000000000000000000000FFC1BD000000100901C19000A01900800C0101C824800006\n\t204200300200251A00200110208002A00245A4221C280282301240268280205220600200201282205A082000000000000000\n\t000000FFDE1704000000800800000409C20000008004180180006060801140204060E0000000480020010020084081219040\n\t840008020000A281A0000001000400441281020000000000000000000000FF65E90000000000160021E0200050124202000000d24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002802C0B08A\n\t802C02002800802C0AC12802802000000000000000000000FF76060000002432012452002110003082032042820000801004\n\t8200048108C880000080CC34804902848800800004005004904C248048140049020049248C40008040000000000000000000\n\t00FFF9F60400000B108B0951038818A190188B15580180000460264868064060D649600000402E04C00202E0360060260060\n\t0610644C1060AE0060028364CC286946126000000000000000000000FF860F100000400C00820C50812E10C42820C00C4C80\n\t0128B20303200B083403002000503483503009303283332A8282A23240300200A203A0B00020300202320B4020000000000000324040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00C40D508315\n\t50D40900A10000840CB0C00900D50C20550551551550B00C40D50A90550900D50C40908D50D50000000000000000000000FF\n\tAD5D00080040040844054A420000000000400400000100100100080100108044800000114110900100150100100080000100\n\t1501001010801001000101000001000000000000000000000000FFAF4300080028808A0880880A20AA0000A00A8008000022\n\t82A80802A82A00002200000800002A0000200200AA82A82A82A80300002A80A02A80002A80000402A82A8000000000000000\n\t000000FFC147000000000C40C00A44A00A00A42A10A00A208000903002C12002802A0289200124290280A8008828AA00280200b24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF48F8\n\t0000000AA0800800000282AA4AA8AA0D00C000003382A82A82A82B00102A00001800000200002000002A82A8AA8AA8208000\n\tAA8221AA86002A82102A92A82A8000000000000000000000FF735A0008000000020000000240004000080020300000088000\n\t4800000082280A00005080000A80000001110010000000000200880000410000000000884000000000000000000000000000\n\t00FF4DDF0000000AA0A20920001122AA0AA2AA08208A00002202A82A92A82A02401000004282084402003300282A82A92A8A\n\tA82B00302A84C02A80002A92202A82A82A8000000000000000000000FFEEB40000003543503543523103541343223503040000724040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (031530030030\n\t03002801003143413043002000000000000000000000FFA230000000001821003005801801801003801901800001620E0860\n\t5620601600620004401600600200E20600600604600620610609602600620254600C086006006000000000000000000000FF\n\t114D0000002012052032522020002002002222120000800804800004810910010000015430810A0088081080480400400482\n\t0844000888004800800044800001000000000000000000000000FF0367000000000848830880880800801800808820800010\n\t200200280200244200200024210230200005234200200200200210251200200200200000291200280200200000000000000000f24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (630830404020\n\t6210000400440000000008008240220000020000008100080040000400480110080040000000000000000000000000FFD9C6\n\t000000041844000800800800C060028008048000042112002002002002002080002102102000002402012002012002282000\n\t01A102006000022462002002002000000000000000000000FF319F4008004004214010004004000004000000000000001100\n\t0010080000200000010010090000100000014410010090010210010010010000010016012090010000000000000000000000\n\t00FF97F2400000400C00C00800C00C00804C0080080080000030024030020024220020814030030028000020430030030130000a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFA5710008\n\t800018008008418090009E580180100980404862260C401E00E0002045A800C00C1044406100380862461860260066600060\n\t0018E418046082224016382000000000000000000000FFD0E600008004184480000180001401180180102182000463160040\n\t0600600000C00000600000D10800002001620600602600600202E002007040406002406006006000000000000000000000FF\n\tDB3300080000000002004000002A01009000004004404080000400000400000104000000000304D001008040004040000020\n\t00002C0028000420220000088210000200000000000000000000FFB05F000000000000003005000000000000001901800001008a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C5162AE2AEAA\n\tE0002AE1922AC0042AC000000000000000000000FFEC48000000001840AC0011801A41801854800121800000400641400600\n\t60460860000060C4402800444036086006006006004206002006006800002402004086006000000000000000000000FFA2C7\n\t0000000358048088438010958CD80180100B800000200614400601640E44E00034C0140B600009010000E006006006004128\n\t00400200600000404A00642C000000000000000000000000FFE2FA00000000180082000181102140190980100B800008E046\n\t08400603600640602800E08804600000028050600620E0062040003060AA01600000632214E2064024000000000000000000004a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (552556540436\n\t4C600000A4225142045424B0446556556556556506556550D56204556488556106556000000000000000000000FF56D60000\n\t004A98888C088B8AB8AB903C908AB09380002A82AE42C2AE2A61342140002142A60AE0002B220828E2AE2AE2AE2AC0062AC2\n\tAEAAE0002AC0222AE28C2AC000000000000000000000FFB3A8000000603800820001801809081C0080102180000000060040\n\t0600E08400C0004C608A02600201200008E00600600600402600000600600200002200622E006000000000000000000000FF\n\tD03F200000081A888068810AB801851A848AA04180002AC2AE0042AE2B64821060000442040020000042062262AE2AE2AE2A00ca4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D45100000000\n\t1A21902801A01931235A00001821800000000600600600010621600004008410000444403600600600600600611400400680\n\t6004004106006004004000000000000000000000FFE35000000028388D8000AB8AB8010018A88AB88180002AC2AE2AE2AE2A\n\t00260860000000042010040042062062AE2AE2AE2AE2142AE2AE2AF0042AE2262AE02C2AC000000000000000000004FFD7CD\n\t000800003C42410841C01C0140184080080180000000061060060000060260000820164048000020C0046006006006006044\n\t004000006800004400006046006000000000000000000000FF6BB3400000151D50514155955CA50359549549158000554556002a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1040162AE000\n\t004046006404184000000000000000000000FFF2A4000000001849050895843841001843803801800008000600600600002E\n\t02600005400608000404600E00600600600609601640450600600440440C2D6314404000000000000000000000FF2BC60000\n\t000018058848418018938B5891800801800000000601600601010608E00030404602A1041060C60060060060060065241300\n\t320061040A8126006024034000000000000000000000FF6348000000031804A50001801A0590180580080B80000000060060\n\t0601041604600029443604AC040961060AE006006006006044000002006C0400000C006284004000000000000000000004FF00aa4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AE2A01262A80\n\t0022009020620434628A2AE2AE2AE2AE2AE22602E28C2AE0042862AC2AC2AE286000000000000000000000FF6EC500000015\n\t51119038B59159058CB951B51D5580014C05565565575425325100004104444060044CE54855655655655640E4A444624455\n\t608400600E054156406000000000000000000000FF5030800000001003801001801803815801801801800000000610600600\n\t0012000000110444056000016022006006006006006006206004006000016006004006056000000000000000000000FFC7F3\n\t0000000AB8840000018898010018018A98AB80002282AE2A62AE2A020624600010428E20000020E2062AE2AE2AE2AE226006006a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001041\n\t800A00840A49801801C11C018001080005406006002052000000000000096004008026002002806806002106096104806204\n\t50E044005006006000000000000000000004FFBF750000000AB0408AA8AB91588390188D8E1AAB80001182AC0162AF2B0482\n\t2A80002202203060042802022A82AA2AE2AE2AA33E3062442AE4040462042AC2AE026000000000000000000000FF0D460008\n\t00001021850801841849801805A03801800000800600600600A0060000000200900D608400600000600600600614601400E1\n\t040060044B6304504006036000000000000000000004FF95350000000AB0898AA8AB8218A98218A988B8AB8000A202AE226200ea4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (070160400860\n\t06006006006000000000000000000000FFDC28800900101C00801C41801581801801C01C0180010088008070072040020002\n\t08018A4460000010E003017004907006046403506004846021006007405007006000000000000000000000FFD16200000000\n\t1221800810C00801821801C01C01800100121502680780200C00000000000200000500608810601500608750202080F08600\n\t6005806007806017806000000000000000000000FF25AE00080000110D80080188B80193584580580180002410040B600601\n\t220600000010890A02020002611300700400600600200002603600600002609400600630E000000000000000000000FF5696001a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (401600008048\n\t000002000010000211829000E0060062C2006100256200004002484006026000000000000000000000FFE982800000101800\n\t805881801881833909D05D01800100081100E00600600628042820000600600008840604200A10600601001242700E886111\n\t0460048160A7106200000040000000000000FF94DE8000800018A0821831A018018318018018018000000210026006804006\n\t00000000002400600100008A0008029060872A040248E00400600010600400400E006000000000000000000000FF57F78000\n\t00001900841801801001811801801801800001010000780640600200020840020600000000E0060070040078060060038060009a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018008018\n\t00000003841801D05A09800100400702600688600600028020000E00800009022E04200010600601210A02600E0860800460\n\t02116096006200000020000000000000FFE311000008001800815800000021891951811D0582804840060860070240065100\n\t001000841202A8040002000290006006080202506002426410014120406006046040000000000000000000FF81A200000010\n\t1800801901801933885801801C09828029407609600702600600805000008A0882A80201AE01200001600608600208600202\n\t600000C0A220604E106020000000000000000000FFE0E2000008101800809801801809801821A09803800100C10602600608005a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (440000008000\n\t0000000000000000000000000000FF88B10000000A90AB9008808888AB9000AAAAA8AA80012AA2322AA2AA00244200000000\n\t004220210020200A10A3022AA2AA1020122AA1022AA1000221885022AA2AA000000000000000000000FF88FD000000004001\n\t050008000000000000001C01800000600000600148E4C80000000000000B01000082245401080000000400A00004D0000100\n\t000000420000000000000000000000000000FFA25A8000000000000840440220001340004000000001000108800000040000\n\t0000000003480000000A0080000020000000490210000000000000308420088000000000000000000000000000FFA9B4000000da4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000094\n\t0200000105510010010050042300A4004041004000008004020004004000000000000000000000FF012B9100001559151518\n\t43845D558CB555D55D558001556D4E557557D465060000000004044160004172AE456D5655655650640D5561265560005564\n\t56557557556000000000000000000000FF97010000000A80AA850CA08D48AA8208AA8AA8AA80002AA2222AA2AA20200A0000\n\t0000020230A0002C20024322322AB2AA0022022AA40A2AA0002C225200A2AA2AA000000000000000000000FFC02E00000020\n\t002020409011000000000140040000010000008008000080100000000001280C04000800008800008000000300C000020900003a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (050802412002\n\t24000B4400400400000109010080100001008800000000002803000014008012804800080000000100034000000000000800\n\t0800000000000000000000000000FFFAE0110000000042008004100000000000000000000000000000000080000000000000\n\t0000100000011220000101000000110010000008000000000100000000800000000000000000000000FF5A9D8000000AAC00\n\t8808088088AA8018AA8AA8AA800022222B2AA2AA2A226200000000028220220024200A2022032AB2AA2222A22AA003AAA200\n\t2AA2222AA2AA2AA000000000000000000000FF54E580080020500140420A00000101400140040000010010808010050B010000ba4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (104805800004\n\t004004000000000000000000FF89D9004000400800800800A04C00802A008028008000002002002002002042002028002102\n\t80200010280240200300208200A002102002002000802002002002002002000000000000000000FF94D60000000002000000\n\t0020000000020020000000008000000018000000000000000000000000000008000000000000000000000000002000008000\n\t08000800000000000000000000000000FFAE6501000040020000810000400000000820000400008000000100000000000000\n\t00100110000000400000040000440040000890000000000001080000050800000000000000000000000000FF3E1400000000007a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000002\n\t30000040000000000800000000000000000000000000000800000000800000000000000000FFFE04010000000C0680690080\n\t0800C00C06860A04800006200201208200300240200010311300202041A02204308208200200391200300300200000300205\n\t2003002002000000000000000000FFAA32004000001001809801805E01805809205801800000600600600600604600605000\n\t4105006000106806C0600700600701600690600640600000700C006006006006000000000000000000FFF246000000401001\n\t000600000000000001000200000000000000000400180020000180400400020800000180000400590480418400000580000000fa4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF00080000004004000000000002002000002000010000004000004000004800000000000800\n\t804000000000800000000800000800001000000000800000001001000000800000000000000000FFF25F0000000000018008\n\t0080080080080180080080008020028020820020020020000020020020000028020028822A20220020008020028020000008\n\t02002002002002000000000000000000FFA11C0000000010000000000040000004000000000000800000800000000000000000064040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20844DA68F60\n\t06000000000000000000FF3ECC000000201A01829800D00011805818881801800080623E00204E4160060040010480060260\n\t00800002880006886006E0622C10E00E31600004000280D047146006000000000000000000FFE4CF000000001811801A0580\n\t0103941920C838058000016826016016804C5680400009304454451000280004010600608608694CA1600F00620000090204\n\tE006006006000000000000000000FF1C1B00000000180182D900000001000005811801800000220000600600400400C00800\n\t2016006040100000080006106006006206006006406000102022006106006006000000000000000000FF409B00000000000000864040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004600602000\n\t608282600701642600710600600720700040600204408602E006000000000000000000FFEC13000002420E03A0DA81801001\n\tC10801800001820040280204200600680680600880B100004021C03124080006006006106A0200600640E0000060C0001017\n\t007006000000000000000000FF220F000000000801801885A01315803844A00005800101600601200620E22E00600000300A\n\t286008080004800086006086106087C06006086201907082020006006006000000000000000000FF19B1000010215819D438\n\t01AD04058A10C1A0B901800001604600202600600604C0080A00340442A010200282004680614681610018700694E001420000464040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00009C151218\n\t05801800000001600602000F144004006080020806004000087048006006006106086484005816004000804022006846C068\n\t06000000000000000000FFB01C000002005003813800801801803A00801800000040600602200600600600E0018060060402\n\t04246000006006007807907406004806004004036C2A006006106006000000000000000000FF0D04000010410801841907DD\n\t1585B93D81800019800001601E00200600400600E01018413400438092684212604680E31E01606310606695698002EB0800\n\t4416686006000000000000000000FFBC2D000000040811900801001001001820A0010184000060460020060040040260000100c64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (680600600600\n\t0000000000000000FFFB87000000001009C55801801009841802805800000001700604040E8AE00600400000510010600410\n\t601680648608E026006010504207004025005055002446286006000000000000000004FFC928000000000001A01803E01C01\n\tA018018098000000906806000286006406026000200085084000002004200086116426006020A86006006024824804A06806\n\t006006000000000000000000FFAECD00840826000184101980D80189EA0080D84000008020021800860162061A6080826015\n\t01800440062500040680628608629080750E71E414104015006406106006000000000000000004FFAC89008008005209815800264040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000008060C6\n\t20608628610648E446104086106C20046016406806006000000000000000000000FFE26F00010011F4018068050014010008\n\t40B61A00000000200200000600400400400100548008C1000160A680608600600620610208600608600001F00C00602601E0\n\t06000000000000000000FF2D89008008605001A0880F807005A09C2100184000009868060808070060260840014852180000\n\t8640E0064260070060260060E2004106104416146004402006026006000000000000000000FFC13900008414164980180180\n\t94C1A01811A81A40000004600600040610600600400000000100400000601641620648610609620000610F0064240440042000a64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180180000\n\t1800000000400600000600600400000000000600400400600400600600600600400400400400200400400400600600600000\n\t0000000000000004FF73E7000001800401200001801801A01801801800000100400600000600400400000100000680400280\n\t6004004006006006006006004006006806007006006806006000000000000000000000FF434B008008400841808801811B01\n\t801801001840000008400600040600600400000000000E088004006016836406006026004004004814002004004004806026\n\t046000000000000000000000FFDB96000404040811801809805841811810801800000004500610100610404408000010110600664040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000000000\n\t000000000000FF215E000001018801007801841801801801A01A84002000600600000680400E220020060000000000802004\n\t02600E00E006804004804814000000100030006002006000000000000000000000FF8DB8000001400C11C00001A018018018\n\t0000190000400068060004465061244400401014065003244848829461060070560061060060068044048170468070000060\n\t00000000000000000004FFD99C000001000801801901801801801801801800000000600600000600600E0000000001060020\n\t0800600200604E10E506206006004026004004006006006000006000000000000000000000FFC8740000018000010000018000e64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000464020040\n\t06006006007006002006004000002002007006006200000000000000000000FF8858000001000800A00801C0580180060000\n\t18018000006806003006004006420000028400006020C12806156406006017206106541C0680601000300200600600600000\n\t0000000000000000FFE06D000001401800801801901C01800001D4180580000060060020072040260000000000802862A82C\n\t20870840860072BE0061C7D00026006201802002006006006400000000000000000000FFD4BA000001000A01003801803C01\n\t801C0200B800000000600600000E006004450000050C00000044412404156406006006C0400402620400001400080000680200164040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (881A00001C01\n\t800000400600288600E086000000000000006000020048246326006106ACA00E00222204400031288344E8CA14E000000000\n\t000000000000FFE96A000001600001201801801801A018018018018000004006002007806006000000000800806002002000\n\t804006006006003006000003804002002002006000006000000000000000000000FFDA87000001000011402101CC18018000\n\t020AB80780000060060024461041040000001004060060000040028060461060064060270028160040009120120060060060\n\t00000000000000000000FF9C9F600001000401000001801801A00001801801800180600600200E004004008000000806806000964040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF55B70000105A40100C00020800000102A400004200000004504210A00800000000000B04000002000A00802888\n\t90818000080210000148020000108100010009800000000000000000000000FF42ED000001000801009A0991981188180090\n\t1081800002412600280E00400400000000028002200000000001600620600640204640600210400004244234600602600000\n\t0000000000000000FFCF6A000401200B01201929A89B05A49949281A85800084544692A036CA4A46000000548A908B2A00B0\n\t2D00916016316A0E802C06A46912A04A40842A42886C06206400000000000000000000FF181A0000011442418B3805C2183100564040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (340330380280\n\tA803C8309300385330300140308231312A10A000000000000000000000FFB6D5000040013280203261200220304449280200\n\t0000D40800880800D10860C00000808800C08800A00C00D00009081080008C08A00290810820E008108007810D9200000000\n\t000000000000FF87EC000101840120C20C00800808848D10800800800000220201200200A00200000020004A0D200000220A\n\t022203003002302002162022400100022022822012002000000000000000000000FFB26F0000004000001010800201820200\n\t01005101800000000000E000220280000000400000000010440020001020400318870100001000240200080280488864700000d64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (40A00A008000\n\t802C028820028220020100004414C2A02A00A82802932802002802802802C228028129008020428028028020000000000000\n\t00000000FF8CAD0000012014002012092002422000152002040000800914C30004C088888000010910089008008088B08000\n\t04004004001048810000C04801154D0C94C800004800000000000000000000FF14380000A90238818C102189188994384D00\n\t390180001060C600680610600600000021040600E00840600601601640608E02E42634610602E10012442C046406A4600000\n\t0000000000000000FF58C4000400888C10800800C00C00C08B00D00C20800122320B4120032130424000000010232230010400364040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF7B7B0002003523542145503302C43002C43303520000D50CA0C48D50800230450000310A09008880910C40D08D5155\n\t1550D508B0A00550C30900800900CB0D50D50550000000000000000000FF7DBA000800410400440004420400000442440404\n\t00010290010210000000000000010A1000011003001121120001800000001481001001001003101109440001000000000000\n\t000000000000FF3BC60008000AA0AA0402020A80000640000AA0A800002A8030000AA81802203A0000000000028080020210\n\t2402A82A82A82A82800802A80A00002408002002A82A82A8000000000000000000FF4CEA000200C00A00AB4940C04D08B14D00b64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A2002002002\n\t8022C200200200240010210200A002002000000000000000000000FF2EB60000000800AA0000F00888AA8101000A80A80000\n\t0000402102A92A9AA82A8000000210528400200200201AA82A92A82A80102A82A82A8000230208110AA82A82A80000000000\n\t00000000FFC53E00080000000008000200200800800800200000000000000800002300800000000401402C02002400800000\n\t000000000002000A9000100000308248000000000000000000000000000000FF798A0000000A20AA09210008A0AA4C400808\n\tA0A800003002902802A82A82A82A80002102C10400803302082082A82A82A92A80202A82A82A8200220240000AA82A82A80000764040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080080000030\n\t0200300300300000002120905301308200210200300350311321300310300310311310300344300300300000000000000000\n\t0000FF32B5020151801001809805805001001803801801800000E00600E20605600000800000010400600040644608620601\n\t602608600E206226206000404226006286006000000000000000000000FF4FDF000001215200324009444400080241200204\n\t0000850A208A00048000000000014008CC904A0294080081000100480400080880480480480280C844D20000800000000000\n\t000000000000FFFC03000000840800810804801801A4C892804800800048211200A8020020000000000B000220210001213200f64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFFF220000A8001001000000002080004004000001800000C000006210004000000000000080010000204204080404088140\n\t080208400000500010200220440080000000000000000000000000FF344F0200000038A0808803C004001048058009008000\n\t00200200A10222200000822020000204000000252200200200224A6020020005404000800824000020120820000400000000\n\t00000000FF298D400C0141C54040640008000040040000000000006010000010114090000004010090290010800000800010\n\t01201401009401081221001001001001001201101000000000000000000000FF9075400400C00C00C00C00880900C04C0080000e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020060062001\n\t0642402420020008220024200E006000020000000000000000FFA68A00088100102104082194D80182982181B92191000860\n\t0622600601E00004808002008265E00000040622400611604600269001451C16010000A08800008600600000000000000000\n\t0000FF9FD700008100182100180180981589012180380B802008400400E10600400008800002010208600802410022400200\n\t600600000200400600800800A0AA102106086100000000000000000000FF7E0A00080000000C022000142094000090000014\n\t11404101500100000002001400000000001004104500100100800900000000102280001103100800402A0000100080000000008e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80002262AA2A\n\t02AE40C0100000000002620000002262040062AE2AE2AE0300004141E62040004224062AC0042AE000000000000000000000\n\tFF9CEC2000310400110B420184180580194580000180000060020000062264C000000000008A020B00084004036002006006\n\t41040020C0060D4800002106004516006000000000000000000000FF5BDB00000101500500080180B8A18038119038058000\n\t11600601000608600800000000000048A0000100B63040060060060820D612020C0001005124300020440060000000000000\n\t00000000FFA552000001001815004841C01C81843813801841800020E0AE42000600640000008000000000220020C0100141004e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF2F\n\t65200113295903014155905905915AC395595200005545545505565545500000000005264860044045105505525565565565\n\t5240C45600400440048E5524B6554000000000000000000000FF5A3E0000D12A380300B4AB821915A8DA219100A980002A62\n\tAA2A02AE0D63200000000002842884804C03042902A82AE2AE2860B60824062A608008E08E2AE00C2AE00000000000000000\n\t0000FFB830000041220031280401831829821809800001800000400000000600600000000000001004028012C00400000200\n\t600600600608208634E20004E026006006006000000000000000000000FFBFD40002830818A11000AB8818498E921186C0A900ce4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600610600609\n\t2014026806004014002024004000000000000000000004FFF1360002210310030B4001A01801A01B45801800000000600600\n\t000600600000000000010010E20000602600600600600601600202010428C200112104006114006000000000000000000000\n\tFF62F4000483201A814400AB8098098A90018AB8A800002AE2AE2A82AE2AC2A800000000022623700422C2462AE2AA2AE2AE\n\t2262AA2442240050043222242AE2042AE000000000000000000004FF4FF6000A050112D1820001C8BA018019058018040000\n\t00C00401000600600000000000000802680001004804000000600604640202001400C8000200440025460040000000000000002e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00440C2002AE\n\t2040000000000000042060001061142224002AE2AE006416202096206000186106006004016000000000000000000000FFA7\n\t7C000005840041052801803803809801803802000000412404800604600000000000044C08E00434C0A40122820060064160\n\t5613200602E00400C0860C6204404000000000000000000000FF5A120000418818810010018298C984580182180000004CE4\n\t0608000608C0000000000001000400020064140820280060060A648600245410600022624C2120AC13600000000000000000\n\t0000FF97BE000011903829001201943CC5805811801804000000600600000600600000000000000C0009061041140020020000ae4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0004FF229100\n\t00AA0458AB88B8AA01190182B8AB8A98A880002AE3262202AE2AE0060000000004442A000002600622602E2AE2AE2262C600\n\t42AE2A40042A22A628E2A82AA000000000000000000000FF0B300001540810A39019540018018C1955953D5000002C608CCC\n\t05561560060000000000044160040440205360565565565160265244A6434004402044016112142000000000000000000000\n\tFFC710800000101801841800003823901801801802800000600010000600600600000000001400E0020860CE016406006006\n\t08600604C006004002012006006002002000000000000000000000FFC9E800008980B81B0848AB8858458810AB8898AC0000006e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006084214806\n\t1100001461000A6004002000000000000000000000FFB679000000041C0002D800003803849800805C028000006102848006\n\t8060060000000040048C600434C0A40552860060060A600404600600200401200E016801007000000000000000000004FFD2\n\tCA0000AA09B0AA0018AA1C18118018AA88DAA800002AE23E2102AE2AE00600000000418C2060004164043841062AE2AE21E2\n\t3C5842AE2300042022362462A82AA000000000000000000000FF859100080004D8018498000B190981380180180080000160\n\t2680800620600600000000033414000620C20000608600600602610600C00608400402A2142C62202020000000000000000000ee4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (070000060160\n\t2600008000602600004000400600600780790608600600404414440008608BC16007800000000000000000000000FF048280\n\t0800001C008A98000018018098008004010440806006800C0744602600002010402701002040000611290684708F68640610\n\t48360840004C248A00E903001000000000000000000000FFAB920000100008024A9C00001801801800C01C00800000530400\n\t900600600600804000628600600402410400720690600E006024006006002004016040007046004000000000000000000000\n\tFF74DF0008000000000818000298C9903800821800800100400408080600600600000000622601600000041400202E007007001e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFB289000010\n\t0050018230000238238098A00A1C0904404020070084064060260880000244060B008246808439010610E0060060A020C00A\n\t0000022C2442004100000000000000000000000000FF284F800000001000A01880101801841C0AC00501808000600EA80806\n\t0160060004000020840000282840400048A60062460060041222C01420280062A208EC2E0A4400000000000000000000FF27\n\t06800080081804801A000018018018008000018000006A8600800602E0060081000800840000000060800042060260060064\n\t2408201202220040A002206042004000000000000000000000FF2C53800100105000801800001801809C0080000100004060009e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001402103001\n\t00000300048030010000000000000000000000FF95C5000000001801808000101841811804803C918000082006A0000600E0\n\t261000000260861061402940440040C60160460060040460C01120104062A2086446044200000000000000000000FFCB9800\n\t00000010018000000038838A38A08C1841810040601700804600601605040000400600640002000440801600640600E08030\n\tA0100020000A6002404004004000000000000000000000FFA6D600000000181984D100041881883810803821000029E00610\n\t002600600E02000000600605821200410410C00E00600600E04000640204A042026002214014104000000000000000000000005e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000080000000\n\t00000100000004012012002800008008000002000800000084001200A8000200200000000000000000000000FF40A1000000\n\t0038888E88001C00100AB81C88CC0680002522432AA2AA2AA2AA0000005422022081004024023122AA2AA2AA2AA310042162\n\t0021002AA102002000020000000000000000000000FFCA3400000004000200200000A0020001220020018000040054006000\n\t0000000000004400100002002C40A4150000000000000130410080050000004048300480500000000000000000000000FFBA\n\t0D8000000880400000000200C80000000204C800001081000000000000000000000881400C0100008410000000000000000000de4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5B8008002014\n\t0000040000A02200122000044000008000090010050040040000000040100044028010C80010050050040040440000000040\n\t0200000C20010C024000000000000000000000FFB0C2808000109113921800001001555951951D53800010E107556D575575\n\t5600000052455654E101157026036D575575575560262564564A40002164045561360C6000000000000000000000FF993300\n\t00004CC8AA88A8000009008AA8808A890880002822822AA2AA2AA2AA00000000A2A22D20000AA0022222AA2AA2AA2AA20248\n\tA20A34A0002AA2220AA22228A000000000000000000000FF70EC0800000222200124000B0108000200000400000084024080003e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000000000\n\t0000000000000000000000000000000000FF473F0100000140200000000280C00000400204040000448D2080000000000000\n\t00000C80001000800084101100010010010000100880080080012880100000900C8000000000000000000000FF22E3000000\n\t04000204C0000020024000020000000000100010001000800800000000000000050200AC08A04200000000000001202200A0\n\t120200040120000440400000000000000000000000FF011088000008088888080008584D8AA88C88E8A880004030122AB2AA\n\t2AA2AA0000002022AA202000002112003AAA2AA2AA2AA3120023022020010022022AA002012000000000000000000000FFB000be4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00400C000000\n\t00000000430000500000400C201800004004005004000281804015800004004000000000000000000000FFEC0A000000B008\n\t00A00C00800800800840800200800000200A082C02002082022000000002002080002002C82002002002802802C020020020\n\t0000280A082042002000000000000000000000FF2B2E00000000000000020040000000000000000000008008000000000000\n\t00000000000000000000000000000000000000000000000000000000000000001800000000000000000000000000FF554600\n\t01004003000024000000002000000000000000000800011000000000000000400000000050081C0004044010000000100000007e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001040040\n\t0000040000000001000000000000000000010040100810000020000000040080000000000008000000000000000000028000\n\t0001000004000000000000000000000000FFFDEF000008808B02A00800820800808800800740800000200201289B20206308\n\t200006000200200000240200200240200227A002002002002029003003002002002000000000000000000000FFBC83000001\n\t401A01A01801801801801A410000018000006816106406006906046000000006004000104007506006806007005005C04004\n\t006002007006106046006000000000000000000000FF108A0000011000010040004000004000016000A0000080000000000000fe4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002000016086\n\t00400E106000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF51400000000000\n\t0000100000000000000000000000000010040048000000008040000000000000008008000000000000000040010000000000\n\t01000000000000000000000000000000000000FF96B7000089A00803000A00800800808C0080020080000020020020028020\n\t0200200000000200202800200202242B002002402802002002002028002802002002006000000000000000000000FFA7510000014040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (260060010011\n\t0640C0004C81000060060160061442020030880C200120628E04406E006000000000000000000000FF226100000088490001\n\t08018018014938508002818000086406002006C0600E00E00000000700600001420011610608400600402208220216A00040\n\t641760404608E000000000000000000000FF5175000000A00A00002000841041801A00852000800114600610700410600E00\n\tE000000006114080102A0080600E0840060010035520028120A8006006104486036400000000000000000000FF9950000000\n\t880800000001001001083080800080000000600600604000604600400000000600600000600040600600400640022200228A00814040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001C51414009\n\t801841815C3480000180000160060020040060160060000001040000A214248621744600C00890E10E10640704608200E006\n\t046026006000000000000000000000FF7162000004241A01800113041801A0B054840000000000C00600280200700E004000\n\t0014448820A0000800216206206234212882113A0000608000E007807006006000000000000000000000FF4A470000000018\n\t01804001841A01A11C40820001000000500608200228600600600100100410208000600149610E0048042020034320020060\n\tA9016006086306026400000000000000000000FF0FB80000018028D061880080187580188880A0018000827206002026106000414040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0441E85608E4\n\tB6806000000000000000000004FF7D4C00000185180190000090181100594081040080000420061100070068060060000000\n\t0408420400612604601604600E0040004008234063000060060C68A6006000000000000000000000FF3ED1000004A21801C0\n\t0085801001081C001442400000002804002802106006006000000436106204006007826007C060C6A0080082800A00400482\n\t680600600E006000000000000000000000FF1E2A000021401C01002001841C15C81800882221800000500600298400600600\n\t660000100C4002004982661A6826006C8004706F02600C80600102700700600E006000000000000000000000FF958D00002100c14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600008005400\n\t02040C42062A6486086856004006107C24804004006127C06006406000000000000000000000FF063C000201811401C00801\n\tC01C01C11824808001000094710608800244600600600000000708020500C446216016824006014004214004004284086096\n\t22720E006000000000000000000004FFD4B4000001E01801000801801801811C0080000080004028C600080622E006006000\n\t20180400400001401180610680680400400202A40000600408608641600608E000000000000000000000FF34E9000000821C\n\t01084801091069801484804000000010300600000200E006004000200004416004404480436806004008190C5A80213825C000214040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80200001C018\n\t31A01801805A3080200020060000060211460040000A0855004804144816D0650649724CC8C0061062061260008370060040\n\t06206000000000000000000000FF954400060180B2410118016018298110218181A800009860060000020060060040000200\n\t05064001E0400600600600720428C00600610C03E000026046006006006000000000000000000000FF3E7D0000018210A100\n\t5881811C81C0D80A806001002040604600002200680600600020000541400440001E00F10620C000005C4584C5858C608448\n\tF8468070A7116000000000000000000000FF09B61000A9801009C48800809801801C0080000400000060060108022461260000a14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600200400600\n\t6000000000000000000000FF1ED3000000001801000801001801801801801800800000600600000600000600600000000400\n\t4004004006006006006006006006006006004004006004004006006000000000000000000004FF020A000000001C01000801\n\t001801801801801C008000006806000006000006004000001004004805005006806006006007006806806006806004806006\n\t804006006000000000000000000000FF28AD100230001810240101811881C01A4B8018048000006006010026200006006000\n\t40000400420400440604E00600600000000600E04E0040860861044040A6006000000000000000000000FFD5F300010004B800614040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000006A46004\n\t006206887006006006006802802006804104006008003006006020000000000000000000FFBCB7000004000800C01001001C\n\t81C01800801A0180002020062A080A000086004000A00084A8600601484680600608600E096052802006E240060260000020\n\t06006000000000000000000000FFF8600000002002018018008019018018000018008000C16116540013006146C0E4005405\n\t0E504104406014344006006940121202103006046005146442004006006000000000000000000004FFC7AD00000000000180\n\t1800801801801800001901800000600600000200600600600000000400402400400400400608600C2040020020060060040000e14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000180180180\n\tB880801800000080700600004400600600400000000600400100600400400700600400400200200600600100680200000600\n\t6000000000000000000000FF5AD8000000000800800000801801801A01821801820080200600180500100600400000000404\n\t6000004007107806047801001006006406006080806006002806006040000000000000000000FF51DD000000000800900000\n\t841841811B41801801800000E00600000400600620C00008010C0140A010D02E2A60060460A0028226087406006000086826\n\t000006006000000000000000000000FF9CDE000000000800A01081001A01A03C00849800840000600600004A80002600600000114040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A0A2C6206000\n\t000000000000000000FF516A000084682D10A080400018218B5802081E018000026A4E10044E846807086001010084114000\n\t20603480C206216406026A08080B0E242020026002102006026000000000000000000000FFF74E000200000800A00000001E\n\t01801800001A0180008060060000060060060060000000040040000040040040060060060060000008060020000060028000\n\t06006000000000000000000000FF2A89000204000800880081821821801A20809900800000611600100C0000660044000404\n\t8620E000C8620400500680700540401200200600600080640B002006006000000000000000000000FF3ADB000000400E008000914040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000814000\n\t010092000000002E0028040280120101000000210010200000000000000000000000FF942200008018621209600004007000\n\t40C000000000000000000000000811000280000080001800000001001204008081C0500240001000018021000028408A0003\n\t0000000000000000000000FF547F000014060804868071001801829821041002000000280602648621000E00400000000620\n\t614031620400410E10640600601008080600201032E082002006806000000000000000000000FF7025000010250824CC4205\n\t353A11A01CC1213B4B8000C8E106826886A96A0EC2C000400A06C06880904C04CC50B6086956C8E840A40006812800A1694A00514040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C10CB0CC0C00\n\tC44C10800100200B42300309211308A00000111305312992302300320228340B2A302300A103303020083443202852812000\n\t000000000000000000FFB6F900420020010030020622830835201601E2900000820808840809008200BC0000210F90C48810\n\t040C00200020A00828808800B00D18C008400014408810C1004000000000000000000000FFFBC200000A0094210010018028\n\t008809018808488000002AB240210212200200200000000201200008207A4820834922120024024320022020000020020430\n\t27002000000000000000000000FFDFD8000000000488000100190000000400001020000038C040086220001010010000100000d14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A82A80000000\n\t00000000000000FF626F000200220A30A00A30808D10B02B24A00A228000CA2002802842802802CC200080040344AC00AC28\n\t3300280290200300210AA02C02812800802802012002002000000000000000000000FF70D900022420100124D28534224224\n\t80090002100000810A44C308808008048080000008C9100800010900800804A048A1010C2494C8D4D4090080480488400400\n\t4000000000000000000000FFAD6D00000200520B003053141801815AAD011821800008604600630600600604600009040648\n\t600040E5165061060161460062142C4416016110006004034006006000000000000000000000FFCAC70020104A0880D50C8000314040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8200520280AA\n\t82A82A80200C02082083202202002A82A82A92A82A8000000000000000000000FFD3DE00031035034034030024C24C0D4300\n\t2002000000D300A8C00400D50D50830000001240C00C00010D30D51550108CC8C51140948B30AB0900550D51450550550000\n\t000000000000000000FF1433000C044004004085024004000004004004000001001001001001001001000001000001001001\n\t011010001001001411209801001011111001001001000800000000000000000000000000FF220200088808A0820940002000\n\t0000000400008400000008880902082A82A80000000008000000000002002A82A8028A082A00000000000000002A82A8A20200b14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018019008008\n\t40800000200210202200200200200000280208240002A04A00200200200200A01201210A0824000020020020020000000000\n\t00000000000000FF5AF60000000CC0CC0E00900AA8AACAA95800000400003B02A83786402A82A82A80000002A83400002002\n\t402A82A82A81000003403C02002200002A82A82A8AA82A8000000000000000000000FFF9B300084200201200002A08008040\n\t00280001280000000A001210A80000004800010000880D00032C000000000142000008020820000000000300000008080000\n\t0000000000000000000000FF97E10000B00880880820200AA0AA0AA00200012800002202A82000902A82A82A80000012A82000714040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF5180400400C00C00C30C00800810800C00800800840000300244310300300240200100301302300108240311\n\t3003143443003003013002002881003003003003000000000000000000000000FF9ED5080001909895801001801001141001\n\t801801800009600610600603600600610000C0040041000060A600608640601640402600640600E00050E00E016006000000\n\t000000000000000000FF784E00024422422320542A00040020042420030C000081080480089480080080000080400504C800\n\t884880804805005354CA48C4840840808800804800804004000000000000000000000000FFC7A3000090800800808800A01800f14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (490000080000\n\t000010200100010108120030000088000108000000000000000000000000FF1BAC0000000800820000000000100A00000010\n\t0004000140004861000082040040000100080000800000200101202804002040000104000080000080080000000000000000\n\t00000000000000FFE299080000800808029800C00410440000800800840010201A0220420220023021800020020020000002\n\t0208200202208A002450002002002080282042602042110000000000000000000000FF27AD400C0040840140040000000000\n\t040000000000000810100010010014000000010010010210010800810010410011210010210010000000010010014090050000094040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180184490\n\t0000601604240610C00604600000600604000030600010600600600620400C04201014200004612E10601608800000000000\n\t0000000000FF907A000801811000821003819805893801961802846001E7E600204606405E1066000040041A600001608022\n\tE08618E21601800402032200808202600609E106000080000000000000000000FFEA8000000192100080D0258058119258D4\n\t001800008054600600210600000600610000600600605000610022E1060162060004C60082200090C8006006406046000080\n\t000000000000000000FF23D0000800148040012040004004008154080040090022000002048011002004000000000000005000894040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFEAD0000000881888AB1A8391184180188700799A80002AE2AE37A22E0062AE00600000041010000050230221E2AE\n\t2AE3CE34A2362322A84120002AE0340062AE2A8000000000000000000000FF97EB2002008458008018498918019258418018\n\t01800000600610208648600620C00000222202A8002C20220460060060060020860080001088000064024CE0060000000000\n\t00000000000000FF279B00000181104281200084592D809810929820800000600600200604C00614600000410C3000000161\n\t0810600600602614400C08200224200000610C006006000000000000000000000000FF9BA8000001801020840001401C01C000494040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (440860060060\n\t1600C084086006026802006546046006000000000000000000000000FF8CC5400401D35D491551058D190189594B95594180\n\t0010655640044600655655600000655655600455455455655655614E0A041645655644E20455648640655655000000000000\n\t0000000000FF42870000008A18A88828818038018CBC8982984480002AE2AE2022A64342AE10600000010021080204E20C22\n\t62AE2AE2062062262262AE0860022AE0043172AF2A8000000000000000000000FF73E9000000A01A0080080180584B801E01\n\t801813800022E0060AA10E4B400600200000200200200000600400600600620640E0C61040060040000060320D780780000000c94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801843800010\n\t600600000604E00600600000000000000400000600600600645641404402600610EA04006048046006000000000000000000\n\t000004FF686C000001843821A20A2080194B811821801908800000600610010E404006006000004004004000002002006006\n\t006106104094116006006004006104006006000000000000000000000000FF4512000001A89A8DC88CD1003A01841A8B0AB8\n\t00800022E2AE2282260862AE2AE0000042AC2AD8002AA2AA2AE2AE2AE0060202042062AE3270062AE20428EAAEAA80000000\n\t00000000000004FFF398000C01C0DC0324124DA21A8DC01821881801800000600600001610400624E000006026026000004000294040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFBA7E0000890898808818008038298058190AB80080002AE2AE2B02AE0042AE0020000240040040002002062AE2AE2AE2\n\tAE2340060860860860002AE0042AE2AE000000000000000000000000FFEEC300000500184800988504190180390180184580\n\t0000600600000600600600600000445444C40400002600600600600608403640600600E00400644400600600000000000000\n\t0000000000FF278500002102580202504891180395184380190980000060060100062CE00634C0003080801001400D008E00\n\t6006006006014504056256226104006108006006000000000000000000000000FFD94500020100180200300D531801B4380100a94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600400600400\n\t60B428E10A2B400400600E004006000000000000000000000004FF23020000890AB0AB8820058258D58418888AB90180002A\n\tE2AAAA82AE1462AE0AE0002842082882002AE28E2AE2AC2AE2AC2262AE2AE22622E0042AE2062AE2AE000000000000000000\n\t000000FF92010011531150949488458C990188980495588D80005565515405565165545560004941544004A4504536556556\n\t5565544C6404046222004104556346554556000000000000000000000000FF19848000050000008508219118019138008018\n\t01800000600000000600E00640600001400400010000604600600600600400E006006086006400006056006006000000000000694040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (050000006000\n\t00000601680614C0000B404E0CC10010E0868060040060054C200410E0060940008063060000060000000000000000000000\n\t00FF5FCA0000018018008058818419018038040018280000006004800004D060050060000060040064040460300060000060\n\t0000A0060260B6026204006046003006000000000000000000000004FFA43E0000E98AB88888911B8038238018440AB8D400\n\t002AE2AC2A82AE4262AE2020002443C42440002062002AE2A82AE2AC1022AE2062163060062AE10E2AA2AE00000000000000\n\t0000000000FF2E5E00000182102180408980585584194080182180000060020000060260040060000442000B000402C0060000e94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tA536804041801101800811801801805821011801000180700000000640700000600000400210400000402611600182641605\n\t6106404084006100006046007006000000000000000000000000FFBB3D802001903081A00909801811801821001801006000\n\t70C701000700680280600000400009C40000642680700641E28F10668600E08406600080702601F047000000000000000000\n\t000000FFCCBA00000180B820801001801801801800401801040000E9010000A6116004006000006086006004204006007804\n\t006080002044017006004005086886200007800000000000000000000000FF9096000803801843A410219118099518A8001800194040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20600C044002\n\t012006082220000488202516000000000000000000000000FFB5C00000009018030208018018118038018038008000206047\n\t0B000610600200E00000402408C02040640030E00600E0041040420A20062020003022020AA00E0800000000000000000000\n\t00FF29240000018010218008818018018D18210A1801030000E8028000064960200C60000060020020005261100468840060\n\t024322D640904200E101120000002287028000000400000000000000FF461980002181182180088180180180380120980102\n\t0000E0060000A621680200600000608000240000600001600444600202A0062020000060800000802030460000000000000000994040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001083510000\n\t081000481480001081001003000400400002280001103280A02301080A00802004400A0000000000000000000000000000FF\n\tC80B000000801820040803805801805815C05022800100E0010002062808208C400000600621604050E11000600400600020\n\t249220004600A000020100012006100000000200000000000000FF49B0000000801805002801891801821841801810850040\n\t60261400060120000160002060441440080460002460042160080100420A00062824A0502012522006050000000000000000\n\t000000FF4F5000000080180000290388B80191180B94182A800006403C00021E00600000200020400622600800E00001610000594040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF653C\n\t00000104108202100100405404000040000000010012808000001410080000000000A00A0000000108000880000000000000\n\t000240000200110089028004000000000000000000000000FF1F8B0001C00008899400AA8020220000890408C88000552003\n\t2AA0420122D22020004224025020022823022AA1822AA22244220219250201200048A08240A2AA0000000000000000000000\n\t00FF2E9000002000404114800004010000200011580000012460000063442508068060004002304280000080880000040000\n\t04000008000440208002020008400000000000000000000000000000FF97B580000A0D00040020001100081500422200440000d94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1222A3A22020\n\t2222200028A20222A2AA000000000000000000000000FF477800080104100300100111000011200551000000010010110014\n\t00081001400000100024024000028001004A0100480D080508420010200001148411015004000000000000000000000000FF\n\tDF7F1001518134011159558C9101089155555955800155604F557D56417547B56000556404404500556427D570575574A4CA\n\tE4564D6116556000C46446505D56000000000000000000000000FF579B00000A08A8A880A8AA8248D48408A880288A800000\n\t22A22AA08A2425020AA00004A10A01228050224A2AA02B2AAAA200A0220020221220800021220A22AA00000000000000000000394040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000080000\n\t0010000000000000000100230400468100000800040400841000000001000040000000000000000000000000000000FF4432\n\t08004010021004220011000215000040005400010000A8800800011010148000000050040300000010800228800350080010\n\t008080080200000000100800000000000000000000000000FF1AF40000020540A00000000401000020020000000000000400\n\t0000001000008000000000000880000000A00010000008000000000A04100100000201280000000000000000000000000000\n\t00FFB73480008C900852888CAA8038298058A88AA88080002AA0022AA2AA2222A22020002AA2922120002AA2022AA4822AA000b94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFF1776004\n\t490002410010010001002000000000000000C00404040004800000000000000004000228005800894200000000041C040418\n\t00004088000005805800000000000000000000000000FFB349002000800800A80800A00A80848A00800A0080400520A22020\n\t0200221280290240200203000100248A00200200200280200250A02B082200002042422080002200000000000000000000FF\n\tB0F300000000022000800020000010000000020000004002080300001000008008000000000000008800005000000008808A\n\t0288820000800000000000000000000000000000000000000000FFECC201022000000000020000000000000000412000000000794040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (228A0A288200\n\t0000802042000000002000000000000000000000FF7404000200000000200100200400000210000000004000100000100000\n\t0000100000000110000031000800000080A00820000004000000000090000800000800000000000000000000000000FFF8E6\n\t010016800800A08880800E00E00A08804D00802000200206300280201208300200208A60000009259A95A41A2AA02208208A\n\t08208200200007A00301A000002000000000000000000000FFE871004001001801889C018018019518018018218041837956\n\t40F006106416006106206004030000CA45164C600600608608608C516056106400006046446100006400000000000000000000f94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006206016006\n\t00800000650600800050211400E0000840140061082AA00A00400054600600C080006000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF6B7300000000100000000000000000040100120000008000000000\n\t00004004000000004000000000001000000000805004000004000000000000000800801000000000000000000000000000FF\n\t67CD000401800801409001A00800A00800800800800000200200200200200200280200200200030008200220200212A0020A00054040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (EB4000004000\n\t7851938001899A458604050280098200204216006206006016226200006004028000C280010068060840E44067B82FA12B54\n\t0400C85226108080004000000000000000000000FF9C31080000001A19850001901C01848807800801800098C08E02700622\n\t600600E00000600600000000060410E004000140107400002042000000006486004000006000000000000000000000FF3CC4\n\t100005005801A00005821809810801831A55820021449692600622605642540041685454000105280040708000C404856044\n\t802D021200810060C6104000006000000000000000000000FFA6B1000001001803800001811801000011101881804004400600854040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00680E106C00\n\t81490E120021104000000000000000000000FFD3D80000008091154028A3803421A01811C00A01800000788600600600600F\n\t88604780E40200000020280E00608100082020030E036096427008405006008008004000000000000000000000FF03F30004\n\t11C41883A0000980100000080180030980008040060058060060060028A600F8480003110108088062060270060048069068\n\t0680400801288600C010086000000000000000000000FF3ADE000005801A03800005841010A01A098808C580200260071040\n\t0601604E00600640E5523000002821143068820164160AC002006A86924080242006904000006000000000000000000000FF00454040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1601E18E0824\n\t060002741D0014A04096806080542002280EB82A60B609407C006016017008006000000000000000000004FFE14E00222100\n\t1E01001001801895811C018000018020106446004806046006006006000C060002004421060065060060072861044AC0A490\n\t4200004006842008004000000000000000000000FF38FF000001021801501001811C15801801800B01000010E00600400600\n\t400600600610004790000401680681600004600608600008400400400480600E024020806000000000000000000000FF360D\n\t000050A0D8410128B3803009840C0DA00011800008C09600600600618608611E08639008051106400700EC868000180E000600c54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000421021891\n\t2808038058118818018240018000106006004006006426006015D0010000028008040800688682E31604610408FAB6006404\n\t084406082440004000000000000000000000FF2FEB002031201881010801901C80C01805820A01800048E036804006022006\n\t40600400100100820414480410640004692600E00100400C006205000017053000004000000000000000000004FFB33C0004\n\t008018010319018018018828058A00A18001A3589682614600400E28600600010480000010020608600680612600C0408062\n\t06204004805A06202A00004000000000000000000000FFE968000010C01B014018E191180100A8418808398020024286026000254040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0600602410E0\n\t0710C846026000000000000000000000FF8EC9200400803832100821805A05201811884000A0801020060070060062062000\n\t0854110502408088E00600611601689443100010852E006400006406806286006000000000000000000000FFB8C9000441A1\n\t1F21208029801A13300C098800008000605006006006002006002004000624020400004816106426486C0600C00000600660\n\t6000005006062080004000000000000000000000FF68D600000380B803040001A11814921841808F01808080600600695608\n\t6006A0642402191C8C001500CC17087A0870600628180801440441602400840740A400024000000000000000000000FF488600a54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (608644000000\n\t008000004000600400E2344060440A044800400600A004006006006006006000000000000000000000FFCBD7000000801000\n\t0008018018010018018000008000002006004006006006006000000000004004006006006006006004000000000006006004\n\t006006004006006000000000000000000004FF9075000000801000C00801A018014018018000008000003006004006006006\n\t002000000000000001007006006002006804004004004006006004007006006006006000000000000000000000FF7C992000\n\t02A21A0001080D801C01021A01848200A0008020060060061060468060200000340840040064060068260C6004100108000000654040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008018008819\n\t01A03A01009801800085804004644602408640E146452D204000020060454C650450608C80601088088108008600A0048060\n\t06804806006000000000000000000000FF749E000180A01A009E9B01C03C01801A03800001800008600600C0860362060008\n\tA0000000082000006404026804B0200488480400C006082000806006804806006000000000000000000000FFEDD100000080\n\t1841401801805801045845800201802010612645600640640E00254848020251450C04715052600405631000008010C00690\n\t2004007006006006006000000000000000000004FFF62A00000080180100980180180180180180008180000064160060860400e54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A00000600600\n\t6006006000000000000000000000FF38B8000001801A0080080180B801009809800C01000000600600408620600600200000\n\t60070000004860044070010060130A6A870A6886002000106006006006006000000000000000000000FFCFCC000200801810\n\t200901801C01C01801800A03802004744602600600E0C6254540406004002021846D42086006004006006006803006006000\n\t006006006006006000000000000000000000FF354E000000801A10000C818118018018118048C1802000622E00600620A09E\n\tA2420829628400C2A80260EA28E2260882AE046EAE0C200600E000107006006006006000000000000000000000FF2C55000400154040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80000092712F\n\t22A800106A44C16CA08505494C5335204826A00801036086A0F046A06000000000000000000000FFC9FE0000C3E01C0D0088\n\t05803805955C31800A30800008204608E22600600644C050006200880200A361020870161040048080008002870500082864\n\t1604600608E000000000000000000000FF6C91000201A0180120080180180180180180080080018020060078060040060040\n\t00006000000000006006006002000004000000000006800000006006006006006000000000000000000000FF583F00040180\n\t1840280801801C014458418028A1800000710644400600200E80600000E00640200000640400689C8460020420020020070000954040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000104401000\n\t00021A801A08181000000000200010081461161000081060105000000100010001004A442424430C40400002800000938002\n\t0100000000000000000000000000FF48BF00008402010001A100040050000184000020000000100000102008000000000006\n\t0400000000888601608040000000130000101600000000000808248041200000000000000000000000FF3298000013019881\n\t08080998180100182191880000000908860260060044860004304062060820000460840160A41048C0008040200026000000\n\t016006106006106000000000000000000000FF23EE000209AA9AA1B044A9AC1A81A01A83A88A848000A0848684680EB1688600554040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (406806056096\n\t10E000000000000000000000FFC840000540CD2CC0C10C80D40C20C28D10D10D44800141200300A08302B40300243142344B\n\t403000A5302220335350202B33320304200310300104B083503222402000000000000000000000FFD82400036038424E4002\n\t432222002042002002460000C00C00890700A008008088008009E0010A01600800180E00800A088048B4804980A00800CC00\n\t00810430C90000000000000000000000FF5CD30000018008309008A0800880852800800988800020A20200A00201A0022320\n\t4008200A22A00102217200201A00A81248240204200250200822200240200200A000000000000000000000FF14730000080400d54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (202A00000000\n\t02000A082A80202002002A02280400402800020802A8008000000000000000000000000000FFD3AE000000B44A20A00A00A0\n\t4A10C00A14A00A208000923002043002842802852810803442002B0051200280290280A833002803402C02012800A0280282\n\t2802002000000000000000000000FFF37400025520820A04A4012202822CA2A034A3040000C11004810804A9080090090080\n\t910C004800024940804A1092088480D0848AC8AC824880834004B00004AB4000000000000000000000FF3C1800000B00180B\n\tAA5829801809903803801811800000640600640608608E11600008610408C00000648E10E00600640400415430450620400000354040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0880AA0AA028\n\t0004AA0B000000002A82A82A82A82202A82002202A03200004800300002A82A80A00882003002302200A04002102A8848000\n\t2A8000000000000000000000FF17EE00014024431430A35415401035254424030C0000900D50410D50C40D50D00C50D40A00\n\t000B01290D48D50810D48D10CB0D40C008004509008005505488004D0000000000000000000000FF6A21000A004000000404\n\t0000000444200040054800000000010000010010010411090010090010018810410010012114011090490010814010010800\n\t00401001000000000000000000000000FF3AFD0008800000C00800AA08802000000000004800000102A8B802A80002A8200200b54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0400C8010000\n\t00000000000000000000FF7681000040800800A2280080191084580180084280008028020020020420020021120020020003\n\t0000A00200204200A03250241208A08A50000002A802CC2002000000000000000000000000FF70EA0002860AA2AA48C0AA4A\n\tAD001188AA88C08400012A92A82A92A81102A81302202B02000000004007182A80000000400400803202300100000C12A810\n\t00002A8000000000000000000000FF22C8000A121080000200004004C2000010092000000022000102000008800005008000\n\t80C80000020200000004A0000020000008110288080002349001000000000000000000000000000000FF18220002A80AA2AA00754040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100900100100\n\t10111102A9001221201001101001501001001001081001000000000000000000000000FFAE2B400400800C40C00C00920C10\n\t884820910800800141320308300200210210200200301300100100300300234315345350340B00B283011001043403003003\n\t000000000000000000000000FFEBAE000001001901811801801001001001001801800000600604620640640600628E106104\n\t0000000C40A642600E406106004106224006020080106106086006000000000000000000000000FFB5810000092000000004\n\t002002235002002422100000000004804804A90800B108008088B5000800B448A4800B11320C80855040804800830C00C00000f54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (301480C80840\n\t820000880D200100003000000000104100000000005401085400A01201502160300800000500080A03081200001000801000\n\t00000000000000000000FFAD730000000000A000000000000C000000001801000001000002000040E4061044000060000000\n\t000A00D022000001600C0045004C40004201000C0080000000000000000000000000000000FF8B820000008C0810800800C0\n\t000141043018884080002022120920820C208200200A0924C200000000201208A0022A208208614A00E3C209800000264201\n\t2002040000000000000000000000FFCCCA400C011004004684000A0584082000000000000100100100130011000000008000000d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00200000000\n\t0000000000000000FF07A6000000004943041841C81803C11D55880025900002608640600600600008E20220620220000004\n\t612E0261140060200800021000020C04000A6206046082420000000000000000000000FFBA06000800042080013002813913\n\t801821801913844003608601600600601008638238600614000000400610404649619420434E2D461221000000E006126200\n\t208000000000000000000000FF09DB00000010181000500D025821905801801801808000201608600602600020400200E046\n\t00009230600600000608600420020E20014220009200E04600E206110000000000000000000000FF22B00008000800240280008d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200000004086\n\t002022146000007203206006000400006006006006000000000000000000000000FF3821000058090991A012AB0019C10419\n\t018A800180002002AE3062AE1162AE02C0002B61140100002AA2062A83022062A6A2EA38A262AE3380002AE2AE0062AC2A80\n\t00000000000000000000FF32A5200144044A0590100189184502180B80401580001440060060060460060040040064444408\n\t0000200600004200E00600200210A006080800006006546004000000000000000000000000FFCD7B00000000805103380084\n\t58099139418000A1800001600613600629600048600200E10A0903000040CE00608C14601408008000000200010000600600004d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180030181580\n\t00018000114006006006006006036006000400400D0000400600400401611700400601400400090000400644600600000000\n\t0000000000000000FF5BB1200124954111D55555801B54025835954115800045055655655644655600400654054A15028455\n\t623655029440E22F4B00B60A0554450004554556556556550000000000000000000000FF35300000820A340380B0AB913A15\n\t00BC418AC0D380002442AE22E2AE2262AE4860002A60440C00002AC32E2AA24A2A62203373212A62AE2200002AE2AE0962AE\n\t2A8000000000000000000000FFC711000210000C4380180182DA01009901800041800010400600600608E00620E00400E00400cd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF3D43000003001A01841001D09800D25A238000038000116006006006296006004006008022310B040000C6\n\t0020462043160401540480040C0804004006006006000000000000000000000004FF9E67000051800055A05A018458000098\n\t91800001800000400600600604600628E00200010004000000421600401410E006C88A049000060102000060060060060000\n\t00000000000000000000FF78000006818AA0818890AB101AAA1018018AA0A980002202AE2AE2AE0062AE1640022A02080010\n\t042AE0062AC2840261220000042102AE3010042AE2AE2AE2AE2A8000000000000000000004FF7DC5000A00800041D41400A4002d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000A0060060\n\t06006204444090044006006000006006006404006000000000000000000000FF261700008C0200A989102110188892180188\n\t20AB80002222AE2AE2AE2AE2260842222A00040000020002AE2862CE2AE2062A02042A02060000027E62AE2AE20600000000\n\t0000000000000000FF55A20000241020058010018018048018D1840001800011600600600600600643400E00000400000414\n\t000600600600402600000C00802400000400C00600608E000000000000000000000000FF2E2D000001009801853092935840\n\t915805808001800000200600600600608E0041060085500000002080060320460060960140A400409600000000600600604600ad4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (021951C0A001\n\t800001600600600600600E4A60160122040000060A200409610C0000A6084048104504006006002006004204006000000000\n\t000000000004FF3F9F0000A10818C18AB0C18018AB0019518A00AB80000262AE2AE2AE2AE2262AE0562B22440000002822AC\n\t30E2342AE02E0842040942AE0060042AA2AE2AC124006000000000000000000000FFF2F50001110159150C591580195380B8\n\t03B4015480005465565565575574C601654354015400000441255644640655041045430044C03400600400E5565560D40060\n\t00000000000000000000FF3CAA80000302980400180188180189580580000080001060060060060061060040020000940000006d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF6D5F00082181184180190193580111580580800180002B600600600700608E00440200A13600400212600624A1\n\t040074B64C600434400E006002002806004124006000000000000000000000FF26B7000015921005000A038018038018D1C4\n\t000080000068060060060068060060AE00000400600401200090400600000000C0B000610600600400600600440600600000\n\t0000000000000004FF5AB20000918078980AB83D8558A98618018960AB80004162AE2AE2AEAAEA362AE506AA020400400024\n\t22AA04632E2AE10401424040C2260060042AE2AE2AC01C006000000000000000000000FFA8D700082114184080104182B80100ed4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200710608690\n\t100402009608A00622210010E20604480E006000000000000000000000FF137C900041000001011001801841801811808001\n\t80200060060078070260044040032042062840200062013021230400312034172100064040800C6016006084006000000000\n\t000000000000FF3E008028014001E0001401841807801C01C080018220007006006806807006086006A060540C40104062C7\n\t020002F0E9A80C124620000600600003680E006094006000000000000000000000FF49DB002001A09C02840C01801891035A\n\t01C00001820000700608E80611700608622A82A0060060050861040422008090060868800870260A60050032060470070060001d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4BA000599280\n\t02600E0260068A60080160460060062860A80A640207000C0000060020080020060CA0000800260020162160000000000000\n\t00000000FFBA900000010018800010238438D1001831820023800020E0863160060070224AE246AD40140240002060464084\n\t4404E00648826002804E12208002000622200C006200000000000000000000FFDAFB800009101810840401801801025881C0\n\t0000882008740610401600680400602601610601200000222C006006006235003103202A46000020C0740600400710E00000\n\t0000000000000000FF5440880041011A0585100180190104B80180000080000060060040070CE00600620E806444442050C8009d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFBBC580000004400004200013404013400460000000000000000100018012284D000011055021050001021000003004\n\t60D02A0008020006040100490000000508000000000000000000000000FF82B8000009001812050825803801851815C00202\n\t80405264963060070070200A4202A8E08604E00050402C002000016226016110406206000140402206006006286000000000\n\t000000000000FF0D830000000A194000380180995380180182000184800160060460160C60100060070060045040C8044004\n\t0020140000160862240360560900000A0026420006006200000000000000000000FFE26800000102182200B00180982B00D9005d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00A2320AA202\n\t02222B0022AA0020002C22AA84A0C22AA000000000000000000000FF3F6F00804200A04300300002A0010201104004B00000\n\t0008000000008008090004008100000A04800A90280000080010810204100400001000000008000300000000000000000000\n\t00000000FFBDCF0000C90148968800AB8540800400000AA8AA80002AA2AA2022AA2AB0124422AA8024020D21002020220022\n\t0228825211A2A648A2AA4521000222AA4A04022AA000000000000000000000FF87FB00004210905000800000000C0000D000\n\t1A0180000000000C00000060860000042460000400000A00802A80800060000000042000064880000000002080400000000000dd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A8208001AAA2\n\tAA2AA2AA2AA2222AA0122A22AA2820002820222120A268A0122A32022022AA2820022032AA0022AA2AA00000000000000000\n\t0000FF583D80080100000100100108000509400440040000000048048C100500110100800140000000400011108032008040\n\t5081200104950000100000009004884008004000000000000000000000FF6F61880101D419010D1D5580115580B023555C05\n\t8000557556557D575574C65571475465564140004062864C64A615444648E12448E5564562004D6556306557556000000000\n\t000000000000FFCA3500008A8A08C08AA8AA8008A88009508AA8AA80002AA2AAA0A2AA2AA2421022AA0AA0AA30240024224A003d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFCC5401010020000040000000022000440000400000000000000000000000008000000000000000004100C8E804A0000001\n\t000000401100000000000000000800000000000000000000000000FF81220080100440900280001340001340044005100000\n\t0000000010008008880000B00080000205000100880800100404500009400C00000102000A80002480010000000000000000\n\t00000000FFCC210801002080400002000000000000B00000040000000800000000000000000A010000000100020204000484\n\t00000100010008010000020000001000100000000000000000000000000000FFD8BE8000328808128828AA9018AA9018018A00bd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (470040062850\n\t860CD106806110C16D37107406006000000000000000000000FFB4BF00000100100000100000040000000000000200000000\n\t04000044004005004000020028000001884B0152010000C050004840404820000089845A2480000480400000000000000000\n\t0000FFE87600000080088AC00800840800800A0080080080004122030C221210308220A00200120200000050200200200300\n\t203220202202210280208822A28A102402002000000000000000000000FFD4CF000000200600200000000000000000000000\n\t0000021880C098A1800808000000080880000002000000000400000000080080290000000000000040000000000000000000007d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000200200\n\t20020020020020028000AA1102A840200200200202000280208228E802002000806002802002002000000000000000000000\n\tFF915C0000000004000050000002000000000000001200000000000540000150800000880000000000800000800800300880\n\t000008000001000088000000000020000000000000000000000000FFB3A7010106000800802800800800804A008048048A00\n\t01B0020022A20020AA0020020C00820882A81125DA5DA4022B208200208A08A14280200000244307A0228020000000000000\n\t00000000FF879C000001801B15801801841841801801801801800045650634E49610610E416006080286000002505016006200fd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF9E\n\tCB000000805140801800801009000800801801008010410610E10600600E0060060001040000000060244042444260040804\n\t8E090000006000286006026006006000000000000000000000FF6BF800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000600000000000000600000000000000000000000000000000000000\n\t0000FF0730000000000001000001001000001200001001000000100000000000000080000400000400000100000080100000\n\t7004004000004006000000001000000000000000000000000000000000FFDC5A000001001000A00800800A0080080080080000034040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (692E00200244\n\tA100022000016026806026406000000000000000000000FF4A05000101808201A0980180B083881821881801000022F40680\n\tEC0F10E1970860069016060100021006842402AA8268042D4E284800062000022C601722E20F906040000000000000000000\n\tFF88750000039000B985380182110D9218C180180100008862A6806A0600600E40640601048401008300ED08024106A00A00\n\t02C88280081F00A082006006416416006000000000000000000000FF84CD000012A11401C058008552018208819019050000\n\t44E4460464160161060D61070000040001000920140C00100082D445004624410044E100016026006046206000000000000000834040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (007486006006\n\t00631608603600100411040056808E81600E00E8103164880262060888808CF0B712704F026000000000000000000000FF7F\n\t450000090000858018158414018018018000010000006006006406086406006006140504200010002A8A026C07C10280C460\n\t0224700E043000006006006017086020000000000000000000FF624E00004000300280180182020100380183000000000078\n\t06004006806006006016020904480409A0002610A20020048F0820000068A882000100600608704600600000000000000000\n\t0000FF8FA200001190300082180180000180180180010400810060061241060060072362860080040080001040469060040100434040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFF8B100\n\t0021011000E1581B801801051801990015840010668600620600618699708608000600020400400210700560044200070C08\n\t808640C00420600648EC06006000000000000000000004FF184C00004040300900180180081188180100000080000060B600\n\t4026016006806006000006010004A074444040041060160C401700CC8600E00040600710C006006000000000000000000000\n\tFFD732000000803200001801800C01803801048040800000608600400600600688602600080600000400E844084814000006\n\t00010E000347896084096946024006026000000000000000000000FF162400014800048180180B801061801801800021000000c34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C0C164C80807\n\t404004046406805086126000000000000000000000FF8D130005502408000498018008018018458100008000047806005806\n\t0064161060060005204084942042AC800002406206084314245C1631400584F817A26436006000000000000000000000FF2F\n\tFD000000884A10003801800C01849801800002800002600611402610E00600600600080000800524444448400702014E0B50\n\t05000417104004106006204206006000000000000000000004FFBDB800040110100180180580380180188180000180002460\n\t0629650610600644608608000600040202410280E20482608620C844D0000E0840060C62060060060860000000000000000000234040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060170460060\n\t0600680600600600004420084680608001000000C041200006306004006014002080042000000000000000000000FF253700\n\t00938440318018118018018018458100018000026006006006006C8E50600610734629028C89040E02E41720630610488802\n\t020E84E00004E844432A48002000000000000000000000FF139D000000000A08185801801A01001801800001800000600600\n\t600600608600600608080008000000C1061AE28604E04600440410000602400100662600E007006000000000000000000000\n\tFFD29B000002612A22413809805811901B018120118400506056C0E92600600765600600080000002508090681640E1204A600a34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFA320000001\n\t800001800801801801801801800001802000611600600600600600610605608608040440000200200E416026204004000006\n\t006006006004002000000000000000000000000000FF88180000018018008010018018018018018000018000006006004006\n\t006006006006006006000000000004004000000000004000000006006004004004002000002000000000000000000004FF06\n\tA3000001C01800801001801801801A0180000180000060068060060068060060060060060000048000040048060060070048\n\t04005006806005005004803001002000000000000000000000FF4DCA000041800402A498018018018018018020018000006000634040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AA44E0060060\n\t200660C0000000002000000000000000000000FFCCE1000001C01A00801005801C0380180380000380000160070068070064\n\t070168068064A6400804D00C04554001800006C0008808820608600400C002804000004000000000000000000000FF41F400\n\t0001001809801229A01809801849A04201800020E2A6006806006086036806006886020804200C2419440602E00E04400500\n\t4006006004206004864000000000000000000000000000FFC17F000001800410C00851811811801A118001518100C964460C\n\t610655654E4462571060064480C080004AA060000C05110008B400880680604444448600200000400000000000000000000400e34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010640644700\n\t6116046026000000800C07006400006840C0200280220000600082F423004000004000000000000000000000FF3486000001\n\t80140080180180180B801801800001800000600602000600600600600780608600002910140600280600100720288708F000\n\t086001006003000000004000000000000000000000FF6250000001A01000200803801801801803800003800080F006000007\n\t0074078160060062062002804000034CF00000000000680AC46006806000006000004000002000000000000000000000FF43\n\tE200000180100000080180181180190180402980A008600F0C00070AE00E20E22608F0062887F000000E20E00E286286026800134040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2300020D4318\n\t82AB1300A09A81A44A01A88341800082609692700688600E0C680E087246000C404808448C0808028800020AA5294C089468\n\t10A5294AB04200A04000000000000000000000FF2FFA000121900030000423C05C15801CA1C204038000286A0621622EA26A\n\t4621620600610E00001003031121420640023000C00802188620604008220204C090084000000000000000000000FF6F2D00\n\t0001A00000800001801801801801800001800000600600600600600600600600600600000000000400000600600600400000\n\t0006006000002800000000000000000000000000000000FFAA840000014014000018018118018018C180610180000060060400934040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600204204000\n\t2002040400000000000000000000000000FF701700000002010044800194B800033900011841800000000000422018002009\n\t850659020000050804000000000031600000440447400E080020800000100208880000000000000000000000FFDAF3000080\n\t0800640101A00000420040000201800001600008008000000E08800050800408000002488400090100006000831020080197\n\t220012400410288000100000000000000000000000FFFC7C000027051A1A0010008018018008019C003180000B6886026006\n\t02604600600600602600002022008404464080E54040020020800000600038200A404000004000000000000000000000FFC500534040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08602608E086\n\t08640E00021040000E00E146804106004154204116026010406054026400546000000000000000000000FF6A15000430C0AD\n\t20D48C42D40C00C04C08D04C3080002022032A3002003C0280322A40B002001100031223043202093422B4A4030AB0021030\n\t218C3C0330A001002000000000000000000000FF079F0402102092811842002042882002B020C2020000800A00A808092008\n\t01320A08000890000810810840A00801020821148904900A009008080692E0830880640000000000000000000000FF89DD00\n\t01489048000218468008008408008008008000102C0255640300200300200300200200020000023A02A00B00020B0020DA0000d34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08800880A00A\n\tA0AA0A80040AA08008A0A80000000AA82002A82A82A82A82A8000080000000040200200280888B803B00202302A88400002A\n\t82A83802A82A8000000000000000000000FF4292000204A44A04A00A00A02A44A00A20A00A02800081200280300280280280\n\t2802802C0200080140080210A84204202280A80A90A802402800802802803000802000000000000000000000FFECDD000228\n\t20120920120020030820020A2402000000B450048AD004804004004800004834000C010D08C8820810204808004D05004800\n\t954880000004835000804000000000000000000000FF79F90400858C100D005101805841851881851901800010E00601440600334040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800002000000\n\t220000000000000000000000000000FFC9D00000080880000AA0AC0A00AA0A40020880A800002A8AA82A8AA82A82A82A82A8\n\t0002200002002C84A02080014A82483402C04802A82000002A82A82A82A82A8000000000000000000000FFD1910002143503\n\t083543543501303543403523500000CD0550CD0D50550D51550D50800A88000C00A90D50520C81350410C40A88C40D302909\n\t00D50D50810D50D50000000000000000000000FF6180000C0444050040040040000040043044440200010000010000000010\n\t01001001001110001001001009941520001081009001029001101401001000001000000000000000000000000000FF13890000b34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008048008010\n\t10000A0142CB00C0CA40004C0CD308810C0800884800800800004804000000000000000000000000FF5D87000032810B0480\n\t0840800801814808820840800000280200280200200200200200200200000010204A08208AC4202200203201204201200000\n\t2002802002002000000000000000000000FFBAD20001400860740AA0800944AA89010088A08200002A82A82A82A92A82A82A\n\t82A80002A00000000000000200100880800002102002882702002A82A92A82A82A8000000000000000000000FF93A30008C0\n\t002022000000004400000014000002000000080000000100000000000000002000000000000100804800104000004008000000734040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (504420400000\n\t00001400002000400000010010010050010010890004C1241000001001200021018641041001421141000001000001001001\n\t189001000000000000000000000000FF6585400400C00C00C00840800800900800808800800100322300300300300B082103\n\t01302A541003302343002113003523143403402003442803123003043003002000000000000000000000FF1B7D0000018018\n\t45801801801801001821801801800000E00600411648650620E00620620600002001401654600610C00400E00E0060460061\n\t0000E22620E006006000000000000000000000FFAB8800030024000820020A2522002202C22002080000800004804004805000f34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (102284000880\n\t06406000000000000000000000FFF87F0008000080800CC01008801000000002000000800201001004080000000004000001\n\t001100000000000001300161000402804404460A04880502003202A0028000000000000000000000FF7AED00000100000400\n\t0021801800081800003801800000C0000041100002004082260042040A00400901082800080563043000A000000600000008\n\t8440220000000000000000000000000000FF91D6000000882854800800800C0A000C00808840800000262200200228200208\n\t210212A02A2001001426020620A208042200A20A312022222080022142000002002000100000000000000000FF6385400C00000b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600400\n\t000000000A00602640604C086088100026006000402012040006056000000000000000000000FF6AA8000001805101113041\n\t849401801C01801805000000600600621600600600608400E0040000801302060060A2000304016212102006146100000100\n\t400546016000080000000000000000FFB83D00080001380180103082100180882184B8CB010000600620E006006206086466\n\t00C00410000000E00001E01400000028E10E40648000E400202042048006246000000000000000000000FFDD3D0000010010\n\t4D821000901011810841815911000004450630E00600620008600610410400800000600404600000E0004A60060361200170008b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01C0A8058010\n\t8180B88180100100000040060000060060060060060040040000100062060162440002061000022020060060001062460240\n\t06046000000000000000000000FF6724200241A818018808AB8AA1918AB9418AA0AA00002AE2AE9002AE2AE2AC2AE2AE2AC2\n\tAE000000004204216002088012324A30B202882AE00002018021C006206000000000000000000000FF019E000001851091A4\n\t08018000438018B180100000000060060900060060060060060040040008400061440CE30804630200C00200A00000680010\n\t8440104006106000000000000000000000FF558700013580502500D001801009801805800801000000600644600600600200004b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600602600600\n\t6000000000000000000004FF45A9000C11841C40841801800A05801A01801000800000400601600600600600600600200600\n\t100000210000645200620400E00600E006006800916446144006104000000000000000000000FF40A0000555325490941951\n\t95480B94180D9551548000554556D4E556556556556556552556000004002044406108550140426C8688E516556404456096\n\t514006294000000000000000000000FF5D3D000083A8B093C8C8AB8AB0218AB80B8AA0AB00002AE2AEC202AE2AE2AE2AE2AC\n\t2AC2AC00002000424A3460862AE0A6220320A202AE2AE00044600E20400622E000000000000000000000FF287B400001809200cb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002112000320\n\t00802600622200600C08E10440C04600610405601602E006136000000000000000000000FF03DA000001804841A0180B8008\n\t45823811800000800000600600600600600600600600200200001000010644E2C020004C316054244026006C040162064860\n\t06104000000000000000000004FF2BC3000201A4108C849841801889811A8580000180000060069160060060060060060060\n\t0400080000004C00600E046104004504804006006004106136016006456000000000000000000000FF64280000AB88924488\n\t38818ABA418818618AA0AB80002AE2AE2262AE2AE2AC2AE2AA2AE2AC0010000003141C60040882100300540CC2CE2AF004A2002b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180180B80\n\t182B822001800000600600600600600E00040605601000011005401600601624602400401611004600640001600400600600\n\t0000000000000000000000FF85480000038040C38A98AB8A98358AB85588C0A980000042AE00E2AE2AE0042AE00222200000\n\t000001420E2AE0462AE2A431400402428E2AE0000C60262062AE006000000000000000000000FF5AB1000001812821803801\n\t8018018018A1820005800040400608400600602600601611242000000454410600610C00000402024C084006006004406486\n\t106006404000000000000000000000FF2EF20000D18A080980180180489580181580200080000CE00644600600630E00632600ab4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2242AE2A8000\n\t000000000000000000FF9C67000902089001001C00803941A0088180000380000B600648E0060060CE004026006022000000\n\t32000E00620000000E0044040000060040040040C0084006228000000000000000000004FF52610001200880CB88D8AB8AD9\n\t418C9801A880A380002AE2AE2242AE2AE0C62A808A2862200002002004062AE2A608E1064342A622428E2AE00422622C2AC2\n\tAE2A8000000000000000000000FF2129000048041912935B54D51801B54801D30351800020655604655655640655531652E4\n\t880004A60045265561083304C04240CC4A8556554106294210456556100000000000000000000000FF60F180001004180004006b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (860B00042060\n\t3408843040820600F41714000700000404400E056006000000000000000000000000FF7C990008D284002580080920B89581\n\t101584200980000060060060060061360023260060140003100541240044460060CF04E1270D402600040011500C10400600\n\t0000000000000000000000FF1D9E000001000400045A44041801A020A1D10445800000680608700600620680101611308400\n\t0000086214004108001200304016000006002005026126014807000000000000000000000004FF915E00000508F088888881\n\t2818218A510180049180002AE2AE33E2AE2AE4062AB0462223240000003041402AC0062AE41410420620028E2AA00430630400eb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (803801803801\n\t800001804080600600080600602EB0000400641000841003222840425610000424000600602080220004600A04C004000000\n\t000000000000000000FFF5A7800001905048801801E01801805801880401800000600700000600601600E086006014000208\n\t140406002000020101022086006056006400006084006006000000000000000000000000FF422380080080040AC01D41A058\n\t01C01801C80201804000705E000C1F00760710F286066C0460000001000644218612680140820E82600E0060010068C40070\n\t07000000000000000000000000FF29F0000002800002201C00001801C00001C00001800100700600710790784740120B0030001b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000000000\n\t00000000000000FFDCC100000180C00C819841C01821AA9829801311800040640600620600E00E00E08E0040060002002160\n\tC6006044100606002006200006022200012006002002180000000000000000000000FFBF7700000180204080148980180B80\n\t180188B0A980802062460065061060862860162AC30634000050C0021FE00669E58608030612020600200208A0C402220A00\n\t0000000000000000000000FF7CDB800001801082881A21803801A03883C40405800000E8C680800680700600522680702000\n\t000000203420402204600500B0CE90A15010210002602220C004000040000000000000000000FF692F8000048820008008A1009b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008050000000\n\t048840604004000600C006400000108080008288000000000000000000000000FF5623800020040010000024000094642014\n\t00060000000000002000000000000003200002400000000280C8030020006008400006080026088080020228000020000000\n\t000000000000000000FFE851000000808008801310A03815C048A1B05441800001200600E006006006200A052AC406400000\n\t0060842C000041610600E08600805008208002202640E006000020000000000000000000FF9F79000000800100900C01C018\n\t418C9815E3100381000061460064060160960938D60060460004004040100140000200061062565243000424000820860204005b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (408C88008AA8\n\tAA80002AAAAA222AAA2AA2AA2020AA0222220004001222A222242228AA220222AA2222AB1120800A213200A02A0000000000\n\t00000000000000FF335901042909000804804000014022A0804002000000A000008800010000010110008800000004000084\n\t208400000000C002800040C000040000080208211280000000000000000000000000FFF88000008009098191CC888AA82008\n\tC9008AA8AA80002AA2AA1062AA2AA2AA0F2002B0219A0002624022123920020A828259A2AA32228A4220026024022A040200\n\t0000000000000000000000FF6C4000000C00D0440C4001C018000018A020180180000040000CC0000000004088161560000000db4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF1DD1800000C0088482AC00EAA8358008548888AA80010022AA2322AB2AA2AA18200320221200020020208200\n\tA4220AA4022022AA04228A22200022202200A202000000000000000000000000FFF0BE800A0B04001100020420000A40002A\n\t400400000080080500C805004005081400C1100400010000C00100009004489000000000C0010440020100004C5080000000\n\t000000000000000000FF5A179001038458C1103913955801501801D55D5580000D755744555655755644735624ECC4000110\n\t52408E48E12E53400E5065571045565142024561260A602E000000000000000000000000FFF59A0000A0082822820CA8AAA9003b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200801800000\n\t000000200B00200010000000000000000000000000000000000000000000FF16750000000000200000000100000000000002\n\t000000000020000080000400800000C00000000110801EA86888004010000001000002000405000000010000000000000000\n\t00000000000000FFD3440100004C00401000A400009422A01440020000001490008010000000000293208000300000000C00\n\t302404002002501500014D00401080000003000200C8000000000000000000000000FFA2D610013201401400041000000010\n\t00A004400000014000000880010008004000101500800001100082000801080001000000000000000002000900084800000000bb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5801801C0180\n\t4001615632605654E0C712640604650640000100624600700603400690451701500E050001046D4541640601600000000000\n\t0000000000FF83DB008000000040002000001001001001002001000044580400590000400000400508028000022040411053\n\t800C084001C04800584C00000028004004804000004000000000000000000000FFAB2D000030100800A00C00800810C02800\n\t800800802000A1120820322C204208240204348240000000200200200205200208201308A00203000102234220A402012000\n\t000000000000000000FF500F0000000000002002000000000000000000000000420000440000008080040000000800000000007b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF9A4B000000000800800820808820800820800802800000A00200200200200200280A08208201008000284280200A\n\t22800300A00200A802020280002002000802002000000000000000000000FFEA400080000000000000001000000000000024\n\t0000000400000000100000000000000400200004288000000008000000800000000000010008300000010000000040000000\n\t00000000000000FFA6B8000000000800804820880820800820800C02800002B00200200A00241A00300A42243A0080000025\n\tBB5D200212A08200B10210B183000003002002003062002000000000000000000000FF406E000050101A01801801801811C000fb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000011171100\n\t444C002001120000040115608204420402E000000000000000000000FF551E00000000900100100101580188980180800180\n\t0024620610600E00620400600600000000000000602400400600601400008610000000001000602200410640600000000000\n\t0000000000FF2796000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000006000000006000006000000000000000000000000000000000000000000FFF72D000000001200000000000000000000\n\t001000000000100000000000000400000000000000000080000000080000680400480600400600080080080000000000000000074040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (810001808012\n\t601710600610608402700602700C20040800600600F08E00700E3020460A200000020108E002024306036000000000000000\n\t000000FFABD100000400D024001901841A018818418040098000206A6600E08C00E20420E006C87006100800906880000046\n\t08E12442C086404026040008066823801006216000000000000000000000FFB6470A0080001041203801801A018018218000\n\t01810010685601610411610441600694400600080080612461400600080001400104C2468000000068820040060060000000\n\t00000000000000FFEE5C120490001200005801821801801821800011800000600700680600600404700600600A200408007000874040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF1D8400000000100D801941DC381980199B800403800000600610E0260AE00C08E00E027106A0050A1473AE4061D71860\n\t604060465CE886458000806023248002006000000000000000000000FF091E00008402508180981000180180180380400180\n\t000060C601600605601413600640C00510801000600600600700110008600081610600000304680340000200E00000000000\n\t0000000000FF4059000308040301811849801801801801800401800000608708680600600602600610F10A00828002700221\n\t200E200006102020822C00C00000007002124807006000000000000000000000FFC25000001000000180180085580181180100474040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (208600E03601\n\t4A0600C0062284082A6006402506006000000000000000000004FF7763000010011801891801B01A01847C51801801800010\n\t604610E01640E00441641E08484200024400F00600681700000260891060080600020480E51620E086006000000000000000\n\t000004FF26DE000020020800D01801001801801801801805800000600680E006016406006046004000000000016024014807\n\t046C0600402610400600000000E004010006816000000000000000000000FF6470000008000809801E01A05801801E418018\n\t05800000780600602608600600600E0A401220000000622C00C806400006000000800C06000004006040094006006000000000c74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (838000107446\n\t00683700600041602E80480E008045286206C0711604005600450080C0262D8005D0E90408200201E0000000000000000000\n\t00FF3C6500004221080480180080182980DE95803801800000E026006086206002246006456421A0000080E84024C02F4162\n\t9612404E20520E04000010784F842012006000000000000000000004FF3952000030020801809800881901851941801C0380\n\t0000F00650680720620210622601614640000012604402C00701020600404809400620000C02620C00220200600000000000\n\t0000000004FF9464000000001E01801801801881E09881801A018000016207A0680600600410600610C8822004000C6007C200274040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000004FF\n\tB067000003801801821801801801811A15A09801800001604600600680600620600081240620000409080684600400001610\n\t400120000600C00500F044082006008000000000000000000000FFEF0B000041851835801C01801841805841A01C85810000\n\t6006806146A060168560403400C601080042042E2068C701650603482E03444E526C8010601680200E000000000000000000\n\t000000FFA02A0000002019A9801C0100181180190180DC01808000600600600600600800F01608409000000002698E016096\n\t40600600C006024006000280006006042002006000000000000000000000FFB303000000031A01821801C01C01801831801800a74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (50004E000148\n\t800206046004046016006006000000000000000000000004FF52D10000018018018018010018018018098019018000426006\n\t42640648610604610C00404644004C20602E00E0C604E0060CC0060000060060000062060020060000000000000000000000\n\t04FF939E00000180180180180180180180180180180180000060060060060060060060020020060000040000040040040000\n\t06004000006006004004004004002006000000000000000000000004FFC221000001801A0180180180180180180180180180\n\t000060068068060060068070020010060008000000000008060060060050060060060068040040070020060000000000000000674040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002A622626E1\n\tCE2AE0A62CE02C2A42A620842820C02E0468AF2860A882600F004006046000006006800006000000000000000000000000FF\n\tB5DA000201801801809C01001A01C01A01901801900008600700E006106406006006A0680E04000400600400400504000600\n\t0000006006004004806804004006800000000000000000000000FFAF390002018018C1A01829001801809A21889821800000\n\t640608700600600E0268868448060B000401600418C00600E10208C08600600660400482680C800006800000000000000000\n\t000000FFD234000001801B01801851001D51851941911851804009605611609605603650E02449651610000400700680601400e74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF84EF\n\t000001801841801A80801951C41801800001804081701600648700700602680401481E000000004006026005046006002047\n\t004400046000004406004806000000000000000000000000FF6ED60000018018018118008018018018019000018001086006\n\t0260260060060070060040060002008040020028060008068028000040000260000060060040060000000000000000000000\n\t00FF7DED000001801801901A00801801801801800401900000600680E8060874060068044060060400000048060060040400\n\t04007001000006006000004006800006000000000000000000000000FFC6B7000001801801D01900801801C018898000898000174040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4C9080060060\n\t0800200008E00601C0C6000000000000000000000000FF716F000431A25A81C918B592D8C9AC1C81A0A411800085710E8065\n\t168870B708ECD490D40E000800804800C2884C4208081488008A6800A2288088E80E824206200000000000000000000000FF\n\t2080020005801C2904580180180180182D880341800020600642E0060462062260040441260001002CC34510420600822420\n\t40C001608E10A00022624680C12E120000000000000000000000FF5C71000001801801001A01E01801A01801800001800000\n\t680600600680600780600400480600000080600180000680680000400600600780200000600600080600000000000000000000974040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200282208B00\n\t200200200208200200000000234210212A40000304200208209200A000002002040806010000000000000000000000FF4A89\n\t00010000182012400200010040000A001DA00001000000A000005A02A06010840244580000805240200404010260046A4027\n\t0004064C0000220628020238880000000000000000000000FFCC8A00000E0020080003142002204000600000000001000080\n\t009200000418088028400000000400298010008001206400000196578006230000000100100C000200000000000000000000\n\t00FF733A00002184180589982982188588198188A009800000E0060068060060061060040140860001000040840B400490E100574040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFBC3C0001\n\t21805805833815001881901801901A81800090640600600608640610600600600E00040081608E0AE406804426A0400604E0\n\t1640601000608650E00E010000000000000000000000FFC9CD000402D40D00D00900E00A14840D40C40C0080000030020022\n\t0240300B41382B51344200110950304340310A4830820A30CB303203153001A0B413042242820000000000000000000000FF\n\t9AD10000403043802422802824001002003400000000100C08000C01000800830250908A20000811000800E00A10000A2100\n\t0840000800100891410810C00800240000000000000000000000FF7BB1020001820800801C01808C1886080080080080002200d74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100100100080\n\t1001001211011020800000000000000000000000FF8F3B0008000A80880800000AA0AA0AA0AA0A80AA00002A8AA82A82002A\n\t81102A82A80001800000002A8A082002A8888280220088A282880000002A80802482102A8000000000000000000000FFAF5E\n\t000400A00800A30D10A00A00C00A00A04C00800080200280308300320280280281300200081080210288280200282A802802\n\t002802002801002C2A902802000000000000000000000000FFE2890000012022442032250010012014012000010000005004\n\t80482C804935004000B20C2C00080000084084900022480008CC40880840000800000800844954000000000000000000000000374040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800080000000\n\t0000000000100010100008081000010000B0000001100001000000000080010000000000000000000000000000FF01680000\n\t000880000AA12A2AA0AA0AA0AA0AA0AA00002A82A8AA82A82A82A02A8AA82002080000082A80084802A80A80103284A83202\n\tA80000002A80000802882A8000000000000000000000FF03030002003501522322841543543543543543540000550550550C\n\t28D50A20D50D50CD0A40000000D504C0C50D50350C00D50D50448D50000800D50C28C80B41550000000000000000000000FF\n\t917F000C0042040040040000040000040040040000000000000000000010090000011290C00010000010010510002010010000b74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A86900020121\n\t04004004412012002014002004010000804004804004804915000000808A0C000810000A8D088800224801128A4154482080\n\t48010051008C4800004000000000000000000000FFB569000000820808000814800800800800804800800000280200280200\n\t200200200234200200000000202202200280202A40200200A00200200000222200A132002000000000000000000000FFABE3\n\t0000000861F60AA0800AA0AA4AA0AA0A80AA00012A92A82A92A92A82202A8AA80000A00000002A85402002A90887C0000088\n\t0102890000002A81486402002A8000000000000000000000FFDC60000800004000100050200000000000000000000100100000774040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (63220222E000\n\t00A482468002116000000000000000000000FFA632400C010004004005804404004404000004020001001001001201021001\n\t509010031028001009021021001401230021208401040001401001001021001001000000000000000000000000FF9DCD4004\n\t04800C10400C00C80C82C00D00814C04800100B24300B0430230030134424430524410090432030030034224434020C32020\n\t1304B00100B4C3043013002000000000000000000000FF973400000180180402180180180180180188180180000060062863\n\t062060260260060064060884202860340B604608401600E006006406004040306006016006006000000000000000000000FF00f74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2602600E0040\n\t0408C00602000000400600008420600E08620E016040000000406080088406006000000000000000000000FFD01100080000\n\t0120024004008080004000040008004000040000014008800000000001000000000800020008000000623002000600030602\n\t02D0200048010120000080000000000000000000FFF04D000000001810000000100001040100003800000000000020012040\n\t002012404C00820031004050400814822009620000004600000E00402028020000000C000000000000000000000000FF4725\n\t000002800802020801820886810810888940800000A22208A00200200220220274201212020000224201240240000A012282000f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001801008\n\t000803801801801801000801800000600600600600600600635601600600000008604600E4864060060880460AE0260B0000\n\t0260A2008004006000000000000000000000FF627F0000018010000418018118518018058848018000006006106006116006\n\t00400422601608800000402650E20400000602200000609602048000621244004608E080000000000000000000FF25610008\n\t0180304000880D80382D81581308A80780C000640608600602600E0040060040060280101844062040840604460963884064\n\t280040500060C0080306066000000000000000000000FFEB400000018050800130118058818018018308A981000060060061008f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AF0B64002060\n\tA62042AD006000000000000000000000FFC62440000180100000180180180180180100100180000060060060060060060040\n\t0610400600030000429449200420001010200008E027006200006004084007006000000000000000000000FFB2020002AB8A\n\tA0862AB0898AB8AB8AB8AB0A90AB80002AE2AE2AE2AE2AE2AE2AC4040042AE00000000421C2840660883C422028830628860\n\t60000D66122742AC006000000000000000000000FF57FF200001800040001841801801801801005001800000600600600600\n\t60060040064A400600080025410404400C04602C002006006000802A00416008104006806000000000000000000000FFB4C4004f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E2AE2AE23423\n\t62AE00100422600E2242AC0C800020408820628E3210042AE2AE0062AC006000000000000000000004FF4F6C000A01800800\n\t40084180180180180180180180000060060060060060060060CE0AC00600080010600610420E006006106006006006004804\n\t086006105006006000000000000000000000FF883B0001559549545559539559559559559559558000556556556556556556\n\t5565464465560000044D6046020556110546256350226516448004556556234556006000000000000000000000FFF6A40000\n\tAB8AB0A80ABA8B8AB8AB8AB8AB0AB0AB80002AE2AE2AE2AE2AE2AE2AC0042042AE00000042C32424A0862AE2102284AE22E200cf4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018048000D08\n\t0180180180189182180180000060060060060060060C80A602C0060000820C80820C64CE0460D648444600600610C2060060\n\t160B62C4006000000000000000000000FF8622000001800800001A0580180180180180180180000060060060060060060001\n\t1611600600080408028210E00440048610C440026046888804006006106004806000000000000000000004FF2A2D00020180\n\t1800201821801801801801004801800000600600600600600600600600600600048001604600400602604C04400609600600\n\t0200006006456804006000000000000000000000FFE00A0004AB8AB8AA0AB0898AB8AB8AB8AB0A88AB80002AE2AE2AE2AE2A002f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620655602651\n\t4126550000000000000000000000FFB4D8800001021801881801801801801801811801800000600600600600600001600600\n\t4006000000008146006006206206056006006046026000006006006006000000000000000000000000FFC8390000AB8A9800\n\t0030AB8AB8AB8AB82308B8AB80002AE2AE2AE2AE2AE2AE00010C0842AE00000001022E20600648E34404C08E2AE28E220000\n\t2AE2862460042AE000000000000000000000FF27290000018018000018018018018018010018018000006006006006006006\n\t20040640600600040420000601600420000002400000604600000400604600600C006000000000000000000000FF4810000000af4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2262AE2AE2AE\n\t0000002202A45462AE0EE25620608E2AE2AE0060002AE2062262AE2A8000000000000000000000FF94260000018038018018\n\t01801800801823842801800000600600600600600000620613600600020440000E0160000000040860000060060060040063\n\t0E004416000000000000000000000004FF53380000AB88B8018258AB8AB8AA8AB8AB8A28AB80002AE2AE2AE2AE2AE2A82A62\n\tAE2AE2AE0004802A020E00E2AE08E0863064AE2AE28E28E2042AE32E32E2AE2A8000000000000000000004FF0BA9001155D5\n\t1801953955955955955911B11955800055655655655655655034E04E20455600010614054654635015040C20E55055653655006f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1881C0180180\n\t1C21801C01A00601800100608600632680700700602610700600000D000024016CC84304060060800260AE206004C0644604\n\t4006000000000000000000000000FF6C8B000800209801829801801801801801802001800080680600600600680608E00600\n\t600600000008801414E00620614E006247006006436004006016104006000000000000000000000000FF5FE4000001825801\n\t885801A01A01401C0185100180000060068060060060070070060040060003048000042060000008048D6000006006106404\n\t0060A6016007000000000000000000000004FF18AD0000AAC818018118AB8AB8AB8AB8ABC810AB80002AE2AE2AE2AE2AE2AE00ef4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (14E006006086\n\t040020000400000000000000FFB94C8000108019418018018018008018018008018000806806006487006504086006084884\n\t01010880820412E4460082174561000262C00060900A6406006006000000000000000000000000FF0CC58000016018218018\n\t01E01801C01801E01801800000F00792F80748E2B410780723600600840009000604600000100D2AE0204062060061000060\n\t0E207806000000000000000000000000FF84DF800001A01801801801C01A21C01C01C01C01800080E806E2E01F08E82D61F0\n\t0602E15E50036108050650700620680708662701E00600601134602E226007000000000000000000000000FF0D4B00041180001f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060460460100\n\t001004000464A028002405600000601040614800622E006004000240000000000000000000FF06B600000180188180180D80\n\t1805021881801021848010600E00600600600400600600608600000000020200600600000440600000650620600801620600\n\t6504000200000000000000000000FFC5B8000001C0180988982380980B801809A21003800008610618604640600600604640\n\t606658800000014242E1B60C602608608642609640602000602E00E204000000000000000000000000FFB246000301803801\n\tA45801801D00D13A01909A01820000600600600600680480600F024006000102100004106400406C9422E04620622800E082009f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000021\n\t8000000518000000000000000000000224000000400414000200000000000028246050000206000006000000000000400510\n\t000000000000000000000000FF0F7680002800000000000000011200000040200000000000000000000000900000001500C0\n\t000080000148000280006480000046000026000400000000108040000000000000000000000000FFE0D80001012058018D58\n\t41811D10011809D20801800000601600600600600400600E0041041000800000001160000064941061464460200160001260\n\t06016006020000000200000000000000FFEBF7000000C0191180181180180092590181084580800060061060060060040060005f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (565565568000\n\t00000000000000000000FF21F50000A8AAA8AA8AAAAA8AA8888AA8AAAA08AA80002AAAAA2AA2AA2AA0922AA2AA20A0220000\n\t008002222AA14208A02A2AA0AB2AA2CB2AA0002AA2AA082002000000000000000000000000FF379F08000200000000100000\n\t0012400000042400000100000100080080100000080000100000008000008000052800000000000000000000400100000000\n\t1000000000000000000000000000FFBBA0000006CAA8AA8AA8AB8AAC448AA8AAA848AA80002AA2AA2AA2AA2AA0022AA2AA04\n\t25020005000003022AA4120885022AA08A2AA28A2AA4002AA2AA422542000000000000000000000000FFDC8E00010000180000df4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000008000\n\t0008800028440000800000000041000000000000000000000000000000000000000000FF6EFC800040EAA8AA8AA8AA8AA880\n\t8AA8AA800CAA80012AA2AA2AA2AB2AB233AAB2AA2AB2AA0002000002222AA00208A2AA2AA08BAAA28A2AA001AAA2AA2AA2AA\n\t000000000000000000000000FFA5FB000C002000010012014014002010012104010001004805005005005421005004101010\n\t000000800010004000444000004400804000804001004004050811000000000000000000000000FFE624000289955D55D55D\n\t55F55F21D55D55C919558000557557557556556546D5655655655600020000044F5560063545575565565565575564005575003f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006002003002\n\t006000020000050200000000220000400000001800000000000200008100000020800010820100C000000004000004004000\n\t00000000000000000000FFE74F00000000022C20001000001000020000011000000000005000800000001008008400008004\n\t02028468691200000C40000100040240020002000800000040000000000000000000000000FFF2C108011200020000020040\n\t004A200000042000000080080000100100009000080000080000000000008000028000000000024000000000020000100000\n\t0000000000000000000000000000FF83FB00002000000020000000020000020031020000000000008000000010000000000000bf4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200200200000\n\t0000000000000000FF13E8000450001E09601801801801945941801A13800000610444600600600620740E00640740600252\n\t602E20628604541640735610690622C002457206006406C46000000000000000000000FF949E008000081041001001009021\n\t0090010000010000054C04004101C4400180400D2002800440E0214C0C11008000404C3288008406000040A1804004004004\n\t024000000000000000000000FF9BFA000248000800800800800C00C249208008108000002102222002002002002212002202\n\t24202050200280200204240AA8232210200280A000452002002002042000000000000000000000FF469F0000000000000000007f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000800006000000006000806000000000000000000000000000000000000000000FFF107000000000C00800810800808A008\n\t00800C88800000200280200200200200210200208200240200280A04A4022282220020020220020020020028060020260020\n\t00000000000000000000FFA3C700800000000140000000000020000000000000400101044808000000100C0840A500000401\n\t40040A000001400800084300A8000200000140000000000001020000000000000000000000FF93F600000010080480080081\n\t0840810800800800802000B88300200200300A03A0B200A40202200043A842DA22222AA00200202A00205A0020000030020000ff4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5821881C01B0\n\t0013800004600651680E00600440600680600C00E4B00060064800022004C6B460008C60210024A1006146106C2600600000\n\t0000000000000000FFE9C9000002005809801801801801809801800001800010602600620600600401640600444400600020\n\t602600004204600600642640E000042010006006046006006000000000000000000000FF2796000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000006000000006000006000000000000000000\n\t000000000000000000000000FF8ACB00000000000000000000000000000000100000000008040008000008040008008040040000c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000000000\n\t000000000000FF5EAD000000401800C01801843801811801801001800008600008600E00600400720602420C016348407007\n\tA460020060462044062140000022C0006006007006006000000000000000000000FF66CC008212005808C01945C818058A18\n\t3188504F800012601651602640600420F0060460240060004060A64400260268060B60260360068321082060AE2860060060\n\t00000000000000000000FF83AD0002000038008838018018218418418010018000006626A0E2460060040060060460048060\n\t00006F1E8C0002200A860060180861A601A000406016426226006000000000000000000000FFEBA4010000401801905801920080c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8400E0060142\n\t440001060064000068060A000404608600610788E000000000000000000000FFB37C018010485907C03945C4B86980781181\n\t141D80600069914071048060441060269C6004CAE02082E1275862363E605E5600464040660A60000260C610600608E00000\n\t0000000000000000FFC77300010000184181380180B901E0180182104180000D600001600520600402610700628508E04134\n\t684E046086408206010000030806216080806006006006006000000000000000000000FFD988000082001920809C09E41881\n\t881E43850001800003744000688600603612608600448EA0628008709600E08A0104A62844204240002020018060470860860040c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801A01801801\n\t8000906047A07807806004007A16006144027808086C26806C0484688620480610000E002004236006006006046000000000\n\t000000000004FFC2D0000020001819019801A01841821A0181182580000160271461060060048661460040A4006504016006\n\tA0627C0206260010A801800680206400E1B6026066026000000000000000000004FF31E1000042003801001A05801801821A\n\t09C00821800000640700620600604600600740600600600400610650400000602708E2CF0060060402000060468260060060\n\t00000000000000000000FFEF39000004301801201809801813881845802A018000006446906806006016006026006016046400c0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF2C77000000001881829805C01841C09811C01801880010622608E8060060810060872048A100640438696620E8\n\tA6200006DA022192100780400440E007207007026000000000000000000000FF6F7B000000003E4180581184584994594592\n\t0E21800045600E00600650602200600602621290640C00E816144802016B3600600608E00610600F40608E00600609600000\n\t0000000000000004FF79A4000002403801801C01805801C01801C0880580010164065264860060220062B6A0680202610C01\n\t6206104003000086016A0100681604420502600E807007006000000000000000000004FF26B1000000201801601A01805E010020c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600300400680\n\t6806004006804006006804006001004004806000000000000000000004FF8080200001A03800001805801809841800841825\n\t800040600682600600600280608680720608000680685608E846000107046800124026006004006000004000056000000000\n\t000000000000FF5B0F200001A0184004D81184380190D94190180188010D64061060063060C0800806C2404E02044C516006\n\tC26306A0E80E10E446414007086808236110804004906000000000000000000000FF6A5A000000001D01801803801841C018\n\t1D801803800108605403600600600000600600490003E02100600600620600644600C186204026006000026006406006006000a0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4D9458459001\n\t5460CE0B691614E103090512046D0402600401704D5160448000460224009050060060040470010060060060000000000000\n\t00000004FF804B00000000181000180180180180190180180180400064060064460060242000422060240062342862040060\n\t0032E10208A006024006046004206000004004006000000000000000000004FF529800000180180000180180180180180080\n\t1801800000600600600600600600600600600600000400600600400600000600400000400600600400600000400000600000\n\t0000000000000004FF712C000001801C00001801801801C018018018018000006006006806006006002806006006000004000060c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF400C000000801C000018118018018018098C1821882100629E0AE16629F4202AE02F2A520602D23804F2AE0AE02684\n\t60A40A6A0F080846076008024010004004046000000000000000000000FFE4A2000001001800209801811801811801D05881\n\t814000630600620600610E00A10F0060048072A480612C4CC00491000604081044680608600402400088E006006000000000\n\t000000000000FF177F00000120184A281821881801C2B8238038018000026826006286426884042284104004816004886104\n\t044004006006008816006006006014006000004004006000000000000000000000FF629C000000001C04101841905801855800e0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800002006000\n\t004006000006006002004000004004006000000000000000000000FFD3150000010018400018018058018019008418058000\n\t50620E006897006A0280E00600694480400042682C40E00455680680280604280002E00140400800E0020060000000000000\n\t00000000FF88AC00000100180060180180180180180090180180000060860070260070020000060060050040280071008060\n\t00021003002001400000086001004000006002026000000000000000000000FF7318000000801800011809809801A09801A4\n\t590180A0007006006C0600E109807116005006004500006006D46006088004046008022026006000024800104005006000000010c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (980180000460\n\t0C00640608600010810000414421C0408160040180940065042200464061008A600002400800602E12600000000000000000\n\t0000FFA4AC000241281908501C8980B889D03A2BC21B218000346D0D1074172D6D048C0822C0CAA4CB4800006A088208800B\n\t0940A10840CD680028682080C108806A06086000000000000000000000FFAC24020080C2182402180180180381188190B80B\n\t800001780642E106006040216A0E02601600443203608609002680000C0C409080210E04E0100242003560AE836000000000\n\t000000000000FFA38100000080180000180180180180180180180180000060060060068060040060060060060060020060020090c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF8147000000A80800000808A0880A80088885080080008220020022020021C220240200A08202202000A14210200280802A\n\t40A102102002302000040080322012402000000000000000000000FF5C6B0000004004822800402104001080010802280000\n\t2080C0E080C06000208A121C520209004208000000080040C9600409048E0504860080084000010800000080000000000000\n\t00000000FFD4D600000000000402000020260000000010040000008000000900000280000000000400201804100200004600\n\t209460901000062A8006400020000000448301800000000000000000000000FF98FB0000A1001800001981801811801901820050c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (10405000890C\n\t208B0800814902004000800001004000000000000000000000FF998B00002100180200182181180190180181180180000064\n\t262162260060C600600620610601641080E8A60AE14600C00654610610610652604082601040609650600000000000000000\n\t0000FF4C2E000400A00820500D00800A10C00D12D40840800044300300300340320BAA3B13143423503021003003203012D4\n\t334B00B423453403003011402C010A3802002000000000000000000000FF4B7F0200410200681004000000802822362020C2\n\t0000C80E00020808800E10440020A00C00400800800A8880090002084084082080080884085100961000088088000000000000d0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000100100000\n\t1001001001000001801001001201001001009048C21001101021041000101401001000001001000000000000000000000000\n\tFF03190008000AA08C0AA0AA0AA0AA0AA0AA0A80AA00002A80002A82002A84802A82A80800002A80002A82A8B002300A82A8\n\t2000C82002A80200002A82A82A8AA82A8000000000000000000000FF7980000000A00A42400C00800800C00C00C00A008001\n\t0028B2803103002A02802802002C0280280080280202A802003002842802802802B028008028010020028020000000000000\n\t00000000FF9E030000010012002012012010014014002032010001004C0080482D004850000000C30948800C0200400090090030c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF52\n\t9500080000000000000020040000000000020000000002D00000000000880000005200400002000000000000008200000080\n\t01028000208000000000001001000000000000000000000000FFA1FA0000000AA0D24AA0AA2AA2AA4AA0AA0202AA00002A82\n\t30AA82A82A83202A82A82A82282A80002A82A82A04008882A84104883002A82080002A82A92A82A82A800000000000000000\n\t0000FF59C00000003543303543541541543543543541540000D50800D50D30D50840D51550809490D50800D50D50C28CC051\n\t0D50D40D10500D30920900D50D50D50550550000000000000000000000FFFBCD00080000040000000020020000040000000000b0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400620640E48\n\t400601600000E106026006006000000000000000000000FF84E000000000022520120120100120120124B201000100480080\n\t100500491080080480508C800802800800894A40404804008820C0C840810802800800004804004000000000000000000000\n\tFFA0D70000000008108008008008008008008808008000002092002002002002002002002002002200002002002002022002\n\tB02402102002122000002002802002802000000000000000000000FF5DA20000006AA0800AA4AA0AA2AA0AA0AA5140AA0000\n\t2A83202A82A82A82302A92A82A83202A80002A82A82201888882A80600880302892402002A82A82A82A82A800000000000000070c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02202211200A\n\t28200212240248208200242801259204060214800210250204221200A000082012082002002000110000000000000000FF3E\n\t68400C0040040440040040048040040040040002010016010210010000090011890090210290810092711480292010611800\n\t61004001000001001001001105000000000000000000000000FFA1F3400400400C00C00C00C00D00C00C88C08C0082010030\n\t0310300B28241342305344B1235530C100B00320A40342340B00200300A40314280110301310300300200000000000000000\n\t0000FFB3EB00000004180102182180180580180180180180801460260364060260A611640608600E00621004630600602E0100f0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF499600\n\t0000001801115831821811801821815821880013600640E00600608400402610620E00C30000000000441210612600640620\n\t0090003040020014006006026000000000000000000000FF65090008001000220000001480080040400000C000000A804024\n\t04080880080080400000082300000000000880000160402280260001060000200101002001104400A0000000000000000000\n\tFF093200000000000200000000000200000000000001001000001082000205444942202400105044000200084C0000046210\n\t40040E514006120000008110020080000000000000000000000000FF87AA00000002080182086080080080088880C80480000008c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (012006422000\n\t0008000200060C6286006000000000000000000000FF62C4000014001000001801801801801801801801800000608E002006\n\t00630E4064262C60861040000020C00460124061260A042608804600600030A000206026006000000000000000000000FFC2\n\t1F00000008104402180180B801829801881809800000602600211615600600620621600604400000A2881460020200062020\n\t40020406006000000004216116006140088000000000000000FFBAB20008000018010AB80990380182D80188990D88000060\n\t0614648602609611618608E20640408000000001400A0106861561182042000000181B210418E006586000000000000000000088c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B62AC2AE2AE0\n\tAE00602E0AE2860840002AE22622624648E32620808E20628E2AE00040E0022360462AE000000000000000000000FFCC2040\n\t0000001A0080180180180180180980180180000068060040060062362B40260060060040000062260060160400AE00240088\n\tE006006000006002006CA6006000000000000000000000FF99B80002800AB8018AB8AB8AB8AB8AB8AB8AB8AB80002AE2042A\n\tC2AE2AE4044FE5860062764660022AC2062062860A82163004880062C82A800210000600E40E2AE000000000000000000000\n\tFFD485200040001801801801801801801801801801800000604400400600604400401601600E20C80000401608E04200600E0048c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF1C890000D0\n\t0AB8008AB8AB8AB8AB8AB8058AB8AB80002AE2AE2AA2AE2AE0040062062AE2AE2250002AC2062242280880A63240C820028E\n\t2AB0042AE0062AEA262AE000000000000000000004FF0CBB000804001A010018018018018018018018018000006006002006\n\t006006104006206006016800004114094090046006046026154006002800027000107096006000000000000000000000FF17\n\t60000504155C011559559559559558A19559558000556D5655255655610400649655655654E0045541145543245104064361\n\t10C2055655240455600455700E556000000000000000000000FF9BE00000A80AB8008AB8AB8AB8AB8AB8AB8AB8AB80002AE200c8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001080262C60\n\t0430E002006006006000000000000000000000FF4A7800000004182500180180180180180180180180000060060960060063\n\t140140060060060820400A60040201160060060040060040060160840260A8006006006000000000000000000004FF3D0000\n\t0004001C01001801801801801809801801800000600600600600651402E0C600600610300000601409010624000E00402000\n\t0046006A04006000006086006000000000000000000004FF85AF000028001800801801801801801923801801800000600600\n\t200600602628601600600600C0000041260040000064060942060D000600200400680200600E0060000000000000000000040028c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (65565562062D\n\t655655455014810444E4A4506546110556414510544516242104104402556554556000000000000000000000FF318B800000\n\t001801801801801801801800801801800000600410600600600400600600400001000010610C00E21604600600440600C006\n\t0C200200600E006004006000000000000000000000FF9DC10000000858818AB8AB8AB8AB8AB8AB8AB8AB80002AE28E2262AE\n\t2AE0040042AE2AE2AE00000020622E20823608E2AE0A40EE22028E0160000063122AE2AE2AE000000000000000000000FF9B\n\t1400000000B811801801801801801801801801800000604600600600602434600600600624830400E086100006220006414400a8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (DE0000000AB8\n\t968AB8AB8AB8AB8AB8AB8AB8AB80002AE2AC2462AE2AE2AE2AE2AE2AE2AC22601023422022610808E2AC30428E78428E2100\n\t043861062AC2AC2AE000000000000000000004FF09BA000000001809001801801801801800801801800000609600E0060060\n\tB600600600600020042008600C04C0062400060A400001404608000422C042004004006000000000000000000004FF6D6F00\n\t00000AB8C10AB8AB8AB8AB8AB8AA8AB8AB80002AE2AC20E2AE2AE2AE2AE2AE2AE2AE3202802262242A402628E2AE24C0AE04\n\t42AE2002042364262AC2AC2AE000000000000000000004FF9B790010001299459559559559559559541559558000556446540068c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (061600241900\n\t7087006805006000000000000000000000FFBF41000000401801421E03A01C01881801803C01802100600508728700600600\n\t7806806225026044814000044254409304400200026026206004904046806007806000000000000000000000FFA6E2000800\n\t001801001801801A01801801801801800000600480E00600600400600600600408628A114108104020026804034046046006\n\t14C402004316004006006000000000000000000000FFC6AF000000201848A01801801801A01A01C01C018001006804146006\n\t80700680600600480500E00000500000E28040000408000001404600000402F046004804006000000000000000000004FFCE00e8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006006406\n\t0044011042210B40260CE0022462C40B20561220800060401460420042A2A06210000000000000000000FF5E838000000018\n\t01801803801A0180180180380181208060C680642681640E03740650C22640C0201140260B64560088844520000000102021\n\t00086042004000006000000000000000000000FFA871800000001800801801E01801E01E01E01801808000602600E00602E0\n\t2430E20624C006204001486406306086000006026130002007806080006086006006006000000000000000000000FF801580\n\t0000401800C21C01C01A01A81C01A01C018001007104C0E047626C372471E7105016814019206A4601600626681E0160AE400018c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800180110\n\tB8018018819118C5801901830000E00610600620600204600650650401408020010604000210004400010000600000401000\n\tA024200002006000000000000000000000FFDB570000000018000439058018C5801803801811828000662404610600600600\n\t60060840044440C0002086000182000006144000042106004000002004202006016400000000000000000000FF0BB2000008\n\t00180002980380382388988182982980000060045A610620600612400624609426E008202006400102086406004486440266\n\t02040800A0840A200400E000000000000000000000FF2F0E000000201809B01C81801801841841883B01800000E0060068960098c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04000040211A\n\t0000022AA000000000000000000000FF3E7D00000000004000000000000000000200000000000004000000000000884B4000\n\t10049420C000008200148000446010004046220026200080200500228480000000000000000000000000FFB0F38000000000\n\t1400000000000000012000000000000001300000000002400000004480200A01200201280001100061001084060800060B00\n\t00130020080050000000000000000000000000FFBED900000000181100180180380184180194B841800000602600600E0060\n\t000042060040040842100A802408800222628401004E1064400260200C21061464C6206008000000000000000000FF53DA000058c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (565565565578\n\t0444E0904C654E55605653455640C15652E55640620044624E486956556000000000000000000000FF9F850000000AA8828A\n\tA8AA8AA8AA8AA8808AAAAA8000AAA0822AB2AAAAB2022822AA28A4420220803225223023222AB28A2A22AA08228A10A00002\n\t202200A3232AA000000000000000000000FFA4C0100000000029200200000400400400200000000000000000000000000100\n\t10008005488804000080000000800000000A0201000000110000090100848200000000000000000000000000FF9763000000\n\t0AA8C08AA8AA8AA8AA8AA8588AA8AA80002AA0522AA2AA2AA1420022AA00201250224028201224222208826222208A00A28A00d8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000A000000\n\t0000002000000002000000000000000000000130000000000410008000000008000210000001000200010000020200000508\n\t000020000000000000000000000000FF2BFA8800000AA8808AA8AAEAAEAA8AA8888AA8AA80002AA2AA2ABAAA2AA203AABAAA\n\t2AA08322200022A2222224020AA2AB00208A22228A0CA00022200200A003AAA000000000000000000000FFD5580008000010\n\t1120120140140140140240120100008044000048048050090510048410850104000100000100080048000140014300402041\n\t000884012A5009004000000000000000000000FF086E000000555903555D55B55955D55955D55D55800155655755655755650038c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000A2B4A00A0\n\t02002002000000000000000000FFB9350000000000000000000000000000000000000000800000000080000090010C008000\n\t00000002020020800008000888020000220400900002000800080000000000000000000000000000FF742B00000040000400\n\t200010000010000400400000000001000000100000000000000005000000004100002C840051000050001004044040000100\n\t0040000000000000000000000000000000FFAC7C000000400020400400000000000024400000000080000080000100000000\n\t00000010210805101001000900C02000002C8020100020400000090040540488000000000000000000000000FF22BE00000000b8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (30020E3D1A24\n\t234058342A4DA0400020820032F24025D3002280003002002002002002000000000000000000FFE559004045805901805841\n\t815004115941911901804024600604E10640615645625688C146004000046006057010114096D54507214206104000146554\n\t916006006006000000000000000000FF9E330200000002080080010010002030000080010000804004005800004404004000\n\tA048200A44A8000240700820004000005800244008004001800004088004000000000000000000000000FF48400020448048\n\t808008208128021128C0908880802044200205200240222224302A11212200220000200282200010A80251228301200280200078c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010014002010\n\t0020000100100000008000000000040010008000000040000040000040040000008068000040068040068000000000008000\n\t00000000000000000000000000FF1772000000A00802800800880A0008080280280080000020020020020020020020020828\n\t0250220000204A002000288082D06802026002002280802002002002002002000000000000000000FFFACA04000000001001\n\t0000000200000000000000110050008044010040091080100140004000000800900010020080080000028080000020000000\n\t1020110000000000000000000000000000FF9824000000800A00800C00C00800604800810800888128200222209220208A0000f8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (280310002600\n\t6004000000000000000000FF1858000001001001801101801800151801800001800002640E88E10600615600600620600600\n\t44480840844064800A081613420010C30001002010210200014680E006000000000000000000FFDFCE088021001001081001\n\t801800001809820001800008608600600E4060064060061000A62140000040240040000060060000C640001000001000202A\n\t002406006006000000000000000000FF27960000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000006000000006000006000000000000000000000000000000000000000000FFD2FD00000100100004c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (140080020040\n\t00C84404E08048020C02700040649020A001006482806006816004000000000000000000FF2B550000000000012000018018\n\t00421801840401800000600600E00620624602708420110009004800C00400612000680480A0264922A10020200060028062\n\t86016004000000000000000000FFFB5E0880210010058810818110040958598044D580009D63868D600E006086A072260160\n\t3621410010413420221081610E8808C691084E1000080828EA480146006004000000000000000000FFB33300000100100100\n\t1001801000209801200101800082600E00608600640E8465460808061042000948840060408A0006820A00800846808002000084c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0811B0092000\n\t18008018018A2042680640E0000060060060040420C08C4206007A0020C94000040E00800010040604200600440811200780\n\tD006000000000000000000FF29AC0000010210059A7007893094235853824191800110706F24601600701E40608411602129\n\t03003043042060308161003CEA0680601653200018710F08E206026004000000000000000000FF8EC8000001001001A21001\n\tA03000041883820045800000E10E00600610600600612400600840602040E02C026801300800C064214178C6002000807026\n\t4064C6047004000000000000000000FFE3FB0000000000010000118018304019018000018A2140600700600F0870072060450044c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002016004006\n\t000000000000000004FF5FD6000001801800801A01800A00609882883E03800000780600600080604EC06004012010004000\n\t004046800040406804000A2E000216006400016003806006106006000000000000000004FFFA410000098418608218418008\n\t4202583288184180006061868C60000061062261A4102008D845C04071200814800082181B008051810EBB620638E0C20862\n\t16086006000000000000000004FF624E020008800808840801800802021820C0180180000060060860008064068A60248021\n\t4000400002420610408000F406024086004006422010404500082506004006000000000000000000FF93A70000008408008000c4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0E0064000008\n\t0800400804601400033E400806016000087007006006047606000000000000000000FF9DF40000018098138A1889C0804000\n\t180082B803800120608708600008600E1060070320870AE4A404200080000042080000808088800789600400C08408610602\n\t4006000000000000000000FFE46B000000800851010841882A2810584CE018818480096206016000C460260C629600380640\n\t6200120D46024141C1620F8A4807A2489622E000007806012006006006000000000000000004FF1850020000840801000C41\n\tA0080001591080582580008060060460000065370060070820A620002040228680442000100601025048028600600E0044240024c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A00001200000\n\t0018018000006006006000806806806806804806006800802801006002806006800006004806806000007000006004006004\n\t000000000000000004FFC6B300000180184980184180500100104C0208438100012D060060000C40260460160440040D0004\n\t080106006906209006016200804006204004116082892000006000000000000000000000FFD1B20000018119018519098090\n\t48114000010809840012284608E000C00804906B0690480C20092082025604602E8064068C60460D488E1260000060020060\n\t04007004000000000000000000FFDC1E000001801885901C01D008004098008059298000426026006000006016006006082100a4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060000000\n\t00000000000000FF681E000001801840001911C15C51805854002D518280850326086500516055406526004C040244084048\n\t508164840008460060A0004A07026006146010846004006006000000000000000004FFA5A700000180180000180180180082\n\t180000080180404000164260400064041360064040B408C0400343000860442D600604600600604600600000600000600400\n\t6004000000000000000004FFCEC0000001801801801801800001001000001801800000600600600000200600600600400600\n\t0000002006006002000006000000004006004004006000002000006000000000000000000004FFAF63000001801801801C010064c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600840401205\n\t6006080016006200156806046000007806046006046004000000000000000000FF0489000001801800001801801801800821\n\t84040D8AA060322E2B652708E2002A606662F2AE62E43828420A10E20600602E4868AF406227826000006003506004006004\n\t000000000000000000FF6B14000001801880001C01A00A01801800000901A24080B04634604100443650600E934154004084\n\t48681685600410080E00040114C00604C004806006022096026002000000000000000000FF82E00000058018200018898088\n\t01820A022028A1B000002006006000004006006286854004C8400010600008600028601612001600600600400082680C002000e4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008008018000\n\t0180000020078060060060040060060060060040008040028068060060060000060020060060008060008040048060040000\n\t00000000000000FF2B29000005801800001801804851A05811800201800005610620450740605601680E0210068004000541\n\t4708614285600600680700000100E0009068062C6083006006000000000000000000FFFF86000001801800001E01A00E0180\n\t0801E0040180002060460064060060158870062000CF20628010600000600300000720600120000000600000600280601000\n\t6006000000000000000000FF0599000001801900001A01801801C01801820083842000E00612C0A7007422C0604708F004000014c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008000000000\n\t0000000000FF854A000161867800001801841835A0188180020180000060062042860062081262060203044040002240B600\n\t6582016006200006210608406000006806006006006006000000000000000000FF1B76000285A83AA0229901A8CAA1922A81\n\tA540958000843096B04A8680EA4028688E81690702C80884CC88C0E83200102ECB0820A0AA00C068002A630CC04C462B68C6\n\t000000000000000000FFA79D000021821800001849821801809C01C00001800051640602600E04680C046406B2024D004000\n\tB040220A6A824A03068000880C000E02600000604405411600600E000000000000000000FFB788000001801800001801A0180094c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (910E00820249\n\t480A201C090010C800860800884800E0042890C840000000000000000000FFA60500008080080080080082088080A800818C\n\t00800042200202200A04241280200228208204200044200304A0030000020220020200020020010620800422428021220000\n\t00000000000000FFA22F0000038018259098280100010000018018800000280280000116D350000D048940406002440008C0\n\t4C4800202260C080849F0400063000021006381388902B0408000000000000000000FFC05E0000000000000146900820005E\n\t40100620400000010408090000000140A01101000408008008000100200010906408400067080006000000E10100000000840054c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (130420200100\n\t00000004800800800000004804804811404820AA0900D54000004814000A00904800908800C248C4880000CD488000000000\n\t0000000000FF348D000101805841811A01841801805001911A018000A16C0600610E0AE28604E10624440642420000653604\n\t6006104406C0604E12600620600014608604E00600E226000000000000000000FF69B1000420D20D02D42848F08C148A0D08\n\tC20820800100300310B00340382A9024020831331030012B30022034B2A130430A350200B20314300040B40B503A320A3082\n\t000000000000000000FFC4CE0002003803C026044030800020030030040A000100880110080000802100080014881090080000d4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF87D30004104104204504004044004004044000000000801000001001801801001001101801101001010841001001\n\t841101281001001001101001001101101800001000000000000000000000FF2AE40000A80A80100A80AA1400000AA1340A80\n\tAA00002A8AA82A82A02A82A82A82308A02200800001000080000006A82202280A83202E82200000000002002A80102080000\n\t00000000000000FFAC4E000200A04C08A00A00A10A00A00C08C00A00800000200280280A00200280290A40A10283280080A2\n\t2280280200288290280280A802802800912C0A852002802842000000000000000000FF12E50002022002C4202001142000400034c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (081000000880\n\t380000880402882100003B02682002A8AA82A8000000000000000000FFC22500000400012000000001000000004000040000\n\t010000010000110010000010002488800480010004100C80010000A001000100800000800022080028800042104000000000\n\t0000000000FFB29F0000A20A20880820AA0A80000AA0A80AA4AA00002A82A82A82B02A82A82A82A80402A824000822149025\n\t00002882400282A83082A82200002202102482A8AA82A8000000000000000000FF90A3000350352204354354204200354200\n\t3541540000550D50550D40550550D504C1080450C80840449120C00800130C10D40B30440D10D4080089052884155090050800b4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (803801850000\n\tE00E01600642602E0060060840442060000A608404600640E50600E22E00401608E000206006006006006006000000000000\n\t000000FFFDFA00023422C2032102002002004002012030010000005004004800804804800804804814C00800884104810800\n\tC04400CA0C20AC48008048008110048A5004000804000000000000000000FF70FE000000800820824800800800800804800A\n\t00800000200200200A00200200200240A10203201000A2222A200204290200A00200A04214A0000021020120020020020000\n\t00000000000000FF73ED00008008008C0800AA0AA0000AA0A80A80AA0001AA82A9AA82A02A82A82A82A84B022009000032080074c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFE243000000800800002880800800800800020000808002208A00218220201206202210200202250044A5220020426000\n\t6200208250620200000050201A088492002002010000000000000000FFBF7000000000040000C40040000040040040040000\n\t2100110110840900910108128906110D1080A120104100066100100170810108000100000100150106101108100000000000\n\t0000000000FF78B5000000800C00800D00C00800C00C00C40C00802104300340210B0134030A34D320B21304A94941300340\n\t2003003053042003142403002811043013093103483002000000000000000000FF548100000580190182984184180180180100f4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000244805400\n\t82A813403810100000E08600044660E006000000000000000000FF61F5000001001008021020009810001921810003800000\n\tE0060860CE00600600405600400200502008600200010209600409021602000400500012E08E000016016006000000000000\n\t000000FFA38000000000002804002002A0220900080800040000008300000010050100488028020200080000000000008080\n\t0C62085200060080061202A00400002880C0000020000000000000000000FF7E6E0000038018818218210210010000018038\n\t0002000100004802060204D00000005144C05000080C008022400001629012022E02400E0880084203000000104040000000000cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018000046006\n\t40600E00640600600600800420480020E00400200240600600E0060C20041048008020964140070064060000000000000000\n\t00FF83BF000001001002001000043804005801802001800008E0060B600600E0260060062242A60AE0000A64CE0000960260\n\t0602020621004601000000422610030600414E000000000000000000FFB27800000100100000100000584410B81180200180\n\t0000621600600605610E336006284006286C00226206008022000206220140200022020CC020600630810600604600800000\n\t0000000000FF9F020000010010400010001C18080030A190A019800000610E08602600600600418624440220512008610200008cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t1C7C0000AB0AB0880AB0AB88988B8898A98AA0AB80002262AE2262B620E1162AE2AE04008640C00040650C2AC22E28E2AEA0\n\t608F14628E1440002AC4360042862AC086000000000000000000FF8EB8000001001002001001881901801801800001800000\n\t600600601608600600600604E0064240100065040044C240000602600189600200400000000610C0AE004086000000000000\n\t000000FFB0D00000AA0AA08C0AA0AB8898C98C90A98A80AB80002062AE1062A62A608E2AC2AE09080C0440600460042AA326\n\t0882AE3C64A84162C86240002AE10616406E2AE056000000000000000000FF84CD0000000000200000018018418210058000004cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (44600680E406\n\t1480060060000044A640602E004416000000000000000000FFB4090000AB8AB8C80AB8AB8898818008A80818AB80000062AE\n\t2AE2A00062062AC2AE4842AC0070043260002AE0A20882AE206088A0028A2AF0042AE0460060872AE0860000000000000000\n\t04FFB4B200000080082000080184580180400400180180000960060160001464260040063044301068000960400040040460\n\t0601002600400600C800004006414016804406000000000000000000FFDCA200015495491015495584D83593415215595580\n\t004D65565565404564D6554556084D5009600444E03055400C1505564885504405325540055562962444065562360000000000ccc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060060060\n\t080060064860061560320140040061020060124000060562000880021060044C4006036006414006000000000000000000FF\n\t500C00000080480180084180402180D000005801800000600600600000600605400600608010600000600E04A08604614E08\n\t00460040060260000100060060060A4006000000000000000004FF50AF00000080080380080182402B815000055801800022\n\t600600600052E0A60060062200000AE8140064CE0022100000061200200000220068040000160B6207004026000000000000\n\t000004FF185E0000018018200018018018018C0804001801800009600600600800601600400600C00420600008E000006004002cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004FF3A9E\n\t000551D51B15D51951914111815B503559558000556556556D4055255600655212251241600455244E416112350414454110\n\t4C453052E00443655640C5560D6556000000000000000000FFCD260000098018218518018010018438020018018000006006\n\t00600200200400400204A0280060000000160060060040040040060040040460000CE0061040060060060000000000000000\n\t00FFB5830000AD8AD8C98AB88B88808B8818AC0A98AB80002AE2AE2AE2A02AE2AE0042AE2162022640002AE22228622608E2\n\t0630608E2202AE20E0001042AE2862AE0042AE000000000000000000FFA4580000038018258018018400018218020018018000acc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008560404060\n\t4408600404E006116006006004000000000000000004FF235D0004A1CE188828188B8C988E8898A84A98AB80002AE2AE2AEA\n\tA02AE2AE2AC2AA0063042AC0002AC22420600408C2AC20408E0C408C6160000862AE2242AE2AE2AC000000000000000004FF\n\t2A0C000001801A018058058210438C180000080180000060060060120060064CE0062060220840040020801422400000A400\n\t444000C0000060040060060A4006406006000000000000000004FF427A0000C388B88B8838AC88B0C9889AA80AB8AB80002A\n\tE2AE2AE2B22AE2AE2AE2AE2862002AC0002A82C62AA2CE4AC2AC2AC2AE3142AC1060004062AE22C2AE2AE2AE000000000000006cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F04710F004D6\n\t48476AC636C22544C061C091500020470420C047060496800714406000046006090916206006000000000000000000FF0E1E\n\t000401C01C00409C00821800801C00001C01800000700680700200628704700308600600400500701402C02400C210206020\n\tB0600400600528648E102407406004000000000000000000FFDDED000011809800005840C058208018002058018001006006\n\t006002006804006002C0601480400000400410C23400400410440605420402E0004060060010060060040000000000000000\n\t00FF0616000405C05C24231C01841801C43C02001C01800000680600680B0020070040021560A600400480690C046100444000ecc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF87930004\n\t01C01C20281A00801881805CA182404180200271061068060001268068270021140062008149501085000144023024062422\n\t14000029000486102446C06000000000040000000000FF037A000081803880011800801C0180180181020180000060060062\n\t063100AE0041161024D4006020034108000104104B2A0024002020140000002C0486012416006004000000000000000000FF\n\tA3DA000001801800003801805C21801801E03003822000E00600E40580C0141160A204200F88E000046087C040022A508600\n\t0080000024046000006006020026006002000000000000000000FF2E8B000501C05D00401C61C23821C11C01A12401982080001cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620600611400\n\t0050080096002226406200000000020000000000FFA75E000401C01C48641800083900003801D00009904000600642601601\n\t600650C00600200440E4A000401448005030C04800E0884C600420A100002206302016016000080000000000000000FF1CF9\n\t000401C01808001901063800011A41800009880001610602610404E10628400208600400C000004004012008084004102008\n\t00244400808009800E00200E00621C080000000000000000FFE0FB000001801C8002D8AB08180001980BC88007840020E046\n\t3068AC02640600C00E4060047140A010420425206424402C4080D61801E464200000201624014600E0040000000000000000009cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AA882222022\n\t4022AA10200A22200000A0122426622AA23220A08A0222AA40200014A2AA4022AA2AE210000000000000000000FF426A0004\n\t01C01825A01801C4180180000380180000000000000000061104000540040484441100000444040040800040040804460080\n\t042C80004A0000400000000080000000000000000000FF395200000000000000004000422000060000400000000000000012\n\t280001104800005001000000004800A8128008006088020006500006000000000000130000000050000000000000000000FF\n\tE84A000201A01B00291C52401C00001C93A2C045800024600610702600204400404A10009400600000C4A400048000420020005cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (7C06000555D5\n\t5D15D55E0BC4584D955D519219558001556557D57546A0655755712645644E556001C4704551651615644440E1164D615655\n\t6000547556415556D56406000000000000000000FF45990000AA8AA88A8AA8AC88A8C88AA8A8AAAAAA80002AAAAA2AA22A2A\n\tA2CA10AAAA04242234A00022232228A0022AA22241228A4822AA0420002022AA0A22AA2AA2C2000000000000000000FFAC7C\n\t00040040040020004040848000040001200000008000000008101290000002108800800000000803088000404001080A0200\n\t8002000000000090000C08000008A8000000000000000000FF9B820000AA8AAC888AAA8A8C888E8AA8A8CA88AA80002AA2AA00dcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030200100000\n\t100000051000000440000000000000000000FF89230000000000240002080540100000021000000000800000000008400000\n\t800540020000000002000000000100001000010400000000030002028800000001000088000000000000000000FFB6BE0000\n\tAA8AA8C88AA920900C80EAA8ACE00EAA80002AB2AA2AA2A20022AA2AA00220322A2AA0002BA0022420020AB0022A20CA2820\n\tAA2020002022AA2822AB2AA002000000000000000000FFC02600040040042040040040020000140220020100010048050051\n\t0080100004080120809000000108800500009000008412004083000008800000900400D005005004000000000000000000FF003cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0200209300A0\n\t0A20301344200000200202A00200294300200282240A44220000210302280B002200000000000000000000FFAA3400000000\n\t00000000000000000000000002000000000A004001088000008208000088808802120000208000002008009004000800C000\n\t80024A0800D00400880020000000000000000000FF027A010000000000000000000000000010000040000000080081080000\n\t0000000840001400110100000401B80800000040008070040801800000000810000000000000000000000000000000FF6996\n\t00040040040020010250042200040005200000000008010008000B00000010080911000000010012A89284284004A800004000bcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010000000800\n\t800C00800800C0080282CC40800102200226200B202082002202C9200B40220808204A55A1820030020021D380A502002000\n\t003012003603002000000000000000000000FF443A000000001801901801801951941F558418018020416407545916006116\n\t056006C0C0944C4410006004056007406146894446147336256400506106C47416086400000000000000000000FF26060000\n\t08000008000000000000000001002000000000001000408480C008084010A0C004224021A000647210088800000040000002\n\t8D000228044000100004004040000000000000000000FFBCD80000000008008808008008B08C0AD2820A00802040A00A0A20007cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF061D00000000100100120100100120000000120000008000040000008000040010\n\t00004805004000000804000000000800004806000000000000000001004800000000000000000000000000FFA5F600000000\n\t0800800800800800800A08A00800800002200200481200200200204308220A04200840220280200A08200200200202A00A80\n\t2000002002002002802000000000000000000000FF0FC3000008000010000000000000000004250000000000000041008040\n\t8110080C000000000904A0080808000000000021000801000000000430001000000000000000000000000000000000FF42A800fcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60A640640400\n\t410C08420080608408E01407E40600400800208E80200000E00622660E006050000000000000000000FFAE52000000000040\n\t040021801801811801901A04800102600680600710E156016807509201280302006084916804800106040110917116106003\n\t416106D5685644E000000000000000000000FFFA88000000000001080001801809881821811888900000600600600E046006\n\t006000040050000000106404424526480026210006226246006200006006006006006000000000000000000000FF0CF50000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000002c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018080006\n\t01845815801891811A5180000060050000060A600690E0C710F0A34160A01060118260070060140825008028461401008065\n\t0700648700F000000000000000000000FF3F0500000000184000000180180180180180980388000060074002178160160072\n\t0720752700600010740020634C40600404208608200600200040608608F02620E028000000000000000000FF092800000001\n\t01012B08218018498CD8258018080000C044544440060A600720E0044A80042000804070040368061962A621C01672822688\n\t0210106004004007026000000000000000000000FF657D000000000201200201801801801A01A818800000026806404406000082c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000600100\n\t4487806080000000000000000000FF03CE000000009880800001801801801081800241000000200600000604600601600402\n\t214241200400410404000400600600008080600604600400700A007C06206000000000000000000000FFBE52000000001811\n\t010A21809851805865863A0381808EC44444260610618E10604E52280A082B4016C0A0806804936080A3646700005E100100\n\t70610D00400E207000000000000000000000FFD913000000001801000021E2B803841E0980B80B800131400E003806806016\n\t00609600E01610740040C04E0130040461094C601028000600200800720400409600E000000000000000000000FFEC1A00000042c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3062440A6142\n\t246A04006000800A26546256C04D010042368CC004096888084447206008000000000000000004FF5F9F0000000018018008\n\t8088180180130182020000002200C400209600620600600400A0062021201042048248040063042040068042060840040068\n\t0C10C02E506000000000000000000004FFC39B0000000018018004808818038010818000020000002004002086006006D061\n\t4494214708208449C2040A40440060D00E050010E056204004956106466086086090000000000000000004FFAC7500000000\n\t1C00800001801803841401C0009300000010069000060060060064068020028A240100400410440732600608400600C0064500c2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200380100080\n\t188D801829811809800102C00400600600600600600400A04210A48020401628400E04F02400420600401680440000600400\n\t4017806000000000000000000000FF69FE000000000001821081803803801801809801820000402410620608648700610503\n\t20A2002044C8C08E00000602620000500010C006004085046008414016086000000000000000000000FF31C6000040000100\n\tE01001881841803805945841800030400400402601600E006086207C0A2C72100064060042063060870C40060058960D4244\n\t096404105D16006000000000000000000004FF5302000000000000801001801801821C01841B11800044412400400E0060060022c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006004006006\n\t006000000000000000000004FF0B4F000000000001801A000018018018018018018000806006006006006806006004004806\n\t806000806806006002006006806806007000006804006006006006006000000000000000000004FF42460000200000018218\n\t01001A098058000458410000002002806006016106006086C06082042004006000A0600600200010600000E0000140840064\n\t0C106506806000000000000000000000FF14FA000000002105801881105AC180184B101809040053204680624608280E0060\n\t04854A0A20A08A50ED00906216517544826A06006880126822096006006006106000000000000000000000FFD0FE0000000000a2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2E2860008000\n\t0800684601600480420E80604680608000C000006000806006006000000000000000000000FF46CA00000000180181040180\n\t19518455041240011140CD21544144325064CE08E494C56A0833002E12E50142410E05280000680000E00101602604600600\n\t6007006000000000000000000004FF985B00000000180180000181180180104100000300000024040C410201600644604608\n\t610000008000601600420640454C406016006100006004006006006006006000000000000000000004FF8A18000000000001\n\t80180000180180180080180180000060060060060060060060060000060060040060060060020000060060000060000040040062c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001801801\n\t809800809A01950094480391688A8124AE8460061260040044C8047804D5400408A40102E800006000886200806002007006\n\t046000000000000000000000FF116F000000001800000001801801811C000218410000280A060A60B200E2EE2AE68646C68C\n\t62C0F00EE6BC05C20C22602005602E54E000056420006002006006406000000000000000000000FF11720000000018018002\n\t00801901A01000110001150014300451454201651654600410614080028600604050400CD1440600610080E0001040070060\n\t00806206826000000000000000000000FFDD5E000000001801808000809821A03021082243088002A0AC80D20AA82007006000e2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1204680C2860\n\t00000000000000000000FFE629000000000001800001801801801801001A0000000020060040058040060060060000060060\n\t00806004006002006006006006806000002000006802006005806000000000000000000000FF49E800000000180000000180\n\t1911841904881861804000480640200200600680620600000490400100600CC4410801210440688700600082E00004700200\n\t6206006000000000000000000000FF48C6000600001800000000801901801E00E01A018001804006403A4200600728600520\n\t42C520400000624500600040600400700052F801006000006002006006206000000000000000000000FFA1F10000000018000012c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010121002080\n\t0600008210100100410106820088230000A08008B00200820000000000000000000000FFFE35000000100145802002801801\n\t905A60845816800000602654608420000610600482000208201000E00400602002240602E006486400402200526002406004\n\t016000000000000000000000FF10A6000000200215A4A320A81A81A518A0201A2C0000812C4E90E90694E90642E80E029512\n\tD22820416C24A34A208AAA2F106910086140D12A00206C4228EC44046400000000000000000000FF117700000000C0018000\n\t0380180188380980980080004A6102C0421620600608628790100600E000006884004002203107C360400362080220500D610092c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (202802C02000\n\t842102000000910E108008009B08802809890006C8528C00801000900800C88A200008008009209408108909C08988090002\n\t40000000000000000000FF9025000000000800800800800804800A0080092080006A280200A00204210280200200A0020020\n\t00702182452442212082002003002210082001042633066423202000000000000000000000FF66EB00000004380981198001\n\t1811868318001808000000018C0906000084168402500C5010840000000064220004040058A800BE01804000802800000000\n\t0000480000000000000000000000FFDFB90000000000020000000000000820000080000000048000200008400000828000400052c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (300280200000\n\t0000000000000000FFDA9C00000022220232420020020022200120020A000080880C809001000800004AB090C004894B0082\n\t4320940A48950840014820925000950801004904885000004000000000000000000000FFE8FF000000121901901881801841\n\t84194900190B8000406494006006006206046116044004424000006826106016126126C0600E01601022600001630C006206\n\t216000000000000000000000FF733E020000410C44C08C00C08C14D04A04C4CC00800114A0034B340352B08A903023403D52\n\t09340928330325324320B40B01310220254110B0103430422CB002802020000000000000000000FFFF96040000218200328200d2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D50C80C81280\n\t800C08D10C88D40D10900550830900D50B09110D50D50000000000000000000000FFBB310008004004204025104004004004\n\t0040044400010110010000010010000011210000290894010015010290010211111490410518000010010015418010010008\n\t00000000000000000000FFE5850008000880A80100AA0AA0AA0882AA08A08000000400302002A82A82A82A80002202282200\n\t002408002101002402802300886102A80000022A80000002A82A8000000000000000000000FFDB8A000000200A00A08A00A0\n\t0A00A00800A20A208000CA2A8294300280280280280280288280300091201280A90280300A902C0300A000C02900802C32430032c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A0AA0AA0AA0C\n\tA09000003A02A82202A82A82A8AA80000209800400002A80500082A82104000000882002A92400022A80102A82A82A800000\n\t0000000000000000FF3DD8000800002004020000000000002200024032000000002000000000000000010801001000000201\n\t0028320020000020000020040800280002000040420000000800000000000000000000FF69540000000A81120880000AA0AA\n\t0AA0AA08C08000002202A82A92A82A82A8AA82104C8C004001002A80002802A82800202002882802A82882002A80002A82A8\n\t2A8000000000000000000000FF6D810000003503503043543543543501543103000000C90A80CD0D50D50D50D50C40D40CC000b2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (003002000000\n\t000000000000FFB4FC00002000980192B811801881811801001801900028602600621600620600630E216286206000006244\n\t22608608600400600608611613600000C00408600600E006000000000000000000FF286F0000002222002042102002002002\n\t0120040A0001010800808805000800000800088010D50C00800B24940800941414D10C210B4804800C008049448050048040\n\t04000000000000000000FFBCF7000000000824840884800800800800820840800000200208200200200200234AA022220020\n\t8000201220200200A14202200200200215200000240A002002002002000000000000000000FF6A5100000008C0880C80640A0072c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000A05204001\n\t40140044400086100108050000008000090000008000000000000000000000FFC90B00002000080082280080080480880090\n\t0900880018200200210220202A00A18A08212A00210801211202200200220206200203201209208004202200264200000200\n\t0000000000000000FFCA29400800008000008180000000000400000480000100900100108940020100002100120128100100\n\t9000008208009081018001001001201001081001005001001000000000000000000000FFB831400000000800800800800800\n\t800C00800C80800101300315308304204B45202314305308300915308200A43202B34344210302300340308108304301340300f2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8000C4021801\n\t93201082AE28610620608400C1042A442013E06208607213E20678260010602809601600000214A022036006000086000000\n\t000000000000FF17B6000000000100005800005815800000105901800000045604600648C104000004244016406000106102\n\t2262A600201000604E086006002080002402006446000086000000000000000000FFA13E0008000000000000400000000000\n\t4200204C10800000000204001100200400000004083002080004005000C00000883000860202803005000802800100002000\n\t00000000000000000000FF4E2C00000000180190180900188180100000180000004040200CC4000200064402004281040000000ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00000000FF9AF020000000080004180100080184284402080580000000160061064560040002060941061168000020441020\n\t1224200A00402600600602C800002402806006004006000000000000000000FFF76000000002280200582080180180011180\n\t183180001080060D620610600400604C2260120062000060962360C610A1240060060060062020800020B000610E00000600\n\t0000000000000000FF8EDF0000000008000018D4801801800081821853844001008648640600604403200408612202629000\n\tE20600600600208422610002628650A2000120C2046006400006000000000000000000FF71E900080000008006388A803809008ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60A85564B650\n\t4548556510556006542004550492556556554006000000000000000000FFEEFC0000000A88CC0898C98AB8AB8A802388D821\n\t00002B022CAA62060262AC2A802C00422A22C0002AA00422220A02E2462A808E2AE0061160802AA2012AE2A62AC006000000\n\t000000000000FF46A700000000204402181380180180000202584100002000040860060060040000040AC10200C000006204\n\t006006006006000000006006016200002041006006004006000000000000000000FFA4B600000008C0A80C988B8AA8AB8888\n\t018CA98580002202A621617E4142AC2A84861542202264802AA6040022025062022AC6C82AE0064840002AA1122AE2362AC0004ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C08210008000\n\t0305520001064860060060040960100142000060400060160000040040060060060060000061140060060060060000000000\n\t00000004FF1A250000000898A988D8218AB8AB8AB10088B0A88000200012A002261042AE2AA2AE4062903854062AE2002AE2\n\t260500002A80C82AE0062270062AE2262AE2AE2AE006000000000000000004FFBD0200080000100180380580180180291080\n\t1010800000010600000610600600410420610010488000615010E12600009400600600600604280000404000600600400600\n\t0000000000000000FFBEA520000015111191192115595595403091111480001284C64284CE4565565565560064464441045500cac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF700200000000180180188180080180000080101500000860160080064160064B208600C48602400414C08210C04C00\n\t60040880000060060C600410401400600614E006000000000000000000FFFB9B0000000310058018430008018348B5801021\n\t000000E14600000600600600401614605010E00000401600450410E094026026006006012000246344006006006006000000\n\t000000000004FFCD4400000002300380588D00080180001480100500000860060D001602E006006006226026026904002096\n\t0020823564D4006220006006112C04004004806006006006000000000000000004FF019F0000000018018418018018018010002ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (082016026224\n\t0102AC2AE2AE20000422E2862AC2AE22E2A8000000000000000004FF8FB5000000410555D55903D54D558558C35501428000\n\t44E44C5425560175444362A642200E5100041164D013601444A44448E1305565540820044065165505564445500000000000\n\t00000000FFCA19800000000001801801813801801801800023800001611400000600600600600400209400000400604E0460\n\tC640E10C4260040060060B2000106016004006006000000000000000000000FF9F620000000838A98AB8498AA8AB8800118A\n\tB08100002263062A02AE1A42BE00022420410624400024422222400422623420428E2AE2AE21600005E0042AE2AE2162AE0000aac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400080000861\n\t1400B0060068044460048004860040000068B022608804800008640400600600000500600400500708600000000000000000\n\t0004FF206C0000000A9AA98AB8C9889AAB8A19478B008980002262442B02AE2AEAAE1D62AC2A80462AC00401420241640218\n\t400430608C2AE2AE2000040062442AC2AE3262A8000000000000000004FFBA810008000A4001801811800801881800804010\n\t800010000400A006226004106016116420002002206006202524102104020400006004220006106026000006084000000000\n\t000000000004FFA7DF0000002AA0ABAAB88BAC18AB8CB808AC208980003202042A02AE2AE2AE2062AE2AE4042AA000326306006ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFDE80800800409A00201C01C01C01881C00C218008040447194015016C06C16C260155148052444004250500D408200E306\n\tE86244027006002001056087025106802000000000000000000000FFA68C000000609801801801C0DC01901A01E020248000\n\t1008262A220602600508E40700028E90602500500600500000400904048410680444600520610C8064070000000000000000\n\t00000000FF05FD000800001A05A018038018018058C1808045800000802600000680600680E0060010560060002CC00210C4\n\t424045348480240060040D40005560AC006006008000000000000000000000FFA2E7000000005801801A41C43C018118090000eac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (966461340A00\n\t4400E00A288000502000224086002000000000000000000000FF73F9800000001844001801C00C0180181088180002200040\n\t2630E00E1069140860160044102140011050A6203008032092A1632424600600610080829508203613224000000000000000\n\t0000FF551E800000201800001809813801809820A03844824010702C0B4106526056A0E3154D40040C641021421002204208\n\t602204608508600644200005000C000486802000000000000000000000FFAEB3800000001E00605811801801811840941810\n\t040000500600608608702404608602400640C00804E20010412832A246086005046006006000106007026006002000000000001ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0080A0000708\n\t620628682400E0080024002D414040610600042C4221002400C403600240600000010000604602A020000000000000000000\n\tFF7123000000000400001800405885801891E218200C4002804644C02E02F10C006004142010004400144052480104012030\n\t10840400601201412000240014E116102000000000000000000000FFC0C1000000000008001980003A918998C71218B58800\n\t02850600602600E02410E00400610000422000400808002600200400000440600210402001001040E0060024000000000000\n\t00000000FFA9A400000040040040582220980B00182110B81B80806402844266162274061060000A65900B40C02260420102009ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF39\n\t5E00000048C8A8CAACC8AAA8408AA90C8AA80480006004030022AA2AB0222AA14232208A06214046A00A3C24022222A229A2\n\tAA2AA0120480000822001422AA412000000000000000000000FFE4E9000000041A01801841801831C0182120188800009060\n\t3444600000010E00000010040420C00208044401402000000400000400040022000244810841000002800000000000000000\n\t0000FF092B80000040200440000200068200008400002200000482800880000002000002A800802008014040010004031008\n\t80100200060000C8080100000040120000280000000000000000000000FFCAB300000040024C401C24209C01A81801A13880005ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100C14000080\n\t4800414080550085400804145000000000000000000000FFD256900000731955955915C09D55D55D09F51855000144E55754\n\t755755755755624E4450C444E080557547416446016084526157D564D6446400446456326556444000000000000000000000\n\tFF56C7000000088AAAAAAC8A8AA8808AA8108AC80080000220924922AA2AA2822AA20A2322325020001122A220A08A2A2322\n\t2022AA2AAAA208200000224A00AAAA002000000000000000000000FFCA460000000020000000204C04002000220040800001\n\t000000808800000800000080008810080008000000100088520820008000000000088000088001000000089000000000000000dac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (048000800800\n\t0000010000400010210800000011010000100A09100C0000800108420200080108100800050000000000000000000000FFBE\n\t601000002400000004400C200000000020000800001000000080008010000005081502000080800004400B00804102000002\n\t00000000008000028000400000100000000000000000000000FFABEF810000088EA8EAAC888048AA8AA8A08AA8008000303A\n\tAA2A22AA2AA2AA2AA00230248B2220082AA01A24222200343220A4AA2AA22208200020232203B2AA20200000000000000000\n\t0000FF5F65800800440200200200400414400040400131000109404104080400505000400000490401000000000800004001003ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF3D6E0A\n\t00080008002008028028008A080285284480A008204200A80200240A0020D220228220A000002502112002A421028A22822A\n\t2C422024080020820A20A2002200000000000000000000FF2C8F000000000000200000000000008080000000000001010020\n\t04100081000000008000200804018A0020000000080C20200808008009800002000010000000208000000000000000000000\n\tFF89FD0100002000000000046106000000004001000000200400000400000010800000841100100140000000640000008D00\n\t000430800080580050860400008000000000000000000000000000FF198D01000000200400000240840020020C000144000100bac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008208010800\n\t000882000404000000000000000000000000000000FFE4F4010000018802000800820800800810A00B00800100200A00A4B2\n\tA022030220A304210360B4000AA00245308282B00A40A00300A00210200004200360200260A000000000000000000000FFD6\n\t4D140010401000001805805801951905855845814051412641741600E51700614E0074044960000C7D075160064D6305544D\n\t5655751620400080608615694600E200000000000000000000FF02C902000800100000800040040000000820020308000040\n\t04004008884000205800404B6D800608200AE888820828004420480100424010449104581400580040400000000000000000007ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF295500\n\t0000000000000001200001001400001000000080400000000400000480080500000080500080080000480000080400400080\n\t0004000800000000801000000000000000000000000000FFF332000000000802000802828A00800800A00800080000220A00\n\tA80208200200200200281610A0A008A00200210284A00200300200340220202880200200200200E000000000000000000000\n\tFFFC260400080010000080000000000002000000020000000000000940400408440940000440000012C204D0100210A8029000fac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFEEBF000000\n\t0002002E1001003A21200000A01800000002008708608692608624600600661C60248020601400082D20800401400A416026\n\t20200042600E106006416000000000000000000000FF9C1B000000001000001805801843801C01011D00000004030E0B6106\n\t046A16216116087020820130A254249004B42902202408C612704691000102610F006A06006420000000000000000000FF7B\n\t2000000000100008100100380180984480180000000080260060040060860060042261000060001060060280060201000800\n\t160061162004000160460260C6006000000000000000000000FF409B000000000000000000000000000000000000000000000006c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8230600E2060\n\t0000E2060870060D7000000000000000000000FF3A880000000018002018810010048019428B0CA3800000202E8262068060\n\tD62062CE027AC61281000160A608204EA800222022C181604B8060000062060068350A6000000000000000000000FFA47400\n\t0000001800001005001200801A228109010000002416016006106C1600610E0A60A704622002620C09208408054340B10212\n\tE106116001016046006446006040000000000000000000FF277E040004000010001801805A03108201001200000010A02642\n\t614401600602E006216004002408D84C26420A060640050B402160680A4122002161969A608421E2000000000000000000000086c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (601600710610\n\t600440604244000420600784400610211414400ED06006906000006016406042006000000000000000000000FFCCFE000002\n\t0010000011008018018018A10498C3000010001604780600600C0060048860528062048068040240148248A0810006026006\n\t006004007817A07052006000000000000000000000FFA0B7040000001810003801801800902001100A00000060A28640E546\n\t0161060069460D610F64216906500C52C6C491C0861E68400B6042016000066106206005006E00000000000000000000FF8F\n\t35000000000800003801802A02802205800800000000BAC780E00600682620720C806A0608A01030E2B5015904204806C0740046c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8C0400000010\n\t000018010818408018418358018001004006216086006CB6006106206012B2708003690600220608A005024C050070030060\n\t0408F04E406020206020000000000000000004FF4DE802000000880060180080180188180100300300000020062162061160\n\t1600E50610790600888004654401650580600420C024806002826004086827856214206080000000000000000004FF3AB100\n\t0000028800041420941801052049041C61000000800602610E08E44688E0060860361000600160244270C44166C008940C29\n\tE00209200401600600618C116040000000000000000004FF0B9A000000021400001820801841C0380B40900100000100060200c6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6206016D0845\n\t402E006006006080000000000000000000FF3AD50000000018080218018A78019401E52218010000007006306006406C0600\n\t600480600360641100400701602612E104004434016202006001006006006004006000000000000000000000FFBDBB000000\n\t001800041821841801170605001805002120408E80648680E00600640C2061820960054AE40E41E046C86055EA424C2A7022\n\t0520050AE0060D6400116100000000000000000000FFA37C100000001000001E01011840883A0BA01855800010C04790E446\n\t28620508602681644B0002ACA07547803C0640255401508401600200E48CA062AE006014006100000000000000000004FF0C0026c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006006006\n\t002006006000006006006006006006006004006002006004004006006006006000000000000000000004FFA2130000000018\n\t00001801800001801801801C0180000020060060040060060060068008068060040068060060060068060068040060020068\n\t04004006006006006000000000000000000004FFA71F000000001A0020120183100020220920180180009080460160070060\n\t0690685600201400280624A0128068062060010B0104086042006006884306106016006000000000000000000000FF284610\n\t0000001A08221841900040A000012418558020A0510F206544114006806806C10B24102925082CC2006227036C2C4040244400a6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000180200\n\t18000000038298A1201025882020600EB06A04204A06002006004006602004802822C2EC0608600600610480200A106004AC\n\t4006E26006006000000000000000000000FF72470000002018001018002012018145510050C110414121064564A451641600\n\tAA1620E8C610240000203208C004007130000C4E003006806104407006046006006000000000000000000004FF5847000000\n\t001804001800000003841801009001000014421600600C0460C64A21260C42060020AC00228204401408E404204004002016\n\t006004104006006006006000000000000000000004FF753000000000180000180180100180180180180180000060060060060066c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00E001016006\n\t00600620C000000000000000000000FFA82B00000040180000100020180180020890C849802180A03601680E10500E1500B7\n\t2B6C04106110886C0E04E2040072A00A09410A7082C06048004107006006006040000000000000000000FFB3190000004018\n\t0000180000180180000100EA0580004A608608E4AE0A60A62A82B62AC9841862B80422CA28620C84F2A81402A81461024060\n\t91045006017806406040000000000000000000FF849C0000000018000018000010018058110910498040016456C16054106C\n\t56152546556456203344502492C54C0401653640652E812806016044016086A0700600E000000000000000000000FF14600000e6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1640F31600C0\n\t0434722000400408000422604E20624201005400600A04200E114026006000000000000000000000FFA32E00000000100000\n\t1800200801801001000001000000200600600200600680600600400400600080000000200600600600600000000000600000\n\t0006004006006000000000000000000000FFC1DA0000002018001018002018000058108009078000A1640604620601601600\n\t0017004CC6A06020806806806804027004404002802802106000866006A0E806004000000000000000000000FF058A000000\n\t001800601800000E00803C01800A018000003C06407825806C46801C0600402F007A004270A740700681601420420A00A0020016c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010084040140\n\t70000602000001003000000880088000380808000008104080190000010B0800000001450400000400188000828040000820\n\t100400080000000000000000000000FF8D080000001010480018080418018118288E08010000206006006280024106006206\n\t0840242E0040A0001000A4968061065062A6040016006100106016004A06026000000000000000000000FF3B510000003150\n\t00301A2A020AA1A21A202D0A490000C93096206A84936026806006884A4C808800320308A148D40969068AE886B4090024E8\n\t00C12126A04206CD4000000000000000000000FFADA200000000109000300010BC13909213C00101000002624602E03600630096c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2914280322B3\n\t03002000000000000000000000FF96D900000020400020222022024020020620830C0000C10000A08800500C900089090400\n\t00810920800948890800800810000900610940800800009001618900A00000000000000000000000FF826E01000000A80000\n\t0800814880800810800800800000220242200200B02260340200210210A202102A0200210A30208228201200248A20201264\n\t3086002002002000000000000000000000FF69E200000008000008101788B13918D94000188000000614A000000100420910\n\t00800052000004000040847040200A80690680008200201000088200080C0020408000000000000000000000FFEE660000000056c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2C43002002A4\n\t2C0080202A90280290200300288A803002842800802002802532002000000000000000000000FF15910000002000003102CC\n\t23520224221023254C0001000005004A00800C24000894800080814840CC4904848B28C05090110A4080480088C882000004\n\t800805000000000000000000000000FF855701000001380000185180B00D901849851911800040680640600E006006886116\n\t44680E004540014004016216006106D06406534106006002A06016086006206000000000000000000000FF47DC0000005008\n\t42420C828C0D40C12D04C00C04800103340300300348230B4022030030820AB00010215350308252B24B023113003433083100d6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000480341042\n\tA82002B421024C0000808D505504C0D50D00D50C00D50C48820821400000C48C40900548D40A20D50D50540900D50550D503\n\t10D50000000000000000000000FFB6A000080042800040042055200048041040440200010000010000000000010010010018\n\t080C9010001801051000301290448081000010501401000801001C31800000000000000000000000FF62E000080008200010\n\t02000900880C808008010000002E02A8AA88082A80002A81002A8328190000008610200100428A202300002A82A82000002A\n\t82A82A80002A8000000000000000000000FF90D1000000048A00042800A00A40A00A24A00A00800100B002002142802912800036c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200200240200\n\t2000000000000000000000FFF8B00000001044000AA0A800048408C1400880E000002212A82A82A92A8AA82A82A82A8B0108\n\t04002A82A83002A88000010002102A90C10502002A8AA82A81202A8000000000000000000000FF851F000800012000002480\n\t4400020920000A200000005000010008100000300000480000004004000C8940080008049000000090000001008000001000\n\t001020000000000000000000000000FFDF260000000000000AA08A0000A80300020A809000003282A82A8AA82A92A82A82A8\n\t2A82404000012A82A82002A8848020080A202A83000000002A92A82A80002A8000000000000000000000FF414A000000120200b6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (453443403111\n\t02B402002013403443403003243003042889103003003403002000000000000000000000FF67D00000000000138000D18150\n\t01813821801801840008402620621620610610608E0840141562400040842260861560060061260841161062020263160160\n\t06026000000000000000000000FF43FB0000002C0200200201291052242202202200000088C0050040048000008010008041\n\t44810800004804848800510934434000804A248C4800800004800895004000000000000000000000FFBA1600000000C00080\n\t0004842A00800928840812800000280200280200200200200200200A2422088020020820020222029028D2002012412000000076c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000190300000\n\t380000980002000800403100C00400084440885100802404000944844441002080400000C00000100A040008049001000002\n\t0000000000000000000000FFCDD800000000004A8000A8008900808820900888800020220202200200A00218A02200201208\n\t20205025120020120226020420022E20D2012000002022012202006000510000000000000000FF6A314008004004004E0400\n\t40041800000000051000010010010113092810A100100102132D009089121000000009081001201001001061000089021045\n\t001001000000000000000000000000FFAD5A400000420400C80400D00C00800800808C0080014032031430430CB03325302300f6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006086000\n\t288000000000000000FFF8C40008000000C9868000140869800009103830020010E04E0AE40609402A00E30E0060121EC220\n\t0581001004E60844C62462262822061A60180124962E4216036200000000000000000000FF8FD30000000801118020000018\n\t9182405502D84000A00460060060061240C000200400620200650800004000810E0040863062265422562071000221263163\n\t06026400000000000000000000FF339600080010000000200015000004202204800800C00A04200002000485000000C00004\n\t200000880400201302002080400800000101004000800B0450000108090000000000000000000000FFC9CB00000004000000000ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (262060603A62\n\t260820062AA20632610222204E2AE0001EEAAE2242AE866000000000000000000000FFF1E900000000200188000400580180\n\t00A5801809800032600600644629600600600448610600680000600601202E0000CE00E8AA10250600680020600610400650\n\t6000000000000000000000FF0AE60000000000018540000008AB043808033842000001600600600E04400210600602C0160A\n\tC00001009024028200400610640000A04600600000600600E006016000000000000000000000FFD834000000000001810000\n\t011801001800001800020000E2160B600600420810E22E00404600E02028420C02000228C006006002012106036000106006008ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C3143040004\n\t953955800028E5565564C65565544D65564515504160040C20024145565520C62CEC0E4882A65562040D4D56556557556000\n\t000000000000000000FFC8A50000002C8001C0008A0AA831011912889893800008A2AE2AE11600E2AE2262AE20E296204000\n\t22A2AA34C4422AA2062060102A62162AE000416AAE2B62AE086000000000000000000000FFE8864000000000018000000098\n\t118938A980180180000020060060160060040020040868061260082163561440060022060060200260160060022060060060\n\t06006000000000000000000000FFE9892000002A80018000A80A890198C0018C588180000062AE2AE0C64462AE33E2AE0462004ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060000000\n\t00000000000004FFB6DC000000200001A0000408100100182880180180002420060061460060001160060000040060002022\n\t4201600400000610608410210E006204556806006006806000000000000000000004FF227F0000000AA0018AA0E800B08108\n\tB8008A98AB800004A2AE2AE00E2AE2A82262AE2A0AAC2A700800A08A0862AA2A829620632620A2062AF0040062AE2AE2AE2A\n\tE000000000000000000004FF0C610008000040018B202000000502184080182180002460060064061060040020040810400D\n\t680000200200411600014E04E22401008600680000400600600740E000000000000000000000FF10BF00000035400195411400cec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (408022222238\n\t60044062AE2AE2040062AE2AE0000262AE4362AE2AE000000000000000000000FF9EAF000000000001000005805081911801\n\t801801800000000600600600440400600600A00200620400200201650C0060060060B400400600600408C00610E006006000\n\t000000000000000000FFAD6600000000002300002180003304002480182380000940060060060940C60062940820B034E020\n\t09608E0220464D60060060042D6006006084206006406006006000000000000000000004FF63DD0000000000010000018210\n\t2B840103803801800010400600620600400600600600A0000170001460062420060060560560140440260068040040060060002ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AB8880832AB8\n\t8900002262AE2AE2AE2AE2864262AE2A02082AE48808612620E04E2AE2AE2AC2282A62AC2AE20420C2AE2AC2AE2AE0000000\n\t00000000000004FFEBE8000000001914801D559518CCB11951555955000055655655655645644655640640E44A1162A444E4\n\t44454514156556554200454556556104014556124556556000000000000000000000FF2DD580000000180080180180580182\n\t1851001805000011600600600600600600600600604200600001601402400400600600408001600600600008400600400600\n\t6000000000000000000000FF009F0000000000890000898A800104388C8AB88980002202AE2AE2AE32400C2AA0642222024000aec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000000000\n\t0000000000FF7D36000000000800000004084000C11821801805800103480680680600612640600600001500400420C20289\n\t20021060040000C0816004006004004006800006806000000000000000000004FFCE220000000008AA0000881410AB807801\n\t8AB8C980002002AE2AE2AE2AE25611E2AE2B03242AC00044440C3267042262AC2AC2042062AC2AE0042442AE2A82AE2AE000\n\t000000000000000004FF8F78000800001040801801803800C02001001801000000600600600600608E00610E126100040004\n\t1000960060260060060040A8084004006004344006004006006000000000000000000004FF020C0000000010AA801AAB8098006ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (120006006087\n\t816406006016006207006000007106017004006000000000000000000000FFC279800800001801800C00003C00C01829A018\n\t118000C07026E0742E99F116E074C6C220768180004806E2C1201A00F307146186C0680610660080480700C0050060000000\n\t00000000000000FF4060000000001000841600440000C00101801823800000F00712600702620602700601608002401500D0\n\t8F0060060A600400020008400E006004006806002004006000000000000000000000FF20ED00080000100080102004940194\n\t188DC0184180001060060060068070168C70068081000045100A40C60060D60170070040141248040064010D60060020040000eec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9801C8180308\n\t000362261CE22620642604642E23200614C60000C09A40200210600A08C4141820080860200041060A00A008600000000000\n\t0000000000FFC94A8000080018098010200128004020A0803901804000700700600601640620E8860064560000A12410460D\n\t608E2860260022CA0560464061000062A600A00400E000400000000000000000FF52018000000018018212002A1C00080100\n\tC81835800020610600650702615611604F48029640000845000700E10602608612200220640F106000005006001004006000\n\t000000000000000000FF1D41800000000801600808105C00909849D0180180000061260060AE00782608E117142406300200001ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF01B3000008001001801202000844211048A89805100004422608E20620E02700602E00642A10C140024036006116\n\t20602200800001201250608000E506002000006000200000000000000000FFEAC100000002101180140800D800E25101C058\n\tA1012040401600604600648609640600008220440000C10623600608640C0802CC0420C000E4400C60060AA0801160000000\n\t00000000000000FFD222000000020001018840000801021808809821008020200E0060060060864863064420862840005840\n\t0230206200620000400010208000E2000AE046002058006000000000000000000000FF6FCE000000000001000C1A00182381009ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (294282C00008\n\t400000A4000880000000000800028000004000000000000000000000FF0CDE000000081820891C888C8806806888CAA8C880\n\t002622AA2AA2AA2AA2AA2AA2AA0422560022001221022425422AA0022222224020202AA1000022AE0023002AA00000000000\n\t0000000000FFB515000000000011034005800020211802001820000008C00000000000000100600040404802408001410808\n\t8108000004084014500090000100410000400150000000000000000000000000FF597580000002A082000020022110140040\n\t00000400000000000000000000000000001300802900002802200404400003500080800484000000001200000A8000000000005ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400004000000\n\t9004805004004005000004408004204500A3484100000000500090C004000934804000401004005014804000000000000000\n\t000000FF31D790000014315510973584995551190BF559558000106D57556D5755655755755620641411450120C086106017\n\t5565174254044C6457556400556556504C57556000000000000000000000FFDC1C0000000AA8848C288AC8A8008888888AA8\n\t8880002822AAAAA2AA2AA2AA2AA2AA1023020CA00100320A28A00A2AA2CAA222AA0B22032AA0000AA2AA2AA222AAA0000000\n\t00000000000000FF363C00800000800000400000000040202000000000002400000000000000010000001200A0040000080200dec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFA23A1080001004040040201501005400100000000000000000000000800001001000930110290000280288000040000B\n\t50D08A80100010000000000000148080000000000000000000000000FFE80100000004400002020400204C01012420000000\n\t000A800080080000100000000040000002050101002012809100000002001000810080040000000000001080000000000000\n\t0000000000FF9C8F800000008CA88C88889048008428008AA8AA8001A13AAA2AB2AA2AB2AA2AA2AB012223C0200006200220\n\t22022AB0021120322322222AA0002ABAAA2023222AA000000000000000000000FFE1CB8008000010490014404000A9420044003ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C0880E860420\n\t4820801404008708500500005801004000000000000000000000FF8BCD000040000800900850A00828802AD094A800800024\n\t204200322A2020134CA10200283200200034324300228201208250A2C254288310850000200232230A002000000000000000\n\t000000FF707F00000060060000000020000000000000000000000882880509000500A08018200001008A0480008800040000\n\t0A0208820000000240800000009800000000040000000000000000000000FF465B00000000019811011040A0000001000000\n\t000000000800480000040000000040001000300020C100804000000000408000080400412200007C07C0800010840000000000bec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800200001\n\t000C48000550910110110540100B00248510048A080884000008008000000004100480000008080000000000000000000000\n\t00FF7F3900000000087080082282EC008008089EA800800020280300A12304208A08A08A08A00A4020500820421823220020\n\t8240280200278221000050B543782002002000000000000000000000FFE15700004000180108185180385180555195580180\n\t0024624612E52E036156256106006154506341D4C34702630611610E4D45574A60A64D000080E00754651604400000000000\n\t0000000000FF6C8D020088001111001001010000001000000000080191413400428C4042201000400012A4A482A80242AC02007ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFE07D000000000000000000000200001001001000000000\n\t0000001000000000000000004804004800000000001000000000005005000000000000800800800800000000000000000000\n\t000000FF406D000000001C808888AAA28800A0080880C800800000004020A00280200280202200200A012000902002202042\n\t0420A2006042042022C00000002002002002022000000000000000000000FF32D1040090000201000000000000201080000000fec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4260064043A0\n\t02E10701022000E020026022B42000000000000000000000FF0886000000001A008018118218018018011810018000806006\n\t10600600E2A44860841829008260000260065162030840C6820002016846010000006A00E060060020000000000000000000\n\t00FFFCBB000000001800101801800810C01901811901800024D0440260A610E2D404600C00600602E4112420A704634E0D50\n\t06044A86CA6316140140A46040006C0D082000000000000000000000FFCB5A08000000180000180182180080181180184000\n\t0000400420600E046000106104026048406100082206006006006116100026006006000400016200026024402000000000000001c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A004E026507C\n\t060070260262460024A70034010044A600F0060550C62CE30A0040062080280000069061024A2100000000000000000000FF\n\tA538080000001800801801810881800000C0288080808C401400681604604A02641601628642200882411689600682628608\n\tA428A07C06A800B0510087A86406012100000000000000000000FF1A29080000001C00901809800810C000888108C18000C3\n\t48040C61261460132260060470092124105045260C610E00D03610200250653614810044080600620E102000000000000000\n\t000000FF373E000000001800801801801801841911041001800000652674744E00600500604C0020F000618000604624E4220081c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004FF4242\n\t0000000018008038018808210018018098010000425004046006006106000016204114284000090126306086006007485026\n\t00641601000920704640F002200000000000000000000000FF73A8080000001C00801801C0C8010418018018018000004004\n\t00612600600780080E0158140440044A08161262062040060000064464060000842860060078068000000000000000000000\n\t00FF9E55000000001861819809823801808110BCC907802110F53605E0961C6816007006062006C1AB10A8520600680200CC\n\t26026040026906100000071166406483212000000000000000000000FF9974000000001C01801809C21900E08000810601000041c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D61008164068\n\t06000005406106886002326200000000000000000004FF2767000000401C01C03801B0002180180880084180000070070360\n\tA6446B2C30A14428880D00C40420682E20E00611613720000730640700000D226806426022224000000000000000000004FF\n\t50E0000000201A00A21801801801001801801801800008C0040068A6006A4E42C02611404404812180040E01601610C4A680\n\t45068B494604000402600684624A007800000000000000000004FFE3C2000000001800821801801A01001857009840800008\n\t414401680654600612410E8044840A04844082860C6C6240421608020640402612800400602600E00684600000000000000000c1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (484E10413600\n\t684E216106CB0AC1552A1040C82489600600688E10081620E40C0060002269261060040C6006000000000000000000FFE66C\n\t000000021C01801801A07001801001DC3800000000620600600700600C00200428080400000400200600E1040060060009A6\n\t0071CE060000126A27606002006000000000000000000000FFDF840000002018018018218212018A1841009201800045616F\n\tA0600E38600480A084008465C800EE18A20E046F14C0E00620014605C33710000608600E006CB30040200000000000000000\n\t00FF0A21000040011801801801800501801804820F1188005571060AE14600E24430241502049424C40022712792708434600021c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04FF747E0000\n\t0000180180180180100180180100180180000060060060060060060060060000040000040040040020060060060000060060\n\t06006004002006006000006006000000000000000004FFB432000000001C01001801801A01801A01A01801A0000040060060\n\t07006806806006800804000802004804002806006806004006006806006006006806806004006006000000000000000004FF\n\t8025000000051801001801C018018018010018011000057506C5400650E2061064160000100020A412450C8464072D604640\n\t0826006006006004002216007140206246000000000000000000FF9295000040401801001821A2190192120280DD09A0004800a1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002604600E00\n\t2004010046AA680A886006000000000000000000FF614E00000000199120180182F80180388098A803840102422C50648640\n\t600680680600480000081080420C024000006006094806006F86002000000916986800006006000000000000000000FFBC5C\n\t000000001A01001911C01801C019010149158080006454004146056206546046A004214B410411549502608040E2160040B6\n\t006016006004904426006007006006000000000000000004FF6E7A00000000180100180182980180580080080188002AE084\n\t05600E10615600E41601009000444020404400640004614628400600600600600442400600600400600600000000000000000061c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00500F107016\n\t04702600280600600000EC0900204900600728680180700200200000C00400600E086006000000000000000000FF75DC0000\n\t00001B01001801A00009801800001A08028004C01600600600600650E406486082806088D068264A40008170060220C222E8\n\t0200200080600404E004006006000000000000000000FF8D5D0000000019010018018002018018014019880A802169862A72\n\t0E2BE22EA0F26E20F7EAAA63B800E0C710428021F22E40A9A841600A002000106524016044006006000000000000000000FF\n\t104D000000001801201801801811A01E01480C1195408462340070161060B6D5640648400000080450C48C44C0510070061400e1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C29800000004\n\t5811009803881921001808A510A3800028600631612610E10621600708600644E00802004810010600600681108200E10641\n\t04000150042A254E056006000000000000000000FF636A000000001E01801801801801001801A01201800000600600600600\n\t6006006006006806006002800806000006006006000000006006800002004004002004006006000000000000000000FF0AAC\n\t000000001811801911800201801801081A80000011500481484680E9A6946806002226816000D000C080A000847106402002\n\t00680B0020005C47B4286026006006000000000000000000FFE52F00000000180160180180000180180100180010200062A50011c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0410A0440200\n\t088020600180000000000000000000000000FF7EA10000000200002022800800000842C80000020000201410169108010000\n\t800888120120000020140840130000800020000108908218000000410008180070318B08000000000000000000FF08100000\n\t000019F00018018438B100180000100D80000A48040048060064944062160060068822000000A0000286086006C000060061\n\t0608000020471600200EC26006000000000000000000FF9437000000211B20885931A03A012AB903281209800082E3048264\n\t0E826A260062B6C4ED46102C40C96286A40A4E0CF2CE4A4A0E426A2E880800B04CD680080628640E000000000000000000FF0091c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1200B1520420\n\t2340354215308008309301320205340248310200BD5314308142B003C13112013082000000000000000000FFF25800000020\n\t820D4804043052002022002002000000500000E002100A8840A08820CC80C0800900808408000C08870A810F4A10A3044001\n\t0900840880820800880000000000000000000000FFA6F8000000001800C08C02800804830C00118821800001228000200280\n\t222280340220260294E04100211200212280A00B00200300600230A000000002012202842002000000000000000000FF7D8B\n\t0000000020000040280010401491160E00C1000100D0000850A0D001040400400048042300082A4A04A8400000040030C0C40051c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000A12\n\tA00800A40A00AB0A00CA8A828000902043002002802802103002803222002800902802002802103002802812D02802802800\n\t0028028028CAA42002000000000000000000FFFC320000002012410010012032042022CD2022510000828014000004804810\n\t80480480080080CD00004804800CB0A4500410CB2082400000490088C808000800904004000000000000000000FF33B10000\n\t0000188B0058018010218D18C58918410000406C16C461062862062064161460060040408444441060860060068540361460\n\t0641400000628E106026326006000000000000000000FF5D04000000400C40A00A04D42C12C04808C20C04800108A003082800d1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A80002002A03\n\t282A8020228000000000000000000000FF0E090000001543001541543523102142222022220000500450D50550D50CC04C0C\n\t48D40A00550200CC0D51550C10440D50C50820D20550800800450440D50C48800000000000000000000000FFBE2800000040\n\t002000020043440440000444440200000000010010000010408000010004210A100210800180140080100100904900100100\n\t1002000000001001100000000000000000000000FF46B80000000AA0800AA0AA0880AC0001000500000000200A802A8AA82A\n\t82A02283A82A80C8AA00002282A82A81000182A82200100182A8000100A203A02A8300008000000000000000000000FF71CA0031c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (201201200204\n\t2A2202A00001200200204A002002032012002002002400812012002492152000000000000000000000FF17B70000000AA280\n\t0AA6AA00A0500C809808010000012A92A82A82A9AA8000B00AA8280098210001A012A82A8000AA82A84803002A82A8000001\n\t2312212A8D10201000000000000000000000FF28260000000000542004000000200A00081000880001049080001000000008\n\t8080000081088010800080000000209000000804800010000000010810080000002B0000000000000000000000FF2CDB0000\n\t000AA28A0AA0AA08008008A2A009002800002A82A82A82A82A8308A292A83289002000802202A82A80A8AA82A81402002A8200b1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00400400C00C\n\t40C00800D08C54C20C00904100B4330234430A24035130420B30C30130030232030024033030932420030330030030130230\n\t4B103103003000000000000000000000FF52B900004010400180191184983180180190102184004060863060160160460062\n\t0440620400428000600E00602600624610622600620602C080086486016026004000000000000000000000FF9C1B00000020\n\t00240010012C02A42022444012340000804004004804000AA00A4004808004884882140800804C80005004C0092080080480\n\t4802084904800024804800000000000000000000FFF2AF00000000001080080080081082080082C8808000002802802002000071c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001030040000\n\t8400010000000000000000000000FF7FC30000000840000000280200010B1001101021104020000030830800044C00000420\n\t60240805000043100000064000084A0040010400050100000030000040000000000000000000000000FFB1F1000020000000\n\t80488080880A800908824800820040868800216203201208A0221C215A052500112042502022182022102302022012112000\n\t0023000E2100002000500000000000000000FFAEE70000004004004004004001A44404224004000001001021031101088011\n\t20120002929170D0010211011982010012810000010010010010090A1081049081001000000000000000000000FF8DBA000000f1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (10600C006108\n\t0262800200020060060B6046102006082036482000286000000004002000280000000000000000FFC5030000000000010418\n\t0180190780D8398000019DC000C0842B60165140260060C804604628201830215601601E40641E20621E0C81A62620900060\n\t60082018092000000000000000000000FFB27300000000000100384580182180192190202980000244240061060000060161\n\t00106000312000416006526086006006206506210006012100006306128300102000000000000000000000FF935D00000000\n\t00400280220041400020000C00D204200A0040010010300280090040006000000000020088050106428220000000220000000009c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A2108AB8AB85\n\t1089A2488188810580005042440062AE2AE0C62AE2AA2BE2B62060000420662162262AE2AEA223262AA41622200020621C03\n\t000C2AA2A8000000000000000000FFDDE600000000004C801801B03001804841820003800020C02400600600600600600600\n\t600095680002600600608600600610208E000006002900096006000000002000000000000000000000FF8471000000000101\n\t80180184982509181580515180001260962CE00600644E00600400600800650028A28A0CE0160060060080020024AE092000\n\t0261205124A4002000000000000000000000FF3469000000000021811801805801009801820105800050E0862C60260062CE0089c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006046446114\n\t000000000000000000000000FFCB70000000354128155955B10954B5582D9141518000554554556556556556556552546404\n\tC8010440E10650644E5565568864345564CE550004126556456404550550000000000000000000FFDE020000002AA4828AB8\n\tABA010CB0889298AD029800002620E32E2AE2AC20E2AE2AA2A62A6AD62003024823063262AE2AEAA840AAAE0A622E0802AE3\n\t040862262AA2A8000000000000000000FFD21300000000040280180182100100090182000380000060060060060000060060\n\t0600603605640012042600E10600600643008200400600620020E0040860CA002000000000000000000000FFFA630000002A0049c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (021540040808\n\t0428E28E12E00400600604C00200609604C80404600408640E004000000000000000000004FF73B500000020021080180180\n\t28000018CD801203800000400400600600600600600600608C82410002000400608600600690408880600610220030600601\n\t6044006000000000000000000004FFF2260000000AA0A00AB8AB88C8AA0AB80188808980002AC2AC2AE2AE2AE2AE2AE2AE21\n\t632420D20400003224622E2AE2AE2062242AE22620300400E2AE2260842AE2A8000000000000000004FFFDCF000000000040\n\t801801902800841805800201800001410400600600208600600200600400090001000E04601600600600404000600610080000c9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8AB8AB88B8C9\n\t8818AB8AD8AB80002C62862AE2AE2222AE2AE2222AE55421A0020064042AE2AE2AE2AE28C23200E2AE0160022AE00608E206\n\t006000000000000000000000FF671500000000010D001801821841845801802801800000601600600600E00600600A00422C\n\t0C20042A030C0060040060060040020C600630C00400642E006086014000000000000000000000FFDE5A0000000000418018\n\t01801803809001801801800005602600600608600600610200610400000001602600600600600604410A2060060460020060\n\t844260562A6000000000000000000004FF292B000000000005001801A41801801001843841800000600600600600600600600029c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0630E0061260\n\t06000000000000000004FFBC3E0000000018880AA0AB8898A90898AB9130AB00002AE2AE2AE2AA2AE2AE2AE2062AE0042840\n\t000060162AA2AE2AE2AE3242822262AE24E0042AE20E2262062AE006000000000000000004FFEE1000000000180D15415591\n\t190D131955911155000049644655655653655655654E55600648000422A15255655055655624454040655410600455652E04\n\t654E416006000000000000000000FF90EA00000000180500000180580500380184180100000060060060000060060060A600\n\t62AC00800045204200600600600601403000600600600000604600E046006006000000000000000000FF775000000000000100a9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (71060A400001\n\t620200400600600680408200E00400E00000621610E406136006000000000000000000FF6400000000001845400001841000\n\t241C01C14001000000400400680650600600640680622F0080042A68230060000060060CF41402700612600400614682600E\n\t006006000000000000000004FF0E3C0000000018C88AA0AB8C90880C98AB8208AB80002AC2AC2AE2AC0062AE2AE0362AE006\n\t24000410258A2AE2AE2AE2AE2040203962AE3060042AE1063061B6206006000000000000000004FFD22F0000000018A18000\n\t01823801005801841001000000608E00600600600600600600600002400608600600200000600608C0020D600422600600600069c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (41E11081C808\n\t018010018001826127006009406107007A4784E2060021004020060042200078063200114060060060004060060261060060\n\t06000000000000000000FFA2CF000004201801C04221803089A08C2FC0180581E021601700744080608C41612702E80C9124\n\t9025302300C01E0570168815A001F08E00600001600F0AE016006006000000000000000000FF437800000040180000040180\n\t3008049851900401020040400490700610F43600600E4070B622400500722B01400120690700F04600635441600408629651\n\t6007007006000000000000000000FF66C0000000201800800201805042003801880001800000400400600085600600608E0000e9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (601601400E00\n\t0000000000000000FF01AC000000001800804009808881903803083805848008E21632620411624603E01E02602050600200\n\t041000822641E01643049200442A09400200610E026106004026000000000000000000FFF36B000000001801800201881021\n\tC00809801C01000000415480600A8471050060A64091000424300230A6B0208612652E88304CCA640602820802620608E00E\n\t897006100010000000000000FF53D9000002481801800001811001840801901801000004C0C4006A522062062064862004A4\n\t05241085200600244082608604200420604640000028E406406016006006000000000000000000FF663900000010180160000019c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000080100100\n\t0400060000002200A81082300A0100000000000000088000000000000000000000FF3435000000001800800001889C01C05C\n\t35801401010008421444620000710600E20E22014002624014001000000635628E0060560442420200102260B60060060040\n\t06080008000000000000FF399D0000000018018200018019018018019011038A2000410400612004E40E0860060104001060\n\t9000030048831000600613628620401230410008640612600610404E000000000000000000FFC24500000000180182001180\n\t684180182180509B8A200160460060B400E00E0C634600620008608008424C00004820604600A2061040022104822860A6010099c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000022000020\n\t040000000000008012000008010010000000000082001000009000000010001200000008002A840000000000000000000000\n\t0000000000000000FF4DF30000000AA8930000AA8C92A8CAA89000009880002002102AA4022AA0022AA2AA28A0022A200022\n\t222220208A2AA2AA19A2022220422021002AA2AA2AA2AA2222AA000000000000000000FF4AE0000000000010000000004001\n\t80182189040180001000D000041000044600000004640401400001400C094246000000000000000100008000000000000000\n\t000000000000000000000000FF3B0000000000002000000002000200021202202400000500000000A00008900000000061300059c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2ABAAA000000\n\t000000000000FFAFC9000000001101400401001204400201441304000000410500500000505100500400105400010300400C\n\t8C0000805004020110001008010002804004004004110004000000000000000000FF497700000055588120055594D953D119\n\t559359558000556557556156557556557556557D2D44610123502541655655755640E52E5565560060015575575575565565\n\t56000000000000000000FFC7560000000AA8248000AA88ACA88AAB2491282080002AA2222AA0AA2AA3022AA2AA2CA2822AA0\n\t012AA2A220A2AAAAA2AA2022222B24822A20012AA2AA2AA2AA2222AA000000000000000000FF397C00000000104A0004000000d9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E04400000110\n\t48000000000441041000820000020C08000000000000000000000000000000FF405700000020008000000000004220200000\n\t440000000000010000A08008000000000009308201010C01508000210008000200C000011000020080100100080000000000\n\t0000000000000000FF6837000000000002000200044400040000020000000000000000041000000100080004040000800001\n\t0800110400000000090410000000450000000000000000000000000000000000000000FF19148000000AA8288000AA888C88\n\t88CEAA888CAA80002AA2AA2AA0032AA2AB2AA2AA28A00238220020271226208B2AA2AA2020022AA2220820002AA2AA2AA2AA0039c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001101029000\n\t00000909440448204048440142346A82E800580840C6EDEB0300021080005000010C05210280001004004184044000000000\n\t000000000000FF8BC9000052048908880830800B528D0A249108209000C4200340212304200A10A08234A80228200104300A\n\t2522A2912A22402D42B0A00201000008202220008202A000000000000000000000FF31B00000000000000000000000000000\n\t0800400000008102A80A8008488820000008000080800008C88AA00000000400001000108003000000000002000000018000\n\t00000000000000000000FFED1D0000000501000001100001000005C02040000020001010100100000210010800000020D48400b9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF50FF0400001000000001000020102100010102040440901500010840820100821840AA80500808080200C82C80\n\t20000050000200020001000280800020004100800000000000000000000000FF79370000000D682281280080080A868B0E84\n\t08028220002A8270A902623092222802003D0201A08009240200240298212A0031C200A00306002806243A00200200200000\n\t0000000000000000FF4155000054051911901851801B55951855D15821884024620F48C14F0CE414086106156086D0E1528A\n\tE09484644E956C465045565070860200020A642E40480600E000000000000000000000FF1A130200006000010090010024010079c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00001600608\n\t6086090126146126000000046004108006006000000000000000000000FF4409000000000000000000000000000000000000\n\t0000000000000000000000000000006000000000000000000006000000000000000000000000000000000000000000000000\n\t000000000000FFD0D50000000000000000000010000000000004010000000000000000000800000001006804000800000004\n\t000006000800004800000000000001000000000000800000000000000000000000FF2F570000000008A2802808800C82A00A\n\t280028008000802008002802802002C104000020032222A1302002802802822002002002812802400028002000003002002000f9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (021C5B818000\n\t40E09600624204603EC10A000A690A9260808277C0806A668C6806A4C12006E20E90041104618190A4070060000000000000\n\t00000000FF617E00800000388580180180106180180002180180A0A370470250CB0061451008001060928060008060040060\n\t0080680480001B206C3603800001E11C002806006040000000000000000000FF87FC0100000058C18018018009018018038A\n\t1A1181205460042A208A116C0A004004800886006400106500C274482460244454064160070A008040700440000610600000\n\t0000000000000000FF97110000000098018038018218018418118019010000006084000400046000004404040026046080040005c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF894D000000001001801805801801821881A018010001A0602602685730600641604683604251641200602604010008\n\t002482A301106007208002444106400206006000000000000000000000FF696D000000001801801805800803C05801401C03\n\t8200907805A30C8EA8F00010200292820604600003701600000809022E416C02896086250000206801402006006000000000\n\t000000000000FFE039000000001843805801801901C21A0900181180000860243000260B750088280280004600620008F006\n\t44800E2400A40C2302086086100081444004500006106020000000000000000000FF71AD000000409801801841861101C1180085c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200660224\n\t54582E04E86E22009C28680004611E206000000000000000000004FF3909008000409815801801822001A01AA90019010000\n\t104404902106016C02A0000008688C88600C20E80200008E880026000414085106C004005460148070074060000000000000\n\t00000000FF93870000000018018018418090038018010018010220000004202A060160120840044068848060040060820000\n\t0082000C80001600409604000408E844143886016000000000000000000000FF728900000000100180180184990183588194\n\t5B058020107636016106846006066FA630642224E3880564120200D601058440600965600E10041008F02202208600E000000045c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3801F0002230\n\t162064460860278240040062918D621490F0170C680641600624D08442610604040C4045030B690604600000000000000000\n\t0004FFF18C000000401801841C019008018C181110188190009070072060A600F40625124020600800600824688E90613000\n\t600E444204084106000205044002126086006000000000000000000004FFE171000000001801821A01881001F01801803805\n\t8880404024A438220C600208A002406004447C00126202080C2600040D80412400E016020104806021086006006000000000\n\t000000000004FF3E3600800000986BA01801C21005847A2190181380000650340020028060020C644601E60409638008E15200c5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF9BAA1000002A0001800005841811821343A01C91080080400601614CB0713700688643710AC9084D02AC4200640612E846\n\t12C024342106040508406316016006006000000000000000000000FF1ED7080000201805801801801801D81A09905C010000\n\t80600606E08620700E01E08702E00020612100620210720602602640413C00F02600000000680A0069060060000000000000\n\t00000000FF81A20000000A1801C018818058058219A38058B9010040649694680F14F0868030023069004560850264E20060\n\t2098608E9841048C5006000084006052806006086000000000000000000000FF7ABF0000000018058018058408118018016A0025c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (562160442041\n\t44000004000004106006006006006000000000000000000004FF328000000000000180000180180080180180180180000040\n\t0600600600600600600000600600400000600600600000200600600400200200000400600600600600400000000000000000\n\t0004FF6C95000000000001800001801800C01801001801800000400600600600600600600080600680480400680600680680\n\t2806006804002802000004006006806006006000000000000000000004FF0F64000000400001800081A01801801C09A21841\n\t8000C4489740740680E00604680600640202020410210A04604020611700000501202600000600600614600614400000000000a5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800022255448\n\tA45690A912556CB0016B4004AA1511002000004004400C01680680404480040480600E00400600C000000000000000000000\n\tFF647800000000000180000180000983050D20380B04C0386AE4A6AA6E40280202E80880680080300600000000002680C016\n\t00680480000406000600601E806806804800000000000000000000FF48D2000000000001800001800011840800911C058800\n\t40610451241504A546456006026020002510020CC00200000069040004060041051100054070060060060060000000000000\n\t00000004FF673B000000000001800001800001800850803931810000E2040020860820160062B65160902A204400000001050065c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF12\n\t5F000000000601800001801801800A010038018000A108852A94240082024062A700190400E2914252040400010030060548\n\t0280400700000100600604400600E000000000000000000000FF706A000000000001800001801C01800001801A0100000040\n\t2E0068160060920D601680E24C84202008C02400845004400400000008A0C202042800680600402600640000000000000000\n\t0000FF90AD000000000001800001801C018083038018218A2001C8060460862AE62A2062A62AE0BC0A23E946463487069E20\n\t50A4040A20112186040050306006044047007400000000000000000000FFEABA0000004000018000018004008A0A01A0380100e5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080482680688\n\t4916140890856906CA502E80E000000000000000000000FFBBAA0000004100058000058A8009901883811815800000500720\n\t490610C40408E48000608E0260201378460260418A004C48E2B220C244000020A0624F015206346290000000000000000000\n\tFF7799000000000001800001800001801801A018018000804006006006006804006800006006002000006006006006000007\n\t806000800004000000006006004007806000000000000000000000FFCE0D000000000001800001801C018A09C15119018000\n\t02020490000608090200700680000440600080410C81000600281C40410200400291000018600E00400600600000000000000015c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000002C\n\t3710890101000061208444405800600000360040014000000800200001A0240420028000018390000000000000000000FFD2\n\t7100000004000000810000208010C00250200000001F0020E00000808420CA0010407C081201018000081006060180480100\n\t300001400800090290502105400A0000000000000000000000FFD44C0400000000A982008185D82180108188989100000081\n\tD40000D400000000600000020240600800AA120060060A002602660624C00640001000618608402600600000000000000000\n\t0000FFB71C0000000004B1830521A05B23A15241B45B01800112893408AA562428A8446810880422C9291020240AC16C80810095c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFC33A00\n\t0000020500900500CAAC00CA0C0C884C4C800133210BC030328AB323482003312343C8310001280B08340B02302341303340\n\t34025010080224AB01108300A010000000000000000000FF97460000002183002002003A0440040230004200000080100080\n\t0A00880150209608810840080821001000E28800800800100800800E88120800900A08C40A08B00008000000000000000000\n\tFF2D7100000000000080000080080A802804840804800040500808A00300220210308018208220A080232802042082142002\n\t28A0CA400002000000402002004002402000000000000000000000FF2EA000000000000210002200180148010142004A00000055c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2202200202A8\n\t0000000402001102A82A8000000000000000000000FFE040000000204400800000A30A00A00A00C00B008000902802442912\n\t802D0A802852842812002A0000200280A802882842802812C02802800800933102C12802802800000000000000000000FF77\n\tED000000250401400401202200200232201232000080C84C084C400048008D490480080400084000410C900C00810C881109\n\t00895000000900C048548C4004000000000000000000000000FFDE3404000000800180000180184180390184180180000060\n\t4600400600400E01648C006004046440B04024426006096006906206046126000100506006426C26B060800000000000000000d5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A83212802A82\n\t080880282A82402A80082A83003204A82282A82803282A82A80002002A80282A02A92A9000000000000000000000FFF54000\n\t00001423541541543141541543423543040000C49440B48B48550308C40450D30D405508405504D0C40D10C40900C408A8A3\n\t0550000900100CC0A00550D50800000000000000000000FF0E58000800000400400600404000400404400400000110000180\n\t0049001080420501001090801001801021011001001001041001000001001001001001001000000000000000000000000000\n\tFFED2A0008000800AA0AA0AA0800AA0AA0800AA00000002202800080002A80202002002882A02A84002A8A202200A82300000035c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF1C55000000\n\t000800800000884800800800800800800000200200A0020028024122020020A200221000200A002442082002402152002002\n\t002400002002102002802002000000000000000000FF72D70000004AA0AA0AA0AA1000AA0AA0902AA0AA00004002A8A10200\n\tAA82410210802882012A8400AA80302200883202A80102002A82A80000002A85800102A82A8800000000000000000000FFFE\n\tB700080040800000040002040040000800003000001000880000010010200910800000108000030008001080200802500882\n\t00101001000003208008041000000000000000000000000000FF81370000000AA0AA0AA0AA0284AA0AA0A00AA0AA0000029200b5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010010010600\n\t01001001001029001000000000000000000000FF105D400000400C00C00400800C00C02D10C40C10812101310300B1435430\n\tCB50308251330320B2814530A2222312402013402433403003002801003123083003103002000000000000000000FF257500\n\t0000021801800001801849801823805805020004602408420E00600400E22402600E02601000401409600600612610610610\n\t648600600040600600E0AE006006000000000000000000FFDEBF0000002014014004012502014012320012010000AC880414\n\t4928004154880834840808804800004C84910800810801150801000004804800804C34C290040040000000000000000000000075c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (041010015030\n\t00003161000080000202000202C60A00C04900C0110020148108040400208108000100000000000000000000FFC38A000000\n\t020000000000001820040110082005020002C42812001020000010840002E02C4504002140A8130006400040280040200100\n\t000000000100008080080004000000000000000000FF6E6B0000000010008240048228088008208000008480002440102022\n\t0324820024782422920824481B224210200A00209A00249A0C2300006000312162082000410002000040000000000000FF1C\n\tC74008004004004404000444004424025204090021181491649281081629201090081041101081101400200280000001000200f5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (CC0000000018\n\t0182000180400384380008108980000064060040040162040040C049600201604000C40600220008200A20408242A0440560\n\t0004608600E00C20C006000020000000000000FF80160008000018018180018038038018130410CD84400061D010A0040061\n\t5240408004060668658004008A146000246304104456202004006202006406404004004006000000000000000000FFDA9B00\n\t000000180180400580180180180300100190805260000102141060000844080000960860000800B200612640642600C00608\n\t6106087490116026004106004086000000000000000000FFACDA00080000000002000000000004201012004409404A000800000dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (408E00600000\n\t6006000006006006000000000000000000FF7DB30000000000AB8000AB8C18AB841A018AAA0000002263124084060262202A\n\tE3662883A622600022622423608821640420644220E20A0060002AE2AE8362AA018004000000000000000000FFFB7F000000\n\t200001800001831801901821800828000000E04220020640600000611600000E006840106104006426006044006212146106\n\t006800006006114006004806000000000000000000FF79BA00000000180180000180200182D90C001883800010608E0A60B4\n\t11610E00400002600211600001001610A00612A50A1340C00000400060000060064060004A0004000000000000000000FFE7008dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (14E002006000\n\t00600C097040102108006026006086114014114134006802006007006004104006000000000000000000FF55280000004011\n\t5580015591400B953900955555800024655248255643654255643051643404600452242844611050655611440E2264060064\n\t04556557556556555006000000000000000000FFA3210000000010AB8000AB88B8AB809C098AA88400002A62060860A62062\n\tAE2AE20E2AE22222600222A22432228E2A204A2260802242028060022AE2AE2C22AA242004000000000000000000FF628460\n\t00000010018000018218A1801C49800000000001600602E00608600E00608604600250601000600410622002E00602610009004dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000020180180\n\t000180382182182D801001800002E0060260040CE0360040A00260100960100A604610600008E00601400412404000680400\n\t6006002000002004000000000000000004FFA57D000000001001800001830095801A00801801800000600208A00600610200\n\t601600602444600000A10800C02602400630612440C500806404006006806000000004000000000000000004FF08C9000000\n\t0010AB8000AB88000188B8848AB0AB8000B862AA2022AE2062022AE20628E3840178002123002322882022AA42624E006048\n\t0070062AE2AE2AE2A82A8004000000000000000004FF4896000800401001800001800001903922801031800101604205201600cdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000006006\n\t004106006006000000000000000000FF94C20000000898AB8000AB8818AB8AB8A985192180002AE20604623C2AE00622C286\n\t28E2A02AE10022222220408E0042AE3260040041422AE0802AE2AE002002212184000000000000000000FF0C440000000018\n\t01800001831801801803801005800000602E00610400614E00400E00600000608401208200C00000C00608E42400C0220060\n\t0400600640A022102054000000000000000000FF235800000004580180000180580180180195309100000060864AE0040064\n\t0608402004601000644008600E1462265460060041143442880060040060060C2308052204000000000000000004FF082600002dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (860880840060\n\t000020000860062064000862CC00E02400601000208400200422400E006046000000000000000004FF4DB60000000A30AB80\n\t18AB88B8AB8AB8C18AB88C80002AE2A62162AE2AE3062AC30428E2882AA4081263162CE08E0565042AE2C40562082AA2042A\n\tA2AE32C20E08E2AE000000000000000004FF6039001000115155801955D1595595591088580180005564A620E44655604E44\n\t244E5565485524444524D615613043600042649452E4005560045565541144A6546416000000000000000000FFDE36800000\n\t001001801801801801801812801800800000401604600600605600605604604000200041204600644608604800601400604000adc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (041001801A01\n\tA04001801829025C0000000060C208200200210E0000C40061040024100000462360064C00AD006144006408006200006004\n\t10C4AE8AE006000000000000000000FFD98D000000015401801801830001801803201805000000601201200300200600600E\n\t00601080210024890C1044000104060060163260A0006004006006046006406006000000000000000004FF955B0000000910\n\tAB8018ABAC00AB8AB8810898E900002AE2023222AA2AA2262AA2062AE2202AA1000802040040AE4000002AE20450E1002AE0\n\t062AE2AE2040464462AE000000000000000004FFFE2700000002100180180182180180184380182D800000400E1061060062006dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00806A060029\n\t0E006006000000000000000000FF02A3800000001801805801E05E01849801C0180A850008640612448408E0060A600E28E0\n\t278060800440040A4011000006006404006000002000403006006096006006000000000000000000FFEA2E800000001C81C0\n\t3A01A01C01C01841D83D08804024E1362060570860060AE406067117046441004C0400400604846F40620C01F00000600000\n\tE006083006816006000000000000000000FF9966000000001481A01C01800201A01D05043821080020E04241300220222741\n\t4024006A0420200480008C40C02021001402608E00680000E005016224105806006006000000000000000000FF2DAE00080000edc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (012400E10E28\n\t020066661442400000641604620200600000400010401E002106446006000000000000000000FFDA4F000000000801801801\n\t800001801941041821808020600E02E2364060064002440164060200880CE51601E05E6460860A610000E000034000484046\n\t202026236006000000000000000000FFF274000000001A01881C21801801821D05095804800004E2C008000009028E10A08E\n\t5000820100000040AC30430704024C00610602649020A090002406006086116046500000000000000000FFF2CB8000000018\n\t018018018038018318054019448AA01265100CB34201024680220E3000D22263400040064A60000002042460060060000060001dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000040\n\t0000004400002200005201100880801300000D00400460104000000000300082460000400003500000001080000105403200\n\t00000000000000000000000000FF0916000000001801801801A0180182180100180080014464280500401101060A42545080\n\t0600000000200613620640604400608203600800C008004202006006016046280000000000000000FF94CA00000000180180\n\t1821E0180180380310B8048D200960024005100422060040040000162AE30811214400409004610408640200628042410000\n\t4002206046106006000000000000000000FF05510000000008019018018000018039610018418A2008610430608E02401603009dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (208A00A2AA2A\n\tA2AA000000000000000000FF959C00000000900000000002040040002400000800010000000300000800002A000000000008\n\t0201030000000000080080000080000000C88000201000004000000804000000000000000000FFFB110000000A80AA8AA8AA\n\t8C08AA8AA8810AA8888000C0A4024225124022AA24020028A2A218A2A032A4924E208A32A3022AA0022AA000222000222442\n\t1402AA2AA2AA000000000000000000FF9C870000000000000000002318000000100000000000006420400428400000000088\n\t006004044000100200200006080114000000000000000082100008008000000000000000000000000000FFC0728000000040005dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (28BB8348A000\n\t2022AA2AA08A222213AAA23A2AA00000A0000022020132AA2AA2AA000000000000000000FFD24D0008000012010012012004\n\t01401001001440000085012403404514C0040041340410112144C10140000004200084480041400040010080808010004040\n\t04005004000000000000000000FF25FC100000145D55D55D55915D55955911955B45800055654C50452CC44556016556556C\n\t5684C08850455655655645722655644755600004640012E556546557557556000000000000000000FF4EAB0000000AAAAA8A\n\tAAAAA8A8AA8AA8AC8AA88A800008200A1020020022AA29220228A2A202200022212210A08A2220022AA20A2AA000322000AB00ddc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000008\n\t420000011400006000003008400000404004898000105612885014000402000006A000186008000000000008001000040100\n\t8040000000000000000000FF78C600000004000020020000420040001000002A0001000120020128128000108000000008C0\n\t05100B00000002000000400000000000000002001000D04C0800801000000000000000000000FFB5C3100000014200000000\n\t03000000002000010000000000101100000000004200000400400400000000000000400909100000810000002C0000430000\n\t010000000000000000000000000000FF73B38000000808AA8AA8AAE808AACAA882EAA80080012AA202202202213AAA0022AA003dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (096006507006\n\t000000000000000000FFA0AD008080000000080000021001080001000600200000C28500400401800D824830029000D04888\n\t44C06DA010007A040800140800420C0400A080C084000000814044000000000000000000FFF67B00000A0001120900209008\n\t0082C90CA00884840102A0228AA50324B44A00A24200280200200008200200280201280250220204200A4820000128820120\n\t02483002000000000000000000FF188C00000000000000000000000000002020202000008000000000400808804800008004\n\tA0300001A30420130000540008000000008000020000800000080000800020000000000000000000FF56BA0000000000000000bdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020028402022\n\t02002802003022802802002002802000002002002002802026000000000000000000FF4FAB00800000000000000000000000\n\t000000000010008500C00001004000B02408300308102A41008900204008005408082082100050108004A000000000000000\n\t0000000000000000000000FF4E8E00000000000011800080081890480680090088000220220028DA29208200248A00200200\n\t203000201205A00201ADA220A3C201A462002201012112002402002002000000000000000000FF28F3000014000114310041\n\t901801955F55805945E200456044556347CC62D65175460064C704549010C2040CE2060560D6D0602614E816306000097104007dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801841801881\n\t88A001010840600400020411614441420604020609210008008800600E40C036046426006016006002006002046006026006\n\t000000000000000000FFEAFE0000000000000000000000000000000000000000000000000000000000000000006000000000\n\t000000000006000000006000000000000000000000000000000000000000000000000000FFDDE50000000000004000010000\n\t0000140000000040008000040000000000000000008060040000008048040000060000000060000000000000008000000000\n\t04000000000000000000000000FFC7F500008000000000000084080080080080080C8000202402080004882000001082002800fdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (470860060000\n\t00000000000000FF8E98000000028100302205801805811C298CA80D0443246086000443080EF8E187965060660C60000080\n\t1061600688481600680008605E006000A06282006002006046000000000000000000FF1F5800000005000020020180180180\n\t9851801A0320000069000061860294010C000EA060068060208040044060A080520600E003006906006000D8642A20600602\n\t6006000000000000000000FFFBFF000000000040000001901801809801801815000000601400400002600C0849164010C622\n\t34300500010168C014450611700610E006026000006932D06026906006000000000000000000FF97170000000000000020010003c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600889220219\n\t491604200025625871601708E09160E60F006002016046000000000000000000FF6F9A000000000002122001825801801801\n\t901008808204E08E08E00004245700FA06106082226231326836C4502008320200648000600602C000006086244103006006\n\t000000000000000000FFC3C2000000000000000001CC5811841A018818508003006124124004A2600208200685090A284A20\n\tC360A68248A82C25040360A3896007026009007883C26106056006000000000000000000FF1E220000000000400000018818\n\t41801881801C00808300600C804204806002022006020C82A545100C689601400E2501480C644200E10602400000600214400083c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01841801801C\n\t19808200608021561221180E0A608B006308894040022432665040010006156C8E46E5060C60040060120464874068060000\n\t00000000000000FF7F69000000000002000001801803801909911001C102017084C0400442684800100A4060451004800820\n\t82004016200006006024817006106000006800006102006006000000000000000000FF070800000000000000000180181180\n\t1841801A2180000868040040004068045040AA24E01400000400230280400040310E40600600602610608401600800780702\n\t6006000000000000000000FF2B56000000000162022005D018058519A1841A0484C168F64E04E440800187006026006842900043c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (700600000000\n\t0000000000FF4EAD000000004100000033803841801901901941E003826504214442206144444A0620654C08042008E08710\n\t714690610710705494E02E294021846146005802816006000000000000000000FF8C7D0000000000000000058C18818218D1\n\t88984180020060148080430360208100062461040082A000600E806930516840814404206307004004006004004202206006\n\t000000000000000000FF3CC9000000000000008001801801801825801E4188220060080040268022020CA082026410224000\n\t0220420140860A042E006114806006806000006203806002006006000000000000000000FF05E5000000000002008405B41B00c3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100004086110\n\t0868464000D6006946006045046144006006802004000000000000000000FF6D5C0000000001000A00118018038419019059\n\t418000336907416010D441022160042C680E884A28C0804404E026A262860868060AE81621600000741601600600A0440000\n\t00000000000000FF1DA8000000000000000045805841821801843001800120E000802006006856806C140860400020000431\n\t2202E006A3E22604608500600616600078620E04E002806026000000000000000000FF710C0000000000002A0001C01C0780\n\t3A05821801904209600682601E0A240A88A8AC02604146A00C322502016008047C16364044006086046004806C14066002000023c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180190180181\n\t0001620614650400420004240610620602444000240E00040640000600600600608600600000600200600600200400000000\n\t0000000000FF0EAC000000000000000001801801801801801801800000600600600000400600000000600600600000400600\n\t6000006004000006006006006004006004006006002004000000000000000000FF920E000000000000400001801801801C01\n\t8018018003006806006800004806004804006807006000805006006806806006007006806006006000006006006006002004\n\t000000000000000000FFDA58000000004000000201801801803801801A0180020064060464408040031220A680648603680400a3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF4281000000000000000001C01801801803941841AC0092640642E204104500D04456956D46B46A3400A90E250130\n\t0104A600004600600E046104006040006826206206000000000000000000FFDD0E0000000000000A0001821803AA3881821D\n\t018480AA601603600422400800883681680600680000220E4008060001060060060060860060000060000060068060040000\n\t00000000000000FF65B1000000000000100101921A01905D11A45805C040547127406034D54128C960C6446156A9000000A9\n\t460B0129130A120010C6006006006004446042006806002006000000000000000000FF944D000000000000040001801805850063c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (06808006A00D\n\t0400010200000E80600044600200600620E206000000000000000000FF003C000000000000000001801801E01E0180180180\n\t038460464061070014440030040000C680000030E24E00084011142400600080200600600000422200604600200600000000\n\t0000000000FF6E5A000000000000000001A01801801A01945A419400106C0600620290608452E2570A620622009100308444\n\t0891800086028842024246046080006106106007026044000000000000000000FF0B98000000000000000001801C01801801\n\t807803822000E0EEA0EBAA0062E48F638C2AE2AE2883205024E42A8AAE7A800805602084644600600000652610600605204400e3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (CD18018002A0\n\tF216CA6856256422C4C848D104A68A0C00A32824906908906806810D269404068C6C00842A2A286A0E826826000000000000\n\t000000FF8921000000000000000001821801401841C0588D8000026107816A0208008E90130000600E208088106484006200\n\t22752A02600A40A0AE00600040210200E027A86316000000000000000000FFA6F90000000000000000018018010018018018\n\t0180000060060060020070060000000060068000000020048060060060020000000020068060000020020060060020040000\n\t00000000000000FFB61C000000000000000101901801811813901901800200640612E0069100044028808080020C022101700013c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFACB9000000000000000091820040101820020000000280100800090C41500100011400E0040040414050000100064006\n\t700060042C10000000012000200103010E02D0000000000000000000FF110800000000000000000000000003028208260200\n\t01420001200001A88801408000016BA00106003301100000060A0100056000408820060010000001A8800850000000000000\n\t0000000000FF83AA04000000000004000190590300180980998180002062060B60660005020040C010004E2081900860040C\n\t620E20608600660E00020E08600000201A106006204506000000000000000000FF958D000000000000000281C81A832519130093c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (601610601600\n\t630E41602600600008640C006486006106000000000000000000FF3BA3040000000000040400F02C80C00E00C00828800084\n\t329208B842402D0A0822430822C324352994330341310341352302B0038C2912123009203102492003543252000000000000\n\t000000FF3F090000000000000002004002902002002442500000140480C00000820290300A00A808014808080404A0C00980\n\t910808808901110010800800400A80C00820000828000000000000000000FFACE30000000000000000008808008088009008\n\t08800200A11210A21200302A0B142A002C0206200000A2020020120020020220B20231C2902200122502002C0200200200000053c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8800022A8008\n\t0002900802482003802A82A0200420A20A202200880200002A83202A82A80200022A80280002A82A82A80000000000000000\n\t00FFD6C7000000000000000200C00A00A00A00D00C00800080288200284B02282290281280280202228000201280AC02C02C\n\t02802802802802C02900802C03022802802002000000000000000000FF20AE00000000000000020000140020000124D22300\n\t00004A25354000A0C08483484480081409080010890090084091094880091000000490CA00800904A9480480100000000000\n\t0000000000FFF775000000000000000011801831911801923901800050600640609600C00441610C01600480E00021600E0400d3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t7E6B0000000000000000AA4AA0AA0AA0AA08028800002A82400400400A00880A02A02A82502880880501102A82882200202A\n\t82292A82A82A80802A82082A82A02A92A8000000000000000000FF46C4000000000000000354354354354354332330000055\n\t0C08110C40C00400D20C40D10540411020450550C40950D10A50D50828D50D51510B00550B08D30550D50550000000000000\n\t000000FF06F10008000000004004000004004004004420440003001011491481000001010011001101821800200201001021\n\t111111001100001001001400000120001001000800000000000000000000FF45200008000000000000AA0AA0AA0AA0AA00000033c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9114A8800840\n\t800800804A00804140805025000004000000000000000000FFB3FD000000000000000000800800800800842A008000002082\n\t448202012202002102042002012100A02A0200200200200200211200200200210000281200250A0020020000000000000000\n\t00FFA1F80000000000000000AA2AA0AA0AA0AA0100AA00002A81080800304114406092202882002206011010C82A80882204\n\t002A82002A82A82A80012A92012A80102A8AA8000000000000000000FFD70000080000000000000000000000000000000200\n\t030000C02400801291100080080210091401031010000884000400800004000000000400030000400008000008000000000000b3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010092112010\n\t81109611001280221021001291001000048268231018200011011001001001001001101041009004000000000000000000FF\n\t6402400000000000002000C00C00800C00C54C00800110312321148345314348300214304340314100300A00240212300250\n\t200300300300304100B00300B003013002000000000000000000FFFC390000000000000000818D1841803801801801080043\n\t62060C000E00600603632E20E50E02420024C4A420E00E206086006546206016006000106006206206006006000000000000\n\t000000FF9EB30000000000002002000012002002004890010001004A208008893448D51208088008D488480812C024800A200073c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF073C\n\t000840000008000092000010042000022080024040004040028804052040603040608040001021048001040614003020E010\n\t0C0000100410540280308080000288000000000000000000FFE21B00000000000000000181004100180002200010002000C0\n\t0800040C002804E04810E2084400084443284040060081041062000080080000400000002802000000000000000000000000\n\t00FFBD970000000000000020808A080080280090880080000A200A02820A2120802C20021420C000602014A0124220024921\n\t021020AA21241201200008A00200A432002002000000000000000000FF49744008000000000000004004000004004004000000f3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020004002280\n\t04006000156140006006084356000000000000000000FFB3310000000000000000008018058018038C584080002860060400\n\t444062242064540A60042C640008420E00004010204021620210A24C00E00031610404E216004516000000000000000000FF\n\t431100080000000000012580188380180380992009C00862C60200343C610C18E2840187040A22200540020004B800601400\n\t42160460A412641000E004026006024006000000000000000000FFCA3F000020000008000048801909825801811800140000\n\t650420050401601405608420004400204A40408220810642E102082006006104046002026406506106044006000000000000000bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600002604\n\tE0060060A604604632608028600408402001620E0000010C8006006400006002006006026806000000000000000000FFC7DD\n\t2000000000000000AB8AB88A0AA0AB8AB8AB00002AE2AC2A82A40062262161C22882AE4CE0402B63443322882261060AA402\n\t0022AE2AE0000460062AE2AE516106000000000000000000FFEFC40000000000000000008018010010018018010000006004\n\t00000620610E006042000007026C8000002C00204600E44E404152882006006A8020640E00600642E0060000000000000000\n\t00FFA18700000000000000000180182080080180180080000060060000141360040D621402600420604000C0861100060821008bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF5F9E0008\n\t00000000000001801805001001001801800000600600101450611404640800600480810000400000400610E4160061140440\n\t06006900316092006006046806000000000000000000FF5FA600000000000000015595595515515515595500005565545504\n\t842864A434E00051628400041404C5504445104C60A45504CE4065565560844D64D6556556296556000000000000000000FF\n\t5A4F0000000000000000AB8AB8A80AA0AB8AB8AB80002AE2AE2A82A404E2263060062CE2AE1062003262142244AE2220464A\n\tE0205102AE2AE4000062222AE2AE00622E000000000000000000FF5974400000000000000000801801001001801801800000004bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (63542CC00E00\n\t600000628200600610E006000000000000000000FF9A8B000000000000000000801800000001801801800000600400000212\n\t601412421000600D2002004A000610222008610E400004084006006804086002006006016006000000000000000000FF1FB1\n\t000000000000000001801800000001001801800000600600002420E00640604400612602409000400001600600E224006154\n\t044006006280016152006006486006000000000000000000FFDE280000000000000000AA8AB8AA0AA0AB0AB8AB80002AE2AC\n\t2A8A9E0062B600E4942AE21709D00000C2A82360882220040A820620E2AE2AF0042262062AE2AE027AAE000000000000000000cbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000006006\n\t0060260060000240044860C4046226516046004116050006006000006406006006004006000000000000000000FF281D0000\n\t000000000000AB8AB88A0CA0898AB80980002AE0140000A02AE2062AE2A428E24620200230022222608E2440060AE1040042\n\t262AE0022AE00A2AE2AE2262AE000000000000000000FF11B600000000000000000080180000004180180180000065040000\n\t020060A600400C00610600204408000200600000C416000004004106006004006022006006006006000000000000000000FF\n\tA6D70000000000000000018018200200038018C5800000603400020800601400600002603413000005609610A2460C614620002bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (66CA00000000\n\t0000001800001802004043801801800200602600621200614000608800600400600200000000A00000650600000600008200\n\t4006006046006006004006000000000000000000FF6582000000000000001A018AB8822C00AB8AB8CB80002AE2AE0062282A\n\tE2AC2AE2842AE2AC20600C02E20428208E00650E2AC2462802AA2AC0002AE1062AE2AE2AC2AE000000000000000000FF9E4C\n\t001000000000001D5415593051011195594D80005564860060A255641255644255649054C02425654E52635051603655044E\n\t4D045255600455650E556556554556000000000000000000FF764480000000000000190980181000C001801801800200600400abc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00080602E004\n\t8361070278A6824006000000000000000000FF96F00008000000000018318018A00040018018418001006806006004006000\n\t0061100468041260060540560CC0260C414640414F104006006002006006006006004006000000000000000000FFFEA80000\n\t00000000001D02201C04100401801805800200600400601600600600600600600000E0110849060060004024120040060300\n\t0200600400648E006006005006000000000000000000FF1D960000000000000018458AB8480280AB8AB88980022AE2AC0063\n\tA42AE2AA2AE23228E2A831600420421621628E04A0060AC2062042AE2AE0002AE0762AE2AE2AC2AE000000000000000000FF006bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (342462120080\n\t5244804AC8620000000C42A1000B208404C846002002226008026016526AA6046006000000000000000000FF2A2980000000\n\t00400008804418000000418018018001A2E00600708602644E007A4E2264A200440180602608C08002C00601411600F80300\n\t4010506016206006006006000000000000000000FF4CE4800000000020000C81C01C205084018059059800A2E9540B649459\n\tE026216206106A8206408100120400401E70400204428E80700240600128E006106C0701F006000000000000000000FF73C1\n\t000000000000011C01801820608481C01C0180000072070A40450060044A608400F00D30608400440E42420000432600524600ebc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t001120001803009001883803800040600400602408628008602010620604428000413008000800030A084000008008126400\n\t136006016006006016000000000000000000FF80FB000000000000001281861809501003001801888020E5C4086684206008\n\t14638018E0262240280042403004262204C202408001420009E02000E30600600608600E000000000000000000FFBFAD0000\n\t00000000041C00001800020201A09C81844000744F22601702602224000A04090200600025008803250608A00400C0061020\n\t834043081060072AE506006006400040000000000000FF9084800000000000011801C018002000C180590580000060140170001bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801000000000\n\t00000000000000000000000000000000FF749580000000000000003000020040000A00000000000000300A02080000100061\n\t000260100880000001100080460200D0006080010048048480000000000000010000000000000000000000FF170200000000\n\t0000040200041C01441003009801854000E08C10210C0060244000140501264042A02344000000A64B000E00C08008048621\n\t60C00060060A6086106006200020000000000000FF33FE00000000000000042180180B01100188390588000064442424444C\n\t62940C03440004060040080040404B0210000406124000014014046010026206406406006006000000000000000000FF29F0009bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A28A28A2222A\n\tA2A220200002204228208A3022CA2AA2A22AA0221320802AA2AA2AA2AA2A22AA000000000000000000FF3EF5000000000000\n\t00842220022000000040000000010000000410010003200000A00001000000008800C08082200092200000100A4240800001\n\t000001000000001004000000000000000000FF18E90000000000000CEA448AA8AACAA9208AA8AA80002AA2421020A22AA240\n\t2C820028A2B227200050A30223248A29A2002AA23A2220026024002AA2AA2AA2AA2A02AA000000000000000000FF28CB0000\n\t0000000004010380000180190100000000000001042080040001400460480060040000202C40241042060040000040001042005bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000888\n\t108AACA88888AA8AACAA80002AA2AA212223AAA00228A00228A2022AA00000A0122622AA24A00A0AA2AB0120022AA0032AB2\n\tAB2AB2AA2AA2AA000000000000000000FFF4AF00080000000000050840120040000040100100010045084009408040040041\n\t0C00000008004101440D04004002100400000000431080000100400500480400D004000000000000000000FFC4C610000000\n\t0000125C81D55915F33D55D55955800155755650755655601655441655744E55600924D20550611750608E5564C620411655\n\t6300556556556D56557556000000000000000000FFE1A50000000000000888008AA8AA8AA84C8AA8AA80002AA0020322122A00dbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200000040\n\t0000020000000000000000000000FFEC5200000000000000000404005008001A000300200000080188080025014000004100\n\t08900C00000103D1800010018010000000400400000012000628C40400000000000000000000000000FF6F72000000000000\n\t02043040020004400000000000000000000B0080000088040350041000000000A01110888001020040200000500120000280\n\t801000800000000000000000000000000000FFFB551000000000000041020000042002002004000000801000000810000420\n\t0000000001480000080C0220000000100480000001050210000000000000000800000800000000000000000000FF5DDE8000003bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04454E006507\n\tC8E22A40E4C6204406C260060D430EA9681043400014702F444006006000000000000000000000FFB61C0800000000210010\n\t0020000020522510B0004220A800046340D4A04605D94A002E00C0880B881202010EC020090011CA5A000240880040018044\n\t00004804044000000000000000000000FF825B1080320048C0C8095090C9108408808308D0952010A08220208A08352200A3\n\t02822422402000493002002802A2300202A48240A008A02000123002020002002000000000000000000000FF255700000000\n\t000020000020004020400010220000000000000080400000004C084880080001052B8008404202000000082800081000008500bbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080080080080\n\t0808800829000900A00000280200B01001408000080204200200200082201200600280200A082083222000002AA800200228\n\t6202000000000000000000000000FFB1501000000000400000000004000000040102002420400001220884200C3000081050\n\t0111040548010AA0110820080540800408000310800800000000000000000000000000000000000000FF173C000000000800\n\t818804858C40800A02804800800090300200A80A04280A10244A00200211B821182002642992812AA204208A0020000022A0\n\t00247A0C2802002000000000000000000000FF757D1100540059419019519159518C1B0984D95192C01171071041075040C6007bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (046947006007\n\t08E080000000000000000000FF0D1008000008180180180180100100180300B80400A022401600A40C228004000006000054\n\t2061000062061021062260020804A620600010200020E006120006004000000000000000000000FF72090000000000000000\n\t0000000000000000000000000000000000000000000060000060000000000000000000060000000000000000000000000000\n\t00000000000000000000000000000000FFF5D300000000100000000100000000040000040000000000000000000008000060\n\t00806004004800004800800806000004804000001001000000000000004000000000000000000000000000FF52410000000000fbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A408004C4123\n\t2008650651600E0008A400234200E00108A2000060A5100006114100000000000000000000FF9754000000081821A4184180\n\t1001B5180510B815A0800641060CF00A26E09400600E206014076008B3A106804086287202184408A0600054200232E40402\n\t0016104000000000000000000000FFCA4D000000201801801805A01001A05A63001801A02000600620602690740C00E81600\n\t600408600200002E00600002604000C002886000012002006000000006004000000000000000000000FFF0F7010000001841\n\tC01801801209001801021811100008680648202000015441014748080492F430D528CEA1081010650400880E0960010024000007c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (809800023A21\n\t851A251458750000042446401600A406070A7484A0E144106868142006004146A18CCC2560B8146700146001506004006087\n\t126000000000000000000000FF340B0000000018018098C8221809901821801E01200180280E909001401086026004246204\n\tC4F29000188600E208000114506000206000206048006304286056004000200000000000000000FFBEF30000000038018019\n\t10201B11803801425801848000243730800C0108A6000425820344282A80042C4600CAB004044602A0032C61010020284069\n\t0548E026006000200000000000000000FF3787090000001801801802001811805A0104180BA80048300E00020510022640100087c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (160040060000\n\t00000000000000000000FF91A8000000001801809804021861821A10081809A0801025260040028A630F0868350160400002\n\t911102070A4000000416710026116000202004A07086984037000000000000000000000000FF172200000040180180980000\n\t1801821D04201809810000200608540408040C086426047B0720C14400029400A006081006005054846200C0000440608684\n\t4047012000000000000000000000FF45EA000000003E01841800205AC1805800001801828000288602400800904C8868C601\n\t680880400400E426002000A200060002A6006000000004806006014086842000000000000000000000FFAF870000000018010047c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (64A043000560\n\t104E030088DC680611CC1410E82010400D00601702400700E020000000000000000000FFA822000000081801841822201881\n\t85181174180180002078560164420274342262B6C47A06A00000886B2531122740652FC240942A740041640410602E004006\n\t342100000000000000000000FF3F61000000001801C01802001A11801815011A41800410630701704220F0C4056216046146\n\t0200300AE094800A08807416044104036A0000400410680602400F012000000000000000000000FF3134000000001801A018\n\t00221A09801800089821A20020202600C02622E0264568840060068404064400260C4416440006025B04006001902002086000c7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00201A018418\n\t01041A012000106006806406045002006082846440024004484012A0C1015042144100063162060060140060060061060060\n\t40000000000000000000FF1039000000205804241880081B0591585050580504402060A8896906C0681720F032406916C8C2\n\t1400852200443600408602108604704648E40409612E2060060A6080000000000000000000FFB17A00000000380181984401\n\t1811801A01803A03802005600688284600644604640400600808820C00E00614000600684600401400600108600000E88624\n\t4086416000000000000000000000FFF12C00000000180380188028980B883921201A01A6004AE08610248720600640E905010027c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600000\n\t0000000000000000FF67C5000000001800001800001801880101809811815040603400E08E01604A2264042263004144C000\n\t20A4004406000086000006006406006004106006206006006000000000000000000000FF80E5000000001800001800001801\n\t8018018018010000006006006002004000006000006006004000004000004000006004000006006006004000006006006006\n\t006000000000000000000000FF70340000000018004018000018018018018018010010006002006802806004006000006806\n\t804000800000004006007004000006006006804004006806006007006000000000000000000000FF9D3C000000301800001800a7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A66B906A296\n\t01626685628C0873AE0C6006206540806486786006006000000000000000000000FF17F10000000018802018002010018142\n\t0181184115008564461469201261541564109165063148A500AC20B46A0828224601140741600600600C02610E8060060860\n\t08000000000000000000FFA60B000000001828019A224014418202118038091CA0116202B27024106B0020686000684880C8\n\t04202000926006A020061000060062060060050A601E906006006000000000000000000000FFF959000000001C4A40184408\n\t1811840003905943800104650444644342640608E09480E0100A400822AC1422504040A41700032E086006406000447486000067c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C7190180510\n\t1901040069E8021060048060028080068000060802A282605770422E29A20480600600700680400040660E00600600600000\n\t0000000000000000FF47D6000000001800001800000801801801001E01930000701000E8054068430C085700008200600100\n\tA84600400084200500FC06406007006028807106206006086008000000000000000000FFC0AC000000001900001800000A01\n\t80D80000982000000462420A614812789600640632E200A0E00800640F0AE000006024806106836006004280826806086006\n\t006000000000000000000000FF930F000000001C0000180400084180188800982280005A60B801E2986AE0AE0AF2CE66F2A200e7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (806000000000\n\t000000000000FF90730200002A192052BA40245D15A09A0BC01AA080001068A000632080F025100242810C0350EC008D6402\n\tC268C8822806432286006A86C568004060564A680E206100000000000000000000FFE868000000001800001C001018019038\n\t418C1809800020601521601748609000E01620612882011020200600600100E2A600402E08600E08604008EB060162860860\n\t00000000000000000000FFE6B2000000001800001800001A01E01801E0180180000060058068020060000068060078028000\n\t00002806006006006006004006006806006000006007807806006000000000000000000000FF9BE1000000001804001802100017c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000836060024\n\t620020A204290308300255A010082042007003082080000000000000000000FFD6A800000004190010205598001018211102\n\t002400000804014081084060600160404060A404C08821404104000601040110C0A000000828002000818002810000000000\n\t0000000000000000FF20790000000000000000000260000000000800000000840100200A0028618050640000600800020006\n\t0010330096400241000800800000000402000000080000200000000000000000000000FF894B000000121800015800001981\n\t801821801818000020600080605400E00408882220020633000000680240600616A006A3260E016086026000806A06B060060097c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (881909901889\n\t800008629600600652604600405400604600440040E48C896006006116D342060160061161108060A6106486006000000000\n\t000000000000FFE7EE000000482880414C14C10C00C00C40C00C248000023002542D5300348B29250320340B4B31290C2023\n\t44342B2CB44200212220200324340100320B002002202000000000000000000000FF65040200002042A02A022021020A2082\n\t083002C000009008381414A0900C1880081C800C00880C50D08900000808800910400840C00200800900A00C38800E88C000\n\t00000000000000000000FF5B21000000080800008800800800800842800900800080208300300404200000130200A05240210057c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF41B20008000AA0AA0AA0880880A00AA0042AA0A000000002A82302402202002E83802C82402A0000208D288A80\n\t883200402200102A80001100002A82204102A8810000000000000000000000FF9895000000200800200A40A00C10C0088480\n\t0A10800091280310200290B04300282282288280282108208240280280B002912802002002C0280080288280A8022A200000\n\t0000000000000000FF71B00000002004004012022242034004504012020000A450008140CD00109500480C80083081480084\n\t0C04000C40880D48004CD5004004950C00004814CA5004814000000000000000000000FF388200000004180010182190589100d7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80410D000001\n\t0200001000000000000000001040020000220000000000000000000000FF92170000000AA0AA0AA08C0AA0AA0AA0880AA090\n\t00003202A92400882282A82892A82A80082200001202A8300088A20008088A092A80002282002A82C90802A8341000000000\n\t000000000000FFEEB700000035415435431033433435409015430C0000A40D50CC0400CB0C10D10C00D10890D50820A41008\n\t400D50C40890D50520550000A40C00D50510900D51100000000000000000000000FF85530008004004004004004004004006\n\t420004400001001000100C211010010400010011210890104010010490200811212000A000100110100100100020800101000037c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (430012000000\n\t80100000410C8090050040008010308A091004480492C800880D4CB20104000800800C00000C44CA080080C8000000000000\n\t00000000FF694C000000000800000840A00800800800A008D080001020028122221420020028020420820020008820020020\n\t0200200201203200000015200080211200A002042000000000000000000000FF52090000000AA0AA0AA0C80AA0AA0AA0884A\n\tA00600002382A82B18002002A82A82A82886002081012182A82006A8238400040A00AA80002000002A80000412A828000000\n\t0000000000000000FF167500080000000000002400000000022040002000000880000010900001400000280002000000001000b7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF35D240080000040040804858048040040140403000C108108100128942122111168000100124132900100504421100\n\t1001001001001001009001009019001001001000000000000000000000FFFA76400000000C00450800C42C84C14C00C00820\n\t80810C353300300302343302314214B31310343300320300240300320300302301100150300308B003103023013000000000\n\t000000000000FF6F2D00008000980000380980181190190D001801820020600610E4AE09608620400620600620E00034C084\n\t51400608E00600E10608000800E00000608600E006006000000000000000000000FF90D700000020040020020200040140120077c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (14220E40E006\n\t0862064800000D640002C046104004006000000000000000000000FF9C4A0008000000000200540C00000480000001100CC0\n\t0504A00A00001562001061203060C00204480102000080A61000300001200200000900A04500201082000000000000000000\n\t00000000FF555300000000180002102184500209209000400804004404101080403061083160242CE10C00C0804945005080\n\t061104000000A009001000400010008010C040008000000000000000000000FF19C400008000880000680080080C80090680\n\t0800802000203201040440A1400204120026021B200002200202240A05210001A0020001002C20000024020020020020000100f7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (182C80000040\n\t8600408A00001004600800633620604000605602E20644208600E00600000010200000600600600400600000000000000000\n\t0000FF9A9200000000100002180184388D813903809880090002420644E08620420002600010630E0CE00000021600E14000\n\t200A00E00602008000610000620600E404006040008000000000000000FF2DE100080000100200180580388988382882F810\n\t800039400420008001001C33810000800E20601000618A0A2008346742086346298000006240404006006184006020000000\n\t000000000000FF7D8000000000000400382990180192185084180002202041500802040A4144200450210026406220008002000fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFD763400000000000001801001801803E01001801000000608000380200228600788002609230A08001682E006200144000\n\t054006000000006008004007806006006000000000000000000000FFD1BB0000000AB0000AB8AA0C38AB88F8810AB9408000\n\t2AE14E2AC3142AE2222882002E81024B24002202062160881840042042AE2A82A86620002AC2AE2AE2AE2AE0000000000000\n\t00000000FFB83D20000000000000180101180180184500190180000062420040240020820000C000000200AA001080868860\n\t260144500C400600000000E820004006006006006000000000000000000000FFCD8100000000100000180082180182181180008fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (882002AA3242\n\tAE2A82A82AB0002AE2AEAAC2AE2AE000000000000000000000FF379100080000180000000100400180182380180300040064\n\t1200404400608000600E00604404400001291110002600C4160A600600000001600000400600200600700000000000000000\n\t0000FFD857000000154800154155114155951949955945000055644A55435055200C51644E51642402401414250155015040\n\tC552406556550550556004554556550556556000000000000000000000FF19FC0000000AB0000AB8AA4918AB8A9C890AB808\n\t80002AE0042AB2032AE24E2AE34028E2121020402A622622628E4201202142AE2A82A80828402AC2AF2AE2AE2AE000000000004fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800010610243\n\t40420060040065560260040140204821200080060960860460060000000020C000E00614E00E006000000000000000000000\n\tFF55620000000008000000000000018418C180184980040062D200410A80202000603600633420410814202080002008E006\n\t00E006000000002810006006006006006800000000000000000000FF92770000000018000000000240018018058018040004\n\t0060060044440062020260040260000080000021140042060440020840060000000020000060060060060060000000000000\n\t00000000FFE1390000000AA8000AA0AA2C80AB88BA0D8AB89000002AE0062AC8002AA0CE2CE28028E0000A100060BA042AC000cfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF9F\n\tC2800000021801800150001801801821801883000000411608E00600644600610202604C00C00040400E0062060160360040\n\t06006006006000006006006006004006000000000000000000FFD89D0000000AB8000A80A80A80AB8AB88F8AB98000002262\n\t320863062AE2862AE00428E2A02A000002220A22208E2262262C42AE0000002AA2002262AE0063262AE00000000000000000\n\t0000FF63B1000000000800000000000001801821801821000000E00A00608E00203200600600601000030400A00210222000\n\t600E014006000000002004086006406086006000000000000000000000FFFAED000000001800002002004001801801801813002fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E4062AC2AE00\n\t600644A2102AE2AE3562AE2AC006000000000000000000FF844C00000000380180482400280180182180180180000160260C\n\t60020001000060000060040080000480060244000061160860060060060044400A600628E006004006000000000000000000\n\tFF12890000000898018AC0040A88AB8AB8958AB85180002AE2262060920AE0882AE22828E3042C45080C428630C0AE2A6086\n\t2AE2AE0060060964802AE2AE2062AE2AC006000000000000000000FF4396001000551801950B101519559559119558350000\n\t4C648640E44E5504365364D253654C5463403064C8516130556446408556006006554106416556046456554006000000000000afc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006887006050\n\t20000000621442728C82E00080640600600000600E00F10F006006000004006407807007006006000000000000000000FFFB\n\tAE00080000380180200200400180182A801825800200623608E00440649002655400702414600C4860201340064060CE0060\n\t0600600608008000600610E806004006000000000000000000FFCB97000000531C01800B00000801C01800C0181100000040\n\t0604652000000600600400610C00E08000E108006240126C0680000680600644200880600604600600600600000000000000\n\t0000FFCD420000002058018A82280AD8AB8AB8808AB88180002AE08624644C4AE02628E0042AE20420620003624024608E00006fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFE23980\n\t0000001821815004001A01801C01011885008001408608643405031644844A2312C600802028C24200601000640600C00600\n\t6000002000006206006006006006000000000000000000FFF58F800000001881803C00001841801901109801004000E04614\n\t600200040E026006006027200101A9610813610824E045800006007806406001847006006106004006000000000000000000\n\tFF1167800000403C01C01204001801C0182140780100201E742661E5021561665161C60170072000C08040C20060E63A7424\n\t80008E80660620600113E007046886004006000000000000000000FFBC9C000000403841E10800000401805C20C01883810300efc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (21612E406092\n\t2020002A6002086506106106000000000000000000FF4D9F000002001801839A030018238418C5801801082002602601608E\n\t00E00000602600608820000800001000E02001600000E00E206088202040006000006216086006000000000000000000FFDB\n\tD60000000099818018010A18C1825923901800820008E60626E3025200A83060062A603004022020029215608621E01A0062\n\t060060020A20001A600204600E004086000000000000000000FF7362000000401803C03A000038118018012D593500810060\n\t0F00602450600614000A00020100010005004E4C60061065444050C691600000242040682690E88680600610000000000000001fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000804060\n\t1000610004604C0140002040C40000060005140100000004800100C0000000000000504000000000000000000000FF61A080\n\t000000000011060022C000000000000012000000000000002802612004602800630028023015041034840600004002000000\n\t00485404000004C8000000010000000000000000000000FFBAA1000000201801A01C01405891801801801810050008402642\n\t64043080100000125200200002880004062AE0061061320064060960000C220000602200E006006006080000000000000000\n\tFF26540000046098858450050A1843801881953945882004E2160060C80461202C002200030E200040448142006140406404009fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF3C28000000\n\t0AA8AAA8C8AA8C8AAACAA8888AA90880003022AA2AA2222AA2AA2AA2222AA28220A0200A23024C228A2AA10A2022AA2AA12B\n\t0AA0202AACC22AA2AA0822AA000000000000000000FF184900000040000000420045200000004240002C0002000000000014\n\t02008000100C0010290A0001200128000240000300021000000100088080000001004000800000000000000000000000FF2D\n\t090000000AA8AA8628AA8850AA8AA88E8AA80480020A22AA2AA31008A20028820228A0521620004020520020AA2AA4022C22\n\tAA2AA0024021022AA0122AA2AA4622AE000000000000000000FF1F4B00000020180020180180180000002000012000004080005fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010000201100\n\t91000008000800000000000000000000000000FFF3DC9000000AA8AAEA8888808CAACAA8888AA80A80022AA2ABAAA00A2AA2\n\t8228A30A28A0030220000020022AA08BAAA0420222AB2AA2922024002AA2232AB2AA2AA2AA000000000000000000FF7D2100\n\t0800400001200400401201201020401040000205000400400400000400511400100500020881400000804000402009080400\n\t4400804200004801004004810004000000000000000000FFB86F000000555D55951D55D01955955911D55881800055755655\n\t654631643455444455750441644914D40655611655701651755655644644401155654E55655755755600000000000000000000dfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000001A0020\n\t10000404088902400808000301001080A0000040A08000000000000000000040020200000000000000000000FF0499010000\n\t0000000040040040003B81862802002040400460008000001440010009008480060000500840240140A21300280010420000\n\t180100000300120200000400000000000000000000FFD0EA0000004002000022204A42004000022000800000000800000040\n\t000040020000020300280048150410000400000040300800000010020400000100800001000800000000000000000000FF03\n\t5308000000000000000400000000002000004000080000000005000000100000C00008488104012010C0000040000D100100003fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F10000000818\n\t0191580180194594D135CD581188825168CE15641650655784401641650E49600010680640E01645710E28442602D2000162\n\t00006257026226006006000000000000000000FFFDE702002000002000000002021840100108140102800CC00402C0848480\n\t8C685281B4886C2486690200002C050938844008400040480010422808002402408C44C404000000000000000000FFB03500\n\t000010080091280080094280481082480080004020030C340A3220CB02200230202320200080200280221200281280240280\n\t240081240000204A802002202002000000000000000000FF1F3F00000000000000000000001000064000801031001318880000bfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000000080\n\t0000000000001000000000000000000000FF41BA000000000800800800800810A2888480080084000522AA00500080200140\n\t080210A20210200080308302201210A80208200220A000080080002084084102012206000000000000000000FF54CB040040\n\t00014010000000000020000010020000405000000308840082B008821020004C048A30B00000A90000800000000008804800\n\t004230820000000008000000000000000000000000FF3B47010000000880884804844A00920C00C18818810202208A802803\n\t80200200310A08298248200005A0C280A74246211B80200206A00086200012204205A602003002000000000000000000FF57007fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (826104200886\n\t00005711644032408A04E05080604304600600420080028800688CC06806006006000000000000000000FF8AE10000000018\n\t0180180180380190180180182180001062960441240000240304464002060061000120060064060061020060A60000000020\n\t0024E244004206006006000000000000000000FF61C900000000000000000000000000000000000000000000000000000060\n\t00006000006000000002000000000006000000000000000000000000000000000000000000000000000000000000FFA98300\n\t000000100100100100100100020020040000000010000000000068000060008060000048000040040000070000008040010000ffc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000188180\n\t1840801800281801C158498000006046C04A0400688220088840000611240128701602840EA0100700214400040000629004\n\t594BA05406006106000000000000000000FFC19300000004180188100080330B219811801C01A0000A63C7826CB22B082042\n\tE2260862860068A800A0028060B61872E23860060D1100600000A1E050082006406016000000000000000000FF77B6000000\n\t001901801A00801A01407861985891800100700E40F00E51F00000601610692E00681082088100610056641A526006960000\n\t400000806200106186006106000000000000000000FFD319000000001801901841801815811801A09901C00002602601420800002040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000806006\n\t046506007916000000000000000000FF95160000000410218611AA001000281AB3881D0180024062166CE0020460860768C8\n\t81619644280800601A2C008680028626340C206E28406003016102801006406046000000000000000000FFD3810000000018\n\t238018080019200898C1C01803808212E3261060228000062064082062060820CAA06080B0832000010E5021410071118260\n\t2000405200600602E006000000000000000000FF4505000000001005801800003842001C01801E858321CD68160240248200\n\t02008A20310C2ED420C24061220482408000170024A400400084602000610204148602E0A6000000000000000000FF96400000802040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0200640410E4\n\t2E2A0408084000010C06040446044000012080204101806202082086026006000000000000000000FF1E1900000000480180\n\t0D04820801C00809805809C00000611618400002023F00E0440CE90600024005C1A0000040C38216804240D0208008468418\n\t71F6002006486006000000000000000000FFBC46000000000801800C00800801800911A11809800088680680C824406CC040\n\tE004006806014082206848000006000002C86407807000084050006806006406086006000000000000000000FF1DFF000000\n\t000801800844804805800805881801842800680601440880808400608490684600480080484680000808042200681622A04000402040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004803880900\n\t0800A382088380D921C80000608E01E03620800A40682700646E38000074680101E00808F2070CE04020200000E084027006\n\t100186006006000000000000000000FF36FB100000244A01840210604801809C29821E01A130027C062270020070040B7C86\n\t44708600DB0002E12E086C27006032206227016480004230004002001046106116000080000000000000FF7C660000000008\n\t01800802000841A01D41811841800008610F0064A240108000644682610EA4C0AA00601700622040702A506006492000A040\n\t28004C16000C06226006000000000000000000FF9775000000000001800800820821A018218018C18010006006005514046000c02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000068070020\n\t07006006000000000000000000FFA6CE000000000001800210200001809840829A0180020464870260064100020061062060\n\t9050200440100600621000604200E04680680000E004006206006106006016000000000000000000FF308F0800000440058C\n\t0020204045841885803B21910300600EA9604E007897517416056C208425008B008C88E046936006D06D0EC16C008864A845\n\t6016802026906006000080000000000000FF9059000000200201800220100101801011D83881864100700688600E00608624\n\t604E00E20683000008604600600602641400608C062100E8600020E20A60001E006106000000000000000000FF58C500000000202040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (625632692010\n\t42045008268400201442B140480704E040C56004816006003006006006000000000000000000FF7CDB000000000001800800\n\t000811805801811885835008642648401455640200E10601621004C00000000641049620600200C00E006000006000446406\n\t002006006006000000000000000000FF46E30000000008018000000000018018000018018000006006006006000000006000\n\t006004000004004000006000006002002006006000004004006006006006006006000000000000000000FF61AB0000000008\n\t01800000000001A01801201801A010007006006006006004006000006804800000804004806006806002802806006000804000a02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018000088000\n\t00101821C11091822102E2CE6CE02E2AE22E2AE8EE4A702E02E7680A244C23009E2842AD2060064680202066000060038030\n\t46006406000000000000000000FF8FC6000000000801800800040A01A11AD08C1A059101286416114494C5055492ED001165\n\t5235000C42410EC400C00CE09201000680E04000E014006007026206087006000000000000000000FF403E00000000080180\n\t0A10000A01D0380198BA0BB88029601600440400604080720080608260005024403600002682600200800E00600010E40022\n\t6006006006006006000000000000000000FFA56A000000000041800800000805851B40A05851800042608605512500010E3400602040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000000200\n\t6006000000000000000000FF2A5F0000000000418008008008141D1901A81841A00000604604450480610B001006C1040490\n\t6A00A23028810C8E806086806006A0A00094C000016402022206006006000000000000000000FF321F000000600001E00800\n\t840800611881801C09800048645600400540080302010748028D007089002084021000016002016007000020006200006002\n\t002026086206000000000000000000FF3EA9000000000001800000800000001831C49003910000600632E2960304A608E446\n\t00E04634E0400022064080410A6017006806022000804010806002002006006806000000000000000000FFCB1B000000000000e02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000A802000\n\t0068000861064160260020A62060002A6400326024004000806006000000000000000000FFCAB7000000280B41A80A8CA82A\n\tC1851D05A95A939400826CAE224CA482F025300A00808C4A082C30A86540906800806912A92A2ECC60008C6A80D06B348049\n\t30227246000000000000000000FF5A0C000000000801800400808009081829801A01C00250600601780608628800E0810860\n\t8220E00002F0002460492C402400210600A22040601002600092020209600E000000000000000000FF279200000000080180\n\t0000800001001801801801A0060060060068060008000060000078020060000068008060060040000020060000008060000000102040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08808008408C\n\t0808088C00920010310B0000C000202010010000200204224040200200200208218220210210204000210008249205240A00\n\t2426000000000000000000FF351B0000000018018019418C1801800280004000000028000040101017E11000E40008EC0021\n\t81000E4484000066060400080000C640008000080002005A1200400040000000000000000000FF0F50000000000000000010\n\t00812060803400208400014002308112000066482072000060E000040810123001000E000008449208088020410281010100\n\t0000001A8000000000000000000000FF59E60000000009A584080E802881801900841909800000604622400400008449008000902040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A00000804004\n\t000000000000000000FFF09F000000001801801885821801851801803801804080644640641610650E004004106006004400\n\t43600440613642600640600608602040600000E106226A16086826000000000000000000FF20BE000000440C84C44C50C00C\n\tA0A04D0CF209048C0028208A80A14322B02328A2C3203A230330A908240B03300300B503022083A5221110B48008340B10B0\n\t03403202000000000000000000FFF75A0000002C02002842002002084340025004020C4082148100C524C80800800840D002\n\t00884830A18800E60810A008008008000106101008008008088000B1200A08000000000000000000FF8F200000000008008000502040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010910012411\n\t41001401101080000C20101001001008001429021001001800000000000000000000FF16C40008000180AA16004000008220\n\t00AA0AA0AA00062A82A82102104882082882302882A82A08204800A8220088220128200210200000100000190220160AA8AA\n\t82A8000000000000000000FFA53E000000322A00A00B20A00A48900800A00A00800080280204A80AA0284304280A80280280\n\t2010A0300300AC0288300294208280280000280880290290A002002002000000000000000000FF6EDC00000020020031420A\n\t34C20004D2010002010000004804104944841105004884820000814800848A04900820810C81010854128000AB0800A3481000d02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04200820A200\n\t0000000001001000001040000050001000000000000020110408010400000030050040088000000001040001009000000800\n\t000000000000000000FFB27F0000000A80AA0A80C00A80A80002AA4AA0AA00002A82A92A80B00880082A82202A8AA8240030\n\t1104002A00A8230210A310010200002B00002A80001082A82A82A8000000000000000000FF0C910000003003542003103103\n\t420C01545545540000550551540500950D00D504C0D50D50D510108208A0D40930CD0A00D00C80C40800430808400D504005\n\t50D50550000000000000000000FFD01F0008004004004044104004040102000004000003001000800401200421000101000000302040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060060000\n\t00000000000000FF647A0000002022002002222002401012012012010005005004004844C008090449148400009408308492\n\t05114820810804090004A00804800810804810A44804805004000000000000000000FF03CD00000000080080480080080082\n\t2800800800800000200200250A00240200200200200200A000202002002202082012002CB21220021080000024A211200200\n\t2002000000000000000000FF2F5E0000000AC0AA0A808C0AE08A74C0AA0AA0AA00002A82A8AA90000E91A0289230288AA820\n\t00000800B82300882202E0B201104180002200012A81004002A82A82A8000000000000000000FF594E00080004200000A00200b02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A04008210208\n\t20820C202242204200200001000040200211A002002006000000000000000000FF4696400800000000000040000000400440\n\t400400008108108102D2C84094A1001020021081381028201009620010001001201081001001001001001601005001001000\n\t000000000000000000FFF58C400000020800800800800904D00C80C40C40810110B5034031020131334934324CB10B403028\n\t40340B0820420032134030C300300308900100308B003483043002000000000000000000FFD85D0800000038019038018458\n\t0180380590D801942040604405620E12600604408600622603600011604404430611612404600E0060C6200000406046016000702040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000418258018\n\t0980000060040040045084860485040044445460400140400802060060401040060163144884080060861060064060060800\n\t00000000000000FF482000080000000000000008008000C00210200210402002800000000361160264402060002000882400\n\t005102A62100900080802082201002100C8010240000200000000000000000000000FF504200000004180180180184580388\n\t01420A00000C200004244000002C641651629051643004400001422400442E01048800004800012051000040013400048002\n\t0000000000000000000000FF4A8408000000280088286084088084284080A830800020A0420001645024420200000120020400f02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (680600000000\n\t0000000000FFDACD00000000180101580004580000184584180180A000600008600240011600609000604C04200000410610\n\t64460464800160064020003000800060060960A6006006000000000000000000FF3C98000000001801043800001840001801\n\t90380580002062000060CE006006006000402004000280004000026020134410206126006044000000086016246006006006\n\t000000000000000000FF584700080000180102380190182001580180186190400061440046080460567880C4190224082210\n\t44C13E43211848432009400640608C2000004560E601601E006006080000000000000000FF3DAD000000001800001841841900082040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2B40062A428E\n\t08C28422E2AF4000020002002AE228B2E2A62AE2AE000000000000000000FF48880000000018000018000018000018038018\n\t01C0200060070068020002860060A600282C88810000420600C00000402C106007080006000000006080A0E0060060060000\n\t00000000000000FF82BE00000008D8AB0B58A80858820AB8898898AB80402AE2ACA043040A82062A82022A82862826002A44\n\t2822608860600C3242AE184000C000002AE3A02262162AE2AE000000000000000000FF916620000002380000180200984800\n\t1801803801A00400600404C12C00604600004200400601690001420000C006114026084006834004048C0000601200600E0000882040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B8018AB8AB80\n\t002AE2A82ACAA828808628E22228AA0624100438002C2266882AC40628C2AE2940002A94042AEA108462262AEAAE00000000\n\t0000000000FFE230000800009801821802011815801831815801800000600400C04C00608602600002712604080000615400\n\tE04604604E00400604A0040C8880007000006006006806000000000000000000FFA7F7200000155954955954155913955951\n\t9559558102556554554D50350056556414533506C064044480AC54615055408444C556426004D501045564428864D6557556\n\t000000000000000000FFDDFD0000000C18AB0818A80C18A00AB8838A18ABC0802AE2A9346A022CE22E28E34E28E21431208000482040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFB497000000001803801824001801801801801801805000650C00608220600600610000608E52E08010E0A444E026\n\t0CE006006006092112000202006228006006006006000000000000000000FF358700000000180080180000180180184B8018\n\t01A14000600400600204002C026094002126136C0402610410604000640E006006802002000A0400614220E0060060060000\n\t00000000000000FF0345000000001801801800001821801881801801801000600680400400620600600602601600010000E2\n\t04016006004146044006030000000100006010126096006006000000000000000000FF3B830000000AB8AA8AB8AA0AB8CB8A00c82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (044061501120\n\t0640E5544125540044065562C6552556552556000000000000000000FF1BAA8000000018C380180000180580100180180180\n\t0000605400640620600600604640400200040000200408600400200600600428A02600408000610600200600200600000000\n\t0000000000FF65A40000000AB8A98AB8800AB8AB8AB8AB8AB8AB80022AE0062162160CE2AE2AE20628E2040060000000040C\n\t408E2061062A62AE3602020000002AE0002AE2AE2AE2AE000000000000000000FF567D000000001800801810001801801801\n\t801801810200602614E04E02000400604A04202400020444040C0044000064AE01600600004200008400608000600600600600282040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8AA8AB81102A\n\tE1062A801808E2AE28E78608C2AC40000000205421208C2AA3BC2AE2AC0025860040002AE2362AA2AC2AA2AE000000000000\n\t000000FF4114000800001801801C00001801801001801001804200608400610200000600600C00004820420001202C08E400\n\t2262520A600400200400408400600E002006002006000000000000000000FFB96D0000000AB8098AB8AA0AB8A98AB0AB8AB8\n\tAB80502AE2042AE0A60AE2AE2AE00C0AC2A80AC0802B22842262CC2AE2222AE2AC02600E0044002AE2262AA2AE2AA2AE0000\n\t00000000000000FFEBD1000000355B55D55B54355D53955155955155810055642C526446510556536546550482150086540500a82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF8CCC000000401809C01C08401821C00005905244810588780801014009001600604C12C09000000120E08C45202C0061\n\t0E08703101202C406005006506106106027006000000000000000000FFEA1F000800001905801824001C01800001A0000081\n\t0000640800012420600604602C044000D2808010E0A412A44400600600600431600C00650000600E00700600680600000000\n\t0000000000FFF543000000401C11C01C1040180180020180080180200060A6000200040006006006204804000205442C0C00\n\t2004006004806000042426004004006086002005002006000000000000000000FF3FEC0000004ABA21AAB8804ABCAB8AA0AB00682040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000C41400000\n\t601302A10E2020AA00600601652610C046240000000000000000FF4D96800000001801801810001C00001801905C05908005\n\t60444884001004A010002640421600E0C08028000304842440D000682200E40E000000C06406082087000806000000000000\n\t000000FFBD1D800000001C01841800001C02001009821D018000026084406402040206126006004046082000005446002304\n\t004006416106004006006000256006006007004006000000000000000000FFFDB5800800401A09C21C00401A22001A09A01C\n\t01900109704416608242E14E03E186485426892159104A2620200444404720E006004406004000006086602C07000806000000e82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (811000006016\n\t01004051654010040400400240610822652610441450600010610000610E00E0500860044065062060464000000000000000\n\t00FF8A7D000000401849841ACC0018A004000180989008000060000060060862060060040041061460883160900840840660\n\t00006044012006002000486004266046144006000000000000000000FFF9C5000000081821821822201A0200880D86194902\n\t800061960060EE60808E0060940FC10E0860005BE1162042740860001A61B400206640C00025600400240426000600000000\n\t0000000000FF6AF9800000401C01C01C005218104430838018018003486C140084040060200802460043062360020024500300182040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tDEC6000000401A01A01801801801914000054000008000000400808802600604600800410000421010800C08000400000C00\n\t000C0284002001000000C4220004008000000000000000000000FF8806800000000000000600400400040000100042002000\n\t00A81200004060060060C00060280081000002800500061100C00000801000900800000004081000C00A0000000000000000\n\t000000FFA89D000000201A01A01C08501C0401590D851800030048628000048C0000100000C415421201600000600022C0C4\n\t016000046008042046202100006006014006016006020000000000000000FF3122000000481E11E018800418A8001801801800982040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00F4365572C4\n\t4D4556526401556D56B07D56557D56000000000000000000FFD05B0000000AA8AA8AA8AA8AA8A8C22AAA832A8A80202AA0CA\n\t22220228A28A28A2422AA28A2A2488C0A4C22222AA2AA3122AA2222020821120802AA08200202222A2AA0000000000000000\n\t00FF8ECB10800040020040040040020000000052002000408010401203480200000000002000800085100804490902002800\n\t80001008000000008100800000048001000004000000000000000000FFC9730000000AA8AA8AA8AAAAAAAA8100AA90008881\n\t002AA2022043240CA2E82883102AA2462B20002620323002AA2222422AA23220642202A6002AA04255A60A2022AA0000000000582040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000484\n\t000000000000000000010000081100081000000900100000080B0000500480000000410000500000000000000000000000FF\n\t5FD48000000AA8AA8AA8AA8AA8AA8C28AA80680080032ABE0229208A0AA28A28A2AA0AA24322A0002020222220AA042203AA\n\tA0020022AA0220002AB2AA0022AA0022AA000000000000000000FFFC0F800800400400400400400404501201401220000300\n\t4A0408C02C00000404400400000480000088100501400000000000508412C028440001005211001111101004000000000000\n\t000000FF5826800000555D55D55D55D55D53913D55811913808055611440400651655455455615640CCA600043790444615600d82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFD446\n\t0000000000000000002002000002A400022010484800800204080000080000204B0020100000000010030010040800280000\n\t000000000000000880000000010020000000000000000000FF412901000000400000401000000203830048A0102000040000\n\t4000000019400000001102001014020200A0200080040AA8038000000020000012A000003E10B00000000000000000000000\n\t00FFC93809000040020040040040020005040008008001210000A80000202000200200002001301003000212800082004409\n\t20000D20200000008001001000121000051000000000000000000000FF20E80000000000000000000000000000000280520000382040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A2A128020220\n\t83002020002082142192002002000000000000000000FF4ACD140010101801801D11901801901831C898258902A8F0CE4243\n\t4655754400411634E506C8400281614640F4960C6116CA62AE2A60A6006002844087C060A600E006000000000000000000FF\n\tABDA0A000802800200820202100505010522601240618042080B929800821C42C2682202F822D028668230A60A6069044881\n\t08042040000CC2814A400C340000004040000000000000000000FFBF130A0010080800800888D00C00B00808800A14808000\n\tB03220E8C2AB22C220290F00310AC02800412002002422C9200200255254210202200004300280200200200200000000000000b82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000400080\n\t7006006000000004004001004004004000004005004000000001000000800800800000000004000000000000000000FF3BF1\n\t000000000800800800802800800880A30A08800102A0C2B42802002050080308402002002202082802002002002002002802\n\t40200200202A002082002802002002000000000000000000FF656B1400080400040080040400000400000002020000000210\n\t810D100082818280201104A13490284484214204502800502008000401000885001248082000000000000000000000000000\n\t00FF4EAD010000014800804810C02800A3080098C800C64200B0A200200380200208288284281280200008300399A00A85A100782040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF30490100\n\t00001801015A01801C41805C0184100521000062060404AE80640042801400E04694601082E024CD48060404060848861068\n\t06016228000456804116006804000000000000000000FFCC8A00000000180100180180180188980590908108200060060000\n\t064000000000A408648E01004010640400420E10014600C006006006086000086106124006006106000000000000000000FF\n\tB2FA000000000000000000000000000000000000000000000000000000600600600000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF0AF700000000100100100140000000000000000020000000f82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (500600600410\n\t600020F0364D209608E006000000000000000000FF8414000000001800001801803C41C01801901801090000700022548848\n\t608084080300011629081009200450201014020701600600600211644800708F80600E006006000000000000000000FF2E85\n\t008000001805003801A419018A3A27A2128180204062070010661083062DE0A9406A2641083000620C53C3066100E3084886\n\t1A6004046010041326082024006106000000000000000000FF6703000000001801009801A05801A49841A092038000006986\n\t40000611610610700008E8064208000261B4004066C000020060060460060060008800066260C6006086000000000000000000042040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002000881006\n\t116004100000034094084A082B404000E006806006056806006004806106446152106004000000000000000000FF8D3E0000\n\t00001005003021803909841845A252073D204669000200004067074C60BE4C07024060C0082225026C0000640160401E32F7\n\t84046091007046813024016006000000000000000000FFBCB00000000018010838218418118098018A15414020087001B240\n\t408210060062A600180380640002A94400708040602400400640600208610024E016087004006086000000000000000000FF\n\t2DEC000000001000121003C018018338C1C8D8A1050010E140284000A40000200C020401060264200320950024208002060000842040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FB3C00000000\n\t000180000180188180C001A03801811012E400012D1014780600600E0C01148041040108860C0800000806804887A1620400\n\t6040002026002804006016000000000000000000FF9059000000000C07800801821A1D868069A01821808080600000200140\n\t0216C07B020000849042901004100201880804120160161063042061240A210641A087106006000000000000000000FF76EE\n\t000000002800800C01A21801800009829849C000006111002000006406106C00200041004A0500400740542834E146104806\n\t0070064060050A20060C6090007004000000000000000000FF77B5000000000800840803003E01804081811801800000E02000442040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006014006000\n\t4060266421C4086016000000000000000000FF80BC000000000883822CA1089D85C0D88180341100212A760608200F400807\n\t00E00228601010422420090100000622E03688420622E304006105207807902000106006000000000000000000FF8E300000\n\t00004800810A01821803A01835901855C4900068D783644690614E026281816408484085924226000086086C060040860071\n\t485160068521068A2834446016000000000000000000FFA1F5000000002800800801001801801801835C01A0000B6116016A\n\t960A000E2860944C682000400808D20F300C46A36327115116496800006004003126442008006016000000000000000000FF00c42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060060060\n\t06006006806000005004006006806006006004000006006004006006007006006006000000000000000000FFCCC600000000\n\t0201820201889A03801841801801A0C008600200740690004700608640F2062064465460440060064C60061068848000C630\n\t600600F106806006D46006000000000000000000FF449A00000000C085814081801B0189180DA81A51A4002404B209684600\n\t710EC4F40E1068168C608400C48D28E006816407406C04C4840601600602602610680E006006000000000000000000FFD5E3\n\t000000008001800447841801881901805005000000600604201600600620680E00680002400400808928810680604620400600242040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000001\n\t900040845805911C41D00015C000100414956457340526126556086006826000806884316201054214004209100106006005\n\t006006807004006006000000000000000000FFDD130000000000018000018018418218958089218850230024406086016016\n\t40E00643654E516500486414026088004004414004200006006006026006002004006006000000000000000000FF040A0000\n\t0000080180080180180180180180100180000040000060060000060060060060060060000000040060060060060060040000\n\t06006004006006006006006006000000000000000000FF00AE000000000801800801801801801801C014018010004000006000a42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (065260000060\n\t0680700640E006000000000000000000FF774B000000000001800011C01C01831C09889881A82048E2260AEEA62AE22E32E7\n\t262A66A64AE2D071467E6C878840200A00A0072A0086006041106446146006016006000000000000000000FF768500000000\n\t0801800801C01801C43821A950219000854150416156C50D564168365561561563048460841080001422421014D002001654\n\t600C00608E206884286006000000000000000000FFD533000000000801800A01803A01809823864823850080410020600600\n\t688708680E00E00E006004086044800000002002A0000404001E006004026006106004006006000000000000000000FFBE1E00642040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000600700780\n\t6006006002000006000806000000806004000006006003006806806005806006000000000000000000FF2AA4000000000001\n\t900048841845901D01A85C1185014441170068160070000001060268266A60008209A1046000254405002C12000006006800\n\t0870063A6084006006000000000000000000FFE39C000000000001800001801801829821C01821B000005806006007C00048\n\t48900600710E00602100500000640080440410350204000E0070290062AE806804086006000000000000000000FF11AD0000\n\t00000001800200801801A03C01815C01A00143615740E3360494868064D648E20701648828E20FAA8081942022802856000000e42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001808838809\n\t4A8019418218059C1801840008C112486006200000000006006606206010000A300000064404000081080006060060401464\n\t06014000906886000000000000000000FF8B660000002A0A83A90A91C31CC9A21805B01C318401004442846A068CED09490C\n\t96D0E8070A68080002268808068088410290000410A6816A0082F056904A8C42E086000000000000000000FFCCA600000000\n\t084180082288380181188182588380802A8005286006206006006046026287A062800C90882308264002085060CC10040600\n\t600008628640E024106236000000000000000000FFE6FF00000000080180080180180180180180180180000060040060060000142040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (880001080888\n\t0800800C00000000000000000000FF33A2000000000800800810800800808C00800120824000340200220208259000000218\n\t208200264904350262210200200222201200000200210000600230A400203002000000000000000000FF98D6000000001821\n\t9018850020A010440200200810002140200200001470060974A04280010300000240440C400021C2240010E4080020000010\n\tCA02A0400058038228000000000000000000FF23DB0000000000040400200200004402804200040008120A0020000002700E\n\t60E2482000005001008800800180201001084000000201110002010080000003A0480000000000000000000000FF40FA000000942040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004800880808\n\t28480280481488890883088890C004000904004802525004890835004904000000000000000000FF1EAA0000000118018C18\n\t03801901881805901905900000440450600601600410C00650600610600001414400610610E046404134800416806000D064\n\t0608E426006406000000000000000000FF0F78000000480C42C00CB0D00C4082C820820C008241B0A1130232A30A2A8B2034\n\tC3003403A134B002240B44B023443303083A020011020830D004B00320309350A002000000000000000000FFA36A00000023\n\t02402082003882082100402002820081400804940D408182009001008008000808808188088008408008409804008008811000542040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040440040040\n\t040040240000040000010018110D10014000010014410010D101100100901100100100104100000000150000100005100102\n\t9408000000000000000000000000FFCCF00008001200A801A0240AA0AA2AC0AA0C209400402A82202A03204A82A828820022\n\t82A00000002A88802202302902008302A82A80282A80004002A82001002A8000000000000000000000FF175C000000280A00\n\tA00A04C00A00802A00A08C40808100200A80288280280302294A80280284A840802243002802802822202802000402002A00\n\t813002822D02802C52000000000000000000FF457400000020C2042C03084014012012012412150028004885010810A0000500d42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F082A8500101\n\t2A82A8000000000000000000FFADCC00080003000008400000000004040040C0000100001100000010020840000030010009\n\t3000000083000080000800A0B000000000400000000200000A0050000200000000000000000000FF7E3B0000000AA0A80A80\n\tAA0AA0AA0C80AA0AA0AA01402A82A00002B00A8AA82A80082302001200102801202C02A03285082A8AA82A80402A82010002\n\tA80000202A92A8000000000000000000FF679D0000002043542403303543545101541003400000D50448D50C40910510D30D\n\t00D40D40048840D41048D40D40C40C10020D50550308550A00910D50C10A00D51130000000000000000000FF68C70008004000342040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1400400420E1\n\t080064A400C00620600608403602000000050005640608E006096006000000000000000000FF8AB900000020023420020040\n\t14002212012012010040004804A40810820825044948900800A848028C0814814910920B08804000000800000A0000100481\n\t0888800004000000000000000000FFD85B000000004800800800800800802800800800810000210A08E10600200200240600\n\t600604A00800A2421420020120220020028002000000000A20024A2442002802000000000000000000FF90080000000A8080\n\t0AE0AA0AA0AA0880AA4AA0AA0000AA822040222228828828810232A2AA4000002404802102302000002A8AA92A80B82A800000b42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (82C8008008A6\n\t840814868082802056241701106010200010149102128004200000221A2420020022420020120000C0008000002102002412\n\t00A002000000000000000000FF834740080000010000000040040040242040050C08010090080000C00012C9200200088029\n\t0010210010014000B0380491021109001021031001001100029221001000000000000000000000FF668B4000000008008028\n\t00C40C84C04C52C20C48800101345240208205310B4C24C24D22D314344124B0131221220421034430031111410410514030\n\t12423223003002000000000000000000FFD74A00000008380183180188182180110190D801884004400414401408640400C000742040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (264020C22060\n\t86080000000000000000FFD653000000001805055842811803821835951801880014420800620E0A00300100860264360C60\n\tD000610040202608802414C10600044030002000E046016014486106080000000000000000FF5CC100080000001000002402\n\t800009000011400000000000404A021025604E2061000400C00801500A83200100885104100B00002080002004A002840040\n\t80200A0000008000000000000000FF3F3E0000000018018058010C000000008A082020000000444034001014E02615603040\n\t000054829042C1440B000804400C3001401480000002A8230310480000080000000000000000000000FF1F1100000008288000f42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60C600680022\n\t602004000800401604A00E000000000800002006016102006006000000000000000000FFE99B00000000D801043800801800\n\t00180190D80181002480460B60A644002604609622E0160060400123161141060281401040860000000000000020060C4052\n\t004006000000000000000000FF43FB0000000018010018118418080818018018238000200085007006216006407227007086\n\t00E0000A821002010600020000420E010000000200046086006302046006008000000000000000FF7E570008000018130298\n\t098078098118218058238E000040C055604600660016803619E20E60E0000020462140364000160042865802000801000004000c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AB8AB8AA8AB0\n\tAB8058AB8000121236D1701608E2AE2AF0C700602E2AF02040A0C624C2A022A2A82422360002A82A80012AA2AE2AC20A2AC2\n\tAE000000000000000000FF7A12400000001801001801801801801001801801804010700400620600000600642E20E00E0060\n\t8042024E05000008201600201400000000000000200642E002006006000000000000000000FFFA1A2000000E18AA0898AB8A\n\tB8AB8AB8AB9018AB8120004A842067060C82882884361D66062AE6020C24103042303842062122260002A82A8002AAA2AE20\n\t42422AC2AE000000000000000000FF97D0000000001800001801801801801801821801800008400C00600E00600000020600008c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C00600400600\n\t0000000000000000FF178E0000000AB8AB8AB8258AB8AA0AA8AB8880AB80004002544861A608828E28E00E0060862AF00808\n\t000420222029C2002061440002A82A90002AE2AE08400E2AC2AE000000000000000000FF06D2000800001800809801801800\n\t0008018480018040214100046026206006006006206906006000100004006000002006082086000000000800004006006086\n\t006006000000000000000000FF69A30000001559549558B19559541549558CD155810004C5000D60365505565561061462A6\n\t55600C09610448255044254455620600055055000555455608654E556556000000000000000000FFAF5E0000000938AB0A58004c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006004080004\n\t01201610E4260024040000000002040CA00620408E404006000000000000000000FFA7F00000000018028018018018408258\n\t01805801805022C0120860462060460064260160060060A04164C42C610602608E1120D60000000001400060060CC0060B40\n\t06000000000000000000FF1A5D00000000180080191180180180180182180180A024C15220E20E400006006B263164560068\n\t0001631408A10E02614E0C21260000000000000060060044A6004006000000000000000000FF0B4400000000180180180580\n\t1800001801804801801008680684680604604604600684680600608022002404200000400600E20C0000000008008020064400cc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (590190595580\n\t1155812042E2200161161105165161065061265500042205485064565462264D454600600600014420655611400A51655600\n\t0000000000000000FF0287800000001805801801801841821001941801800005600600600600604600600600E04600000844\n\t80104C6096006446084006006006000208006006004202006006000000000000000000FF895D0000000AB8A98AB8AB8AB884\n\t8818AB8018AB800000602202600608E28E2CE00E0160262AE60003600C0063262060062260160000000004003122AE404626\n\t0042AE000000000000000000FF4795000000001801801801801813810801929001810208628021631602000602610652630E002c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (806006000000\n\t000000000000FFE5E90000000ABAF1CAB80F8AB9218058AA0208AB001000627006600608E28E28E45E0464362A8008020008\n\t0062202141040022AE0060060000001142AE4760422AE2AE000000000000000000FF5AA60008000018038018010018298298\n\t018B5801000210611652644622002600622E02620E0040C01040000360060160960060060060040000000240060260A20460\n\t06000000000000000000FF781A0000002AB8818AB8B18AB80B8898AB80B8AB00B030630650E4CE2AE28E2AE0862860862AC2\n\t801042A000E2262A60162542AE0060040000802442AE08608A2AE2AE000000000000000000FF355E000000555D51D559551500ac2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0108302E8000\n\t0080289760510720608280000005E866006402806806000000000000000000FFAFA0000000401C01C03801411E01C0180008\n\t141514000060A604600604000600600E00E40FA2403480D22C01034100B00400380EA0708C00800500740614600700700600\n\t0000000000000000FF98AB00080000180D801901A01813945A00082001014022E08108604642602602642601600600430241\n\t54C52D010802288E01200600600400010A294806016206007006000000000000000000FFF052000000401C01C01A41801901\n\t8118000080010000886008216316000006006106526B0E00000008000000600090C425542006006007000200024006286132006c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A01881811A83\n\t000004612E006486316500000216246546D0A010202C5200E04910508610642650680200800080611624620708F206040000\n\t000000000000FF1886800000001801803809801801841C41921909034142E1120163364201004104060060CE022408C02003\n\t0360A010441600510E006042100000006A06346302006006000000000000000000FFC8A3800000001801811C01801851801C\n\t41841801808124620020600E0002C60460460C60A608A0013021070400002823060040060060239002001060962160960060\n\t06000000000000000000FFAF70800800401C01C09C11A49C059C1B818079638841016012B3654650623E436526086A0700A400ec2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00000000FF4456000000401E0388B80190180182193580583180484461022060A611642801002E44E51604E0002364044405\n\t1604000410431601600450000002C316006416016006040000000000000000FF54F300000000180388B8038C180182182399\n\t3805802001640020602600602600612600E00E1260C002E01402020601810001404600600020000012C20640E00610640600\n\t0000000000000000FFC2C3000000401801A018018438DD881809801829880020E64210600E12000E20E19605600650626009\n\t658420048663000202C08E00E0900904001C411609601A006006000000000000000000FF54D4800008401C01C41C09C21A01001c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A2BA28A23220\n\t200211A2AA2AA2020000A000C2AA2A22022AA2AA000000000000000000FFC900000000001A01801805000000002000000000\n\t0020000144210310406006006100520308014040004004004000114004500000000050000000040000010010000000000000\n\t000000000000FF4B438000000000004001200000000A804013402C0108000208080040006046026420010000000300000000\n\t020108020550020000000080000400480000000120000000000000000000000000FF6B88000008201A01C418138059119018\n\t0180188188080060560062162401002002060060264063080860A400802648000204600630610400800000600614E0040060009c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (118B5B558001\n\tD5610E01411435655451410450412450608950652E5464475462864C65575564B60000105575565560065575560000000000\n\t00000000FF1A1D0000000AA8AA8AA8208AA8AA92088880C8A880802AA48250A4CA2CA2AA2AA0822820832A23202A23223322\n\t222AA8022222AA2AA28A0004003122AA2120922AAAAA000000000000000000FF69C800800040040040040000000000044000\n\t000000C800042052044000000002022802020800040080100001000900000001000000000000040000100000028000000000\n\t0000000000000000FFE2C00000004AA8AAAAA8088AA8AA8148CA80008480082AA0420600000AA2882884580404302A20002B005c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF5E1A080000000000000400000400000000008000000000114021031020004000010052030900800080814000001010\n\t0A000080000000C0000000000000000000000000000000000000000000FF93F68000000AA8AA8AACAA8AACAA8AA88E8208AA\n\t80202AB00202600608A28A28A00E016027252200273A0320232221B0522A3AAA2AA2020001802AA2AA2AA253AAA2AA000000\n\t000000000000FF38BE8008004004004004924010010004021214000041004010000000000004004000008041010000800800\n\t000081000D280000040040400000C0045004120440004804000000000000000000FFDB3B880000555D55D55955F55955955900dc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80220200A003\n\t502A02002802202000A02800002802002000000000000000000000FF0D1D0000000000000000000003280800020800800000\n\t810128420010800080000020021D201404900400001001000008800508A8C88000000002080A400100018000000000000000\n\t00000000FFA51D00000000000019000410000040008000E0060200000851801000000040010C006081003010000400602280\n\t40440800000441811000010400000000A303A0000000000000000000000000FFD52000800040040040000020000000004008\n\t200000810002080800400400000404200100000A00881000089301010201500000008000080004080008000000D000080000003c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4820C4A04880\n\tC201208200300210280A80200202A00800204A80204245228200200A20200201208000200207316228200000000000000000\n\t0000FFA996000010001801889815801921801C13249803840013040F424516016094D14046436136CA63282150D642F50781\n\t6887286C8C28E006A0600008602522F2A6006000000000000000000000FFE1860200A00000A00000A00030191011A17A5181\n\t0A00A2114422D02C809A8C2E40A01A86290102A11C4E8018088C88802405404400102000002968468C284000000000000000\n\t000000000000FF753600000800080081080A800C00800C10840800800012040200328201201233200708200A80A040D0A30A00bc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF70130000000010010010010000000000000002002000000800000000006006006000000805004000004004004800004000\n\t000000000800000800001000000801004000000000000000000000FFE23A000000000800802810900828A00A0080092480A0\n\t85008A0000040120002088100B210200A00802200A00208300200200322E8020028022800020060020020020000000000000\n\t00000000FFADF00200C00000A00001200040800000C04C020008009008012451480012B1040B40400C481415401002801008\n\t10101520000000408020000848280D08280000A80000000000000000000000FF60EF00000000080097280C8188A0800C0080007c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (462080060368\n\t10C4200200620080E00299EE46006000000000000000000000FFA4F3000000001801210801A01C4195194191183180000004\n\t17500440007210140504B0620C826500B56A3244C006B010462460C401000090E20000F03004608C10622000000000000000\n\t0000FF3A87080000009801001801831801803811005801832031000600000C45004000000C01610401600800000208409602\n\t8106006000000080006000506080006006006000000000000000000000FFB2FA000000000000000000000000000000000000\n\t000000000000000000600600600000000000000000000000000000000000000000000000000000000000000000000000000000fc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (840080004E09\n\t02140804000000A2A2E2CD00E2C900114000310622E8060A729485200200600031690304E81630E000000000000000000000\n\tFF0A8D080000001A00401801801821801E890138A380A0200216A0102582F00802828A08E14C0060805200080AA086086026\n\t207088028100114000886129046116106440000000000000000000FF2CD9000000001801118941A29805B43805BC18018208\n\t45010608600A20002611702000680490E00850E6A200402E02058600E0202024129161002460025065278040000000000000\n\t00000000FF0B36000000009801001801801801AA9A2120190D8000888006006A06806206096040206A44026200000102204000022040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF65\n\t8C000000001800E008148018058418008D184D802000000E04140000000600600402400620000610400600400E4003060060\n\t02106A06206006006002296046106000000000000000000000FFEC1A0000000018C1000943419801901BE1803A0984200401\n\t467361A2B0700E30625E184C04A0311140640C80662E0D0806F4611609618631610004686604603740460000000000000000\n\t0000FF1AA7000000001A81111801801E41801803C03C01E001A0800600704A40120FC0E4864150AE11342000692D0060C610\n\t1007006206024814004000D0F08480628700C000000000000000000000FF67EE000000001840001809401A4180180181182300822040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00610E282A0\n\t688600410028650E026C46804200000000000000000000FF6031000000001801800800201825903811A13801B00180040640\n\t052400600620605630C00D8040C000C08A80005602680600E002906086006080417202816926004000000000000000000000\n\tFF9E9C000000001801800800905813811860021B018D606009670610108600AF9969020444A74A4408444202008006416E7E\n\tB0652208600611E0009060126CE006006000000000000000000000FFFDEB000000021800800800801801801800A218038000\n\t08000F80000400654E0472000040C4148009085406114807080006406846406006006001026102106206004200000000000000422040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (011006006806\n\t00640600F80F005220100000AC4006000006CA604600600204E00662600010E02610E122A04000000000000000000000FFFC\n\t41000000001801820800983C41E81810A11E01A1801A931E286596000C2748662229400208840402418E2082566060A70260\n\t0200682610E005056806806B86004000000000000000000000FFC1F5000000041848C05890841885A21C0182182B92002001\n\t2702E24B01620E246100017090021C880040060A10260164063061062A751600404054750692600601420000000000000000\n\t0000FF18BA000000021800A01800C05C11895C01C05905A2020002074070220000060360D44C6C12410120D3400F0808069200c22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFFB3F00\n\t0000001801A01800801801C01201801801000000200500680200600700600600600680600080680600600680600680000480\n\t4806806001006006006806002000000000000000000000FF54B1000000001811801808101A0182100D221031A2008C0D2E10\n\t604601105620604620608601608408600604602600E3060C0900000406004004206A26806426400200000000000000000000\n\tFFD07800000004384194592004DA0590120180D4858900C020064362960060060CF30F10F456046408C0688E516406946006\n\tC00800A8815683602084E106056006008000000000000000000000FFECAE000000003801C8082000991980180B80B881800200222040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000044004206\n\t004000016026846006002000000000000000000000FFCE52000000001811800844109851805A414011503401454008144849\n\t0A0D0E03654648684608713124ED2634E08602600E4000808012064160004C72A6287006004000000000000000000000FFD4\n\t1000000000180180080002188180100381100381001062A640C28441602650601604E48E40E40008600E0064064062060002\n\t10008006006000006006006006000000000000000000000000FF28B500000000180180180080180180100180180100000020\n\t040060020000060060060060060060000060060060060060060000000000060040000060040060060020000000000000000000a22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (870D6012D000\n\t8600E25604E08E00020880622E0C790E00600E506006446806006001006846842006002000000000000000000000FF261800\n\t00000019018019000018018011089830020A200AE20822EA8A2AE2AE2EE0A609E0AE2884E862E2F61A62D626620E2064E600\n\tE00620E100606046C62006002000000000000000000000FF84D1000000001801800000801C018018018081011000324D4435\n\t4C10510D46316556546D56D100941162864460860860D6510088CC0006004214086006006807806000000000000000000000\n\tFF3939000000001801B800008A7821A0103396588900C020488408402400600600600600620686020008600E00700600600600622040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFDD7F000000\n\t0018018008008018018012008010000000006000006002001006006007806006806000006006006006006006804000000002\n\t802000006006006002000000000000000000000000FF03ED0000000018118018440119118058008180410000220044004004\n\t006020000416446806280000206006416026026807006EBA082000806000156506506006806000000000000000000000FF65\n\t3E000000001801E01800601801801A80A8000100021000244044058114002C00865072468100A008E107C068061070A60170\n\t06006000006288287006A07007006000000000000000000000FF8AD4000000001901A01880001A01E01200E015019002804200e22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (092004603000\n\t10940160728000100000000000000000000000FFD08F0000000059058818008018038098459040811C003000040040040000\n\t1000000600650604000005600600600600600602A94004000000200000601E00431002C050000000000000000000FFBCD000\n\t0000209AC1A24A10B09895A21821A43C21010040088CD44920C860101089168CE826D00800346C0EAB724620E88E4C20B494\n\t4812B2A80000E8AEB16C4084C200000000000000000000FFD204000000001801888820821821B0990B08128A480010424080\n\tEA0604600620622620620E05700000704600610610622600C2002004A000200090680602680210401000000000000000000000122040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4160B9010161\n\t9408808A70810800200818C80580AC0000C00004800890810801080880000800844208000000000000000000FF826E000000\n\t000800800800C28C00800A000408008009002802140004002409000022482002382000022A02012002C03002002492016202\n\t04A003402002092002000400000000000000000000FF9472000000001801848001C000000814B0021461404001016D2A1280\n\t0670061060400400000280108801603208201090A00850241A40084A0000018004840460490100000000000000000000FF50\n\t3900000000000010202004420803420A4020026000C00201009010007806886380220008000101900001008200810649A01200922040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000002002\n\t0420024820100140031500100100800040048D4844820824044820810B0081084044C90C88480488400400402CC04C90C108\n\t40004830000920894000000000000000000000FFC3BF000000001801941801845801815801801101004800C90C4060260060\n\t0401400604611610600808601641640651684600491401440621600008609608E00E256130000000000000000000FFE0B800\n\t0000402D02C00C40800A04D40932AA2E40AC0830204214210B0AA292D032A320344302B08084A142103102022202C0224214\n\t302B0C3010C4B023C23543082400000000000000000000FFDB3B0000002082A02202480802A434010048010800880848904000522040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0900810800D5\n\t0C50D50890A00800000000000000000000FF5B4D00000040040203040040060040060240040000C800000000000100000180\n\t10210010811010010000C9000001129001000120001000001011000101001411001000000000000000000000FFB1B9000000\n\t0AA0A80AA0000AA0AA0AA0000AA0AA00080002A82002100882882C83002004082A00008802202382A8260AA82A8A00010400\n\t4000402A80802A8040100000000000000000000000FFDD2F000000200A00A00B04A00800A00820C00A00A04080280280290A\n\tC0280200288A8C284280280000280280280280A0030020828CA8228A2800802C02802A12A22800000000000000000000FFEC00d22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C82A8288402\n\t2AA23A2B0010590A002012A82282A82A90002502002A80082A82002A82082A8000000000000000000000FFA6380000000000\n\t0000000840000000050800000041480010010210804408000000280900080000202880000000000810000010505000281400\n\t00000080000400048000000000000000000000FFA9B50000000AA0900820A80AA0AA0AA1000AA0AA00010002A83480C8288A\n\tC82A80882A82202400000212002A82A82002A82A84092803482A80002A92482A80C02A8000000000000000000000FFE51700\n\t00003543543543421545543540423543540000800550510420910551510C00C20940D50801040CD0D40D50C08550D504808200322040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000010180180\n\t180180180188190D0C1801840828600C40641608600408602429411408600048609608620608620620611401600610608000\n\t6446006006006006000000000000000000FF849600000020020C0442022012012004814012002008800804894814C2080482\n\t4D48800880008808C4C088920001000804804244948888000800800020800800801000000000000000000000FF12E3000000\n\t00080090880080080080082A80080080C8002002042102002002002006006006802000002022012802082002002912002042\n\t00200000290A002142002002000000000000000000FFE1430000000AA0E06000AC0AA0AA0AA0500AA0AA40080012A920162000b22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080100110130\n\t010000004000000000000000000000FFD21C0000000008008008208408408C080081000882200820100004C001A440001101\n\t00100801211059200A2124020021120120C201A062002000002202382102202042050000000000000000FF6F3A0000000000\n\t0058000240241841840048445001010011210C52242010A12282082200210080010010014012890011010C10052000000080\n\t01121001560799021000000000000000000000FF33BB000000000802C00842C04C00C00C00C00C0090490434430930C240B1\n\t5343250A02242301284100322300308B0230031030034024C201280103310B012003443002000000000000000000FF93D90000722040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8818021E0664\n\t067470004463321865803081065260040A430028309001E0060246060026C2000080000000000000FFC99900000000000102\n\t1901901903940805821809800A00400200400420831000430630608E00F04000E04203600821040600E00005402050310008\n\t622608C00E08A106000100000000000000FF16FF0000000000001240C40040000901240A200002020D04000000004A600600\n\tE0002803100C0040020108246008080200500090000090030210080240010010110010000000000000000000FFAFCD000000\n\t08180380100180000000008A042021108244050825001010600E0861401083001040204004A41060040A448022001400048000f22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000011805\n\t80180194884084992080024A600684480C0460200442060A600602280000600000600400600602610210600004E800006806\n\t0CE0060C6006000000000000000000FF1F14000000001001022849801801805903805811812000432A116126400006006156\n\t40E44E08604000600200600000000608600801429208202000653620604E002000000000000000000000FFC1CA0000000010\n\t010818018458418018C1111881802000402223622E04604600B00700700600690808620220600000000E0460B008440A02AA\n\t0000600604608600000A028000000000000000FF88DA0000000010010048458818838108010058E984221545B222C1881060000a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04556D5654E4\n\tC6A48006000000000000000000FF6F0A0000000AB0AB0A88A18AB8AB8230A1023888800B30420E2AE2A20AE28E2AE12F20E0\n\t2E2420202AE2AC2AE2AA2A82AE2A6AAF2A60C60A60202AE8242A6226A04004000000000000000000FF2C5A00000000000111\n\t1801801801800020081800800B8CC00400600200000602222E03600689200000600400600200000604610788600400600000\n\t6006006016804004000000000000000000FFAA0B0000000AB0AA0818918AB8AB901818181802804A05E0062042000882C828\n\t800600618630A0002AE2A82AE2AC2AE2AE20EA262264322060002AE40601628624E006000000000000000000FF0703000000008a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6126136C0602\n\t0000006002006004006006046A28326046106000006006006106402004000000000000000000FF5D610000000AA8AB8408AB\n\t8AB8AB8AB8110900020012A061422AC04048828E28A80E0060062090082AE2AA2AE2AC2AE2AE20E0D084E30622D0142AE2AE\n\t20E226900006000000000000000000FF0AB400000000180080480580180181180300804500800060A300500C406006007206\n\t12740600C800006006006002000006016004016006416800006116006114092004000000000000000000FF57CB0000001549\n\t54802955955955955885045133012040641355531015055651210650634EC2400C55655655655255055650EA0020E45654C0004a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018008018018\n\t0181184008900000020040221060060000260421061260060100040060060040160160060060100062060160044864461161\n\t06050014000000000000000000FFC217000000005802801801801801803915005801002012E29202600624600600622640E2\n\t4600402000610E0060460A6006006004096046124000056116002026300324000000000000000000FFEADC00000000080090\n\t180180180180183500581100D808E32A806812240026002206A060AE08480000600600400600600608600000610E00480C00\n\t680614600E0C8004000000000000000000FF39E700000000180183280180180180188184892000020460020043200060060400ca2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C2AC00620222\n\t2086000000000000000000FFF43A000000355B51955B55955955903801880150004049003250642631051655030610620655\n\t00445504D655043651655655445054000E35000444608E52624254A4D6000000000000000000FF6CD2000000011803801801\n\t8018009018038858018000002112006026006006004406006406040000000044006046026006004000000006000000006006\n\t15601200244E000000000000000000FFFE740000000A98A98AA8AB8AB8AB8A18010218AE000224400220E2AE08E28E28E00E\n\t00618E2A00002AE2262AE2862462AE2AE2A022608E20600000400622631A000004000000000000000000FFCD1A0000000008002a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (126106004009\n\t00003100000600600400400000002610000400600428613280E00E000000000000000000FF06070000001458919C58AB8AB0\n\tAA8558118018C000002AE2242AC4A808E28E08C00E01604E20C0002AE3842AE38E2862AC2AC3782A83862200002AE2AC4061\n\t423B6226000000000000000000FFD18A000000401C03801C0180180182992D82B801800000228603608A02004600005644E0\n\t3600000000600600008600600200610000834600000408C44400E002002006000000000000000000FFFEFC0000000018A180\n\t98AB8AB8AA80092184989580802AA2262AE1162AE2AE2CC0D64C60962900102AE2162AE2163162AA2AE4042AC22E2A80002A00aa2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9C03C00C02C9\n\t900BB05A009502406B004066224A661E1D4286006806A8C01116C88502700E817067004006006006060000816036C0208300\n\t4006000000000000000000FF1883000000001C01809C01E05205A41823800401804202100400415005008600400600E0D602\n\t608501102E040847007816B16000000096000104027046026206006006000000000000000000FF7C84000000083805C23801\n\t801001801825CC4222000000100C00440442600604422640F24692600000680600604682E006006084004016010000806005\n\t02E406006106000000000000000000FFDBE8000000429C49811A018010018AB8898080080100004084004000000046404106006a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (506002084006\n\t000000000000000000FF486B000000401C01811A8BA009408018018A5C0181001248402A450400649008C406026116202000\n\t11434008700F486800014C028C20880202008A408E00600E222006400500040000000000FFA2B60000000018018018018248\n\t20C258218A9844912024C14004C1104080C044C0564C652E020051004A10A8012603608080400E04620A20028004EA0E04E4\n\t02002006000000000000000000FFEE8F000000401841801805820E40D03009E51832000009422014E00208002620432E3262\n\t0648E020004507281096046087005117026204200401404406112106004006000000000000000000FF2D7F000000201C21A000ea2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (860821400940\n\t0041641600604000E21010005002000002600200600420E006200280020000000000FFDC39000000601F0180DC0D90180902\n\t59018A3890820015004244400010614040404640E25643020800433004000648600800600402428008000808608040C00412\n\t41060C0000000000000000FFBC990000000018018018018C104812380580980002000040061060266B600600408600620602\n\t620000400010000600600800600001820208040801601026E61600E0860A0000000000000000FF4DB6000000001883803C21\n\t8210000898AB805898840010E28E50E00E00802620402629E02608C1A810404C22E20600603051610800012200000040E000001a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (88888A8948AA\n\t814040800254622220C31C2CA2882AA0080100C840200000210208A2AA2AA20220222222208A0000000120486522124062AA\n\t000000000000000000FF7344000000201A018000018020000000000880090002230000040020006026004100120000000000\n\t404284006000000104080014004000000000248020020028430000000000000000000000FFF5E90000000000000000000200\n\t4004C0000240C401221000881001000260060062204082404C80200A80502460000000500480801102400000001005000880\n\t80080000000000000000000000FF81D5000000201A05801AC1801901009829811801808000029201454C0204100944861460009a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4104C0040000\n\t00000000000000FF7487000000155D55B55955931811949955885A898042444404556406156514556304104204494000D064\n\t24517557556516556405404556000000556446446096C0D556000000000000000000FF0E300000000AA8AA8AACAA8B28888A\n\t08AA900800810200A2AA29224208A28A2AA0D24C20120CA0002D28122AA2AAAAB28220A2AA2A23220000000A221208220208\n\t22AA000000000000000000FF0C2D000000400400000000400420002000048020008208810800011040004000005044803100\n\t40100500900210000000408008AC00C0000000000000840002200A0000000000000000000000FF6A760000000AA8AA8AACAA005a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00100A805020\n\t0800800108000200C00010000000000000040250011000000000000000000000FF6ACD000000000000400400020000100000\n\t0402080000050080000000000000400100120000000001400C80040000000000000090128120000002000108010100100000\n\t000000000000000000FF9CD20000004AA8AACAACAA88C904800EAA880C04800220224A2AA06A08A28A0AA00E00618E242001\n\t00300208A2AA2ABA222AB8221422020000002AA2323920022222AA000000000000000000FF59780000002004004012004004\n\t240000010415120042004004044004200044000400000480804041000C440010048050490A1004014010000000400084000100da2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (10100808B10A\n\t42CA00C0248650A2A20CA402C0E28322ED0600200084A08200244214200208281040300A8220008020020030020020000000\n\t00000000000000FF96AB00000000002010000002022202A0A20040080100008001800010000140020800000849C282AA0004\n\t00000810000230010080120800A00002888008000000800000000000000000000000FF8C0B01000000400020000440000001\n\t000003014404600805001204004008000800680004004800004010018A8C400080000000300000000000012004C0A8818080\n\t0000000000000000000000FFDD890000004004000000000041520340000120C400C20800200004804400200002204082400B003a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF71FD01000000480016480088000A082810E80A08C8402A204A30282A08221280204200214202200900210200\n\t245A81A42A002000002022002028202403782102002000000000000000000000FF70DB004094055830501845950332323833\n\t953855CCA0516B06556554957C04D5611704E52C506B0004740400E80E10E40610E12828680680400008E10E216006006000\n\t000000000000000000FF35AC0800000A800208300000200003178B02200000810080200288840081EC2A8EC46A80A8051AF1\n\t014BA53C84408402D4001000040010464280400009101100004000000000000000000000FFB96000411204C808000842890500ba2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006000\n\t000000000000000000000000000000000000000000000000000000000000FF62FE0000000010000000010000000000002010\n\t0100000000000010008060060000000008008000000008040060040000000000000010010000000000048000000000000000\n\t00000000000000FFDFAA000000000800000802A0041200A800908B42AA00953312C020041020010814000002020420008020\n\t02C02002002002802800002002002028802022002002002000000000000000000000FF561710000015000400000010400054\n\t00820442100100A00000848B504094C02289042B0810C0155040044008900000015080080800002002028020001000000000007a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (58A980088080\n\t0200E006044466B070AE400427084006426000306008A008A200600600606805000200A00000A00680659610600000000000\n\t0000000000FFF1EA000000001840001801920040001951C01909C2800AE106C1491040E4881048080C482E80E002A2E81624\n\t8231146046087108802812012402882406001044436000020000000000000000FF6E2000000000188000B809800002009801\n\t813841804000640E10400004004000C0A440C2860460A000650000608000410605600010000202200005210E000004006000\n\t000000000000000000FF0C1B000000000000000000000000000000000000000000000000000000600600000000000000000000fa2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF74D1000000001808103821808000003801851825C0420C410ECAE2A1928C904A20C428700A047480006040C00084\n\t82703600A00000080712200010702B156846006200000000000000000000FF14A50000000019000158118400004018018018\n\t5180221044065078080A6C0028201000652A00E08000E280037A140C60A60121000800070424000C729700624E52E0000200\n\t00000000000000FF8C4600000000184000181194006250B845A0A800A68242708E02C286008006008292A3C946B060308A60\n\t060060021044065E694082A14B002100053102006406016010000000000000000000FFA0060000000018200018018800000000062040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0402600004E8\n\t0610600000600C00000100E00640E242206200000000000000000000FF84A700000000180810184000030020180380B00102\n\t0000400630440000802700400400414400408400680400020004600600600000680400000580640609600214640000000000\n\t0000000000FF4A9F0000000018000059919024C0505899882858A0C001C22604600E90703645F15616600014C0002E618682\n\t6B0000645605000002F0070068080053420060062A6000000000000000000000FF2B110000006018400018018520000018C1\n\tF208028081B444D600E9360204871070022160080142083060272400000860062800A004E1260A70900D601682642640E00800862040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D1004000C101\n\t750E4143468C0416000202A1400600624880610408008602410608645000F02C00402510609221622A20E200000000000000\n\t000000FF1E09000000001800001800000600043E01A8160161100442C6006000126206403010417000445000546084486086\n\t806086202020086C4700210090795280700600E000000000000000000000FFC0120000000018180018404400002318698110\n\t5100402940360179090181769864401E63E02940500268652000060060062105100961060020C50460228460168060000000\n\t00000000000000FF66190000000218000018000000200018098050010000505006204450006006041004004C04104C00007800462040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF1A670000000018024098020000C00418458000100401806026216666806206C0600E00F00000C20804600400E01E0040\n\t0608200000E02E10E00008E413716026016000000000000000000000FF4EFB00000004182008388000006048DAA18060B008\n\t002C70060070062001264E2056086208854004D2700404120603600601032080670400408407680206E00308600000000000\n\t0000000000FF8EA800000000190004184003400C04581384000A054004E50E02C08E00F8964150C320502652710109612584\n\t6826C97807C2610012600748622000624A087006236020000000000000000000FFED0B00000000180000184004000000980100c62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000600600600\n\t6000000004004004006004002006006006000000000000000000FF9F40000000001801C00800000001801801801001800200\n\t6006006004006006806802006006806000006006806006006806806000801004006000806006802006806006000000000000\n\t000000FF1120000000001881849840250011A01C89A01003C80200E806246806C0884612600610640620601400E000000206\n\t236006006800100005404404007024022006006006000000000000000000FFE1F2000000001825904904004105B0D801A430\n\tC1A121546D36006096006B1680E92E20F04E13650308612004E046104806B46CA0028C3480E1220CE006002026D26026000000262040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (098A01227206\n\t00E06402E20600601430600600600800680682600604600600600800060601401108E0801160040060060000000000000000\n\t00FF1093000000001C41C05800000081809C0990900990004365460D68169402A602610044F116A170320A62802A804EC8C0\n\t565072085100048A600600680F002804007006000000000000000000FF68860000000018018018000000238A392184112584\n\tC010601640630641601649622000622604640040600E0065060060860260000000042060000AE08600200400600600000000\n\t0000000000FF74DB00000000180180180000000180180180100180000060060060040000060060020060060060000060060000a62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t9869000000001801800801808101A21801801001B04080622E08605605002615608A0AE22E04E250206AAD0A000680600E02\n\t6840200003006028807002006806806006000000000000000000FF3B49000000001801880809800081841D01C8902384A008\n\tE49E207A8E2068AF6AE26E8FF2E60367202A674C0C66EE2EF0FE2860000C0000086058047042012006006006000000000000\n\t000000FF0E08000000001A01A01800010081801803C01001D040006847536354CD054715651410640ED46056546010900006\n\t0072064C604820000280400608E008A06005006806000000000000000000FF4B1E000000001821900A10000023C2B8A5801000662040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02E216456000\n\t00800A20600003614228600808E02E000000000000000000FFDCBE000000001A01A01001800001801E01801801A000006006\n\t8060040000060060020060060060018060040060060068060060000000000060008060028020000060060000000000000000\n\t00FF0EF0000000001C01804801800001901815A41101820000604694E206906000806121006816E96000006104C16A260070\n\t06046408430002C56000847012B1F004806006000000000000000000FF898E000000001801A00801E00001801883C01601A0\n\t018078062261075003014062040070070061001270040010060444464860000000000060000AE02A0030050060060000000000e62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001004003\n\t000060060010680000A0028001A80240006420018220880010000208300010808008080500800800000000000000000000FF\n\tA22F000000001A21804031804003801881894005800008608600600420000000600420620600602000658C00600642000620\n\t60004401E240600000640242400000600E000000000000000000FFA2E40000002118A1A00201800501D21D21A822C180408A\n\t6A86C86844B1680884EA40B26A2E82E940016A04809346A070261060002A0CA288E800286A0A856C00426006000000000000\n\t000000FFF3750200000018038B342188000381180D821805930000E017006C0400688628600E00608610700030690C00000E00162040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF5F50\n\t0000002401830422041000002003482032001420961400800000810098000010080940C40D10509000858900800808808000\n\t880800888800D80A80808A00280120000000000000000000FF964B020000008800810800800100820820C009008200402002\n\t282002002C4012A10410200200204000200200220200200250200002801205200104200224200882B0060000000000000000\n\t00FFFEC50000000018002080018000800880020200C0088000820801102018E9072C12014204180900810000144060882404\n\t40020000300400000000230030110000840010000000000000000000FFD7D00000000044500A00000800001000001000220000962040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (022A20008888\n\t22C12800C12002912002002002000000000000000000FF44A200000020000120020000000140140120120000808080009008\n\t0082080492092C9409009008C0004A88A2084C89100480C000820914920A009048048208AC004004000000000000000000FF\n\tF005000000001841801801800001901801909021800000690640610601640412611640624E00614040604620650642602600\n\t60100802340960004CE014226106026086000000000000000000FF2EA7000000442908C54C14904500C00D20804C84940154\n\t340300B00310214B00202308310324B41090348B05300301340330200042110324301000340311320280201200000000000000562040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0D50C00C00B1\n\t0510C80D08C00C08D21440D50908910C40B08550300000048A30C10C00CA8D50CA0C00550000000000000000000000FFED90\n\t0008004004004006000004004004006404000081001001001001000801080501001041001801001011041021000000001000\n\t001011121000101801000001801000000000000000000000FF73EC0008000AA0000AA0A80000000AA0AA0A80A800202202A8\n\t3602A02882E82082403002082000002A8020088300020AA88000002003001000820202A8210A002A80000000000000000000\n\t00FF50DB000000200A00A00804A00000C00A00804A04800088280280A80A80200280280280A82284A400802802802882A02000d62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFB20B0000\n\t000AA0000AA0A80000000AA0AA0A208680002AA2AA2AA3000C8A884030E02AA2022AA2002A84004882102A8AA82180002002\n\t202001822208202414102A8000000000000000000000FF4ADF00080000000000020400000000000020000000200000000080\n\tB00208000480000280A00081000002402400100408010480012800000400800000000000A8800000000000000000000000FF\n\t1F990000000AA0000AA0AC0000000AA0AA08C0C800202A82A82A8230288AA80280082A83082A84902A80C00882802A8AA932\n\t00002C83202082012282C82880A02A8000000000000000000000FF89EC0000003542003541502000003543541523540100CD00362040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (210904301300\n\t305141300200B023013000000000000000000000FF79D50000000019098018018418000038CB921001028020422400400600\n\t608400C12621441420C308406006506206006046404000414086424400004016086006006000000000000000000000FF72E2\n\t0000002002002002010004004014002012280140800800800800800044D08C088008C8800903000AA8A20850800004144800\n\t10C800844A008042048C0A84804800000000000000000000FFDC730000000008008008048008000008008108018000006006\n\t00614A42200204600200600600600800200200210200200280200004209210A000112112012032002000000000000000000000b62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1080400A6126\n\t10834000840855009012448C2062C4020010004088404090040250208008100240008000000000000000000000FF77A70000\n\t0000088880080102080410690A822C0008010010012303020020511601034611410500002120020E210208223220200012A4\n\t02202000112002002412002100040000000000000000FF137540080000040040040000040040040040102012200002880110\n\t88349208201408280020001221009100009008041001000001005001001001001000009401001000000000000000000000FF\n\tDCA5400000000C00C00C00800D08440C00C02930804011210A5434D241344A5430120C20421430410D340A02B0AA1034130000762040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (690700080000\n\t10418079058A8900001805828007840015E2CE0A641C19648004600201600660601211615A2880401060064001804044FA20\n\tA10200200E226086046000000000000000000000FF1CF4000000000081809021909842081951024011800000600631610400\n\t014049610222600608E00002600645600000400610000000800249200000A146424306006080000000000000000000FF54DA\n\t0008000000C000812400012000004A002010042054002040022040E406208010008000100008120140006220120000480000\n\t208000100100020120000000040000000000000000000000FFCDF9000000001801000001800088020120100090008051004000f62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006096402500\n\t2AA0462022462AE2A8000000000000000000FFCE19200000000001841805800800001801001921802000600E20E08E406000\n\t02E00400600600688000230600600608E006002001002406022A0000240E032116006000000000000000000000FFA8090000\n\t0000100180580180180000180100D00D80004D61460260240200460860CA4A625632E42000600A2260004260060040000000\n\t2A510100002146106026006000000000000000000000FF705E00000000100180180182180000580180940180212072970260\n\t2420601700600B0071270260020060000804800460160040000801020020000A2016004016006000020000000000000000FF000e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5415053652E2\n\t9434E54E44E2845541165105504C65565500000001545520045504260C44CE556550000000000000000000FF1F640000000A\n\tB0AB8A9CAD8018AA0AB8AB093489810280F447026A064AE2AE50620505602F4060402AA08A2AE2A83362AE2AE00000602610\n\t80002AE29650220E2AF2A8000000000000000000FF0A2F400000000401811805801800001801431021802000624E22E00640\n\t000600602400600608601000220002000000E00600600000620600028000600E40A006006000000000000000000000FF355F\n\t0000000AB2AB8890A98008AA0AB8ABAE18418080546306086206088288206A4400E1860061002AA4220882AE0042AE2AA000008e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001801\n\t081A058018000018010012038034206206306806046006426C0404600608E200000300026006336006004000000006004200\n\t002096046116006000000000000000000000FFFE6C0000000AA8AB0010A98018AA0AB8AB8A110180000460060062AE08828E\n\t8070840060060070022A80600882AE0042AE2A80010000062AF0062AA30608E2262AEAA8000000000000000000FFDC530008\n\t00001801003801000800001801001003802000601651613400600702E894306A06156C000040200060000060060040000045\n\t04040800000006056086006000000000000000000000FF80C200000015495514395100095415595510500B810030E1061065004e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0E0040000462\n\tAE01E2AE2AE000000000000000000000FF1551000000004801801829041000001925041025808013611654600E4000460060\n\t0E13610E10600401002000009604E006004000100204404004004006526006006000000000000000000000FF23D700000000\n\t18438C5883804000001811009001805200602600600402600644610640642640E02000440E4260460060060840000140A612\n\tC000336006006006006000000000000000000000FF768C00000000080183380100000000180101514981009368B683600420\n\t002611602ED17336A2691000400E2000060060060040000002CC004904004046406006006000000000000000000000FF797C00ce2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C2AE01632408\n\t609628600020604028E2062AE2AE0A600200032C24E0002062AE22E2AC2A8004000000000000000000FF0F27000000355955\n\t04DA28150001955905951025804011611612642E5105162064D610630E50602455600E51041604655644E0005402A6146004\n\t516556006556554004000000000000000000FF23D98000000118018010000080018018018030498080026006206006004006\n\t4A600E00640602E00808E2960460360040060160020A0006006000046006106006000004000000000000000000FFA6280000\n\t000A988980910188D0000AB841087099800024620640E2A608E28E1CE2260060060760002A058608E2467842AE22C0002300002e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00001801201A\n\t00008001A01C01809C25808013711650600602400600608413610610600002E0220400060040063060041080041060001260\n\t06104007004004000000000000000000FF4DC40000005E58AB8AB8AA0800018AB8AB893889807020660605E2AE08C28E08E2\n\t2445604E0260002C608208E30E2AE2AE40E00661022630600031E2AE2242AE2A8004000000000000000000FF760100080000\n\t1801901A04000001801811801901808040624600E10402002601600422E02600600200604004008600A00610600000000C21\n\t6000006006326004004004000000000000000000FFB9D50000000018AB8AB8AA1220018AB8AB8C1903801048E0CE0862AC2C00ae2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (408040601640\n\t6002100006000000000000000000FF84A0800800401943A01D01800003C81C39A694319A2004710618641612400645E62610\n\t600E00E04090F0060972A06028660460420E000606400004690620600B090004000000000000000000FF4494000000601802\n\t001C00000001C09C01889901804020E24E01610400C05600608600600602621400748200084004600600600600002C004025\n\t006C4600E015005006000000000000000000FF076000080000B800801000022001801801A218018000006026026004204026\n\t44601640642640E00880740820614000680604600604010E02C000006006016004000006000000000000000000FF9D4A0000006e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60619E09600E\n\t10662800610603600800600602602E0000520080C8286006016000010004000000000000000000FF6567800000001821811A\n\t0180000B94188188B821850040608E2164060140000AE4444060464560012D6D4E2863460220062065041400060040008264\n\t16026082B2E02E200000000000000000FFC13F8000082018A1801881800001A09A01801881800044612E44E2165045281460\n\t042C62A602604814624E0000160210160460420000062041002262B6006002006804000000000000000000FFA5DF80001000\n\t1E01001001800603881845805041850000600622604624428608604E4362AE09600103602E081D0800700F8060001000064000ee2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1A0180124180\n\t2109941841801001880000602E4862040140800C60CC00602600641010E22604614004400600622C02008A00011040620E00\n\t2004084026200000000000000000FF8CCE000000601825811C01808001805901915005840028E50604600402444020600410\n\tE0163560404260162800002860CE0061061000024D0000156006042084410006000000000000000000FF4FAE000000001801\n\t181C0190A005801821801041810008E00603607452400601640640E0060860000061060004102860AE44600400008A2A0000\n\t00E006606000044016000000000000000000FFDAE3000000001803801821880081803805905013890001662608614C2942A6001e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000008A0\n\t088000000000000000000000FF9B200000000AAC009808A88000AA8AA8AA88488800002006000182022AA288088204450048\n\t0204002AA02208A30240A2AA2AA1420002023001C02AA2AA2022C039200A000000000000000000FF1DF10000002018458044\n\t0180000000000000402400201301105400080040060000001301001001420000100460044400000000100000201100020000\n\t00010000024400000000000000000000FF96A580000000011003000200000000000002800001000000200000A00060264400\n\tA84004204084000004804060C81000000005400001100202400000000C00480080A0000000000000000000FFD20800000020009e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040004000280\n\t01005440001020111005004001000500014400004804000915020110000000000000000000FFD033800000755D4D95595180\n\t0555955955955825014015411412455615655420455610430450410955644E537C0613755755630600055644E20155655652\n\t6416A06556000000000000000000FFB6080000000AA8B282A8AC8000AA8AA8AA880902814048A0CA0823022AA2AA0122AA08\n\t20922820C02AB08A2AA2120422AA2AA41200004A2220002AB2AA2AA202202222000000000000000000FFD5ED108000000200\n\t0004040000004000000001000000400240008000400000010000228030000401000100000088001001000030800000100080005e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000402000400\n\t2000000000000020020020000000200000440000400420408510800000400040148000000080000008000201000000120108\n\t008000000000000000000000FFDC3900000020004C0000000000000000000000240100110110540000000040000000130100\n\t1000000000D0020808200800800020000100088000000000010040220000000000000000000000FFAA3D8000000AA8808AAC\n\tA88000AACAAEAA8AA899800020620640E2AA0AA28A1CE2AA00600E0760002AA20208A2C24022AA2AA20A0002222220982ABA\n\tAA2122038C22AA000000000000000000FF5D0E80080040040000020000000140100105004800000200002400500000044A0000de2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080100045800\n\t00040000000000000000FFD555000088000052814902800808400D44800912800042AC320A30CA02700288E8860028020260\n\t80D0320200300202A80204200A01220200A080012282802202282000020000000000000000FF72E100000000000000002002\n\t00000AA0102840203200080000200000010D10200000000C2909003003010080000000000000000000100000000080001000\n\t0000000000000000000000000000FF0A6600000000008038400020000210001012C05040000000008400416C013001062982\n\t0081040000000000288000000000080000C00000080000660000628800000000000000000000000000FF9B15110000000200003e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004044051220\n\t0808A01910020530000048400000000022A00010000004000000000000000000000000FF6352000000000000904804800800\n\t0248008008008560022C13642002402002802C0240200220200000200221208A00228A7A2003002002802280003E03462002\n\t102000000000000000000000FF4849000110000155A0B8A5821A10623F55A539558C0053685734515600C4D4516956026126\n\t14C1488C70060060060160060A600700EA0680E00023628F227206006000000000000000000000FF5D8C0200000000015080\n\t2240200E11B0033210002A81A086880840805C82240A04A12884390002A961450CD1900006102400003C005000904120800800be2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000060000000000000000000000000060060000000000000000000000000000000000000000\n\t00000000000000000000FFB76D00000000000040000100000000020000000120000000048000000000060000000000008040\n\t00000800006006000000000000800800000000800800800000000000000000000000000000FFB32000000000000080882080\n\t2C044C080C242850800082300200200202210081100080200A00204100200280200200200204200200200280428002200200\n\t2002002000000000000000000000FF73530400000000000000000000080100010800000800A100800840A1091C4892014011007e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00610400000\n\t0000000000000000FFBB93000000000001A01801A0180000582020180180002240A2E0440640044742004624411690808084\n\t600660001600600600614600600641400069E802E06126006000000000000000000000FFFABA010000000503841A81801900\n\t249A40103B21A2C2AAE31600300E800000024B0508404640628840E506100106B060471060174170460240A0806420002026\n\t206000000000000000000000FF4A4800000000000988000100180008189202180B900200604611200601010811400C214006\n\t05004008600E016006000006044006046006006000086000152206002000000000000000000000FF687F000000000000000000fe2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (206021807406\n\t00103620402603602628E016006080420006207006346000000000000000000000FF4C35000000080009801805881832001A\n\t04801800A000C060879008858032308A20014CE4AE20720828600602804600609642601690780E0060890268274460062040\n\t00000000000000000000FF7979000000000509D41A018011000458088238228C4000E40E10020C20A540002D000A600ED404\n\t1130E29608E00E50602604603644E0260460C0002427046486206000000000000000000000FF092E0080000000079010C180\n\t08002899828818C984800D404240E04600010E29816E80C0A68000200261064078864060468845C641600624C0009040020800012040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180000B801E9\n\t3C41200400E00C80441488080600100653445400280C20651600600700400608628600604410400401410601620604604000\n\t0000000000000000FF208300000008024D801805801E00001801A51801000184600411411401004600408603404C10220C00\n\t6106021006006206206306006004006004006006046006006800000000000000000000FFFFFF0180000024219218C9867800\n\t18991D8ABA9A988058620A40E64C20A10620684AC06004886020506A0641600E00631600E016007006046611304046984806\n\t025000000000000000000000FF34C1000000002001841B0910184C609801903CC2C48001654A00580420240FCD600A08628400812040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (304080000000\n\t000000000000FFBED5000000000005801C018018000018218A99310805127108A09406826006044014CCC20E88320020E00E\n\t80040C00628600482602E00C004200000106026206004020000000000000000000FF836D000000000605801A01841E00041F\n\t0080189448820A648484E0040423164461468060044D200404600600640E08E28640600604640E02400080480600788E0040\n\t00000000000000000000FFDF56000000000001801801C2181822B85084380000C200620542406D0820EEA038B600602522A5\n\t488362860601060060062060469960268A446000600604E006124000000000000000000000FF818A000000000001803C014800412040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C4807106A064\n\t0601422E00608629440FA2A04408681680E006084106000000000000000000FF222200000002044188590100180850581980\n\t98105C20147A0008289692600680682426600402280408600620620600420620400628680E80E00000460E40E00640400000\n\t0000000000000000FFCFF7000000000021A0780192B820483933E21A0400410B600800020E08660600200408680C08236500\n\t680600010411600610650700E404006004814006206116104000000000000000000000FF216F0000400000058118C5801804\n\t021801A0395545044160C022802641788E22829400DA4700209402628700600600E14E0070C6046C0624402488890600610600c12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001801001801\n\t8000006006002006006006006006004006006000006006000000006006004006006004004000006006004006004006000000\n\t000000000000FF3322000000000001A01801A01801401C010018018010006006002806806006006807004006806000806006\n\t806006006006004006006006004005007007004006004006000000000000000000FFF28A0000200000058818058418010418\n\t0120352380208061068864060461160460D620700610600C1462060000000060864060460400040020060161060061060040\n\t06000000000000000000FFBDEE000000040401810041815E34001A43029001C100A1724E44E8A641620640E406896456046200212040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00000000FF60EF000000000009904021831AA34218192C18098A40846C061868208068868060060040060860040060060060\n\t0602400660400E006080700004006406086806806006000000000000000000FF3A15000000000001A01C01A01841001AA110\n\tB203C0000061568160105060B632620E88E0568462A00062B612842088E406008006040806800000C0700688600600400600\n\t0000000000000000FF4B260000000000118018218218830298050011518B1030E00622654002E40600E12624630611600045\n\t600640608624609604002E000086000004126006006006004006000000000000000000FFAD9000000000000180180180180100a12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (601600040000\n\t7007005006805113806288026006006007014006000000000000000000FF3872000000000401800201A01A01603883011145\n\t90025265361032300A64A609644604624620E29008E0262000204082A6006006008002402040806806006006806026000000\n\t000000000000FF8857000000000001801801809801015EA712F0E180822EE2A720A2886AE20EAAEAAF3BE22E02E2E023E2C6\n\t6862A72DA6C602E006015003002510246807016046414046000000000000000000FF6147000000000001A018818118010218\n\t810083159000C86D56326D5094ED56D5734E244556257B144C6016028220406106086006006110402044006006006006006000612040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (03C230D1C800\n\t00600629600650630E28F94620400700600024642E00000820611608630622614210C02821240214708600E0160000000000\n\t00000000FFADA1000000000001801A01A01A01801801A01001E0000060068060060060060060068040060060000060060078\n\t06006006006006806002004000002002806806004006000000000000000000FFC889000000000001905C01C0180141180140\n\t20058042806016243000A06049006006A8E90680600080605607E006026816880846044802106000146C0680F026A0600600\n\t0000000000000000FFA634000000000001E01901809A01029801080611800300600682208100E0002460960071170260412400e12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF693D000000000002080280202220002140042080100220801800800008900E2582004800101000100005200078961A\n\t0208200000420000020100010000519000478000000000000000000000FFE97E000000000201800011801841181801134003\n\t8AC01460060840AE60600008608634418603600030600608E006040806082C060060022060200047400A208E006406000000\n\t000000000000FF0559000000000141A0582982B951411B09311A058480D36B36824AD680E800846A06904936A2ED00917006\n\t8881008A2426A54056916A0AA24800824888A0AA4EAA7206000000000000000000FF57EC0200000002038C9881801803883A00112040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (34203324A002\n\t00A0034430024030110031234D21130A3202000000000000000000FF7EE902000000048020026124000C2004840002000002\n\t820880240940800010100400800829000841408000D40848C000A0C25280A18AE8404800B20880800000A000000000000000\n\t00000000FFD833000000000400940A0CD0980200081AC80800800209202211400214230000205200200220210300200A0020\n\t0000300290900A00240280000A40A002002016002006000000000000000000FF5CE000000000002002E00002408000800020\n\t902800020002014202000010870211200004404482800F12000160062109000100200C00108880500000082413201842080000912040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A0080028228\n\t0AC0280A812802842802902802822800802802A0200283200288300200282A842800C0290280A80280200200000000000000\n\t0000FF28530000000000013003412C100140104200120000429088008948808C0804808950840948488800804804800804C8\n\t0804814005000C84C94C20910848C40804A30004000000000000000000FFBCD30000000002018A180180584190194D801001\n\t804805600600E10644600414600644621610600014600600E004106106486C0601642C00612030E20600600640E006000000\n\t000000000000FF1F5F000000000000C048548C0C04C00E00B2AC00880910300B34304310210B00B533103123A5313020B48300512040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF109500000000055433420220420035448C5543520040C10D40288448D50510C40C90D40CB0800800D50550911550891550\n\tAA8D50550C088D0C41500C90C50D50410000000000000000000000FFE25900080000000040840054A0004006106004000101\n\t0011000010010810011010010010012010100010012008010900010000010010000010090910010480010400000000000000\n\t00000000FFF9620008000002AA0001480000000AA0C00AA0AA00882402A00602202002E82802002082004000602A82A84A82\n\tA8440AA82202A82A80404000000302001802A8180000000000000000000000FF8BB3000000000000A54A02A14A00C008088000d12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (023320020028\n\t0200000200200020211211200220A000000000000000000000FF90C80000000000AA0460AA0002000AA0880AA08080802AA2\n\t92B182A82322884023222A82AA002000AA82A80C8AA80012A82A92A82A82A82A80000E03202012A818000000000000000000\n\t0000FF5275000800000000000010150000000000000000010008000900108000100010802000800015000000100002000000\n\t0000000000000080000000020020000001020000000000000000000000FF04360000000004AA1000AA0004000AA0A20AA0D2\n\t00202A82412202A82202A80482282A82A8150000AA82A80892A82202A82A82A82A82A82A82004002282802A820800000000000312040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (840220A14B08\n\tB20248314210200200A4420031091434022B348A20320302308B08900B04341100200208B003003000000000000000000000\n\tFFE8560000001120018218018218018018B1941881082202420424401403440E4042840A600428420000609600600400E046\n\t006206000204206000116046006006086000000000000000000000FF7A790000000000013082002D00004012212012240000\n\t8008100C4804880844CC8908800800C88810001004820004800804800004800804000C088148008208008440000000000000\n\t00000000FF57470000000002008208008028008008048008118040006046002002016002006006002006026000002002202000b12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF7C\n\t1600000009002400000400000014800008000415400C00101000100500B60105301202104D048010450054E1162042000244\n\t88110008440200008020110000100000000000000000000000FF57D70000000020008208208208508008AA80248000012010\n\t0022E10528020130100041312100000006204240201000206200210200000200A00828200200200210200000000040000000\n\t0000FF0BBD40080000040400040040040040040142002C01001082A100138000100009005060801005100900100800120000\n\t9001001001001201011001400000001001001000000000000000000000FF6644400000000440800C44C00C00D50C04C0482800712040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200620608604\n\t040A046000106004004006006410080000200000000000FF27EE0008000000018018050018830238098A38898A0034E20E2A\n\tA00811640802628600440608E01009608E1C84001461C602000610008A106060036444096182106048010000000000000000\n\tFF727B00000000000180000104985580980180381184000062260024A00060B442E55608C006146140126116416126006016\n\t0C600600010200E480026014306002006000000000000000000000FFCAE70008000000000000220300000100820000000000\n\t1400C0000240130546208028140408020330010200026346320010300000120200130300110428408000000220090000000000f12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006A482A0\n\t04628846640623E11640E2002AA2AE0880880062AE4002AE24800A80602028624622A2AE0462A8000000000000000000FF3B\n\t7F200000000001911801801805801803820801C02240E3061000080060440060C60063060068000020062464260400070100\n\t06000402056800026106003006056000000000000000000000FFDF4600000000000180480100182180183190B8B580820A60\n\t360460062CE00631641608404E3460200060060060063120065460061200C048600000E05408400628600000000000000000\n\t0000FFFACC0000000000018018410019018439158A1D01880320F10E2AC00F04600308700622509700E4000064260000104000092040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFC89400\n\t0000000155843B559558CD955B5588904B80000C602740454820651200644655454E50600C5545565105304065564AE55610\n\t8482C040044364CE496556556550000000000000000000FFCAA50000000000AB9018ABCAB8B18AB8C980489180C8AA68AE28\n\t722600E2AE90E1263060261364202AA2AE08E28E0AE2AE0A62AE2802908AE00230620E2822AE20E2A8000000000000000000\n\tFFBF6D400000000001901801801801801801824801802801600E02C00608E02209608E006006046100002006020000008006\n\t006006220048046008086006042006006000000000000000000000FF65E90000000000AB821AAB8AB88D8ABA81841801800200892040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (148006208144\n\t094810006086027006007000000000000000000000FF37D40000000000019018018018C90018018218098080A46A06816008\n\t286026AA6006006406006000000006006426090006406006120014846000016016116006006000000000000000000000FFFD\n\t020000000000AB8138AB8AB8018AB8AB801901C10048658632422004628A4460062AE8060170082A82AE0880883662AF0062\n\tAE0002063170002A62262072AE2AE2A8000000000000000000FF508E000800000001835801801801001805911225A00000E4\n\t07014090D0600600700E04520700680000400624604640000601200601004020502005610602E8060868000000000000000000492040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A60822066A62\n\t8E41600E2060060461602A02AE08E08E2822AE0062AE0000041060002AE3262060442AE000000000000000000000FF18B900\n\t00000000019218050218A1801801881001800A01601604004E01602208E14605613610628401000600040000200632600600\n\t000440C08400601600E406006000000000000000000000FF6C0E00000000000180580111381100180182D801804800600621\n\t01060060064262061042064360000040064460260300060140060004AC1462400061061460CE006000000000000000000000\n\tFF899300000000000183180120180580180190A4C3C04000E02E10090702E00200ECAE00412EB4F08000400624000000000600c92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFFA1B000000\n\t0000AB8138AB8AB8AB8AB8AB812055804054E01628220000E28C0264962AC0962862902A62AE2AE28E4062AE0842AC006206\n\t2A80102A82AC2A62062AC000000000000000000000FF10420010000001558219158918119559558020018052016006452502\n\t0165100C612655632650E204556556550530086556326554006536008044550454556506554000000000000000000000FF18\n\t02800000000001880001001801801801800081810200600604A10020604430E0060064460360000160060060061040064460\n\t0400610E00000000000400E126004000000000000000000000FF07170000000000AB8198A90410070AB8AB8019AB808A2A6200292040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001340002\n\t08000006096016002000000000000000000000FF6FD6000000000001844001801801801801921001801801601600204E0160\n\t0408E10600613710640410E006400000006806326005004004000084002006006126004000000000000000000000FFF1F500\n\t00000000AB8C18AB8AB8AB8AB8AB9410AB80002A67E62022543E608C00606E2AE0060060002062AE08E0EE2D62AE0162AC00\n\t42442A85002A82AE2262162AC000000000000000000000FF229F0000000000019038210038A18018018A805581105462B610\n\t204A0A604000641600401600600400600600000042C00600E00400600642028400000600600E00400000000000000000000000a92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (208650642400\n\t64060063060A630000E30620810010E206487322056006000100102002403897007800000000000000000000FF8A7E800000\n\t020281801C2B801903C99910C04A09800050E94602225429E33458E006196087006000D068960260B6067116206806C0E016\n\t00008008220625300E044000000000000000000000FF30A5000000020481801823801811C81821E8920D801000620608A404\n\t00600403602622404E00E005007006040240007006000010000084208004432426106806002000000000000000000000FFE3\n\tC0000800000201809C01801001C0180181300180C0006806152104006244426206004206436110826806026206036006013000692040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0F0000081000\n\t018018810018098A19039AE8C9840000600E1940440A60A400644608403601E0802064060064063042060260940061006900\n\t0027600E00E3A6004000000000000000000000FF3501000000000201801801809821C09800201805830448E0060222AC0060\n\t0C20622600628E5264100C60B602605602712620700250622C000290010406306007016228100000000000000000FFEBCD80\n\t0000008005840401801909801852049803904034633640210C0061142260064564260A6480A8F0162100100163161064C642\n\t601400000040004614E006044000000000000000000000FF0215800000110005821C11E018038018048208418A2003600E2400e92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000004802A\n\t8110300000480000000000000000000000FF0B6F000000000001800081001841841801909895850049601604410420600420\n\t608600410621600004610E00E016024006820000280020000000456006416446006000080000000000000000FF39F6000008\n\t000001801821955883805881825841880004630610402C11633408624611405608604050E046020300486026406104004208\n\t548080004496104106412410000000000000000000FFE5B90000000000018018218A38939138858008218800026286004406\n\t24E20408608666C40604653000E0060082C0086506186000006000028410006086006006206040000000000000000000FF0A00192040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A0000000410\n\t000010000001000000400020000000008A80080000000000008000010001000000000000000000000000FF1EEB0000000000\n\tAA8108008308AA8AA8D08A88AA00002A07E02344023E02AA0000682020000000002AA2AA08A0C80222AA0123222223000000\n\t001021021022AE46A000000000000000000000FF05A100000000000000A00110000000002800500000000100100000840100\n\t04088100090130100000000000446006010000B26004004128000000000240028000000000000000000000000000FFF49D80\n\t000000000012013200C00000000200000000000000000904280000064202000202004305000000000064264800000100880900992040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08000004010A\n\t410010000140120100408000020000000840402000003080000C0440030501005004400404801004C4100401004400000100\n\t0410030005100000000000000000000000FF114A000000000155911955955D55B55B5111580100000140044464D60145560C\n\t412455632450C481557D56136514556D5732705544E5460005005460D64C6556356000000000000000000000FF376F000000\n\t0000AA80082A8428AA8AA8828A8854800054A01222211200A2AA02249220A0922820002AA2AA0AA08B2CA2AA88222A2C220A\n\t00028142A0224022AA012000000000000000000000FF986708000000040002400000000000000304005400005402B000800000592040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8000012A8000\n\t000000000000000000000000000000FF3BF30000000004000B20000000000000420000000002000000090008000200420200\n\t000200430080801000040440000000010228C30000000480090028000000110000000000000000000000FF14ED0800000000\n\t0000040000020000000001400000060100100000000100000881400001301004000000000000000000013208800801080000\n\t00000000130800420000000000000000000000FF040B8000000004AA800CAA8AA8AAEAA888EA09AB80022A62A6323AA26A60\n\tAA41600E2AA0060460002AA2AA28A08A2ABAAA0020020022320000002226822032AA002000000000000000000000FFB6A90000d92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C85007282802\n\t0904C2E910C40D1010C54002888010040040040042A0004064084804404004000000000000000000FF37290280C408C0A090\n\t4D088ACC42810890944A28AD00822D0A4360CF00340282280A206486822000882002842842A0200204280200A20220200000\n\t2803002082002002000000000000000000FFF2C20000006000080002000000081220242000040040400040000000A808C081\n\t0900000000000040000200000000000000800541801800830100000C20020001A00000000000000000000000FF40F9010000\n\t0002000000620000501000042080D40140088440C00C0012840038032001010878800000000008000000000028000020000000392040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000221000004\n\t1501000003140000820202200D04940840280A10401230280110810B11010008000880000508000000001000800340000040\n\t880020800000000000000000000000FF5667010000000180800840808800824800800E00800300288201200202A00236B103\n\t02240200204100200207A002002003782003003002002000182002002022002002000000000000000000FFD4A00501441145\n\t41905B11155C45A33955B45853F5044D65554550D489450684E0564065164960000060060460040060062A62A621620642C0\n\t804AEA05027886006006000000000000000000FF65460020000000310010470A00901036A80101800A412280040A8020644000b92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001060000060\n\t04406006000000000000000000FF6CFF00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000006006000000000000000000000000000000000000000000000000000000000000FFC3C100000000040000\n\t0400001000000000200200000080400000000000400080000100000000000000000000680600000080000080000080000080\n\t0000001000800000000000000000000000FFAFAE000000000000800800800848CA0A20800850A8A004A842A02A0304A90200\n\tA00202A002B02800002002002000002002002002002002002000005003006004006002000000000000000000FF67C900200000792040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (210403604626\n\tE200216006026806006006226006017416822000C044A0586018006406000000000000000000FF0DDA000000000201803800\n\t801A01801824801801042000208400220600040EC8232404700F01602008600608002080E04680604680E117012000064940\n\t506011006006000000000000000000FFE1FB100000010151C05C018018118119202012918142C0E090CD2D03400886042C24\n\t08603600643031620614083003600644E40608600600200901400800688400E006000000000000000000FF0DBB0000000000\n\t01889800081801801808815001800210604000200A0C803608200400600644600000600600E00620400008411600E006342000f92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0B8018B5B050\n\t41843D25800881880000201420584102C400C5400514610E10E2010C608600000000400D10790604620E4320001060020060\n\t1408E206000000000000000000FF1FC6080000002201D01C098D1A218C9803011A01B20400F50881084012422000CC04006A\n\t8E8862A010708611100000E02E4440A6506006022000107003006044897006000000000000000000FF3694100000010141C1\n\t1800801801801901A0BA09820148604849010009410002408408604600600800E40601600E2260271164AF08709631201089\n\t600A207104216006000000000000000000FF85E20000000000098D1A0588580D80981A041881C0C000A00606201EA202266000052040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (401600600001\n\t6806000000000000000000FFE328020000000001801800881801801820C230A1A010404904004044403A0102200200604610\n\t6408046026086007204004846106406306100000801002806880006806000000000000000000FF07EE08008000200184D800\n\tA41B05891800815801A02004C20582408C002800802A1240600600612C00E006108001816046446046506006800004056202\n\t286800006006000000000000000000FF015600008000000BB03CA1811A81803AB13C2CFF85801A21063946809081C002490C\n\tAB644604E00882760600760600600608600603600720A00042F182006046006006000000000000000000FFC263000000000000852040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0279478C60C0\n\t20E106016406086006827086056106526000055056006114047046000000000000000000FFA736020000000001829800A81C\n\t21C01C41D138048000C210422860064D6C160128A50060260A622400708650000021602E246A8E40E02E00400C00480F4068\n\t04006006000000000000000000FF737B000000000001801820821841201A0020180980501340170018040921409129021060\n\t0600602040EA062060060860168060160D6056006148800006A06008006006000000000000000000FF32A6100000000201A5\n\t1A2080198180181D931AADB4000850445401BC8420100A204208700604600CA2E3060000780161464044060260068860A5C000452040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C3003584994\n\t9A09C818A3B15208221104E546D5222211401625714E48414008EC8600680608680480620604809755400002E10701610E12\n\t6020000000000000000000FF0811000000000181D01C01A2182180190102188282336D00435060B200303600244430E00620\n\tE00400600602640600400478410600700600600000200702E865096006000000000000000000FF0EB2100000208221C01C29\n\tA49C01A0980DA81A08D4420193B8266003022346AA280508600E80600708624E00000090E10600620698650F80C086602086\n\t00611401E006000000000000000000FF50C00000000004018838008038139418A5003C20909102000308E21649700E80A35400c52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (026006006000\n\t000000000000000000FF52520000000000018008000018010018018018018000002002006006006006004006006006000004\n\t006006000000006004006006006006004004002002006004006000000000000000000000FF23CC0000000004018008000018\n\t01801801801A0180100020000060068068068040060060060040020068060068068068070060060030060040020020020060\n\t07006000000000000000000000FF019A000000400000202800A01805401A23825811A2028009020060060020024451060060\n\t0682E00420600E028000016006046007106006004104C0602E046006006000000000000000000000FF102E0000000100200000252040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D64364145560\n\tC6B50420006106232006317406002004226102006007006800000000000000000000FF437C0000000001A080784480990480\n\t38058538038A102AE80420640600D20C88100600600E806000006086016006086046E1AA0600000608A0001E200200E80600\n\t6000000000000000000000FFFE23000000000440000A00801801151931C01D4CC30051654E506106A344B450C056A0649620\n\t604432628E9204200A6C0600200EA8E00E80C00480280F40E006007000000000000000000000FFD329000000000008000900\n\t009801803801805800885004600400E04E08400404448609604615649000600640600E00E0060024060000C610400000200600a52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A01601801801\n\tA01A41C02240212500E00620014000C427026036A00401047026000041006006802207802C06000000006205006884006000\n\t000000000000000000FF010D000000000301001802801809401B0D801B0190800200062460D6050A1094401650F487028088\n\t48E48613040000E10E012106092806802080006804A26004806000000000000000000000FFACCE000000000000200C05A01C\n\t93401829A098A980808032AC48EBAEAA008022C3AE28E2A62883A822640E0AEA0E03FA3700350F08888E0001010064046461\n\t04006000000000000000000000FF5370000000000080801800801C00405D15A0194191244460D515605645455434CC56D56400652040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (064560000000\n\t00000000000000FF9942000000000101885808882824001B0188900168002A808708620704604601610600E4070A02880063\n\t060000801264C640804614A34E2CA000000128017122086080000000000000000000FFA9D400000000000080080080080000\n\t1A01801A01000000200400600600600780600600600600000200600600600600600480000600000600000280080100680200\n\t6000000000000000000000FF23C5000000000011801144801001553905841001804280200C88700680004020408680700604\n\t0000906C06607046806806222006602046002000A27094046004006000000000000000000000FF919B000000000601A0000100e52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (401800808808\n\t621E0200101410002401A8000000300004208120808000000000000000000000FFB44B0000000800021A0080000006000028\n\t0000000000080010000000401B084000001804400200014006206064066004C8400B400808100400000F8090490200A20080\n\t000000000000000000FF644A00000000000181B900802828101811A11081910252A20404630600A02206440600E006080400\n\t806006146006806224000426026206382018806020006096446000000000000000000000FF77E9020000100234A49B45A48A\n\t084A3C31805A838002802A3482E82EA8A412C44806946826A0880001702ECA941020E816800406A060068028103488012C6A00152040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (40C00D44C84D\n\t4090034838A32238D222A413223403103A0328340000300335350300320B1124C300204B40300125300300B342A020080000\n\t00000000000000FFA98502000001051040040A3883004002003042020000801008500068810800A088100210301108008008\n\t00838880890800818000819040828800804908820C40085010000000000000000000FF28F5040000000088804C048208008A\n\t280080191488002121E20A201288200210200200200200A28000200200210000A00220280200280241200040204200600280\n\t2000000000000000000000FF8C5D0000000000200400700400410001C40CB04000000004048094003604100100810402016000952040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (82A800000000\n\t0000000000FFB0AF000000000000A00AB0A20C02C00AB0B00C80800280240290A90280280A102802802802803081003002A4\n\t32028CA83280280280280312288084288A802802802000000000000000000000FF516C000000000000000203310310001205\n\t2092220142810088800009014884808910800000800C01005004801044A04880C88804000804C04A0020C805004850004800\n\t000000000000000000FFDC34000000000201921821021803B0181182900B810200E216106206104104096016026056016008\n\t40640600601441604644600683608614C0109040CC40600E026000000000000000000000FF4259040000010510E0C914D00D00552040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A82A82884A8\n\t2A82202A82A92A82A82004000082502A8200AA82A8000000000000000000FFF8EF0000000005543540042802103542103082\n\tCC0080D41230CC0CC8D48C40540C50D50D50D50800D50D50950B30A48B30890D50D50D50820C00840C49550890D505500000\n\t00000000000000FF2D9200080000040040050000040040040044040400010818A10010801200099111090010000010020010\n\t01001001001101000000000001101003400101001150001000000000000000000000FFF81F0008000002AA0AA0000521240A\n\tA00402200800002A01202302202A02302202202A82A82A80002A82A80880880002000602A82A82A80081000802202A82802A00d52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08C880084081\n\t0000A0A208600608210A10210600600600200080200240220200205200200200200211220040290200214200200000000000\n\t0000000000FF8A5A0000002000AA0AA0004AA0AA0AA0500A008A00002502003022830012202282222AA2AAAA80012A82A80E\n\t80882A80102A82A8AA92A82501001412082A8200AA82A8000000000000000000FF32430008000000000004B00040200000C0\n\t0420000048010000000000000100810100000000000480000000400000100000200000000000308000488080000220000000\n\t000000000000000000FFFA4D0000002000AA0AA02A0AA0AA0AA0820920C800A02002082482484082A02202202A82A92A808000352040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF78DC400000400440C40C02C20C00C02C04CCCC008A0040B04205230300B08B4420821421031130031434D2503423\n\t122002003003143503003023103503003003083000000000000000000000FFBD5C0000000000018119210018019118098018\n\t2B814002620420402C28620608E0444042440061004160060160144164060863464160340160000160140560060060000000\n\t00000000000000FFBACA00000000020120024920020140120421220100208A0814850848A508008048088008000008820050\n\t04801025000D00800000000804844902928044804808000800000000000000000000FFAC8D0000000000008008848008008000b52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200062462200\n\tA00001404002001001081400100000A0200000000000000000000000FFD52000000000004000808404000000002200204000\n\t0023400844855050440043002002040031008030015002E0060402081004004A014001000008000001000010000000000000\n\t0000000000FFFEBB00000000000982082080080488A88883880E092010228300140002200200108168104040200003200278\n\t210821A01200202204A21201200000A38A572402142000010000000000000000FFAFE5400800400410400400400400400540\n\t48040102800011340000010490890800000000A140100100920004122108007066108100100960102100100100500100100000752040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A1001842009\n\t028500710604412210524731700600202000E0460C01004260A600600640600A04E000446082206244004000008000000000\n\t000000FFAF4F0008000000098039A09950018AD80180704500002022B20464B612023660422E08618E00A128226006020008\n\t016616182006000402026060206032006004404180180000000000000000FF88980000000000018010000018298418030110\n\t01090040602200E04600A4060140960060362900102C60064064560040040041260200020860900860420AE1041440000000\n\t00000000000000FF553400080008000000000001405000200A1400401220008008048010108090110100008000100080100000f52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF055D0000000000818DC8408810458AB8AB001891800072202040601623622620650E45E57E4861002AE2AE0A80882AE0\n\t5E32E2AC0402AA006500C062AA2AE322AAE000000000000000000000FF9DA620000000021180290383180980180101380180\n\t800970080060861061160060060260060368000060060060460064060060040AA002046A0009600300600600600000000000\n\t0000000000FFFD040000000000438210488048A380180112102B80400024864D623601200215452650630620230000600640\n\t62060040C410600640200250E10024600000610A004000000000000000000000FFFAC7000000080009805840801805911811000d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600610600\n\tE006092004086800084010806C24006000000000000000000000FF85A600000000004190180091191195595515590180024C\n\tE54431635644443602421621630601250455655651011055655655655650E5504D6484944442556494D56000000000000000\n\t000000FF00290000000004B18818898958918AB8AB08D8A3C00000A3570B732622622A22603708680614E4002AE2AE28E4AE\n\t2AE2062262AC2022AA24E00082E2A02AE00AAAE000000000000000000000FF52E54000000004138138AB823823801801801E\n\t05814000001400600610E00609604602602E34400000600600024000600600600000600200600040E0080060260060000000008d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (058100016110\n\t126146006086024026C2ED0E20680400600620042000400400600622A004056B042840D50070120060000000000000000000\n\t00FFB2410000000000C98B1804801801801801200841A0100000062162160D400E50E2960860260325000060060060060060\n\t0610E000106006106000856004006002806000000000000000000000FFEE8A0000000001018438208A98818AB8AB0AA8D980\n\t222A12248468062063224069061060060830042AE2AE0E80882AE2AE2262A80462AE2070040063072AE2A22AE00000000000\n\t0000000000FF9CFD000800000005801804841001801801C4080180A204000400600610410610C80600600600080000600604004d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t0DE80000000000AB8018088018AB8AB8030888A5802000E08242644622E2043260960160460000002AE2AE28E08E30407442\n\tE3041020A62AE00213600C2AE002226000000000000000000000FFF8570000000000019138A08C3801801801043803810000\n\t024020E0A600608C00600630612608A0040060060004000060865060A040640400600440C40400601210E000000000000000\n\t000000FF4B7C0000000000018418048110018018B100081180122A600810640E08604611423605640E246000006006046026\n\t0B640E00600E0CA00E0060001061240062A2006000000000000000000000FF8B0900000000020580188880502B801801001800cd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006086002000\n\t22628600600400200E00620000E006000000000000000000FF884C0000000018AB8830010A10AA8AB8AA80D8AB80500D428E\n\t08600E4860362AC00610628E2560002AE2AE0AE4CE2AE2AE2220880862C62AE0002AA2162AE0882AE0060000000000000000\n\t00FFF95300000000195595380B90515595585095591181203000401060961024124100062265165160045565561105102564\n\t0612A43000E036556004226546552130546006000000000000000000FFDB5880000000180184180181300080180084180180\n\t0040004620612604240000000E44E02608600200600640600600600410A24001601600600200602600242000600600000000002d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (102A40001060\n\t0E0840A000423685740E02E001006006006046006004207011126086004000002147004210006006000000000000000000FF\n\tB3DF000000001C0101584584500180180088180080000000B020E2A604420000200630612680600400600644000000600612\n\t2300016416006004002016002127006806000000000000000000FF0AD20000000018AB09195D8010AB0AB8AA9018AA813000\n\t820007640621C1082AA5C60060062860042AE2AE08E28E2AE2AE00A0206460262AE0002AA3062AA0062AE006000000000000\n\t000000FF084E0008000018018010A1051000801882801821800005430E02E00642E1460242A610600604600600600642002000ad2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFFE51\n\t800000041810801009801001D05925E09811000248380010624E04020620022604620E006001906136480089806004002100\n\t00F806004020004007844002006006000000000000000000FFAC58800800003A00C01801C41081AFB8038C180D12C120A542\n\t4E6006C281C6008006D2682764641080748625644601601601283082700601C0180140468140070070060000000000000000\n\t00FFC024000000003841249801A01484801C00901820830080C01600600680C00815400E00E12700E0040078060000000860\n\tC62A304024680E0A4004003006284003006006000000000000000000FF0E8E000800001801021881889000A0180182D80081006d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (061000200060\n\t26008022186006000006246064080000000000000000FF16AD0000000018898818B1802001889841808083800022E6220862\n\t2608E21844E4B639630607600A00E046146116106106540010406016160002016286190006086004000000000000000000FF\n\tB2628000000C18008080048010038058338A380108020020862360964200864C220E0260873160201468463260064065360C\n\t228800641600400041602E234002826006000000040000000000FF47D5800000021828850000841A05A01A81829843084010\n\t215240643620042610204640641600641010621600844001603600B08001600600404000682622400600600600000000000000ed2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (042010040800\n\t03300A82300504080000800000004062460002900900000000000C81000000000C0428000080000000000000000000FF20C2\n\t0000000C181190190180508594980980808180A02265260CE04625250000E02E0160060C60000A6006106516406024000300\n\t00620E040000016556124002106004000000020000000000FFA9740000040018818098219490098018019040018400106002\n\t40640E1020004C630614648641604041604622002004651604002800604600802020600620C0064060040800000000000000\n\t00FF08E10000020018018018058A808982584584001D92A009600000610600601000600640E0060060122060060002A80260001d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF89440000\n\t0000000202004002000040008000000401010000200280000001000202A01000000002800000000000200000000800000000\n\t001002000000009242C0000000000000000000000000FF03370000000AA88C8408C081000C8AA8AA88888881602A204A0700\n\t003224022025C00000002AA0002AA2AA0AA0C82AA0222220002AA2AA2002003D22AA2101022AE222000000000000000000FF\n\t9FF200000000004208500002800000000100200000800041042080A010800400000030012000000000000000600600000000\n\t0000000000000000050000008100000010000000000000000000FF73ED80000000000004802A1020A4000000040022000001009d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20002AB2AA22\n\t210021BAAA22228BAAA2AA000000000000000000FFFDEA800800001200004000041200401000040000000100051020032100\n\tC044004008448020004002804804020004004088000000004004844302000005024210004000000000000000000000FF6C59\n\t908000555951D0B903915835D5584B913911800045628E104094D4C434504004224515556000557556556515556556236001\n\t55655644E00054655641600E556556000000000000000000FFDD6D0000000AAAA8888892902CD08AA8AA88A8AA80002B2002\n\t08200A22210A2B200210228A2AA0812AAAAA28A28A2AA2422B20002AA2AAA8A0002022AA2800422AA2B20000000000000000005d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100018400421\n\t400000890000210010000000050000000000820000800000208440208000000000800000000000000000000000FF58390100\n\t004000404480100120002004C80400420080140C201004081201300002300504080000810010002400008000000C00008008\n\t000800000C0000090000000000000000000000000000FF81EF10000000000000400202000C00000000400000000101002080\n\tA0010000120000300120800200000000000420000000010000000000008280000000000040000000000000000000000000FF\n\t28138000000AA88A8808B08809A08AAC028C88C88061B0300A426446203A0221A0960160462AA0012AA2AA08A08A2AA2AA2000dd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (520308802000\n\t008000D00802815302C0980811204180A4472C0282000208AC0AC2A87000A842022004420460118480000000400001C40001\n\t0008400485000005400040400000000000000000FF6BC2040000080000940A00A00802810804A42800A0005020821060A242\n\t250B002C02006402812008242002A0288202300200280200A20202200080220A802002202002200000000000000000FF56DC\n\t00000000000000000010022800200000002001400008400282000808008A01002000900A0400000000000008000000000100\n\t200000000000000000000000000020000000000000000000FF4BEF0000000000040020004022800000080C408A0000030B08003d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0020020022A1\n\t002082002800002002000000000000000000FFD08C10802000010801001003240000809008024020814004A80114005000C0\n\t010408A10128041240000400440150000550000000010000000808000000800200000000000000000000000000FF4DAB0000\n\t00000008C20E00802C00840C00E088189A218920020430020C201210280200220288308000200281202B0022AA0028020020\n\t02002080802002003202002002000000000000000000FFB854040000100001941801D05805A0980594584B80405048541545\n\t56546D3412430700448E0D641240600600600D04700702608720600622600080E00E006006806006000000000000000000FF00bd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (460524100400\n\t0040200641010000E00600600600C00408600600604601600000000612601400E004000000000000000000FF6CFF00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000600600000000000000000000\n\t0000000000000000000000000000000000000000FF93FB000000000001400201200000400000000001000000500400400000\n\t4004804004000000004000000000006006800000000000000000004800004000800001000000000000000000000000FF769F\n\t000000000002820800800802000A00A4B400A22010200210200A003202222123002402092088002002002000002002002002007d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000200005\n\t891A00245801A414B9089809A040402004040004822A0011000828791528808000600690600650411400F00600620420E189\n\t840086006444804004000000000000000000FF5C63000000200003901800861801429001200A01880000200C04000C804808\n\t238880006000040040026006000200004004016006006004C0600000012688690C004004000000000000000000FFD9E40000\n\t00000005801A40405801831001001811A94080700E40400E1001005004901423121000080260068402400040444060160564\n\t0604611008044E006045004004000000000000000000FFFDE70000000000018418040010050010A91158218000090100104200fd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (070260000400\n\t0E8C6005006006000000000000000000FF8EAD000000002001805800801800805811001000880028AA1400FA140168058165\n\t11A0001401040200600600000120220200600400600704608200A00610EA84006006000000000000000000FFE07900000011\n\t0001801840001C00801B4100109095000014000043160060AC2460404000028004000070060310A000220200683640602600\n\t600040802704C085106006000000000000000000FF622E000000000001821824205804801801205420A0C088910052424611\n\t688410720002030A02003001600602604601202230600C02E0460260001024170450C4016006000000000000000000FF68D000032040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E0426C00A008\n\t41E4026800826206080140802602086006046084006408002816007204012006000000000000000000FFE7E4000000000000\n\t0019540018058210417430410013006406104006004402100046104002046004046806206006002022006006006107006004\n\tA00206006006006016000000000000000000FF247F0000001081000018000038451012210011010540000000104006004152\n\t28004600408210600408E0060C8000082012046506006846000004C00056006846106006000000000000000000FFA7370000\n\t0000208581385EA59BA28C3D07001010A00288A00C6C81647EE00004628800060008800008E0060071468021020262D4407000832040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002044000439\n\t01891800815002C032290010436306145124A06406A0602600E2062440940060260070261060261060030062068020049440\n\t2600714A30A02E000000000000000000FF1577000000000200001834211C003010A400114100835068270843040064460268\n\t0602700610051011700E00110000600600680103620600222000620F00E802092806080000000000000000FFCA6100000000\n\t0004003A00281801A01713400080323022210400708600C00280050582480048628810EC0E10600680208210E00601620402\n\tE05000208600E486082886080000000000000000FF9364000000000002063A808F18015014090B800069201122446184060000432040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600414680211\n\t0086000006000000000000000000FFCAC900004000D802201911803405811821C219000092810550206916A48C8F406848A2\n\t740604E50508702600604690684690680680620600600400600200102E10D046000000000000000000FF09B9000020200042\n\t001800822C408410B0029000089004280524644402600A1C090C233006004A21087006007006006006066802006002C06000\n\t606046806003402016000000000000000000FF5EF3000000008020009808801C27861008285480040105292D00620D00E082\n\t82248608200EC0E00500E086E000C00061460160A200680425600540790688E102002916000000000000000000FF2D42000000c32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (406444416426\n\t42605440E04E10600600240600E026006084004004004002002004004006000000000000000000FF6C470000000018000018\n\t0180000180080180180000000040000060060000060020020060060060000060060000000060060060060060040060000040\n\t02000004000006000000000000000000FF6D4D000000001800001801800001801A0180180000100040010068060008060028\n\t00806006006004006006807006806807007006806806006004004002800004804006000000000000000000FF5DCD00000000\n\t1800233801930001A0588390D8502800C0080610600680000600000208601720604C0161064001000060060061460060040000232040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180000180100\n\t0411A05800809A0564800444801460A6C00148916D5515651654654C156526250120002046926106404154006A2482680620\n\t200400200E000000000000000000FFB25F010000001804001801000819C01908AB3931001000502602E2060000411060840C\n\t6206106006206106A0600600200600E4068440C463400661C002602004002006000000000000000000FF803C000000001800\n\t001C01400001805201945A45080005004F0C6A072A401004709610710E80F50008620625052021200F12700E10A0048A4801\n\t004806802804804006000000000000000000FF994F000000001800001801800801841049801801053010030641614E00C48000a32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (026027206026\n\t807006000000000000000000FFD21D000000001801801801A01C01601C00C09A01808004240500710700601024308C007096\n\t0062080170060000208020260060060040560052A040600600600700400E000000000000000000FFDD22000000001801801A\n\t01A0101100380000180284000028CE14682640A1400884070B6C062C61201465068D030002208E0868864240870040080060\n\t02806006806006000000000000000000FF3D67000000001801801801A01401001C00009A80A8000B22DD2860AE2BAAA86C62\n\t2C22E0AE28F02808E2AE12E68624A31E0A640F8E8026004110406042006846004006000000000000000000FF687A0000000000632040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (349070428869\n\t0000F10E8A82888040860A62B621420D094D004848A68B28A2A46006000000000000000000FFD88B00000000100180180904\n\t5252803B2C521800A00090680600E00608600602828723648920601022600600000008404E20600600000300400084421620\n\t780208E4B6000000000000000000FFE19D000000001001801801001800801800C01800800880680500600600600600100400\n\t6000806000006006006006804006006806000000004000804002806002004806000000000000000000FF05E9010000001805\n\t801801801801045940801015854801A000006806806800042025006807046500006826306046002006026E4700400491480000e32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A000A0120000\n\t046180090049000908500C0080086850900140050080900001080000000060064001A0800029000708040000000A000280A0\n\t000608000000000000000000FF7A4C00000000000800010808C0821100201201000100010200010720038040208200340401\n\t410400A10008006806000001F410D1050810408000280100400040051020000000000000000000FFA7C50040000010018118\n\t0100382180185080888580082261000860060061064C005C0A624A00601000640608E09E004C0E006C0680C004084050C760\n\t84202102286806000000000000000000FF0E15000000201291C81B41311A81A81A00A0AA958808C2ECACB26C4EC368C7280800132040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0640428E0060\n\t06000000000000000000FF7D82004000420D54F48C20C12E04C08C34850CC28A8181348B08328300B22B00B12B0230322135\n\t0881300315290301200208245202A48322302004B8A30130230B2402000000000000000000FFCCDD0000000402440C024021\n\t020028020B2422000C000080212008008000209208A0000820B00801028880861200810800080A00200804800A8080000881\n\t0810828880000000000000000000FF131B00000000090090080484090C800804C05802900800249252200200240200210200\n\t2100082081002002113100082802022002101002014001004462082402102006000000000000000000FF01FE00000000009100932040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02000800002A\n\t82A80A8088320A202A8808AA80282000002202A8200000020A20000000000000000000FF30F4000000200800A00C00B40840\n\t820A10800A00802020A802812822A22802802802902012012A0000300280240280200A8023220024808A2800902802932A32\n\t08A012000000000000000000FFE37000000000020200135020C11420230520320001000A0B308C090080081054CAC08088C4\n\tA24840005004C00024890904004804804804814A4080C000804900A00904000000000000000000FF0FAF0000000018018019\n\t039418819259011030018000006006416006406106D24006106504106000006406006014206506C4600610601400E010406200532040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C0020140AA0\n\tC84002A400202802480082A80102103095002001091082092A82A82A94A82202282A82292A8020000001220AA82A82202482\n\tA8000000000000000000FF1B860000002001543542102D45041102841343500080100C10890D00A20D50930808CC14490108\n\t01550D50D31510C50540D513085503008A8800900D50CB0D20328550000000000000000000FF86DE00080000040000042049\n\t06C040040031000841010080011010014401410400310A984080100080100100080101010000100000051115100800000100\n\t1011900000000000000000000000FFE0AA0008000002A80AA0420000402C80600A80AA00008100002002080882A00000482200d32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (48048B400400\n\t0000000000000000FFF4A1000000000800800800804940800800920A4A800000A00201600622200288200200622201200000\n\t200200204200A1120020020024480A2000802802002092002802000000000000000000FFA8EE0000000000A80AA102040000\n\t0AA08E24608000000411006422AA1898002008082A2480CC0000AA82A80888883212212A8320AA80806004003302A82A8320\n\t2012A8000000000000000000FFF4A70008000002000000840000084020104000040020C200C0220028090000200500010080\n\t320422000000000040000810000021000028200222428000000008801000000000000000000000FFDD180000000000AA0AA000332040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A10A1001000\n\t0010000A10A9009021009009001041019001011001025000000000000000000000FF2DEC400000000C00D00C44820C52C54C\n\t00C20C50902311301221213243314349350A04335344B0A10034020C30021030CB00312301314900B0010032030434030430\n\t02000000000000000000FFF54200000200980180180180180180185380380184022444060442040864160060062040060862\n\t002C612600642C22600648E00C046000406000126006006006086006000000000000000000FF2EDB00000000020300035133\n\t020D20122000900040A2AA4B308C08008004C80482C080880C224A10004804A4040488080480088C004000810A080880008000b32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200004401\n\t2008010201003025020002810854002001010003041024810000E3161003100000100084A800021010043003022000002000\n\t0000000000000000FF391F00000000000180002404004C008021040020000203048440040004401020000400030041040052\n\t01200C625640000000408C020000008020020200000400100000000000000000000000FFDD00000006008801084800004800\n\t88210280B008820234202312918030A6020226030600321020000026020020404120427820020000A0302000092002428100\n\t002006100000000000000000FF8A2E40080000040040040000040052140859040008230811480000280810A10C908820100900732040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4CE006000000\n\t000000000000FF8E24000000001801801009801911815821800901000030000100700604001221200B4062060C6200006006\n\t00020008440608400011434000602000802C012406106056080000000000000000FF2B7C0008040018018010490758ED8EB9\n\t058258B309082502C204642E01206614E0CE3862260160300160060100000640060000942840106060200005824400040860\n\t0E000000000000000000FF884C000000001821805001001801900801851843100200051648E15608648600630602E0CE0060\n\t4022628600612E414156400100404000106208086006000144006006000000000000000000FFD14B0008000000400000200100f32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060060000\n\t2000200600200222588000400000402E036106046006000000000000000000FFCF0C0000000898A98AB80F8018C9880811A0\n\t08AAA0402B62020963062A22264060CE4462062AE0002AE2AE4880882222AE2AA2AE30000001400091C106326204806AAE00\n\t0000000000000000FFD177000000021800801821829801832945950800000000E00E00608600600610622600600600680000\n\t600604602600200600200208044003480022444E1060D4006006000000000000000000FF2720000000005803801101903825\n\t80180980280181200000C245605601210A2520024D614E00604000600640640610C00600400404C090486020100084012006000b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801901B02401\n\tC01200403008702600000600600400601600600000600604640600A006006000048409046841046000000004016806000000\n\t000000000000FFF2DE000000155955155955833925A03B01940105C02250410E10E15645645615645411644E55600C556556\n\t55051045255655655010845055200D55650050044D48F556000000000000000000FF8D88000000089AAB8AB881888889AAB8\n\t238308AD81002A64832264162AA32A0AAD130962A62AF0422AE2AE08E0CE3222AE2AA2AE2040A048400240425622E2D62A62\n\tAE000000000000000000FF324C600000001801801801880811B49A2380284900800164000060061000062061020261060060008b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00000000FF0875000000001003001801891001801801830A3180821040C68A60460A608E256810C2E10E0060100060062402\n\t200960060060044320C000600800630E10400A557006000000000000000000FF2CAD000000001A010018018458358C180DA0\n\t2005A03202400820E31601000610610410600600600000600600600600200600600410601080280080602401400400600600\n\t0000000000000000FFCD090000000AB8A90AB8AB801881A0B0B1C90081800224C240446C062003220022244062262AF8002A\n\tE2AE0880883222AE2AE2AC0062002AB0002AE0042242A40062AE000000000000000000FFB260000800023801001831845803004b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600640400600\n\t6006144124006000446300006006000006006006000000000000000000FF36CD0000000A90A90898A18C58AB841803088801\n\t801022404600E2160162043842A00462AE2AE2002AE2AE0EE28E2262AE32622421E0002A65E00263262642022AE2AE000000\n\t000000000000FF5DCD0000000050010458058118018A3911800811808210C30022602E08808C00C010086006006004006006\n\t00004000E00600E00408600000E00400608E00C14A006006000000000000000000FF57D20000000010030018118250018098\n\t41822945803200404E086086226046046000456006006120006006406006086006086094042000006400296006104002006000cb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (890408888100\n\t08020630E0862061260260140060060060000060060004000060060081060C600010200022204E00A1020060060000000000\n\t00000000FFCE530000000AA0220AA0AA0810AB8298AB0888A8813222800610600608401615428C00E2AE2AE2882AE2AE08C2\n\t8E2262AE20420E28600009200820A0AE3022AA2AE2AE000000000000000000FF985F00000011435411410C90915591584391\n\t2825804244808C0262261264124165442965565562A455655651013054E55644445040600045600410E40648045655655600\n\t0000000000000000FF790480000000000000000082D001901801800805801200013404644E04E28240604452600600600000002b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF1AEA0008000000D0400001841801040801020A33809200D04E08608722702D02290E45600600620080680400400601\n\t20061062569060002C240843220600A102006006000000000000000000FF1C9900000000040400040180D80111000100A801\n\t804288430522602E08E28400004608600680611000600442442000200682E080006000816080883136040012006006000000\n\t000000000000FFA88A0000000AA1100AA0AB8818AB0070AB0C4881801032440441E3064060442882060062AE2AE0002AE2AC\n\t0CC0CE3B22AE21600027E0000060001424062D02222AE2AE000000000000000000FF9B7B000800020200020040001001801800ab2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (41401028204F\n\t2B20043064000B2000106206416002002006000000000000000000FFD6DB8000000004018000510058018C1003848C0D8002\n\t20A20451622600E121A0320609620D00E00101700E04C0082822260020100060401040000864060020020060060000000000\n\t00000000FF0078800800002201A60409002803809041826AA1800286284D0C6006C0548100284600E1011060009068264040\n\t0606201745200CC061010440010070060801D6406006000000000000000000FF29FB00000000A00040000180180300C89110\n\t08C1852310509000601714600C0A808E20602622632C00604408400000B00710302614E40020E00400600650A00200700600006b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5805800024A2\n\t840060260460C61A60260A60042060800860060045402F429608600602650020404804204640600A01804E41000000000000\n\t0000FF79500000000004018000210018088830E2811837860042242C48E00E4166360560DE4060C814667810600616400601\n\t442600604605614040400000202E286052400026000000000000000000FFA024800000000401D441131218058510018A2A01\n\t008090600022648752600800A00441642112E00040F0A400C4C600A80E0029142962A00540C053628604E202002806208000\n\t000000000000FFE08A8000000100018000210018018A508D90080100C210F0C005644E0A402050350410651021608101601400eb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF00AB80000000040200002000000000802801002800000005102800801300102100004500080002000000C0006006010000\n\t1080900000004A84C01000000B00C0108000000000000000000000FFE3340000000004018001018418118010248400418100\n\t00602801620E0060920060D400E21010645000600404400620428610208600E04000C11048C3060460000000160000000000\n\t00000000FFA4CC0000000000018A204388B803849100900001840050E3065261264864020560042A61464360802961240140\n\t0010404600600E54600022000000201610E208000006000000000000000000FF819100000000000180001100B80090501880001b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A222AAA2AA2\n\tB22AA0002022A05022AA0B22222322AA000000000000000000FFD76E0000000004000000220104000A000100100000C00104\n\tA0108080000000080000000221000008001000200200010000508A0800000028000840C00003000900100400000000000000\n\t0000FF35430000000004A880009E8A88888C108008008100602BA1020183006123321902040004422AA0802AA2022AA6E83B\n\t22AA2222022AA00010200224A2AA4022022222AA000000000000000000FF8C4C000000000001800000002042044004024002\n\t00800040440200280001000200B0080544000020000008004006000000000040000000000000040000204010000000000000009b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (808134A02200\n\tE2162AA2022322AA0479022AA6002AA2AA2AA0EA2232AA00200B2AA0000020080022AA20210221BAAA000000000000000000\n\tFFF64880080000020000000000240200340100101100800010040404490000040050045208808044C1004810000004000805\n\t00480000400002800000C00400010D080804000000000000000000FF6F8F90000000015580011194391380DB3313590B8002\n\t407014424224D5654C446D56294017556081D565561561145465568440A655600004E5001255575064445465560000000000\n\t00000000FF01720000000000AA8000A08C88C88888AA8CA8A280022A342A3020021222222422CA00B00A2AA0002AA3222AA0005b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF7A\n\t3D0001000000044000806060002043080802000400020208000000800008020880010000A000000000000000008000000008\n\t00000000000000A08000000000A00000000000000000000000FFD49F09000000040200002212C04801000204402200201415\n\t1028009000008001000045000900000100000000040000080048012000000010048000100109020008000000000000000000\n\t0000FF7E72000000000000000000000004104000010000000100000002002000005008000008054000008800000000000010\n\t80000484010000002280003280000400B0020000000000000000000000FFE6B88100000004A88000888008C08208A88808C800db2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (680780700600\n\t6020006000A0E006006206006006000000000000000000FFFB2A0A802112000810820A00400102141900B40B08A0A88208E8\n\tCB00000830C243040A180C0243A86A44888445740040A09040040450000042A8000080004800404004400000000000000000\n\tFFB7370A00049008008008008C08408908C4C50940828010282220200A2B24C210243221215208A400212212002002002802\n\t002002022800002000002003002202002002200000000000000000FF74860000000000001002102000000400000020040040\n\t4000000001008000004000001004008001118800000402A88408000800000000400000008000008000008000000000000000003b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (003002802002\n\t08280280000280A802002000042002002000002002000002002000002001002002002002000002000000000000000000FF68\n\t530AC04103001001000C0400000220004104080200110210C094008008408440008C0008820140D001080000400011510008\n\t00000000000428000080000800000004000000000000000000FFE938002000808800800800824C00E00C008048008100C028\n\t0210200208280200246200200219A41000200200200200200A00200200200000210000200200280200200200000000000000\n\t0000FF3BDD140005801801801A899418419519457533430540546A57005816556547147C54496D2E5164101160170060040400bb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF877A00\n\t0001800000000021841011801883809905080005600600800600602400401240408600640000600002600622648404E04600\n\t6000106500006006086084040006000000000000000000FFE41E000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000006000000000000000000000000000000000000000000000000000000000000\n\tFFDDB80000000010010010000002000004010000000000004004004004804004001000004000800000800000000006000000\n\t000800000000000000000004001000000000000000000000000000FFAD62000080800802A00A00A008002000898008049040007b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (054016026000\n\t006240106016107106800006000000000000000000FF20B80000058000040240018A100583D911903C830020442022084062\n\t89240280600620480691620048600420602E00610400402620600008608054412211F503004026000000000000000000FF30\n\t59000001800000300001A1120181180B801029000018204800C8021008A844F00600600608600800688400620080E0F40060\n\t0640600000600001C006016006024046000000000000000000FF8013000001800010020301905001C41809A0502905204075\n\t128C644681228C8944820C54268D604810612048625001600400400E0460010060210840560060060000060000000000000000fb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (830AC0420025\n\tA40AF340084A8E606160006002207006A1E042024046006000806008C47712206012004006000000000000000000FF9F3700\n\t0001801845000001E41C0100141180D001E02022A12032C2020208260D600880752612600021600240F02000608204600600\n\t6001006001006006406406080006000000000000000000FF4FD8000009801820020601013901241801A454358080106A4320\n\t020E2420142058B000402604610009680400E02182602200404600600080600080601200600A084006000000000000000000\n\tFF62DD00000180181008012140B811201901811C018C8024E30604120600EA062A42908A43460360200060440C600644641200072040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF6CEC000001\n\t841821880461841049C03B4101E004100001C2C0404024200C668D60A40866260263100662027A660000618200E0A6186000\n\t22620012E02A20610302E106000000000000000000FF5247000001801808C000010016118058098402010220004801016D44\n\t4A108650600404400611600000640C8060062C6012016146006000006000216056506007804006000000000000000000FFAE\n\tE1000009801810842001009081831801AA00418000084A0600081420E00E40640410401600E0000878048060004460020060\n\t06006000006008086806096086004006000000000000000000FF807D000185867989000201825805205D01C09015812000A000872040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0600610000E0\n\t0188600210600300E046000000000000000000FFB993000001849B30A20485041801908801801049800000000EC971202060\n\t0E15402E10001700620005600210620600600E204086006020046400816523016402A46006000000000000000000FFD61F00\n\t0001801808800401001A00C40811C2150D8A2028004E426B0112E506054007022806A9610808702300602105601700400700\n\t6020006000506102836082006086000000000000000000FF894D000001801821880001801801821801A81891010048449094\n\t4004808806007B4408404624640008602282604600E0028060068060C044640004608202F80205602600000000000000000000472040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (810440600600\n\tE14008600E40600002600600600000600630600600600002800000E40600E206000006000000000000000000FF4B89000000\n\t245B15880009800009805852C05881844048040C48080C94643614700E006C460A620020EA0608620700600E816006006020\n\t0002001060A6007026226006000000000000000000FFA613000001801A43A4814181DB08B008AB91305082202C1207004048\n\t0262268050028000270A600120620600600700600600E106006000006000006002007022016006000000000000000000FF13\n\tD5000001843801882029AC38C3802F41B884808900020020114000080006404482003206206000007016006001506006086000c72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (EA0000000018\n\t018000018000318038C08018C18C0040201440E24402600648E09000402420620840603208600600200600600E0060004000\n\t00004026006006006006000000000000000000FF7D0500000000180080000180000180180080180180000000040060060040\n\t06006006006006006000006002006000006006006006006000000000004006006006000006000000000000000000FFED2F00\n\t0000000800800001A00001C01800801801800000000500680680400600600600680700600100680200600600600680600600\n\t6000000001004006006007006006000000000000000000FF6073000000209A0180C203140003809B0080180188000048440000272040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (608000001000\n\t601E00E817006000000000000000000000FF7C67000000000800800285001401851694C21C0584004424545411403440D645\n\t7446556A44C5655115604400612800042611601700E040000100036006006006000006000000000000000000FFCD2F000000\n\t0048008821812009019A1090801821808000228602600680C80600600080400402610004640401600600000700600E006000\n\t000000E04006006806000006000000000000000000FF56FD000000001801882201020001C4980192D80D80A11565448C010C\n\t50834E844220156B0D0D60401061020464A950A00650600603608008000008400E00E006806006000000000000000000FFD800a72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004006806806\n\t116303004801406805006846800006406006016000500000126046006006006002000000000000000000FF5D87000000000E\n\t00601000A01A01A01081821801800000620D00582000484401720200E84220748000E00400702900040600680600E0000000\n\t8100E006006806806000000000000000000000FFF44F00000000180100900380380101180BC01A059200C4604654C0842A6A\n\t97C4605052600B04E05032602228E08002A0A688E00F00602000000800600E00600E006002000000000000000000FF6B6300\n\t0000001801011001A05E81001829D89883980022202C29D2AD2A0EAC2AD2BA02623A28C2A94A62AA5BE28F2DA1060868070200672040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000023429221\n\t12ADA15A41A825098C9B018000C2280682C057244CA484E82AA04926C160012C6808046A08CA401608608703600024000002\n\t488E086006C8EC2E000000000000000000FFF49F000020001021003201C41883C29805A03851800008E0A720430408800850\n\t440102041602600000E32430608000408604E056906000100001A0C4460170CE046102000000000000000000FF7C6B000000\n\t001000001201801801A018018018018000002004004004000002004002002806006000806804806006004006006006006000\n\t000000004006006006806000000000000000000000FF1F5D0000000048000010808418518350018C5811844011600480400000e72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (500000000002\n\t002902012002000000000000000000FFCF9700000000180580185404400008000A52002800000440208040140042242A0A04\n\t004240024000A000A10101061100000200B00A8000A800000082290080A0008124000000000000000000FF94730000201080\n\t000000020001220781400404900000100480400E083100480005680004100100000880093806DE2810090C08004400000400\n\t00061001080C00560080000000000000000000FF57A40000000000A810F00190185180209128190180000A20042440000841\n\t8400E0161040AE00600000600080600602480680600E016000020000E0644680601608600E000000000000000000FF335D0000172040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (461465064060\n\tA601600000600E88E0C408600600E00E40600004000004650E00650630E006000000000000000000FF4D75000000400C44C1\n\t28C0D40D14D48C80822812800122300B00201354B50340B83314340BA02001C4300200241301208284240384A00050000140\n\t202280202B043282000000000000000000FFF5BB0002002403422103082022802004010022400000A00800108840C08C00D1\n\t0000820801608000060A10001001000980810801000000000000804994000848A00E00000000000000000000FF1777000000\n\t026800800CA003880490080020C804800040A0120230A206200204200264210200200040200202300000200200B40200200000972040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0880AC0AA082\n\t08808800400000400200002A00008002A00000002202200B02A82A80002A8A002A80882A82200402A82A80002A80000002A8\n\tAA82482002A8000000000000000000FFDE1E000000204800A00A00A02C40D00B10C20950800080280240200294288290210A\n\tA02802002000002042802A22802002A0A802002000000000902002002882912002000000000000000000FFAB990002002202\n\t0420023124040242A0453154010000810CA80D080CC0CC310080008110000000000048880048048008941250040040008000\n\t00C34804004844841000000000000000000000FFC02100000014590190180D815841801A319019418000106406D46444004000572040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002308010002\n\t10008000000000000000000000FF51610000AA0A80CC0AA0AA0AA0280AC0AA0A812200003002402802A00302002A82082202\n\tA82A8000AA82002A82A82A8228AA82A82A80002A80002A8A282A84882402A8000000000000000000FF0B7600015435215035\n\t43502423122C82B02404B00000D40C00529548AC0C88C804C1020D51550000550528D50110550540900D5055000055000090\n\t0550550900CC0550000000000000000000FF2F20000000404600400400400402400400404608000103100105181150115100\n\t08C1011001800000800001000001001900001001800001000001000800001001090000000000000000000000FF5AEC0000AA00d72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080490480080\n\t4000004104800204804914000000004000800000000224004A94C04000000000000000000000FFD327000000004804800800\n\t800902840800810800800000A00240210214208200210A00200200200000282A002042002002002802002000000000802012\n\t0020020CA000000000000000000000FFD1A50000AA0880800AA0AA0AA1000880AA00000800002801100002080002002A9220\n\t3282A82A8000AA93502A98882A8220AA82A8AA80002A80002A89802A80600002A8000000000000000000FF38820000000004\n\t0000000208802000000208800400000080C8800000010020028808280000000000801000001441001010208000800000000000372040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010005000004\n\t0042044840240008000810810092D10102A90D92812050010084092010094210410014010010014000010A00016011053010\n\t81001000000000000000000000FF4AA5000410002C00840C00800C10C54C00D24C1095003431031130834C20CB1035334334\n\t5300A00951301308300300300308B0030024110C0001043003003003103000000000000000000000FF31BD00000001180188\n\t98058219431019098018A1800000624602420400620640600408608610600004644602608410600640600E02600000000000\n\t6016236114006000000000000000000000FFDC710000002202312002002002312052004A32C300008414A88D4824C088308000b72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (608605620020\n\t4000000000000000000000FF92780000000000020500820520000440A000005000000002001101204202402102A024048024\n\t8000120020000106010100000100000000000080000400000400080100000000000000000000FF197E000000003801829804\n\t0000B000C0200C0040048002044412402424C00000402C148544000200030240300126000200090010020210000000020080\n\t040000080000000000000000000000FFA750000008008800080880820812890084900988804020210200200A092102322002\n\t10001A18240008200200200048240231200220200010000000210A08A00A400000100000000000000000FFC931000400000400772040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02610A406000\n\t00613600404608E006004006006000000000100006006000128140000000000000000000FF1F1C00000000000100800980D8\n\t2182090184182180000040120040042040240C60400464000060000060061040000062060840060060000800000002060060\n\t00104100080000000000000000FF544E0000000000010878098419A3805800821903884018C00E00600604041803400C40C0\n\t6445600010E2460A03000061060040060060800000001820061AE180064018000000000000000000FF2FEF00000000000512\n\t190580180B80982288180D900000C2860880A000A08420429409409408620002E40604040640E00600C1060061000001000000f72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002982580180\n\t9211801801800004400210401408610280600712E00E00600000600600200008600600200000600000000080500600600602\n\t8000000000000000000000FF5049000000089AA80AB9018218E08B98918AB8AB800022640E00020010E0C2054004E942340F\n\t60002AE2062AC2C82162AE2AA2AC2AE0000000004042AE2AE2AE144000000000000000000000FF6061000000005800001801\n\t90D810801801801801800001428642000008600220408400C006016000006006004006046006002004006000000000234806\n\t006006404C08000000000000000000FF8BE300000002000500014B80180580282B801801800010604210C14C242430154448000f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AE2AA086200\n\t000000000000000000FFEC0F00000000580280000185580004194180180180000060944064C64340124040D4006006006000\n\t006006004206106006002006006000000001026006006002400010000000000000000000FF45CE0002000C1B009519019099\n\t541258A1955955800051655425022020C42E55442C40654655600055652E55453044E5565525565560000000015565565565\n\t52485548000000000000000000FF6DF90000000A98A90AA04B88188D885C038AB8AB80002AE04212C0140063020842001462\n\tA43060002AE2AE2AA08E2462AE2AA2AC2AE00000000008D2AE2AE2AE0102A0000000000000000000FF7EDB00020001184D00008f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C60060000060\n\t0605200600600608E0360060000000000C60060060120A2000000000000000000000FF28F400000004588080185588080080\n\t3801001801800044E00010E14E24603200244C00410E00600000608E00220010E00600600600600000000000680600600242\n\tA140000000000000000000FF712E000000009805802001845001049909801801800010600442400408400600408600E00600\n\t6000006046002006006006002000006000000000006006006002002008000000000000000000FF76930000000858298AD885\n\t8090AB081E278AB8AB80000062AC00430404E2872AE1002A62262AE0002AE2062AA0A82262AE2AA2A82AE000000000AAE2AE004f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (805805001841\n\t001801000000005400408602000600005600410600000000600602E0460060060060D4006000004000006006000016006000\n\t000000000000000000FFFD100000000898AD8000018908898A98890AB8AB80001062A000410424622612000E34400E2AE000\n\t2AE2AE38608E2AE2AE2262842AE0000000002162AE2AE332242000000000000000000000FFBBF000000000180184200100C8\n\t03805825001801800001600020404402601248210611420600600000600600644000600600600000600000000000E0060060\n\t82012000000000000000000000FF09080000000258048898D384084080180100180180003260080B650E096102010224044000cf2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A241E0000000\n\t00000000000000FFF73B000000001A0081090180180502182100180000002040162A401620000640610600600A0060000060\n\t06002000002006006044006000004000122006000004006000000000000000000000FF197C0000000AB882AB08AB08988988\n\t388B0AB8AB00002AC20602C23608800E2AE3062AE2022AE0002AE2AE28228E2AA2AE2364042AE0000040002022AE2A82260A\n\t6000000000000000000000FF9D25000000555B51D4203592595188D915155955000003054401444011055602842E4144C255\n\t200055655645655055655654E48C55600000400040655655044450E000000000000000000000FFC0FB000000001811804001002f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20090A648704\n\t400804400A007281106000100000007006001000005000000000000000000000FFDD66000000025802888001001831805A25\n\t001801000000402609650809400C08E2220070820000000060060844060040020161448060000000004A2006000000104800\n\t000000000000000000FF4ED9000200201A01842801805805831809001801800080080D246040821546000102002045002001\n\t006006802000802002106C1000600080400000B006800012446000000000000000000000FFC9CD0000004898E98000AB8E98\n\tC18D18810AB8AB80002A838450600060054422600A2AE25E2AA0002AE2AE22A0AE2AA2AA3260042AE0000040001522AE2A8300af2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (218018910419\n\t01914050A20128740320210E0440262464430D6140C8650614408842400A04F00280612000208010C0060A88864040000000\n\t00000000000000FFFF85000000003C0100114484010582580D4918018409A2202432522104F88608420002603300C0200060\n\t0648A0000130438160460060004020022060078A0086004000000000000000000000FFFC74000400401A014310A00200CB88\n\t3A43089829934911303501C80B02680624411948340904610140605E80210740A02204702688614120210211680701000640\n\t4800000000000000000000FF3AEF000000401800E20801801811881901021CC9000000420100680E40421640902388E10608006f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (014000000000\n\t0000000000FFE244000000080001041000989949801801801801808000600409401008600022408204A01C40A00820608620\n\t44804240040260040060000040002020A6000052000020000000000000000000FFF73E000000200403481004801883863061\n\t8A1881880004E0940442C2236682114702032120082030046266494206004004086504006020104000482206000022008280\n\t000000000000000000FF976D000000201A4002380A801821801883205A03800004241000E03600202E11502F086282246200\n\t02E0070040062149120060020064000020000050164B0092005000100040000000000000FF1271000000003800209800001800ef2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000028006\n\t080010000084000000004002440000000010010000000000000000000000FFDF280000004244040880280200800D40040000\n\t0000000102881080300003085400000005400000000000001000260081000000100000000080000080000004C00A00000000\n\t00000000000000FFC87F00000040044228580580180D84394592588188000362080061062464940044101060061000400264\n\t0610010601008C026000006200000000506486008002000400080020000000000000FF7B8100000010000140180900980180\n\t180180180380880060861064421060244CC12000E4C203241040E14620000004000410600000604000000200004E2A008201001f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C8888AAC8280\n\t082A2302242402AAA0328AB2922AA0A292A0002AA2AA34208A20322A2AA22A2AA00022A0021022AB0000CA2AA00000000000\n\t0000000000FF848000000020022000000000000000000020000C00000D010100040003003000005023108008800080100000\n\t0001020088000000800000000000200000000288100000000000000000000000FF465B000000288CA8C008068808369008E8\n\t8AA88880002B20022020022A20020022422020022020002AA2AA2122882322222AA2222AA0003A20000D62AE000402200000\n\t000000000000000000FFA33100000000180184388001200800100000002200080040240403040140440141480C8008148000009f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF3C44000000088C208AC8808848AACAA8AA8AA86080012830022AA113202203402202002082242001AAB2AA38208A\n\t2022222AB9032AA0002020000422AA0000022A2000000000000000000000FFE9F90000004002024041100000000200044014\n\t4800080008548910C8800500A01004001408C000010050040002451411000041050040000000024050048000040040000000\n\t00000000000000FF24F6000000555915F51955949955955955D558818000406C2C55782650748615650410644E4060005565\n\t5645633451644755623455600155600008DD56000044456000000000000000000000FF6C150000000AA8A88B08408AA8C080005f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00800290040C\n\t00800080000000000000000800040000000000000000000000000000FF182F00000000000000000000062820800810000000\n\t00500000000000000420C60400008200200000800C0080000008802800000000000000000000000020000000000000000000\n\t0000000000FFA3F600000022421200000405400040000000010A0000010A880008301089485400A834023004800000000005\n\t0200090090800410800000100000081000000008008000000000000000000000FFD204000000000100202048000000000000\n\t20000000088200200003008200010100000080001000000010000000200400000000A000000085000223000000034000000000df2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (955913840105\n\t492690754491692DAAD10C81680E5564514860068060042AE206006084000000200000006004426006006000000000000000\n\t000000FF73920200800000A80822030224424003C16030816940C0CC882848140400AC004CA42004298042A800442C004534\n\t000058000404000000000028004004005004004000000000000000000000FFC2D40000100C08008008908808008A08049049\n\t0882C00223020020C2093002002012002012022200082002002002A028028022020000002000000030020028020020000000\n\t00000000000000FF689A0000000000000000000400000043200480040000208040100410040888508280000000108030400A003f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFFE33000000000800800800800800800801080800A0002020020000420832032422020028020128280422020020000020\n\t02002002000000000000002002002000002000000000000000000000FF507E0201000040A008220410000200008000010028\n\t000880903000050000C8000000200028800A8000004900004000000800000000000000002800000080080000000000000000\n\t0000000000FF5CA1000000002C108008008C4800800800804C00800000280200202208200200214200200200A00102200200\n\t2003802002002002000000000000002002002003002000000000000000000000FFA614000010141801801D11941809B5581500bf2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (65010040CC20\n\t400C000100200000446142007014356300000000000000000000FF33FD000000001831800081801801801021801801822002\n\t440E1060080024024021120120004060A005601604604600400404400010002000000010600200E004006000000000000000\n\t000000FFE41E0000000000000000000000000000000000000000000000000000000000000000000000000000000000000006\n\t000000000000000000000000000000000000000000000000000000000000FF62890000000012000014000012002000000004\n\t0000000050050000000040000000010040008000010000000000068000000000040000000000000000010010010000000000007f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (05800003440E\n\t10600800614354000315412609640008603610610600202220200200004040000010600201600E5464800000000000000000\n\t00FF96E1000100011841810029827811829001AA1A518220240802A06A4658221700F30D0428122460E006E0460262268940\n\t040A40040A00C00000002270B282632504E000000000000000000000FF68410000000019A180025180080580100180182980\n\t8009082240E0243041060060A420400300600000608600600010408C10500804000000000000600304644400600000000000\n\t0000000000FFAE04000000041A01800001AC5800831005B51A4D8080504046816C2020004214A4225408C00964001061460800ff2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t7CC0000000031841911061801801883C01C21A1181000C008A18608614601229086360C09404600100600600600600200300\n\t200600004000018001E0020A6006006000000000000000000000FF91CC000000025813E01001808801883C01D21C21882190\n\t6932806145C0604200040204F02400602804684E00E000002002082002000000000000006082306406026000000000000000\n\t000000FF0F3900000000390C880401811801801881881801914000C2460072000470A3050A0300442680600900600E016000\n\t002002082806000000000000007103206406006000000000000000000000FFA19D000000041C08800481D0180380184380980000a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08208A202004\n\t0000000000400060068060C6106008000000000000000000FF3931000002000001003801812059029F210558258000310014\n\t097084256CCE00420600E82225654808E0268161C001A00201A00408000000002040E0068060260260000000000000000000\n\t00FF2B7300000A000021000B058010810518410018218080024004104824504906A1442E0260C200600010E0460460060020\n\t0200200010000000000009782CC8720D246200000000000000000000FF266000008000010100080180300900190100180180\n\t0000CA04804404004086524906007302006000006806006000013802802000000000000000006008046084006000000000000080a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (808862004040\n\t4024724B01A043046002026200007037026040006106006004000000000020506044107516406010000000000000000000FF\n\t4EED000000101901802C11A01905C008014818419000404010044003926086546096C2F12608E01000600600601600600600\n\t6005000000000001407106516104006000000000000000000000FFA37E000008001A41C00B0580180188080522DD11808013\n\t4D1005480209620754600E20610E03632000720604E000086016206004800000000000806814406805106200000000000000\n\t000000FF3D07000000000001003801A03001501805001889880040628442690600400E0A400640E01240601000620E0060060040a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF7D77\n\t000000015801A00809A01901801000C034218000A00000802000242022022016203006016008006006006000006006006006\n\t00000000000020200428C006006000000000000000000000FF8ACD00000010190BA01801A218058210109110118940116212\n\t0400869003125021008D0924146B0080682700600E8060060060060000000000400120060042862060000000000000000000\n\t00FFF525000000001A63A05801804801800B01009809802000F8010040820070200130020860030060800060070460060060\n\t0600700400000000000000E106006206A06000000000000000000000FF112500000000BA09801801832941820989203E059000c0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060164060000\n\t000000002C6A26AA4006006000000000000000000000FFD66100000000000180180180184481188400182D84003500464940\n\t80008404002000004086236000222202006006102006026006400000000000002006004006006000000000000000000000FF\n\tE0D8000000001801800801801800001000800001800000600200200600600600600400200600600000200200600000600600\n\t6006000000000000002004004004006000000000000000000000FF86BF000000001A01801801801800001400801001800000\n\t68020008068068060070048000070068008028020060068060060070060000000000000020060040040060000000000000000020a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A2AE22C8EA23\n\tE2082E92CEAA50862D60B13AA0B21AE057482106006656208000000110023102004006006000000000000000000000FF5C23\n\t0000000002018008012158000C5E04151801B140806554814516400414492284CC45575062A140C14504E001003417006106\n\t000000000000006000806005006000000000000000000000FFB879000000200181A018210118009238A00018818A40020004\n\t80400000008480200485480600E04001410404600600200600E0060100000000008020240068040060000000000000000000\n\t00FFC2BB000000000401800C21A01A00223820483881A80100028C0260305200B454B2C830604408650010202250E000002000a0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF154C0000\n\t00001800800001011A441110051058058000006000904806107040084844814046846400004C04C070068028060460060000\n\t00000000506C03546806006000000000000000000000FF699E0000000018018010010018000010032018018120802C810040\n\t0300600000D00450408D147D00805005046008003406006006000000000000007002004006006000000000000000000000FF\n\tA98B00000000180000200100BA000A500113180190010000540164C840A408C242A6046246C0E02828A14A88E02020288E80\n\t632E000000000088802083006006006000000000000000000000FFCA86000000001801005401000A000010014018298020280060a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (602600000000\n\t000006640200E00C006000000000000000000000FF5918000000245B02A81229201B02B0120123181380008C3050C34C2303\n\t0C02800804D04B0F0AE000D20A804C6080884306037246000000000000C26902D27204906000000000000000000000FFE05F\n\t000000481840C242018B30286211450838C18000210304086110B0008E3280A0026026206000004024006000024006106016\n\t00000000000010E20200F00D226000000000000000000000FF8AD7000000001801800201801800A010012018018000002806\n\t004002000806000006004006006000804004006806804006006006000000000001802002004804006000000000000000000000e0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01244A002003\n\t003002042022402000002282803000102103002002000000000000002042402000802000000000000000000000FF40770000\n\t00081800113A00012001000420080020000124400000C2844C5048E044C42842040A80000201708800060400000805400000\n\t00000000A04010840200880000000000000000000000FF4E8500000002600006000000018804000000A60400000204200C00\n\t00101000030100110448000000500400A50006081080100208000000000000080180280140220000000000000000000000FF\n\tB8C80000001019A08840111A98360B10010218C9800040E200404036030002040004004094006000000000026806004E06860010a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002A00000000\n\t590180580182B8018C18A9801805800044600400E00621410401415440640600600044E00E00680410600E406A8600000000\n\t000000632C02600E026000000000000000000000FFC49D000000510C40D28C14C80C92C10C00E20AC08001903343AC352B14\n\t2022A2220313305340200110334285200B0424A2123042000000000001843003C13522002000000000000000000000FF3CC2\n\t0000002002002000002002002001822404020000000984B20900A08380089030C20800A00000AD0800001090820850C09000\n\t000000000000008A00030C10040000000000000000000000FF0DC100000001084280082C844800900851000100800018204A0090a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t001041001001000000000000000000000000FFD97600000008A0A80A80AA0880CC0A80A82AA0AA00000002A8210000018000\n\tA202000202002A80002A82A82A8AC8A20220A202A0000000000000AA80002A83402A8000000000000000000000FF1C900000\n\t00240A00800A00A04A02A00A00800A008000152802822C02822C0A10A8D228288300200100200200200210A91201200A0000\n\t00000000002C82802802802000000000000000000000FF9AA800000020020420220024024020220300100100004008040891\n\t28C848C4004804810849004001001000004024800804884004000000000000000834001154804000000000000000000000FF0050a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000100100\n\tC0AC0000000000000800800000090080000888000000000001000028000000000000000000000000000000FFA9A300000008\n\tC0A00C00AA05200C0A80AA2AA0AA00002202202A8280280200B002080482282A80002A82A82A80882292282200C000000000\n\t0000AA82882A82A82A8000000000000000000000FF6C290000003503141543543303103143501541540000440D40C00A30D2\n\t0AC0CC0C10010D28D50000D50550551311440C50D48440000000000000550A80D50C08D50000000000000000000000FF7F59\n\t00000042041260C40050048040400000040000018011010010510480D004914180110100000100180180124110000101080000d0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000200234\n\t2012002023084022002014010000C048308008C0C8088804484881500900400100480480482480C108804B44000000000000\n\t004825004800804000000000000000000000FF91EC00000000080080C8008808248408008008008000152002002012022022\n\t11210228204200200000200200200200280208200A000000000000002512002002002000000000000000000000FFC6D30000\n\t000AA0800A00AA0280400884AA0AA0AA00001102902A8200009200A002005202802A80002A82A82A82882A03203294100000\n\t00000000AA80002A82A82A8000000000000000000000FF4F62000000004020400000004000040002400400000088801012010030a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002000000424\n\t000C2012000000110000000000000000FFEC1100000000002040140A00000040E40040452002A10012910311A10092012090\n\t21241081080109009241031009001001001000000000000001011001001001000000000000000000000000FFDC8D00000000\n\t0800D00C00800810C00D10C00C0894C142B00304343334331340B14300B4834D241100341344301301300B50300200004000\n\t0001003023103003002000000000000000000000FF568E00A00005582184180B801801831845941841800008430648600600\n\tE02608420E3040360060000D6006006006006086004006000000400000006006004006006000000000000000000000FFFA1E00b0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (640612031624\n\t24022D642000600E00600200604400200600000000000000602400000E444000000000000000000000FF7317000000000100\n\t00408A05008C0840218000880040040040200048500010110208000040100140020008000006100000300000000000000000\n\t000020200020040000000000000000000000FFBF090000000218010A18000000090010899240101000034008004404544148\n\t080484008454230280120030010006010108284000000020000000010020004000000000000000000000000000FFE92A00A0\n\t0000A80080000080084087082680488484002821023CA00A00200204204A5E600240200000200220200044201204241201000070a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018108050\n\t0188484B80180384580180005340042B240E0420160024024842B20060000560A600604600E0040040060000000000000060\n\t10130090004000000000000000000000FF1C250000000018018A100580480310380180590580000042040083062220062060\n\t000160440060000060860060002260044A420E008000000000026004420044004000088000000000000000FFA60800000000\n\t18008A1011852910041849809811844000E24450A2861262762120C210821802E30004608600600410603400200600000000\n\t0000006404180006204000000000000000000000FFCC65000000001881803081800820009013811801800003008402602E0000f0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00002AE00202\n\tC2802AE000000000000000000000FF7FBA0000000048888410008C880000180180180180000558A600001200200400A4C000\n\t600600600000602600620000600200600600000000000008E00E004004006000000000000000000000FFCD6B0000000AA081\n\t8A80899118000898898CD8AB80000000BE1028260062362B01A01081462AE0002862162AE6CC2A62AA2AE2AE000000000000\n\t2AE0101042602AE000000000000000000000FF4E27000000000025C00043848900243841801801800000040600610628E106\n\t00A00E04200600600000600E0060020060020060060000000000000062A4404004006000000000000000000000FF72FB00000008a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0440A022C2AE\n\t2AE00020620E2AE0A83A62AA2A82AE0000000000000660402AE2AA2AC000000000000000000000FFCECB0000000218200028\n\t5180500184380180180180005060C60505405041040020020060040060001060860060061060020000060000000000000065\n\t44402016006000000000000000000000FF30FE000000151822012955805955D559558D195580002804165572A02D452C3020\n\t1654E5545560004D648E556130456552550556000000000000406504552556556000000000000000000000FFF34000000008\n\tC08A8A90820208AA089CAB8898AB800005420620201202A2242A2448A5420E2AE00022E2262AE08E22E2AA2AE2AE000000000088a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000285180\n\t1801801801801801800029600640601000800C10A0860C008600600000600600622600610610800600000000000000615200\n\tA00202E000000000000000000000FF987B0000000000000108018A184B801A01011801800053600E09640804008C4AA40690\n\t000600600002E08600640001600600000600000000000010E002002002006000000000000000000000FF1C970000000418A8\n\t00580180D001801805943801800000410400010428C00600600A004004006000106026006006006002000006000000000000\n\t406530006002006000000000000000000000FF2A6000000008B8025A18AB8010818AB8A98058AB80000042242200240042260048a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5565445524B4\n\t034000000000000000000000FF115F00000000B80180B8098000030010018018018000214006010080004002502056002454\n\t006000006006006006006016004006000000000000006006002106004000000000000000000000FF6CA100000003D8A80AD8\n\t118438078098AB8AB8AB80004043040062A02A02A400400E0080062AE0002AE2AE2AE08E2AE2262402AE0000000000002AE2\n\t122A6282106000000000000000000000FF014B0000000038020019038C98B194580100180180000440D41480000000044464\n\t2040022E00600000600600600000601604000600000000000000600200604A484000000000000000000000FF98830000000800c8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (082060042AE0\n\t002AE2AA2AA0AE2AA22E2042AE0000000000002AE58637A4022AC000000000000000000000FFA268000000040003C0080180\n\t209102080180180180000840260800020081260A60802C800600600000600200240000608601600600000000000000600400\n\t0004204000000000000000000000FF96690000000C00538C18818320B10AA8AB8AB8AB80000242AE2A02202A82AE0262002B\n\t40862AE0002AE2AA2AA2AE2AE2A62D62AE0000000000002AE02E20002E2AC000000000000000000000FF8802000000501951\n\tB5094590804110D155955955800004C41644854A54441241242E00232C5560005565565561505564565045560000000000000028a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800A05800C01\n\t803009801C01800100E08700531410614520500620E087006200406455104120003027006006000000000001006004004011\n\t804000000000000000000000FF569D0000004018ABA21803A2C001801001A01801800129600648403512E004524080056086\n\t80600000600400400600208610E006000000000000806024804148004000000000000000000000FF8B690000000038018008\n\t09800031801001801A01800004680604C08600400400442708622E0060010068030024000020060250060000000000000064\n\t16102402004000000000000000000000FFE4780000004A990188B8E59800838AB0AB8AB8AB80001062AE0042142042AC01C100a8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B64864828260\n\t00140400000000000000FF9543000000401901801005800C0180100802182584210A400048E24C5004B0890C420C04161461\n\t28446444CC408604200692400600000000000088610600A006086000000000000000000000FF7E2C000000405801E0000180\n\t084180100382190390A810602020200700A0000A001312120E1360D013600220200010200608580600000000000248610604\n\tE026006000000000000000000000FFFD5B000000203801A01401A00821803001A01C418C09446E001120454424100105CB00\n\t004680E00108F0030520060C2006044806000000000002A0600682200F106000000000000000000000FF3E890000000019010068a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (628E44E41052\n\t62004000364B4006006006000000000002086106084082404010000000000000000000FF2E9D000000201801801041842801\n\t889001851801800000628441204640E00E00602A02604610600008620420422008409600600600000000000000604604400A\n\t244008000000000000000000FFEF8D000000001801C0102102080380300580990183004361440021240560064CE28241E166\n\t20640000601409404600C246026006000000000000086006020042004000000000000000000000FFA1C70000000010018A80\n\t11808931801008021D21800001402132EC8CB002A0400002D00D0E8B641023600400401022300E004006050000100040006400e8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2214304000A0\n\t1180000000081100040040A40001001000140540800000000000400100060000001100000000000000020004800000100000\n\t00000000000000000000FFD9B800000068000040408001000404000180000000000201080104080300100084A00804300000\n\t000001080C0006088000040000000000000000000010110320108000000000000000000000FFA11F000000401A01D0001080\n\t1905885008001841800002400600648408600210208200600600600000E00010040000448604600602800008004000641620\n\t44120040000A0200000000000000FF2693000000001801829000815829811000001901840800C5260C600C01655221244A4D0018a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620455600000\n\t0000000000000000FF9B990000000C08AAAA88928888A88880AA8AA8AA800832A20A2A200221222223208A2A24022AA0002A\n\tA34B2A20AA2222AA2AA2AA0000000000022AA0022422822A2000000000000000000000FF3325000000240400040022008400\n\t20900000000000008000010010808000080802002200010000000000800A00000800010010000000000000010000002B0090\n\t000000000000000000000000FF007D000000028AAACA88088008888800A38AA8AA80002022222B24022C2332322402202100\n\t2AA0002AA2022026AA2222AA2022AA0000000000002AA472220052220000000000000000000000FFCBA900000000380180180098a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000090\n\t140200010000001000000000000002000000408120000000000000000000000000FFCC980000000BCCAAE068B0CC08AA8C08\n\tA28AAEAA80002AA3A23422223022022130030022AA2AA0012AA24220A0AA2222AA2AB2AA0000000000012AA2AA0220422AA0\n\t00000000000000000000FFCC4500000040A20020204004440422500140140100090001208011510800040048400110550040\n\t0100500081000110800480100400000000000300410108C004014000000000000000000000FF653500000050195591190190\n\t3955903955755B55800055745741745642E52444493610ED57556000D56C1640E356C57556556556000000000000556556800058a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (204008804A04\n\t00000000000000108040088040000080C20020000C00000810000400000200080000000000000000808C0800800000000000\n\t0000000000000000FFA65901000000400000000000000204028020228000000008280002D0040200208C0000800800051080\n\t0000288000008000000000010000000040800000000000000000000000000000000000FF3F300000002004000B0002002000\n\t04000820000000000000081000000401280004A04C0000000001000020000000100800000000000000000001000000080408\n\t000000000000000000000000FFA8B200000000200000000843000001200000000000080008008308901100000D081101000000d8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002000000000\n\t000000000000FFA3DB004102015C51801911905AC1A55D15155F159400515557556046556546B57084A06156006341016006\n\t00610684600628604000000000080000620E006006006000000000000000000000FF9EA00A00000A80000800030092057810\n\t4B483001000100402C0255008002210200048500844008300040145504000146A4004000000000000A880140800150000040\n\t00000000000000000000FFAEF100210400CA28800C9090090084480090880C8A00D0A5032228024420831420020020832020\n\tC8013002022082022002402040000000000000003003002802002000000000000000000000FF2F4D000000000000000200000038a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000008000\n\t06000000000000000000000000000000000000000000000000000000000000FF6175000000002828A00800800C00C0080100\n\t080080A089280290280200200A00220200200200280080200200200200200200200000000000100000000200200200200000\n\t0000000000000000FF29DB0C00000A80002100040140001200121044000000C0082882082802024000000010088000004080\n\t0000000001000540000000010000000508001100001000004000000000000000000000FF4933010000000C28908800802A00\n\t800800C0080080A028A00208200280200A64200208200280351000200300200200200200200000000000084000300280300200b8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (843840023801\n\tA04021655653640A0D4312D42012056007221010146006042546016046206000000000000000104800106006006000000000\n\t000000000000FFCD0A00000000200080180180180180180200180B8400046006006082004026006502486106000000006026\n\t00200040601600600000000000000000400A006086006000000000000000000000FF44BE0000000000000000000000000000\n\t0180000000000000000000000000000000000000000000000000000000060000000000000000000000000000000000000000\n\t00000000000000000000FF8BFA000000001200001000000000000001A00000000000000000000000400500400100480000000078a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF673500000000200480000181180180180004180D844005210600650004404E0864041560062240082071060040\n\t80406016216000000000000001906016006106006000000000000000000000FFD784000000000001801801801D0393182384\n\t9805B10020622E28E02208418202A08A2020860040401260060B222608E0B600600000055000000042800608602200600000\n\t0000000000000000FF0A50000000000000801821801805803801813801800000600702604A00F200210802802E0600400048\n\t6926102000166106016000000000000000854006006846006000000000000000000000FF3A1400000000000480184181180100f8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600C00080\n\t6016006000000000000000007804006006006000000000000000000000FF642A00000000112180200183390191394B805811\n\t81000062C6C2684C004822182030A02106602000006006004806006806006000000550000000402007106002006000000000\n\t000000000000FF4341000020005000800001821801843805A498038C0000628702709400700004824140A006002200106006\n\t00500000700600600000000001010000200702E006006000000000000000000000FFF9B0000040022105800001811C018419\n\t200158898221202026A060A000480222B21480F906804C0000600600400600600600600000000000810000680612E80200600004a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01A01881A010\n\t506926006204005800200814044246202001A0E00E0040060260460060000000000008008020060068000060000000000000\n\t00000000FF55C9000400001885800201819927821C01803847800007E0069C614412650008004C53413F0021000060264240\n\t50006006896010000000000004014246006000006000000000000000000000FFFF06000000008809800001801E4984D81184\n\t5801822080401620600C4440210A988000480600400000614604440680E00610600000000800000088240409600400600000\n\t0000000000000000FF0DD1000000040845804001E05801801809A0190180302058060060040040C6406000004006004024000084a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF6C8C000000003A95809C03C81811815801841D2984504062174EE91C9021000503C632190600600480680E40600004\n\t604700600000001008000410104610608A006000000000000000000000FFFA8A0000000908210018A180381595584DA01803\n\t8001826006206100000007106017008206002500407006006406006006006000000410010810A02006006002006000000000\n\t000000000000FFAAB2000000008A01001801C01901801809801C41C0000870C6006441202426A06806A1120620288020E88E\n\t00622801600600E008000000000000013006016802006000000000000000000000FF0059000000001B0180000180180180180044a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002007006006\n\t006000000000000000006007002000000000000000000000000000FFC8DC00020000982880180184180182182BA008018000\n\t00600640681080681600440E20500680608500600E0060000060060160000000000000410060060000880000000000000000\n\t00000000FF02BE000000001C018A98438858159118018018A1E0400D6C0E056100006006104800024206006A004070060062\n\t06006006006000000410110010C06006002000000000000000000000000000FF2C960000001059090A1901821801805801C0\n\t1895802108E00E10600480106E60610601000600680000600600600700600600E0000000000000200020070060020060000000c4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D82988804262\n\t062A611450E2A64CC9504060D000F10040602643240800600600608004800000000000600600600200000000000000000000\n\t0000FF9F0B000000003809900001801841801923841883842000E0D600E0440400080044000B620000604000601600200600\n\t6006006000000000000000006006002000000000000000000000000000FF11E1000000000800801801801801801801801801\n\t8000006006006000000000004004004006006000006006002000006006006000000000000000006006000000000000000000\n\t000000000000FF8D4B000000000800801801801801801C0180180180010068060060000060000048040040060068000060060024a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF50E5000200001001A02001901A0180988988B089C8000063AE2AF23A0AC2A320C2060B468640E1A828616E32225E016006\n\t006080028000000010806006002000000000000000000000000000FFE746000000000800800005C01A25801801835815C540\n\t40604E417545250456214D554C0150154A2C40640604C1000060460160000080400010012060060060220000000000000000\n\t00000000FFEAC6000000200868804001801A21801801921803808010F00600640400080880400C20600056401010600600C0\n\t06006006006000000000000000006006002000000000000000000000000000FFB60B000000021A0080000380180180B8118000a4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060060060\n\t00000000000000002006802004000000000000000000000000FF1653000000044001100005801801C05C44000C4184415460\n\t0700E106C0100234414401405050CA0000600600400000600680600000080000000120600600402200000000000000000000\n\t0000FFD64D000200000001200001881A21801C002208018000006046007C8702400200401408404090505000600600400600\n\t6007006000001000000000006006804002000000000000000000000000FFBE55000000001000800003A0180580180181200B\n\t82C140691640604A20F44A015546A4C28F2260812062A60AA0A800E0260160000080400000080060060020010000000000000064a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800082600600\n\t600E210082804004000000004000006006040040006086006000000000000000406C26414206000000000000000000000000\n\tFF178B000000228028B41A11933A31A35800021911824012744600EA46C2CD0A004884046C80824A00A2EC0E88884744F2A6\n\tA06000000000000880828326C8482E000000000000000000000000FF6C6808000040360280D8818018038819418838038880\n\t21611652608B10702228C85030001611401080600684400800601610600000000000100128200604E306A000000000000000\n\t00000000FF4615000000000201801801801801A01801A01A018000006006806002004002004006000006004000007806804000e4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFA7\n\t9F080000000C01810A00C20B00820801250892920800200300200206224200047A042042002101002B0208200200A0030020\n\t00000000000000082806020002000000000000000000000000FFE7DA00000002180000780808800C00000192000040212080\n\t8862001418400C001004484A084F8208300050430106000A000000000000000004D00000111C05A400000000000000000000\n\t0000FF6B180000001120000800002040005000218806000C811804208882A040001150918093008010000002800000800E00\n\t0060000000000000000100220080208008200000000000000000000000FFC2D700004000023A86988180180388BA0020180D0014a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400480400000\n\t0000000910800B04004810000000000000000000000000FFF616000000011809001801805901941A210A1001800200600641\n\t604E0C640E10601400C10600600008600E206086006006006000000000000308426416116206800000000000000000000000\n\tFF26A5000040480840C34A04A00842804C00810A94B40008320A8034032130222022C35238234B308000232304B043303A42\n\t002000000000001021002003C23082000000000000000000000000FF82E70000002082402004044022602442C02025000008\n\t000A11010C40808C20A84000A00100800801000C08800820F20409280000000000000800848A0000080100000000000000000094a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008001001821\n\t008011481021900801021400000001011001001000000000000000001201400041001440000000000000000000000000FF7D\n\t090008000A80800A80AA0AA2AA0AA2A20AA0AA0008A802A82A82200400203802202A02A83008002A82A82A00A82A82A8AA80\n\t000000000004100108082A80002A8000000000000000000000FF0529000200402A24A00800800800A00810A00800800A04B0\n\t0300208B00B00A812912012002842400802802812802803002002000000000000A00ACA0428034C200000000000000000000\n\t0000FF04210000002002092020010014014010012010010108805004004800AA0C808248048040009108C0805004800C01000054a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF921700\n\t0800000082000000000000400010000200000104800000108808802000000880880081082300000000040000000100000000\n\t0000000082080808000008000000000000000000000000FFDBBD00000008048208A0AA4AA0AA4AA0AA0AA0AA00202A12A82A\n\t8208220A80028288210AA83081102A8AA82202A82A82A82A8000000000000010150B082A80802A8000000000000000000000\n\tFF9B8B0002003522303341545545541543443541540100480D50D50440C00D08A50CC0540550420500550D50CD0950D50D50\n\t550000000000000800C40540D50D40550000000000000000000000FF508C000800430030440000200400000400400600000000d4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (016000000008\n\t250000046006016006000000000000000000000000FF606D000000203104202000001401001211200401004014C00500480C\n\t8044848210D0834004904900804000888C0080100400400000000000091080C004804D04000000000000000000000000FF95\n\tCB000000828A28800800000800800800800800800080200200208200200A0120020820020120080020020020020020028020\n\t0000000000020042285200204A000000000000000000000000FFC8B50000000840000A80AA2AA0AA2AA0A20AA0AA0003200A\n\tA82A83203A8860280200240AA82202012A8AA83200A82A82A92A80000000000001000802802A80102A8000000000000000000034a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (320820820501\n\t220021820020020E000008200200200244201A00A000080000028000010402008016100000000000000000000000FF205A40\n\t080050040000040040240040042040040200A108900100100109D5812410090011116010A13110480E800100100100000000\n\t0020081601021005001001000000000000000000000000FF16AA400000C00C008C0C00404C00C00C80C12C10892104B00B22\n\tB03308305310B2830430430030C1003002092003003103002010100420101001003103503003000000000000000000000000\n\tFFF6C3000081801845801814001801801845801905840050644610608640600420602E50C00614E00022621600600600601600b4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF71CA000001\n\t84100100180801183480392B001801814002622600600E00448A116014082006020102496000204028004006006000000000\n\t00040201408E204006010000000000000000000000FF082C0008800000000500100080C210A0AD84000000804200A0400030\n\t2000104200101000001100800800200000560000800100000000000005100000802802C0000020000000000000000000FF9E\n\t960000000818220C180800000000000180D00808002402104300502002100B42202B01500080000504200000060001000000\n\t10000408200000000080280000000000000000000000000000FFE42F0000808010008008020008000008830108C0820001240074a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000000A\n\tA0100006206006000000000000000000000000FF259A000001801044003800001801801801855801804000600600600E0962\n\t900024A455601608E04000600408C00600400600600000000000000825000612A0B6000000000000000000000000FFED1500\n\t00818010000810040418018118008C180380002860860060A60C600020010240614600600000602400400022410E00600040\n\t0000000090000206016056100040000000000000000000FF6EC40008018210010D7802021908901800091843862009601640\n\t60864942620CA0062020A611006020E00020418600406601600020000000000000200E10C50600800000000000000000000000f4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E2A600E0082A\n\tA0044402062084002AE2AA28E4AE2AA2AE2AE0000000000001482022AE20240E000000000000000000000000FF9CE3000001\n\t8030088008000018008018008C980180200060060060072060810002004C0006000400006002006000002006006000000000\n\t000308008006006086000000000000000000000000FF8D880000018A80908A80AA0AB8AB8AB8A20858AB81802AE2AE2AE2A6\n\tE04106AAA40A1002C62461002AE2AC2062AE2AA2AE2AE000000000000400042AAE042246800000000000000000000000FF84\n\t02400001802008800000001800801811001801C000006006006006044026006000000046046A800060040460000020060060000ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (22400001A41B\n\t058A80AA0AB8AB0ABAA28018ABC0802AE2AE2AE2262460022A805A0042062A90102AE2AA3060A82AA2AE2AE0000000000010\n\t6074C2AE000226000000000000000000000000FFEE3E000801A04A45841800001801001801820801A0200060060060161264\n\t4200012801411608602000600404600600200600600000000000000011700610D106000000000000000000000000FF571B00\n\t0001908821935954155955155954804955808055655655653609623255608000C54E55610455655443655055255655600000\n\t0000000000007556354457000000000000000000000000FF11010000018A908088A0AA0AB8AB8ABCAB8898AB80002AE2AE2A008ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000002040\n\t6006020006000000000000000000000000FF08FF00002100084184C000001891001801801801801000600600600600C03404\n\tE10008E006080000006002016206006006006000000000000008136006110006000000000000000000000000FF75B9000001\n\t002811802000001801801810901001C0200060060060860942940064A05560D6000408006002096200006006006000000000\n\t0000080460060D0096000000000000000000000000FF99570000019298C580000000180180180184D8018010006006006016\n\t046022000004004006000100006002026006002006006000000000000280104806400806000000000000000000000000FF33004ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4104C2450102\n\t5405564160045564964D6350456556556000000000000020416556510556000000000000000000000000FF14318000000338\n\t0400180000180D80180100D80180820060060060060001080004120060060860140060460060060060060060000000000000\n\t08006006010006000000000000000000000000FF55EA0000890A98898018000AB8018AB8A392B8AB80802AE2AE2AE2AE3242\n\t040060142222AE3060222AE2862260AE2A62AE2AE0000000000000020062AE2002AE000000000000000000000000FF68A900\n\t000500380590180000182580180888180180400060060060061040845004280020060360040060361060000160060060000000cca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00AA08188008\n\t00000AB90B8AB8A30830AB80122AE2AE2AE2AA2AC2C61000023002AE20200C2AE2162AA0AE3222AE2AE00000000000000845\n\t62AE4002AE000000000000000000000000FFC408000820000801C00000001829801800031001808200600600600604001608\n\t044401600604204200602600200008600600600000000000000A0A6006020006000000000000000000000000FF261D0000AA\n\t2808B00AA0000AB8218AB8B30A18AB80502AE2AE2AE2AE2A820622812422E2AE2320042AE2862AA2AE22E2AE2AE000000000\n\t0000200862AE0A02AE000000000000000000000000FF43C8000114553935B558001559059559540039558040556556556556002ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (11800008200F\n\t000007000000000000000000000000FFE027000000600800C01C00201E09C21805011001810200604F08703210421612400F\n\t20E206004005007A86104001003006006000280008040000004006006006000000000000000000000000FF34DB0008000008\n\t4884D800001821801801041001810200600680600300505604C5260000061340068060AE00440680A8060060000000000000\n\t0220C00602E006000000000000000000000000FF925700000002B802C00400001901A01811209C0180220070060060020040\n\t06D0000F150806002000006006002000102007006000000000000040126007300007000000000000000000000000FF29E70000aca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A50210482E4\n\t2E0044000470565042C8442016106020000000000510108206006484000000000000000000000000FF6BB880000020000300\n\t1A00001A11A018410A1AA180A044612604743028610A09242404A1165040289260A630440682280700600008000052001002\n\t2806200004000000000000000000000000FFF0D3800104001005801800601803801821001C898A01A87C0640600505308240\n\t7A40000096282000116006402240042007006000000000200008141096217806000000000000000000000000FF1BD3800882\n\t401000401C00401C01C21803549C418040047106AC6404C0A862A1618514304605A05084E846002026802807006000000000006ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (441001520002\n\t00582184985309180580005464060D62A00062920CE0A602A24E00020004601620020600400600600000000000000010004E\n\t406304080000000000000000000000FF9059000000401100890012001823821801081803800008600608E00440208602E026\n\t00000600400000600600400000408600604000000000017000048E24E016410000000000000000000000FF98FA0000000010\n\tA04000080098058038890098119C0012643620600C06240604601E5824C626C02008640600C00600C0060260004000100000\n\t000021260B000E288000000000000000000000FFB9B8800000020001C29000023801809843043801808040620F0464A0A16C00eca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006802AE1020\n\tC2000000000000000000000000FF2FDD000000403804101800000000000001080000000000000000000400448001400814C0\n\t00000000000000000206000000000000000000000010000000490448000000000000000000000000FFB95E80000000000804\n\tC00000000000000182A00000C00000000000080100480000404000001300200000000900061100000000000000000002C002\n\t8000020000000000000000000000000000FFDAC6000000200041A00800049803805881045801890000602E40601003600240\n\t60161060864500201060260900B023410E0C600000000000040000C08610E002000000000000000000000000FFA55C000000001ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (621520655644\n\t60005565564265564575575560000000000004C0427556126086000000000000000000000000FFD8850000000A88008AA800\n\t0AA8AA8AA8AA9088AA80A02AA2AA2AA2A22AA10A2A23020422AA32A0002AA2AA2820AA2222AA2AA0000000000002480022AA\n\t40A40A000000000000000000000000FF7FF20880000000D04000002000004001004000000021000800001000000000148100\n\t049000110011000000008000080800800000000000000010010800408A48000000000000000000000000FF87F60000000A88\n\tF54008000AA8AA8AA8AA8048AA80002AA2AA2AA2B22A24022B22920122AA2020402AA2AA2224AA3222AA2AA0000000000000009ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200000000000\n\t00000080000000010000080000081001013002000094800010800000000000040001000000000000000000000A0C00004405\n\t00000000000000000000000000FF88BB88000004480C8808000AA8AAEAA82A8AAEAA80202AA2AA2AA203A223532020421032\n\tAA2020012ABAAA30A0AA2A22AA2AA0000000000000021022AA00200A000000000000000000000000FFD66B80080040410140\n\t000040100140100044040100008050050050000000448000444810040000010040040480000110048040000000000001000B\n\t4804020900000000000000000000000000FFA4AA800000691801D55800555D55955855955B558101557557D5754E536404C0005ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800100200200\n\t0000000000000000000000FFBD1600000000000000000000002009231000004000008001080100004400C8C4034800188004\n\t01000A0000000010000A08000000000000000002000000800000000000000000000000000000FF6577000200000000000000\n\t00000010002203800800002A00000000408002000C8000048000840002000000000000800000000000000000000100000000\n\t000000000000000000000000000000FF3FFE01000008808444C00040020000000000000000010000008000C01000010882B0\n\t4008000400088000000A00000010008000000000000002C0408800110040000000000000000000000000FFC4AB000000222000dca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04208A603808\n\t002002082002003082000000000000000D08020000002002000000000000000000000000FFC10F000511001B158038818018\n\t3581388570D0B5880081604F046C17A443160570AE0161070360C00C600600600F00600E0000000000000000000000000068\n\t06000000000000000000000000FF27430800010002010000020020011090510416000800548D0411014400C86058040C1046\n\t0410480000400000420840462C400000210020000A20010000000000000000000000000000000000FF9FE700010880091280\n\t490080080C800A00B0490490008122428C24B200200300300208220208A04000200200200220300220000000800000000000003ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100100100000\n\t0000200001000000000000400000400000000000000080080000080000080600000000000000000000000080000000000000\n\t0000000000000000000000FF5703000000800800000800800820A82800808800800080208A80202000200202280280248A02\n\t2008002002082002002002000000000040000008040000003002000000000000000000000000FFE2FC100001000000000004\n\t0040002080050400006800008000801001408480000008000000800000000800000C10001548000000200000000020800000\n\t000000000000000000000000000000FFCA30000000800A00800800800820802802826800800000288A002002202AC210300300bca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (005016000000\n\t000000000000000000FF6F46010001001811801800041809825801D4D005A040104206012147016406C45406156406006821\n\t006004006046227046000000000000010001080000004006000000000000000000000000FFC2300000010018018018000018\n\t018018118010A0000020C02E2822062C004600410E4061260060104061040160101060160400280000000001000000400140\n\t06000000000000000000000000FFE41E00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000006000000000000000000000000000000000000000000000000000000000000FF4EA500000000140000007ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (06006A000060\n\t04006006006006000000000000001008000008006806000000000000000000000000FFBAA900000180000100180004000180\n\t58088028A020400374164028874504840075060C620609600000600400600004702602005000000000008010002000E00E00\n\t0000000000000000000000FF4CE5008001001808801815801A49835815009000A00008407608E32E10203632404620E83614\n\t601AA0610604643E006016000050000500000040860001004004040000000000000000000000FFC38C000001001800001801\n\t801A018018010A1803800024480600601608210618400E00688611662200608600E00028600E00000000000000800204000000fca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801E05809803\n\t825800000080600680200400010484602600600E00600C006004006000006006000000000000000004000000006006000000\n\t000000000000000000FF4ACD180001800506001834000199905820A11980800080601601A1060024C4706C8686600615E400\n\t606006006006006006000850000118E0039020060080E004000000000000000000000000FFE9A6000001800001001E2060A0\n\t41801850800821800000E04600600610200C807107006006007000006106046410006016001000000201000C204400090160\n\t04040000000000000000000000FF6CB9000001880111031880014003901800E4C840000001700600200600024482620600600002a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C0200000000\n\t00000000000000FFCEDE000000800000001801801801801801885E04E200A560C61060A40020448860178B610620E02E1060\n\t0400630601612E000000080000000002000820106884020000000000000000000000FF2DBF000000800010001801C0182180\n\t1801A198A0020030229741241535293483E12620E2668461000060440060800064061200000000010004000407804C607600\n\t0000000000000000000000FF23640000000000000038000018418218018018A1A800006C0680280420620424644640640600\n\t680400621400600620600604000000000000000408000100E004000000000000000000000000FF77EC0000000802080298810082a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E04D00700700\n\t600601E006000000000000000904000001006004000000000000000000000000FF5C990000818018A10058018A1C018C1821\n\tD04804120001209710240E01A1265AE006A0680FC07024006206086000006436000000000000000081148040016904000000\n\t000000000000000000FF300E000601009E0004594A211945835889801800000010681630BC27007106407536086086106900\n\t006006006006006006000000000550200028C00001006004100500000000000000000000FF71CA000001001809001801801C\n\t018018018018000004942026C0A15694640E006C8E0C608604E0B008622E00620020E126080000080000001404001000A2680042a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018004018\n\t0180000048068040068060068020060060060048010060070068060060060000000000000008000060060060000000000000\n\t00000000000000FFB975000000209821A45891AC1803A93840020101C0000040264060160060060400CE4270168060840064\n\t0610600000602600000000000040000000C006807000100500000000000000000000FFF3CC000080201901A01840011949A4\n\t1890201841A200104C8E10E406016506D1640711600610E81400700600680600600600000000055100082C20600600600000\n\t0000000000000000000000FFD98F0000018018000018042018098018018218A08000006A2600204600224600600602E1066000c2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF8DEF000000000003883803801B0188184C502829C00021000728CC4632614C13140534682640281128E05611\n\t6001006016010408140080000000206006006000000000000000000000000000FFA0D7000000000121801801801801829880\n\t01190392C00404B604608E00E0042000D400E0160A2500006086426046106006400000200000008000006006006000000000\n\t000000000000000000FF8BC20000000018018018018018018018000008018000004006006006006006002006006006004000\n\t006006006000006006000000000000000000004006006000000000000000000000000000FF587500000000180180180000180022a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A0680E006000\n\t026426080000000000001A80026006006000000000000000000000000000FFFBC9000000000001801A0000000183980A083C\n\t09C0002AE2261263863AE2A42EF7AD23E0AE0E62A868E0F620E0260C60663080082800800085000460060060000000000000\n\t00000000000000FFCB96000000000001801905801A41905840113CC58500154556814C56416554110054106D56210CAC0060\n\t06806000806406000000000000000000006007006000000000000000000000000000FFF63900000000008380180200188180\n\t1800069803822090408608800F0064048000040861062000440070068060060060460000000000000008040060060060000000a2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180000180100\n\t0080200600600600600680600600680600400000780600600600600600000000000000000000780780600000000000000000\n\t0000000000FF47E30000000000419058000018019019400031419100002016C03046806814082004007006A0A08200601614\n\t6000806016000400040000000802406006006000000000000000000000000000FF8432000000000001801A84001801F03800\n\t001101E00090388F016407007004822204086137022020006046006007006006000000000000000000006006006000000000\n\t000000000000000000FFBBE8000000000001801800000041809840309043848004E4260870CEC8E34C8100CC00E2060064080062a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF6E860000000119238019180018018419142C580100000028C600201602600642610604E046000010006006006010\n\t03620600000000000000001000601EC06200000000000000000000000000FFECB2000040221901A23A88211911A9180A0C1A\n\t3315008D212EA0A42604E906D56AA6A86C068908308160A750E80603724E00000000000000080082600E0060800000000000\n\t00000000000000FF6F7608000000B84D801805803803803800005901000120200612601628600E00600E00E1164042000062\n\t060061000061060000000000000002001161072A6200000000000000000000000000FF4872000000001801801801801E018000e2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008808010008\n\t20000000000000000E00108000B00880000000000000000000000000FF04AE00000000080094080080480080080000020A04\n\t00213032183002202002A0A00300200200A60100A20200200300A00200000000000000000000300200200000000000000000\n\t0000000000FF3D63000000001A0400384785180C4000024000A000004A5000620C40488480004808F00A007C014000018060\n\t00C60004800000000000000100000860800A0400000000000000000000000000FF28C80000000282D803000000A68048A048\n\t52200002C00000080088218100080400000810880000000008200080068000080000000000000000400268000400000000000012a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02B255004090\n\t0804800114304810894000004004800800804885004800005004000000000000000A00000004804828000000000000000000\n\t000000FFF68F000100001803801821821901801842221801800015611600644640E206004816086106486520006006206006\n\t006406000000000000000000006016146200000000000000000000000000FF3B69000000414CA8D34D0CC14804820A881149\n\t0085212022432C2812803002443102A428230430100030830030528130020000000000000114511020034020000000000000\n\t00000000000000FF0AC608032020600020428020030200040001030009009485008402088008008802B000010100082900080092a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF2E3900084040050040050040260000004004040000000000010090010010010000010008000010010000010010010010\n\t00000000000000001001000001001000001000000000000000000000FF44510008800880000AA00808C0AA0AA0A000028000\n\t802202A82A8B200083A02202A82A82A82A80002A82002A82A82A82A800000000000000006000000022000000000000000000\n\t0000000000FF840400004C204A04A00B04A42800A00A04500800800081280280200304280280280280200300282080284B00\n\t2802803002000000000000800800802002912500000000000000000000000000FF97BD0002002202B12002202004012010080052a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80A82A82A800\n\t00000000000000E00008002A82A8000000000000000000000000FF2231000810004000000010020000400000048108008010\n\t00000000000900008810010008000000200000C8000000000000000000000000000200000000000400000000000000000000\n\t000000FFA5D700008C0AC0120AA0320880AA0AA08C00812200402A12A84802A82302A82A82A82A82A82A80102A82A82A82A8\n\t2A82A80000000000000001000010002A82A8000000000000000000000000FFE5DE0001243503523542C43105541543343044\n\t440020C50D50D51448C40C50450550550550D50800D51400D50B50D50D50000000000000800800800000CD0128000000000000d2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (818840006006\n\t00E02614620E1060042060060060002062062160060060860000200200000060000160004060000000000000000000000000\n\t00FF7ECF0000422202022002202004012010001414550080840000841005304800804005004804804888800805004A008010\n\t04000000000000004800800000005000000800000000000000000000FFA1A4000000004920800904842800800840A1280080\n\t2030280250200204200200280200200200200000200200200200200200000000000000200000200080200000000000000000\n\t0000000000FF84F70000880880480AA0080C80AA4AA08A50409001010182A80482A81082A82A92A82A92A92A81002A92A82A0032a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tB5BB0000200088008208008808008008A0808900862200210210204202200221200211010200200013211200200200240204\n\t040000000002000068A220340000040000000000000000000000FF53BC400C0000040000000000044040C4005904C00D032A\n\t12880293010882810010312010A9089281149281240001009000000000000081001011101441001000000000000000000000\n\t000000FFFBC0400440002C00800800908C00C10C40C00C0280013234922C341321210344B4A311355313350300B103002003\n\t01300208000000048144300340300100B000000000000000000000000000FF1D60000000009801821841803801801901801800b2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006016008000\n\t000000004000406618000200000000000000000000000000FF4A6600008000182102380084404184990080B80B8100506316\n\t00604610600E08E08000614644601010E2460060000260060000000000000045000060002404000000000000000000000000\n\t00FFBE100009000000541440400801200900A004C034008004820022041000050810048822041020044020640000000604E0\n\t1000000000000000055002E000400000080000000000000000000000FFB79300000000580000184181384000400000002201\n\t000000004840C84000080C828C108200040000486000028006006100080020040400400008006000008000000000000000000072a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000062860\n\t0600600411600A002006086840006006006000006006000000000000004800006000006000000000000000000000000000FF\n\t2E200000000208000018208000018018008C9845802000600204C00600609644610000600604E20000600600620600600600\n\t0000000000004008006000004000000000000000000000000000FFCBC0000000000814001900810001901840801801802000\n\tE0020C4206006006006000086006006300206086006000016206028200000000004050036000084000120000000000000000\n\t000000FF80260008000018011018D892A10182180084194184202C600E40601609E5666064104564360260C800603600600600f2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFC9B0\n\t0000000AC0AB8AB8320900AB8AB800889889A1202B02AA0242AE2AE2AC08E2A62AE2AE30E2202AE2AE2AE4AE2AE2AE000000\n\t0000000040482AE2A82AF000000000000000000000000000FF7CEA000400004001801810050001801E009118018120140006\n\t4260060060040260000060060060800060060060000060060000000000000040C00060000060000000000000000000000000\n\t00FF93FE0000000890AB8AB8080880AB8AB80000188980802A82AE4142AE2AE2240462222AA2AE2060002AE2AE2AE0AE2AE2\n\tAE000000000000004620AAE2A82AE000000000000000000000000000FF8F4B40020000500180190402200180180080380180000aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00006000006000006000000000000000000000000000FFF81B4000000880AA8AB80988D8AB8AB8018838AB80002062A80042\n\tAE2AE2AC4062AE2AA2AE2C70002AE2AE2AE0A82AE2AE0000000000000070182AE2A82AE000000000000000000000000000FF\n\t4CD1000800001000801901843801801801843825800600600410400600600420601600600602600000600600600600600600\n\t0000000000006000006000006000000000000000000000000000FF8C120000001511549558C5901955955801823955800240\n\tE55409455655655411655655655649600C556556556550556556000000000000006000D56550556000000000000000000000008aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00613200600\n\t610600640000800600608400400600600000400600000000000000C040006000006000000000000000000000000000FF05CF\n\t0000000018058018058058018018148018018080006116200006006006006122080006006040006006006206006006000000\n\t000000084088006000116000000000000000000000000000FFD4CB000000020801801821821801801800811801A0C4086006\n\t04A0060060064460020000060560880040060060000040060000000000000041200060000068000000000000000000000000\n\t00FF4EF300000000400080190580380180180184180180040360045040060060041160060020060060000060060064060060004aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF8F620010\n\t00511914D55B3455595595581415595580404D25461065565565465564464565565560405565565563505565560000000000\n\t005482C055000654E006000004000000000000000000FFCF31800000001800801800003801801804001801800000A0160060\n\t06006006004006006006006000006006006004006006000000000000000500006006006006000006000000000000000000FF\n\tF2120000000AA8A98AB8A98A98AB8AB8A18AB8AB80002262260002AE2AE22E2AE00E3202AE2AE7002AE2AE2AE0AE2AE2AE00\n\t00000000002242002AE000226000000000000000000000000000FF66AE00000000180180180180180180180180180180400800caa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0020000006006006000006000000000000000000FF5D6C0000000140812AA0A82A98AB8AB8800AB0AB80022204062262AE2A\n\tE2AC2AE00E3462AE2AE0002AE2AE2AE0AC2AE2AE0000000000002A82102AE006286006000006000000000000000000FF0B56\n\t000000023820801A00001801801920001801810000200E456006006016004116006006006000006006006000006006000000\n\t000000000010000006006006000004000000000000000000FFE3B70000002A18CA8AB8AA0A98AB8AB8A80AB8AB80A02A20A6\n\t3282AE2AE2AE2AE3362162AE2AE3102AE2AE2AE2AC2AE2AE0000000000002A80402AE00632E0060000060000000000000000002aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (206347106104\n\t117106C1761690600082602E8061048070060000000000781F8000006006106006000006000000000000000000FFBCBA0000\n\t2060C401401400009C01A01810001821800100284640A00602600C00602F0070A640600020708700E0050070060000000000\n\t00000000000007406006000006000000000000000000FFAD4B000800034035000004201A0180184200180180C01004860920\n\t060060040061268B600680650C80600680640480600600000000000000008C00600604E006000006000000000000000000FF\n\t4BB0000000100001201400003801801808001C01800201404E8020068060040074060070060060000060060060040068060000aaa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A4C700000000\n\t0401A01C008C2409801800001885802020420E0200860060840062074D6C1600640020111704600404004600000000000000\n\t84904C6516006006010006000000000000000000FF3C2E800000210041801800800041C4180A0038C3800094452600011623\n\t6444D4E40630E016556400910006546104840806000000000200000000010006A86006000006000000000000000000FF5BB4\n\t802000000001805800E04021D4580400110D9300025A96101C0FA0E2252262060860060362010AE0362A6004026006000000\n\t000400400000009806006006000006000000000000000000FF89DE800020402041C01C10A0A301C83800005C0988C010500F006aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000040\n\t28620E006006008006000000000000000000FF6D7800000840184184200082580992580002090D840048440604A156006306\n\t00622E48E04E006000050356006004000006000000000048010100050106206006000006000000000000000000FF86940000\n\t00401807023A00B018018A38000AE009800009C00600A00E50E2060060060460260060980260060060040060060000000000\n\t28000430000006006006000006000000000000000000FF842400408800182140D8328099038098000000018EC00240A61962\n\t663A611600C1FE0061C602602048E32601E00400600600000000000040000000E006206006000006000000000000000000FF00eaa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AA2AA22A0122\n\tAA2AA2AA2AA0082CA2AA2AA2AA2CA2AA00000000000000000048A2AA2AA2AE0002AA000000000000000000FFFCA100000040\n\t1814001805843800000000022000000228800004800000000000400000000000002000600000000400600000000000000000\n\t0000006000000000000006000000000000000000FF5D0980000000002044C600600000000000090000012202000050000000\n\t0080530000000000000200026000000006046000000000000000000228446000000000000006000000000000000000FFC4EB\n\t000100201801C11442C1180380980011080188C00440B60822060360060141060063060264A0280006036004020026000000001aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000711911\n\tD53D55951D55D558003119558100307556007557556557556557556557556250517556556356516556000000000000000428\n\t555557556556000556000000000000000000FF6EDD0000000888CC8A88AAAC8AAAAAA80008CAAA81200222AA8022AB2AA333\n\t0A2AAA2AA2AA2AA25028A2AA2AA2AA28A2AA0000000000000002080AA2AA2AA2AA0002AA000000000000000000FF410E0800\n\t0002202220040000000000000004200000400480000910000000000000000010008000000208008000000210000000000000\n\t00000000004000000000000000000000000000000000FF3CA80000000EE880C808A88888AA8AA8000400AA80005002AA0522009aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000002080208\n\t00800000000000000000000000000000FF75F500000020000000000000220000000000020000004200000A88008000008010\n\t00000000000040020800800200020000000000000000000000400000000800000000000000000000000000FF04178800000A\n\tA88A8008AAE8C8AA8AA800088CAA80200022AA6422AA2AA2AA2AB2AA2ABAAA2AA00028A2AB2AA0AA28BAAA00000000000000\n\t002008A2AA2AB2AA0002AA000000000000000000FF5EC6000800400000404400202201201000201201000000C004C8100500\n\t4000C00804004804804000001005004000001004000000000000000040004004004004000000000000000000000000FF5D95005aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200200202220\n\t200200282008202200A002002002000000200000200000002002802002802002000000000000000000FF9707000000000000\n\t0000000000002000402003040480000250800200000488100200000430400C10000000200000000000000000000000000001\n\t800000000000000000000000000000000000FF6AAD0000000020300000400400000101000120100100088081420420400020\n\t668000400080111000001111000010001800000000000000040400000000000400000000000000000000000000FF428B0000\n\t000000202CC4000200004000000220000100090800000000000000000000800001000410000000000000000000000000000000daa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004608808\n\t08880C00800B00C00800880000200200208210202200A04201A00211200060220200A2030022220080000000088004584020\n\t2208A082802002000000000000000000FF538F0501141105018C583185581180B92D8D595593404A608E5174961164C64A7A\n\t0600620E206208006027016006007004000000400000400800004006006006006006000000000000000000FFE04202800000\n\t404000000310B1012830010000010200011C4406084D0A581C094A60404148000260100004C05804000084000000000020A0\n\t00A0284005004004001800000000000000000000FF046F02810A088500922848932910814D14B50A509020422002D0A10A91003aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200600000\n\t0000000006000000000000000000FF1838000000000000001000000000000000200200000000000000000000000000080000\n\t0000000801007000000000806000800000000000000800006800000000000006000000000000000000FFC59C000000000208\n\t8808202A02008088000088082080002002802A8220302224A00300200200204000228C80A20C002022010000000028240000\n\t084000088286002002000000000000000000FF77D905000000000000001520B0000820000002003200000000220808040814\n\t080400A00010000200800000000000001484800000000000000080000820004001800000000000000000000000FF16CF000000baa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006856406082\n\t026000006924106006046806000000000000100010008004104046000806000000000000000000FFCE38000000000001201A\n\t01801841801A00A11200B0408960170A0436906106C3610400690604601082000C0060060000260000000000080281004881\n\t04004006800002000000000000000000FFF55B00002000A02100182180188180384090383080002240860080064264160860\n\t00156446116540110444006406000006000000000040000040006024004006000002000000000000000000FFC4F200000000\n\t0000000000000000000000000000000000000000000000000000000000000000000200600000000000600000000000000000007aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000182384100\n\t1005801A129010208142826806846016207106006807A460060440020000860062040000020000000004D00400D340021400\n\t6006802402000000000000000000FFA4F400000000A041801801001141805A21D01040824221611609622E4C600752E00E12\n\t604600682802000E0862040200220000000000080C80084860C4006006002002000000000000000000FF0C550040A0000001\n\t001A25855901815841803888B800186616026446846AEE0060B720E20208C28048EE840070061069060004000000201000A0\n\t046044094036004006000000000000000000FF0277000100000001001801801A018018018691008400026C0600000600704600faa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A0600E406006\n\t007006000000000000000000FFE649022000000001800843021043801800001801100002680604680E80600640604E046806\n\t04600008600600600600610E000000000000020828008016806806806426000000000000000000FF3A0F0000000000018C58\n\t008050298119D18218018048006006E074461C604621F02700680618400088640660600480600A00040019805071810040E0\n\t47077007006026000000000000000000FF8A9D000000000001881800809091803805F21041E100106C170000062060860070\n\t06206006006003406106006205106002000000000280000802040406006016006006000000000000000000FF50A7020000000006a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2600600000C0\n\t0204600600600602708600000800020000028B000205006007002006000000000000000000FF810E00002000000180180900\n\t1801801881813040A00008E00600600620628600604604785200448800600E0060060061060000080000000202A810620680\n\t6006006006000000000000000000FF1C6D080020000001801E08011801A0585314100000400CEC1E4BE0E605E866E8620662\n\t602A024A6004600600780604700600000000000000080006000E206807006006000000000000000000FF1ADA080000002021\n\tC20001101483801A02001403001020600612610E8068161264060070060D68030060060070060060060000000004000000020086a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801801803811\n\tC21A81811401801A01600E00E006046006016007106000004280A1600600680600621400000000000800012000600600601E\n\t006006000000000000000000FFC190000000000049801800931B89C05B41521427A06A08FC072070160274072C6806086820\n\t10511002E0160060060060260000000200002600C9D00206087007026026000000000000000000FF4DA1000000000045801C\n\t01101445801844809009080000604604695710641603644602640000400080600604614600700E0000000001400092000079\n\t04406046002006400000000000000000FF5BEF000000002001841801001203801C10C55441C000226006A06006A2611600600046a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040060060040\n\t06000000000000000000FF317100000000000080120180140180180100080180000040060030060060068030050060068060\n\t00006806000007006006000000000800800000006806006006006006000000000000000000FFC75E00000000004080180190\n\t1821801AA1001831C001004806C0214608500600620400602600600422600604004600642600000000000003000000000400\n\t6046004026000000000000000000FF3B21000000000004001801845885C41805021C03883890405284A816004A16D2604004\n\t7206806500006806001106807006000000040950C00251006D06506007046006400000000000000000FFC88800000000001100c6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600604600000\n\t7006A01206006006000000001000000000006007006806002006000000000000000000FFFB64000000000009C01A03821811\n\t8D1301901005800020455724640704434E304D0E05642611612500611650808E80E906080148108000020004000006106006\n\t000806000000000000000000FF3B48000000000001001821801801801011801101894004400601615628C00602C046286016\n\t00621004E026000246026226000000000000000000006006006006002006000000000000000000FF5EF80000000000000010\n\t01801001801800000001800000600600200600600600200400600600600400600600000600600600000000000000000000000026a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0B001081A00A\n\t85801B138000000016C4200601454ED2400A20E2060464A9D0600E0200A4806A8C280000000880000A200000068070070040\n\t06000000000000000000FFC84E000000000001801085001701880801821AC380000088EA02B24E2CC80E2ACBAE6F632E0AE3\n\tA802E0BE0C89AC02E6B4580088088000020440806006086007006006000000000000000000FFDF9A00000000002120101180\n\t1001801905089515E040906016546506C16557540C5400641654644C516806000C2604610600000000010000100400000600\n\t6827000006000000000000000000FF572F000000000209901101801201A218C90DE84180193940061868860060060000020000a6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (693644100600\n\t0000000000000000FF8EA7000000000000001801801801800201801801800400600600400600600600200680680680600000\n\t6004000006006006000000000000000000006006006006002006000000000000000000FFA74F000000000001501045841011\n\t810A41889A419142042426486066045546004804016887286000000006000004001004000040800000000000006006006007\n\t000000000000000000000000FF5D73000000000001C01001C01201800801C018218022080801007C8644400600432602600E\n\t006000810006000404021004000001000000000000000006006026002000000000000000000000FFB94000000000004100120066a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (820000007000\n\t081000006008000000000200000440006407008001110006000000000000000000FF88D00200000400120218018018158888\n\t01A418A1800004600640400660601650200000620620600040880404094620000600000000000000000000E006A068062060\n\t00000000000000000000FFB9EB020000040294889A51885801A0A2418C58258200816A06834406A8620600280680602E4568\n\t08C08424200406A01016000000000400000820908806216406884C00000000000000000000FFC61F00000000042084388324\n\t18B38C0885A1189180004A602E80400600E0C600222EA365060862A0006015080806006146000000000000000090C000061400e6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (106000400228\n\t20080200880C0080100080080080082C200800800880800604A00600900820000000000000000880B80900804144800E0000\n\t0000000000000000FFA5460000000000A0802000A00200800800A14002800061220200B6020030060021400228021DA47830\n\t202000000400200400000000000000000000404200280A004002000000000000000000FFA9D200000000410110C4093B240A\n\t42144110841000001280241700100807A00006010484E00002000070084010004065800000000000000000280160060A0AA0\n\t4A0006000000000000000000FFDF910000000000086000762002801120A402074000000000480009000088018000015008080016a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (912802000000\n\t000000000000FFF3000000000002242012020230010001222B52290122840000C8800500100500480C804894A44840800085\n\t00000C801404000000000000000840A048A8814004804800000000000000000000FF6E1E0000000040018C1805891A21901A\n\t05801901800020E80610601600640E004006006206016440106C06220C0600608600000000000000040001432600680600C0\n\t06000000000000000000FFA437000000040550804C30A0080AE14C2094C828800112324344AD034020825035222C20230C30\n\t11202002000143503202000000000000001021103002002142283202000000000000000000FF00070000000202402C1080000096a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (10D50450D505\n\t40D10C80000000000000800830910C10450550450D50000000000000000000FF754900080000040042045440040040035000\n\t0640000000000104100100100000151000180100100100000100000104100800000000100000100904100000000100100100\n\t0000000000000000FFABEE0008000000881480A408C0AA0AA00000008200041802A80202A82A82A82A82802A822008800028\n\t8B202A8A202880080000000000000000000A82002A02A82202A8000000000000000000FFAC47000000200400AA4A10A00A00\n\tC00808C008008002C128028028028028028028430020028028108420128001028231420000000000008008108028020000020056a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0AA0200AA082\n\t0000AA82A80202A82A82A92A80012A82402A80402C92A8AA92A82883200000000000000000000A82A9AA8AA80402C8000000\n\t000000000000FF293E0008000000000100000100000004920002880140000000400000001001000020000808090020001000\n\t0010080200500000000000000000002200A0100001100000000000000000000000FFDED40000000000AA0920800AA0AA0AA2\n\t022AA08C00C12A82A82882A82A82A82A80402A82882A80102882A82A82A82882200000000000000000202882A82A8AA82882\n\t88000000000000000000FF8C6F0000002003342043303203543540202AC0420000C50D50930D50D50550550C90D50540C40800d6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020000000000\n\t00000000FFDE6000000010590900192580180180189180191580000060260864360A60C644440600E2862060000060160060\n\t4E00600600000000000000E40000420E000400004006000000000000000000FFBA7C0000000002012002A220020020100500\n\t14110144000000908800800804804A0880505480082080000400000480100C000000000800000820804800000000A1480080\n\t0000000000000000FF95D4000000200800824808800800800B08A00840800000200240200200200200214200210200200802\n\t2802002802042082000000000000002008402002000000122022000000000000000000FFE11A0000004000AA0880000AA0AA0036a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620000041000\n\t6000000000000020408200006406408200000006000000000000000000FF1B310000000828C98548A29C080080088002088A\n\t810002214200201210202424202211A00200200004204C00A000002000000000008108082450000002000000414002000000\n\t400000000000FF544E40080040040240040050044040040044040009012810082010816090011012C9021201221008189081\n\t0110A4199004000000001040021001005009411001000000000000000000000000FF7ED8400100410C04C04C00C00C04C04C\n\t00C00C0094012D351245308300B413013113543053043108013503003502003002000000011010523001003003001001002000b6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2888381B8540\n\t00620A00624602601600214E00628E00609018000400200601018600810000000000610006013E4400484060200000000000\n\t00000000FFA3B30000000018A18258048C102100985304182180000C612208600600E04204A2160060260060200004040020\n\t06000046010000000020006400016006010010016024000000000000000000FFB57A00080400000400002A0000A00B010202\n\t00C012401200005500202164502102A000002000002800648000000014E04000010000004000008000E3064500C00A000600\n\t0000000000000000FF6B3E00008000800000300100104200400800000003000104A01482500C65100D0004280148000100000076a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF7265200000001080C09811401001889803809801800408E08600600004600400C00600600600680000001600410400\n\t0084000000000000006880046007001000254044000000000000000000FFC3630000000018458258C080B8018258300A5801\n\t800044644E00600609600410254E00600600450004608400200E046016000000000000006200006006000000106006000000\n\t000000000000FFF05B000000001805801800801901841881103903880000640A23620E54620440200609628E0061000260C4\n\t0020060A60060000000000800060500004460000800C6002000000200000000000FF8D81000804001881811850801807101800f6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002556557556\n\t000000000000004200510556550550500512000000000000000000FF882E0000000018208A30910818AB8018C01318AB8000\n\t20600E3262A822F2AE2240262AE2AE2AC2802AEAAE0052AC2AE22C0000000000000061014AE2AE2A82A92C42AE0000000000\n\t00000000FF65094000000010208010010010018018C9043801800000628602E0000078060158460060060060000260060058\n\t0400680400000000000000615184000600000004C022000000000000000000FFFB42000000001808881A470F18AB94588180\n\t18AB80001565022AE2A83062AC2244062AE2AE2AC000288A260042242883240000000000000060002882AE2A82A801428800000ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180001060\n\t861260040060060044060060060041000068060000060460060000000000000040200460060000008D004600000000000000\n\t0000FF1E140000000018894ABCAA4AB8AB8A98040038AB8000A2E0062002AC2AEAAE3440162AE2AE2AD6042AE2AE000AAE28\n\tE2AE0000000000000052808882AF2A92A820028A000000000000000000FF94E3000800001314008800003001809812005801\n\t800100604601400600600409010E006006006800006006002006007006000000000000004400006006800800000006000000\n\t000000000000FFB3DF000000001112154954155155955800111955800054E036484556556554400306556556556104516D56008ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF793A00000008104100200010904080180200180180000040844000CC00402600628600600600448404610602A116046086\n\t000000000000004000420006000000012042000000000000000000FF06A70000000318008500240250148018290018018002\n\t08C03608600600600C08202E00600634C00200600E10000600600E00000000000000C1000060060000000820060000000000\n\t00000000FF01F4000000001422800000001000803841021801800200444E0120060040041520D60060060048040060060000\n\t06006806000000000000004010200007001000002002000000000000000000FF6BD200000000180100180000180180188A09004ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AE28E2AE0000\n\t000000062A804808E2AE0060002AE28C006000000000000000FF11D200100005190293011190991195584D95515580004CA4\n\t9030E4545564CC4460065505565544065564D640655655644E00000000000654820A55055000600644E55000400000000000\n\t0000FF4A65800000001810814041801805801803801801800000201022600400610005600400000600400000600601600604\n\t6006000000000006000100206006006006006004006000000000000000FF257000000000388B0800880010808AB8800AB8AB\n\t800022420406E3042AE28622E0042AE2AE00400028E22620222628E2260000000000002A426808E2AE00000022228E00000000cea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000431013\n\t300400701602400600200600400400600680600604600600000000000600000004000000680400C004006000000000000000\n\tFFE5230000000AB8E88CA0888AB8898AB0618AB8AB00002AC04010222C2AE64630C2AE2AA2AE2AC0002EE2AE22E2AE28E2AE\n\t0000000000062A84000CE2AE0060042A42CC006000000000000000FF0E2F0000001038308020230238430018818000018000\n\t00202000600400600408A2D60000060040840060060AE0060060860000000000060001000000000060000860000040000000\n\t00000000FF8C5C0000000AB88288008D0AB8A90AB8898AA8AB80022AA4800163342AE00C2022AE2A82AE2AC28028E2AE2A62002ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF5C\n\t13800000121922C01009869C01C038098218219602312A9042D084D3F6068042B69D64966440400860470060040060040000\n\t10000006440000006006007006004004006000000000000000FFA7BB000000001803A20408001C0061140980544101044250\n\tA002E0AC02702420000720702710E20400600600600600E20E00000000000E10000000000000701400400400600000000000\n\t0000FF314200080000180184004000182200109580000100100048402061068060C308000680600600628000600610600600\n\t6006000000000006000550406006006004004044006000000000000000FFFFA0000000001804800002801A0180100180180100aea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (641E00000000\n\t001E440000086006006006004004006000000000000000FF14F8000000001800801001101C01203C05801C25808030B00001\n\t652C12A14C0240063321460860025400860060040001440200000000060005020060062060A6014084006000000000000000\n\tFF71F880000008588084120110180181188380380190C011205050525440310608C016A028068C4048000046006484010004\n\t000050000046080000080000006816004004006000000000000000FF8665800000045E488030039138018059058218818022\n\t00220008520600609212C4C60061060060101060060065040060040000200000260000000800018060060040040060000000006ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002108036404\n\t0C210004240608E0860060803000040160060000560000000000160000500060064060A6114004006000000000000000FF4D\n\t5F0000000018008048008818C000582580185188402924000060060022160820B602602610600002010C0062260000060000\n\t0000048600000008014000E006004004006000000000000000FF0C140000000018018228018018808010019C188D88000422\n\t000061560162460822A64060160064000060040060261061060400000002860005280000A000E0060E410400600000000000\n\t0000FFDAF100000000181080480D8258208810A1829901802006208802600410605644200E05645E01468000600C00E2060800eea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF2B6D00\n\t00000AA8AACCC8D4CAA9408808AA81808C00002240000021022AA30033A1922202AA18200028A2202AA2382CA32000000000\n\t02AA00051008848A2AE2143222AA2AA000000000000000FF5051000000000001003809801845002000000004000000800034\n\t0408006000080044008000008000046000000100006090000000000000000200026046000080080004006000000000000000\n\tFF2A2380000000000004022400008802800014402000001000000080A0006150000408100000240500006088000000026000\n\t000000000000000150206206000030008006006000000000000000FF217A000000001801A20C08C418001018818118818080001ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000004\n\t000000004000004084000000000000000000000000FF1404000000555921D55911955D01955955A45B55800254600050E556\n\t53600E40DD56436556556200556557556556516556000000001556000500134517556436556356556000000000000000FF26\n\tF70000000AA8AA888880AAA8088A88AA9208C880023220002122022AA02A2224232AA2AA22228028A22A2AA2A228A22A0000\n\t000002AA0000202AA0AA2AA22022A2AA2AA000000000000000FF77AF10000000000C20042400001040000008800000000000\n\t000400000002A40A000010080000008000000400000404000400000000000000002040402000010000000000000000000000009ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200000000\n\t300010000C8000000280020001000000020000000000001000000500040040000080000000000000000000000000FFDC2208\n\t000000002A004022000204000000004000000000800011000004048008000000100000000000000000000000000000000000\n\t0000000000000400800050000200000000000000000000FF01038000000AAC00888C80EAA8EC8AACAA8808AA800023200020\n\t22AA28A00222A2AA2032AA2AA00028A2AA2AA2AA28A2AA0000000002AA00003828A08A2AA2022AA0AA2AA000000000000000\n\tFF2079000800001000400200200004404001405401000000C0000A0050000204005001004804010000040104004004000004005ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF4438010040\n\t084000830800C0090080080CC10A0080020C300204301280A8A280280200210A01200028A08A002082022002000000000022\n\t08200000A002002003003002002000000000000000FF74C30000000000000000002000000001400400500000400CA00008A0\n\t100800020928488020040400800000800000000000000000100000001000000000000000000800000000000000000000FF4B\n\tC80000000000000000000000400003100961100000100008000100320248000400000800100002000000000800000C000000\n\t00000000440512800000000800000001000000000000000000FF57EB0000002003002204100000000002000280000000100000dea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00008001800004004000000000000000000000FF3D6300000000040080082080080A80080080082084000624020022020020\n\t0209200200200A02202004230326294300A00200000000010208255080A062052803202002002000000000000000FFB52701\n\t0040104001851801801881801C554CB84980001468C604602E4D654400608C28F10605600208E08E00400600780400000008\n\t0006006802004006006005004006006000000000000000FF902E0A00800000A9000000021001028101020401020240863C02\n\t410500009504C0E4004054204400C200848841A40400AC0000280002E810502001400002C004004004000000000000000000003ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000600000\n\t0000000000000000006000000000006000000000000000000000006006000000000000006000000000000000FF705E000000\n\t0002000010010000000010014000000001004000000000806000000000000000000000006000000000806800000000000000\n\t001000006006000000800000806000000000000000FF89160000000000008008008008282008888088A8A000002000000A80\n\t0028220822020020020A402200220040000401220200005000022A2A2002004002000000202004002000000000000000FFE6\n\t800C01000000D000004002000524800122400020008890480408048808800001400000104000000018051040000000CC000000bea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (510000000082\n\t01A00043841813801801901819808088680E80C00400E0220060031060460040008060049020060060060000000010040060\n\t00800000004006602444004000000000000000FFCC87000000048001841803C018C3815801C51C0591400264560148060C88\n\t4200609201600640C290108114000407088006000000000006206090100140045006006004000000000000000000FF4B9900\n\t0000000001800009803801801909803881840011600600404400030255642220600E00404000044400004600000600000000\n\t0004006400026006004016002004004000000000000000FF4818000000000000000000000000000000000000000000000000007ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040610612000\n\t0000046004454006802000000000000000FF7DF4000000000023821811811805001821C01003800000600E80C04648100000\n\t612680600600601000000780228400000A008000020826037040200000224005454006006000000000000000FFFB06000000\n\t04000184181184582101391181340582410464260048260800002060C65060162162880084CE100A44090002000000000007\n\t20608810612600580C004C46002000000000000000FFCC29000000000001A05821B01989801801BA1891980000E906004006\n\t036A920EE21A00E026004020986004512006806146000400010415106300826406024007802014000000000000000000FF4000fea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (306CC4026212\n\t006006006204006006810806046006000000010006206904006006006880004804006000000000000000FFCDA90000000006\n\t45800001801803001801003009810000400400400000600400604A0260060060040060065101068060260000000008440460\n\t10800000006000000004802000000000000000FF6570000000000001845811967819019801B03181808002E8160042869060\n\t1404680602600618602080600600040480701200000019101661600946641E586184804016006000000000000000FFF76E00\n\t0000000001E00001E09901001840801003880005308780C347216004007086007806006029106006002004007102008200040001a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000002980\n\t1809801801000201001011C22050420620604E28644280600228E2870A732C0AE20608500602700600000100920F2862A022\n\t00080070028A2C44002000000000000000FF819D000000000011800011801A038018000010498400044004204A3004780400\n\t60C64060860260A000F21608600680608600000080080E006201A2600E004000000446006000000000000000FF9E3F000010\n\t0000418201E1801A61C818F0007081800141458412C00002600418608E11640610601414600E864007007006000000000406\n\t106840000000004000140006002000000000000000FF699900000000040184200180180110190102110180300840040558020081a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (807804016306\n\t456046007814006000000000000000FF2DA9000000000001800003801801800248001015D01000024600620460608708608D\n\t08600600E80003600610450600680400000000020E0E640510E006007003842802006000000000000000FF8C540000100000\n\t89884021809805800230041069808005800610E40488610604E44600680620620E00E0070958060061060000000000070060\n\t8A000800007122002006002000000000000000FF193D000000012045841801841953034001041005D0004441360068060560\n\t5300600200780702600400701642628680611600001052004620F40228630645600A026014006000000000000000FF5B59000041a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020060060060\n\t06006004006006004006006006000000006006006004000000006006002004000000000000000000FFFA9B00000000000100\n\t1801801800000400001801800000600600600200680300600600600680600400600700400600600600080000600680600100\n\t6006007007002004006000000000000000FF48A20000002022058400018418432140080018018100C4600E00600484E00E00\n\t600600700622600C026016420006806006000000506206516110200800006016006004000000000000000000FFE253000000\n\t210351880025811909820000041821C01001650600FC0410692610E10F08600681620400600680500400708E00081002605600c1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080001802001\n\t801828101A204A180780904960060C702E0060044060060060D690600400600666600680600600000000680E00680480605E\n\t006006803002006000000000000000FFC0E8000000080003A0C201A21801021882149831CC810C620708213428600414E40E\n\t11640600680491605700F4464C6086508340006107006000000800005006002002000000000000000000FFAA550000000000\n\t8180000380182980184800180180200060D621620403649400614620608642E02400610600600600600600000000600E0060\n\t00006006004006002002006000000000000000FF4354000000000001001801801800800000001801800000600600200200600021a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000010040\n\t17002006006000000000000000FF599F000000000001000011801800011808041811842080E03602E0821268140060060864\n\t4E0064880062160072AA00654C0000008060060062A8000080006006804002000000000000000000FFA8F4000000000001A0\n\t1801801A00081C02001C01CA0062E2AE22E292AAE28C26E2AE28603E2BE53000EDAE80E3732A60840882A000600700755000\n\t6006007816004002006000000000000000FFAA3C000000000001A00211A01800811810249D359440016556032D4455751400\n\tE5560D6546906804226016006C06007D56000401006006006004800080006006002802000000000000000000FFF85F00000000a1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (628600600600\n\t420380604582E05600600600000000740620E002401080004C2E516144046000000000000000FFD1D3000000000001801801\n\t801801801800201001C002006006002002006002006806006006004002006004006006006006000000807806806002006007\n\t004007006804000000000000000000FFC83C0000000001050118058418008419102198538042206806006802A08800107006\n\t81640700E000101006007002001004400001006107006000006046004006003006000000000000000000FF74640000000000\n\t01A01801801800E01800001921D00100748600743200148184E2CF05610708780144008600600200100400040000600600600061a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020460400102\n\t8A00000205020000000082000000000060604080008602800001000070000000080060480000000000000000000160A60292\n\t00010220006000000000000000FFF76C000000000001800001A41825079840001015800240649641624000008230685E0060\n\t0600440020080444600660000600000000600E206130006216004806942100006000000000000000FF3B4E040000000201A1\n\t5A8190D81121188022B105800340F086842A02A010C301604E426A8F234910C00004807006A0101600000090680E8868288D\n\t0C48A54006003400800000000000000000FF92FF000000000003800001801AA3821812001001800094640721610800640A3200e1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (301300280380\n\t3483042000000000000000FF692D0000000004042003002084002005042000000000AC100104880C810C19021080201000F4\n\tC800800040820D44800800000000000900808C00A20808800028208880800000000000000000FFE231000000000100800800\n\t800D01800808022C80800002200200219000210200302280300203020000200401A00200200400000000200200200008C502\n\t200006004004002000000000000000FFA63D0000000000000198819820400018900084420000010000224400706200080200\n\t800008000088007420100020006500000000080200080008146006441000880400066000000000000000FF41B602000000000011a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002002802A00\n\t802002203002803552000000002C82802C00802802012112883102802000000000000000FFCAE900000000000030A2000010\n\t112020002242010000814014008A4C80100480422C00480510C80280010C01110482100400000000483480482AA44C009240\n\t04015034800000000000000000FF22E9000000000001845841A1180100190000180180000060160162A42960440068060060\n\t0600640000680682648400600600000000608600600012C5062260060AE004006000000000000000FF4AE4000000000704C1\n\t0D00D20B44C28A2C428854800144BA03A4301300350B2820528220034D310100242350B023403342000001003003003309000091a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (435435433233\n\t01541501540000D40CD14D0D50D50C48551410550550D50A00D10550CA0D40D10A88000000000848D50C00930D10510540D4\n\t0D00D50000000000000000FF3DD7000800000400400400400000440644000400000100000080110104102100000080000100\n\t1401000001041001000010000000001001001049001001000000001401400000000000000000FF5A4C0008000000AA0200AA\n\t0AA0A20A80A80880AA00002A02A02A00002882A02A88802A8AA82200002A8A208A02282880000000000000002A80000880A8\n\t200A202202002A8000000000000000FFD23D000000000200A00C00A00A00A00802200A00800880280200288084300A8020020051a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000100C2442\n\t002000000000000000FF22F70000000000AA0200AA0AA6AA0A80024AA0AA00005402A9AA82202882002A8200AA82A82A8000\n\t2892A82002A82883200000000002A82A81800886C82A82B11180002A8000000000000000FF28C60008000000000400000000\n\t0000440020240000000080000000000000810001208008000000000210000080100400400000000003000000482000200408\n\t08008028000000000000000000FFE5FB0000000000AA0CA0AA0AA0AA08C0900AA0AA00000082A82A82282882882A92C8AA8A\n\tA82A80002A82A82882A82A82200000000002A82A80002C80882A82A02400C80A8000000000000000FF0E550000000003543100d1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (530030002030\n\t03003442003002000401441013043041002203001013003002002000000000000000FFCC4F00000004000184180180180580\n\t18010019098C4220600614E40600610420600630620600E1000064160440040060060000000000A620640000402600054600\n\t4046006000000000000000FF9DB800000000040030A20120000020222100120100008200000048008410D500409400400500\n\t080080000488C804800084000000000800804828804820800004A05114800000000000000000FFD4EC000000000000800800\n\t800800800910A00800800028A00200211200200200282200280200220004280202200204200A0000000000020020004420020031a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80300B001800\n\t02805401002000002300002960004800880000404080280062080200000060000000000401000002000060060002A8000400\n\t006000000000000000FF4335000000000000920800000800820831800880800000200A0C0082422182002202082082002090\n\t002400006622002444000200300022032040000002540002006004002010000000000000FF1AA74008000004000004004204\n\t000404005804040A210E92A10012284410291290012292094010502190056010040010000000010010092010210042210010\n\t05001420000000000000000000FF2FED400000000400800C00C42C10800C40C48C4080811134B340315210B04B03348B04B100b1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (460844860060\n\t08000000000000FF43B20008000000019080298A58318D590182584B934000422E01603614020A00628600E0060062200000\n\t1C0064060084061000000000060060006686601480A6060006004000000000000000FF0FC200000000000180800190184180\n\t180984180380000864C610610600450A10E4060B60AE00E04000004400600610000600000000000C10601001600600000641\n\t0006002000000000000000FF8EFC0008000000080000000041100540A011402011401001000905081260001100000C054800\n\t800020E0C0000020086080100000000010100012086006000200510300006000000000000000FFF0850000000200000018010071a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (40022882A622\n\t60022883240000002A82AE2AE620888288220AAE2142360AA000000000000000FF9134200000000023000001800811001801\n\t801801800000600400710400400800600600600608680000000608E502040004000000000006006800046046100006944086\n\t004000000000000000FF19E200000000000990A0018010C1803800841801800000600400624E02610200600600600600C000\n\t02600C00604E00608E00000000000400600020600600800600C016400000000000000000FF48AD0000000000098000298211\n\t01881840891811820200600C04624620200200608600620600641040E48400404601614600000008000400E040080000410500f1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (03931C019559\n\t5580005525564044365325145565565565565560045165560AAD465175560000005505545560009305105505574344441500\n\t00000000000000FFA8450000000001018CA0AB8AA28888D8018A98AB80002AE2AE2AE0342AE2A42AE2AE2AE2AE22C0002CF2\n\t2F2AE92A28E22C0000002A82AE2AE0008AE4AE2C82AE2242262AE000000000000000FF7FD140000000000104000180002080\n\t5A018018018000006006136084002044006006006006006000007807A028120268040000000000060060A040004000000600\n\t408E400000000000000000FF21E70000000000958200AB8AAA430A980188B8AB80002AE2AC2AE4042882202AE2AE2AE2AEA20009a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (685400000000\n\t0000000000FF5DE5000000000001801001801209801800801801800200200614483400600400600600600680400000600600\n\t2016026006000000000006006000806406000806084104406000000000000000FF92300000000000AB8210AB8AB0938A9A00\n\t8AB8AB80002AA2AE00520428A2042AE2AE2AE2AF2AD0002EEAAEA82A2628EAAE0000002A82AE2AF0000A80A82A92AE324204\n\t0A8000000000000000FFD99E000800000021801001801805841C018058018012002006005086006014006006006006886800\n\t006106002406047006000000000006006040206006000807105084006000000000000000FFC95D000000000155915155955D0089a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (28E226002014\n\t2EE2A60000000000162AE00008E08E0002AE2262A40AE000000000000000FF37240000000000A38010018308159410000018\n\t01800020A08E10600404200E00600600600600C5040061161421460060160000000004860062400200400000060160040000\n\t00000000000000FFA04600000000000900100180590100204500180180000860460160960060820060060060063440000460\n\t06212216006006000000000056006110206206000006086014206000000000000000FF435E00000000000110B00180184180\n\t200100180180000060062160860220AA00600600600600500000600602A1060060060000000000060060A0200000000006810049a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (90A88AB8AA80\n\t002042A82AE2AE2AC28A2AE2AE2AE2AE2AE28028E2AE0C822628E2A80000000002AE2AE4402AE0AE0062A82422AC2AC00000\n\t0000000000FFB273001000000001B55355910815509930954155000001440855642855044E5565565565564C650451654600\n\t44065164500000000000465560D0550530006550554556350000000000000000FFA675800000000001801001800881001800\n\t80180180100D4000006000004026006006006006006000026006000106046000000000000006006100006406006000096006\n\t004000000000000000FFF5940000000000418AB0AB8C09208098880AB8AB801006220622622428E2262AE2AE2AE2AE00406000c9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (404000000000\n\t000000FFA1DB000000000001A0040184501584184B80000100000D6000006000004034006007007006006500006006406086\n\t0060000000000000060062084000000040000C4006004000000000000000FF3CC50000000000ABCAA0AB8910218C58858AB8\n\tAB80002062A82AE2A828C2042AE2AE2AE2AE2AE01828E2AE40623E2AE2A80000000002AE2AE03008E08E0042A820E2AE0AC0\n\t00000000000000FF8D2600000000010B801001802841023002801801800028412000608600010200600600600600E0000260\n\t0E2A8146006080000000000306006400000000006000000004000000000000000000FFF0940000000000AB8AD2AB8A284B280029a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060460062\n\t00000000001007046000000000007800004406004000000000000000FF7A8680000000040BA09C01A40004C0DC01843A2991\n\t0102400055E0024041A503600700740600600011600600640600600000018000051E99600040600600600000600600400000\n\t0000000000FF532A00000000000D800401C01001E01A8188045300008A710100650403440CA060260260A620608440608640\n\t4006096000000001000006204400020400006000200044004000000000000000FFB756000800000401800001A09101813801\n\t80040100100060000060060440840060060060060060020260060D400600600000000000000680610602624600600000200400a9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (083807800010\n\t228010641E00C29260604604614E40C00000608400600600600800000000008645400000600E024000082044004000000000\n\t000000FFF071000000000001A31C01C00082801881821C00944040F041006022004028046C0E24E086026100200446206206\n\t000240200000C0080600E43050E406204430028086004010000000000000FFB0C4800000000001801881820000A038018A18\n\t0088A000E08042614252C200016116916C061560805102864062261104000000000004870064002204000040004024060040\n\t00000000000000FFD5D2800000000041C11901800000811801805800802180C00000604A08402584708F08F0060CE00000640069a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF860D000000000001C01D01C02011A31801083843904001200000604C2241224060060460160140100084440060040000\n\t4000000020010600440020621620412042E004004008000000000000FFE1D300000000000192D801140123C8180900180184\n\t8020654800620608400202651620E0A60442C040010400600600020001000000000601600011002008C40010400400400000\n\t0000000000FFF354000000000001803801820001C8190F05982180800020080062042B441200608600602600422800E00440\n\t64060060104080000000060040500000200CC090200104604000000000000000FFF500000000000041A81A8188202D82990100e9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000800200224000000000014000000000000000000000FFABF50000000000AAAA8A8088C8880CC888870150800020\n\t20002AA4042AA2A22AA2AA2AA2AA2203002EA2342021822CA0000000000002AA54200008808A2000006002142AA000000000\n\t000000FFBA0900000000000000585182184244180010812800001000000001080040080000000000000000800061100C8240\n\t006000000000000000480000026046090000110140004000000000000000FF970B8000000000004004022040000020420040\n\t02000004800000024000600000000000000008802000600000000802600000000000000002822840620602000002001000600019a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000000000\n\t0040840001150050050050040042000001040000200000000000000000050000000040001050001040440000000000000000\n\t00FFC036000000000155911D55F15911F5593184593180005060005564CE156515557556D565565560105365560165565560\n\t000000000015565560201143565568004C4556356000000000000000FFA2530000000000AA8AC9108888CA8808AA900A0080\n\t0032A0002AA02A2AA2222AA2AA2AA2AA2AA02028A2222AA21228A0000000000002AA00A2302AA2CA2320000323022AA00000\n\t0000000000FF8F3F0000000000002444000202010000022900020000000000000000200020801000000800004080000000320099a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tA16410000000000022040000004400000404010000003280008000300000C900000080000000000000000004000000000000\n\t0000001000000408000000000000020000000000000000000000FFDDB800000000000000400020400020002010400A000000\n\t0000000000200000000800000000000090040000310000040000000000000000000000040240000000110000200000000000\n\t000000FF2A429000000006AAC888AA8A88CC8AA88880882080000520012AA2820AA2022AA2AB2ABAAA2AA60028A2AA0022AA\n\t28A0000000000002AA2AA03028A08A2AA0002022AA0AA000000000000000FFB25A00080000000120044242020141000040320059a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00029C000610\n\t0600A40C4A08104000000000000004000000000000000000FFEF9D0A0002000000800800900810C028AC8008400500082202\n\t0222420021220420AB202082122100AA200A00280200300B00020802300202208808A0020060060060020000000000000000\n\t00FFC6A800000000000000000000000008000002801000010200000000008280000000000080402000020080000000000008\n\t00800001800000000800000000000000000000000000000000000000FF8C6700000000401000000000820012431008201000\n\t010000E0800000AC08080008000000001000000019010800004000000100001004008400400000000000008004000000000000d9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200402000082\n\t00000100000000420000000040001000000020840555000000900000004200020000020000804200800000000000000000FF\n\t23E3000000004010800800800800A04800802800000020305B00208A00A41208300300A00A20202001234A1834020220236F\n\t00000421020420C0022002022002002002000000000000000000FFD2B1140004000001801801909C09825D5582585004800A\n\t602700604611610604614600E024506100016004087006006006000000007007006088014806006005004004000000000000\n\t000000FF52BC02A022000003001000000001109001110000602102070404C6244412D80050156241040440015490358002240039a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF8F67\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000006000000000006000000000\n\t000000000000006006000000000000000000000000000000FF52B70000000000000000010010000000000000000002804800\n\t0000000000000008008000000000000060008008010060000000008000000000000068060000008000008000000000000000\n\t00FFBA6B00000000000000080080080089088080280800002020048060CE03200208200200A00E28400000220E0020044020\n\t00080400002242082090004002000000000004000000000000000000FF9B6D02A0220000040000000000000000080000000000b9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (064100100045\n\t86806010126006004000102006000000000000000000FFF5F4000000000001041800805A41A01A09C0108000008061050061\n\t060122060060860160020040000A606002C606006006000100004006006000000000004020000006000000000000000000FF\n\t9D09000000000201481801C8180180185380030021404160240064070030C601652620608202C020B2108000D00600000600\n\t000080610F2A6B2800800000404008C016000000000000000000FFC22300000000000100180180180180190190A002000010\n\t64044160061002060060060464120044000000000440060000060000000040060060000460060040000060060000000000000079a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00400602600\n\t61060878060061050060001060070C0034006024200000037006006480050008017017084004000000000000000000FFBA90\n\t000000000243A01804021A01811801A8080000020060058064460048260AE2060AF4060060208814C600A22C200525000000\n\t9360060264C00080502140B6002004000000000000000000FFFD9F00000000000180180000182180194589480001234162C4\n\t4074861160C600E24641610602E0404000860020040008040000800060162A734880E00600400608880C0000000000000000\n\t00FFE6980000000400010A1800A97811845801801202200009401410F006842016006006026308004200016801904106017000f9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF8ED30000\n\t00000001843801800801C01C2182000000020844061260160024140060260068840060000068460234060478060000000060\n\t06206100826006006004402800000000000000000000FF5AE7000000000041801801822801E019018022C0000328400C0878\n\t06002005806006096206006006026047012406826416000000004006507800000120006144000000000000000000000000FF\n\t7F1D0000000000058198180118E78458A182BCA000022860050064061C60D6656466646004806040036506020104C3610D01\n\t0010106D062DE050126086406806806004000000000000000000FF51340000000400018018020018898098419298006003000005a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (044000600642\n\t620800E90624E084202002000000000000000000FFB212200000000001801810001801801801C25000008001420504710680\n\t240C04E04600602500704802604E4464460260070012012060062A6881200020006024020002000000000000000000FF9DBA\n\t000000000021801801C00641803805A00800014200480E80690680600401630604602408610804600E402046007006800A00\n\t20600602E420006026004056026000000000000000000000FF8C8A100000580025831816C00011801A1181C8762022614804\n\t08606E6040440460861A608601E0C000680600300700600600000000680690621042040000480E18500000000000000000000085a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00600E80E40E\n\t926914144140806010096D060000840068548A6C46896106A16911016457006086206000000000000000000000FFD5FC0000\n\t00008001801809880181801801821808208140400701700E00410602600E0060240464008860462166B640642E0100006C66\n\t06006840006007457807116002000000000000000000FF462F10000802000583588280085B805C5780181000021048B62060\n\t8600604E00E48602608412600400628600600E00E28600000102F0A701E0F1801E2800600648C002000000000000000000FF\n\t0792400000000005889841451821E018C18817400003B0400400E20600A28408600789600500721081704600E006247006150045a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (63DB00000000\n\t0000001801801800801801801801800000200400400000600400600600400000600000600600200400600600600600600600\n\t6000000000006006006000000000000000000000FFF059000000000000001801A01800801801801801800000100400500080\n\t6004806006004000006000007006002004806006806806806006806000007006007007007000000000000000000000FFC837\n\t000008248000001849809801801805841801800080200440628600600601680601400100600400600620084404F086006006\n\t006026046A00000100006006006000000000000000000000FF3FFD0000000000041319038C184D8018C188195180801000C500c5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (204804005000\n\t000000006C06006000000000000000000000FFA9DE000000000002021801819800B800118C3881800000420E200080086004\n\t046426006020006100806006004614806407004006106006016260006806007006006000000000000000000000FF55D10200\n\t00000209001809D4390181008591390D9080A8649643214281621428E0C60B6000417000007246D360040860860840B60370\n\t06906000008080006007006000000000000000000000FF7DD7000000002023029801801801800041801821844004E0461022\n\t104A60C400600E2062A014604802E08E00608444E00E00C0060064A6006400006006006006006000000000000000000000FF0025a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0600E087287A\n\t96106310004050801006006005001002002407007806027001001001006206006040000000000000000000FF95A300000000\n\t0200801801A018018058C3901805840050200690B13700644E00602600E02028428100648E81600E0060A280200620600600\n\t60AA000880006006006000000000000000000000FFDE8A000000000000801801821801C01901801825882122A8A60A322E20\n\tE2AF6AE68E2AE0801AD5F802E3BE2A68862AE28A08A0AF0AE2870C715000E186006007806040000000000000000000FFB5F0\n\t000000000000001801801800804045901811F440536457111550016335086156116550406004806C2601400C0070C600440700a5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000009\n\t0C5801821883803811823801800040E8A652C00344EAAE04602E08621040608000E844444807007006006006124004094288\n\t1108402060D6906500000000000000000000FF6B050000000000010018018018018018018018018001006006004000006806\n\t006007806001806000006004804004007006006806004004005000006007006006006000000000000000000000FF93940400\n\t0000405181181190590001015585181585001020070110070460068060060064004040000000268160168000020030068060\n\t46016001006006006006006000000000000000000000FF85EB000000000001801801801800000001801809F02102A43700020065a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (510002020162\n\tA6001080080010000000000000000000FFF97F00000001004A48000000A08204A00000040000030201280000008100200001\n\t110800408000000070004106800064400800000000203801D228610E210028050280000000000000000000FFB2E700000000\n\t0091101841A91841800283801801800080600640E2BE02600650622682630000600010080400600600000600600600420400\n\tC40800600600E006006000000000000000000000FF596B0000000002A5209AA988DA48AD0085D01A038000142A16806AB400\n\t680708EB0644604010E800B00004806D06A09027086886A06C26A06820A40A9084E806A06000000000000000000000FF359000e5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B20B4830C200\n\t294088300141240220304301344348300300300308331302329344B543002810000000000000000000FF0A39000000000500\n\t20832C2200002A404030004000088D0801231104800C00800048000009304800E90004A61040A00800004000A00800000800\n\t868810800551201000000000000000000000FF8B3A000000040020800880C00808800A108408008008200002004002C0620A\n\t0C200200002100800200A00100400201A006002002002002002020004402462002002000000000000000000000FFC6F00000\n\t0000000107200194442410040C0A200200025086801804043480900290812008000904800074200001100060205100800A000015a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00200202800A\n\t00A00A00800A00A22A008002C0AC02802802B1282A802802002C50802800802002842902803083002002C028028028128028\n\t430C304AA42100000000000000000000FF63F100000000024040122822B20040020121100100028A49100040048048010048\n\t0000410009484082011490C80880100C004004930800000800A24A00808880808010000000000000000000FFE7A500000000\n\t000181180190B801801801801801800A22620640429408600604601680600001620010680603648E00600400C00600604E80\n\t6040014006006016056000000000000000000000FF94450000000284A8940CC4840C24CA4854D40840800A08B083893802440095a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80282A80882A\n\t82A03402A8000000000000000000FFDEC30000000003503543002241541543541000000000B10D30550D50900C10550D5055\n\t0B48D50840D50540D40D50D10CD0800000900D50D50830930950C48D08C00550000000000000000000FFF90C000000000000\n\t6004000400000000004000000009001000000001049000001000000000001001000100000001001001000001001001001001\n\t001401001011000000000000000000000000FFD1570000000000880AA0820800AA2AA0AA080000000A0000202A82A8020380\n\t2A82A8AA8000220000288A202002202A82200000000102A82A8020088088200200080220000000000000000000FF19AB00000055a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002002002002\n\t00200000281209200200200200200000200200200000200200600E042000000000000000000000FF20F70000000000AA0AA0\n\t024804AA4AA0AA0C400000082A82A8AA8AA82002A92A82A82A93A12A80002E92B03212A82A82A80000002A82A82A80000880\n\tC82AA2222122A0000000000000000000FFE90200000040000200002C08840040000043240000080200010000002480210000\n\t01000000000000001008010000020000000000420000000000200400080040148000000000000000000000FFDA4700000000\n\t02AA0AA0CC08A0AA0AA2AA08800000002A82A92A92A82802A82A82A92A82282A80102882212282A82C82A80000002A82A82A00d5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4C04C00802C0\n\t0C20C04D02C02C08810100310300344B00220B08B0230034C30528000030030430020030134030010C311345280140240200\n\t2002003000000000000000000000FF2F720000000018898018098C18018C180180180194400160065441042AC02604428622\n\t600E20622043635610602602E00602421020620600420000400E404114006000000000000000000000FF4A83000000001000\n\t201330022201201000431001000000080000400488C800804800804808800808800004800800801005004000804804804828\n\tC44C21001100888010000000000000000000FF7BD5000000000A00800800A10800800A0080280080008020020020020420020035a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A6246450220\n\t2A8028008000000000000000FFEA0704000004402300000380000408010000000000A00000040200000504C0004508420016\n\t00E4402462A8080020046008040408430020100400006016200088000000000000000000000000FF91FA0000000000888009\n\t08880800862002802820984000A0020062862C610A02204210230200200000A41070A00200240020200000208A2264100142\n\t13001101002000000000000000000000FF4D3E00000040044040000042042440040040044802017810F92810290001010890\n\t310010A1220000001005431000189005005001091241108019200000000000001000000000000000000000FFD1C00200004400b5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (06346286106A\n\t4000600C016006106406406000006206002C000C04090072B70AE140010000000000000000FFBA8100000000108080194198\n\tB97990200002D813848029002605800A01620620020600603E4D72802000045060060000060060000060AE0030A001004044\n\t600E006080000000000000000000FF40F400000008108180180382500182802C00184580002C000600400402248E04044E00\n\t604600710848840400600600004600600000615608315000600600E006406010000000000000000000FF9A80000000080000\n\t00802404010210805400405004000482800C02A04080300200084204064360280960000080000860202000000004001000000075a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8AB8AA8AB0B1\n\t8C08AA8AB8AB80000002263004462AC2862AE066226006A2602028823620E826288004A322A845E14649E0002E80880364A6\n\tC16000000000000000000000FF64F400000000184080180080100182080080180180004020060C10B200004E00600E006006\n\t10680004001604620604054C10200040608640680000600600E20614E000000000000000000000FF8EA10000000010008018\n\t0180180B80D001001801800015411601240600600600030611600601600000608410609600600601600012644E0420500064\n\t26306016206000000000000000000000FF1D0200000000100180980180900380300104980188A00044A610254A206046400000f5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (070470460068\n\t00000000000000000000FF165D000000001935955954155911944954155955800044455455244A5525545505565560075560\n\t14516D56D555565564CF4D4550556556556040110110006007086000000000000000000000FF98CD0000000018AC8AB8AA8A\n\tB88188B8AB8AB8AB80000A02A62280062AC22E2AE2862AE0062AE0002AEA26AB600E2AE0542222A808600E02602848E2AE28\n\t610F0A6000000000000000000000FFB886000000001800801800801803801801801801800009200600000200400600600600\n\t680600600000680680600600680400200000600680601024004014E55622E000000000000000000000FFF81000000000188A000da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600400480402\n\t600600C00602600E01600000600600682100042088E8AE82E000000000000000000000FF530C000000001814801800001901\n\t8408008018018000456004082096004004004006006006806010006006104804006086804000006006004008046006206006\n\t106000000000000000000000FF24F60000000018808AB8AA0AB8418908AA8AB8AB8000006AACA23302AAC2AC2AC2AE2AF806\n\t2AF0042CEAAEA202AC28FA262A42A82AE2AFAAF004288488426206206800000000000000000000FF01E00000000018018018\n\t000018238008000018018000415014802896806084006016006807006820006106005546006D071040000064069068008060008da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A81018AB8CB8\n\t818AB8AB800002644421809E32021601C0142AE2AE2AE00028E22602420628E2262260002AE2AE1E600008E08E0060560060\n\t00000000000000000000FF222F00000000180080180009580180180980180180005161261404420000560240060060040040\n\t0400611648E006006086106000006006006004020440006026026000000000000000000000FF250800000004380080180202\n\t1801821825001801800000440C00000610A0843064D60060060060000460060040AE04601601600000600620E0084060064C\n\tE49648E000000000000000000000FFEBAF00000000184080180000184D80D801001801800008400401104200200400000600004da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00600600000\n\t0000000000000000FF574D0000000AA0AD8AA0AD8AB8AB8858A38AB8AA000024A2AE00602602A2AC4862AE2AE2AE2AE0002A\n\tE2AE0D42AE28E2AE2A60002AE2AE23600848E2CE286286286000000000000000000000FF3691000000150155954551855955\n\t91194595595400000261164460C640E54210452655655655600455654C0B44CE5164D6446000556556416010150550526506\n\t52E000000000000000000000FFF664000000000001800001801801851809801800000008200601610E50600200C004006006\n\t00600000600640400600600600E00000600610600000600604602E056000000000000000000000FFBEED00000008D8AA8AB800cda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000026006\n\t49400600600608400000700600E0100062464C649648E000000000000000000000FF2CB5000000000001801401801801809C\n\t0180180000010020040464462060048250070060060060040060060440060060060040000060069060000400000060260260\n\t00000000000000000000FF01EF0000000AA0038AB4898AB0AB8A18818AB8AA00002822AC74E48E0062AC04C2AE2AE2AE2AE0\n\t0028E2AE0042AE2EE2AE22C0002AE2AE2260002CE08E01E006006000000000000000000000FFAD5C00000000000180000380\n\t1001805811801800000030A00608620602200442000600600600600400600620400602600608E00000600600600040000000002da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3851801C09E2\n\t3E20004010604600789748E14200E2060A642600600000600600604410620400200000600604640000000000600600600000\n\t0000000000000000FFCB2C002000002061A80C23B41C21C01C0180391200A081210681740E206482C6702700600600640000\n\t60061160040860040124001E704682600005E00600600E006000000000000000000000FF6C12000000002401840441C01201\n\tA03801801802050022200C10682602201508002E0060864260044D6006024406416006005000006094004000000480006016\n\t00E000000000000000000000FF0D8F0000000000D1A00023A0100180584D801800000003200488600615200430600600600600ada040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (506510010000\n\t000000000000FFA0EB00000000000184120980182B8078898C1828060051206200608E04020230001620610640E000006002\n\t04600602E0060060000063042040080C602600602E29E020000000000000000000FF4254000000000201801C838948018218\n\t05805882000000440C53600680600682644E0064000A041020004600E10408004400280000602E00610000E3164AE2060265\n\t08008000000000000000FFBED7000000000001C01801B22809801C098018C8000004610C09654609642E4162061462400204\n\t0055000608E42441040400A20000602E006200000500006006006000000000000000000000FFDCC6004000000001D0080580006da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000463200100\n\t080060001100000002084C00004060064C8490488000000000000000000000FF61DC00000000000180148381182580395390\n\t1902020000403028601600020640005640640000010000041244608600010611600000600440420000628602E20600604000\n\t0000000000000000FF8B310000000000018010099059018A9801841810000000400000610600208604040604E01013000820\n\t0102006006000006006000016016106000000050106106056000000000000000000000FF5423000000000001801001801891\n\t889821825840000000240205600600208200000602E00E0064801862CA2360061560C608E00000E4440843101100004060D600eda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000400000\n\t0000010100000004000080220000800004020000000000004004000000000001000000000030000420008000000000000000\n\t000000000000FFFEAC0000000000AA8C8AAA9C00AA8AA8AA8AA80000000003222AE2AA01A2024CA00A2AA28828C00028A446\n\t2A02302CA2243360002AA10240203808C08A010000002000000000000000000000FFC8250000000000000210018000000000\n\t0000000000000400080000001200080240000000260260000060080001000260900000000000C00080000264260000200200\n\t00000000000000000000FF83CB00000000000000240003400000000000000000002881000000002000A04002C00000060060001da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF52B1000000000201400400003401001001401200000001500000400404000088C3108040040040000000840040\n\t04000104004001005000088040004000040028050000000000000000000000FFB786000000000155D43D5594595595595595\n\t5800000042644755755648E4570045565565545140005564CC556556556556554001556D5655600055411652450452E00000\n\t0000000000000000FFAAA90000000000AA88A8AA8088AA8AA8AA8AAC00000032324A2AA2AA2822AA8020222AA2AA2AA0002A\n\tA0122AA2A228A2322220002AA24A0220002AA2CA282282282000000000000000000000FF0273000000000400208400008400009da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001000004000\n\t0000050000040810111D00000001000000000040000000000000000000FFAB82000000000200044400020000000000000000\n\t00004400100008000001504000010000200000000000000000000200000800008000000000102200204C0490488000000000\n\t000000000000FF78300000000000002080000140000000004000000000080000800000100000820000000000000002040110\n\t000000000000010000000000000020000000000020020000000000000000000000FF86A50000000004AA8808AA880EAAEAAE\n\tAACAA800000010A2B22AA2AA26A20219A2AB2AA28A2AA00028A2222AA2AA28A2AA2220002AA2AA2AA00008A28A00E0560020005da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800820080021\n\t00D40400C10414432C00500501C00C1442402404040000040000040900600010000410283040000044444040000000000000\n\t00000000FF512200000A108200800B02D008008008000548008400042A1300208A2A208200280222A0020A20800220020000\n\t02803002008020002002022000082002002002002000000000000000000000FF4A6C00000000000000000020000800000400\n\t00D00140000040020000000840000000000000000442001A000000008008000000000000000000020000000002A020000000\n\t0000000000000000FFC9BE0000000000000100000004001A800001000000019004010004000088000000408008400000000000dda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF9279100000000102000200000000000090284000002009000000800000043000080000C81000420000000400000400\n\t0001000000040000001010000001280000004020000000000000000000FF803A000000000260810800800808800808000800\n\t800000200200200200200200200200280200200040200200100B0020EB1100000020127625400A2002282002002000000000\n\t000000000000FF8227000014110001801D059018098B1C04053B2984A0044037046016414824004004244004004280006004\n\t000006006806000000006006006000004006006086006000000000000000000000FFC5E20800000000820000000010010012003da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040006040006\n\t000000100000010000006006004446006000000000000000000000FF8B410000000000000000000000000000000000000000\n\t0000000000000000000000000000060060000060000000000060000000000000000000000060060000000000000000000000\n\t00000000FFCA9400000000000000000000020000000020020000000000010000000040040040040000060060000060000008\n\t00006000000000000000000000006006000000000000000000000000000000FF7697000000000000800A0080080908080000\n\t8810800080220600020200300200282200282400000000200A00002880308C0200200020020120005440020000060020000000bda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010104000A40\n\t062862969884804004201138E603E00004602000001680610608001008201340A14001E04600400E00E00000000000000000\n\t0000FF66A6000000200001801801809801821800020009800004410600E50680000000000010200600600000704000000680\n\t6006108000004000004000000020004006016000000000000000000000FF0DE4000000000001801C00809C01821A40200109\n\t84009004060040061000403200008420000100021000100010060000060100000220464C30020D0D20004016006000000000\n\t000000000000FFC5110000000020210018028018038118000200418100000026514006008100000240002140040000000000007da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFB7D5000000010040849209821801811D42001901E001802106047886006000006136016006506009406006000815026084\n\t0010008064062860204010204C6006006000000000000000000000FFBDB30000000000038218018038818098002038010040\n\t80A0A60041260040800441168050015000081008060002040200040000800462070960100C00002B40062060000000000000\n\t00000000FF2AF7000000004040801005801805809C0000194184800023260040060000203204060A400000000010000E0200\n\t040200040000000240253240000C7506004246006000000000000000000000FF3CFA000000010041801A15851A158419600000fda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (460060060400\n\t0000400500540000100011464607E000000000000000000000FF4AD300000040004180188188183180180004000580004000\n\t0610C00E20600000600600680688600000600610940604640600000000600620700002600600600600600000000000000000\n\t0000FF59E2000000000001001A01E03801841810000001800004800600401610688029620000604601600400605601080600\n\t6806000040D00100000010800400006946806000000000000000000000FFC22600000006000580F805811975807A0A005801\n\t04401A20460260460654640CC026106006006000B4602E6084049870040009302C6097016701356B860176A74060000000000003a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000020404640\n\t788600C302085C0624604780600804600600044782E006030200006107B571290A604604E206086000000000000000000000\n\tFF9E21000000000000051101821840025800020041000040C01600400600040200002008722E026024806806000406026006\n\t22100002480422400102020002F006006000000000000000000000FF76980000000000038A1805001801805E00001E210000\n\t00E08E00640600604000600C00682E00640000600600180600600620080182608E0270200062060440060060000000000000\n\t00000000FFD5EB0000000001A1091C018C1809C4180000780100018060860CE246006C0004604C1074070C624400600608800083a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF3F\n\t230000000000048000498D5810951A81C0140C000120605180608000522410688404604600600A0A60060568160060260080\n\t0601615604643213600692600E086006000000000000000000FFA3F2000000200001861801801808001800401C0900001160\n\t0E00600608402A22400518600600E04088716600000605652600000002682E41600100610601600F00600000000000000000\n\t0000FF741A0000000000050018AD809800009880001807000108E2860C405E40784204608400600608602400708602804E80\n\t668600000880C914004640008280187046006000000000000000000000FF99F70000002080028010018C39001438400100010043a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600444040600\n\t6006446048006006004006006006000000000000000000FF0E21000000000000800001801800801000801000000000400000\n\t6000000004006006006006006004006006006006002006000006004004004000000000006006006004000000000000000000\n\tFF6D1A0000000000008002018018008012018010000000006000006000006004006805007007006000007006006806006006\n\t000006006006806001006006006007006004000000000000000000FF2E28000000008000800101801900A038418090000000\n\t00628028601011411444420640600609600400600600644680200604020F024804104900000C41006406006006000000000000c3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004540D0D550\n\t916556154550546557046A4E01600650E456002205000006200A01000002000000006026006006000000000000000000FFFB\n\tD100000000800190600002181980008B8EA00A00808A6000A0408100708600400480622E0260008060060060060066040000\n\t070068060067A8006806007006006006000000000000000000FFBE82020000000020A11000041801C4091590115004C03440\n\t002D4100526507105000116006006806006926427006D2B0140880860D400401400200000000400600600600000000000000\n\t0000FF391101000001200880100000182190480181500210000042C000423000E05404608C24642E32E20013600610E026000023a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF0FE100\n\t0000000000801801801801800801D508206020A060000264010364060179480040C104180880800600644200000200000600\n\t7806007000000001004246206004000000000000000000FF8509000000000000A00803C01C01845C0080080C0A0100634049\n\t70B00848B602640652421600E2A0006A2E50F01200220A000006806006006020000800006816006006000000000000000000\n\tFFD4E7000000000000880801801801C0180500080002004062A00CF22806C22F0A708E08400629E30002E4F602E00222E01B\n\t2A828698E10700E040006006006416406006000000000000000000FFA0C1000000000001800004001801844020950052144000a3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4A0C06942922\n\tD02A00848900A04307086824000000000000000000FFA56F00000000013180D041021881003003001000000108600040E000\n\t00824208408708E5175160090061021030570131060000062142048340A8480228044026006004000000000000000000FF65\n\t3900000000020080100100180100100100160000000060000060000000020040060060060060008068020020060078060000\n\t06002002802000006006004006006004000000000000000000FF5776050000004250811801C01A41944A22C0014010404060\n\t00047000D00006086000456000800000101004505042104002000006AC4284444800006007004006006004000000000000000063a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002080092350\n\t088890A40350070061104064200000C040F0000900000004000500E00060C6061000400420000000000000000000FF66EE00\n\t0000040002000000100184040002000000000050000010001180920080101800119709600000610002040800620042000028\n\t0300288110236036001000000000000000000000000000FFFE76000000010051821089A3982100A004800000000002600040\n\t640010013610410000600080000820080200202400411600000610002002000800E106204A86006004000000000000000000\n\tFFB0DD000000000204B21295809A29248281B280A0000082E0210A60084A090A034C28C46800000800A0022284AB06B0140600e3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFBB0E000000\n\t028554C84C50C88F08C82C10D420800001032841402208D0A8A2D220CB0D2082003129202102003223413C0A00100320310B\n\t02B02910310B442003403402000000000000000000FF7CE00000001002243842402004081040102413000000008020880800\n\t4804C042024110820830C84084128408CA00880480000200C38890C00A00884800800030884000000000000000000000FF23\n\t2700000000000080893080084081090093002000000020400200000020028400022C20040000001030030020022120062000\n\t0200200210240010020A410006002000000000000000000000FFD7F800000000018900300200001042008008C0C000010D080013a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006082007000\n\t02488288288AA82A8000000000000000000000FF3C40000000400482AA8B50800A24A00A00A02A00000100A0004020008028\n\t8288A002842842042800802002003012842883000002902912842B22A42802802002002002000000000000000000FFD7C300\n\t00000002302022020010002000002313080000840001025000094014404CA409080400488082008400510080001400000482\n\t0840910808804840824005004004000000000000000000FFBA8B000000100001801881A01825851883809820000050600010\n\t600000440C00600480600C88C000146C0400400600610440800610E40648650000C0460168160060060000000000000000000093a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (82A8488000A0\n\t01003202A82A81002C92200002A82A82A80000002880080001082C80882A92A82A8000000000000000000000FF4811000000\n\t20025420A2A01543543542003002A00000C80550441551130CD0481208C90510510A00D11440000C40D10C40800000900B00\n\t800B08950950C08550550000000000000000000000FF6A7D0008000004044004026000004000004404000001000000800800\n\t040040120C110100000014010001100010010010000000010413414C1401001001000000001000000000000000000000FF10\n\t8F0008000001000000000AA0880AA0000C002200002802A80882A8220220060008200288A88202288A2800032028833000000053a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E80000000008\n\t02800802800800800A0080A000000005200000200200200208A0020020028020000228120000020020020020000220524020\n\t00442002002002000000000000000000000000FF5FE60000000000400AA0800AA28C0AA4000B40AA00002102A9AA82A92215\n\t108310482A12892882002882A00002A82882A80000000000800902400884C82A8AA82A8000000000000000000000FF3E0600\n\t08000000000C001220000000000000A00A000002800111000040000100812004104104010204009000001002000000000002\n\t8028048040000200141000000000000000000000000000FFBC210000000000880AA0B00AA4A80AA0000800AA00002C02A82A00d3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000900930100\n\t4281001001001000000000000000000000FF1A26400000400CC0900808C00C00C02C04D00C20804148304111353310B49352\n\t301300301304B00002302300108200300300301105254B05300100220B003003001000000000000000000000FF702B000000\n\t08D80180182380182180184182301510800062902260062040260160862AE2A4004000016006000004006036044000206006\n\t206400004086006006000000000000000000000000FF04D20000000013492002484010444000002012010000884000004004\n\t894B50404CA4810844044880800004001004841000004000B10C0082C94A804A20804004000800000000000000000000FF740033a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (108048048008\n\t020046036040446000200248096028088000000000100000006016200028308028000000000000000000FF83A30000000001\n\t000810310400010000200C502100000805000402C80140D00801101505260060000060000000000060240200002004002001\n\t00006016000000000000000000000000000000FFFC1F00000008202081080284082084680280180E8E800000080820020020\n\t0200A10210201822400000A0E400018600200A00620800A0A2022000440102140106040000000000000000000000FFF14D40\n\t080040840000000044040040040040040104212010212090012812012210012010054090000211010010000010010014010200b3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000010018A\n\t1800081821001009900100000020442000600602000401600604600E00601000204440008E00002E40600000400600610000\n\t0008204036028028000000000000000000FF485E0008000010018308040918998051088C4004114000032000E2160340940C\n\t600600600025020A00000403800601000631600000608C306282488300044606400000000000000000000000FFEBF7000000\n\t001001801800045901841000800010020000800041642608012410608E086020400440224004040424106006006000004094\n\t406400156406104086100000000000000000000000FFD9AE00080000000010000200A04000008002408810C04100802000480073a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0064C0000000\n\t007007000000000000000000000000FF6F742000000018AB88C8818AB889881805B022010000002000226006200444446696\n\t146288A886002A80060000022882260022A8206206206130CC80A8204AAE2A8200000000000000000000FFF40B0000000018\n\t01800841801A21801851810000000002200000600605033420600E80E84004080000441640082A00690E0020000961460168\n\t00226006104006800040000000000000000000FF639D00000000100184281200180504B0850C0000000049400010E0060840\n\t041360465260060060800060C40A848602600400600002401414648800640602C006000110000000000000000000FF47CF0000f3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (061160460070\n\t060068000060861400160071060040002C6506206040006006006006000048000000000000000000FFACEC00000000180190\n\t5913955D30915825900400000055000055600635254655602755751655600455254F5484D655144E0045505240C4446014D3\n\t0550556556550550000000000000000000FFF2BC0000000018AB8A88A38AB88B0A38A1C2800100005060002A60060AC00E00\n\t610620E2AF2AE0802CF22E2113222AE2370022A800E04E0AE20088E2CE2CF2AE2A8280000000000000000000FF035E400000\n\t0018AB830821801803021881C48001000000600000600600001600630E00602700630000380680100200000600200000620E000ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0018C9800805\n\t801A4484B881804000000000480000600608203200624600680604680400210610088E20080E806000316046206034220200\n\t006006000000000000000000000000FFF11E00000000180380C84180180080184D201200000000200000600605630200600E\n\t00602680608004601600800604608600400000620604E200806046004806000000000000000000000000FFABBF0000000018\n\t018A08898AB8888818118AD00000002AA0002AE0062020062AE0862AC28E28F20628AA262202260883260042A803608E1970\n\t820880882AC2AE2A82A8000000000000000000FFC26F000800001801801811801C4081181180540000000310000160064061008ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000044060060\n\t06000006000000000000000000FF1CFE0000000898AB8AA88B8AB9008E98110AA0AA000021E0002AE2AE2AE2022AE2AE00E2\n\t8E28E00028E23600000E08E00E2260005460062AE00008E08E2062AE000000000000000000000000FFFC3000000000580180\n\t080180180000380D800000000000600000600600200200600608602602600400210E00000600040610600021620600600042\n\t0000046006000000000000000000000000FF154F00000004180180084180195280192180000000000A400000600600615200\n\t60062260060060000460060003464460C600E0000C60B600602000624608E006000000000000000000000000FF9099000000004ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000600\n\t60000000040000AE22008E080000006226004000000000004006000004000000000000000000FF06FE0000000AA0AA0D5889\n\t8AB8AA0AB88182100C000022E0002AE2A804640C2AE2AC2A82AE2AE0002AC2AC0002260AC2AE2A80002AE2AE2AE0004AC0CE\n\t2AC2AE000004000000000000000000FF40D0001000154154155910955854111943955154000048600055655054450C554556\n\t4C85565560045504C400040611044645000001611655404055035054E556000006000000000000000000FF4A898000000000\n\t00001801801800001843881000000000600000600040E086006004000006006000004004000096004006000000006006006000cba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000098418018\n\t0000184394588100000360000068011140100040060000260260000040060001160040040900000060060060004240060060\n\t07000006000000000000000000FF093E00000000000112380180180420181180103100001060000060004443208070060060\n\t06006000044004000006444004000000006006004020004220007006000006000000000000000000FFCFC50000000AA0AB00\n\t18CF8AB8A80AB89181D14300003040002AE2A81060402AE2AE2A828E28E00028C2AC00022648C2AC2200002AE2AE2AE04008\n\tC08E2AE2AE000006000000000000000000FFC8DC000000000000001822801800005801801000000004600000600001602400002ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (405000480600\n\t0004000000000000000000FF4931800000100000800001801803801801801814010000610001610002E20228E02602004E42\n\t600808400E01000200400208050004E006006500004000006407400006000000000000000000FF03B4800000002044800001\n\tC81881C1188380900A068004508014EC8092690308701C1100061060400444040400020C4002000000126226386000604006\n\t007006A00006000000000000000000FF1CEE000000002400401880E818800038838098000040486808006029004820005087\n\t00600600E08440C00640040650400C009000006424200000004050007006000006000000000000000000FF561B000800000000aba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (446086406000\n\t04400209000602C00E1500000064040040400040084AC2CE000224000000000000000000FFC9A70000001000450810230238\n\t0B88D8018A108A0A2012C0900066501040480063C00100265363A800400000040600402609000000600402A0880042060044\n\t06208004000000000000000000FF2693000080000021C00000A0188184180580980001002060000061280A60C00140002AE4\n\t1050000002400E4484821040822310000062160040203541064040268A000C000000000000000000FFC50180000000040180\n\t010180180380980180100000204440000C600081628021480514603004005052C41444800044400A10030011600600630200006ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A04000000000\n\t00000A000000001480000000004803502202201400060064C00060A80000080060000000000000A842042000642601000000\n\t0040000000000000000000FF5C77000000000001081C22003C15809805881802000002E0000064000040D000430001642010\n\t005000400A3204860A404E0000000060140501104841060040164B044C000000000000000000FF51A900008000002100B001\n\t0098019058098318200B4000448044E0C048C4000C400010610802030000400200000600C106400000006006002000054408\n\t154286000004000000000000000000FF792000000000000100B001049901843809801930000040620022E01024C2000B600000eba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2CA2AA000282\n\t000000000000000000FFA4240800000004082002004004010000002002200000000001000801000088800000520004000000\n\t000000000000201014000000000000200280400000000804000000000000000000000000FF7B2E000000000088800CCE8AA8\n\tA80AA8AA9008AB80000020002AA00002011200048A00228828C0002AA4060005D62AA3220000002AA0120424802AA08A2002\n\tAA000240000000000000000000FF199800000000000502100180040580000001400100002000000000000080041080042100\n\t26026002004400000440004108000000000400108010004006120000000108000000000000000000FF25E880000000004008001ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A28A0000AA2\n\t320003220AA2220000012AA2AA0020002AA08A2AB2A80002AA000000000000000000FF99C900080000040024440020120100\n\t10014004010000208001004800A14044C1491402000400404000012400000400100400000000414080008000000000500400\n\t000C000000000000000000FFAD2B000000000145953C95955955955955955C0D00005560015560005564445574CC01655455\n\t45105564C400045415654400000055655694E048156536556556000556000000000000000000FF17600000000000AA888888\n\t8AA8AA8AA8AA82A8AA80000A20002AA0000C24020A302248A2AA2AA2802AA00A0000022AA2320000002AA2023120282AA2CA009ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000210022200\n\t2802100000020020000000080000240400000001000001000400000000D009000000008000C0040000801000000020000000\n\t000000000000000000FFBD420800000000244222084004000004000005000000000000800000000110000C20348020020480\n\t4001000000080000800000008000000D0110000200000000000000000000000000000000FF75FA0000000002000000440000\n\t0400000000004C00000000000000000000000000000000000000100000080000802000100000000000004002400000400010\n\t00000000000000000000000000FF1EA8800000000488C888C0CAACA8EAACAA8AA90000002AA0002AA0002ABA222AA08A0022005ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0408E0000000\n\t00000000000000FF73D70A800048B200000008001400264000403410000024001808000001002414C084001C250CC1001404\n\t04081880000228420811000000004020024040004844044000000000000000000000FFB8E210004021280C80090280081081\n\t082003082210005020100000000230820A240A4123020220880B232301208202600620000A00200200280000282200200200\n\t2000000000000000000000FF84FD00000000002000000004000000020A000008040000010044000000804001000000000100\n\t0200000000880000000000000000000000000800A208002002000A8000000000000000000000FF9D7600000000000000000000dba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000220608\n\t200220200202000200202204A000820002000000006000000000000000000000FF68650A800030A200000010200000220200\n\t202400000020100000000000002000880000000040480200000000080000442C0000000000000048020000002A0001000800\n\t000000000000000000FFF16B000000000A00806800800810800800000C0000000030E000000000300A0021020220C2312000\n\t00200200216210210200080200260200A0590020022A2003002000000000000000000000FF3408100040015835801905841A\n\t11C1185415104414005060A02400008C7144416416C161040042100161440961070450040000060061060040004260062072003ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010800081108\n\t08040000C0000000000060000062060040000001001360020060420060060000000000800080400040460040281060000000\n\t00000000000000FF435D00000000000000000000000000000000000000000000000000000000000000000000060060000000\n\t00000000000000000000000000000000000006000000000000000000000000000000FFFB3500000000000100000100000120\n\t0200000000000000000000000100500400080000000700600080400400080000000000000000000000480000080600000000\n\t0800000000000000000000FFE14F000000200A00800800A00200800800200808000000208808000000200A0222028220840000bba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (602000000000\n\t0000000000FFBC2800000010580108583180100102124008488C062002E0100000000068000261060E010602600103400000\n\t40062860060000060428A220A070000807104000016000000000000000000000FFE7DD080000001A21001001801001003202\n\t000A00000004600000000080660800600610402604608008E000006006406006000404004844400800044800004228006040\n\t000000000000000000FFF102080000001831101A41200005242004402880002000600000000010694804608E844021400000\n\t006000016906146006000006042002880488404208044400006000000000000000000000FF00410000000818018018018020007ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (68000000C024\n\t0A20820000660063161EB00081209E01600E006000000000000000000000FF0036000000021800001401821801E098000040\n\t14420010440000000000228000600E04200E01700000A88031408400A00200000684600601108900210110601600E0000000\n\t00000000000000FF6843080000001800001801A4080481280020080800000960C000001000254000600EB070000100000001\n\t004C690701200200000200615600210000C400014006006000000000000000000000FF40BC000000101C08001801804802D0\n\t081001200000000060000000010860A000648E00600120000100200000E12602200200020082400508029044424E0240060800fba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (280011E95000\n\t0000E00000018000204471E01611602700600000000800280680480C0000144155ED00287052600000604600600000000000\n\t0000000000FFF9BC000000023821841E81800801000004000C00000000400000000000200400680600284600600401200800\n\t4006804814000006006006021004042407006400006000000000000000000000FFC422080000093801801801800801040000\n\t08080000000160480000001078041069060860860460149028000460260A4904001800000240000040006401007800006000\n\t000000000000000000FFC66200000002980000519181980582584008080020000063001800100E204208600640206E0268090007a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFF5B2000000401E0180180380D8405050800094080000046010208020000405006106203406406404100140084224\n\t11600600000600682600251010008628500020E000000000000000000000FF412A0000002018018018918018084811121001\n\t1000014060001000010250350A600E80200F0A702002000008C00400600600001490C2040220000082200042000060000000\n\t00000000000000FF9A8D000000001801881809800810084888001C00000041600008000002241402600680300E8A60218200\n\t0030C806A0400400000608681600220000A046007007806000000000000000000000FF38900000000018258A1001C00800000087a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060064060\n\t26000004804006806000106820026086206000000000000000000000FF493B000001C019000090018A0049A21CC0011C1010\n\t01804806208821805406086000907806206C040040C0086C2601600688001600602623634D80608648B00600E00000000000\n\t0000000000FFD9D2000000001801801801891806001C20001C00000080400000000080100408600600200608600146001060\n\t400410602608004E80600610200400203600E006006000000000000000000000FF0E5B000000265885809801821808021808\n\t022840080000600000000000140400600619200E007004210208404004607006000024C040042AB4305028080268C60060000047a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001010014004\n\t41062304C025420E0061404800D604641440C20040642600E006100506006006006020006206002006006000000000000000\n\t000000FF43950000018018000010018000010018000008000000004006000000004006004000006006006000004002006006\n\t006006000004004006004000004000004000006000000000000000000000FF5A5E000001801800001001C00001A018000008\n\t0000000048060008000040060060008060070060048040020068060060068000060068060040000040060000000060000000\n\t00000000000000FFE2E4000001841800001005802001105808045800000004400E00000000400600410040640E106806104400c7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF8A8D000001A01D000018018010010448441540801540011556510450A00556104150D1354F107124006D564D6546C061\n\t3600020020010200400000600800690008E000000000000000000000FF5CD500002180390401300196118197E80818010E04\n\t0038000E108000201087044000A0000650600404400600680690600600000604600602478400600680680000600000000000\n\t0000000000FF029A080001A2182808580180000020082C2130001000C0C4360000110841262972100324060060C000714A88\n\t601600748E030054214006026808006088006006006000000000000000000000FF2B0A00002188B8000010018000018008000027a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600E00602680\n\t0A80284006006840004006000087006000000000000000000000FFC479000001801901001E01C00801C00A002C1000002000\n\t2086480400209014305B100060410010000064C640622600608700100200788620700000400000040608E000000000000000\n\t000000FF4ED9000001801A01401001801800823844215C800D0081344E010030002CA680604048E50E0063280040160B6106\n\t40600E00000600E004006208006010802006006000000000000000000000FF7D7B000001801803001001801800C01A220098\n\t800AA00032A62A00A88BA22E6AF6880AF2AF2A669822C2AE28723E08F28E0A83AE33E00440641880628E802C06006000000000a7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000850106\n\t000000A48A0444C300C260008208002328A6280806D06806000A168128A2D14C00934C288A40502260000000000000000000\n\t00FFBE01000001821800101829B23042901084010040000020445600000008414408600010A5165172880022170002AE02E3\n\t260001040A400E025080C04080A00900006000000000000000000000FF698C00000180180000100180100180100020000000\n\t0000400600000000600400600000180600600000000600000600600600000600200200400000400600000080600000000000\n\t0000000000FF533A100001951950311801900801B00800005C000000051006000400800804004040006001080840006006000067a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t06950000000000A114000040B0400E0002128020000004022000000029082100010020480702638000852C00000802108000\n\t0000040040008040200006001140250100000000000000000000FF26D8000200400000016020154080000080000084000000\n\t0810000000020000800000100A971960118400009004000000200002000200080A0200018106001880C00000000000000000\n\t000000FFB68F010085801808081B0988102B30001000414000002000060000000080842AC2000260000000080122066500A6\n\t45E51600008018800201400008402E204028026000000000000000000000FF70D1040081A01B2C255801A09309854000224100e7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (50600600008E\n\t02654640604011610600602442E080000000000000000000FFB9F0010004800C22D00888C84C409008104008A0000140022A\n\t0000012098A20A210108A84208310010300214330302BCAA00140330300310B0090430435029028020000000000000000000\n\t00FF8B0D00000044030422821002020021A10021200000008044C8000000C40240040800C0814C208C00B24880884900B800\n\t40000818C00D20E008908608C0C20001004000000000000000000000FF9537020400820843800C00800800C0000000081800\n\t004290020000000045029004C0092800004002002013002202002202000502002082102000100202180000802000000000000017a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000008000000\n\t002200402A82A82382882880202001000002002202200002006000080000002002882082002A8000000000000000000000FF\n\tC9D2000000800A0A200A80804A00A20A00200C00000090A00200000080B002002000802042842C00022C4A80A88290A90200\n\t0902822842A02A0080282280280A002000000000000000000000FF6C0400000100120120C2452202422130003240000000C2\n\t400400000088455080500088000480480088C880B24829000010000850910D009508488AC8009440C4004000000000000000\n\t000000FF2F43000001A4190103580185180183190011380A000004600600000004640600642040608C00C4100543162140060097a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF350A\n\t0000000AA08C0AA0AA09408008A00008000000002A80000000002282A0AA82A84C8AA82A80092282A85302302282A0000300\n\t0280002A80002502882A82002A8000000000000000000000FF71150000001542A020C2C25543523142002222000000D41000\n\t000000D48B00550550CC0550510A21110A20A00D08CC0CC0000A48900C80810840D10B10D48D485500000000000000000000\n\t00FFDE8D00080000040040040060040040040045000000010010000000010000108010010008000014008810010011010810\n\t100010091014D1001011001041000151801000000000000000000000FF02740008002AA0A00A0008088088080000108000000057a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000A308308\n\t34800848C2C800804141004800000000000000000000FF3F3300000000080280080081084080080080480080000020020000\n\t0000200200200021200200240000200204240A00200200000240200200200008244200200A002000000000000000000000FF\n\tC1CE0000004AA0C80AA0AA0E00DC0E000002440000002A80000000001012A0AA82A8000A89288000A202A80080022A222A00\n\t00C04802802A81C01000882A9A002A8000000000000000000000FFC61C00080040000C120010000000020000010000000000\n\t80000000000000108000000008010400002400080B00200080080000800300502A041002004000000080000000000000000000d7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (92600000210A\n\tD001201201001009021089001009000000108000001000441009081489000201001021001000000000000000000000FF89E8\n\t420400410C20800C10C10854C04D4AC10D1490012B10020401512A948350300104310B14311144B10B10A00A012002041402\n\t103053103089042003003003083000000000000000000000FF14420000000058018218418218018218010218410000006206\n\t01000000600601620800622420440008400642600600600600004E00628440604000630604602E0060000000000000000000\n\t00FFA25400000020122020020020520220A2012882010000805004000000CAC80C0048008A004484481010C800A808A080890037a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFB3CA0008\n\t000020001000100000901020A000200810000003300000104800204802802000860C60000400800904000000100004000004\n\t08010210100526500200220400000000000000000000FFDF7804000000A00002100904C00D0040C002304000004400000000\n\t804002800000100044465060004B0004054010000000020208000104000422000006000008100000000000000000000000FF\n\tC4B500000000082084080080080082080881880A800010400202800800010208A01006248440420010648228315309340240\n\t00222A2326242000460092020102006040000100000000000000FF9CA6400C0040040000042040402040040240448008010800b7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004400C0D208\n\t62000C040614C082006000000000000000000000FF8453000000001800881000881900841108801809020028400612010000\n\t43062060004004060860000A200600722700F08E0102040040080260002A4028204002226020000080000000000000FF379C\n\t00080800980180101689981692400E86198612002005460A0690500246006500000060058000602126006116386086488006\n\t0060022940A001C40000442208E400000000000000000000FFF4E800001001380104180080180180004080D000000000000E\n\t00000000000608600804010040000000224610E00640620610000400428028435000408608412211600000000000000000000077a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000004A006\n\t00600004000602600810C0860060060864260001262260020060820060200A6026006000000000000000000000FF90A20000\n\tAA0AB8AB9000AB88989188A8000790008000DF22AE000000C22286046000020288A8800080E1862260668968060002062062\n\t52A044082000882042062AE000000000000000000000FF75EC2000000018018A200180180984080000300080002000060000\n\t0011004600600090084004080048601690E00601620600010E14600203484201404600404E806000000000000000000000FF\n\t669900000000180181100082382480100088180100000140060000004040164B60004100060060200204460065162460B60000f7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F76100080000\n\t180180980080188080200080100000008000060000008001062060000100060068004CC81611408612630E0005163068008A\n\t4008006006056114006000000000000000000000FF600F000154155833155955905881904000905800000040055600000040\n\t0556556000D08D56D16004C4642F4462AE40611600041409425055402A55651020650CD56000000000000000000000FF6960\n\t0000AA0ABAAA8440AA8CB8228A980088580080000022AE0000000CA24E08E0002C0ACEAAE022804246226A0EA07026000026\n\t05628220E0202B22AE286246AAE000000000000000000000FFC9884000000018808000008298488298008310008000042006000fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2060A00CE208\n\t0D0246044006006000000000000000000000FF9154000000001A1100180184D81080300004B8010000004006000000004006\n\t00600001084604700000502600600634680E00022604E44800608000004048C106806000000000000000000000FF2B1A0000\n\t000018C380180080182280880180180180008C400600000084C00600600010000680600088401600C3268063060000164060\n\t0280402200240600602C006000000000000000000000FF0EE30000AA0AB8000AB8AB8818848A0800881001800131C2AE0000\n\t013842AE2AE00022028E28F00822E2863B480F05F0260000860869812AD0082AA0880362042AE000000000000000000000FF008fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000160060060\n\t0200000600601010C006006446026006000006006006002440052004006006006006000000000000000000FFBBA40000000A\n\tB8058018AA8AB8AA88180996188180004042AE0000000242AE2AE0002A828E28E0000042AE00600604600600000640610A24\n\t60F021208E2062262AE000000000000000000000FF93A1000000001815005801801800841800011803800004400600000001\n\t400600600000002602610449400630E1260063560000060D640200600000200010E096006000000000000000000000FFF690\n\t0000000018A18D180180180080D0C5905849000030C00600000048400600600000000600624004400604620E34E00600032E004fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001808\n\t00080180100180810900002380000160060000002B60060060020000060060042A400620E00608640600002610642E000300\n\t004040004100006006000000000000000000FFC06D0000000AB8880A88258AB04388A0098AA0C380002162AE0000002862AE\n\t2AE0022A82AE2AE2802242AE2AE08E20E0AE0002AE2AE2AE2AA0900040CC2AC3202AE006000000000000000000FF6D9C0010\n\t00155940152955955155945823815911800014655600000000655655600255055655654401455614633641615600048E0560\n\t0651000452251054E456556006000000000000000000FF8A668000000018000049018010018019058018018000084006000000cfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (248000080860\n\t2C006001806004000000000000000000FF8349000800001841020CCB80109003414100002200000040000000000860060060\n\t0600002602620010600400600E14E0060000060060040000A4046424006010006004000000000000000000FF081F00000020\n\t1D12004801801A2400181580181080000CE00600000084680600680600000600610D00C80600632640615600000600600400\n\t0204086004006086006004000000000000000000FFFD8E0000000AB8440888118AB9100C18418AB89080002462AE00000024\n\tE2AE2AE0062A828E28E0002242AE2AE0061066060002AE2AE2AC2AA00870A48C2AE2362AE004000000000000000000FF61C5002fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04060A604680\n\t00083105284D444630E00600600620002E2060144C21100000040A4046006004000000000000000000FF9CCE800040481801\n\t8008418258120418230159010A000850400001000C020604600302010600609022F80C09600600E04641000605600E102100\n\t002104056006006006000000000000000000FFFCA6800000413BE188CD81803A081019838038810000006000040421000807\n\t106E4262048651640100544E40602610602600818642E00744200000208410E047006006000000000000000000FFC4440004\n\t00003C01089C01C010200000018C000000000460800080202060A680600E082056046044086004006046006086000036084000afa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018010008\n\t0180180B8AA009008089920004620620020000025600600600008E20650010220400E0260061060000060042060421004042\n\t04214120146024000000000000000000FF3D040000000018010008C18AB8C59000831F000184803661C600000058016E0062\n\t9E38066604600000002608620611E10600000610404600220010007C08408800E004000000000000000000FFE69900040040\n\t1C00813A01801800001841801842080008600001008000608602602600000002052008610400610E34611600000624600432\n\t20A835010404C207126004000000000000000000FFAB5D800020089800805801A41800021841801800100000700004848002006fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000412\n\t00080000B0000000000000000000FF118980000000000400000002C0020240CA02805400001101300000000C00000002402A\n\t00060061004A02003400081480000000004400001000100C8006008120000000000000000000000000FF19FA000000001801\n\t001C018CB801800101040002008020408000800008600600648D48042002000000300400C0064C6006000006244004100410\n\t0840D4004000006046000000000000000000FF277800000000180101490180190D95404B9100D00400106200400300006506\n\t04604600011040002000254410653601600E000006006204400020050404544450016006000000000000000000FF6077000000efa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AA02B0822AA\n\t2AA00010220A08208A22A0AA0002AA10222200A0002A22AA2CA2022AA22A000000000000000000FF1FEB0000000000080804\n\t0040002202800021201000000010800000004280010000400040040042800010008000000802000000000008000000100800\n\t00000020004000000000000000000000FF99070000000AA8E88AACAA8808E888080089688000000422020000000022AA2AA5\n\t02C0028828870041712205A0021026020002AA4022123462102102AA2002002AA300000000000000000000FFE71000000000\n\t0001001001800000008001000000000042400000000041000000011000E0260260000080960003204001500000000880C803001fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (ACC0800CAA8A\n\tA8AA880CAA8C288080012AA2820000000022AB2AA2222AA28A28A2002332AA2AA0020022020002AA2AA2ABAAA0000020AA2A\n\tA2022AA2AA000000000000000000FFC203000800201004200200444400040000440021000001100C00000043100500400102\n\tC0040040000248414004400000000000040490804044000040000040D5004004000000000000000000FF52A8100000355905\n\tC3595595591190595590194380005564540000001075565565175565545540004C4556556336456156001556556556554400\n\t25655655650DD56556000000000000000000FF1AD70000000AA888CAA8AA890C8A89292A88088A80005022A20000000832AA009fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020400228488\n\t228000000000000000000000FFE3DE01000000000050000000000000000000A0A00000000018018000000000000000010000\n\t840000000800000000801009500000400400440000000800400000000000000000000000000000FFC68A10000000022C5244\n\t0000000000C00003004000008000500000000B10000001088000200201000010000002083480000010000000000004005484\n\t00000121000000000000000000000000FFCA0400000020000001000000000004040000001200000000000000004000010000\n\t00000000000000088000000120000150000000000000000008000000000008000000000000000000000000FFD0228000004A005fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5611600C4840\n\t100040C400600E000010006001006006004000446006226A8E00E000000000000000000000FF075500200008100000000100\n\t10800020010052110000024A9401401002C0250A40258000E42CC00004440405000000000800400000402000422810440401\n\t4004444000000000000000000000FF64E00001280008A400488288090CA50804840800800001244200220800300280205211\n\t30224A200002202202A002000000002001002002002000282002002002000000000000000000000000FF9202000000000000\n\t00000000000000000060000A0001800000080080000800000000000810000008000B0000001080000000000000000000000000dfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200800A00800\n\t800800800800000002A20200200000208000200200A04002400000200208200200080008400020200220E000400000000006\n\t002000000000000000000000FFA76C0020000000000000002001000040000004000000000080800000048000021040000004\n\t208800004804000000000000000000000020000028800820209000004000000000000000000000FF85360100001008601008\n\t00800800A00800800E00800000A8120120000020C21030020021029020000020020820020000104020000025821CB58021A8\n\t2200A002002000000000000000000000FFCBD300015000194400590590191585180504914380000164460864800060060060003fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (140140060060\n\t00000000000000000000FF982200000000188400188180388180D0C089080500000060060060000460040062062000000000\n\t0000200200600600001000601000600800014012C044104016016000000000000000000000FF44BD00000000000000000000\n\t0000000000000000000000000000000000000000000000000600600000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF0111000000000000001000000000001000000000000000000080000000000000000000\n\t0006006800000800004004000001000000000004005000800800000000000000000000000000000000FFE27200000000080000bfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (680008020010\n\t4026026206810008402081226A005022884AC015015006006000000000000000000000FF22B8000000029880210AC5811811\n\t80F8A6888801908021601600610000E0C41068962CC00602608022240208400439001000640111602C82243000020408510E\n\t016000000000000000000000FF2128000000051800201801801809A018008028038000C16106806001016004006006114006\n\t0460005020020460061000004060084470C680201080402480400600E000000000000000000000FFF282000000001840150A\n\t01841851801C02A22A2100800060060064003061140069070040000805008420221062064080000060800065044A02004044007fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (019E78301818\n\t80828847020110600608600800708640E4160461C730650060E0060040060000000024000661940034209022AEF070461860\n\t00000000000000000000FF460E000000001800410823811B20241220E30801020100600610611000600E1160062864064260\n\t0001620E224006888208002010086806022049006D5700610600E000000000000000000000FF5F9300000000180000088180\n\t188004124020222900000C624621600080600E406406C8622014028180600E24608600040000201000680C04210050000408\n\t5026006000000000000000000000FF31610000000018421508018258C0601000020021000000E1060064003260160062060000ffa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600000\n\t0000000000000000FF3F3000000000184814E80582981400900483090980004DE44E02E20000604406600E0970A600E10409\n\t680400E004818000004000E26060348560202116006826006000000000000000000000FF7BC3000000001812209809801800\n\t013000820849000110600F00E00000640C00600E006806006000A0600481400600000000400004600C008001206046006046\n\t006100000000000000000000FF0D32000000001800001801801A00003A82802E11080002E22E416000006944006006006006\n\t807804006006806086000000004000016000000880406806006006006000000000000000000000FF02FE018000001800060900006040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80600E0E7216\n\t10408600004000400100600610040004A1B6087006806000000000000000000000FFDB06000000001E00604F01801841801F\n\t2194DC1180000064C6C0601000714600644650610720600000604680440F001800004000296034412A880800042040060060\n\t00000000000000000000FF791A000000001802120801801A0982180000844180012462060060100062060860062370070061\n\t0421608640400608000800500008620E040088091424024006006080000000000000000000FF5C2300000000190000080182\n\t9800621801E01803800000780604620820F00608600652612600E00014609430400408003000480008620440200812A4060400806040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (108180080194\n\t1A03800003640650610E00610600603000404600601414000600200000600600000600080641600000614220600600600000\n\t0000000000000000FF97BF000000001800845951901049829D41805A11A000486146816006006046486400D0400700E80080\n\t02468024208A6806800806280894825508816012046007006000000000000000000000FFFFF6000000401800000C21C01A81\n\t821C01C11801800022E01680E0800060062C600E00690640E0000061868041360A00000040000160C402380010280E126006\n\t006000000000000000000000FF37A600000000194002881D88180D80D804000107800108604E08600041605402600600602600406040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000000000\n\t000000000000FFB8980000000D1804821823801011821903841822800001600611600600608E4460000A4306046140000006\n\t01220000640600000620004C204010006002004006006000000000000000000000FF84FA0000000018008018018010010000\n\t0100180180000040060060060060060060000040060060040000060020000060060000060000000000000060000060060060\n\t00000000000000000000FF9F4C000000401800801C01C01001801001C01801A0000040068060060060060060008050060068\n\t02800006802000806806800806000004804002806000006006006000000000000000000000FFD3360000000018008098018000c06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A82A01253A0E\n\tA80666F618828E088024204000C0600A806106446000000000000000000000FF85D7000000001A01801801811A01A40801A8\n\t1800154011655700650608655708641000754600645400200600205000600600010680000000080082408612602E00600000\n\t0000000000000000FF559B0000000838408218238D122128888101301A00008260860A601720600600604000620700600010\n\t084600A00000600600000600020C045100006006006006006000000000000000000000FFE637000000003C00801801901841\n\t914811A05300804034653644634654F24610E310C0C03640E014222516D4214802712615054F09020600600080601200400600206040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (804011811100\n\t000000501600E106006046906000006000000000802D96002800026006041047400806046110006804084006006000000000\n\t000000000000FF3108000000001801801801801801C00801E0100000000044160061062A64072063280040C1200101003004\n\t002050006006080006001004004800047000044106226000000000000000000000FF3A1A000000001800801801C110010204\n\t011011010CC01160A78064068060B6886000806406826448000004080200006A2E0011070000060070004061060060560060\n\t00000000000000000000FF62B4000000001820801801821009820803821F21002028E22621E22E4EE28E62E3E82AD0AE66E100a06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF77FA040000511200909929B13A05A24A23B25A400000324C0612E0062C754600611084E000800820896B0E80A0\n\t0092688600080E0A08CCCCCD00C349149040B7116000000000000000000000FF9453000000021080805801841A01288A1100\n\t9B0D800100E10680602600700E016000486516516000247026202010206246400026010000000020806024A0400620600000\n\t0000000000000000FF435C000000001000801801801201000801001801800000680600600780600600600000580700600200\n\t4006000000006006000006000004004002004000005806006000000000000000000000FF9784000000051805801801A1180100606040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200260200000\n\t200200000200000204A000002000100802006000000000000000000000FFA2AD00000040000100210C4B0001000011021222\n\t00000005C000800100085100800040400700600102428C00840800002100002001811C024170408018090080C00000000000\n\t000000000000FF967600000012800020C00000200400006009800400003402101300218202A0800100028097296020008000\n\t0401403801007000000204A0090400020000000408208000000000000000000000FFCA2E000000041001801A4180190304E9\n\t0B00110800008A400684680630610E046088206800100000086126006000006406000006080000000080144424004806006000e06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C18218038000\n\tA962CE00E00600644600640028688C00C0000068064043001061062000060000064161002064160060068060000000000000\n\t00000000FFC6FF000000400C00C40C44C48D02C20C08D14950800104200394300290388A0C2081002002083001A0B5430420\n\t210034020810020095330434310C3003092403402000000000000000000000FFA9080200000000C02C04A00082002A020030\n\t40100000C01000880000000400100C0088130C00C800610C40804800020280000008800840E00A00A00880A0082408000000\n\t0000000000000000FFFF95000000080000800800840800900800842AC000000190020020020820028020001030000000000000106040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF56610008000AA0000AA0AA0AA0CA00804409008000002A82A82A80002A80402A82A8220A882882800000201A008800\n\t00002A00002A8080000050250220208AA82A8000000000000000000000FF3495000000000800A00A00A00A00B22A20A08A00\n\t8000003002802002802502003000802042842800C12802812020802802010802800802A3288088A892882003002000000000\n\t000000000000FF418C00000020100020120120024020129424424B00000048040040040040548050008900048048000C0508\n\tA04C00000000800004800A28880A48820804845004004000000000000000000000FFBBE3000000141841805881801801885000906040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040288000000\n\t000000000080000500100120140800000000000000000000000000FF58B80000000AA0000A00AA2AA0880AA0020800AA0001\n\t2A82A82A80002A8AA82A82A80212A82A82002202202A82A80000002A00002A82282A80203502A82A8AA8AA80000000000000\n\t00000000FFB2450000001540003543543543103202102441540001550D50550000550510550D50CD1510550880B10910A100\n\t40800800550800D50C50AB0800C00C10C08550D50000000000000000000000FF0D0800080000040040040000042440052041\n\t400000008000010000000008000000013000000010831011090010010010000090010010010014130010010000000000000000506040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C20100000048\n\t048040008040040008048AC044844C82908890800800800800000804805228800892D2880480400400400000000000000000\n\t0000FFC253000000000000000A00800800800904900800800000200200200000200200000220280200200000200200200000\n\t2002108002002002002240002002002800800000000000000000000000FFB34E0000000AA0000140AA0AA0880AA0300404AA\n\t0000AA92A82A80012A8AA82A92A80102892880002302202A82A80020022200002A81802A81000002A82A82A82A8000000000\n\t000000000000FF9D3F00080000000000000000000200A100080400000000000100000100080000000000004100020002022000d06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF7EA04008004400004A040240005840042044240000010010210012210810012010810054412C10291E9101280000000001\n\t001091101089091041001001001005004000000000000000000000FFECDE400000400020450C00D08804C42D40C02C048001\n\t0030930034411030034010830030135034530134030824C048200300140300B0931032030030030030030020000000000000\n\t00000000FF90CE00000008000008180380580188180900180108002AC0240840100061260882260860040140002060062060\n\t00006206008126206226206100006106006006006000000000000000000000FF917A0000000002002AA0002002442002114400306040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100160160000\n\t06006004000000544004004016116000000000000000000000FF11A70008000000000000040220A192014802001004A00901\n\t104000205000000800200003062860000000000803404000A808000000020002804820808840001001000000000000000000\n\t0000FF1E9B00000000000000800100102580001002000008002B001008000000004011004008000604E20040408000050030\n\t040000805009040020C240000000000000000000000000000000000000FF817F0000001A002000080088A8008B6884800806\n\t90000024C20020080020C000020200023C0040000422124020311130020002022020220024801024C010014200200000000000b06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000600600\n\t600000600600000640400604608049000022000010604600000600600E02C450284024050006006000000000000000000000\n\tFF40B10000000000000018010010018838008800A5094008620600602800E00600000600400600640000000C004001047506\n\t10000600640604040800C00C284126406000000000000000000000FF159A00080010000006182104D0438019408C00A00000\n\t27000048000840E18400008600402010022004208450614052624660000600601C0140400245440046062860000000000000\n\t00000000FF4FEB00000000000000182300988382981480000802002000A81000001060241001260062D0400040002104006400706040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFAD\n\t5D40000000004000100180000180800080182280000000000040000060060000070050070463018080032480002062260000\n\t060064460260D0006346007007006000000000000000000000FF06860000000880AA0AB8AA8460B581800418108080002002\n\tA82A82A82AE2AC2A8006984A88AC8400030906C4C00022E00E0002AE0062A40C40D0106204200AAEAAE00000000000000000\n\t0000FFA9EB20000004000000180082000188000002B81080000C8000000000006004000006034040000A000002D608400000\n\t628600000600600440680005608C084006006000000000000000000000FF1F7100000000400000100110900D8258AC80004500f06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60260002AE00\n\t6BA41870002AE0262A82AE2AE000000000000000000000FFBA9800080000000000100101184188003084C010000008000000\n\t000000600400000643400600688024040A10A000CD629700000600608508410000401608E006006000000000000000000000\n\tFF04990000001540921559551559558C415495410800005505505505505565545500065545565160045415560060000C6116\n\t000556006014410400554016556556556000000000000000000000FFC51C0000000AA0AA0AB0AB8801018221008018A28000\n\t2302A82AC2A82AE2AE2A80060052AF28E0000800220000000068260002AE00744E20C20022E3262232AF2AE000000000000000086040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00E136126000\n\t00621600000610400600600213000202200015601600000600604E0840020C4014052006006000000000000000000000FF84\n\tCC000000000002001000001801009800000801000000600600600000600400000600404600680611000202200114E0160000\n\t0600600E028002004314002006006000000000000000000000FF22790000000000900010000018018C400180102980000060\n\t06002000006006000006004806846080000002312000406B06800006006004C0452800600600080680600000000000000000\n\t0000FFD9F90000000AA0200AB8AA0AB8AB8000AA8AB08380002AE2AE2AA2A82AE2AE2A80062AC28E28F2042202AE1060000100886040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF512480\n\t0000000001001805825801825801813801800008600611400000600600000600000600600200000041000600600600000600\n\t6006042008004006046006006000000000000000000000FF248B0000000000000010880018AB8C98C5801883800028620620\n\tE0002AE0860002AE00428E28E0002002222820000060060002AE2AE30600C0102062262822AE2AE000000000000000000000\n\tFFB1A200000000000012100400D801005800009841800004600600600000602400000645402602600400008A00A000406346\n\t000006006086446028016086002006006000000000000000000000FF8CA100000000000000B0200C18018418558C2809000000486040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0002AE2AE2AE\n\t00A0082AC2AE0062AE2AE000000000000000000000FFFC7100080000000112900180980000000100900100000A200E014000\n\t0065260000063020060060040820080C200600620E00000600600E010026088144104006006000000000000000000000FFA1\n\t7D0000000000010AB0A98898AB8888238A1083000022E20E2060002AE2AE0002AE2A82AE2AE0002AA22808200632E0A60002\n\tAE2AE2AE2920202AC2AC28C2AE2AE000000000000000000000FF6B4D000000000001005955943954115091945953800040E5\n\t465400005560140005560525565560044284C24100064B614600055655644652000044641644E5565560000000000000000000c86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (070050000060\n\t040800860960860064C5003406000006006006201306C2502E20044400028E04E007006000000000000000000000FF00CE00\n\t0800000001401809821801A44845020022000015500F12600000600500080600602602600000210751080605601600000600\n\t70068800400040060AE006006000000000000000000000FF8E30000000000001801A43C05800000911811811800000204600\n\t0000806004000006006006006004000456020006506146000006006006440000006006406807006000000000000000000000\n\tFF73DC0000000000010AB8818898AB8899118838D180002023C624C0002AE2AE0002AE2AE28E28E0002A810604000600661600286040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF8DBD800000\n\t120001B01A3180D802000001A288408A004942A680684000E50608048F0064403482200C7306002406006406000896206907\n\t022440104004024406006000000000000000000000FFE7678000000004030C3049815E50048C8D0108A0904000C116000281\n\t02F88780000724224622600010C026102206006206000046106007142110006046007A06006000000000000000000000FF0B\n\tB2800800440001423C81C0180DAA888380089884214048468042C1026406800C162080161160000441070008060060062000\n\t370B7706A9A008104026007007006000000000000000000000FFCDFC000000300001C01C81801800080821C200040000881200a86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060044260900\n\t88004484544006006100000000000000000000FFC19F00000000000180182180380200C82900908100800060060060400062\n\t8408010E0060060460021060262060C640616E00800600622600A2020802942241160D6000000000000000000000FF8EB300\n\t00080000050018018A98E98828D300102D02200062360040080060042082061C61B602610201404610422E02600600040601\n\t4056002102004514094086006080000000000000000000FF63AA800000000401801089801801840401800804800008080600\n\t412100600600010602620810002088648604200628628600000611600610210843604C00445743600000000000000000000000686040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000000\n\t000030402602608080612C0044485001400000004080002040400040800C8000000000000000000000000000FFB29A800000\n\t00000800000000000982C04C02000800001000000D00000002D00000000300060062003100001081000500100000000A0000\n\t0283004A0030000000000000000000000000000000FF4A050000000000018018098B18218A080500000A0400080226004090\n\t00600441040608602000002080600604640414620E00000608C0060004004A8024004226306000000000000000000000FFF0\n\tBD00000800000180192180390A0108D18101200140004006000000006304080016026308080000006526404116006006008000e86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9D0000000001\n\t128028AA8AA82292280888088080002222AA4220002AA08A0002AA00A2AA2AA10000250204A2A230A0A20002AA0A22AA00A2\n\tA02023223022AAAAA000000000000000000000FF2BC010800000000000040020000008000005202800000000004880010000\n\t00000800020000004281000100080000100208000800800001000500088000000000000000000000000000000000FF3D5800\n\t00000000608A08AA8AA8328808848928A2800020A2AA3120002AA4000002AA04228C2880001222022220120026120002AA40\n\t22AE08600011A2002002AE2AE000000000000000000000FFC00400000000010400C00000008180000101000000000440000000186040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000080002100\n\t0000000000000000000000000000000000FFB5908800000000AA8AA8AACAA822810CAA88088880018122ABA020002AA2AA00\n\t12AA30228A28A0002ABA23A222AA002202001AAA2AA2AA2AA20104A2AA2AA2AA2AA000000000000000000000FFE0E2800800\n\t0000000D0401401080011140043035000008C004000001004024001004480004004203450050500000040000000805008004\n\tB24002020014055004804000000000000000000000FFA9F0800000000155955D559559558231559011030000345556046001\n\t55655600055741655455400154E44E456556436146000556557557554020406556557D57556000000000000000000000FFF700986040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000080\n\t8000800000000800000000008000000000000000001000008002400000280A0000000000000000000000FFB23E0000000000\n\t0000000004000040011000420000000010008002000000000000000000000000000000010000004000000001000000008010\n\t000C8040400400400000000000000000000000FFA9DC00800000000000020040008008840002402400003410000D00000000\n\t000010010300200200010000001080000500100000000008000001004A0000000800800000000000000000000000FFD4E400\n\t000000000000000000001004400000800000000080000000008000000000001000000003000001080000005001400000000000586040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (015011004194\n\t18B194580184194594590D8C4010648651420651010600608001601400480109600600654000605000000640600749600000\n\tC22610400E086150000000000000000000FF9265028000000001611001008004000611030041080008C0052440000C800420\n\t400800010C084020000018C0C00010000000002014000000428010C005004040040000000000000000000000FFC0F60500D0\n\t1104208C0950B42804840944CC488482400823022B280233008200200080A00A00200101200A2024C08820500000024A2002\n\t412001002002902002002128000000000000000000FFF5B1000000000200008000000000000010010228100000180000080000d86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800800000\n\t004004004000000000000000000000FF4DCC000000000001800800800A00A00B000028110000002802002802000002002000\n\t00200400000010200200000008200000000200200200210000400020E002002000000000000000000000FFF5710280000000\n\t0000100005020008020824004010404000000008204880004000080000000850200000100140000000000008000400000000\n\t00008000000000000000000000000000000000FFE7AF000000000400800800A00800880800A0082800203120624026222000\n\t0200200100201200200108200280200048200000014202201A00240104204200A402402000000000000000000000FF38E20500386040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (168161002040\n\t804000001468B550640100401000000601620540F029520104002C04504000000000000000000000FF3FEB02000000000180\n\t18018010018010C1005028000004600602000000002600620000620800000000E00400608808600000000000400400600200\n\t0044120000000000000000000000000000FF46BF000000000000000000000001800000000000000000000000000000000000\n\t0000000006006000000000000000000000000000000000000000000000000000000000000000000000000000FF0C28000000\n\t000400000000001001801000401000000000000000000000000000000080000600600080000100000000000000080000000000b86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000481C01801\n\t855005881101445030020004600600000400140600E40000610020000012604E08640000200000000000640400E248106484\n\t023406006080000000000000000000FFE3BD00000000002B8898C5801881813C4BC0904110400D68060AE04204102E806400\n\t082A0E42640040E35000608080490000000610C006A06800300004082114284000000000000000000000FF196B0000000000\n\t11811901801A00005831810201042000E00E8068060000060060803068060460000064842068080868080000040040060064\n\t00038424000000000100000000000000000000FFE7A6000000000543C81801C4D8842818030210000040117016108006000400786040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08D060060000\n\t00000000000000000000000000FFD1CA080000000401C01845807889803C4B421041904104604E1002C60083060860080022\n\t8602640040411200602000010000010602E00601E848016016903004784000000000000000000000FFAC7300000000000180\n\t1801EA1008001013040401800010E09600050E0080060060100020265060020050428060002A200000000408600E08700080\n\t620700208F006000000000000000000000FFE66E000000000001C01881B4120000160140020080010861260C001400008600\n\t60000070411080000068060060004C2000000082006054106140A0E40C083004004000000000000000000000FF9AE202000000f86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600050200E08\n\t6000256002014280004000000487806024006C08006006442104004000000000000000000000FFDAD50000000000E3843801\n\t831020121031811020000086680680600400012618600008700600640002E0D6A4C010064620440206166014047041806026\n\t200206006000000000000000000000FF9D1D000000000105801803881043E011250010420000006007001006000006006000\n\t012806806004086B03405820004020000006006004006004106046000404804000000000000000000000FF96050800000002\n\t0180188180190020D801001400000000600602000402040610620000648602E004006006804820004000000000054024006100046040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (09841A8590B8\n\tA0621805911115008129780780680C0C018E00600000208602E024104462064040224A0048030400F0968260C10060860023\n\t0F006000000000000000000000FF0541000008000001801809801E01811955814431100000E0860070040400060570080038\n\t2730600484400A005A1180613000005620640711641048E004010104084000000000000000000000FF3F3A00000000000180\n\t180180980448BD11C050010000006006026804000006006800A1200F10720020400A004488006000020004086846846A0810\n\t6004020001000000000000000000000000FF17B4000000040001E03801821801835A01883488000000E0060260060200460000846040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400400400480\n\t6000000000000000000000FFF28700000000000180000B801800209A01800001010041602620600E00600800E80620614612\n\t680400405200200642211600005600400684C0A8206106006406006000000000000000000000FF416D000000010009800501\n\tD2D921821B4DC12651100004710E01700602600004680E004406A06824024800040416002046100007016D0610700400E006\n\t48E09688E000000000000000000000FF99DD000010000001801803CA1807801801E01001000012602E26E604100106006000\n\tA0220601680081C00280400000440000040740600600642410600628200400C000000000000000000000FFFBF5000000048000446040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A42262160A0\n\t0B611254E04623289604011602684E046100006006006006006000000000000000000000FF97E00000000000098040838050\n\t01800029800003130004E00640604604E00001621640E00E08640C00420000620600202648800608E00620600048E1060060\n\t06006000000000000000000000FF849100000000000180000180180000180100000100000060060060060060000060060060\n\t06006000004002000006002006000006004006004000004004004004006000000000000000000000FF4F3C00000000000180\n\t000180180180180100000100000060068060060060000060060070068060040048000000060030060000060068060060008000c46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2001A0180198\n\t200080A2E29A8002F0880AE0A86AE6B946E28EAEE2262BE7A80AC2880BE226A2A2BE2A900E0AE0A6027180A0608605614600\n\t6000000000000000000000FF746D000000000221800001F010002041441120900440556500C56D1008600008E0A6C1755740\n\t600C00604AC06106C0092600100420015420100100400600400C006020000000000000000000FFEF62000000080001800003\n\t983049808024090008002008606000650000700000602680600604600600480080600680040600000600610680664600C006\n\t004004006000000000000000000000FFCDDB000000100201C80031841208294301B040B1004048688E95701650654952614600246040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004004006000\n\t000000000000000000FF45B80000000000119001518410418003148002000001406801406400006000506006027011000000\n\t80600240600680002E000106A00816E05040906004026006006000000000000000000000FF74DC600000000001800001B014\n\t00400022D000A882004171000060000862000AE0868055280002880060400060860028060000070030070070000060040060\n\t2E006000000000000000000000FF283500000000004180000180180008430080C00090400A620024E31020680820604640E8\n\t0640E00000480A40E00640110600000600494E00408080600600E086006040000000000000000000FF3FA7000000000001C000a46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (108000006020\n\t0624E26600042600008440000410002000043404400400E000000000000000000000FF6C240000000004A18221158352222D\n\t5C08050230000094E0008C6C31006020006086806000020808A22A068AE846820CAE000A06A26886C0E8B085080488CC240A\n\tE000000000000000000000FF86AA000000000001800001801E00201903604101000020623621600600620828600E4A650750\n\t608011200A206286480006000114014205080200100424424084406000000000000000000000FFBA85000000000001800001\n\t801801801A01000001000080600680600600600000600600600680600080000000600600200600180400600400200000000400646040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800002810940\n\t800040000010280206244200200000200600200000401002600A01210200220200060210200200200044600020A023006000\n\t000000000000000000FFD86600000000000000000000600582641802200000010810006003000008010000800700060260C0\n\t0004040A40802A4000000100008280088600000200520080240000000000000000000000FF075F0000000000000002C26400\n\t4194008400C08000012001311910080000418010081000862865090080004000000400000000180400100401501000000000\n\t00810000000000000000000000FFA640000800000121800009839021889800000008000000E800006020406200086806284C00e46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2082C0000000\n\t00000000000000FF1B95000000000001A0004185380590580B102051800000600C24E0140060000060061068849045000042\n\t06A4604600400600028E2C601604620010C406006016036000000000000000000000FFB197000000000500800680900C20C2\n\t8CA08105040000082282082343402020C0200305340B00304830302301308324350A0010030030033030C92230334A344200\n\t2000000000000000000000FFE1110000000002014203003002002000023103350000020608808810000028600000800B0490\n\t0800980A41000000C04198000800A20800E008888B8840880E508A0000000000000000000000FFC23800000000008080200000146040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (101100100000\n\t1001011000001009001001001049001001000041000000000000000000000000FF8ED00008000000AA2AA0AA10002A080088\n\t0AA00400002A8AA82000880002A82A8000420288A880603082202A00002200000000800402002A8060220200000A00A00000\n\t000000000000000000FF40D8000000000400800200A84A00A04C00C002808000802003032842002001002002802042042A00\n\t882892812802882802000C12C02842802800802892812112102000000000000000000000FF2E880000000004010000012312\n\t802302232002530000804805104A04004800004004A900040048008448000000008140000008408C8888800C0888C824D20800946040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100040020001\n\t0000010008000281000008000000000310400002030300080000004000000000804000880002001000A02212012100000000\n\t00000000000000FF3E970000000000AA4AA0AA0AA0A20AA0AA03208A00002A8AA8220020000AA82A80000102A82A80002A80\n\tC02A80002A00000002802A82A82A81002A82A82A90880B0000000000000000000000FFF3C60000000003545543542502442D\n\t03483542280000550550D00A28000550D50000880510D50800400D40D50800928800000C50910C40D50810C50C1089013014\n\t0000000000000000000000FF220800080000000000000040041040040050040000000000011015080008010000015418010000546040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000000000\n\t0000000000FF59960000000000010012002012802012012212440000804005044800000005004000C0084484480080480000\n\t0800908800000A0480480080082088880080002482C000000000000000000000FFD496000000000000A00800800808800800\n\t892810800000280200A15200000200200014A00200220800210200200200200200012A002002002008002002002912102000\n\t000000000000000000FFB7780008000000AA0AA4AA0AA0220AA0AA0000C000012A82A8290200000AA82A8000000288288400\n\t2A86382A80022200020000402A82A82A80802202A82A8600600000000000000000000000FF9C63000000000000000000004100d46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002002203222\n\t003022200122022022002400002002012012002100400400000000000000FF0C0800000000040042040058418050A4005014\n\t02000102904100108100128122120000128524500100C0010080010000000010010D02112812B91610090010050040000000\n\t00000000000000FF7326400000000420C20C10C00810C2CC20C00C14800112B5134035230011030430402030D350300104A0\n\t03212093002022501103482103103021003013003003002000000000000000000000FFDE1600000000800180180380900180\n\t1109029081810000600415400622020628630008620600E0A02040960062262262060202460062462463002062060060260000346040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (485000100190\n\tA000600001008000000E00608800200400444000204614608613222E00000620E00C1044C820002003012600600000000000\n\t0000000000FF994600080000000004400008000180808400000C010012040000002021041000009000001620644000022002\n\t05400402004480000100480080B0480448040040010010000000000000000000FFA867400000000040000009002011840048\n\t05011100800005202C84204400001000C010002610E14042010C000088444400140500210108020000504404004040000000\n\t000000000000000000FF8263000000008011801802808840980880880000840008214A00200204000240200020254802001000b46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFD0FC00000000000180180180091184283300110100000061160061040000060060000D200604600000224E24E006\n\t30802600024644613400444005402401402E006000000000000000000000FF59D00000000000018018018208820208050250\n\tA9020020E0AE0860442000A620600002208220201000200600700600110621008602600400C00009601000000E0060802002\n\t00000000000000FFD3E10000000000018C18019208C20329280238A5082034E4080880800504A60060000264500180000024\n\t0608644608A0AE04000622604608600000C404184086076070000000000000000000FF92240008000000098858010008019000746040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0648E0060212\n\t2600030652E106546420B2C225204AAEAAE000000000000000000000FF0097000000000001A01801000800002842C0103200\n\t0000603000000000000600600000600202200008E0A680600600002600000642E00600600000600000600600600000000000\n\t0000000000FFD1620000000000AB8018AB0A402208809080115800002AE2002A82022A80062AE2A8216A88AC800086E14604\n\t619E81010E000016006456016008204314214A06AAE000000000000000000000FF41D5000000000401801801012001800000\n\tA01224000000604000004A00000600600000604400484048408610622604048600008E0962062D680010008E0A610600600000f46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80188380002A\n\tE2062AE2062A80062AE2A82AE28A28B0182262062240472A88260002AE0062AE0070002202AE2AE2AE2AE000000000000000\n\t000000FFACD6000800000201C01801040901824804000C03800000600800001000000600600040700600604010E016006C46\n\t50000E0000260060060060080040040C4006006000000000000000000000FF0CFC000000000155C019559549441109100005\n\t018000556500550556550006556550557552D12004C4640F55651655050E000556106554534130550550550D56D560000000\n\t00000000000000FF732F0000000000AB8018AB89082B8888C080100000002AE2C02A83402A80062AF2A81262AEA8F002A062000c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF47B400000000000180188385588990984B00812180000060B61360220000060060000AE0060064403260062D65460002\n\tCE000006006126106208004484404006006000000000000000000000FF0A2000000000040180180180000004004100022180\n\t0000603600612E00000600680000604202280000E04E00F55600049600000600E00600E15090600680000600600000000000\n\t0000000000FF5FC6000000000001801801801909801815801011800000610600600400000600600000680680600088608610\n\t6006000006000006526006526000014004004806806000000000000000000000FF7BFE0000000004ABA018AB0AA8320CA881008c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (051652205600\n\t055655640645642008E406412556556000000000000000000000FF03E1000000000000001801805801845805900801000000\n\t600614602400000600600001000400400000600600002600000600000600600400645011600E082006006000000000000000\n\t000000FF68590008000000AB8AB92188183380188182500180002AE2062062C80002AE2AE00000428E28E0000062AE006046\n\t2000060002AE2AE00600612020403C1242AE2AE000000000000000000000FF11DC0000000000018018118000000240018848\n\t0D800000600600600600000600600020602202210400E00600601612800600000600640E4560800AE0060960060060000000004c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8900002AE25C\n\t22C0860002AE2AE0001E028C28C0102262AE2A80062A85060002AE2AE2AC2AE00064606E0622AE2AE0000000000000000000\n\t00FFD1FF000000000000001805881080041801800829000000608E0161160000060060000A800000000008E00642000600A2\n\t8600000600612E106010226124022006004000000000000000000000FFB6880000000000AA0AB8AB8218A38098C180A8AB00\n\t002AE2862163160002AE2AE0002002AC2AC2802AE2AE2A828E2A802E0002AE2AE2AC2AE08000630420A2AE2AC00000000000\n\t0000000000FF16970010000001541558318538441159538B090500005564465462060005565560002005505505444265561100cc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t7785000000000480001809A0180804400000380000010264A124040610008700602020208408C0040060052002A700200E00\n\t0086206000044300084006000006004000000000000000000000FFE42B00080000040040180180908180202000D840000000\n\t604008022C00080700600040000404440000600600054600028E0000060060048064B4004486401007004000000000000000\n\t000000FFA697000000000000001C019458005500082C18050000806904004006000006006000012044004108116004000016\n\t0020460000060060000060000AE007092006006000000000000000000000FF1C6C0000000000AA0AB8AB91183B9000920418002c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00E406028106\n\t006208456408014034010316006148110000000000000000FFC27680000000000000180188182200000000180080400164C0\n\t4C040600009600E40000201400405010E28C0000870040060000160961444B60504145044020070060000000000000000000\n\t00FFE37A800000084000001E0188100408008000980880201160020020050000060078000002040040280070860000060060\n\t0608000E016026106050014286200007006000000000000000000000FF3087800000082480401C09C01849C220E020980080\n\t01086802102004090816856418000214044000116416040026004006000006106104C160024040068028070060000000000000ac6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400060A05002\n\t8440043640E20000E02C00400000420424010E05611650800608604410E008000204520216434220000000000000000000FF\n\t073B0008200000000218018010081A595981180900800066A606621E20020610E0000060244044000060041000664260062C\n\t00060064060841000820040A00062A4010000000000000000000FF66E1000000000020001801821083903803805811000004\n\tE00600E0220100860460C040418415408800608664040620409E1001064860A400458010220420200600C200000000000000\n\t000000FF30C800000000020000180D8098418000A00358240A41086011300087000036B0620000A01440C200006A048C0096006c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFF484\n\t0000000000000000000010018000000840920000000000100040000000000000004004004000534006000010526040000000\n\t00000C240202000000204000000000000000000000000000FF18108000000000000000000CA09184000204800000000000B0\n\t0302800000000000002C80060064A00004880005408082880000000002801000280900301300001280000000000000000000\n\t00FF473A00000000000000181182104B80180380102200001160100080200000860061000061040140900071040000070064\n\t0600008600610844420210804C008086104080088000000000000000FFCC050000400000200218058099000218018438081500ec6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (56000556D564\n\t06556048444556555556556000000000000000000000FF080F0000000004000AA8AA88893288C8888349480000AAA22A32A1\n\t220002AA2AA0004AA2AA2AA4A000220200028A48202A0012AA2AA31213204B28220A02A2AA292000000000000000000000FF\n\t5FA102000000000020000000000000000002000800000000000200A800000100000000000000040000080000000080828000\n\t0000000110000200011001000800800000000000000000000000FF3C210000000000000AB8AA80482288A8AC90082100002A\n\tA20220200A0002AA2AA0000022AA2AA0021031220000020125020002AA2AA02200A0002263C04062AE242000000000000000001c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (011000001000\n\t0001000000880000200000000000000010000040000001000008000240008001000000000000000000000000000000FFF52A\n\t9000000000004AACAA8AA82A8C888888888080002AA26223A4220002AA2AA0003220AA4AA0002AB2AA0000422A20020012AB\n\t2AB0622AA0023A22AB2AA2AA2AA000000000000000000000FF83A80000000004004014010400000200400004050000804104\n\t00441000100500400000000000000043084800002104000000100500402040040104D0051050050000000000000000000000\n\t00FFCFB3000000000000155B55D558CD915935913B43800155650C484006001D575560014565561561095565560005175460009c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF55530000\n\t0000000000000000000000000008008400000000080001000000000000000000000000000108000000000000000008204000\n\t00000000000008000800088000000000000000000000FFBB050000000000000001000000000000080220000000800C109180\n\t00000020040000001200000000000400040040000840000000000400500010420400C00020400000000000000000000000FF\n\t4052120000000000200000000000044044000024000000000008030000100000000000820000048900080000054081028800\n\t0800000A80000008000000000800000000000000000000000000FF11F0000000000000000400200100000000024010000080005c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006208200216\n\t2820D82D82402182402000000000000000000000FF99CC004010105800145A01001041C01003C0110B800091601600611600\n\t042600600602120604600028E00600600600700600002620602680600005601600682608E000000000000000000000FF974F\n\t0020800010220000010010002010101650A90001025001014000400104004004000041410040000804084000080084000800\n\t004001000080800801000000000000000000000000000000FFCDB20020101028002A2800800820800804A00810800008A002\n\t00280A200482002002040822C2A02028200200200200200200000200204280280000A002002802002000000000000000000000dc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800004800000\n\t000000000804000000004800000000000000000000000001001000804004005000004000000000000000000000FF5C930000\n\t00000000000900800800800800800800A0004420021428020008020220020000028020000822020220020020220000020020\n\t02402128002002002002002000000000000000000000FF1FA20020800000220000100040440400000400C820010000008008\n\t00800800000000000000000000000000500000000100000000100200000800800000000000000000000000000000000000FF\n\t570E000000000800200808802C3A820800C00800800020341203280200006200200200000300200009B00220205A10200200003c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (174300000030\n\t1000001800C00900000801924051800002684600600600000680600E01000690400094612644600700610E00080600E02600\n\t648A92C104C05404004000000000000000000000FFDAE6000000001000001000800801800821000101800801610E00601400\n\t0006006006100016004000006206006006006006000004006088400002000000030014010000000000000000000000FF4299\n\t0000000000000000000000018000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF4079000000000000000200000201800001200000000000080000bc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02600A007410\n\t404504024804004000000000000000000000FF654E00000010180000080040010180020108092180000360B6006006000006\n\t00600E0800061060001424C6026006006096000006006110000088108000040004020000000000000000000000FF06460000\n\t0010110014184085084984083995111580001164060061D600040680602600800E02610000011630600400481610080400E1\n\t26206240804084B0C20E004000000000000000000000FF0A46000000001000001800800A10000811A2300980080060060061\n\t0E00000600604600000604600000200600600601E80600000400600400400002600600606604E000000000000000000000FF007c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060C00160060\n\t46000006006004006006106246106006200005C06000080224000000000004800000000000000000000000FFA75300000010\n\t18001418C0840A09882A01D129758100B2608480690600054E6063260008060261400001160062244E418720000621E10608\n\t618048440C00C807004000000000000000000000FF9641000000001900000880E10848420953402801800145610604E05401\n\t000600640F8003060A600000000602E00400601610000602600C0008101070960B7006006000000000000000000000FFE6F6\n\t0000002018000018000022800000A500080180800060170370060A814600609600148490602000200702E006A0400700000600fc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001800\n\t001801801801801809C81E01800010680681600E00000600600640000E00622104602600600408C006001046006006026220\n\t004004004004044020000000000000000000FFF1A20000004018000A1200A00800200805081851800088641602E006000006\n\t60600600002600A19C13618660600640400E0001060060870261181005E0500004020000000000000000000000FFF6770000\n\t00101800141880804803A00801450001800002F00604600400000E00600600004600E00120600688620400609620000E0465\n\t0E20600002C80C004004004000000000000000000000FF78A0000000001800001000804B00104801820001800000620E006000026040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060069800048\n\t0400C006004000000000000000000000FF650B0000000018000A1520000228689015819801800009E88A0070860000160060\n\t060000268060040070661074049B418600001EA06014604045146416506006006040000000000000000000FFE76D10000000\n\t1900000905C21903800A35C051058841006026B0E00E04804600F50604020C2B621100608E11644400580601100602600788\n\t6A40A94004084006204000000000000000000000FF48C00000001018000000000022040000018210318000046C1600700E00\n\t000600680620000C0062243170060068042040062000C6026204004480016806006006006000000000000000000000FF460600826040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000600680600\n\t0002000800800806006004806000000006006006806000804804004804006000000000000000000000FF88BA080000001080\n\t040A81801902201A00801801800000604600411600004600620600084280020400002610604408608000000D024804506044\n\t016006006006206000000000000000000000FFD5F8000000001800100A45841829889A4584590588208AE106504007048106\n\t016816040A0A44880800088E016404006001008006406806006200D04804094804006000000000000000000000FFD7DA0000\n\t00001800001801801A01801A11C31C01800002601207600500008600610E000006106001006006006004044007000006006000426040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00001808000C\n\t09A20828200212D40A098000006816A060362001060265264201068820840110464A6006007110008126015006A060000000\n\t00016000006000000000000000000000FFC05300000000180400084180580180000180480582001060060060860300062060\n\t16010012050400000016006104006400020416406416026140004104004004006000000000000000000000FF9D7500000000\n\t1000000801000000001800001801800000600600600600000600600600000200000400000600600400600000000400600400\n\t6000006006000006006000000000000000000000FF1E16000000401800000801800401801801401C0180010068060060060000c26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (604100600601\n\t6006006000000000000000000000FF6E13400000001820000801C0080181040E82109182000060812520E826050E7662AE2A\n\t004A4802800090262CE2840172C800812602EBEF027001004084014044006000000000000000000000FFEDA1000000001000\n\t001801800A00240000A143459540556CD000651040005700E306000516802434002355086536026100000228200A1000502D\n\t00000008000800E000000000000000000000FF4ABE200000001040041829000A018000008981038000096560016600008076\n\t006006100E0200000000278C01645C006000000A06046146006000004004004004006000000000000000000000FF0257000000226040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006000002\n\t004000000803806804006000001006006006004000004004004004006000000000000000000000FFFD2F0000000010140408\n\t01844051800000004033800001641401A00000010600600601092685200000220604684602E0000403B8600AA04069490000\n\t00096008006000000000000000000000FF37D8000000001800000A01800800600000A00001E800007224003C5022020622E0\n\t060010070024080000060A640600602000100600600200700000400400502400E000000000000000000000FF3F8C00000000\n\t1000000A01000000028004013109854154E0900220800000D6886306000D0A2000400021568060B400608000000100000C0000a26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180003580510\n\t8821901890804081800000685000688000000622624600012440600014600220640600600000043000028024440024002832\n\t0000026000000000000000000000FF20F70400002098002C0B2DA48A2C221B308C2281800080600080625021142700744600\n\t0AA48D68008D280AC8E826B16000080CB6806B16A36A28A14804A04924006000000000000000000000FF8E9F000000003800\n\t00980120080000980281184380008B6A1223608600009622600620801640600040282200650E026020001004824024004080\n\t0C602E0C0A0E0D6000000000000000000000FF8302000000001800000A01200801801800A01801800000600200600600000600626040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (900C50810810\n\t804000000000000000000000FFD88A020000008800080808800800800802800000800000260200200200840200200200000A\n\t05200040A40300204208210000004A04214A00A008022002002002002000000000000000000000FF2FFB0400000000000010\n\t0300000384010400A42200010A00000600001008600008000482403840002300081883A00210000800000200100302300840\n\t0400402C008000000000000000000000FF22EA0000000000000001B006404182800866040000010110003112280102000004\n\t00200000020000080020000000040020000000000000000100008000480380980000000000000000000000FFFE520000000000e26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04000A008109\n\t00D0C000804950880800000C40800CA0A00A0080094890891084C000000000000000000000FFEECC04000000180000190388\n\t10018A188D001801800000E0A408E48401004600640602000642E000024A060860C600600000040600608E40600010600600\n\t6016006000000000000000000000FFF9ED00000050080040AC08C22C24C00C208CC820800028220B422002101C0340382200\n\t10A310300150B0020034030C210000115302322303348904342B313083082000000000000000000000FF8646000000302000\n\t20820020020C2002603900400000508908C08D00200088C00020000880808800805001000808B08000000B80800C20C0088000126040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000404400500\n\t4A00002000000001000130001000000801000000001001009001001000001001000000001001001051351101111001109001\n\t010000000000000000000000FF131F00080008C0000840C00080AA0200480800AA00002A84202A80200002A82A82A80000B8\n\t200202400AA82A80000002A80000002A80000000A0200200010200680000000000000000000000FF3D6E000000000800204A\n\t10A02A00B00A20810A008001002D02803082800003002002800802922800822002802A02A4A80080088A8028129528008D28\n\t02C42842800000000000000000000000FF1F1F0000004420002482242C1200214305445201000080480D000A14000005004000926040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400002A8B800\n\t00000000000000000000FF78960008000000000000840B409002C49021040000000000408000880008000000000004800002\n\t820A00010000880090000004800000A0148142400220000040080000000000000000000000FF2F840000000AA0000820A010\n\t202A00A0AA2800AA00002A8200AA82A80002A82A82A80002A80A00002082A82A82A82A82A80002A82A848000000042008822\n\t02A8420000000000000000000000FFAF790000001500002C82102002443000021441540000D50890550A20800550D5055080\n\t0820D30800811550550A40B40550800848D50C08C00C008C8910CC0D08848000000000000000000000FFD84300080000000000526040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00641600000\n\t6006046026206406206006016006086000004006026086006000000000000000000000FFD9870000000000000842C0208210\n\t3100010512010001004140805004004005004000000800880900928804804800800004004800800810820890804948908804\n\t048000000000000000000000FFC3370000000000000288089448808048008048008000002802002002000802002000002002\n\t04200000200200200200200200200200250208A2000D2002442002002000000000000000000000FF23510000000AA0000500\n\t120500220200AA2D44AA00002A92082A82A80012A82A82A80002A86087003402A92A82A82AA2A80002A82A8020200410200600d26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (208008048208\n\t040A0000800000200220A02218601240248028240220A00001A00209A60340200200200240200200200000A0520020420020\n\t10000000040000000000FF22354008004000000824004200004804004004A400010216A10010010010090010004006A00210\n\t51001181110000001081201061448080001681014080111001000000000000000000000000FF9474400000420010002C00C0\n\t0840D00C20C84D0080015030234132431030131030001020C20C300101300320240200308310340300249200B14100208200\n\t3003002000000000000000000000FF9F760000000820000C1821845801821881821841804002C0860040060040060064A00200326040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400620418004\n\t0000000000000000FFA145000000040000001001009001881800001003802010008E40002600010E00630000620400600202\n\t610600610640E206006004416102046222000004004006084000000000000000000000FF2446000800000000000100010011\n\t8B00B000011200C04281100005500105000281000000002104300C04002A0000000008000000000400008228208280120280\n\t080000040000000000000000FF4657000000040008021001003021800120002004002029000000020000400010024004C004\n\t1040280000004400444002000802002204100900200000000A8100000000000000000000000000FFF1C70000000C2000000800b26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (116800036046\n\t0063120860060060360C6112036800056004504046004000000000000000000000FF27D40000000C20000010858499118019\n\t25801801800000615604E15600000600600000405640648028401600604025600600610441444450430008012E02E0960060\n\t00000000000000000000FF31490000000000000010098238A800B94180380180002460060064060000063060400060060262\n\t0050E02634E20300601600600400620A0160004003260262A6406008000000020000000000FFC15900080000000000110982\n\t38A404381400317181000900063E01161104060D60200060064360502064A600608600E20600600600E0EE0260100100141000726040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D8AB8C803308\n\t10AB80002A822628822E0002AE2AE2A800028E28A4008142462AE0A8C0E0060064860841242044004C60162060CF2AE00000\n\t0000000000000000FFB8A74000000000000A08010A3000042003003001800000000600800600000600600000020608648004\n\t60860060000A6006006B0648C080004001446236086047806000000000000000000000FF9F2F0000000000000AB821041022\n\t08C1080E10AB80002A83062003060002AE2AE2A8002244066100D042962AE002006006006216406416106120A06644104206\n\t2AC000000000000000000000FF820020000000800000180908300182200000B001800000000610000600000600600000210600f26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004000000000\n\t000000000000FFBF290000000AA0000810AB0910320880408818AB80002AE3062262060042AE2AE2A800207C2A7004084226\n\t2AE2AE0060060060860AE4A22AF000206304054206AAC000000000000000000000FFCDC40008000100000000551010018000\n\t0000B001800000000C0400070040060060000000060068000461060064060C600600604603400405402001408402C4060040\n\t00000000000000000000FFA4F3000000154000014155801944110090131155800055044E4C04CE0005565565500020864560\n\t04C8E45655655621600600703402603255650810C004404316554000000000000000000000FFA15B0000000A40000AA90180000a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040040060060\n\t1601600600608600C1081040200160C6006006006000000000000000000000FF73E800000000000004004590D81180582583\n\t380180001360841260060000060060001482B60060000AC0060064C654600600602E4C424424C0100240160AE00604E00000\n\t0000000000000000FF367C000000000000004001831888003821805801800000609600610E800006006000000006006C8400\n\t408600600654E00600600600421400409008412E02E096006000000000000000000000FFDF98000000000000031001805801\n\t8201148518018000006046116046004006006000000506016000C4C016006006806006006256404004004400056004504046008a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (111954151955\n\t80004461064465565505565560001100005560040C455255648E21655055005640650650401040E44E4C655644E000000000\n\t000000000000FF825680000000000000A001801909801800001801800000601610600600000600600008000008E000000000\n\t006116406000000006006006006020006006006006006000000000000000000000FF661400000000000008A0819219238898\n\t818818AB80002164202162AE2A82AE2AE0002400442AE0026042AE2AE0060062AE2AE6060040140040022863062162AE2860\n\t00000000000000000000FF9CC9000000000000000011801880021811801801800000621000E0060000060060000000060060004a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF63F30000000000000C00AB8AA0238880840AB8AB80002463462062AE0002AE2AE0002202A80060002AC2AE2AE2\n\t061462A82A82AE2AE4162AE0003262AE2AC2AE2AE000000000000000000000FFEFB200080000000000400185180004380000\n\t5801800008603608600600000600600020029000600600C0020060260A60000000860AE02602E0220C400400600608600000\n\t0000000000000000FF06030000000000000800AB8AB8238CB8B00AB8AB800030E20622E2AE2C82AE2AE0002282A82260002A\n\tC2A82AE24600E2A82A82AE2AE0A62AE00822C2AC2AE2AE2AE000000000000000000000FF32140000000000001500D380384C00ca6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (50015A621010\n\t680000018C85645E54614150700F006113006000000000000000000000FFC7F8000000000082402481802004000080001449\n\t82400C004080008620100000702000800B04600400482F046006006000000002406004000001815005805006806000000000\n\t000000000000FF459F000800000000020001000111804254001001800111002015000628000000600000880242E002804006\n\t006086547000000007006506006022005004004006006000000000000000000000FF4D4C00000000000000A0010000000200\n\t00001C0180000261160070060310070070000800001060040040068060360160000000060060360040101160060040060060002a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080052218801\n\t020100030006000810006200000002A0600008C3070965220060481401001060062003084865260442924460000000000000\n\t00000000FF4AB58200000000804000010140000000C000102180204080201402060004010068080500000261000941060060\n\t020860100000242064060520A128710700508B006000000000000000000000FF395582000000000000000100800004004004\n\t1001800101000002020600021102600000044241608010408200620000600800005000600600C00800609620600300600000\n\t0000000000000000FFF54D8008000000020020818000038202000015018001420001500806301009127010040B202060608100aa6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFB2480000000001000800018018D401184000502195404401000004060000A010640000001611400000425622608600\n\t6040120006006096016240004004024104006000000000000000000000FF98BF00000000000006000180188A1C7830001801\n\t82202060061860060000B600600000000E40440001402E12604200E01000000600608C404000004004006004006000000000\n\t000000000000FF66870000000000000800218A9821809880041919848010E20640630610000618606800011409C220004056\n\t60601800600000000605E06450E030014004686004006000000000000000000000FF7EE58000000001000002010000018200006a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AA00A142000\n\t0002A02AA10A10200020220A2023222AE000000000000000000000FF0F150000000000000000810241018200000000000000\n\t00800800000000000000000000042C0002804904240000040100000000100000201481200100001001100000000000000000\n\t00000000FFBB4080000000000000004C00000180000002C00000001200201300000000B00000000001001000000001080005\n\t205400000000000003002002081400A0028000000000000000000000000000FF1C9D0000000000000000210A980180190000\n\t1009800000840004800600000000602800000600002008608600E20E00E0000000820960240001084842A450440C2260000000ea6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5955800044C5\n\t044AD556000484D56000001446296000056C0E557C0621680000010755655611600055655655655655600000000000000000\n\t0000FFCE9E00000000000000002888A8328CC8000A8CAA8000222222232AAA00122A2AA00080128322250004A0022AA33200\n\tA00000022A2AA2122024C82A22A22C222A2AA000000000000000000000FFF33C000000000000400200220000040000000000\n\t00001000480000010000080000000000080405002000808001500A0000800254000000000548000000000800000000000000\n\t000000000000FFE84D0000000000000000008C882A88A8000800AA80003123923022AA0003022AA00000001222A000524102001a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF7F5D1000000000000000000200000200000000000000000140008800000000000000000888010282240020000800010000\n\t00022880000020000A000000000000000000000000000000000000FF60048100000000000000AA88882288C8000AAEAA8000\n\t2022022222AA00026B2AA000000322082002183A43AAA2020020000000022AA2AA4620022AA2AA2AA223AA80000000000000\n\t00000000FFEA208008000000002004844001000000000032010000004004004805000805004000800840888000004C308050\n\t00401001000084004020028000010010008800004000000000000000000000FF080B90000000000000055591594D91180015009a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020022020220\n\t2200280A082000002802802002000000000000000000000000FF50EB00000000000000000000020008010820208004000000\n\t0000020800000001000000000000002202080080000084080000000000000000004002084080000000000000000000000000\n\t0000FF8F250100000002000000000000401423760884100100288000001010C008200001A100040000000000038088000080\n\t1800000000800000001400208040040400000000000000000000000000FFF9BB010000000000000200004088004000000000\n\t0000150008100000000081000000000000240000008108000148540000000100000000108540000000000088000000000000005a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800100300204\n\tA00200206200216200200280200006011A0020020020028020A200308A0025D100A5C21C241A000000000000000000000000\n\tFFF741140104000441801809021001A01523033C8D828001640600720500522600E024406204026002020006004006046206\n\t80700600600E00704100C026006006000000000000000000000000FF170E0024000000010010014012001050111010000000\n\t700018424994004004104104200004000040000510105800000000860845001000100828C442000000000000000000000000\n\t00000000FF4B91140302000020800810C40800800800A40C12810000220A20208200240208200240220282200000080A002000da6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF61\n\t1E00000000000000000000000180020020020100008008008000000000000000000040040040000008000000050000010000\n\t00000800001000801000000004000000000000000000000000FFC5C5000000000000A10A00800800C8088882008C81000020\n\t0200008A20200200200280220200300000000200200200280200200200211200200000A00200200200000000000000000000\n\t0000FF8FBE004000000000200200000040004000200000000020001081100400000000000020000400080000080000400080\n\t0000020140000000000000004800000000000000000000000000000000FFD3D501000000000080880080081885AC449B8882003a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00600610600\n\t4006804042A18004004000000000000000000000000000FF2B15000000000001801804820C10000044000001884090410404\n\t6D4C80804E10610010E04102E4C00008483240060C6A07006006426ACE50708810004400400C000000000000000000000000\n\tFFCB09000000000001801800800821808080044001810000421410E00400000600600000600010600010008000401600E006\n\t006206004006054400202004004000000000000000000000000000FF42990000000000000000000000018000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D04086086812\n\tA42106006400006080A02000000006006002404A0E40408602682E00602802C086007004000000000000000000000000FFF2\n\t64000000000001801804000011810922A0040188C0804C2E096AC200A0460A60800060200D22A000011612608A0064060065\n\t0642632E1172D0884026006016000000000000000000000000FF71BB00000030001184180080080190304112B81180000844\n\tD607654C01400E01603614600001404008006080600080404481400600410422410050000440410400000000000000000000\n\t0000FF4AC1000000200001801C00820820005001211A61800060404600600400400604604608E002006002000000A061628A007a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF0E8B00\n\t000000000188180080080A08400801000382400C600600435600A00780620000600090202422048E20A00620600620620600\n\t4006004000104104004000000000000000000000000000FF60750000001000018C38208028A1A50840C61C01000083C45604\n\t70020C20260A608010E0680802802202CEBAE06002441400430E0860440A6010814626806904800000000000000000000000\n\tFF3A280000000000098038420346A0000800901D11800020688611600228392612E108036090A08280000007046000046044\n\t01601612608C1470A0224047206007000000000000000000000000FFBDAE000000000001801A04828A0C432808808103822000fa6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00508609602C\n\t3072A044C02C004000000000000000000000000000FF2784000000000201801801801821801C01A00111800084408614C487\n\t04600600782600620000000A03080608220611400408480610E02408680A004006006084000000000000000000000000FFC7\n\tF2000000002001851810840830059959994049800002600E8042A600700600600610E05808200420000E0031060CC0060042\n\t06006586046040814016006006000000000000000000000000FFE7EE000000002001801800800801802000400001800028C4\n\t1240404610208600600000E0000A000450101600200E00600400650600600D406B054240440040040000800000000000000000066040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (029060260160\n\t0700600600700000000010000600200610400400440600600400602400C006006004000000000000000000000000FF48C600\n\t0000000001E3189986083800D943A1184B8000A3288280600612710600600630604008000C0402262A220606520C18420E00\n\t6404046090A04006006106000100000000000000000000FF4C8310001000000580384000920380155100590185200108522C\n\t701700E4160060060160014100040A000780A047C8488440C00600603420E211124024114004000000000000000000000000\n\tFF4828000000000401C218000000004410014059018000D022864AF00602700600602600620084000810880608229600400400866040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF5E8A000001\n\t800001801C01401801801C018010008000006806006006806007006800004002004805002007006006006006806806806804\n\t806001006004004004000000000000000000000000FF23D1080049800403801800801A04005813C0180280A048622E20684A\n\t006A0600600000680008400402040602684602640E20600E00400C415020406046106006000000000000000000000000FF87\n\tA4000001800201C258C9831A29809B41825D08840105608704680684600E00680020E00040C80C800046B0E40620610690E8\n\t06806824806B1415600400C006000000000000000000000000FF6488000020000001801C01D81B81A03801821C018000080A00466040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AE12E8240060\n\t85006004004004000000000000000000000000FF61CE008001800003801A00801040040002A01804804094EC060169025462\n\t0E04E01014E52A116048481047026C565470A62CF4068044068040A000E000806006000000000000000000000000FF1ABC04\n\t000180000180392180100588208882580080004060060A620601608620610020600044400402040630E00600601600614E45\n\t614C086400406004004006000000000000000000000000FFECD1000001800001801800001800001801801000800000600600\n\t600600600600600000600200400000200600600600600600600600600400600000600600000400000000000000000000000000c66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (184A03612602\n\t420003684650402000000E48622E4A62AE006006884004820201806006006006000000000000000000000000FF8309400001\n\t800001821C0280180180001320483082007018300C004608728E03C0882CE2A622C038080AB792E26E2E65F70AF20638628C\n\t0C762004E044004006000000000000000000000000FF9A400000018000018018008012000002001306259500050440300493\n\t0571462244400165565162C402080640641650680600600620000E201008006080800004000000000000000000000000FFAB\n\t772000018000018438249812018022000221D9840000825062021E00E066204060024806804004038106006006006006806000266040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A0000018000\n\t01801800A0180180180180100000008060028020060060060068000000060040000000060060060060060078060060040068\n\t00006004004004000000000000000000000000FF13F6050001800405801900001045940110000A0580C0BC08152149824460\n\t0600480000601610E800422006506006806016C0600620080E2048034060A0006006000000000000000000000000FF6F3C00\n\t0001800001801800801000000608020C4A800000020404440700700641402000431600728800280680600700600700600600\n\t3006006008026004004006000000000000000000000000FFAD860000018004018018000018000000013128018C000500480800a66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000021000\n\t0000100000000000000000000000000000FF11DA0000018000018819429050018098001080498000D0082022000800680600\n\t400000660612604000610640E00602602650E106480066080000244010000534000000000000000000000000FFD457040201\n\t800201C8BB50889200201A404A034B8000208541020D0700E026824008A0CA2E806800A0494688E826D06D26CAEA0E886C46\n\t906A80826C84814804000000000000000000000000FF0F9D000001800011801802A018200D5913A15001800114600A41202B\n\t906A1608E1000020870CE0A808220E00721604600E00604620500620800848E00E0C0154000000000000000000000000FF5800666040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (088028420000\n\tA48810C00800200800800A00A00B80A80808A50800B50808830840880800000000000000000000000000FF51F60000018004\n\t08808828800000800AA8000910000000204200200010200280000040208200200010221A00210A1820020420021021120020\n\tC040A00202A002000000000000000000000000FF34E40000000001041000000000019C415040002400002A00010080A08512\n\t0108100000610C0840B849402018006040005802002000060040810018078C404088000000000000000000000000FF083500\n\t00000000000420806000218200060B008000010012905400404011500184880000600481020000800000000000000002000000e66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000100000140\n\t124530129045443500B2CB0000C0480C88C80480C0040040D08008008B08000009090908209408408488048C088083080889\n\t08B0890CC0000000000000000000000000FFA3E00000018000038018810838018A394B82102D80000840AC00453612680E80\n\tE400046006506100206006306106106126046106006006416000436046006106000000000000000000000000FF3FAA000400\n\t800320D20C40808D40C00800F10D00800040A2035430034121422028014032B302305110B10B0030234030135030034B34D3\n\t0A3151083313503412000000000000000000000000FFAB340200000004402002002983402022000422030000818D08000F1400166040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C50850900C50\n\tC90940000000000000000000000000FF07EF0008000000004000204104004000344404000000011009001001000001000041\n\t000001001011001111001011001001001001001001001049101001001008000000000000000000000000FF408E0008000000\n\tAA0AA0001100220840802B004000000C0A402202202202A8AA82002A80000000000002202002800000000102A80502000800\n\t00000200200010000000000000000000000000FF6B53000000800400A00A90A4AA00A00C00800A0080008320A280290A9028\n\t02002000802D52C02A00002802822812A12B12B02802C0A84AC02A40A4280284280A000000000000000000000000FF70560000966040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A82A9B002A82\n\tA82200080002222B23C22AA2AA2AA2A82A82A82A80082202A82A8000000000000000000000000000FF826400080000000040\n\t040200200040004202210C00012810010080008008010000000002C80404000000080A028020023022000040029010020043\n\t0100020400000000000000000000000000FF58120000000000AA0AA00A0821320840800820AA00002204802A82A0220AA82A\n\t82082A82A83284000002202A02002A82A82A82A82A82A82A80802282A82A84A0000000000000000000000000FFEE30000000\n\t0003541540D02402D41303085002000000010510540D484D0550550548D50800D10800000D40C08848930880880D5088082000566040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000023801809\n\t8118A180B80900188104000060140064461060040860100860060162000A000600E00602632620600642612E246410004006\n\t016006000000000000000000000000FF5D8A00000000020140134928820044924140520100009148A500480514C805004100\n\t8000008908008008108008408008008008008008008008A090C800800CC0000000000000000000000000FFD2050000000000\n\t0080080480490080480C84880080000020020020920020020020500020020022000001020120120020020020020020020020\n\t0000200200200A000000000000000000000000FF09180000000004AA0AA50006002A0D04800900AA00013202482A8230310200d66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (081080044C40\n\t00000000000000000000000000FF1B3D00000000000280080880C8A088800080000980000A248200220009000200201800A0\n\t0211A140001222942E828828829423A220A04210225015240211A052000000000000000000000000FF2085400C0000040044\n\t040042000450040040041000016116010810050010010092600010A008100100000110800000000000140000020009102110\n\t4000000000000000000000000000000000FF07FA400400024400D00C00C40800C00C00C00C00904114310308300300B00300\n\tB30000B4B21030130002230022820820020131420924020830C300A002522002000000000000000000000000FF793A00000000366040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000601006\n\t400000011600609E3FE01E206112006206066000402184014004408000000000000000000000FF630F000000000001803801\n\t809085801148001003914021640804E20401401000E000006000214000000406206086206006206002006404006450000020\n\t080004010000000000000000000000FF5FB700080000000000400801010188001002014200A05081300102300402C0130000\n\t0880102002004A0288200000000000000208000008000400200048000000200000000000000000000000FFC9EF0000000440\n\t200C00000010038020080001010A2001001000004000800010010010620C0004080C0000100000020220408000140148448100b66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018818310\n\t09821002801109800004600C14608400400200E00052680600680040842600E00E02E2AE0060060D61440B68210862C60000\n\t06000000000000000000000000FF07B300000000000180184580588180182103382380000960C200E42000600412600000E4\n\tAE52800002011644644640600610600200400E00420045200C2A4094000000000000000000000000FFE57600000000000180\n\t180980383000380104988100000A60C20060400063440460081160040843403410071272070070070A64020060360860000A\n\tA20800602C000000000000000000000000FF2F7600080000000180180186182A1630A00090418E000260006261946440081000766040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (604848055400\n\t0000000000000000000000FF1AC30000AA0000AB8AB8218818238890A088B2A380002C62202472122AC2AE2260004860A610\n\t3040A002064061060160068862AE0840960A425022E024204286000000000000000000000000FF444E4000000000018018B3\n\t80108802300882B04B8000086020026AAA0040060060000070260020000880069061060361060A60064840040C4008006206\n\t006006000000000000000000000000FFE46F0000AA0000AB8AB80D8811220CF088881201800021630430600C2AC2AA306000\n\t0060060460201D00461D608618604622E2AE61660621600800640400C226000000000000000000000000FFBB84200000000000f66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (106006002000\n\t00800E0860868860860060044840062840000062C4004006000000000000000000000000FF60BC0002AA0000AB8AB8098AB0\n\t2A08988188180380002062A63060222AE2AA2AE0002362362AF000A80017C260664068064862AC0262AE0170412AE1060582\n\tAE000000000000000000000000FFEC12000A00000001801891855011801012041009800000600801612000400201600004E4\n\t0C21200000088F00742EC2730E45600402404640400010609412C04C000000000000000000000000FFDE4500015400015595\n\t5801955844111144101281800045649041700455455255600052650455601444054603621608643601655402E55420610055000e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180980000\n\t180180380180000060060060220560060060000062160020040000164160964060061060060140C610401000625601600600\n\t0000000000000000000000FFA49F00000000000180180194589182B8290298AB80000060AE00601610608E00600000614611\n\t22800002A602642604E44E44E0864A40064241202C6104324094000000000000000000000000FFFF82000000000001801821\n\t80190000180B04982180000360160CE88E00600600600000E08E0028080212A6216A0E25642EA360060140060340B0006008\n\t2A6004000000000000000000000000FF3E68000000000001801905801801823841805B118000086006006202006002006000008e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20C2AC000000\n\t000000000000000000FF4EDF0000000001559559558418CC11591390381180005564565564C640E556556007556110546506\n\t0025560160160560565564CE4540485040D0046156496526000000000000000000000000FF8F258000000000018018018019\n\t01801841801801800000608600600E00614600600600600040E0000020060060060060060061060040040040800160061060\n\t04000000000000000000000000FF2A180000000000AB8AB8AB91582388188388180180002AE2062AE2822062262AE0002AE4\n\t0622206000000618600608608600622E00470E04C20001E004004236000000000000000000000000FFE53B00000000000180004e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (508860100020\n\t1649608640600610601600600200600800C254016006000000000000000000000000FF116C0000000000AB8AB8AB8AA0238A\n\tB8900AB8AB80002AE2062AE00E2AC2862AE0072AE20004E0000020065061464861860062262AC2AC2AC0202245040462AC00\n\t0000000000000000000000FFA7BB00080000000180180180180002102183112380000060860060160A600600600600604000\n\tE0000020062464A630648600600610400400C400286206024000000000000000000000000000FF05B40000000000AB8AB8AB\n\t8AB82B8AB0838AB0AB80002AE22E2AE2A62AE20E2AE0062AE2A81062880022CE04E40E12E42E2AE22E2AC2AC2AC4502A602E00ce6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (880001962801\n\t800C010100046206404206006801006008886A8090000002200E64700624E2060074065047D442400008E206007004000000\n\t000000000000000000FFBF28000400000601A0180591000000A000000001800028640401404610400088E208447001026005\n\t002006006C060064460078B60260020C600001500D004000000000000000000000000000FF4C050008000000018018018001\n\t0180002400000180000060160044C60040100060008071002262800022C602642E04E44E44E0860040040044840840843250\n\t04000000000000000000000000FFE89E000000000001801801800010001810001C0180000060C60060060050260060060060002e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000000000\n\t00000000000000FFA7C380000800000190180194011181080014288D008021640E2AC1560AE10000624000E1004021010022\n\t0624611610600600700E00600A20608012C44C406136100100000000000000000000FF900C80040000022180380181000408\n\t880C000801008053600648408E0471200062802268015020000020060462060C602600E04E3160560960A802500500600400\n\t0000000000000000000000FFEEE0800000040041E05801800042000813800801000001608610448F8270C000610188652020\n\t800002200E00600630E00E08E00600C00000C128326406006006000000000000000000000000FF4D6A800800100581C0190100ae6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (641000400E02\n\t610610620E00600E00600200608008022C2040C8080080000000000000000000FFDDAF000000000001081801905890002050\n\t102009820008648E0041021560C040E40000E00000612021424610603602600600620610600608E000400104104004000000\n\t000000000000000000FFAAEC0000000000010018018018040630A980114183000860C604624000602600E006806000002028\n\t20800E40602600600600600600601248E618052086004000000000000000000000000000FF9F910000001400010019058038\n\t4388100180102188200261260160401060063160060062600F820000002608600602621E1067060C40044040006020160840006e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (328A08800C08\n\t8880002AA5622C02042202122AA2422AA00040218222C0024821424821820022AA0020020022083122422020020000000000\n\t00000000000000FF20E500000000002000000000010980002A04004400000001080400280100000000480060003140001000\n\t10410090400000100000100010080000048000040054000000000000000000000000FF032C80000000000000000000400180\n\tC00000A00000000004000081000801280000818000000202400002C00204200482484280004484A02280401000C809048000\n\t0000000000000000000000FFA329000008000001001801821801890100020003904044E00651440A0060000060210062C02B00ee6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF252F800000000355F5595591194590511390D1558001D56556D5654E55643555640C55600150621045655601\n\t60160560565565565560565562204CC556D57156000000000000000000000000FF61960000000000C88AA8AA8CA822888880\n\t88ACAA80002AA00220A22A2AA2A2AAA202AAA0000820002A22CA04A40A12A22A2AA2AA2AA28A20A0202232823224AA000000\n\t000000000000000000FFBB360080000000000002004440000280200000000000000000000000000080000080001000040080\n\t0800002404A0300480000000000280000010004000000400000000000000000000000000FF825600000000008E0AA8AA8A88001e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0002A0020420\n\t048448428000000210000030100000000480000000000000000000000000FF82A80000000000000000000001000100000000\n\t0000000000000001100000100000000000009300000300104100904000001000000000A00000000000000008500000000000\n\t00000000000000FF6C599000000000AA8AACAA8A883A8808A08C08AA80002AA2AA2AA2222AA2022AA24BAAA0002120802820\n\t02182002082082003AAA2AA0022AA20022A2AA2AA002000000000000000000000000FF4B2280080000040140140140010002\n\t304D001400000100401108410400400480409480100004844001400008000000000000000400004012020800501101000000009e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080084084080\n\t80A0220200228308210308000200000240200000000802220240A80200208280280280200080200280200200000000000000\n\t0000000000FF3EA200008000000000000002000000868208A6121400020088440000C50000C00200020000080200000000C0\n\t0100000000000040800800000000400000000000000000000000000000000000FF47D50100000000000000A0000000004148\n\t04050400000D9100008000000000000400050000031000000010800000000000000800010228220800000040000000000000\n\t000000000000000000FFCCAD10800000000040020000200004401202C0000001000000000000000120800120000000000210005e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF6B8C010000002000800800980812A2084AB42840822041266266AA22602062001182010002802000000010002003\n\t80200200200200200280306000305B01A01A000000000000000000000000FFC4070001100500018018B18218018098030350\n\t090B0149700E2268042AE1063000040200064A6000000010A474864160060060460062262270010060060060060000000000\n\t00000000000000FF060B0000000000AA0010000010282001113810650080244D04014D0400420C0004040000008004000000\n\t00080800801000001100000010000200400205004000000000000000000000000000FF94D40000080280008008108008008000de6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000002000000000000000000000000000000000000FF874100000000000100000100000180000000040000\n\t0000100000000000000000000000000480500080000080000400500400400000000000080080080100080000000000000000\n\t0000000000FFDEB4000000000000800800800220804A82C00882044002210100C04000000200020200000200200000000010\n\t2002802002002002002002002000002402002002000000000000000000000000FF73AC0000000040B4000000000204040210\n\t2040010100000004801404000210001000020000808000800000000000000800000000008000000400800000000800000000003e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (389011800004\n\t648284619E00600600000400000600640000004000680204240200240203E006806800004006906006000000000000000000\n\t000000FFD025000000000000801B0580520002181200008000000070C220400688C10614008002009714E0000000000C604F\n\t30612714701288680608E2A8012026006004000000000000000000000000FF0DF402000000008180180100110180580004A0\n\t00000050E00200C4060040464000000000064060000100002061060060064060020265564060004800060060040000000000\n\t00000000000000FF7D6E0000000000000000000000018000000000000000000000000000000000000000000000000000000000be6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFA19C020000000040901801021048510080C00C2582804062120120848040060082000302061460000002000060C02000\n\t0209280620E006286532217007006004000000000000000000000000FFB40A020000000100801805401081802000C0291180\n\t01296022A3680410C1262200800201060162000000200860AA2022C20C200610600609635030C02608600400000000000000\n\t0000000000FF650A0000000000008018818118018618191615118001036B424462461060460C010600014EEA600040904022\n\t40028A2450E0020A0063EE216000002116106406000000000000000000000000FF2DDA000000200001801801A03800001803007e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (500E01620600\n\t614D009131001412016807806004000000000000000000000000FF6170020000000021801801821050100000002130000004\n\t6806404100014006010100008426086000000010046006046086006004400000001888000006006084000000000000000000\n\t000000FFDA8C00000000000080786380180384612090AA0181214A70421C224400E246800802180006046002800008024140\n\t020080510006016846006400016006106086180000000000000000000000FFB757000000000000881803009E022100308488\n\t03822108E28A01240408620702120202010620600120024000400020023000000600708630E02240408E006406000000000000fe6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3002000B6812\n\t20400300700720000400000680630020008013412E0962460061060AE40E00620A0040960060060000000000000000000000\n\t00FFE6EA000000000000E01821825201800005801E0180001560058020000A4806A0000700000642600021008000C4060C68\n\t2600600400020002084000608E106004000000000000000000000000FF51D8000000000000801C01211004006401811C5180\n\t0080701500230020400608080600000600650480804010634642681F40602474008070192100E64688600400000000000000\n\t0000000000FFB821000000400021801C0100140982000020040002000064C7C00C002040060800000000060060000810000400016040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t20A6000000200002811801A01809801801981807800040E40220300200600600118E00000620200000088026402608748600\n\t710602E006006010806006006006000000000000000000000000FFF57C0000000802408098018DB8040C18058038A0002122\n\t754200010B9660060010060000074420041000410848064060064060168060469461080042C7806086000000000000000000\n\t000000FF4DCC000000204440841831821841C53C1143101180000864D2042522316006080045050086042001310808804406\n\t006206086086086286246080926026107806040000000000000000000000FFCA7F000000000200801841803A08201A01211000816040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006006006\n\t006004004000006004006000000000000000000000000000FFEED10000000000018000010010018018018018018000006804\n\t8070000060060068060000068000000000008070060060068060060060048050008068040060000000000000000000000000\n\t00FF2C69000000100001800001801800025801A5182100001060840064812468060060060100060000040000000864060068\n\t86006806886004404104086506086080040000000000000000000000FFCE680000000044258404498CD829891C11A03C9100\n\t4002E034446050116806086034040106A20000310088A060461060061060060562840240000448270060000000000000000000416040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000086406660\n\t4208202608618E0408060024000000008064064068069866A496C004004000006004006800000000000000000000000000FF\n\t9622080000100081801004A01A00300500412801800004900B00F48220604610E85648831755201400010014F03614E42E00\n\tE02C00400E08EA05004006006000000000000000000000000000FFA5C0000000002011801000801801802042080843800050\n\t00820860020CE406206206000006002000100008406106006106406104014024004000106006006000000000000000000000\n\t000000FF50A7000000000001800001001000001801801801800000600400600000600600600600000600000400000000600600c16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF2847\n\t000000000041C00801A00800002040003801824108685208600000202610E08612820613424001000008E006096026840006\n\t0260042A4828007006006000000000000000000000000000FF7B6F000000000041880809800E01880000103801800002690A\n\t09EAA022A54624E44689828E0847080800C000E00E0AE28E24000F0C602C5CC4501064060060000000000000000000000000\n\t00FF82810000000002018000000000000042402041058440110050D26B5248200E11690614044695204411000010E8065160\n\t46406004004006006000806004006800000000000000000000000000FF0EAC0000000002019040120400118020A20602138000216040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0644A0020222\n\t260260480A6C0400E400000000000000000000000000FFE600000000000601801001201001801801A00E0180000060028060\n\t00005806006006000006006000000000006006006006000002002004804000006004006000000000000000000000000000FF\n\tAD4E100000104111805800C408118000001118518000D0014200E200002406006C46440006C56000800830546546C0604601\n\t2006806006806400186006006000000800000000000000000000FFBE07000000000001801800800A00000000080885800000\n\t808242615048230E02722680002700608108100000600740600640380700600600640000420600600000100000000000000000a16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020800028008\n\t00800001800000902300004004400E02806402180102A00000004400980E0000120000000000000000000000000000FF86BA\n\t02000008024180110220000D801911808881800000000004680400052E406206008006C0640000000000E026006006046002\n\t00200620620000401400E200000000000000000000000000FF4A9E020000100021A8D28002424A351A01AAAAA38000801000\n\t884040AC1157046B26408B064268000402808468A6906836806AA2C82886A86B00A06904A260280000000000000000000000\n\t00FF8535000000000081A21013091100401955A00C01800034EC4A84ED0000C2060060020010061160C840000108E20E20F200616040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFE0DB0000\n\t000042A05082000C026033C0041C020400000001001310000008100210402008409C4848030200800808980800808800BC0A\n\t00800800800880800800000000000000000000000000FF9AED0000000000008E6888C3C802840840810902800000802608A4\n\t26B0A00200240200000280A180000080002002002002002002402022022000302042002000000000000000000000000000FF\n\tE65900000000010000100040008180048A42002000014A144140001146020000002040020600002024000010010000816032\n\t41400204C0180460400300200028000000000000000000000000FFA6F300000000040000005010200188002000205000013500e16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (280A80280280\n\t28408D2802802040000000000000000000000000FF137F00000000020120022C02530024021420440C0000804084AC801488\n\t5004004900000800804800000000800808A00890890900910910908808C00800804808000000000000000000000000FF8F47\n\t00000000400182584183100194380980982D800050E0C430600402440E4060862000160D4140000040106006506036126086\n\t546206086010046016006000000000000000000000000000FF41C0000000000140C80D08A84C44C10D42D40C808000023C03\n\t02BC0A303103003242001042203200450201023083023103013043003023243241503143102000000000000000000000000000116040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D08D50C00D50\n\t800C50800D50D50810800800880A00890800D28CC0CD0C50CD0850C00D50D50420000000000000000000000000FFA9C80008\n\t0020040000040040040000000041442000008010014910000000000000D10010015090010000010010491010090111011010\n\t01101011011001001000000000000000000000000000FFBEFE0008000000AA0AA08008402208A2E00A806000002A82000402\n\t202102A80008000002A82A80000000000002104402100002202202202200000002A82A8280000000000000000000000000FF\n\t45FE000000000200A00A00A10A10A00800A00B00800000285280290282B003002452800802802810800800B2A9428D2822C400916040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (765700000000\n\t001C6AA0AA0AA03248848008002000012A82200882A12A92A80002200002A82000000000002AA38220234220022022032022\n\t00202402A82A82A8000000000000000000000000FF85320008000000000000A0000080004004020000000080000000000012\n\t00000000800000000000000000002281400004A00000080000800000000C8000000088000000000000000000000000FFBFE1\n\t0000000000C00AA0AA0AA0A20AA0B20A008A00002A82A80202A82A82A80002000002A80200100000002A82002482002C0228\n\t2282282300404802A82A82A8000000000000000000000000FF14E400000040055435421234825435051030C30C0000550D5000516040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002482503000\n\t003003002000000000000000000000000000FFE7D51000000018018218258098018819018319018140044056246026004006\n\t28600608600600E0400062860060060061060060A640602E00E540006006006000000000000000000000000000FF97720000\n\t0000140500020120020024424302A28500008048048408108048040041150008008008008000048008288208B08B09089009\n\t00900808828800800800000000000000000000000000FF7191000000000920800800800908800810A0081080000021124020\n\t0200200200200200200213201000200200200211200200200201201200A000102002002000000000000000000000000000FF00d16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (005040001000\n\t00108046010020004280400100040000200040200428508000000004000000000000000000000000000000FF7C7A0A000000\n\t200082082010880288080213090700201220300020020122021020020120122420004020009A2C02B02AAA18208A50211200\n\t26800AA402402010000000000000000000000000FF624F44080040040440040240000C40044C400424000120960D0A102140\n\t1401201201000001001000001004040000400050000010000080001020151001000000000000000000000000000000FF5BEE\n\t400000404C20C04C00C00808C30C10C00C40900140B10308300310300300320301202340300000300248210204220250200200316040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000804001001\n\t9C192701184406B8C0007041844000808600201462040600600600400600401000002641645E606006106042002406006020\n\t16605C004000010000000000000000000000FF0AB60000000010018030410C10098918020A908800800A000E002084006126\n\t40E00E00400600408020000600600600602600600200200600644000C080504000000000000000000000000000FF80FB0008\n\t0400008002208004803590004202005005200400002D01500003402100080400800001080000002080400080204080400004\n\t20000100108120120020010000200000000000000000FF14520000000000240020000010018280C00081001080000080400000b16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (160160087142\n\t8C2AC000000000000000000000000000FF125520000000180180480200100980000402080180000CA0840AC08E1040060060\n\t0600200611680000080600620602E086106006006006106800006006004000000000000000000000000000FF78D700000000\n\t1001821809033901841821813831800000404E40200600800600630E00400604450000000222E0CE40645602C10210A0CC24\n\tC48014E044006000000000000000000000000000FF1DE7000000001081801801001800003881801803800000C10653204602\n\t800608600604C08E02400000004708700709700620E0022820CE006100006200046028000000400000000000000000FF428400716040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (455655641700\n\t65565564040020044060362060364164D44D4556556010556550554000000000000000000000000000FF25C10000000018AB\n\t8AB89508B8A38A80AB0C5881800022222D20EAA622C2AE2AE0860022AE32E28000000321608610645612C236226104084500\n\t0263042AE000000000000000000000000000FF53BD4000000018018028050010000000010138018000002005006046054006\n\t0060C68020060061000010020B6286036286146006006004004280006006006000000000000000000000000000FF9DE90000\n\t000018AB8898A008102208E088090AC78000212A04804A362242AE2AE0260022AEA060000000061C601649600660422E226200f16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018018218\n\t03845901A00000891A01800010690E806C4E04E0060064460060040064800000000860860860861040040040040042100060\n\t04004000000000000000000000000000FFF7890000000018AB8830B109102208C08C8018AA80002662262AE1862062AE2AE0\n\t060062AD2A30040000040260261060262042242242AE2AF0842AC2AE2AC000000000000000000000000000FF077500080000\n\t1801801821021011C00000001C0980000810820C2006104006006436006006006800002000006A2682688600610410C24444\n\t4010006054004000000000000000000000000000FF2EFD00000000195593112114594C150150121D54800048954A552A0E5000096040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400008C20421\n\tE000000000000000000000000000FF25C100000000180180D102121800041801823820800000608E02400612400600600610\n\t6046006084040102096096016006004006016004504404246016146000000000000000000000000000FFCF7A000000003801\n\t84082980B88980384B811901800013400601205640C00600600600608611620211000A42644644625612411610654C054088\n\t006124006000000000000000000000000000FF40EC0000000018018080080118100458258258008000014006002006104006\n\t00608E006006016804000002C1721723720E02C11610E004004000006000006000000000000000000000000000FF3914000000896040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A82A82262AE\n\t48E4002A809020E10E22602E2AC22E22E2AC2AC3002AE0AC2AC004000000000000000000000000FFA79D0000001141558058\n\t0C92284C15592990580900004564524064A61165565505504C6D2E4564065525504360364CE45600C4D64D64345245022461\n\t56406006000000000000000000000000FFC88C80000000000188180180180100580182982580000560020560040260060000\n\t00016006006000000040046046116006004106106004004008006004004004000000000000000000000000FF98F30000000E\n\t98AB88180180182388988188180B80002062262942960442AE2AE2AE22E20E32600020022200600608608630C2262260040000496040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0201821C2080\n\t080104000182880B800011600600600612600600000001400400620400242001609601700600400400400600608000601000\n\t6000000000000000000000000000FFE81E0000000AA0AB8558498AB82308808188080180002263062062AE4062AE2A82A832\n\t4AAC2461002A84001064060865862AC2242242AC2AC0082AE6042AC004000000000000000000000000FFB7E7000800000001\n\t8A98C00101000018030498A380000860840A600620600600000000E00600608400200010630600608644400600610400C008\n\t08E206120006000000000000000000000000FF0E730000000AA0AB8018950AB0AB0A98AB083891800028622E3062AE08E2AE00c96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006106006\n\t000000000000000000000000FFEB2D800800180481C11C048008010218A48A30099000A26036006002006802500400046806\n\tB0E0000040102A70469868C700400602E0040E4040106845404004000000000000000000000000FFFE73000000000401E058\n\t00800801120000000003800044642600E0060070020400000840064120240020004468862062078862AC4040060062082040\n\t01800000000000000000000000000000FF313800080000000191390280088900404A00214180008060D60B600640E8020000\n\t000850068CE0800021104A6446C4645600610C114004004200007124004004000000000000000000000000FF44260000000000296040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (005060060260\n\t4000404002614648600600C01200200C084538404004024004000000000000000000000000FF1414800000000441A0190415\n\t0081085810848093880000600608608211641214814004E08600E2C210601000632602628E04600644E0060061020CE21108\n\t6140000100100000000000000000FF6EDD80000000000180380280C8010918008000019100016516056002106822CA020002\n\t700610600000408800600600E22E8A4546406056006020086044504004000000000000000000000000FF4C6E800000000101\n\t801800014001009940943009808000E08622600210604300000040700600600000614008600601608E02600604E02C10408000a96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (803900810843\n\t001800004081820010600600E0A602E4800B00A002710601402080600004622610600E00600222A01600615000C400140120\n\t000100080000000000000000FF2FB800010000000180180494481108D80800802D814000E006142406086020000000016006\n\t04440010400800610E046486256002002006106000046114004004100000000000000000000000FF7CFC0000800000018038\n\t008009010699E504182190A004E44600400600601400000000680600610000600000600E0060062060020020060060001040\n\t86000006080000000000000000000000FF7C8200000000000181180080282B00180700380582000A622642C2260260A4000000696040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004802000000\n\t00000000000000000000FFD8780000000000AA8AA8408248AA88D08088807080002AA0422007022AA2220000002202622520\n\t008020001024020821C2202222222002002008402602102402000000000000000000000000FF1ED300000000000000013000\n\t000100002800008300000000801280C80000000000000000060084000460000100900100001000100000004002A000801451\n\t4004000000000000000000000000FF94DF80000000000000000208A001822004044008000000023000000000008800000010\n\t99081201003100004A04404402500281001085500D0000340140020530000000000000000000000000FF5E0500000000004100e96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (500000000100\n\t00000400401100000001001000C0040110011080000100000000000000000000000000FF565E800000000555D5580D005055\n\t95112915195500015565344A44465564448000005575560165015460004360364CE0165564CE4C65565562105570560570D6\n\t000000000000000000000000FFF0C90000000000AA8AA88C8D08AA8A88C488280080002AA5022AA02A2AA2AA00000032A30A\n\t2823002AA00020A10A22220A54A22A22A20A30A4400A302A42A02A000000000000000000000000FFA9AE0900000004000001\n\t0028008000200200200100000000040040808011080010000048002A00010080000803000002A00000000080000000A0000200196040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4C04C0800420\n\t2004200000008001504000080000D00000000008004485010080004A04404404500001101000000001300011400215300000\n\t00000000000000000000FF0D4200000000000000010010000000001001000000000000000881000000000000000000000000\n\t00000000010090010000000000000000000200000011510000000000000000000000000000FF26608000000000AA8AA84085\n\t082A888882880EAA80002AA202032233AAA2020000002AA2AA0820002A20000020020820822AA22222A2AA2AA0002AA30300\n\t2002000000000000000000000000FF26BB80080000040100100120100000101105108300000040140040010048050008000000996040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (011400000000\n\t0000000000000000FF0E2C000008084802800800A00800804C00840C00800000200200300202200200000200002290200000\n\tA04A08A122122002002002002402402800082012003003000000000000000000000000FFA6B0040000000008000000200002\n\t00002000022804000A80000000000000000002801001000004000C0000000000000000000000000010000900000140800400\n\t800000000000000000000000FFE3900100000000801022A00000000044820C20800000200018000000000980000001828000\n\t00000200000000000010180000008000008008800A0000008090A8000000000000000000000000FF2B66090000000400400000596040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800800804008\n\t000800080000000000000100000000000000800004000000000000000000000000FF180601000000088890088A800C008008\n\t50D9E81000000080130128020021020000424880020020000020030020028020028020020020030030000020020621830000\n\t00000000000000000000FFE9FB04001010591580180180180580504188102182000260060060040478040000861201461060\n\t02046056006146146006006086006C0620608208680600F224000000000000000000000000FFDF5D0800800AB00100C54000\n\t102008152C64511900007140300080040041040084252300010004001158081118008010008000000001901100100001500000d96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF917B000000000000001400000001000000200000000000000480000000000000000000080500480100\n\t0000805004000000004000001000801000000800800000800000000000000000000000FF1CB3000080000080000800800000\n\tA00A008210000000000002002802001006000006808002002002000002002002002802002002002002002002002002002802\n\t000000000000000000000000FF6A761000000CD00901028A00044030200000000100002140200008040000018100000A080000396040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FFE7C6000000001A11801A01881001B10A00001801000080400700621200600000000699800200600000E006\n\t00208200620621A20600400602E04820408601E400000000000000000000000000FF709C0000000018058289104145518409\n\t002141040000080206106106006004000106400806B260A004E00648710E486C074468070061062573103021070048000010\n\t00000000000000000000FF7F96000000083801801840080001000840100000000000000624620630600C0200060000220060\n\t00006026006206036046006206540006106000010004004000000000000000000000000000FF409B0000000000000000000000b96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (810060061081\n\t01004046000206104086126000204017006404000000000000000000000000FF0911000000005001400A20200B45220932C0\n\t18220000002306A0D09630640800048E52010200610801640401280200681400020600210400484040E004A55A04000A0000\n\t0000000000000000FF4F48000000105005000950200A1104010091390400010820060A60862060100400064000420C602000\n\t600608200A29600600200600000648624010C006004204000000000000000000000000FF0B61000000001A5982C90580B0B1\n\t998820301811940011420620604A0C6100110086000002206080066024300300024024822006AA608404408004201600610000796040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008C00B04000\n\t000000002605600604400200000700100332600400400E01600600404600F00008E00604600440E00E204004000000000000\n\t000000000000FFD36F0000001018118218000508018009009001020001000006C06006005202008006100212006014004006\n\t00620600608E00602000000600784002000642C005800400000000000000000000FF73F5000000085007024849829B519028\n\t448638C1858030200707495614600600040600020A0068008564040002009840A40600260860040840000160068071040000\n\t00000000000000000000FFCEA2000000001021200893801803652010803809880140848600400640710E10010E220082007000f96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF002C000000001801828801C01801820000B00009000100408682701620600400008600008A2072840040044CE0\n\t16C5408401600608E11404520001600E006007000000000000000000000000FFA815000000401801800C0200081184180080\n\t1800000001400680680E40500200008680000200420800400422610EA0C004086080006004004A4812600600C00600000000\n\t0000000000000000FFE90A000000001BE1950860140809208C04803C70000100C10600618682400200000680011209610500\n\t460C106086046124006018004514004020205804004806000000000000000000000000FFD43500000000380180180020080100056040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800E1040062C\n\t610608E2B60060868058A6006006007005006806000000000000000000FF1DBB000020001A03848801AC18018098BB9C1803\n\t0200A840C653700480600E00050601800201E8000040040070070A401400602600600400408C00600417F146540000000000\n\t000000000000FFC155000008085801900805941829C00C05C00081000000404629E2060068860002060200220D6016004804\n\t00608600402410610E0044040040101C4006417027800000000000000000000000FFC569000000455801820C558238818232\n\t00851851004004402E0061064D7024010106101C93A0620400C00C10600620410C0963060061040040222070060861062A0000856040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018010000\n\t0000060020060060000060060000000000040000060040060060060060060060060040000060060060060060040000000000\n\t00000000FF9047000000000001800401801801801801801C0100010000060010060068000068068000008000050010060040\n\t06006006006006006006004000006006006004007006000000000000000000FFB73E00000814A201810011B01900003A0180\n\t1890000004000602440650600000600610004030080400000600490680604600600600600680400A28480600600600600400\n\t0000000000000000FF8D84000020000203800223A038518498C5811844022030009600408405612800E806840290800A040000456040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF620B00000002000102200710102080909920080000000BC01602882E0069202060063880188810048002064C642600\n\t60064066C405E206006804006806006004004006000000000000000000FF5D920280004CA001045001201040851205002802\n\t100002402708C40602603054E0A60300401020444003060840A7007496006004006306004021104006006000006006000000\n\t000000000000FFFCAB0000000000010010018010018019011008000040484506044056006000006006400000000406000006\n\t004006406006086114106016014002006006006004006006000000000000000000FFD171000000000001800001801800001800c56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (40400E006006\n\t007006007004205020806006006004004006000000000000000000FF1E8A000000000001800801001A00805001A3180A0500\n\t000016004086006100526246010050000D08110006006446C06B2E50600600620600E9100040060060078040060000000000\n\t00000000FF2DEC000000000001800801C01A00821C01883812082000024600420602600808E4A60200200003202000C60040\n\t862066CE08600E12648E01C110907006006004014006000000000000000000FFE43D00000000000100000180140080581105\n\t09040540080516802D4F10E9505560D6410150102434D10006406456406116506004004024406220A000060060012240060000256040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (220000000000\n\t060120B3506108404086008211416102000AC68AE22E00620624E8020244060060020C4A0680611611011600000000000000\n\t0000FFA149000000000001A01001801800801801800000000000000600200200600000400600000080400200000600400600\n\t6006006002004006004002002806807804000006000000000000000000FFBB4D050000114001801801101000001005001800\n\t000040015610600E006100046006000000002000000006446406006006406046186824006A4038400600600122C006000000\n\t000000000000FF2F65000000000001A01801001200401011000D010041881AC600442608F85000E09620210090202020104700a56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF3A3F02000018004000400205800000041004400000000000114982015002800010002200000000004000000A0000200200\n\t000000228040058050280290080101000006000000000000000000FF7F9E0000000000119010011010109071411221200000\n\t018406022026A2E00002680601008010600000012620602606610E5060020841140860000404060062900100060000000000\n\t00000000FFAF89040000004401B092B1A81290AA3A9120833200008D0826D42C06056200856026AC0080846800200806A068\n\t06CA6956806CA2C968A6A96920A12956D46A24A00806000000000000000000FF5DED000000480003843005849840A118419200656040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030230830C34\n\t8300350302301108B403003892513012000000000000000000FFCA6B0000004003022902084842082C02000002410000C048\n\t00844D808C00402040A4000800800810300C00800808880800A48E20800880A00980800800C0100800C00000000000000000\n\t0000FF60F40000000000010008C0C00180800804080802800000202200200600210800800200200802200000029211A10200\n\t20A200200241260200200010206A062002182002000000000000000000FFE80900000004200002B0310200600390A8218089\n\t00001A40463000580010000010004CC64025C08100000040020040004002018010002000002003800020042460009E00000000e56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00008A0802A3\n\t2A42802108002002802800A02C00800802852842912B028528028D280280AC008D2A428C2022802802000000000000000000\n\tFFD2C80000002204432002080412253042010143250000C1480090490508C840004004000800908802808B48D00D08C40848\n\tC009008008C0AC080AC00888810110004000000000000000000000FFB6610000000200119018498058C10838819018010000\n\t0140560440A400602000680602640012E0000001162061062060264060062960560161400460564464060040060000000000\n\t00000000FF4F29000000100520C0CC00B28C10C5082CE2AD40800130320231340A4A210100200340A02100300828120308B000156040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFA7\n\t1000000015431435453031028C2443502A22400000C00D50100A00540540000550800D50910A00D40D00850900C808B0A90C\n\t48910808C00C08900840CD0490000800000000000000000000FF994D00080000000040401041040040000044440200010090\n\t000010000000110000010014090014010010010C104900100114108105100100104140900100081000100000000000000000\n\t0000FF58AC0008000880880AA0820CE08010008A03011000000002A84001082302000002A80002A84200002A000050001000\n\t00000C0328240248050020400000200200000000000000000000000000FF5476000000004400A00A20A00A08A48A40B00A0800956040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200211200A10\n\tA002002000042002002092002002000000000000000000FFD6610000004AA0AA0102A20EE0AA01048002008000002002A92A\n\t8200AA92400002A80000002A80002A82AA2002022AA2AA2022300202A82A81200002AA2ABB21000000000000000000000000\n\tFFE8BC0008000000200000040000200080040000020000128001048051000008000000000000020000008048000240030400\n\t000000200300100020028290001021000000000000000000000000FF4B390000000AA0AA0A02C40800AA0A20D20880D00000\n\t2C02A82A82C8AA82800002A80000A02A80002A82A82082802A82A82082202802A82A80100A02A82A8220000000000000000000556040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000043003003\n\t003001001001002142083001402202402402202542002102142082023000002002003003002002000000000000000000FF16\n\tD81000000000138219498019250958458A5801010030E20E4A400601600000802042600E0160000060AE0060460860060164\n\t2641624620E230006026046004104006000000000000000000FF599C0000002000014CC0092012012C820020C20500008848\n\t00804804004848800000800A48800800800800940928800800820900A00800800910D1080080000480480000000000000000\n\t0000FF58B400000000000080080080080080482C900850000004A0020021520020800000000021020024000020020120020000d56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF43FE00\n\t004000A01002008401203203102001400500801000260400000080000900400400840000004040A00044202802800000804D\n\t0040008050000040020000010006000000000000000000FFCAEA080000020023000868800080800846820885800000C20A28\n\t201400000000000060200201A410012902302812902C1AC8A202012002102400403403402186042402400000000000000000\n\tFFB2EC40080040040040A4005804004824004805000021200001005001001001101001198028081001000208000000060030\n\t100020000280221200000000001101094000000000000000000000FF02F340004044A440C12C02C0CC08C40C00C10C02804100356040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00600E00E006\n\t00650008720700608002000E200000000000000000FF3CF30009000000219818018C70E290D9818010A00B60240106222046\n\t02C22825000000603E0160002A601600609610641640618618602E04609040200618E000010002000000000000000000FFDE\n\tCC00000000000180102180100C8410458010000C000800361020961541000800000060260C61001461062A60060060260060\n\t06006056086000000006416000000402000000000000000000FF12F60009000000000200000400100A200002000001001200\n\tC808052008008015000004008012008000000824004000802000000800000002000A0800000000000100160000000000000000b56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AE030C062AC0\n\t00200AA809C0060060020066A648241618606641622648402410602804418631E0042042AA000000000000000000FFC1C620\n\t00000000010409018080480010008058000000002006C0222600400004000044400610680080601601208641640E08601622\n\t6006106C000A6006006CC4844002000000000000000000FF389100000000002180383384500489384B841000000000400608\n\tE10C00600011000000600624E00000600642024E04610645610601450C254000416236126008090006000000000000000000\n\tFFD9470000000000418218018811008098018410C4000020400642620400642840000022610400621040F00600312700F00700756040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFB26A000000\n\t0001559111559550C495595581300200004085565024C6555001550D5055600644E0048062C65565260A604E406456556556\n\t55600035651651684CC54556000000000000000000FF3FDA0000000000A90A98C98A30208018A58ABCAA00012AA2AF00108E\n\t2AC0002A0AA82040060A500000710E02010724E28604622E04C48C20C24008222E006D24A4C2AE000000000000000000FFC0\n\t254000000000010028018010108010018A1C4800018A000702900600480080000000400600600000600600000E40E2860AE0\n\t060060060040C8002046046504104006000000000000000000FF97A700000020028F28D8058900800250808892AA00002AA200f56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100040040041\n\t4055654654680E886006000000000000000000FF1F17000000200201811801801905801801A812000000C0400612C8060060\n\t000008000060060068000060860061068868860060060040040040080068168164C6016006000000000000000000FF622400\n\t00004004ABCC30AB8AB0088AB0AB80310200000842AE2042162AE8002A82A82AE0063270000060162AE02600600608E3262A\n\tC2AC2AF0000040060060062262AE000000000000000000FF3E9A000800200201801801801114949011A0100100000000064A\n\t00460050000080010C600641600000604611704600700E906086086026024008217007446014104006000000000000000000000d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (421620600000\n\t00002360060840002AE0064860460260660863200440440C45000040060062262862AE000000000000000000FF21F5000000\n\t000005905001942000045800081800000004C006000026046000000000016346204484006086056296086006006000004514\n\t00400000E01600E10E04E006000000000000000000FFB3CB00000000000184080180188D901803043801000000400628C096\n\t10E00000000010600E02E02000644E40604640E28E4561082D40444542B0326546546006006006000000000000000000FF40\n\tE300000000000182000180004000180004995100000540068020D600600000000080600610E000006A56006A1625624F2261008d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F50000000018\n\tAA0018AB8CD8498AB8818AB851000028C2AE0B42AE2AE0020060002AE2AE2AC3002AE00E20400E20E40E32E22E2AE2AE2AC0\n\t082062C62C62AE22E2AE000000000000000000FF2E9100000000191414B95584580380C1318859550000044D565205464960\n\t020040004C605624444455603602C216436416456446416514404040006506506436496556000000000000000000FF4C2480\n\t0000001800141801801805801803801885000000400600400600600200600000600600401000604605442604602600608600\n\t6006004100056006006006106006000000000000000000FFCF9E0000000000A98098AB8099219098A90098AA00002842AE02004d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000600425608\n\t654654600410C026000000000000000000FFB256000000001800009000801D45000809000021000005400604C00200600000\n\t680000600600648000600681429600600600600000000400608001601600E116006006000000000000000000FF246F000000\n\t0018AA0350AA8239018AB8710AA0030000244AAE4042AA2AE0000060002AE2AE2AC0002AE5063841061061260862202A82AE\n\t2AC44032601601622622628E000000000000000000FF92900008000018200018018890298200038318010000494006012006\n\t02600200400000628609410000628608408608608610600E08600608C0084AE04E04E106026006000000000000000000FF9200cd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (106004007100\n\t04600701400804650640604630608E026006006214084008106406006004014006000000000000000000FFFE2D8008000031\n\t88483883801C2590A80182188005200B308E4000260060040474180269648040000262072048160064468164064760066140\n\t0008620610622C004006000000000000000000FFF9A3000000003810141482801821C0A881020405800000180E0020070060\n\t0000600100600E006004006006006206006006286010080080026000004006207454004006000000000000000000FFAC0F00\n\t0800001800503000911011000903000111800008000650000200600000600000680680400A00654E04704652E48F45611000002d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000180008\n\t180300300182288180800302202072260160062860A600620808611E00408000000608400610E0860A622611611209421000\n\t4226206000000006000000000000000000FF3968800000001000001C0092182348002104194980000A008600220600620420\n\t6100406006A060082860C640620612601600600640600420E05030E00600E084004100108000000000000000FF056C880000\n\t001000021800821813120103002204028081080648000688600402728080600600E0100060860042362062D62B6416206406\n\t126000006006506804014000000000000000000000FFF01D880000001000605801841009040805803900804114010609004600ad6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (548400320540\n\t540120020026000000000000000000FFF9B10000000018001018001030050028090000038420401446012006486046006480\n\t02200E20210900002620620602E0060064062060001060C0084006416100020100080000000000000000FF65FB0000000018\n\t000059440418919109410A2031910014808C1025360165160460404800260060004100060260060860961460260161060160\n\t000064C6086000000000000000000000000000FF050B0000000018000038A10010C9848809892101888000E00E08E0AE00E0\n\t0E42603002602600600010810612600600600600600600E080406490414086086060020006010000000000000000FFAB8A00006d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000000000\n\t004C0289080280000080080480080000008408000440000048048084000000000000000000000000FFF1B60000000A900008\n\tC0AE008812820884140800800048101242E2AA2AA2282AA00005E2724125C133A5020021021221020A222222210210202000\n\tA01201220228628A000000000000000000FFDECD000000000000002000023001000002080044000000000640000400000000\n\t600004000C288000006000500290000000000010010140000008000010008008008006000000000000000000FF6FED800000\n\t0020000400001000C811203005211000002294B00800000001000060003001000402400805480300405084A841010010020800ed6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001000021441\n\t04408440D001000480000004D000044000004014000000004C000C0001000040900420040020040080080020020040010000\n\t000104104000000000000000000000FFC2EE800000155800155925D55D558131558058A3800052FD563042CF556554556000\n\t55455600E00144E036556216436016436456446026556008556506506454554556000000000000000000FF74280000000CA8\n\t00088C888908208C08A880A82A80001002C20922AA2AA2A22AA00028308200200022200B22A00A20A40A30A22A22A20A20A2\n\t102A22C22C222A22A2AA000000000000000000FF43060880000000000010080000004800000A840000000040000100000000001d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002000008004\n\t28000000000000000000000000FFFF0A01000000000000000440040004800015211000000800005201408000000000000280\n\t000002110084480000404284A8530108110500000208000540540100088040000000000000000000FF670500000000000000\n\t0030000000104000000024000000080000800800000800000010100015000000008000029008000000000000000800002000\n\t0010008010000000000000000000000000FF09978800000AA8000AA8808AA8AA8408AA800810800022A2AA043A022AA2A22A\n\tA0002032AA2020802A20022AA0420020420023223221222AA0002AA00200222222228A000000000000000000FF372C800800009d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001587000412\n\t0000000040A008000000000000008002982B0800800124004010000800000000000000000000FFF4B2000000000080904900\n\t8028128A0C00D008C88000102202002802A8200200224250000208200040200000200201230A00200A00280200200000302A\n\t002002002002000000000000000000FF4DDB0000400000220000040800200002020080020041020088048020040000000000\n\t020000000082000020000000000000000000000010000880000880000000000000000000000000000000FF51260000080001\n\t0400020034000010A08010200000004581200407801008810000080080000100000000000000000000000000000000200A80005d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002043000100\n\t0020120021024001004001400140000000000010008400008408000000004000000000000000000002882C00000000240008\n\t00000000000000000000000000FF1C1D000020050204802880C489A081881A90C8208081092002842D029228020030020000\n\t02002000002000802802002002002002002803003000803003802402003802000000000000000000FF88A000005000012388\n\t3881C0303594B083C8B92B802010E48E02400442688400644450000600608040600080600601651600601700604612608020\n\t602E006026806006000000000000000000FF8B2700200002820100040510100060100102260B000104406081C5441040040000dd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600200600400\n\t4000000000000000000000FFD638000000000000000000000000000000000000000000000000000000000000600000000000\n\t0000000000000000000000000000000000000000000000000000000006000000000000000000FFD61A000000000000001000\n\t2000014002000000000000800000000000001000006000800000804800004000800004004004004000000000800800000800\n\t001004004806000000000000000000FFCEA1000000000080A00A00080820880802240A128000120002002002040004802006\n\t00000200A000002000002002002002002002002002002000002000804002802002000000000000000000FF79B30040400000003d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000A6000008\n\t00350080490A830220400006006006386808085000006006006006000000000000000000FF65B60000000000218118010010\n\t09000985A80A0B800000600E80620000004680600088000602000000220000600280200A0028060268860061000060104060\n\t06006006000000000000000000FFB2B0010000000041882A14014211800A010409158000C5400E422A400440860000081001\n\t461402A01023110174A654E00E4B6246A0E086106820926222086104006800000000000000000000FF40D300000000008180\n\t18000A000102280108880180000040260020000040060800420000060000100020004060160062260060060260064164100000bd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2C83800E0900\n\t96018018B180014472042A000600600608608620880620004100252000409000800002000604600E08700100610600600600\n\t4006000000000000000000FF24A1000000000041840A0C880811821011002001800002420454882200400690001621001621\n\t00200020200360000020020220A680680E016400804102006406006800000000000000000000FF6962000000000001808804\n\t892801805C03029201800000C00602200200400610004F00000608032008309040E3423120022AB44641600600E2C004744A\n\tD06102006000000000000000000000FFB099008000404081882809025001120841A108918040A260362061200258A6006100007d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (044124006006\n\t000000000000000000FF2974000000420021B01810810401000101084C81880000C28500050600600E006004000206040000\n\t10200000408602600E086096006408006000046040814044004006000000000000000000FF7BC1000000000201A21C088880\n\t03800801000801800000400E802806806006006026000C8600000600200000E0062060260060060060000062002060000058\n\t00006006000000000000000000FF529601800000444180288180C9839491D1875CA18040A1E80501114681E0060060360002\n\t960100189820181C4008380020418146026006017000A04006006406006006000000000000000000FF52610000000000018000fd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (163100000020\n\t4008D826406286427B01008006004020144203804002006006000000000000000000FFF554000000420001904811C0342100\n\t8905901881882020700604B0030840100060040000060002080060802040060060A600E0088802064B4000044A420AD00200\n\t6006000000000000000000FF0961000000000603800800803A41A01041400E11800002400582C00608600200628400000E01\n\t030000200010440E00600640E00648610004E43000400A084004006006000000000000000000FFEBF3000040000021874A04\n\t80980181123D0708098040C0401C00428607E80200600400080662809008270049628612614F287087006040506B8801440200036040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (845C51A03809\n\tB2B953A00000E840884806886006006086800C0E00800000684008E026206504040206008000004040805002006004006006\n\t000000000000000000FFAC65000000002011800A93D83801801781801883800080E824084686087804606084000006040000\n\t00200000401E006006006000000006004800004860004086004006000000000000000000FF482B00004002000D810A05801A\n\t0180902183FA2180000565040010060060040065040214160200040020000340169860060860204009568040400148100051\n\t06006006000000000000000000FF5B9B000000408101800849C41051A0400DD018118080106404044003014008006004010200836040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060060000\n\t00000000000000FF38A700000000180180180180180100080080180180000040000020060060040060060000060000000060\n\t00006006006004000006000000004000004002004006004006000000000000000000FFA50C000000001801801801C0180140\n\t0800A01801800000400080000680700600600680100600000000600000600700600480000680080080400080400200600600\n\t6006000000000000000000FFE81E0000000318818018C3801801811A25801C01A080106C0002510600E00C00600603000628\n\t0004006800026006086004280946000000004000124402004086004006000000000000000000FFF5BE000000003801801C0100436040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030400608000\n\t6006006106000946006006806000006002007006006006000000000000000000FFA314000000001805878B0F97E8141B00C2\n\t8700E180000240000000025048140060A6A28812C00000086000006C06406C5E02061E056066016000006002006004006006\n\t000000000000000000FFED9C008000001801800801C00801C4121000450D8C808CE009424D06036444B4E8CE410002108000\n\t14613104601610E004221086206006824880005002006006006006000000000000000000FF58CE0000000018018008118008\n\t41801103100001800000604000C0060061060060060C0402000000006000206006006004100006006006404000004002006000c36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20C010008003\n\t4000010060040C42030970068000360202560002010060000060070060040000068070070042000050240060060060000000\n\t00000000000000FF8B94000000001001801901C0180088980894580A01208C684D0048B22048330270060010060001000060\n\t808060060060860000A6006006006022006006007004006006000000000000000000FFCF9D000000001001801A01C8180080\n\t1C20889A0A0A8008E82427C68232C2AA2EE00E0C020E2800000060A022700E08E02408088602E00622C4C000405600700600\n\t6006000000000000000000FF72CD000000001801800B0180082029008894434B8140127050B02152214036006856000C528000236040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6A8000000000\n\t0000000000FF2192000000001881901001801001322804808085000080E128C0212629430F006C950408A208020044400000\n\tE2062070060800441262860070000274540860A6096006000000000000000000FFD187000000001801801001801401000A00\n\t8000010000006000002806004006006004000002000000004000006006006004000004806006004000004004006006006006\n\t000000000000000000FF59B1010000001005800901C00854811290805800000000701020F003107006000006000006010000\n\t846010006406C0640640080640680680600000680C007006006000000000000000000000FF5E1F000000001601E00A01800C00a36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (108000080000\n\t1080004805204A001010021250000094640418E106000000000000000000FFEFF20000003000002440242224540440640001\n\t0400004100305209000801000061102001C02804000100000100004400080000001001800804020002084863200462860000\n\t00000000000000FF13C500000000190180220380000808008080000980000066000CA2806248024004040202061000004E42\n\t0000602602608600000400624645E00006604400600C006000000000000000000000FFB708000000001C1182A0D58D220A21\n\t0350B422510000946A0114A202824002800824400A0AA10808894400CA692692E916020C04A06826B16A80806884806C0E8000636040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (ACA0C10D0280\n\t012030CB44220220300340B0020012230034010CA0010030032A34A200108320344333341344AC039030830C300200000000\n\t0000000000FF5DD40000000412802A04900402025300022A0000000080080081080084080C810A00000400800800800400D6\n\t8D00A80D40800A00800C00A00800811484000810800850000000000000000000FF803B000000400000A00440C90000808900\n\t80280080001C200E00700280000000200C0100020020022020002022820020020200022020220020C0003032002082002002\n\t000000000000000000FFE33D00000000404801810850C1000024081182A300000281C42004701082800060A010102C01E20800e36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF399E000000000A00A00A00C30A8AB00A04A008008000002A28C4210281291280288A000802802800803000902842\n\tC52D52090802802812802842802052812042C02802000000000000000000FF222F0000000014012010432032410082492282\n\t00000103090500C8148C4004800A24000000800820800000A20A80900800C409009088008108088A00840009008288400000\n\t00000000000000FFFA5D000000001841805885801955321805081801800012E20408C14C12688600628E0888861160004064\n\t0055650600600620020610610E00604008602C2262160060D6000000000000000000FFE0650000000C4D00828A30954800C000136040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002A82002803\n\t002482A02A82282A80082A82A82A90302A82A8000000000000000000FFBDAD00000040035435431030428832034C31015400\n\t00CB0800C50450CC0CC0D10C41000D50D50840D508008C0A80D08C20450D40D40CD0C508508A1550D51440810D5000000000\n\t0000000000FFAC8B00000020040048000041040040A000454200000100100100080010900100100180100100100128000100\n\t1149031000001011001101001041001801000C81001000000000000000000000FFB54C0000000000AA0AA08C080000022080\n\t0820AA0000A801500802202102202A80100002A82A80002A80000080580400000002282202A03A00002082002A021818028800936040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (88C000800000\n\t200220A08220A09200201200200200201008200200210201211209000A002002002010002042002012002042000000000000\n\t000000FF2D400000000000AA0002900800AA0C00AA0002AA00002A82A80103510402502C82200002A82A80000000002AA20A\n\t2022503002202202A02A80002A82002A88802A8288000000000000000000FFBBB000000000000000004005004200C0000424\n\t0000000002001008800000080400800000000000000000002080000001080800100080000000002080000001002200000000\n\t00000000000000FFB0250000000000AA0324A20A20AA0802AA0804AA00002A82A84C12002002802882A80002A82A8008028000536040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF66F2000000410C20C40C00D20C12D00C00C50C02800108B10113310308301240340300B0A31028000830020020821420\n\t2231000A112022002888403003003002502002000000000000000000FFE34E00000002180D89581381182180188B8810218B\n\t4042444600604604600601612C00400600E00000630608600620E10600030600620642600010611454600400600600000000\n\t0000000000FFFC3F0000000014002C405225520021420022100100010048050C482C920840840904804800804800A4800480\n\t0820920820020900910810800820800894800444800800000000000000000000FFBCE900000000080080880080080084080000d36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000020012008\n\t000000001000028800000008E000106106000000000000000000FFE42200000000800000300008A0B00010910C1024048012\n\t00000200800040040162500000040160000002800800003000002884000000C0440110280088526000286006000000000000\n\t000000FF424700000002106288880A80090088886291080000602022A045405200240A00208220A002084100082002802D82\n\t9224A20000C2092002002000102006002006002002000000000000000000FFED6F0000004004084204004245024104404094\n\t0008010090050890210B90002010054050A1000000001004000000008618000008008318000000001061019180000000000000336040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018800004004\n\t20210E00C500012006426006000B0009624710700720602608002600E006006C400860061040000860820000000000000000\n\t00FFB2FF0000000018011A10A180984008F00980010506001002000064060440E40C000600401602100000621640646601E0\n\t1E0000060060960271300060A6000000006000000000000000000000FF845800000000180100100102188410182115002100\n\tA002841002E04628400810440600400604100000600600610610648600000600610604700000614601400000000400000000\n\t0000000000FF729D0000000000000000000400420201000200C211000A801000048052800804E4002400080004001100284800b36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t41B20000002890AB8898AB8898A1A8C0852000010000002AAA08A01E2041D42C82240062AE2A80003268060661067C640400\n\t03AE22E2AC01C020644A062AE0042A8288000000000000000000FF333700000000500180180080381580400310C015000000\n\t2000C4250604C21002481480600600084000E00621644600620E000006006006106800026046002414006004000000000000\n\t000000FFE2D10000000418010430018218000410498201218000534004002046084044006086006006000000084006086096\n\t0560C400000610600424401011408E0000C0000026000000000000000000FF23FD0000000018410210A1809800049109800000736040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006036000016\n\t016116006840016010006504006046000000000000000000FF602B00000055595591015510594A149943B221550000551310\n\t52650655551251255300243255000C55700613608600655600055654E4D65560445565405525545505320000000000000000\n\t00FF8C3A0000000CB0AB8CC8AB8A9895880089A800CB00000422AB1220862A420028F22C0062AF2A8020226006D0EA3600E0\n\t840002262A62242A40080852A72AF02C2AE28E000000000000000000FFF0B200000000100180280080980180201100000100\n\t0000204300A02E00482002300400600600000000600640621650E00600000600600600601000700E0020040000020000000000f36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000042849241\n\t56004052002806006310800814006006216206246004000000108014004824004002002006000002000000000000000000FF\n\tB75100000020180183300180180180D8D5B05005800000681400600600010604600200202000000000600690688608600400\n\t0006006004004008004800806806006006000000000000000000FF0E040000000AB8AB8C10AB0E1889C8180101108980002A\n\tE02420E2062ACA0228A2AA0021002A90042AE00602606E84E2AC0002AE2262A42AD0042AC2A82AA2AE2A82AA000000000000\n\t000000FF988A000000401801800001805840031841055001000051100041642601500600608200200200080000E006006007000b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF4F96\n\t0000000898A98880198AB8D38018918AA08D80002060042242AE0062A628E2362062402A80000062AE186006086044000220\n\t22000400400000C2222AE3060CE28E000000000000000000FFC57000000000580584214500182181180B8000018000006404\n\t00400615401604201611600000000405600601611604630400010011000410400404408200204E0200020000000000000000\n\t00FF5B8600000004180180000080181012382180004580000B40D409400640400600608604615000000028600642644640E0\n\t4C0000080004D424C000484012006106406046000000000000000000FF699A00000000180180000001384202180183004180008b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t8000C004004086000026000000000000000000000000FFEDD50000000AA0AB8C088D8AB8918CB8AB0090AB00002062103202\n\tAE31600608C22622E2A02A80002AA2A810E0CE22E2AE0002A02A02A82AC0002AC2AE2AE22E2CE2AC000000000000000000FF\n\tE67300000011411591114595590010D84195510980004D650044455640654E55054243650AD500045525504363164D600E00\n\t055055045054400454C44E550416510550000000000000000000FF3E4200000000000180580180180180180188100180000D\n\t6100014006002156044106006010000000002000246406106006000010008000004000004006006006006004000000000000004b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000400400440\n\t400E40400608C0160000000020000A644640E00600000600E006006000006002006894806024000000000000000000FF9C65\n\t00000000000182103080000102080183020180000B00C40AC00615250204410E004007000005002000217116047006800106\n\t10600600400400400A400006440004000000000000000000FFF6E50000000AA0AB8918408AA0C78888AB8440AB800020024C\n\t2042AE04642648C2363242A42A80002AA2A80060060862AE00022E2262AE2AC0002AC2A20AE32608E28C0000000000000000\n\t00FF14FA0000000400218240018018020218830010410000006028092006136002000006086003000004002000006046006300cb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFDA0C0000\n\t00000081810C2180184100B800831608804040614802408C2540100040060431061400000820400460060062000100060060\n\t8600E010006000011014000004000000000000000000FFC2480000000104C9C41905827A21041890801D00940015E4801040\n\t0420C00000440618301700000108202003E80690EA10808106006016444488104280006824806004000000000000000000FF\n\t94C40000020006098010008400011000C41000400080001000006004004082204006004A070000840060082862868560860A\n\t0206456406006104006502040044400004000000000000000000FF7F1E000000000001C0D882800249002000102000000000002b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000600602644\n\t6000006086406020006184000000000000000000FFEBA8000000010021841801021803045811081871052000623008211400\n\t410400C0860004068401280020081060A600E2B014000E006186484280104006010000000004000000000000000000FF4AAB\n\t000010000401802C08800020020830840082808000109002A3262AE2080040260000870A0400012300016206006002140006\n\t206006226030006010210804086204000000000000000000FFDC890000020000218098C28000000908229480808820340220\n\t14000604200C404406022896080000002008206286146102000506456416054400004000046014200004000000000000000000ab6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (290080000000\n\t0060000401512200000000002A0440408130000000008080480000480100006100006006000000000000000000FFCC5D0000\n\t100000018030000000010008400C0020004000044024200410000001408600080700200000A11000E2060062460A00062061\n\t2610650000600E006020100004000000000000000000FFAB760000000000418018020500431448880001000D000881081020\n\tC442C5540040260001160A00000024000060D615608620000E006006006048006086010000006404000000000000000000FF\n\t1AE800000000000180181300980109B8810018050A0008E0002124040040A000400600000E00045000200000600E0A600220006b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (169A00000000\n\t000000A00000000800022840800000000080C40950000B10000000A000100100000020100010004000000000001000800000\n\t0000000080000000000000000000000000000000FF48CF0000000000AA82888A0EE90008088090309080002202AA02220028\n\t02A22AA2AA2428028020002AA0000020020820020002222222320320000422220AA2262AA2AA000000000000000000FF777B\n\t000000000000104000000112048004088010000009000400005004801400400408C406116000004000010110040404000110\n\t100008008000030010406008006004000000000000000000FF80DE000000000000000020000020004028040022000000000000eb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (22A2222AA000\n\t2AA2220AA22208A0AA000000000000000000FFA16100000000000121204321000120844140D0430000044004154905095000\n\t0000005090310000000010000404001000480000000000000400001000100000C4220000000000000000000000FF46140000\n\t0000015592192D9258C195390312190B0000547414424556C074AE55740F54754F55600104E0004363164D75460005465465\n\t565560005564563564D4536556000000000000000000FF7A650000000000AAAC0888C8082ACA288C820080800030A2AA2022\n\t2A2222AA2AA2AA0022823320002AA00030A0CA22A2820002AA2AA2A228200020A2A22AA20A08A2AA000000000000000000FF001b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000008\n\t20C30400800000000000040800000001000000000008020000400001000008000000000000000000000000FF1CAB00000000\n\t020009200A03205403004000204800001284A00280005010202011000010110000002400002A044040891000000000008800\n\t0000000010200110020400000000000000000000FFCAF4000000000000000000000080004014010004000000081000000004\n\t0508000420810100000002810000010110040040000110100000000002000100000000400000000000000000000000FFCF74\n\t0000000004AA8208A08908048808808A48C080002020002822AA00A0020AA00A2B22222AA000182000002002082212000222009b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01C010001081\n\t01100116800100010155153900000008005558084500050000010000000440000040040404102C48000008000A0850880000\n\t020480028218208000000000000000000000FFF2F3094094140840840800810800800C0CA04C400120800200002522229143\n\t00000028220240200000B4832020CA20A21610200211000211200000A006842002002240000000000000000000FFAB040002\n\t000000001086040000800102A00C808004000000000880000008000008000001100280020000008A0C000200400400018008\n\t40000412000200800000000000000000000000000000FF8DD40002000020000000000A010004010015400A00000800002200005b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020020000020\n\t02802002802000000000000000000000FF73CD00800000000400400000800000000020020000000000004008080000000008\n\t00000000000000004801000001280000000000120000000000020100048208208000000000000000000000FF05E900000600\n\t0922802800840800800C22844852800100080020020200100200006041240200200000200208300200280200280200000290\n\t200041B002003003002000000000000000000000FF2F231001041438418C1803811901009833003043032108020000634600\n\t0144000020D2648F40E00000F506C86146C1643612600611000615620800E006046006006440000000000000000000FF3C9400db6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000620000010\n\t60A60060000060560161060B6026206406010006006400100006006084000030000000000000000000FF4803000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000006000006000000000000000000000FF02390000000000000000000000000014000000010000800000000804001000\n\t001001004004000000000800004000000000004004000000000000005000006804006000000000000000000000FF944E0000\n\t000008208008008008808408A2A88C0580000000000042020000020000000020020020000020060A28020020028020020000003b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04001801809A\n\t29809941081901201020004080004008610208182380800031600E0460000168070002850A60262102020000062062104044\n\t46220006200028000000000000000000FF34C8000000001801801A11A11A21201A0120100000000000201060020000420401\n\t008860B6006000006E06022C4600628E002002008C06066000000106006086006000000000000000000000FFCB4E04000000\n\t1C21811821822020101840100000000090805000202E10000601000042600602600244E00652600600748E14700600000740\n\tE05280444EC4040E406000000000000000000000FFA7F800000000180180180180001000100004005000000000000000060000bb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600040404664\n\t6006806000000000000000000000FF7E20000000101E21805801801CA0801000C0A801000100104100490000100E00000001\n\t6047046080006006000006006006110000000106806008086406008805000000000000000000000000FFBD28000000081813\n\t885C85A00000E01408900885000000000000A0000004120000100061060060810460A7882405006806002880000006886000\n\t084006036006000000000000000000000000FF6FDB040000001C41801801824410801020940A100000108008000050000002\n\t44008004600604600045602E5120270160060A2002001206016029086556000416006000000000000000000000FF8B1D0000007b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010909006206\n\t1861044060C60064440A610E006806020507010054256086000106000000000000000000000000FF121B0002000018058018\n\t0180000002D620000000020000800000000C00000600005100640600600080628601700682624E1060060400060000000049\n\t07006004006000000000000000000000FF2C2C000200001813801901808000005800400000002000000005080C0002060000\n\t00006086106004046046006226006006006106000006800004000806000806000000000000000000000000FFC65900000400\n\t1821901C05809C00C6391090AD0500011988008260080010060600101066268860000161071000241861860806000000861000fb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (188590182180\n\t18491418233094004000400010024104001016021000106306007001C06046086044006006C07106000040C0621000400600\n\t6006007C00000000000000000000FFE898000040001801D01C41801801289C01001000200001042100C10400000E0480A080\n\t600600608400620710608C2163460860060800000160240C8006001006000000000000000000000000FFBE9D0000000018C1\n\t889A01800001881883A01C00000000020001008000000604000000400400F00000600610611431600620600608000E000000\n\t504006006006006000000000000000000000FF64280000400118B980D84180001580309B971860020010014106000000085600076040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006800004\n\t000028000000000000000000FF66DC0000C02D1131811A49801A01901A41885911280004681012600404100684E00054E200\n\t4044022020460C482601600640640600080640024A106006007006006200000000000000000000FFC9AD0000000818058098\n\t09801841A01A01C13800000000000088500000100400006082E00E00620001F00600600400F0060060060000000060200840\n\t06047004006000000000000000000000FFBBE940000003182DE25801821815841841911AA808001201002040300200660080\n\t002060062160044060478364C40060A7C26206000511006094006006821106000028000000000000000000FFAB3B2081420100876040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060002140\n\t0001610608000608600E006016000000406000114006006004006000000000000000000000FFB07200000000000180180180\n\t1801801001001801000000600000200400000600600000600000400400600600400600600600600600000600000400600600\n\t0006000000000000000000000000FF89B7000000001001801801801801801801201801200000600100200600000600600080\n\t6000004000007007005006006007006006001006800000006006006002006000000000000000000000FF50D0010002200001\n\tD21A01821C09841A05801A2100002068004068A400003700600000611000400400200600408600692604610600002600010400476040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (811801801801\n\t21182A104B120000A00010446934400D4E004440116250006116A4640F002916006D568168060000500062AE804806000002\n\t000800000000000000000000FFB9350000000A00018238018891C320119A020AA80000800000002806000006004060006010\n\t08700080E00648090600680642600600051800600008C006006006006800000000000000000000FFFBB00200005418058058\n\t41885201041A01C2C8201400082410056054101356114408C4EC2010402612700604A4464260870D70060480000962068048\n\t06000006000000000000000000000000FFDEC30000000010018A180184981510182388088A0000452000006504000006004000c76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000040060\n\t00000000000000000000FFFB16000000001801E01E018050812018A2D008000000000000C8E4264004820060008860400040\n\t0000640600600600600600600600004E006028005006806006000000000000000000000000FF4E2400000000001180980180\n\t14018096108038AB800020400802609400802800643100E40808693102480E00C08E20754E00E08700000600650000E00600\n\t0006000000000000000000000000FFD3A0000000001001801801805D01A21920C098418A0028420013EE2C09028A88E21842\n\tE22810C0600A608703C2A66A608E086106028A0628E000016006806006006000000000000000000000FF48D500000020081300276040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60A0C3680082\n\t6C94C16AC7086896C06836200886806800C04A86800A84886000000000000000000000FFA4D9000090005909901809801A01\n\t8092052C8009000040E01000601400011408600140F2080060009060240C6006006A4614E2860000060C620004E806106036\n\t026000000000000000000000FF86560000000012018018018018018010010000010000006000806004000806006000006000\n\t004000006004804007806006006006000006806000006006000006000000000000000000000000FF8438040000000C079018\n\t418450511018009058040000050010006904001041006000606000406000206007406006006006416017000906806400004000a76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400494020430\n\t20000012000020010861C1000008000800003B00404001010000800000801001A00A00000001901300100180000867880760\n\t00000000000000000000FFFEFC0000000426002080001000080082080A410000014000000200000001984000000003A82280\n\t00000100008000400200300000000000000000000780006010086000000000000000000000FF6BBF00001010184380190D80\n\t51411051941008080000150000046000000C2600600000E4000060000060041262060060060461C600000600600062400604\n\t6026100000000000000000000000FF873B0000402C9825829C81AC9C95205928202AA40000800000A2EA400000248060008A00676040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620E00E00000\n\t0000000000000000FF57AC000008704A54A22E22C14C12D00E8ACC0D48000009208943310200040320200011224140B00100\n\t3003113103203A0330B08200108310B0090032531031030A2000000000000000000000FFD68C000028400404000280290090\n\t20024240A2250000000000800E00000000004000804800800C00001220810900880C00C18820200800880A00800800800800\n\t800000000000000000000000FF321A0000800A4828C608008208040008008508C0000000801010206C000800000001042000\n\t0120000A200A68202200200A00221A000002002000002052102002002000000000000000000000FFCEEC000000008090484000e76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A80002A8AA8\n\t0800002A82A80881400002A83A00020202A84A80200A8000000000000000000000FF2512000000000A00A00800A20A00B00C\n\t00800A008000802800A0A802000412802000902800002A80802002852D0300280280284A8008028028808128028024128020\n\t00000000000000000000FF131800000000000100100120822322A04503420100000040008A080C0000A40040008548D10008\n\t00000000C04849004000C40C80000800810C00A80800C00880C00000000000000000000000FF226E00000002180180190192\n\t194184582120B805800042600010644600088C00600002610000650080688620400608608604605600000E0060004161060400176040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (40C00AA4820A\n\t202200000000002402800002200000002A82A82A80002A82A82282A82A82A82202400002282300002882A80A82A828800000\n\t0000000000000000FF457F00000055415415455410032030034C5523540000800800810C500002D0800000910910D50800D5\n\t15508108C8D50D50A00800800CC0C50800D30D50950110D30000000000000000000000FFA628000C00600400000200440410\n\t4000080104900001001001091050001101001001001001801001001001001000001001001101001101081001041001401801\n\t020000000000000000000000FFBD700008000AA0AA0AA0AA0920880000882800AA00000000004002A000080000000020020000976040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A00000000000\n\t000000000000FF868A0000000008008008008108048008008408048000002002042002000102002000002002002280002002\n\t05200200200204212A002002002080012002002002022000000000000000000000FF14430000000AA0AA4AA4AA0900840AA2\n\tC068800000000000002802080002100000002A82A82A85022A82A83802AB2A82AA39A2120002A02A85000002AA2A82A80880\n\t00000000000000000000FF089C00080000040040000044400A03400000000000000000001401000008000000004402400002\n\t820000004A04000000000A8408000008000280000000001220000000000000000000000000FF197C0000000AA0AA0AA0AA0800576040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (090010050000\n\t00000000008081008048641020000028781474000000000000000000000000FFBE98400400408C20C00C40C00C08C04C20C0\n\t0C20100130250B00900201100B0820010030031530090034032020C304201251200301201211304800200200300200200000\n\t0000000000000000FF8D910000200058098218018018A193110984100182C004600610600600004401610000E00E40600000\n\t600608400630634600648608628600640000602E046004006000000000000000000000FF991A000200201201201201223248\n\t2010530033490000800800814940000854804800801001004802800804804800804800800800804810800C02AA080080080400d76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080090008084\n\t00200400401000000D0408288420000100400000006000408040000000080010000000100000000410406000016000000000\n\t000000000000FFED4B0000000100400000000000810C20800000400000220200010004008004080080000010080000006400\n\t480020C40200300000100520130410000000006008006000000000000000000000FF12E00000200029188608028008248008\n\t0012081012A010A08208010200002A00800000240236A5000021020028821928AA802E024020020020005431020227021021\n\t00400000000000000000FFBCC7400C005804004004244004084084284004010801090009005000001001004061009001001000376040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FFA73100000000182180980180180114484382103100000860160060220000005060100102044062A00060860070\n\t1610700700700E2060060065000A5006006286086080200000000000000000FFB75A00080000182184982180198182293312\n\t0124028024600E16202E2004B00064880080040060220060064161CE0262263065860060060062A200441640C00421600000\n\t0000000000000000FF7C630000000018898018418038030008010080000CC040602600008E4A812201612000008412600000\n\t6006006006036226206006006006086020404086012004400000000000000000000000FF844B00080000000000000000400000b76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600608C00600\n\t62062A630600600E016200006506400012000000000000000000000000FF3F5D2000000018AB8AB8AB91D8859000A10988C4\n\t80003040042AA8100000142360002AE0061162808863A64461D62AE1661064160062AE2A64003664760AAC42088000000000\n\t000000000000FFADB2000000049801801801801853880001000C22000004E006000448000304806000006006406800416806\n\t01602600608E2AE22600600600690008610E404142006000000000000000000000FF73AF00000008380180180194380104A8\n\t15845011000010600600610200005210E0000000040AE0000460162C441600620600608E006006016200014206000416240000776040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (410002080000\n\t050005001504000106084000006006406D001270060048060068060469460061100968000050060060064060000000000000\n\t00000000FFED6A40000010595595595595595595490310414C00004CE007429404000546554000556006556284C075564464\n\t0E5560B600E04E0064C0446104554056151246330000000000000000000000FF70080000000A58AB8AB8AB8218B182C88B8A\n\t488180002040042AA0400002262260002AE80602600021622E0944062AE2174160060062262260802160862AE08A0AE00000\n\t0000000000000000FF4AA700000002980180180180180100082980080180000040048800D000000F0060008060060060000A00f76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFA9D90000000C1801801801801801000041821435000003600648400400001600600000600600680401480608141600\n\t7236286206006006000A04004AA60004C6000000000000000000000000FFF55F00000000D80180180180180180180B08D800\n\t00001000040048000000860040000060060060000C6006004086006086806156006008006100006016406014046000000000\n\t000000000000FFFBDB0000000018AB8AB8AB8AB8AB8AA881051C80000020000482C2A80002262AC0012AE8062AF2862162AE\n\t22E1662AE00602E8060062A03AF0062AE0060A8104288000000000000000000000FF39070008000118018018018018010008000f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006206006026\n\t006116006000006000004006004004004000000000000000000000FFF0B30000000AB8AB8AB8AB8AB8038418B18A58490000\n\t30400440422000000622E0002262262AE0002AE2AE1004062AE0C600608E2AE2262200003C60064AE20608E0000000000000\n\t00000000FF5E470000000018018018018018018000038018A300000440342541000005061060000060160060040040064400\n\t160060260D600600600600000400601600004E400000000000000000000000FFD1810000000018018018018019298CD80980\n\tB001000008C28408401400003600600009610600600000600610852600641620624600608E0900000544A620610604600000008f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (189500000040\n\t0410600400028E10E00600E0060060000000022360260064861060060060080060000160460000B402000000000000000000\n\t0000FF9A410000008AB0AB0AB8AB8AA8AB8098AB09588100002862AE2862860002262AE0062A62AE2AE0002AE2AA2AE10E2A\n\tE40E22E2262AE2A82AE0002AC2CE2AC2AC2CC000000000000000000000FF7679000000954154155955955128100101931801\n\t000025453404E5540000464460065465565560045505500060965560164564CE556540556004406516150404510000000000\n\t000000000000FF3DBD8000008010010018018018018458018218510000056006016054000006006006016006006000006000004f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF802E000800000A0080180180100114100002900A000032E006082126000016004004906006806000006000086427006456\n\t486446006086080000004526405094404000000000000000000000FF67D5000000801001001C01801001415001801C400000\n\t00600604300400000600400400F0060060008000008160960070060560060060160100000008160040040240000000000000\n\t00000000FF4ED00000008AB0AB0AB8AB8AB8AB9018AB88388400000062AE24A20C0003B62AC0042262AE2AE0002AE2A82260\n\t462AE18610608E2AE2262200002AC0060AC22408C000000000000000000000FF141D0008008000000018018000040120230000cf6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0600E0AE0060\n\t0600E49608E04020400E084226004000000000000000000000FF7571800001100800901801900031431020895021000020E2\n\t4708600001000601629600C0260060C000008200000700621600640600600604642040601615440600400000000000000000\n\t0000FF7F8F800881C89281401C8D80110130B0A084330590800660160C740000000600E00EC0500680600081F080880006C1\n\t6A4701F20600601612600100502602D006004000000000000000000000FF1253000080208C80E01CC9C55001005080001000\n\t00A000608600600400000600402504640600600410080011600608608680688600E48601000C800046004054004000000000002f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (880028608600\n\t60A008800E00630E00600600600000600610204601600600600600600600600000600600422E004000000000000000000000\n\tFFE0CA0000018010030218458070C91610090419C782400063162864080200A628658600628E2060A8100004238086506086\n\t006106086006006430024006224016004208000000000000000000FF5893800001800C20815809C0800440008093504000A0\n\t02600E02600020000600604600400610600000040208203754E00E1260B622604600E2000100060040061040000000000000\n\t00000000FFEDC6800001801001281A018A91080000009090009000416427046002008004006026A54246006120006002002000af6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF3F\n\t7C80011202405400000002002802004A04003200000060060000200000200001001000000001004060A84905200004102004\n\t400000900902C0208520006008006000000000000000000000FF99CB00000100180384180180101100104811112405000462\n\t0640601424012620604200208630612000640600610648610E08601620602600600000800600400608400000000000000000\n\t0000FF1E7500000100180181581581102300908200300088402861161460A011001610641200221600601000000422E01604\n\t600604614614600601642004400624422E004208000000000000000000FF9074000001061841801803805121049023041801006f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A42A30A2222A\n\tA2A22AA24020A2CA2AA2AA2AA000000000000000000000FF0E541000002282A820000028A40000200000000A000000000002\n\t1124000000004008008001000080200080080020800080100000800000010000080040000000000000000000000000000000\n\tFF15520000000409008AA8AA90010010008088800100002AA2AA2AA70000050223822A2222AE2AA3004AA0021420422AA182\n\t02208A2AA2322220001A20022AA2A22AA000000000000000000000FF70500000201101000000001121021120000041000000\n\t006006004090000510100000010000000042006404024010000040090000000000000002004010004000004000000000000000ef6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AA2AB0024A2\n\t0002AA2AA30A2022AA2AA2000ABA232024032AA08200200A2AA2222220090A20020AA2AA0AA000000000000000000000FF34\n\tC080082140440840140140120104100502900500000000000010040010100041100800050044000008A00003010040000401\n\t10804000000100040000000000000000000000000000000000FF70F0808155901801D55B5584190580992D15594180005565\n\t5651600E000D56556446547557556210156C564560965564564564CF55655654648843651655655635600000000000000000\n\t0000FF26E600008A8908228AA8AA82A82A80A8C88828B000002AA2AA2AA02A0000222A222222A2AA2AA0200AA20A40A00A2A001f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF243800\n\t00000A00000000000000800000200200000000000000000040500C0006000000000060000011000000000080000000000000\n\t0000280000080001000000000000000000000000000000FFA01F01000404404040000015210C144032000042000000000012\n\t80000000000001001480000001002000890D0520000010440341000080088280208520000000200000000000000000000000\n\tFF7AC308000010010A0004000000200080000000100000000001400210000000000020000800800010000000000010800440\n\t090000000010000001000010400000000000000000000000000000FF30A48000A880C8048AACAA8008509408808AA8808000009f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (506046000000\n\t006001004000000000006000000000000000000000FF3A0D18000410002260100000151000020044A0090000500808024204\n\t005020044004004004404151020004C04404044404800000200000D41150D0120800008020C000000000000000000000FF68\n\t09100004000800900800800A20800804A80A00800028200200200200200200300280200282200080220A0020022020022820\n\t42000000002800006800000000002000000000000000000000FFA20300000000000002000060000800000000020000000008\n\t000002000000800000000000000000A80018002002000203080000000000008200A820000000180000000000000000000000005f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020002060060\n\t02002002806006002000002006002002002002002002000000002000002000000000006000000000000000000000FF0E6300\n\t0040000024200000200000000240000001000000000804400000102000480400000100400204080000400000000010000040\n\t0000000002004401000080208000000000000000000000FF4D7D100020000800800800800800800820814800800000200318\n\t2042502402042002003002C02000112002002003002002083002000000002000002010060000002000000000000000000000\n\tFF8565000000021801921801801841801C259018010000006006006A0480488600700780400684400080641500400740608F00df6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF3FC1000000\n\t001801821801011829001801801028800010200C0AC406002002106006000006026100006100002116106016006006000000\n\t006000086000000000006000000000000000000000FFDAD50000000000000000000000000000000000000000006006000000\n\t000000000000000000000000006000000000000000000000000000000000000000000000000000000000000000000000FF1D\n\t9700000000000040000100000100100000000000000060068008008000000008000048000000010068040040010000000008\n\t04000000000000000000000000000000000000000000000000FF1C94000000000800800800A00800800A0080080880000020003f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (021000480064\n\t20022000040080026000000000000000000000FFA88C000030049021025805001A41288A01A0140084000860000040860064\n\t46106106800106022088820504420027486006024812100000706000516010000300406000000000000000000000FFE42C00\n\t0000001801801801101A01123C0980100A80000060040043060060060060068008860020002464048C008600600E85680200\n\t0000406040086000018500046000000000000000000000FF75B3000040049841C01841001801432851C01084820002200000\n\t480600681200600610808E80020950800050004600600620600608004800620082600002000000600000000000000000000000bf6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (640682F00616\n\t684629E4260020000069065E1086026006004000200018C06080452400008000066000000000000000000000FF000B000000\n\t000804085802A0BE00808801401801000000600A00780701620600700E006106802000000206000006206006004008200001\n\t106000002010010000006000000000000000000000FF29D2000000003083901801C958099009258030400080042016006206\n\t00480700604E000C16102000407000000006806006006000000280006000822200040000006000000000000000000000FF12\n\t32000000040A00C01821889851800821001D40820002281295700600480E10600611000E80240008830020000E00600640E0007f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (530000000110\n\t1184B80100188500090D819221000100600A70715200600600600600080600200000080200010608649621E2160000000000\n\t00906000000040806000000000000000000000FF3246000000000800001820001808081811A41005000008600E8040020040\n\t06806006006007002204006003840006086107104106000000400214006000000100006000000000000000000000FF106F00\n\t0010604800821800001800005821823201800000620200400202402600610630602E08200440000280090782600600600608\n\t0280000084086000040080206000000000000000000000FFF4540000000415610218009619D096A905821C41050005EA060000ff6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020011600400\n\t4018000241006088000000000000000000FF3C2F000450741401601800001800042801053820000000700E0448001048444A\n\t794681600600200480610400008628620608C006000000556415405420200000006000000000000000000000FF1FB2010000\n\t010010021C4000180005080104190480000068020AC0C80040040060060060060222801000042412A600620E08408E100010\n\t406288084800000080006000000000000000000000FFD98C00840000140108B8010418810288018010A1000000608604E002\n\t00600600600600000602A080886042400C46006006404406080008088080006008000000006000000000000000000000FF130000e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100006140140\n\t0328060860060000060C6026006006046404000800000006006006000400000000000000000000000000FF980C000011B010\n\t15845840809A11A41A43A104030000016886842506000046400200802006406804006004806007487006286844000200D504\n\t0C446446C00000000000000000000000000000FF8D5F00000000108B101820001808000801805D8100000060060028800060\n\t04006206106066282000006106000107007406014006001000006000024010000000006110000000000000000000FF31C400\n\t02000000001A3C00049814100927801C03000010E1820062208070040060070A78060120040010460A0026006006A24226000080e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000100100180\n\t180082180000000D901121084000650602200608820200005054610603600441640641640604608600600400000000600400\n\t6006000000000000000000000000000000FFDB14000001800001801800801801801801800000800000600000200600000200\n\t0000002006000000000006006006006006006004000000000000006006000000000000000000000000000000FFEBE0000401\n\t801001801800801C018018018000000000006806002006800002000001002006000804006006806006006006806804000001\n\t000004006007000000000000000000000000000000FF69FF000021A40101801800801801A05A01A4002100008060110028460040e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (166030506006\n\t400000000000000000000000000000FFB1D900000100080180380180184001020181404184409465500C3556440500000510\n\t00E556116414000146006117507516806806000501006284006006000080000000000000000000000000FF354E0000010020\n\t018018018219E8074209806021000000608E70200600000000000000600640E0042070060062460060860064441000000060\n\t04806006000000000000000000000000000000FF7AD0000001203A01841840801814100001801001000080E02800A2360008\n\t3043050000E00690640004004602600E10E427027006440000046040006006000000000000000000000000000000FF0AFC0000c0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (024300000461\n\t06400000800006017056806046006446000000006000006007000000000000000000000000000000FF538900000180180100\n\t1E00801800000000001C24722011004E00208640000200044880602600040100682600600740600600600600028000628000\n\t6006000000000000000000000000000000FFA4C0000001E0020140180080182180980000A881000004648002A23602030700\n\t008000E30E116110000886006116886D0E0060240000000A6010286007200080000000000000000000000000FF828F000001\n\t801101001800801801801800080985182001E2260BB22E08822E0602E828E0060A630002EA262260060AE2060260442A00010020e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B038CBB15A48\n\tC23A0A20A34120D0488000A008A0802004200C02100108A06C26CC880092888EA8E40E80E886C4EC06000220B0E880D0E846\n\t000400240000000000000000000000FF0B8B0000038298018418838898C188180B0812828000006006234314101106C28000\n\t04C109000088006006026006286206886086000000826229006006000020000000000000000000000000FF11320000018010\n\t0180180080180180180100100080000060000040040008060000008040020000000000060068060060068060040000008060\n\t00006006001800000000000000000000000000FF0AB6000001C008814438408018041140040018008000000000082006001000a0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (021920020000\n\t20020000000000000000000000FF200E0000400100C000A0010400A414000510128000000060068300000000046080804000\n\t00004180006008009409008480680000000200660000008000000200000000000000000000000000FFC54200000208020058\n\t0014000040000002000344000000600620088828024002000000064804800002E000101B010011001002000004000885A000\n\t0060040000010000000000000000000000FF7970000001821839801883881900000121847008800010006600260400040208\n\t000806603640000008600620601650600601E086000000006040206506100000200000000000000000000000FF61370004010060e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080002604600\n\t4000006006106006006006106446000000006000556146020000000000000000000000000000FF56E7000400C04C30AA0C08\n\tC40C00D20C4CCA8A10800151304303220200100200800120BA134C308110340B00248A2824832530120004012432A1803202\n\t100000810000000000000000000000FF87CB0001002082034602004002082082D02980210000800880008800800984810800\n\tA19000A20808900C908A0000281200860C50000020800A08C40000000001000000000000000000000000FF431D0000010468\n\t0000482892A802882808800A128000612002442854000002000000002082186002002002002002002002002002000000002000e0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000AA0880AA0\n\t8C0AA04000000000002A82A82202202102202A8AA82482A84000400A83180882A82A82A80000000000002200002200008000\n\t002A8000000000000000000000FFCBD6000400A20B00800804A00C00A00A209028A080008028028020021009128000009228\n\t02A02A00C02802C42803002802B4281200080080284088A802000000000000000000000000000000FFB3C100000128A24B00\n\t1220201242200294230015000080080090888C84880480000080000094C8408008C0800804804804808D40000000908C0000\n\t0000000000000000000000000000000000FFE6ED000121851801805805901943801901805925000000600620602E0002A4200010e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF20980000004301320AA4804AA0821284AA0AA0B000002A80A88C82A00402082A82A82802A80C\n\t00102A82402A82A82A82A82A82000000002A82002200000010002A8000000000000000000000FF221600020000C084554130\n\t3543503543000C20100000D50D50521540540D48D50D50D00D50930A00950C20808D50D50550AC08C0000800D50C40D40801\n\t000000550000000000000000000000FF4DDA00040000000060024A0004004000004006000001001000401800009140000001\n\t031000401401001101000000001001001080000001001001001001000000000000000000000000000000FFB6C700000000000090e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (810800030800\n\tC00940800000805004800800000000914C10808800804800000000000000000000000000FFB5B90000008088088008288008\n\t00840A0080005080000420024420120000120020021220025022000020020020020020020020B20000020020000020020020\n\t00000000000000000000000000FF42160000003044800AA2800AA0D00040AA0AA08400002884A80002B05202002A82A82002\n\tA80100080A82182AA2A92A82A82AA2500000002200103B20020000002A8000000000000000000000FF35660000002A043000\n\t020400000000000A0082C40000000000808008000000000000010000000000200000520000001000008208000000000000010050e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (050044048000\n\t0400000400000060060100100500100120104100102100100000110100000000008010008020028110100008000101D00100\n\t0000000000000000000000FFBC90020440C20C00C00C22C00C40800C1082040080000120AB40310300124340300300322300\n\t3000013403103003213402002002000113003100002203003001000000000000000000000000FF4F63000001801801801809\n\t805881881841800001000000600615600414000600610E00E08E5061000260460062061261064164862102460060000C6006\n\t004000000000000000000000000000FFAA480004010A322520100520022D28C0002002030000800A0088C8042908A400000400d0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (486300000000\n\t000000000000000000FFE42800000000000800004C10000005000410008200002064160402D00A8488208320000148500400\n\t1060000000900202000000080000000002004882A8080200000000000000000000000000FF29310400000000200000440410\n\t0000004100000000000160D608808002042000409001011000008004E020080C04C48C000080040000340801000002000000\n\t00000000000000000000000000FF4FB800802000080001488880282188080882004184400021026240024800041020265022\n\t02282100002382802042082002A82202048002002101063002400000000000000000000000000000FFB0C8010401420441400030e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (860160000003\n\t0C0AE0000060060860AA00000210602000654E006000000000000000000000000000FFED5400000180180180185180180382\n\t1801000000880040202640400611012450640610400400635008608700610204600700600A02000000630108F2A600600000\n\t0040000000000000000000FF133B00000180181189580192086381006512A0488CC008052400414244042401414600614610\n\tE0280002060A601609E006006786000000006000406006006080000020000000000000000000FF511C000001801801881803\n\t841801800001054092810010400A04440A00000800600640601621600000620614604610620600600600000000600004601600b0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80080B821A00\n\t80400500000020008060000000860070060020468860002000068060000060060A600000000000E001806007802000000000\n\t000000000000000000FFF53C0000CD00188D8AB8AB8AA8858C806188804000002A80AA20622000002600680622220E326000\n\t2AE0542462AA2AE2AE44E00000000222E000506006002000000000000000000000000000FF137F000001101A038018018008\n\t2182008B82032080000040040C6800000D030060060020460868400008260060020060062262020000000068004B60060030\n\t00000000000000000000000000FF6CB400004385582180180180081580580100200A800000640001409600001400600609400070e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFEFD3000401901C01001801801C21814008024501000000600611500100101600600702630E8460000070\n\t86806006006006116506000006016041026846006000800000000000000000000000FF716C0005558C1D5515588595592191\n\t25541505518000552550CD555400144A0060064D64064360041515570B65565565564065560000045460142D653600600000\n\t0000000000000000000000FF3F6000008902B8A98AB8AB8AA88988190288801500002CE2AEA262A80002C600700629284620\n\tF0424AE2045162A82AE2AF0060280000022A700200E28E002000000000000000000000000000FF1C7A00020101180180182900f0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620000644C14\n\t628E00600640641600030600630000E546004000000000000000000000000000FF0902000001821A01801905800A25835840\n\t010010800002200002480680085200600680E09608681000080529600600600649600600000410E80022E546004001000000\n\t000000000000000000FFF52E00000190B8010018298008098000030402410000006406016004000102006806106022016000\n\t206004006006006006806006000006006010086016006000000000000000000000000000FF6F130002AB8058AB0AB8018AA8\n\t81880089082083000028A0A8A862AC000203006006226B17A270100A82AC4262AE2AE2AE0362AE00000422700080680600700008e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018158048018\n\t2100000040040041460000160000000060040001000060060260000060060460040000000000000060460020060000000000\n\t00000000000000FF5F220000898AB8A98AB8AB8AA8AB8A18A800000100002AE0AE3462A200022E0062AE2060420040E00AE4\n\t840460662AE2AE00608600000E2AE0600A60063A4000000000000000000000000000FFF8A300000180180180180180080181\n\t1804000121000000200000600E0001060460060461120160044000044160060060060D604600004400600440601600C00000\n\t0000000000000000000000FF128C00002380180580180180080180580000000C00000064060AC00200000628E0061162262A0088e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFDE1A0000218018018000018018010210210018C1000004000000810600008E00800009601412000400014448\n\t60000060060862540002000000040A6006002006000000000000000000000000FFA0950000AB8AB8AB8AB0AB8898AB0810C8\n\t00188D00002AC0AC2A820E0002262A82A82AE22C2A82082AE2AC40E2A82AE2AE20E3340002A82A828820E28E22A006000000\n\t000000000000000000FFC5E10001139559359541559559559139148018150000510550404456000446540550446304410484\n\t55000E0163105565564560840000C8550504416536452006000000000000000000000000FF7F3800000180180180100180180048e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000082806000\n\t02F016026006000020006024216006014006800000000000000000000000FFA64E000001801801800001813A0184D8228000\n\t0380000042040022A800045400000109621400020020600214608800600620601400001000630000E5460040060000000000\n\t00000000000000FF689E000001801801C01801D0180180181080081100000440040060000000060008000069260000140008\n\t024168408068060B7146000000006014406016094006000000000000000000000000FFA9F90000AB8AB8AB8AB0AB8658AB8C\n\t18808008A1000028C4AC2AE0000001862A82A82261042A80800AE2AA1062002AE2AE1062040002A02AE0001E60063240060000c8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5C2008482000\n\t001240A410E04024912E10010804610750008010E00002600100E00610E00614000000602021600601600600000000000000\n\t0000000000FF13E9002100001801024705811809001000C01828800024441420A0204300A608004021600610000001020E02\n\t7001406006086004000010006000006006006006000000000000000000000000FF12FC0000000118014234A1C85B01C5D800\n\t905800000000424C20200000000700111080E90640011816720F706981207006017404140008606100006006006007000000\n\t000000000000000000FFAFA9008001901801C00A21C81801B01C4180000180000841040C200000100C8000001460010080040028e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF7E110000008258318019018018818438830028418A000042040CC2000A00560802200240861002A010E10C00E000\n\t10600600600600000020E08008608600A046000000000000000000000000FF80CA0000008038018230018158038C18210A88\n\t91000062408424402000020E00004850402E01000808010438602806E01604640C0000400061000060060020060000000000\n\t00000000000000FFC024000000001809400889801841021011401835800008C04C0460880001460200001060061000002001\n\t00006B00507006006126010000006020206046206026200020000000000000000000FF02EC00A100111801001805A018919000a8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (044100000000\n\t00090310000000100000400010010000000000000000000000000000FF110400002000002205000000008401404A04410800\n\t000060060881080000000000000905400000004060A014000000000024000000000000810000854010000000000000000000\n\t0000000000FFA0C70000018018018018118018059018C10A8905800044408C01013000020600001012400600050040E01010\n\t6490206006006126008000006000086026202006000020000000000000000000FFB18D00000184182182580180194180580B\n\t0048098A001142244804001400860A042000412E00003000000021602005600600600E0000004160A02060860120062000000068e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A280880002A\n\tA2AA22222A0002020008002AA0AA0000000AA2C240A800AAA2AA22A002000000AAA00020A28A2A22AA000000000000000000\n\t000000FFC92800004A4000000904000004000002D10800000000000000008000000000800000000200000080000084480000\n\t0008000810000010000000800A0000000004000000000000000000000000FF585B0000C90AA8C91448AA8AA8588A48840989\n\t0680002AA2AA2342220003220000002224020003004AA20A1020002AA2AA1020720000002223001E20022222AA0000000000\n\t00000000000000FF39790000040000001020000000200000000000200000004004000000000108000000000008000080006000e8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF4211800080CAA8AA8008AA8AA8AA8AA82080080080000AA0AA2022320002AA0000002AA0020002000AA2120420002AA2\n\tAA0022AA00000022A6000A20022222AA000000000000000000000000FF99C900000140100120040120140204841100002000\n\t0000000010410000005100080000000000040000001402080080500400150000100080020000004001000400000000000000\n\t0000000000FF5E3C000101955955845D55D559559558058538B380005563564A45460005560000005560D600020055744401\n\t600155755643655600000054E00041653654F556000000000000000000000000FF502300008A8AA88AA088AAAAA8809008A00018e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004003000\n\t0800000000000000000000000000000000000000000000000000FF62F40000A0002200056000000000000000026008000004\n\t82000000400000008000008E0000000000800000000000000000000800000000910000100001000000000000000000000000\n\t000000FF299800000200000001440040000000000A02009000000002000A8000000000000000000048000000000910140001\n\t001000200000000000000100008540100000000000000000000000000000FF36260000304000001400000000000001001120\n\t2400004000000001100000000000000003000000804000404100000000000B000000000010000040001001080000000000000098e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (110000001206\n\t0060060060060060070860064060004471174165045568541004260000008060000060000060000000000000000000000000\n\t00FF05E004014000100100400000111100000004110100000100040040000440250012840440040040010200848018040000\n\t04400020400001000001800001008220000000000000000000000000FFB895040002810840A80800400800800850A0080000\n\t0000080200200202200000280200200220200022308A21228231200230042220000000200000200080200000000000000000\n\t0000000000FF411F0080000002002000002000880000000000800000000000000000000000000000000000000000000000000058e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t7592000000A00801800800200800800800801801800000000600000200600200200600600600600080200200200200308200\n\t0002010000002000002000812000000000000000000000000000FFF1EB000000200000200000200000000000002000000080\n\t0000004000000024000500000000000000000084800804200005000020000000000000000000000240000000000000000000\n\t000000FF652000000080080085480000080080080080080080000407826020420020020020021C2002002001042002002002\n\t202083000002008000112000102000002000000000000000000000000000FFAA41010005813841101800001801801851C03000d8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04622822040E\n\t000000A06080427000006000000000000000000000000000FFDEDD00008000180184A80000180190184500808A000000002E\n\t10640600600600600600610604E00002600630E00820600000002600000000405000C0000060000000000000000000000000\n\t00FF7E1800000000000000000000000000000000000000000000000000000000000000000000000000000060000000000000\n\t00000000000000000000000000000000000000000000000000000000FF4B6900000000000040000000000000000100000100\n\t01000000000000000000004000000000000000006000800804004004000000000001000000000000004000000000000000000038e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000010164060\n\t4600600700200704604600601040000E006040006004421006000001404080016000002000000000000000000000000000FF\n\t3A570000D1065864000802011823809AEB0032080400000026086207116026154406006A06A26000020816B8C20CA0C00040\n\t0704010000506028306900002100000000000000000000000000FFA1D8000001201A0080A800021801881A00A61822000100\n\t0806406006006046806A0608648600E00000688680648403622800082E000000006000026000002000000000000000000000\n\t000000FFEBEF000040041840A0080242184D855891802220000000000600604600600600420712704740600840008E0060A100b8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFE408\n\t0000C09DDA8008784042181182504301D019040100000600E00611620605008610670608E06000700640441682D007400404\n\t080600506000006500600000000000000000000000000000FF0BB2000013801922A09804031801821005001001080100004E\n\t00F80600640610248600600601600020002610C0070540460000060900000060A02A60010001000000000000000000000000\n\t00FF2DCF004004A01C00251822401889803000803081080080002E00600780610600380609610600600024702620F2080070\n\t240000040000800240C0426400000000000000000000000000000000FFAA86000021801800A41800401811843800409100000078e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8F8802840000\n\t0000E008024000006000000000000000000000000000FF438E18002185181800505804184980100830989000000090078040\n\t0400600601000600600608618C6000E608600278E406450044000000686005104000186008020000000000000000000000FF\n\t9C920000A0801C0082100000180382102900192400000001060040268060060008060060060060000061060A480200400200\n\t0006000000106200004000806008040000000000000000000000FFC3CE0020808018008C1000001901801800801900000000\n\t000780400600610600000600E00610600402001600600200600280008600010002600400400000600000000000000000000000f8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001600424600\n\t62060A000601608680608E80040600518E00492600064C008000016006066080006008200000000000000000000000FF75E3\n\t000002801840201800015841B15009009C48008050090604400610610640209693600610602080602608C204004110001804\n\t000309834088007040047140000000000000000000000000FF0188000500841804045800001801801800801A140000000086\n\t20400600600680A00600740600E00400000F0450040452102A810400000000420C0868000068000000000000000000000000\n\t00FFE5C7000201801802001000001811801000009800000001000E20400780600600000680EA0610E010807A1680408203480004e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF023B0000\n\t8108104000900180180180180180000100800068060460060160020060168060060060140000060060140010460068068001\n\t000160048061060840C8400006000000000000000000FF9D7B00205501109102104192D8458B5A0990104100015460060044\n\t07086480B4600615690700692000684684F30480000E006A168082000260A8006046044000000026000000000000000000FF\n\t7FDB000020849888009800001801801040011810000002090680400700F00680010700600610600060600612500600410600\n\t0004000010006020046000086000000020000000000000000000FF6CFA0020888B18004218600E1847C610615818400000800084e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (684610010800\n\t6005406006004000000006000000000000000000FF2ACA040001001089003001801801801881801001008000620600640600\n\tE400400206004506306420006046006004000006006406000000006000006006004000000006000000000000000000FFFFBB\n\t0000010010000010018018018000018010018000000006006006006002006006006000006004000006006004000006006006\n\t000000004004006006004000000006000000000000000000FF00170000010010010010018018018004018018010000000007\n\t00600600700080600600680000680300680680600480000600600600000000400200600600400000000600000000000000000044e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A62BE22E08E\n\t22E3CF4876AE2AE3A000E1BE0A64AC8096A6026226080001006000006146144000000006000000000000000000FF53E20000\n\t00801820801841811801803C0194021194402062D640E4C708650600200A09610201680400000620604600800600E0060000\n\t40004004806006006000000006000000000000000000FF6ABC2200000010022638018A189F805801803001000080680700C0\n\t06006206002002806012016800026206206204020006006006000080804000006006006000000006000000000000000000FF\n\tF8AB002201801A038090018A1881B298338CA2090C404CE1524AE0B624612A03014E0D7026026084C485165265560495460200c4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (68EE004000C0\n\t1930A31C01801801956245911A1180000402060060060060460070420D600400600040100600600680000680680680001000\n\t6000406006006000000006000000000000000000FFF999000001801801801001E01801800401901009002020002E01624600\n\t620600601600600400600000600600620600820700F007000040006000006806004000000006000000000000000000FF965F\n\t000200401200601821809801A01A01C214031400046086C0408E8861060070A221628600E10080008E206044000006006806\n\t0000000060000070A60A6000000006000000000000000000FFFA9E4000010010010410018018018018898210050AA02CF2AE0024e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000004000\n\t00600600600000030E000000000000000000FF78BF000210A2BA8BAA2C29A11B218A0109A052118000480D2488603632EC2E\n\t8CE8C28A6AD0126810890C0E0068AE0A00A6286906000000D168A08C6D46896000000826000000000000000000FFB6C60020\n\tA3881801800801823803800001A910A3800100000C25610600610620221620E0002060000460864B620620020E0162460000\n\t0000621021600E22600000020E000000000000000000FF1E6900000100100100020180180180000180180180000000040060\n\t06006006000007806000006002000806006004000006006006000000006002006006004000000006000000000000000000FF00a4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (070020522222\n\t021420028420000021030020020010168060E2000000042000082012602000000002000000000000000000FFE5FD00000000\n\t3008080000500060100000008020000020122000008108812C50C0248A4E248201501270005187A04A04E800820000000039\n\t84B80081C8050000000000000000000000000000FF7A0F0000200401000000004000000006000421020000400010000860A0\n\t00800401000101008000000072888A0010200A008C0000000000000000020200088000000000000000000000000000FFD7A5\n\t000082809847870829829801A80009890801800090004C40400600600600608220E05020600000E40620604E0000062064060064e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000101021911\n\t8099018018218A1051821801800004C0360060868060B652690601608442602804600640E286210006006106000000156000\n\t0160A6226000000006000000000000000000FFA491000420D00C42CA0C00920800800900C10CA4800050310340204A013803\n\t003003943C4A803101082C9210303210043202342200000100341148300B00A000001102000000000000000000FF5BD80022\n\t092A02102000000424822413402002C800000501808A891803520088100800008C4848088C00148048009108000009000000\n\t00800A00F10020820000000020000000000000000000FF1841000140900880902900800C00A200908008048001084002203000e4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010014030010\n\t01000000001000000000000000000000FFD4610008A80AA0000880000AA0AA0200000000AA00000002A82A8008AA82A8000A\n\tA82A82A82A80000A82A8000240000208000408000000020000088000020000000000000000000000000000FF1CC4000004A0\n\t0A08A00C00C00A00B00A22B20A008000802802802C22000802A82002802802802800C02802A93002500042002A2200000090\n\t2800C02802A12000000802000000000000000000FF22350002014002A222400120120120D309212200000000480100090400\n\t4000848000000004004B008000048448C8848904004900000000A10A80840000880000000000000000000000000000FF3AAA0014e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000800000\n\t0000000080000000290000020848800000000000450000208000400000000000000000000000000000FFE0340000480AA000\n\t08A0000AA0AA0AA1000900D200010002A82A82A82A82A82212A82A82A82A82802A82A82A82482A8A488002A80000002A8080\n\t2A8000228000000000000000000000000000FF8B3C00011415434C3542003541543002023243540000800D50D40D20550D50\n\tAA1550D50D50D50A00D50D50840C90508500000928000000880B008C0800930000000800000000000000000000FFE5B90008\n\t00400448440400400400400404400400000000000100100000100110000100100100100300100100110100080080100000000094e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (502012012004\n\t01401201200308248248000000000080080000480090C004800800800882C010048009148000840048000000008008028008\n\t00880000000800000000000000000000FF434700000400094484480080080080082280090480008020020020028020020028\n\t02002002002400002002002042000852002002000000002300002002052000000002000000000000000000FF30BE0001040A\n\tA10C0880000AA0AA0AA0500C600000000002A82A82A92A82A82302A82A82A82A80000A82A82A82002A83008002AA0000002A\n\t80002AA002300000000002000000000000000000FF6B9B00082020000000000000040002C1280080000000000000008009000054e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200104340200\n\t2000041002100000000000000000FFEEFB400D80418400400412400408400400400400020100100100900100500100108100\n\t1409021300001301019121001115124000000000001088008138000000000000000000000000000000FFB2204024004C0C40\n\tC00C00C40C88C00D00C00C02820100300300300300300B00348B01300B053002003403103033411403032002000210003092\n\t042002202000000002000000000000000000FF33A300000400180100180580184180184B81380180000060060560060860C6\n\t0060260A600608620002602C20640600002600600600004008600008E426006000000006000000000000000000FFD6E8000100d4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (406046016006\n\t00E00000E00000600600000600600600000000628024E1460060A0000006000000000000000000FFC82F0008000240001140\n\t200CA14002002000012800A001008012E0D60800500880000202004D004008E4002A02800802000800002000200003001100\n\tA0088030000200000000000000000000FF36B7002002140000000000000100000113003003000000000000600608014C0002\n\t080C42040840800061542003104100A00080000000100800000C0480200000000000000000000000000000FFB61C00000000\n\t0821800808820820804820908800840010200202200240200240402641A10200A10002200608200640020A082842000220000034e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (580801000180\n\t1801811801951053000001201640E00600608E0540060160AE00608020000000000600000600600E00000008000028648641\n\t0000000286000000000000000000FFC20B00000002180080A003883801809820023889000000A02E2365060A610601400624\n\t648604608010624032630620020600702640804000400100700608C000001206080000000000000000FF0E7000098000D898\n\t86080381194180800E03B841080020612E2062460262D21047A6186066506640000020006006100186106006008000006000\n\t306406006090040006000000000000000000FF9568000000011901880841821801822008081801954050600608600E40620200b4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08F286208000\n\t000286000000000000000000FF2890200242001908841801801801C03800089000000080004B00600680688204C116007886\n\t006000000806806006000806006026000000006000016226004000000036000000000000000000FFCE1E0000460158420018\n\tAB8AB8AB8800AA80018400002002220162AE2AE1042142AE6262062AE2000AE2AC2A8C560002AEAAE08600000003A0004060\n\t06080000000006000000000000000000FFAFCA0000100C19408A5801801801A4200000200000001401028C60060064401050\n\t069060068068000000040062CE000006006246000000206D0003603602400000002E000000000000000000FF364A000140010074e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0E2AEA0E2AF0\n\t840A9AAF2A82AE801AAE2AE1060000002A90041060062AA000000006000000000000000000FFDA19000800081A0490180180\n\t1801804001204A018000803000006806806043124806006106006C0000680200710600080700650E00000024480004605612\n\t600000082E000000000000000000FF3CE2400410155822913955955955948154823955800054A480556556556432484446D5\n\t644ED56284550552557556000557556216000000554304446116556000000306000000000000000000FFCD35000088021910\n\t42B8AB8AB8AB8A98AA13083000002C82B33262AE2AE20E4002AE8CF236AAE0802AE2AE2A80070002AE2AF02600000010228100f4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02B801801801\n\t84D901910021800000208200600600602E00400602E0060160020060A025000600000600640600000002200008E126002000\n\t000446000000000000000000FF0909000050001C4022180180180180B800C93401800002201280400400608E835246806026\n\t806A04000000000006000006006A46000000002B04436A2E002000001356000000000000000000FF7A4C00008400190A0038\n\t01801801840000041001800010A5200060060060461041060040860060004060060008060000068060960000000000008861\n\t06002000000006000000000000000000FF6A620001000AB8000898AB8AB8AB8800AB8010AB8001A028002AEAAFAAF2062050000ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (564920000000\n\t16000000000000000000FF4EF6800000001005004801801801812805805001800000401000600600600E0440060060060060\n\t00006086004000000006006146000000002002006006032000000006000000000000000000FFEC430000000AB8000818AB8A\n\tB8AB8C580000011B800022A2222AE2AE2AE2D60042AE2862AE2240024AE2060802AE0002AE2AE02600000020A00200600628\n\t2000000006000000000000000000FFBF9D000000001894001801801801801833822081800010200A0040040060062D400600\n\t600610600420001600000600000600611600000008200422621602A000000096000000000000000000FF2803000000001820008ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C2AE2AE0000A\n\tE2D64042A80002AE2AE026000000110000746006002000000006000000000000000000FFB716000800000031032801801801\n\t80082115180380001120100060000060862240060260060260060000360A40020000060060060000000820064A6506022000\n\t000546000000000000000000FFCAA80000000AB0490A88AB8AB8AB8A088915188980002A82A02AE2AE2AE24628C2AE2AE2AE\n\t2AE0002AE2060B42AA0002AE2AE20E00000042200000E52E48200000054E000000000000000000FFAEA50000001540851009\n\t55955955908912003841800044454055655055640611455628E5563160041505064145500005565564B600000044A0040160004ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (05C11A82001C\n\t230018018000006C00206201106826027226C8BA0320620408000600E410A0210702600600002800C0040160060060000000\n\t06000000000000000000FF2FDA000800000805044801801800005900111A03800010410000600600622E4360060020020060\n\t0040602E44480000200600640600000014400008E12610E000000446000000000000000000FFFED7000000201131800801A0\n\t1800040A32023801800003400800600100600690480600400700600400080610E000001006006116000000208004026216A2\n\t2000000096000000000000000000FF6AF40000000AB1010888AB8AB8AA0888410018ED80002042202AE2AE2AE1860042AE2A00cce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C48000000640\n\t0000000000000000FF8D3A800000281001800009A0D852000A419018880080100400040430C0600600408E0C805600605048\n\t6316C4641201000600600600000000A000016006000000020006000000000000000000FFFEC58400A0100811000011805E49\n\t840800001088004008400004784020700780608780210A00610824190F204002003006006006000000006000006016004000\n\t000006000000000000000000FF6E79800880407009020101C61A81820A0290120001204050400061970071870048172432C6\n\t9662C0027406044901011086006006000000662000066006800000040006000000000000000000FF2A6E000000400801820C002ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (10420000000E\n\t00600410200600601600040040604052E3464C6210000006400000000000000000FF80340000000018018700218238018018\n\t00001811088020240808608600600608E0C658C0220F420008600E04600600200601600600000000400222E0060040000000\n\t06000000000000000000FFB1AF04004000102300818D8018098AA88980382100004022C04262081260C604446600408650C0\n\t02000006014104480006046006000050000022006036200008000006000000000000000000FF282E80000000091190420581\n\t1800000821131808022008A000210006006C560068162408034060C004048623600A00308701600E4002004060000863060C00ace040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000103390\n\t5085000050000002600600000640000001400600040000600000C41454000000011000000010030042021002800000009000\n\t0000000000000000FF9D0D80000000200A00200000003200010001002000000280000060260000000C80000C000008008020\n\t60001400C0000000000400000000050000088120080000000440000000000000000000FF5AAC000000001945905809801808\n\t08DD01005821804008208044021000724600600E0091024041200A648640E00E00610600600620000000600000600600E080\n\t000006000000000000000000FFDD050000000018118008A582D8000408489298010C8021201008810604609610E106020042006ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000016000000\n\t000000000000FF54E00000002D4840882CAAAAA8888AA88888484080000820002AA48AAAA2AA10A2AAA8A2AA2222800AA2AA\n\t00248A082AAA2AA20A00000022208020A50A28A00000054A000000000000000000FF73EA1000000080000A00000004020204\n\t2000002000000CC0000000000010000000040A51008001000010000000802000008000000000004000005205004080000005\n\t40000000000000000000FF356E0000000008B08A18AA8AA8848AAA40820808800040200028C28A2AEAAA0422AA2432AA22A0\n\t000AA2AE21200200E2AE2AE022000000312000142002242000000002000000000000000000FF44450000001300010080000000ece040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004000000000\n\t10410000000110000000200000220210320000000090000000000000000000FF32EC81000000A8AA8188AA8AA8D2D20800EA\n\tA8A8800020A00028A08A2A82AA2AB2AB2030822AA0000ABAAA2AA2220022ABAAA02200000000208000200204200000000200\n\t0000000000000000FFE0BC80080020010404920120144000040444828C000005400000404080500040100480480110800240\n\t1004541020454805004140000000000402000040000000000000000000000000000000FFC16B800000123D55803555D55901\n\t80BD13B55F138000404000554557557556556D5640C456556400356557557C5614D5565564B6000000156480016036086000001ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000280200000\n\t0000000000000000C00000000040000000000000000800000800000008000000000000000000000800000000000000000000\n\t000000000000FF07020001000284082000060020200002000000081000200000C00100000820180808000000001000000000\n\t000000000000000000001000100000400800000F00000000000000000000000000FF4C271000000400000000000000084125\n\t0000020000000200000204408010000000011110280004800000010010800C08000004000000001282001081200100000004\n\t40000000000000000000FF12710080001002000C420020002008003200000400000800000000000000000008000204000000009ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800000000\n\t00000000FFEE2D00000182100D801801C01801801801005E898080206016804006206026007027406007106000006406546C\n\t06504114010006416106006000006806006946000000000000000000000000FFE1F90000180114210210452040400001AB00\n\t020000000A028C024000205085D0021C80000000400000080000400400400400000000000000000080008002040000000000\n\t0000000000000000FFAE37000410A00C04800800800800800800A04880810000201000200300000020200240200308200000\n\t22024A320228208200800240A082002000002002002126000000000000000000000000FFE19E000000200000200020000000005ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600000000100\n\t4004000004000001000000004800005000000000000000000000000000FF7299000000803800000800000A00A00A00800800\n\t900000200220C002006002002006002002006000002002002006002806000002002802002000002002002080040000000000\n\t000000000000FF066F00000000004120020008020020028D000000000002050D040101200104000C08000000001000000000\n\t005000004800000000000100800000000100040004000000080000000000000000FFBCDA00031080280085E87C8868008008\n\t40806800800011A00280A003002062102002002002002000002002002003002002000002002082102000C02002002C02020000dce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01051004A000\n\t0460168000860064060461060C60164861084200060460060000000002860068062360800120464860060400400000000000\n\t00000000FF95F1000101801801801801001021023041000901800000610600000002610601600600E0020460000060060860\n\t06040000000006006006100020546006006016000000000000000000000000FF41F300000000000000000000000000000000\n\t0000000000000000600600000000000000000000000000600000000000000000000000000000000000000000000000000000\n\t0000000000000000FFF957000000000400400400001000001000000401000000000000600600000000080000400400000000003ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF4B09400140820801009801905800855841001900800004600600000E0061060100070160220060084400060270070A\n\t000400030200600652C00015202440A004000020000000000000000000FFA48D000001000218A0580112100180501582180A\n\tA000C04116C060001262060264860040060260000000272870070040000000280440068160B021241000241C020040000000\n\t000000000000FFBDA920000980A8018078210010A1801019809811800080408E0060960060068068068A604A286080006046\n\t40600611C000000052806006804000002804092804000000000000000000000000FFF1A000004984CA11C118210A5101809000bce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0060060028C2\n\t000086006006000004006006006408040000000000000000000000FF189C000201058000015A238028919248010093A08000\n\t49E01600E04602E7D60248061042072060000160070060060272A6000600F540860161000124000000064000000000000000\n\t00000000FFFCD7000000000600001823882900820805601800800188780640780000780621500602DC064070020000060062\n\t0604640600000100788480400A022010010006000040000000000000000000FFE9E6000001842801409C0180180990190100\n\t54008000006046000221206036A0C0560AE00300600041604780720600000400010211480700610004200400800442000000007ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (980082000861\n\t06006027A0600600600603500608EC0002600648600600228600000600400400620034600200600200000000000000000000\n\t0000FF80A5002221818841B018018190011991D4A09822820000600682601800680660600600616288620000000680625600\n\t200604000680400F09400081E006047842000000000000000000000000FFC0A8000100100008A358018000018000008008C5\n\t802000E006046006806006007286884006006004006006016C0600200200000702600E102084007002007000000000000000\n\t000000000000FF3E5B000200802809801801800001000088814021800000612781640033600602622E80600200700420002600fce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF1B5208000000005288980186C00108E055801082804083610780600000E807A0E50601408781608C020087007066007006\n\t0000060442240961A414200208606E000028000000000000000000FF5B520000050001108218018020008000118B28209000\n\t107006416246047116107C960950061060040160260860160040000000074041060220054020320170042200000000000000\n\t00000000FF439E000100080200935801800004000001801080800010680600602040600700600614410600700004000628F0\n\t0E005500020006004006000200402002046004000000000000000000000000FF9D71002221000000A01801825003805000A00002e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060040060000\n\t00006006806004006006007006006006000000000000000000FF25E9200001200009821A8B040A0000120081180188000060\n\t1600640015610650220600E10210600400080600604600400600000000680600600400680E0160C600604600000000000000\n\t0000FF8373280005A05083811A0100AA10091A10841125800012600701604600600200814E10600300681404E12488710E10\n\t4006010000406336346144406446506016046016000000000000000000FF004D00000100220090788B800009804001905800\n\t800060600E40600608601600602600400600610000700400708608600600800600500C2060000032022660864000000000000082e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80000AE04633\n\t60804A602688828E106306106420408486006006145486408000016006007000006806007006006006000000000000000000\n\tFF123C040001881001801809000801011804810111804000601600601601640E400046416042046004046006486006004006\n\t000480006006006004006006006006006006000000000000000000FF6E0B0000010000018018018008000000008008010000\n\t0060060060000060060020060060020000000000060000060040060000000060060060000060060060060060060000000000\n\t00000000FF7967000001801001801801800800000800800001000080600600600600700680000600600200080400600680000042e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF45\n\t4700000180100101180420080083380280918F80201A64A608E08E2AE46E3884AF88608202626020F2C62860064A52862082\n\t80008006806401006006406916006106000000000000000000FF69BA00000100080180180103190000113181005185402561\n\t57456550C561160081564425565123140400060425460165560000000561560060AC00600602E00600600600000000000000\n\t0000FF91EE000001000801A01AED0018141818819060018000606106006006806A0600080684220200300698680700200600\n\t6006000800006006006006806006006106006006000000000000000000FF1D2A0080018410818019010008012452A080080300c2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (580600000000\n\t2006006000006006006006006006000000000000000000FFC7A1050001140901409806A20815818A6090088100002B601664\n\t080602600488340665204638480004002600500600E006000000002006006800806006206106006006000000000000000000\n\tFFDC48000601801601001E00800801801810811821820000E40F00100040600700A12E806886005220026006004406204406\n\t0000000000D68072A9006006006086006006000000000000000000FFE0B2000001000801001A00810900800B0080080B0120\n\t0060A60562B0016ACE80220604225200E8900000068260A60060B600000004800600600000600602E00E00610600000000000022e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (284236000000\n\t22600600640601200E0000000064022000060A600600038040601628600000620660618608600E000000000000000000FFED\n\t170202D5A41D09921A00334B05289A48A083438000AAC4B68008A6AAEC26CA60969328B6880A808888AEC004C68460C60002\n\t80A0692EC8E84084ED0EA46A16AA680E000000000000000000FF0778000001891821C1180880184144388584400980000040\n\t0741601600609601524620220224000900640609000E28E0160010000AA00602748850704608F94600E32600000000000000\n\t0000FFFF34000001801001A01801000801001A0080080180000040070060000060060048060068038000000000078008060000a2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFAF7F00\n\t00C28308010088008108608B09A8802900800000300600400200600210300250220200201001A0A20868A65028020000001A\n\tA00212A00010A0A2022002022202000000000000000000FF01EE000020000048020100025003140003029018000050108800\n\t601F00030868402828413422438010634100C1482080080000000140A8000210280540100228500080000000000000000000\n\tFF6DEB00010008012044000014811000000010000000000008000160270004200009000280C0190008006010510A100408E0\n\t0000000000000100A8000000000000000020000000000000000000FFD7CD000009809801A8581488388100901581002180000062e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000A80940C80\n\tB00A208008C0A90830000000000000000000000000FF535500014994192182190D841901841905801909800020610608C00E\n\t00650650681650E0060940000062D60144162460060000002160561060080060B6006106286006000000000000000000FF90\n\t21000402C14C00A14E40C92C32C90C10D48C40800110201300308208380B00A52300314B2035091530034821430820220001\n\t010A330300B001083403483203003002000000000000000000FF4CF60202143442804104482002042022002402C200008281\n\t00B08980189090838AD4800800C04C008C0808000C00800804000800A40D40800800820818888C002080000000000000000000e2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010010000018\n\t008410010010110010010010010010010088100000010010010A1001341009001011001000000000000000000000FF178900\n\t08200000880AA08C0880A00CA0AC0200AA00002002A82880882A82A82282A81002A82A82000A8000AA82A824020000000000\n\t80281080002A8200000200000000000000000000000000FF8DC0000400A00800A00A00A00A08A20A00A00A00800000280282\n\t2C02800002002802A9280300280080280A003002802042000850A02802842800802812842882802802000000000000000000\n\tFF9C7300031234A4450010422222042002023142000000930804804820804000900004840801004840C00B408050048C888C0012e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF8DB000082C\n\t00802000002000213000400008A0000000000000000001001000090000220000000202200489000000000828000328310220\n\t0402220000482A00A0000000000000000000000000FF37030000880000CC0AA4AA0820900A008810002A00002A82A82880A8\n\t2A82A92002A82A81402A80002A82A82A82A8280A800003202A82A82100080104A02C82A0000000000000000000000000FF6C\n\tAC0003002A41123543103502043103282203540000550D50D30D30550551440D50810D50D50820950840550D515104800008\n\t00840908C08800D50C80810C10800800000000000000000000FF2715000C004C2400400000428440402440452480000100000092e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (164860260060\n\t00006016006006006006000000000000000000FF07E800045120422020000021228420C20031024A0000800800844A208048\n\t04004800800D008048008008008048049041040000C0800800C10A10D00950890800800800000000000000000000FFE84400\n\t010094091000080080083084082484480080000000020020020000004B000200202200200040200200200202204A00001200\n\t200202200003220202210A002002000000000000000000FF34010000460180020AA2AA0A000409008C00008000002A92A82C\n\t84892A82A89102A82A84082A86180A82A82A82A8248A400002102A82AA0824000020022022220020020000000000000000000052e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200600620\n\t640214A1022121000024421025860860060000021DB02300200906360B00332310B002010000000000000000FF1643400C01\n\t400400400400000008000400460000000000100135400120100108101800120100D0000B8081005001001200000000000008\n\t001020000000200000400000000000000000000000FF6F87402400C00C00400C048C0848904D00C108008040001003002023\n\t503403403082143403003040122083113513003002000002012512053050142422402522012002000000000000000000FF1E\n\t7501000184180004380181180184185580180190000000064040060060060C6006016046496000206026026006106226000400d2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D80000098208\n\t0A04180000100A001801004049080000000C40812800E00E00640400210802602800600600604E0060060000060065060064\n\t8008602E02608E08E006010000000000000000FF864500080004002A0100C4108004002014100108088000041045604E0000\n\t300000900004500200000A60100000100100200000000002900905001100304200402100A8000000000000000000FF8ACD00\n\tC00002000002000413002002314D011001080000000015604608020002008014002410002040604014820800002000021020\n\t0280030000100020000100200000000000000000000000FFC8A20000101009000028008008008809008048408060000042100032e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400E24680024\n\t60B61462160460AE000000000000000000FF96F30000C180504200111200180380080113414B000000000600640000600620\n\t600400200004E00020030C08600624600600000420052610E04008E20640E046016406000000000000000000FF0DCD000001\n\t80184000190A0918A180D8210A088500002000260060064260260061044A200000E30015622608E306006036400006005017\n\t5160010372070070074070AE000000000000000000FF10AC0008019069000318480018A81889350388030140200406140086\n\t22E60619E07420244000622800801600E02601600E20000675600620607860618640664E006006180000000000000000FF8C00b2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AF09720E2AE\n\t2AF2A92B60422AE2A430F2AF4A72AE0000042082270260020260070A702702EA06000000000000000000FFF20F4002010050\n\t0000088982480B808810AAA80080000010048060000071460060064060010060000001061260070070060000061440060060\n\t000CE22614EACE00E00E000000000000000000FF375B0000430408C80AB0118AB8880C4AAB95510180002A0AAE2880A82AE4\n\t0E1262AA2AE2A8A060200AE0042462AE80EAAE0000040E0006006040106006016086786006000000000000000000FF8F4F20\n\t0011128A0000082180084002C8018018018000010006040006006B26097002006000106800000046856006106006000006010072e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (06AB8428AA0A\n\tB0099010800008010008AB00002A82AFA8E0882AE0062272AE1060003870000A80042862AE2AE2AE00000420202617701080\n\t6806026006006026000000000000000000FF8AC3000A01A04404000805801800101800001000000010000480604680602604\n\t68060060000068000060170060060160060000061070963168012175364062960060CE000000000000000000FF4C49000155\n\t910D541548258091400C3D4240095400005505565565305564164D655605635044E0145504574165565565560000064164B6\n\t406004406116207006526526000000000000000000FF265700008D0910880AB0A18AB8AB8108AA80003280002292AE2AE28E00f2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (016024436296\n\t0560460D60A6000000000000000000FF63890000418050000D5001840811800804114000000000008E006206006006006006\n\t0940000062C00065000060060060060000CC14230630628008602608629620640E000000000000000000FF60AC000001C492\n\t000000C188402984488C1348000000000006046001006806807006154D080570100000008168060060060000040C208E0070\n\t0003622E296296316896000000000000000000FFC2E700000190000000100583180208884100080100000008060064460062\n\tD6116006406040806000406334046006806806000004012C06C8E008486106806846846406000000000000000000FF599400000ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (545564C25325\n\t505565441504365565565565560000404520564165240160562D6056056016000000000000000000FF752C80000080000183\n\t180580084D845801800841800000200600620600600400601210000000600840600400600600600600000000200600600000\n\t6006506086006006000000000000000000FFEAD400008980100000108B8018818AA8C8020088000000020428E0AE2AE2AE2A\n\tE2262062A82AE0000AE1002AE2AE2AE2AE000204202006026000006006206106006006000000000000000000FFF6A8000003\n\t8B100000002190D043800820001844000000004602600000600600609602600000600420002800600600600600000400A056008ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (890001981889\n\t8008800200C797408180000062AE28E08E2AE2AE2AE2022202A82AE0000AE2262AE2AA2A82AE0002A841A506346000106506\n\t206006506546000000000000000000FF4D8D0008208C20010818058008018018008AA8000000006306006200006004006012\n\t0060000000002000060000040060060002880822860A60004C62860064062862A6000000000000000000FF9BD90000AA8A20\n\t018038A98AC88188988880088B00000062AE2AE0AE2AE2AC2AE2A222E2A82A82800AE32E2A82AC2AE2AE0002A80C202E40E2\n\t8844E02E02E42E02E00E000000000000000000FF9B6A00011281000105593192A95395591580095580000060365561305565004ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8100E1E70260\n\t06006006000000000000000000FF15C300000180000145180B821834094481C20000000000700640E00020610F00602F10A1\n\t0808A504440007003202003006000001106006006004816016806006046006000000000000000000FF4A5B00080080000104\n\tB843915830114009914422000000680602602600680600614710A0000022882060870028020008060000000C630610629010\n\t612608629620640E000000000000000000FF36C900000184C001A01801C40802400041800011800000600600620080600600\n\t680A0008008060000000160060028020060010002020560360004362160560460D60A6000000000000000000FFBB8F0000AA00cae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (620620300100\n\t44802000070050A012E90E12000014C00612635032602E006446306026000000000000000000FF79808080010C00A9809901\n\t800814014511014901840001682E04000000600EC1688314200200428044602610401000E006000000900086006000006016\n\t006006026006000000000000000000FFCE2780804012008B005881C08C01801820012801820000644604600181604620F086\n\t021001006000000046086016006006000000404016006000426006046006006006000000000000000000FFF58C8008000000\n\t41C2380BC20821A81811020D018000016A1600640714E8260076234008810660001860068668070168060010002181066061002ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AB8008050108\n\t0002400188182111204462D633044600602620604A10A10800000040003640040001600600000004641654610041610E3564\n\tC6016406400000000000000000FF1C1E000005800021800109001801803801000821808022602E00602601613620640E0880\n\t8808840008E02E28834C14210604000000426E20E45004604628E08E40E006000000000000000000FF86EE00004080000582\n\t00010108018898C100A8898A2000600641640056630600603241003011000800000600040400000600000020001600600044\n\tE086026006026206200000000000000000FF92C380000300010B291883C52C20040000280805800000628632848E2161121000aae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (250220200250\n\t2542000000000000000000FF0B0C00000002110002000400102200204C0000420000004000026006000000000004024D3600\n\t40C00060200040145040000000000080500100004302D00500400D00A0000000000000000000FFB24880004008403400C040\n\t00001000800004400000000000000060260000900000004900000880004062800A00A0050000000000040300100120000000\n\t080290200408000000000000000000FFA1D200000180080195080902584010810180A88D0200006006000108246206106006\n\t20284011008808E00611001000600E08000051600600E00010600600600E146026000000000000000000FF6DC80000018000006ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (516556CAC280\n\t55655742C4145065560000001560560160800160562D6056056016000000000000000000FF94E900008890280A89088A8AA8\n\t9088C8A088A88080002AA2AA2AA08A2AB22B2AA2AA08AA022920202AA212A8228B0822AA00000024A02A40A44044A02A02A4\n\t2A02A00A000000000000000000FFC73E10800000000002000001402020423020128200000300040040000002800000000200\n\t000000100000000810A00088040000002002804A00004C02800004002802A0000000000000000000FF25590000CB00984088\n\t08C80AA8C08A08808880DC80002AA2AA28868A2AE2222AE2AA0020042262020AA04A20E2464122AA0000003825023622021800eae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000024000204\n\t202009408800004A00000000000000300001000000000000800000000011401010000000002000500300004302D00500400D\n\t00A0000000000000000000FF64FC888000CAA8AA88C8AA80888089880080082080000022A828A4CB2A80822A9003A03AAB22\n\t22080AA2AA2832032432AA000000002002202618002002202102002002000000000000000000FFC87E800805049100044001\n\t00000442041242140000000000040040410049008040002208B504450000008084D005020804000000000000000100000000\n\t500080000000000000000000000000FFFB2B80014B955155911955D4190B9419038D58298001487556554116D56057556356001ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002002002022\n\t000000000000000000FF0F0C00020A0000000000000000202000002000000000001808800000000000000000808080000000\n\t000001800000000000000000000000000000800210000000000000000000000000000000FF423C0080000200020020202000\n\t1028800002000000000000000400000000480080100804000000010000000000000008000000001000010000004100012000\n\t00000000500000000000000000FF5A0300013040000000400008403000011404000400010088000204210004010014300B00\n\t01090000200001030010850000000000148300100100080000080290200408000000000000000000FFCB9900000400000004009ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030020000028\n\t0200280200200200080210200200208101200200201221A062000000000000000000FF91F3000003925901841801C0182580\n\tD801801801840000001640404604604640400600ED5654410004655600454605510600004600610700615044600F40600600\n\t6046000000000000000000FFE4940100110A800560404000100110A0012C200000000082AC08400080109003C80010000000\n\t4000000808004800004004000800000000800000004504824008001800000000000000000000FF03BB000400904880820A00\n\t800804804800800A00820000000120202204282240200280224A34208004254A0024C204A1020000420020820020A9242082005ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001000\n\t2002010000000000006006000004000800000000804000006004004800004800000000000000800001000001000004000000\n\t000000000000000000FF1F260000000008008008008008088008010008008000000202228102002802006002003002002000\n\t802002006002002002000002002002002000202002000002002002000000000000000000FFD7190000010B00000000000000\n\t0001260010400000000111540040000008800508080002000040000000100008000048040000000000000001000000000200\n\t00200000280000000000000000FF3AE6000000800800800A00800800800800C00E00800018100230A082802642002802002000dae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (022060068000\n\t00000000000000FF74C30800018458498010D58018418054010059218800400136000006006006102416C423050C00004010\n\t4600008440848600000610630710E041106007416416816416000000000000000000FF20F20000B188188180100100980581\n\t1911101009800000020600000000620E0060C608200420000010610604022402000E00008E01002642610000E04602600620\n\t6046200000000000000000FF41F3000000000000000000000000000000000000000000000000600600000000000000000000\n\t0000006000000000000000000000000000000000000000000000000000000000000000000000FF9F9A000000000000001000003ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C08010E00F00\n\t008710000640030632602880000000620E082010C06424200000000000000000FF014300003184290180092CA01805814009\n\tA89093800040000600000600600208242614608612400080014602010601002600100600612420400100610E834002016024\n\t000000000000000000FFC7F4000081881021809001811825A11001303C100C40100E9E0360000442000030C2303014A00000\n\t2808000C402402400E0000CE08E1041881A018E126A1250A01620EA00000000000000000FFD9AA080401801C09811001A098\n\t01A01081211825000000082604600600680A86200E0022040000000060021042042042C6000806806A04024000066916006200bae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018018814\n\t01800000180F8160008064060C20068042460020040000020020063020060004062A002E00E024906516106016206A860000\n\t00000000000000FFE4BA000409A41001C03821C35865820001C6980784410100060060071441000A21871170360160008060\n\t0600680720600640814600670016812101E02661000003489E800000000000000000FF6478000101800005883A0084180185\n\t0001809411E00050040600600000780000A04E20600600608008800E04708600600600800580600180580000604600628004\n\t4047200000000000000000FF7873000681C51A05900801803801800001801A01800120800600000008448301280EC0FC0600007ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (602600000000\n\t0000000000FF86BD000001205001880011A01E218858418018018000000806006086004407B022268048060060000060C081\n\t208E34A00E0000042060420020408060060000068C6046000000000000000000FFA57D00400501B8018000010618078E3819\n\t869049804004000600600008410600218640400600600440001A00A00600308600002621060246200C6A680780298601E106\n\t080000000000000000FF1FC5000021140043801001C01801809D0180990B800000002E50600610700F80A006004106402000\n\t0060008020060021060000270470120060080A7516C8E206006006080000000000000000FF5CCC000011010801A01241001800fae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (206016006007\n\t00600600040C006002002000006436C9802E006006000000000000000000FFC89400404180002D9080030018298019438234\n\t0980400608D6406100885C064A2C0680608600E00400014E806917446006200084A302A24022048A69864020061061060800\n\t00000000000000FFB501000001A450058440D0921803891841801845808000025600600600450600A02610601794002000E0\n\t0620400648400600022611600249201001720E403106506127800000000000000000FFD6E30000038C004180001040184180\n\t9801C012A5800000100708600000491609202540688640000420000700400708C01600000604003600202500620E112206820006e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080180000180\n\t0000600700600600600000480600600600600000600000680100600600100700600700600000700600600600600600000000\n\t0000000000FF71E1000001801041033088901801808841A01001810000600E00680000620001400720600600600400000100\n\t60000068060000460160060860040B600680612E006046080000000000000000FFF006000005845003001020A238518C0E01\n\t823855800005714600680700F0800440260A610F03602040E000206000306006200896346546C16209006146106006506106\n\t000000000000000000FFF3C1000003801011980005803805821805E00801800000840780600610C0061000062260077060000086e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF1FF20880018A9001001800801C01800C31809A01820040502E1462408071001468CE80640604600C8A0083016801\n\t006006000906026006806004007006006006006006000000000000000000FFC8990400018010010010008018018008018018\n\t01800000600620600600640000400642600E0060004060100060000060060000060060060060002862060060060060060000\n\t00000000000000FF118800000180100100100080180180080180180180000060060060000060000040060060060060040000\n\t00006000006006000006006006006004006006006006006006000000000000000000FFB633000001801001001000A01801800046e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010069400001\n\t06000806006086806041837006006086006046410000000000000000FFB460400001801001440000801C01800801A01C0182\n\t000170068A60260060921041AE2462060060182A608100E00100000600008702610600610040740610651615610600000000\n\t0000000000FF1512000001801801801801801803825B059041059400006557406540156B40856C0600614600632402050200\n\t61400061060000060060460064450D6006406006006826208000000000000000FF83C42A0001801801A01001811801801809\n\t80080180010060060062060060108B400610610E62600000600000600000600600000680600600600008600680600600680600c6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001C00000000\n\t6006006000806000804006006806004000000000006000001806000006006006006000006006006006006006000000000000\n\t000000FF6D23010401951801800800811801820C41C1180180014060564000060A6618096007147106006000000013006000\n\t8020060000060060060060004064060062060AE086000000000000000000FF8F4B000001801001600E00801801800C01881D\n\t01880000654620004000E0808163060060460060100062820060010020078018078060260065002862062860160060060000\n\t00000000000000FFA700000001801C01840000801805804905805803820180E01680630080604204400782610700654082000026e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFC1150002038008818418418098418A18031448280000046036000000A0618404ED061160060840000060062060020060\n\t0600029600648600600000600608602602644E000000000000000000FF6213080005B00A41C95B00C01C01ACAA132B3A8200\n\t00D2615680088E336D20C364470B7206C2489088080A426C00A46036000C8EC96C0E8CE810D268A68C6B2683680E00000000\n\t0000000000FF3543000001832A938018018919138019010018300000016206D160068060081060160060D688400000E34208\n\tE05009210600000602614620600080EA1700E0164862A6000000000000000000FFA7A100020180000100100080180180080100a6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A0087918400\n\t0D00A20A00900808A90C00910900880A80000000000000000000FFEE40040005800800901800880800800801008810800010\n\t300200400310E01600202A00200200200800200E82E13620280A00000200202208A00046A012002002002012000000000000\n\t000000FFA97200000018014F00810135008800100001004000000252000061960200000A42404006201200C000E3E014040C\n\t5040000000085C0008030000000128028688758000000000000000000000FF0C190004000080000140040001001100080820\n\t84000020080809600E090408201010088080250000006000C00000080C600000000081002000400002C000000000002000000066e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (130000000804\n\t824A00934B2C820914914904900C80800A0C80488C920804000D00900890840800804800D109089109500000000000000000\n\t00FF278B000005901805925015951901901801805801000000600608C00E1164C401611628640E08E00000602410600C04E4\n\t060000065461061060004164060062064C6016000000000000000000FFBF23040300C00F40C08D40C00C50C48D00D48C5280\n\t0114211300310200300B04244303300304302110311244350330214200149300340301304104313311308301344200000000\n\t0000000000FF7BD808050022242028229000021224A3802202030000088184B08800800A6081080486481C8008009808108800e6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t03E40008004500004004002002004044004244C8000000080100124100104140101010100108100100110000100000000000\n\t1001009001101001001001501109001000000000000000000000FFF232000A882400AA08A0040AA0AA0A00C8000090000000\n\t02A82884A8110400080000220A202080020A80002002202002A80000280002202880022A82A8020110200200000000000000\n\t000000FFF160000004840A00A40A0C800800A0AA00A28A208000802000802802C02802C0AA2280200A842800C029228B2802\n\t812802000802A52802802A80802802802A42822802000000000000000000FF8BA700002130C0002012C020140120024328220016e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (240AA80002AA\n\t00214A0424002A82AA0922C22AA2AA000000000000000000FF2C2F000C000100000420282002000A80020000040001001000\n\t0200000000001282280010890D02020000208C00010000000002304000800203020000004A02000000000000000000000000\n\t00FF183F0000AA1022AA0A00920AA0AA0A80AA0080040000000AA82A80882A82881302C02302A82480804A82083082A9288A\n\tA80002A84A02102081002A82A80402002A82A8000000000000000000FF6B9300013430235431030015415420231034C32000\n\t00000550D10930C40950A00900CD0440400900D50C90410D48550D50000880928C30C88800D50D50810820D30D30000000000096e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060460040\n\t0600600600620620410600602002E00600608608600600000620610E00600010600E006006006006000000000000000000FF\n\t65C30000012D12002404022012012002002213120000804804844800800908A40A8081480480CC80A008088B480008C00000\n\t0800950C40C30800800800810848800800000000000000000000FF9A6C00020080480080A920800800842800892820800000\n\t000200224200204210A0521020020C2000002122002002822002000002202082102280002002422002002002000000000000\n\t000000FF909D0004AA0000AA0940484AA4AA0880AA10000000010002A82880882A82000000012202A82004000A82412402A80056e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFF5F0\n\t002000801038808800800020940804808000800000200600040200200A00234241201610600000200A012002106002001003\n\t20300300200002300350B483043002400100000000000000FF6323400D014804004004004024000004004014000001005001\n\t4540090010110010010850012014003810112050010010000000000002080010080804082800000000000000000000000000\n\t00FFB7DA400440C88C50C10C00D10C00810C00D40C00810100300B00210B0030430230030830435030004030035030030030\n\t02010002002202003011043003512142402002000000000000000000FF3F320140018018018418018058418018058118018000d6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000064964\n\t8654E0000360660064A644630E0A0000000000000000FF697200000180180991100100004180902000004180001060260A04\n\t0800C20200210654000608601200210610632600600600000600604600604210408610610608624E0A0000000000000000FF\n\t761A000800004080084002008000008048000040054008013014E1560900500082000A012002050800654008054002800808\n\t00002102205404A8510300000008500120000000000000000000FF7F27008140008000040001110000011003140000010000\n\t00284561060000400200002040C0100240056000080100100000008000000080000000800A008000202000000000000000000036e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600604000600\n\t600400400600000610EC0000400600610E80680600004E00E0AE0A6800006046206006306006000000000000000000FFFBED\n\t0000018058318138010010018010238A5005800022E0060062200040520C20040040060060802002940064242A6004000486\n\t22620640E1000065060C613602E336000000000000000000FFE30E0000018058018448210A10018A3000011009800000E406\n\t0060061460AA01203600C05604620010620604E0060B601610100708708700E30822740740704F0070062000800000000000\n\t00FF8EA30008018019018298250B01A180301406918F854000E31601014602628206240E000106006100084046626006006000b6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFE8B80000\n\tAB8238838018AB8AB8AB8ABAA8103888800020E2AE2AE28EAAE2048842ACAAF2AE2A62000AE20CAAE224A56AAC0008A7206A\n\t070064002AF1360269168A6836000000000000000000FF68CF0002018418010208A180180180180008180380008068060062\n\t0000610C00400600780600608020000C00600401600600004E02640E20600000600601600E206006000000000000000000FF\n\tEBAD0000AB8998118058AA8AA8AB8AA88CA018ED80001C62AEA880882AE28421CAACAA82AEA361004AA066AAE01600E2AC00\n\t00060860060062002AE00E01E646006506000000000000000000FF2AAC400001821905121800800801800800011C018000000076e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000600600690\n\t6000006006006426006006000000000000000000FF7B764006ABA890AB8880900AA8AB8100AA821C898001AAEAAE28E2882A\n\tE0062AF2AC2AAAAE2AF0042A81062AE2AE20E2AC00042E9268060070042AEC0680E04E006026000000000000000000FF3D8F\n\t000A01A81041349A01000801801001051A0180008070070060460070D644600600200700680000710400710410600600040E\n\t0CE156356900004206D06006216006000000000000000000FF252A000155913155113005154955943154A2D9518000557557\n\t556150556446556556D52557556404150426D56556CC6D560000862160C614E484554156346506136336000000000000000000f6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02640048E006\n\t00650C006006006004000094006404006514000116106046016004046486106056056046000000000000000000FFC1050000\n\t0182182192180202180180400A801801800000600600600602608610E00412C00600600020620400600400604400022624E2\n\t8E28600048400E00E00620620E000000000000000000FF607000000182380104300A0018018C2000911C2180000060060460\n\t408041460060040040060068840008440068048A6804000A8628E2D6236B0400432E326906ACEA8E000000000000000000FF\n\t82D7000001801001A00A200008018082008038058000006006806006006C0E80600480200680640000630C80600400600400000ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (308B00015591\n\t200D90C93191395595308095108D800055655655653040E4465521025465565540045500965562805565160003560D605641\n\t600444E42E286056056056000000000000000000FFFD8B800001801001800851813801841900841801800000600600600600\n\t610610000200600600400000400400600000600600040610600600600000601652E206006006000000000000000000FFAF66\n\t0000AB8C98018098AC0C98AB88802188B88900002AE2AE28E0AE04422E2260242062AE2AE0020AE0242AE0BC2AE044000006\n\t00600602600200E026276686086086000000000000000000FFC09900000180390D0050000038018401008418258000006006008ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (106046016004\n\t0074C6107056016046000000000000000000FF89AA0000AB8AB0AB89088D8C18AB88183110481180002AE2AE28E28E2AE226\n\t2322AA2562A82AC0000AC2AE2AE2A82AE2AE0000060064061660002AE1062262861E6486000000000000000000FFB71D0008\n\t018000A184080180180180004D002021800000600600600008609400222A00E0060040060004260060200060060000064063\n\t060A6006104086006106486306000000000000000000FF603A0000AB8AB0AB9428818818AB88A8440100A380002AE2AE2AE4\n\tAE2AE2362222AA2862AE2AC0002AC2AE2AE2A82AE2AE0000AE42E12E20E0002AC22600612E40E12E000000000000000000FF004ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (860008060120\n\t1A6FE09C81C0000150274061D90068262082460860CE006020A02846067016066006000000000000000000FFD05500000382\n\t2C83829C01C21E01C0B001021001802100700600E00100644600300210722010600448400608600700602620801600608E00\n\t6025104006006006006006000000000000000000FFB3BD000801800001A3380380980184180A10B045800000600602602600\n\t700E00A00209600000600200400600600400680600022624E28E28600280400E00E00620620E000000000000000000FFB49F\n\t000001801C01800841A23801A15100040309800000700600600000608608200204600100400440500700600280600600011600cee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800411800801\n\t8A880104BC218509000280C1808100610E40820600208708300A10E80610621000C5268562B74069163400062060A6006000\n\t10212E006106406006440000000000000000FFDE1A800001801A01828C0B201801C2980A00280180000070065482209004A6\n\t00A00200600240400041400640684200600600005601600600600880204600608E006006000000000000000000FF00008444\n\t21800021900813001845840800084001900000600654604008208702200380610420600000404700740400700608040610E0\n\t0600601021210E006086006006000000000000000000FFEBFB8028039A3483A80801201C01A038140A020188200071660065002ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060000440\n\t56006006006206200000000000000000FFBD21000011901805800931845821801824104003084004640E0881264260CE2020\n\t4240E21200600000400E0060064160060000060060064165200060064C628620E026048000000000000000FF23300000018A\n\t180391188181180180182280300301200263064864A602242624A0A600600C04604000400E00650600614640000640614620\n\tE08051210608621606E206000000000000000000FFF1A20400418010418028298418478018008810090A0008E10602600020\n\t020E06220220666412402010400610640000E02610000600604600622033A11622600E006026008000000000000000FFF37A00aee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20224062AA2A\n\tE2020021002AA1A22AE0422AA2AE000002002402762100182102202282182482000000000000000000FF9E5A000000020000\n\t00100200000002C411901000000000000002620602C1000080040000040000000044000004A0000000000110140040010080\n\t008480100010050040000000000000000000FF876180000000A00000002000000010000200A0220000000000006026200208\n\t4C00000001282C8500006010000008000000000240208288080400440028028020200208000000000000000000FF57870000\n\t01821801823801801803849300050949040008E00602000000600610E28A10602610640800C54603602E00600E0A00060060006ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (558099559259\n\t55D559558A3C819259558001557D5655411748655600C136556C0CD56400156556556516D575560003560D60560164005164\n\t4E2C6056016056000000000000000000FFFF510002AA82A8AA8AA88C8AAAAA8808CC8088A880002AA2AA2AA08A2422CA0822\n\tAA2AA32A22A2002AA04AAAA4122AA2AA0000AA42A12A00A20022A22202212A42A12A000000000000000000FFF58E01000014\n\t200001040000000020844C01000000008000000002000480000C02010001240000800000000000400040000000004003002A\n\t00800200800001004A0300000000000000000000FF91B40000AB8808AA8AA8890AA8AA8508A086488900002AE2AE28C08A0900eee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04000A802802\n\t8020200208000000000000000000FFF2A4108000100000000000000000080100444000000080000000000002800023103100\n\t0000000000000000000500800800000110140040010082000480100010010040000000000000000000FFAD218004AA800EAA\n\tC208AA8AAEAA820820C808AA80002A82A828A0EA2822AA4030032AB0222AA0006AA2ABAAA0032AA2AA000002002002222000\n\t2020022126820A2082000000000000000000FF700C800A011000010004410012014024001000050001005004004440100000\n\t034000805005100000000400804100804004000400100000000000000010508200000000000000000000000000FF77AC9001001ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000088002122\n\t022000C8208280240340A10240020A002002A08000002002002002002002000000000000000000FFC9520000000000000000\n\t0800028220008000800000000000000000000018000008204100004000808000008098888002280000000000000000002000\n\t00220000000000000000000000000000FFA58C0002000000000000000684400B000800202200000A08410000000000004002\n\t009A0000000002000800080000080000000000000000000000000040019880000080000000000000000000FFE08A00040003\n\t200028A00040000001240A008000000000080002020100000008050000130800050000000000002800000000024020828808009ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0860800D8084\n\t08489F6800880D80800008221A222002002002003002102003002000002002002002002002000902A2B80200000110280381\n\t2002802002000000000000000000FF9356000401881881801809C09801081881809801800012602600400600680600632EA2\n\tE14620608250780480EC8E51610E400416806006200000006006024106006006000000000000000000FF0C7D000001001001\n\t0000010C3185040438004544000002148409D2006200040048051000040E4000000104100004004444000880800801010000\n\t484800C15000800100000000000000000000FF73FB000000900900800800C00A00A00C00800A80800000224000A802202002005ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF24150000000000000002002000000000010012000001000001006006000000000800800000\n\t000000000004000000000000000001004000000001001001000801000000000000000000000000FF520E0000008008008008\n\t00800001A0080080080080000820262240020220060020060020060068000020070030060060020000020028020000000020\n\t42002002002002000000000000000000FF397600000000000000000028251020065010000000008205001102004010002040\n\t00000001120800001000000000000000000000450000000000000800000000800000000000000000000000FFC64E0000008000dee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (262D63564062\n\t0200600010414600E006000206102006010002006006AB6844024204000000000000000000FFAEE2000001805C11A4585180\n\t0100411040800B01800008630600004622600601680F00620684630000600000520E046106000207426456100491406D4650\n\t6406046006000000000000000000FF890B00000D88180180188184C000001111801843000000600600020008402600624630\n\t6006116000006000004006016006000006006006440000116006026006006306000000000000000000FF7F70000000000000\n\t0000000000000000000000000000000000006006000000000000000000000000000000000000000000000000000000000000003ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (803101822841\n\t831100800C01800014ECC701004000500600704680F00600600000680020E03700610608009700002601000000680C840084\n\t000006000000000000000000FFC18B400041CC5C498089118528018290C880090480000864860804A654220710F01602E096\n\t24610000600100722E02608600000640202630000940E20680F424004106000000000000000000FF2D3B004001C01801A030\n\t61811408A0164488883180008050361065000060067066960020368CE5020110010840861064060000048A270C5286C05C64\n\tA4414410000114000000000000000000FFC29420004B8418418318018010908410019118018000806046106106006426D06100bee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060164020060\n\t06000000000000000000FF5E50002009901801E04941C40821C09201801809000004601610608180608E0060060060478060\n\t0400600681600620600600002E006206090004006106006306046806000000000000000000FF8D1300002188181180100180\n\t1809803144866C818000E0404702644600608E06618603202608E9000001870060162061060006243A89444204D80460E400\n\t4000020E06000000000000000000FF1B31000621801801800801C15809C45200E00900800110C30603600000600648644E04\n\t200E12F200008006206026106206080104A2900404190030620EC52008004116000000000000000000FF4704000011801811007ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (24AE00600C00\n\t0041086036106106000084006884009404006004044A02882006000000000000000000FFA0F9000001821821A01043800805\n\t841100928A8980000048060060061060068062060822060160020018268860479061060000040AE804008282006024044082\n\t802106000000000000000000FFAEE80000018318218250338609318390008208EB00000460069E600000C0BE876856006956\n\t02E01400601E2068060260260001060AE106040004026684808006102486000000000000000000FF6AF60000019059098C88\n\t01800C41803001801C05802000400600600601694600680605080604600401000640600E846026000004006004000004146100fee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (7BA19A018618\n\t00800801880000C01684E00628400614F00E10A00700600000010600600600600600001C00621C0200005071240C400205A0\n\t06000000000000000000FF8857000001825811A10011A01A1780580091080100402E400E82620180608601602719302600E0\n\t040100060070060260060000040260050401053860C5020902022486000000000000000000FF69A7100005801C1588110184\n\t3801C05808802B448221004146006006026216127006022006006514230100086006006006000284086144D1100C84620C00\n\t5402102016080000000000000000FF79FB000001911B01D02001A01C81A01900800800000080500600600108600600642F020001e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600600\n\t0000000000000000FF5CEE000000001801001C01801800001800800001800000600600600600600600400700600400280400\n\t0800806000006006000006006006006005006006006806006006000000000000000000FFCEFF000000001210001801821A00\n\t203801804081A04002684600600108630600402600604400200420000600600602600600040690610622600C006C07006006\n\t106016000000000000000000FF1CDA10400C021A03501B05C03804201E09800025B40049688701640622600E01500E82E005\n\t00AC8C028806886006006006000106826446116004846036886406006106080000000000000000FF3F3A00200980180180100081e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004080002\n\t20600200680600000640600600600401E007004006806006000000000000000000FF16B5010000001803001A01901C212010\n\t0508100580C100F03640E4800364460372A70B600602400094001680610604E00608141680720750E0010068060050060070\n\t06000000000000000000FFBBD110400000180100180180180300108100100180004062061260060060860040060060C42100\n\t04000406406006006006000006006006006004206006004006006006000000000000000000FF45F100000000100000180180\n\t18000018008000008000006006006000006006004006006004002000000000006000006006000006006006006000006006000041e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1A2080180440\n\t080994208260272062080B648EA0500400710C02209000100680612609605600000600600622640100600600280600600600\n\t0000000000000000FF456B000000001801001C01801A4080188110081188A024700E20660600E2A602D0A420E2AC04A04002\n\t020E00608606E00608020E20600644E401406006412007006106000000000000000000FF1DDE000000001000801881801910\n\t28168D00000195400061574061101565564062D6826116416314100002046152116C560008060069168070AC046806826006\n\t046806000000000000000000FF3FA808800000100080198188780018100100018390000660060060060060068042064A641400c1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (106406000000\n\t000000000000FF49980000000018010018000018010008018010010000806006006000006006004002806004802000000000\n\t006000006006000006006006006000006007002006006006000000000000000000FFEEB5004000001004801881801C45881C\n\t04181A01800081644715010684680600720482700644E00000100480600400600600080600640650600040600600A0060260\n\t86800000000000000000FF8CFB000000001E01001801E01889801C91201C010080006096000101007026006154006006A062\n\t2008000502600C0264060010078060960060A8246007222006006007000000000000000000FF06F9000000001000801801800021e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (22028001C002\n\t300810000000401A00481000021C0000200180600000000000000000000000FFDCBC080000081801885860301803000A1188\n\tB0418000786416000000A0680640620203E01E00600000200004600000600600008620618600600021628604620608620E00\n\t0000000000000000FF7E390800902A1B098C9A50013A89200943A4D32D000120605680088624E0268B6D02B4E8AEC16820A2\n\t0840106AA10A68060008AEA56C96906800B068C6886D26A4E82E000000000000000000FFA58F000000009825801900121805\n\t10081188100180000C650751601610628E20602200640610608110848820E01021650600000708602640702884E20625201600a1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200200300208\n\t0000811028B08810C002242C8090845000040880C00814800844204900000828840820400860800800980800800800000000\n\t000000000000FF1B17000000020840C08880C00988880903040984800000700600400200600A0221020824020020100161C2\n\t08E08200200200000200200200200800206200A022032022000000000000000000FFFBB700008C1042800000100000051040\n\tE8025010000002028000658E0C910110540000026138004028462C20050D5286800005004082002901100285000340081480\n\t00000000000000000000FFFC0A0000000000062001000A4000050400010022000004090009600603108001002170008040810061e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020000000000\n\t00000000FFAE900000000002002014000452242202012002100000A54004804A00A8C004000800D14000800A008B49248050\n\t04005004000C00A80808000C00800C109008288108C0000000000000000000FF8F7100000410580580180990580384182193\n\t3851800011600608C00600E90614630600600600610040400C0060C48062060002C620610611604811608602610601600600\n\t0000000000000000FFD372040200600C40844CC0A00C80D0C910C00D048001422C9300330B242003C0B01252BA3332304901\n\t35422434133020820010030C30234030810234231130032C3002000000000000000000FF272204040040802826020840A20000e1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8550450D5155\n\t0D50000C808908A0800C00D50880D00CC8D30C00000000000000000000FF247100080000040010C000004440000450420440\n\t00010018010010010200010010010110000010010000018010000000000010011010010010010010010010C1121000000000\n\t000000000000FF22CC0008AA0AA0AA0000AA08829008A0AA0AA10000000002A82884A88002A82A8AA80002A82A8000200200\n\t2202A82A82A80000284400200000002A8030010200220258000000000000000000FF7AEF000200400A00B54800C00808A00A\n\t00A00AA28000880000822802042800802002842803002800802812092802803002000902852D02802800802902C2A90290280011e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (820260300000\n\t2A82A82884880012A82A82A81402A92A80002512002A82A92A92A80002AA2022AA0020002AA2AA4600A20222AA0000000000\n\t00000000FF498400080000040041400000002004400000002000000A10000200000400000000008000000000002C08010800\n\t00000000000028000408000000000220020000000080000000000000000000FFD1220002AA0AA0AA0402AA4A808A2AA00410\n\t810200002A82A82A80A82882A82A82A84002A82A82004802A82A82A82A82A80002A82482A80002002A82A81084102082A800\n\t0000000000000000FF68B50003543541540C01543343023103543542140000C10550D10930C90D50D51550348D50D50C00800091e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFBB790000218018258018140AB811805809801821100004643600400604600610608610600400600002400608610600\n\t600608002608640600E00000E006006106406006000000000000000000FF938D000200001201253000021201000200290303\n\t0000800804844C2000480080080484C804804A0088492C804800804804000800800800800C00800800D10800808800000000\n\t000000000000FF307F0000008008009008000128448008508008088000002000002002B3000200200228200200200002A002\n\t002002002002000002152002002000002002002412502002000000000000000000FF7FAD0000AA0AA0AA4002AA2800882AA10051e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (500004000800\n\t2000C8200020110200800008900210000000000000000000000000FF5BEA0000208008A28008000EA8200008108008008040\n\t06A00A14008200600200A10200E0020020400C241211601A23E0020810031832030020014832022031832030020000000000\n\t00000000FFC98D400C0040040040040040040152040040440100010110055440090010214110050D16050051491050050010\n\t91000000000200000080001000108410500400000000000000000000000000FF94E3400400C00D00C10C00400C40C20C04C0\n\t8C00800100300300230B00302304324320301300B01300300340300322B0024003124020A210340300200300200A0020020000d1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (98028E400162\n\t460083B600620638E2460160C820600801006600608600602600000641620610E08004E0CE29662627619630000000000000\n\t0000FF51A00000010018039058140018818420010010A1900028600E01004000600620E30E00610008E01010201621600600\n\t6006000006106426426130086016102086006206000000000000000000FFED140008001000040400400000900220440200C8\n\t00002880B0206016400020000050110040110080110000420220000000000000210040340248140020050000010410080200\n\t000000000000FF085D00000000000000800A00000808201501204008000042205462060200002A44A042000C0080A00440000031e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF98A140000192184180180000180482004180280480000020060400060060060D28160064C0086800450006006022006006\n\t00000600E046346800306046206006006126000000000000000000FF206700000101188B8018240018218038010219208000\n\t00000600602000600420010600601420E04000012600608C00600600034E44650600E0000465060B61364262160000000000\n\t00000000FFBF7700000102180982184002180188182D029812800002228632620620622600200608600C2061400202060C65\n\t4C01602600100700700700E201217106427047407006400400000000000000FF12BE00081912198988380A0018718800010000b1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (08D565560000\n\t964161560260043561164D204648E126000000000000000000FF771C0000018C18A98AB88A0ABCCD88DC8C88D83000002A92\n\tAF2AE08E2AF2AC3292AF2AF00700E8202212A72AF280AAE2AE0012074070B70270008974360A680742610600000000000000\n\t0000FFA472000001801843801800001C0280180CA48A02800000300700620080700500108700700712600080108F00712200\n\t60060002460A6406316000006046006286006206000000000000000000FF1FC30000018038058AB8880ABA8988808B8C9908\n\t80002A8AAEA882882AEAAE802226AAE940826000190A0EAAEA42AAE2AE00004609640E40606000E10E00675609E4560000000071e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800080680680\n\t6046006804006006806802C4680000090680682080600600000600600688680080600604A84E08640E000000000000000000\n\tFF5BF14000018AB8118AB8880AB8A108800308100080002AE2AE28E088AAE2AE2AE22E2AE2AA007001AA820E2AE2082AE2AE\n\t000026826006027010006406202096846036000000000000000000FF70BA00080180D8018018400018010400400018048001\n\t0060060062470060040060060064122A600080001600601000600600011612600611600022600640A0061068060000000000\n\t00000000FFDC720000019559019559521559311541205032A8800055655655613155655655644E556552216014550446556400f1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFC3\n\tF200000380180180180000180502384404500280002160060260000060240160060060460062245100060064120060060002\n\tD60060061060244561061040060C60A6000000000000000000FF5D770000018018018018000018000098000008C080000260\n\t0600640600620C5060060060840061000000060060C000600600000624E50622628008645604E4C620E21600000000000000\n\t0000FF59B40000018018818018020018020018000280A4800000600604620000600400688600600411601000002600610200\n\t6006000A8E48EACE2160102AEB2E086206457086000000000000000000FFD90900000180182B801840001A110443490038080009e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E2AE00002E02\n\tE01602608024612631003602600E000000000000000000FF825A00011395415515580195595291195084D88A000000E55655\n\t61305564064B25565524C25561061265565561065565560002D60D628634630640E2464422462460B6000000000000000000\n\tFFA3C58000018000018018018018048498008418000000016000006406006006100006002000006000004006006006006006\n\t000506106506406410016406002486406146000000000000000000FFAD840000A98AB8AB8AB8000AB8A90818880898088000\n\t0862AE28E0AE2AE0840262AE2AE20E2AE0000202AE2AE0002AE2AE00000608602E00E04000600621410E00600600000000000089e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (016804006440\n\t0068060110060061400062000068060028120068060000D6006006006008C561060020060C6086000000000000000000FF31\n\tF20000AB8AA0AB8AB8018AA9F08A488280504100003862AE28E08E2AE2AE2402AE2AA2402AE0102AE2AE2AA2222AE2AE0000\n\t0648606E11E00018601606200E116406000000000000000000FF313400082180000100180180180082380490184000004C60\n\t060064000060CE00200600201200642040E00600443400600600000620603600E0000C610E08201608E20600000000000000\n\t0000FFF53E0000AB8AA0AB8AB8018AB8008818AC88990A00002462AE2AE0AE2AE2AE2082AE2AA2882AE4802AE2AE2AC2B42A0049e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF445B80\n\t0C09C00401805C01809840801C20A118008000025006006186007006C8100602280080600020F4160077068870061B000682\n\t6406006040A16086042506006006000000000000000000FF7F37000209A00001401A01C10C95800843C01000000108700600\n\t605000710E8A000E32E21040600500702720B04310700602000602600608E004426117006026006006000000000000000000\n\tFF2C08000801800001001801800811808C41D010480000026002026006006006140006000808806108006006002102806006\n\t000406A4E5062A628000645648C4C620E256000000000000000000FFFCE5000001800201801801800804802810853105000000c9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000016286006\n\t016040006086000206206006028000000000000000FF701B8000018000010258018808308048208218318000281086000006\n\t08E006A0201610600203628000ED07108090C068060000060262AE0160B014642610609614E006200200000000000000FF9B\n\t8D808001808041A03801A02B0A800900A8380180008040045500291068064020C648611242604100600E5008A00060060080\n\t0620628648600004E0170C22C6006006000000000000000000FFF2D681000180802102180180580080190090580080000240\n\t424D6001106007002347802082026020436006086006006006000016406086206000006006106006006006000000000000000029e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0041000040E0\n\t0640604C20600604E2D000628609000820604600000630600600600000620624E406486206000000000000000000FF565300\n\t002180000180180308002480410A8058B5100020608612000E0C63160063040864B600600000604E20014010601600000604\n\t64D649654044E026004016046016450000000000000000FF157200002180001980586300101380108B801883080010E0060A\n\t600E00608E0142842162AC00602807600E20402400600600000600600628621030E10632E10601620E000400000000000000\n\tFFA1A80000018000018C180102104082100481380100A010624620E00022631604C43401A40400600004646601400408602E00a9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFA4AB0000AA\n\t8001008AA8C808A0AA8880AA8880AE800022259228808A2AA2AE0222300020022AA0420422AE2022062AA2AA00000248206A\n\t11A002102012450002112402000000000000000000FFE28A0000000001200000040000010040010000010000000400026006\n\t00000040401000044400008000800000410C0000000002D00000004004004502400000000800A0000000000000000000FF38\n\t3680000000001400004004000002000002200000000900280062260000000900802A81100002404A00001480400000000000\n\t002485000C01200801105484C8228210000000000000000000FF2AFD0000018000018C180102000182002184180100A000E20069e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001005000000\n\t00010500004480400140000000000000000000FF263A900555800155D5595590990B909D05955D1580001568565545575575\n\t574D65564C7456556000D5755644C4155575560002D60D628654650040E2C648E2462460B6000000000000000000FFC86500\n\t00AA8004428AA88A8888AA88AAAA8AA8C880003220222AA28A2AA2AA48A2A20D348A2AA4004832AB2A22432AA2AA00002A02\n\tA0122222A024202210203202200A000000000000000000FFBEF6008000400000200000424020022030001040000140030000\n\t40008040010010048081010044080000001050A00050000000002000300080080C000802001008820000000000000000000000e9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004000100089\n\t00004008100002000010001200810010000004002485000401000005101004C0220210000000000000000000FF449D108000\n\t00000020000002001400212000021000000300D00004008000000000000480010000880000008108500000000000D0000000\n\t5004084500404480000800A0000000000000000000FFFB1A8000AA8000AA8AA8AA88AE208888008AA880800000200228A08A\n\t2A82A82222AA0822A32AA1002AA2AB2032022AA2AA00000208202A00A00008200200210A00A002000000000000000000FF2D\n\t4C800801400208401001245000041200001000000100900000404100400482100540084100408100900500D10C80500400050019e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B2100100840A\n\t10812800804800800810844A88884004100210215240204A002002803203082000202082A422820A214A10000204A00204A2\n\tB0002002412002002452000000000000000000FFAA4600002209000008000040000000800000000000000000000000000000\n\t008000008000000000800A0408008030210000400000000000000000000000800000000000000000000000000000FF058D00\n\t0400000000004002188000004420200000000000000114000000000000000028000000000080000000000000020002000080\n\t0000000000000000801000000080000000000000000000FF525400040000000000000000008002040C0000220000500200020099e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0800000000000000000000000000000000FF9AD5000000820C06804800800800840802A00800800100301200A00206200200\n\t3802013002002200002002003003002022000002002002002000002002002402002002000000000000000000FFBDB9400023\n\t85100989580188D801811C09845D119040027006084156406056006006A0740790600028650EC4E506156156500006856007\n\t056550806006416006006456000000000000000000FFABE63001031014000000054010830202E80AB028000000420C204008\n\t000000804820108004004101040001284054604400040001000000800000000000000200000100000000000000000000FF2C0059e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF24180000000010\n\t0000000000000000020000000100000010000060060000050008048008000000000000040010010000040000048000040000\n\t01001000004000000000000000000000000000FF5136000201A21A00A00800800000200800801000A0000064060A80020020\n\t02006002002002006000002003002006002002000002002002002000002002002802002002000000000000000000FFC91A00\n\t00042000002000001000822020B40AC02820010000012040100000008000200000050002000000005040004000200000000000d9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000380000388\n\t1009819101001801801869000080602E0060060C6086006C0600110640600020600680702690602200082280688000402020\n\t6004802086004A06000000000000000000FF707B00000D800005941841A40210001809911C05000000602600008640644750\n\t6106040206006001006C4640632644602E100446006120004240D06414007487406004028000000000000000FFFDCE020001\n\t800801801809800000001881003889000005649620040011408602E046408006006050206006006006006206000006006200\n\t40400000608444600E00620C000000000000000000FF7F7000000000000000000000000000000000000000000000000060060039e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (30D900107004\n\t01104C014006000000000000000000FF086B000401840401801801800A0080180B923A21900120600E4400000860AC00600D\n\t146C0608600190500402688600600A00000A4A5206414080004484008056804006000000000000000000FFE2720200018000\n\t00820821E40888801090909885800002E0062000060164270071262361062060000064470060060A60121004020062202062\n\t0010610D422416004006050000000000000000FF6A5000000990040110100180104100180181381100008062860062802264\n\t046AE344410206006028044404306286F06240000000014014144000D0420440280421480E000000000000000000FFA2BE0000b9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C60560064964\n\t0604601000704600600600600E00100700F020204000006004046004026026000000000000000000FF8356000001800000A0\n\t0001800800815803001000000040680780600022E80600780634E40600600000600608680620600600000610634000400021\n\t6006046006006006000000000000000000FF7C9700000194022330902180180780B831955810800018718600620632F55442\n\t6304806006106003645464E072060060100000900140B404400200CD1E421004004006000000000000000000FFB8AE000001\n\t800022008841801841801020801840E800006016427A000040060464560078060060001060070262861060200000802468000079e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (808002000C01\n\tD21C018012020C182800000260070060004462240060448464861460A904400400E006006006000006004020006028004006\n\t007404806006000000000000000000FF67550006218000A5001001800A008018018030010280886006006086027804206824\n\t0278461060A082400400F846406106000806404804006128004004006404006106000000000000000000FF5BF60180218000\n\tA180101FC1081084B829001041000088602602609000609C12E00420E12600600401C02414600630608E0018060048068040\n\t840140048260061860A6000000000000000000FF7CD5000209810400008001AA082080D84B9410100000846026046006204200f9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (105464060060\n\t06042106000000000000000000FF1ADA000001C020111012A5981805841801801920000003602711600600400400608C8860\n\t0600600000400500E00608E10610002620C2E41260000A4206426004606086000000000000000000FF95AA40A00180008809\n\t2803C11A51841801005C82050008E08608E01000680450E00490620E08600400C004146846926006000006C1400E48420401\n\t4004206804066026000000000000000000FF7E0B200001800043009001841945831510805A10020040600702650790614400\n\t680422E1260060004040A448620E206086080216004007414010204005007405006006000000000000000000FFC7940000090005e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200400600600\n\t0004004004006006006006000006006006004004006006006004002006000000000000000000FF36B8000001800001001801\n\tA018018018000000008000000007006006006006002006806006800800004004806006007006000807006006004000006006\n\t006804002006000000000000000000FF86C6000001A00000005A01801C21801808202008820000200604608000600600000E\n\t0C689608600400E10420700612600600000600E086204404006006026406002026000000000000000000FF7D3F0140018020\n\tC5011B4184190181188020002280004C012600640610712601008620EA2680680040602409621721680600025640621603400085e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00001C118669\n\t43BF428001400180008A000700600600600600080E0067060868000030060060060060060008060060060060000060068070\n\t04802006000000000000000000FF6CA8010041800201801801A0880580012320101580C00C854E32E0A804E44E4004AF0C60\n\t461160040025448360A600704E000486806006804004806006006016006006000000000000000000FFF63F00000180200100\n\t1881900811800001001021900040000600600640600600000641600E2060A800201400600600640600000600600600400000\n\t6006006046002006000000000000000000FF98FA0000018000000018018018018018000000008000002006006000006006000045e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (680600608600\n\t4006000000000000000000FF5E9E000001800200005201B01891809AB2800808912080230F5360A902633620222A00834701\n\t655000680600E126A068B600000600E107806000A0F006036006800016000000000000000000FF6BB4000001800101101001\n\t801B21801944800A3888A02082AE2AE0A622E22E201AE23A04AE20E0A80062AC00E0A640622E001286006006004550416106\n\t406006100106000000000000000000FF6C18000001800020805801900811A1201030A0019140040356D5655004655644050E\n\tA56156016D4C00200681654700655600000681651600600400600602E90400600E000000000000000000FFAC17008001802000c5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (406004890000\n\t00440E12E00600602E00000628628620E00002628724640440C026000000000000000000FF0FD6000001800001001A018010\n\t01801C0100100180000040060060000060060040060060040000000040058060060060060000060060060040000060060060\n\t04000006000000000000000000FF1BB10000418000A0881511910911816045817A050000002006000017006006002006A900\n\t06000000000006044806006006000006006006806000006086206056084086000000000000000000FF705800060180000180\n\t1001E00801800401F11801E00004204600020000600604288302181600000000000400540600640780000600640E0042D0000025e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060A22240000\n\t010E0000000000408820296007008A0806846002008812009020000028000110000000010000020040000060000010808000\n\t0418000000000000000000FF4DAA02032180880188185180C1718800810D1029800000621602000011608600609609602604\n\t000008808604640628600640000638658638E40014E01E006014006186000000000000000000FFEEA40200B1B12309D29821\n\t84A341A4C28D3232918000C260AE82080EAAE126944826946AB6C40890B288A6C06AB6C86A86040AA680684E886890D16856\n\t88E904806B16000000000000000000FF5E6100000580002380380B901209901841009023800010C206D1610600620E00E30600a5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (11304310350A\n\t000000000000000000FF74100004492C021A2050005C000022024020A2D60000801080908840884804000A00801000A84840\n\t800C00908889000A00000A80800808810800880AE0800A44800800000000000000000000FFE82E00048080196494A000C000\n\t0885E810900800800000300600400A00302210200220220200200801622A00300600241A0000220020020020080020022020\n\t00002022000000000000000000FFCD5200000210108002042000028010002102510000002A40080061962200108841001404\n\t0040C1001641000202200001E00304000000600400900201000B0400308200000000000000000000FFEB64000004002000000065e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02802800A22A\n\t028030020028D2800832942A02B12810832882C02882912812000000000000000000FF4D0700000120123228D00102104123\n\t02C02042220001000004804820824C0C0009409000010048088148B0001004804A00000A00C08948840800A80C20800A0C84\n\t08C0000000000000000000FFB0C6000243901101943801905801801815905881800000600608C04600600E00651608EA0608\n\t40C00A400682600610603640020600600604600810600600620E006006000000000000000000FFC83D000100C20C34C00A28\n\tA20B28D34D40C30C4C800120281300311208A00394302302300342301100B2831024020033020110830832C350B40122312B00e5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (152110314208\n\t3143300000550550D50930021080D50890D48550550800881050D50D50550810800840AC8808890810940A00800A20D08C50\n\t000000000000000000FF081F0008004004104122000124044004204004000001000801001041000001001001100001001001\n\t001001001000001000001001001011001001001001141001001000000000000000000000FF3E3B0008AA0800000200AA0880\n\t8C00000008808800002A82A82882886000002A8000220AA82A80000900002A82A82A80400000800000000000000001480E81\n\t20240300000000000000000000FFF40A000200A54C80A00800A02A02B04A0CA40A00800080200284280288A8C2802C1280A00015e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020020020000\n\t00000000000000FF052B0000AA0AA0460484AA2C00900AA0180AA0CC00002A9AA82884882A82A82A82A82202A82A80182A82\n\tA82A82A82A82020003822AA5422A80082AA2AA28A2A82A82AA000000000000000000FF8561000C000B41400A420040042002\n\t012204000400008010000002010882280002200010008000084205000000000003000002900002A024000041000829000800\n\t0000000000000000000000FFF66F0004AA0AA0800800AA4800A00AA0820AA09000002A82A82A80882A92A82A82A82292A82A\n\t80002A82A82A82A82A83280002302A80002A80102A82A82102A82A82A8000000000000000000FFAF7A0001542002142101540095e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (311105300300\n\t3483550002002002002082413000012412103082002002000000000000000000FF7A4712004100380D801801901801803801\n\t8A1801810000601640400600E51643620641628600604040400620E006000006406036006206006200006006406046006006\n\t000000000000000000FF6A540000012002114402010294092002002002000000804004844800804804800800800804804800\n\t804804801004000800000800800948800800800800840800800800000000000000000000FFCD450002008009209028008028\n\t42800924800842800000200000224200200200200210A0020020000020020020020000D200205200220200200000200200200055e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200000090800\n\t00000000000004600600809024C5000A840000028800C000410400D400000040400004002140000002080808800060000000\n\t00000000000000FF306B02000180280B0008000C4980822820830840848001210A0480024066020021022020860021203220\n\t0209208210880220300B043402002201203103202422003002000000000000000000FF90ED400C0040040040040041050008\n\t04C2402000002100500524400900102500102800102908540100500510100400000000000000008000100040800000000000\n\t0000000000000000000000FF6D6E400400C00C80C00C00C40C20940D14C04800802100300301200B0030230030D20C30330800d5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (700600000000\n\t0000000000FFE0F20008039E38098A78420098038C20A08E0045884030610620020604640E1180020764160062006105EE11\n\t600602000E00600600E00608623000E20609E00E0162A6100000000000000000FF6A8500000980191194180C029801900009\n\t88800903000060060A800040608E00012A08608600620000001624610600000608600601620610E080486406106216006326\n\t000000000000000000FF476F00080800008001003000000002800A00010C00A0080000096006028100080048090490208000\n\t00840032010820000010000020000801010834005002000008E000080000000000000000FFD5FA08002000110000000002800035e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (244846A06AAE\n\t2A808600241649600600A000006486146B12216006000000000000000000FF86DC2000002258090210008018018020008058\n\t10800002E00600000680600600012408E03600E801004416006006000006002006036026042C0004640608E0460160060000\n\t00000000000000FF3AF30000010090A480580102580180182080002180000860060462000060064D00120060861462801501\n\t260D400600023600054E40628E48008031602E4461100C62B6000000000000000000FF8D0E00000300380181180100388580\n\tD8C3800081880040E00620620600E0060000020060064161000800060060164C10160030072270160022210370B70460041000b5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (213190013100\n\t00C46D56D56550556D564C28C6556D574CE28440AD56556D5655042E0060060060465562040161161075540064C600000000\n\t0000000000FF99210000AA3032C028B8AB8AD8AB8818A8C8B8098000806AAEA8E08F2AEAAF000004226A0E22628028E80F22\n\t4AAE2A880E00084604680E1302010AE006C162222A6AA6000000000000000000FFECE5400200001020001001801801809802\n\t82B80480000060060060010060060004040060068060000A60070040060000860004CE2AE28E00010022644622600608E006\n\t000000000000000000FFBEF90000AA0818052C98AA8898AB8E808A8E81C78000B06AAEAC84A82AEAAE540F04226A062060000075e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF4CE2000001801220A01800833801802000A00041800080E80680600600680600020610E80600E200006806800806\n\t0008860068860868CE0060008860061060000060C6000000000000000000FF7E6F0002AB8AB8078AB8AA8858AB8800A088A0\n\t8300003362AE28E0882AE2AE2B009E2262AEA0700522E2AE2AA2AE2A802E0060268260062AF0041060268362A84668160000\n\t00000000000000FF5FE2000C0183101080100080180180C205800001800044E00600604600600600A03609614710E8008025\n\t0611000600052600608690634640690040694E006004006016000000000000000000FF1A0F000555B55909B551549319559400f5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AE0B42AE0000\n\t0640650608E50E00600021650601620A2AE146000000000000000000FF892900004182102280102180180180B80080188500\n\t0000600602640000600600000E4060060060040160064040060000160162D600604645608404E20600604200409600000000\n\t0000000000FF78DE00000B81300094D80180180184180092B820800000600600600600600614808613400600610202000600\n\tC0060004C64A600624650608640208612E2AE082006246000000000000000000FFA099000001A01090801001801801849C0A\n\t8218100000106006046240806006810046006006146905100006004006000206006216216206006C8422F30E21600228C416000de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (88A88C80002A\n\tC2AE2AE0AE2AE2AE2A83201142AE2AE2802282AC2C42AE00020E22002E5360262843000260262263042AE00E000000000000\n\t000000FF8D8500015583411200B11195595594295591482200005545565565305565564825485445565560064C0556406556\n\t0004160C005604604650C00604604E4C6546556016000000000000000000FF8AB780000580000100102180180182C8018208\n\t20000000400600600600400600001020400600600000000600600600000610028600628605400000E29610E0560060A60000\n\t00000000000000FF42D000008198108880188B8AB8AB8818AA84181980002AE2AE28E0AE2AE2AE2402260022AE2AE2002862008de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFBFDF000201A0010900101180080180294100081000008048060060000060060030900848070064040930020030068000\n\t160508D600600601408404E0060065060060B6000000000000000000FFC5650000E98AA1570AB0958AA8AB88881100082200\n\t002AC2AE28E68E2AE2AE2A82202442AE2AE0003002AA01A2AE00014621000608E01E2040007060060060062AE40600000000\n\t0000000000FF6FA00008018000200A1823801801808801800880800000400600600000400600A00000C00600628400800414\n\t40060000A600800651600E04428428600600600C006206000000000000000000FFA09E0000898AA0010AB8818AB8AB8808C3004de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (780600010600\n\t000600E006006000106116006206026006000000000000000000FF15DB804C89A00035060201809881828803804C00080100\n\t52060060C6006A06C0500001120700640001100F6074470788060090862A690601454048E08F026106006006000000000000\n\t000000FF44BF000001800020803401848D01841803021A00080030640641648002601708200000414F046004006002022007\n\t08000E00814632600600600401600684600C006006000000000000000000FF14EF0008038000208012238008018218151338\n\t80000000600602602600700680200002C0060060800240033420060014C6080406246D460C620008652E2AE034006206000000cde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0100205A422E\n\t6360002042B61040980840B60062080000042446061803060000060061060B40A00860A62264242C600E2000000000000000\n\t00FF525A800001800100854A0180080388080188890A820000688608000600600604600020000681402208600003012F0100\n\t060C00060AE00600E00A02600E106106042106000000000000000000FF9B8C822401800009002881820A01800C01C2280080\n\t00004026140220336006A040400080A602421000A0000000260000160000260160060044A020600600608E00200600000000\n\t0000000000FF6DD2840511E00000800901801801810C29C008008001807046146001C8FC0600602800040600600980401600002de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t4BA300000180090180184188000582180180388184400062362300000040270261120260C600E04800600000820610800600\n\t00060060060C608010E146106004442306400000000000000000FFB30F0000818000418AD0118020018008818C8851090011\n\t61061000464463161044002062060062000062000200160002061400060D64464160500464160160C4002006000000000000\n\t000000FF4F9D000081800019881805803001905885801825888004E00600E02602600E086200124206006000106204404146\n\t00000600000600622620600000E20644E004106216000000000000000000FF65D200000180002500102B881001822853822800ade040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000A0000000\n\t510008000280080000000004020200000000000000000000FF7AFB0000AA9C49148518AA8880AA8AA8890AA80080001C22AA\n\t28C48A4022AE8120522022AE24208007A2D62062AA00014200000208A01A0020001020020022102AA4020000000000000000\n\t00FF36D000000000508000800000000000100200100300000040000260062000000060440280000004004000240C40000000\n\t100000D0000040010000448400400020006090000000000000000000FFD8AD8000000280320A200002400000004000013000\n\t004500000062260A80003483100800001500001000100100000004C00004002405005203000801480C811000624000000000006de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (012090040040\n\t41001004B204040B1005000100800884145004000001000280000280C000000080901080040000A0000000000000000000FF\n\t55D5800555F5500D913555949D55D13955C339538000556556554516D5755654755445655655640020643445455600041680\n\t005604604655600044644E4C6556516016000000000000000000FF381C0000AA8008208828AA88A8AA8AACA88AA8A8800000\n\t22AA2AA08A0AA2AA0020822022AB28A200C8320220A2AA00020A00002A5320230AA3002222222222A22AA00A000000000000\n\t000000FF2A960880010010A0020000204200020000100000000100100400000000100101000408100000008015008008080400ede040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF56CD\n\t08000000011200000001020048C00000804000008000000204200008010008000000000004000089008C80000002C0000000\n\t2405400001000801280C8000000240000000000000000000FF490F0002004000200202000400000000002004020000000000\n\t0000000000000100000900000000800000100008000000100002D00000000002004484004000000200900000000000000000\n\t00FF10C58080AA8AA80088A8AA8828AA8208AA8A2C8880012ABAA828A0CA2AA2AB2A22AA223AAA2AA0002A32232032AA0000\n\t0200050208A50A2AA0000121020122AA28A142000000000000000000FF68CB80080141100000100142140100040300000400001de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (014008010008\n\t01000140000801005044800000000000000000000000FF68BE000000A00A0080080080082180080580080080000000202120\n\t0200000200000009200000200080220A00200220000200200A002002002080002002003002002000000000000000000000FF\n\t618100000008020012800000000A00800824000000002002000000000218018002002000C800000001008020002805000000\n\t0000000000000020000001000000800000000000000000000000FF2DCE000004000000000000000100000000080000000000\n\t0000500000000000000008000000020002000000000800000000A80000800000800002000001000020000000000000000000009de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (480002420800\n\t4024004001004800000000000000800004000800000000000000000000800000000004000000000000000000000000FF37FF\n\t000004A008008008008009008008008008008001002002002002002002002003002000002000002002002002000002002002\n\t002802002000002002003002002000000000000000000000FF99DA0000018818018A1801A0182B8098058A1A018000006026\n\tC1400600600600700600E0A802600200EC9600780E4280060870160060060060020078060060048060000000000000000000\n\t00FF1D7F000001001000011001001000009010221000000042440402C209844024004C145040000040010040044040440000005de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF57680000\n\t0000000000000000000000000000000000000000000060060000000000000000000000000000000000000000000000000000\n\t00000000000000000000006000000000000000000000FFC73900000000000000000000000000000000040100000000000060\n\t06000000000000000800000000000000800000001000004000004004004000000801000800806000000000000000000000FF\n\t9655000000801000800800C00800011000A00800800004280728800200200200200600200000200200700600700200000200\n\t2002002002002002802002004000002000000000000000000000FF3FA600000000000000100000000000000024000000010000dde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (220491803204\n\t20200060502469C0226800040000000000000000FF9D7D000001A01841921811801881041831C01801800000600604602600\n\t6486406136006000046000406106006046000806002006002082802000026044027008406000000000000000000000FFDFCE\n\t000001901805801801901A20003841931851000050600600002600700614702609610050602002621640600F000046006517\n\t0060460164A0D06006D26144841000000000000000000000FF55CD0000498419118418018018800018018019018000026106\n\t00040020610600600600604000610010600610610605000600600621608600600002420600600C0080000000000000000000003de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A6000006006\n\t206407006200207000086106006406080006000084100000000000006000084202806000020000000000000000FF767E0004\n\t01801001801905809B08821821E01800800101614614008980600600620640620000600000F08600600601028C0005060020\n\t80400000806104904416400000000000000000000000FFFEEF000049D4111508180990184080180980988880000060860002\n\t0600700632700E09610032602104648E08610E05102600210E402002012280486424104847010000000000000000000000FF\n\t2BD20000018008218018418018411378018A593100006E64060260013063064060860060204060813C60062064269000040000bde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (091A00020188\n\t0801001841801800801001801800000010600600E00680603600600614640008600420685641600601000600600400608700\n\tE004004002004804046000000000000000000000FFAE7E0000018018016018018118809010C1803800000000610780622030\n\t680780780640600000600401620600600600011600E40E00610610600400400642414CC06000000000000000000000FFC34D\n\t000001800001801845801801805899A81910000101644600633620710600600680600000680004620600600601040400800C\n\t0100704D800000615020400201E000000000000000000000FF75A3000001800001001881801831E29801881E00E000246006007de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (816006006004\n\t007002C06400006000000000000000000000FF75AA000001810D15449C21841801801805C018008000806087006001206007\n\t1064060261000060042A62264060060000040060840060868162040060A208E000026000000000000000000000FF3B6C0000\n\t0180088DA41A0180180083140582381000200060060060064160060061064061000060101478860060060000040060041064\n\t06406310004002015802006000000000000000000000FFC69A000001AD1861815801841D0082940183B986002068690700E6\n\t0010E02611640608620000678C80640610618600810400610608601610608C004D46104042006000000000000000000000FF00fde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (069160C60000\n\t0E80700E00080E1060460060068C69060068040D4006146004286046445806006006000000000000000000FF3960400009A0\n\t080182180180D801801801C01820000044600EA961060860060068A60070000060000060076170060200040060048A7006CA\n\t60002060021264CE006000000000000000000000FFD112000001840C0920D8A1803901881801C03810000128E20600E02112\n\tE03781610640600010600788619611E00600010C006004806416706006086423086066806020000000000000000000FF01FA\n\t000001810801801811801809831D45881910800002710604608600610603680E0060080060140160461060061001040060140003e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001801\n\t8018018018018018018010000000006006006000006006002006006006000004006006006006006006006004004006006004\n\t006006004004006006000000000000000000FF93C3000000001801801801801C018018018010000000006007006007006006\n\t002006806006000804006006807006807006007007004006006004006006004000806006000000000000000000FF897C2000\n\t00001801841831801811A81881801020000000E00644602004600684812600600600000501608610600600600E0060160048\n\t06006006006006004112006026000000000000000000FF827B000008011811C09881811801A49C45D05110000008650C08600083e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1600602CC160\n\t0600680400E006000000000000000000FF626B0100000218018218038018019E0001981A1880000060250060468068860008\n\t06186106000004006A86006006806806006006064006006004006806005020806006000000000000000000FFEBF500000002\n\t1801801C0180180180040180180000000045264A62100064A610050640601624015400650600600600608600600480700700\n\t6005006006006002006006000000000000000000FF48D500000000180182180B801801800091801800080000600400600600\n\t6006000006056026000004006006016406006406006004004006006004006006004026006006000000000000000000FF853D0043e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600620230E02\n\t421600000800600600E00600600600000400700E007029806006007002000006000000000000000000FF2D5C000000001001\n\tC09821C01805801801C05B5080010064088C62302872A60220070050460000A080600600602600604E000006004006806000\n\t40E00600400200E046410000000000000000FF44F1000000001001801C01801A05811C81801800080000629038642E506206\n\t44028624408E0000A8006006006206006286000005004006006000046006004006006046410000000000000000FFBEDC0000\n\t000018018118418018018000018859508000006546046150846B4600050E00645600014D00680600E046006056006004006800c3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (40015883A8B8\n\t8B843841801801B0A8800000816404516016006C0642700EA0A24601000202642608C08F20724620A40C2064062062020A71\n\t16446005206406000000000000000000FF295B000000001A0180180180180180180180080000000060048060000060060048\n\t06002006000003806006004806006006002004004006006002006006005000006006000000000000000000FF5A8701000000\n\t1401801811C01C01808011881801800000600704040600604610300605504644000000600601700600600600200400680600\n\t6800026006006006000006000000000000000000FFDA5C000000001001801E01801801E0000180180160000060C6000100040023e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000016802\n\t0040706200000000000000000000FF110400202010000600A14002000000000004001000000000000960062C008848028020\n\t8600118001000060020008200000000000600440000200000000000020046030000000000000000000FF1ACA000084081801\n\tA8180B8018018000018029808000206098000040C0680602E80600200600000002600600400641608604661C02E006036000\n\t3A62864CE204000506000000000000000000FFCA24000080321A31821C01A01B03AAA2B5A40A488000B268A8800886526156\n\t88C526802816000C00A86886A4542690E89684688485682E8B6800A0EA4688EAA08008B6000000000000000000FFAA61002000a3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (812003002002\n\t00100894204300300301300340324320320300B211083003003003323512000000000000000000FF2CBD0004004112204012\n\t8020211036814010C2040000008000B0C800001001011024000000800810284000A08880048C508208C0800800800C408108\n\t00800804800080000000000000000000FF27AD000000442280C20800C008828028A28A084080000225020000828070260030\n\t0250300E00020010288640200600200220200200212A08201000A00220208000200A000000000000000000FFB30F00000002\n\t80580000001402600802084000290000880A2000611E820200204009000020000400840A0008062008022841C100140200600063e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4A10800400A0\n\t0800A04A00A00A208000002802842802002000002800803002800C000020030030028028028D280A8128C28A280085280280\n\t2912842802000000000000000000FF48AB0000002012830014014010242202000002080000000000804A0000400400000480\n\t0004800802004805001004000D48C00C80CA0A08A08802C008D0890824800000000000000000000000FFA38F000000009843\n\tA018019218418419018059158000806B1608C00680680640680628640608840000600620620644645602E116146146406040\n\t0160A6446024006006000000000000000000FF8B03000202140810800CA0800E90D00C20EC0C40800100300300315224200300e3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A80202A8200\n\t288000000000000000000000FFEC7A0003543141145543541541143345541542200000550D50D10930551550550D51550800\n\tD50A00550550D50D50800828CB0908C00A108C0800C00C10CD0D20D50800000000000000000000FF56450008000000000000\n\t0000020440000000040000000010010012010000008000000010010014008008010010010010010010010211211410010011\n\t010010C9041000000000000000000000FF761A0008AA0A80202AA0AA0AA0C80880AA0AA0820000AA82A82880A8AA8AA82A82\n\tA82A80002A80002A82A82A82A8000400000420000140000200080240220210288000000000000000000000FFFF1A000200200013e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020000020024\n\t00002002002002002002012002012102102000002142002012002002000000000000000000FF9FEB0000AA1104AA0AA4AA4A\n\tA6808AA0AAAAA0CA00002A82A82880882A82A82A82A82A80002A80012A82A82A82A80022AA2402A83102022026002AA4122A\n\t82002A8002000000000000000000FFFFDA00080002044000000040040000000040008C000080000004020080000100000000\n\t00000000008008000000000001000000200A8000410200130080000000000000000000000000000000FF8CB60000AA4220AA\n\t4AA0AA0AA0B00AA4AA4AA08C0000AA82A82A80A82A92A92A92A92A80002A80002A8AA82A82A80002A82882A82002082100000093e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C00C00C00840\n\tD50800C44800800104300300A003043043003003003013003001013003003042402002002402002012403000002103003002\n\t082002000000000000000000FFF8051040458018118018259438010038D1009801800010604604400600608600600E206006\n\t20600024600620620614E10608E006046486006000126406046006046006000000000000000000FF60040000002142010012\n\t0120100420020000122000000048008448208040040040008050048048008048050050048008008C08008C0848848800800A\n\t108008A4800800000000000000000000FF5CDB0000008C0800A00800800851800801800800800080200200220200080280080053e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001302460\n\t80000000000000000000FF87E508014400100800000210402000102000000100001200245060060001200000004000080000\n\t004000004002002C0100000204000100000000000100C04800106000000000000000000000FFB96300200880080080182082\n\t8C8008AC88008800800004204250C00200600200600200600600200002240200206690284208A1820632436124410A320241\n\t2200023002400000000000000000FFB231400C10400400400400410100420000422000000100500152000102100500100918\n\t100120100100D005005000008018000100000008001000000018420404000000000000000000000000FF8DAF400500C00C0000d3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600610010\n\t62060061170872360060820250070060410D700600A02A023106000000000000000000FF2EE40008018518118098A1801801\n\t88287F8638A90A0054E28610850E42600600610A00600600608020608600600600600601E60641618E586000206426426200\n\t480026080000000000000000FFFBF6000001801803841941801801801901801803152001632E410000026086026002016086\n\t0060404060860060460060060060060060560363104060C6046482104026300000000000000000FFDEBA00080005000C0400\n\t0200200000008000000200C02800100064864000880C00800101000000400800000000880004080000002080000400880B030033e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AB8AB8298A08\n\t05889907800011E0062884882AE2AE8462AE2262AE0060022AE2AE2262AE0062060042121840660060020064160903042880\n\t06000000000000000000FFA2E400000100180180180180190180281580182180000C64268400068060064168068160060068\n\t0000600600E00628608600610204400620680004E0AE22285604402E000000000000000000FF733900000180300180180180\n\t18038088A182589100002061160064200060060C60020860060060000060060860060360364AC04840849612E00050640601\n\t2080006506000000000000000000FF676C000001801801809805803C01883C018058B1000000600600600E0060160860120000b3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600C0468CE00\n\t0000000000000000FFC0C240000115595595595595580194988995592000005564575561505565574D655545655600600455\n\t6556556556496516496556556146136004286016556226552456000000000000000000FFE0ED000001C890ABCAB8AB8AB901\n\t8C0A898A9808800122740E2AE08F2AF2AE08F2AE2362AE0070012AF2AF2A72AF41600622C420028016806000036946000246\n\t28E206000000000000000000FF9B5A200001601801E0180180194380084380180A8001806086006001007806007006006006\n\t00600180780780780602604602600000041620600004E4A6001084002006000000000000000000FF5B440000018E90AB8AB80073e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000006006\n\t00600608708604C00600234629700020620E006046043236000000000000000000FFCAED000001801001801801801801842A\n\t418458210000006816006006006006916004096006006800006006006006C164160040060020068060000868860063160060\n\t86000000000000000000FF17FE000001AAB0ABAAB8AB8ABAB188C8838898830000AAE20628E4882AEAAE2262AC3262AE0070\n\t00AAEAAEAAEAAE0260262842AE2AE80E02700082E026AAE01428A106000000000000000000FFF13A00080100580180180180\n\t1C35C1384180584000000060A7006046006007406005106806006000006006016006146D361061062034864CE8014860075200f3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B8018AA8018A\n\tB88A00002AE2AE28E08E2AE2AE2AE2262AE2AE2AE0002AE2AE2AE2AE0066064341062421060062002061061060062CE40600\n\t0000000000000000FF4BDB000109021001801801801835800895801800000000600602600000600600608600600600624400\n\t600600600600600600404600A04E00E02400628604604C0020D6000000000000000000FF9F47000001805001801801801901\n\t800841801840000000600600622600600600600E00600600610000600600600652E13630C50E0C23064A60800D604E48E484\n\t026406000000000000000000FF5ED600000100100180180180180DA0080980181000000060A6846440806006006806807006000be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000006000000\n\t000000000000FF9EE40000AA0AA8AB8AB8AB8AB80B88980B8AB88080002AE2AE2AE2AE2AE2AE2AE2262AE2AE2AE1102AE2AE\n\t2AE2AE22E20E2AC20A02602602600002602628C2282AC02E000000000000000000FF04C90001020089559559559558159558\n\t15955953000055655655613055655655645655655655604455655655655645603600441241204E2CE28404E24E4564125100\n\tD6000000000000000000FFAEEA80000000080180180180180182380180185180000060060060060040060060060060060060\n\t0000600600600600604600408228E096516510016496026006004306000000000000000000FF0CA20000339C90AB8AB8AB8A008be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030060060060\n\t0652E53600612AC0430648608A0D604E04C110004406000000000000000000FF99A5000400001801A01C0180183590129580\n\t1A0100010060020064000060070060860060060042080068070068060060070040060C104F04E0000062861060020440D600\n\t0000000000000000FFC7670000AA0AA8AB8AB8AB8AB9418011418AB88580002AE2AE28E08E2AE2AE2AE3362AE2AE2AC4002A\n\tE2AE2AE2AE1061062AC24200C40600620070600620632628C006000000000000000000FFA89C0008200048018018018018A1\n\t8018A180180000000060060062000060060061060060060063000060060060060860860C40421022060060202860060040C4004be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801801801800\n\t800000640650628100C02600704E00780600400000E20600600600600600600014650600E10010601644640A004006000000\n\t000000000000FFBFF6880C02008001C01DA1A039099A5C09A09C018000A07206006007006827007027006046804040807207\n\t10761650600F00C0108BF2871860A0016406006286004006000000000000000000FF7F26100042009C018018458018058210\n\t09909C01000020680205600080700700680600630610400500700620700603621700E0060000064060240060060041040040\n\t06000000000000000000FFED44000800000801801801A01901853041C01855800000600602602600480600600F006006804100cbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000000000\n\t00000000FF3BC1000000000801883801801825805881881821820002E28605E18020608E02601E00640600E00000600E4060\n\t0604600600400002E28600E0081A648600C01002400E000000000000000000FFAAB2800000001001821803A0180181180382\n\tB80A88A008600208022602600600688650E0060040501064061462160060970060042060062C612000E21622608E00C02640\n\t8000000000000000FFC795800020001201801803841901801801901A0180000060025004008168068060060060C608404080\n\tE80608681649640600400C00600621600000E00E226002004006000000000000000000FFC076800000000001E01E01C45811002be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000052\n\t83302000200803004803000D0528080000006200000000000000000000FF95D40000000018018A38038018418019018D1821\n\t00C01370824001000040960461062860060160000861060A600E00600E0060060D200604E02004E10601430C0C4026008000\n\t000000000000FF25CB0000000018018018018058018898458038819200406202090426046006006006016086006100006426\n\t0064260060060060062061064062880060164C404001400E200000000000000000FFE8DD0000000018018018018038018818\n\t2180189580002060022060064060060060160060860060D00060B600602600610600600408641E106200106406084224084000abe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A02004040000\n\t0011100000000008008040000048000004008000040010040800800008082102000000080800000003040000000000000000\n\t00000000FF62750000000A80AA8AB8AA8AA9400891400AA9A880002AEAAA28C4AA0022AE2AA2AE2AA2AE2220402AE2AA2AE2\n\tAA1021020AA24232240200200070200231C3802AA482000000000000000000FFDDBB00000000000000000000003404009400\n\t0004000000000602620604000000000000000001000000000000000000000000010801004804804000000002003000405000\n\t0000000000000000FFC61280000000400000000000010000404000000000000000000060064880000000000000000802C000006be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF4C8280080020140140140120100024100040142A000100500000404090100480400480480480000100480500500400\n\t004030900000009051000001049100400C000100000000000000000000FF0D28808000125955D55B55D55815155815555949\n\t8001D57046554516557557556557557556556111557557D5655645643655612608604E2CE50044E24ED560245560D6000000\n\t000000000000FF22870000002CA8AA8AA8AAAAA80AA8A80A8AA80080002AA2AA2AA08B22A2AA2AA2AAAAA2AB2AA4802AB2AA\n\t2AA2AA22A20A04228A22A0220222A00220222222222AA02A000000000000000000FFF0AF0000000092004000000000A0000000ebe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800280820000\n\t000000100480880000080800000220000000000000000000000000FF35CF0000001400000000002001000000400000820000\n\t8014A00204000010008000010000000002890010008000005283300004800003004803002D04280000004004000000000000\n\t00000000FF133A08800000400020000000003400009420004000000000080000000000000000000008000000000000000000\n\t000000000000204300480480080000800004100000D0000000000000000000FFAAAD900000008EAA8AAEAA8AA8018AA8018A\n\tA80880002AA40228A0EA2AA2AA2ABAA82A82AA2AA0002AA2AA2ABAAA0020022AA40A0C21020020000021022AA0B20AA40200001be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000040\n\t0538400000002410020C08400000054040100040410000480004000000010050450090100080000000400400000000000000\n\t0000FF81AC000000C00800880800C00801800800800C10800000240300200200A000002800002000200020022A8200280240\n\t2002020482003002002000002002002002002002000000000000000000FF6851000000202008000100000000020008100200\n\t0000000028080000000088000001800000000282C00008A08810008000000000000800200282000000000000000000000000\n\t000000000000FF7CDD0002801002000402000000000002220000000000800001000000000000080200400000000000800000009be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF0630000000000000004001000000000001000000200000050100400000002400040C080000000000000000000001000000\n\t000000000000004800800000000000000000000000000000000000FFFD9D000000900800840800800800800A008008008000\n\t00228252200200200200218200200000000000260300300200280200001A1634030020000020030020020020020000000000\n\t00000000FF5D53000481803C01881C81C01801841A4B081809800100624E004006016096007A06006000200000046D160142\n\t17C36006000506806007004001006007006446006006000000000000000000FF20F900000100001100200100100000000100005be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040060064000\n\t2000010400610020600E406024006006000000000000000000FF7F7000000000000000000000000000000000000000000000\n\t0000600600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFC4F9000000000000000000000000000400000001000000000000600600000000000000000000000000080100080000\n\t0000000005000801000800800000800004000000000000000000000000FF4980000001800800800800800800800800000800\n\tA00000600602000200200200280220600000000000200200200200200200000200200200200000200200200200200200000000dbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000140610651\n\t6240406007004006006000000228804004805007106084240014116004016000046204004004006006000000000000000000\n\tFF9D69000181A08801841881801801801931807001800000600600E00600600602700600600000000000620600401602E826\n\t10000400408484600020E00E017006006006000000000000000000FFDE7D0002019098018818018039058C40019010150000\n\t00641601040600600602600600600000000100640702600453653602080100E00408E0290164060060860060060000000000\n\t00000000FF507B00000180190380390184180180004180100180000060060000000040060061060060000004500060060064003be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFA8\n\t72000001801803809001821821811801001800920000610E0160004540060060060060000000000840064000060860061201\n\t04016006026020446006104016006006000000000000000000FFA708000001801041801801801C0180040301180088000060\n\t16040000007006805806006000000000106004300487806004000080C0601604602090200400681600700600000000000000\n\t0000FFD9F8000401801801925001845903944501101804800100621600000600600600610600600000000000600602121630\n\t740E0C004000C0020AE0A800200640E0C6006006000000000000000000FF01EB0000019C0087841901811841811C0984500900bbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (609C00000000\n\t000600210100411C406006006046000000000000000000FF15D4000001D01901805001801A01800254001800000000600600\n\t6006004006006306116000000000414406006206086306001000026003B02000004006804006006806000000000000000000\n\tFF25160006018008018010018018018000000098400001806407A06020006106006006006000000006026A86006D06006006\n\t200000200812802006884006806006006006000000000000000000FFA3810000019410418499018318018018050458200200\n\t46626614600602F086604F86006000000000625284160807066004280014107006016000A020040840060060060000000000007be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006046006006\n\t80E006005406246000000008805C0414600610608401020650610A848000016004044016006006000000000000000000FF2D\n\tD4000001800041803001805801805D008898208001006006006000016006084A1608610000000800400400EC860464040082\n\t06800082208280006084404004006046000000000000000000FF0E450000018000418018018058118001002A184000008078\n\t8780600601600600400E00600000040800400400E80620600400820000610680A22800400401400600600600000000000000\n\t0000FFA306000001880081801981A0194195C4002118000000186086006600006E0614408600610000020020E2148061668400fbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF534A00\n\t0001901805801C0084182D809801809903A00000610D206006006006406826006006000008C06A0404690690600640821040\n\t6006016000006006404004006006000000000000000000FF6C7E00000180100380181B80180BC01800901802000004668600\n\t600684400600402F406000000000A04004106006006104000006006016000000006004004015006006000000000000000000\n\tFF3046000001801201801201C21951941C548C9800000002600EA06080027006244006016000000004004015806287506804\n\t20000F840006100054006804214006006006000000000000000000FFFEB200000188100180180180184181180080190080200007e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006002\n\t000000006006004006006006000000000000000000FF62850000018018018018008018018018010018018000006006006000\n\t006006006006006006000000006004006006006006000000004004006000006006002006006006000000000000000000FFE2\n\t86000001801801801800801801801C0180180180000060060060060060060060070060060000000068048068070070060000\n\t00806006006000007006002007006006000000000000000000FF425B000001801C01801804801801A01801001801A0200060\n\t4600610000E006006A16046006000004806004006406006006000000104104046004816006026006006006000000000000000087e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (068CE1500465\n\t56806287006106020494806800006007006D06000000804002000284806006002006006006000000000000000000FF956000\n\t218100180380188000180195C140981001800000600504E006086006006606006016020000A2608080604601600600000000\n\t6102100000006006000806007006000000000000000000FFD1D4000001001805821800001801800000001501800000608E50\n\tE54080632700690E0B612602054054710C0360060A754E0080B1054800000001006006006004006006000000000000000000\n\tFF14B0004001001801901884001881800000829001840002620600600E0860060060264060060100080164244064060060060047e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF8E60000001\n\t801801C010010018018000008010018000007006008050006486007026006086020480806026006004006006020000006002\n\t001280006006006004006006000000000000000000FF66E9000001801801801001001801801A0101180184000264050C6100\n\t8460360060060A6006000011006083006007806506000000006002004000006006004007006806000000000000000000FFC9\n\t59000001801C018010010018818018A1829A01820004708E2A62AE0062860070EF3CE0AE0082A800E36E22E2260AE2AE0480\n\tA882E002004000006006004806006006000000000000000000FFC0A2000001001C01801E000018018004000112018400007400c7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80CB6216810D\n\t0088E956B0C806816816000000000000000000FF303A0000058C18098018C5841801A21A42091009800000E00ED060060160\n\t8E00601020600600000028600380601682E2060000080070C6324000206006045496306306000000000000000000FFF16700\n\t0001801801801801A01801A01A00A01001800000600600600000780600600000600600000000600600600600600600000000\n\t6806004000006006804006006006000000000000000000FFE71E000001801801D41005401801944000201B018000046C0600\n\t0006006046006A860460060000001060020060040060060000008071001008000060068068070060060000000000000000000027e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (601E22802000\n\t8029000000000000008228720408800070000000020440004280000400260000000000000000000000000000FFB3C9000002\n\t2006080001440000000024F00804200001008008296047180001000201010200200000000480000000920108008000008808\n\t2C8400408020580108000000000000000000000000FF85ED0000019018438018018198A98201019013018000806284000100\n\t816286886002B8600600000001600200600604E0060000002142A600000024618E000014006006000000000000000000FF58\n\t74000211805805C09C09C0DAA9A8430920112580000C6A8682088E2C6A2628EC22096C06210800816B52D26906106836010200a7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (7F0004008208\n\t30D00E90C10C40C14880C00880800000300300313201200200B00201200200100150B40332B0028230020005010C30034834\n\t01233003003493003002000000000000000000FF58F90002082A60102010BA20204031400A20028800000840009248808050\n\t0CB1480000C004008800FC0804890800000A00000E80800804D20800880800800C80A88880000000000000000000FF5B2600\n\t0000A4080080800100080080080100880180000020020000020030020020020030020000020020120421828820020001081C\n\t200200200201200200A24200220A000000000000000000FF01E60000000104001004001205000C04000000060001021000000067e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (022022000022\n\t00004000002A82A8000000000000000000FFD8C3000200A028008A0A00800A00A00840A00A208000002002842802D02800D4\n\t2002000002000800B02D42913002002902800000902912902840802932A22C0A802802000000000000000000FFAF6F000200\n\t2B120120500140120021420524030B0000004000804A2080480480400080400400084085080C8408C8004C40000910A28805\n\t008800888A00888920804804000000000000000000FFF67100000188B801801843081901921849101805800080680608C006\n\t10600610680610600600000004600C00630610612E000000016224046000006306526026006006000000000000000000FF9F00e7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A92A82A82A8\n\t2A80000000002A82A82282A82A82A80003280882082A80082082A82A82A82A82A8000000000000000000FF448B0003543501\n\t540281545543543085343102100000550550D50930D01550840D515500000008008808A0C90C40550A88800450908CC0CC88\n\t40D488A88B0C80D50D50000000000000000000FFAD0400040004220000000000040044240040040000000000010010000000\n\t01001000800001001011001001000001801000001001041001001001081001001001001000000000000000000000FF58E400\n\t00AA0000AA1080AA2AA0AA0A428808E0400000AA8AA82880880382A8008AA82A80000000004400002002002A8048000220000017e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000084280080\n\t0000800800800A00800840800080080200200280200000280080000000000000200200200200200200211002230200201020\n\t2002002002002002000000000000000000FF2F870000AA1802AA0AA2AA2AA0AA8B00A80AA08800012A92A82886892A82A82A\n\t82A92A80000000002AA2A83222A82A82AA0002006001402A00000622AA2A82A82A82A8000000000000000000FF2260000000\n\t0022000024000000000400000400840001001000000200020000488000000000000020010208020088800000000080420010\n\t000000000200000048000000000000000000000000FFC2310000AA2102AA0AA2AA2AA0AA0800AA0AA0AC00002A82A82A80A80097e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000320\n\t000004000000000000000000000000FF0D0D000410C00D00C00504C00842800C00800C008001003083002403003113093203\n\t0030110008082132C3403003042003002100023003002800302202003003003002000000000000000000FFD49B0000018018\n\t0180004181180182581100180180000060465440061160060060061062400000000060041061060060060060004060061060\n\t00006026006004006006000000000000000000FF7DF500020120800100000100120021400520020200000040048448200008\n\t04800004004000800808800804890004804800004820890850810800910800800804804804000000000000000000FF21F7000057e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (084001081000\n\t080004100000800901100C0280000080000440310220300200100000030000000000000000000000FF849900000800000000\n\t010000800C004000000001000000008000608611008010C20000000000000001000420008085000000000004080088000048\n\t0080004800800800000000000000000000FF1C3A000001800890844003800D6082091C000840800040602648000200200600\n\t20060860200000008022B6882042082802112480212002002001003052052402402012000000000000000000FFE613000580\n\t400400400420400010180401000400000100100122430100100900100100120900000820100100100411000100000000001800d7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801001810001\n\t801C01801914081021808000600640640630600E04620600600000080100608900E02604708608E28000600404480141702E\n\t102202306016000000000000000000FFEBBA0000018018018080418A181190600108300982C010E006048006086606426316\n\t0260900010000062622063161060060060000061C612700810E006606006086006000000000000000000FF8AB90000018218\n\t11844001941921810041825011840021628601000004400600600614610000140800620050640600620600600001420620F4\n\t50006406056004056006000000000000000000FF233B000000040000000020000008088040040000004008028004620622000037e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000461260C00\n\t02006006000000000000000000FF2A0900028F8AB8ABA8E2C98AB8718802009818AB8000AAE826A884A8AAEAAEAAEAC6AAEA\n\tA80000007062A2316B162AE00E006000606004230060306756060C022AE2AE000000000000000000FF6EB900004180180182\n\t0021801909810090005801800000630602020600600600602600600000080000681208600600648600600009650400C80000\n\t6026112406006006000000000000000000FF45C7000001801001800005801805825824831001800000600E00600000600600\n\t60160060000000200AE0020360CE00602600600004604810000012E10E2020D0006006000000000000000000FFE04C00000100b7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (610E00600080\n\t0841006800C0600600608E006000136452006800807006117042006006000000000000000000FF8178000555955155B54355\n\t95580191014415595580005565565561305565565564CE55655000000449650012E55655608600600055554744601421640E\n\t207556556556000000000000000000FF772D0000898AB8AB88828B8ABA838A9CB38038AB80012AF0C6A8E08F2AF2AE2AF207\n\t2AE2A800000002E2AA0262262AEC260060000060802A000043600620010E2AE2AE000000000000000000FF366B0000018018\n\t01800001801941821C11001801800100700700600100500700700700700000000802700A40700600625600600000681080C00077e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018000058018\n\t09815804001A0180000060060460000060060060060060010008140073293060060062060060000040020C281520E4162960\n\t06006006000000000000000000FF8672000201801001800201801A0182023180180180008068068062468068060069168060\n\t0000000049600200600600688600600000609200A000086086006806006006000000000000000000FFC3570000AB8AB0AB8A\n\tA0A98AB8B78840810AB8AB80002AE2AE28E4882AE2AE2AE2262AE2A800100482604002E2AE2AE02E0060002AC22630300412\n\t68260362AA2AE2AE000000000000000000FF6B6D000441801001840001801801802000829C0180000064160460460040060000f7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E11611625400\n\t6006000000000000000000FF90B20000AB8818AB8000AB8AB82188D8218898AB80002AE2AE28E08E0042AE2AE2AE2AE00000\n\t00000860221062AE2AE0062AE0002062022420000160060C60262AE2AE000000000000000000FF683E000001841801800001\n\t801811801811001801800000600602640002600600600600600000000421620201600600600600600008C10A10A004046446\n\t036012006006000000000000000000FF774C0000018138018000018018838459028258018000006006006026296006006006\n\t0060000000000260884A60060064CE00600002602204200049610E206302006006000000000000000000FFD2FC0000018018000fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000006004\n\t4A634A006000006086000006200100106004486006206026006006000000000000000000FF7B8D0000AB8AB8AB8000AA0AB9\n\t4B8A18C50AB8AB80002AE2AE2AE4AE2AE2AE2AE2AE2AE00000600040E2AA20E2A82AE22E2A80062AA0260060004262262260\n\t822AE2AE000000000000000000FFC61700015595395580015495581594990193595580005565565565305365565565565560\n\t000060040160024365505564565500060CC4344160040464CE08E50A556556000000000000000000FF78AE00000180180180\n\t000000180180B80180180100000060060060060060060060060060000060000060020C600000600600000600648642600000008fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000188380\n\t4003801001800000600602642600600600680680600000400002E0004A60000064CE00000000630648600049610E04601200\n\t6006000000000000000000FF7257000001801801800400001C11840011801001800100700600600000680600200600600000\n\t6004206004016000806006001004000040026004046446097320806806000000000000000000FF4FCA0000AB8AB8AB8000AA\n\t0AB8218880B18AB0AB80002AE2AE28E08E2AE2AE2AE2AE2AE0000060001C62A80062A82AE1062A80042AA01E11E000106006\n\t2060062AE2AE000000000000000000FF5FEC00000180180180000080194180184D0018018000006006006000006006006006004fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006006\n\t000000000000000000FFB13C000001801881800101801801815841800801800040604600600000608781600704610000C000\n\t006002006001906006000100322103000000016026000002007806000000000000000000FFA3EF000405801A01800209461A\n\t1180B823840C018000B868060064664070064068068260005C64000465C2006000C1600600148009200600014000E00E0010\n\t07006806000000000000000000FF455C000101C01C01800010605801840003801601800100608655600100700600200600F2\n\t28004004086004006400006006000000004200306004086016006007006006000000000000000000FF1080000401801A018000cfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000040000060\n\t0C10E00002C00600000420C402082200006006002002006416000000000000000000FF969000000580180188000108180980\n\t1821029801880000618677620000E0060060062164500060000062C00060807140060000044F64061200C000624602A00A00\n\t6006000000000000000000FF383C000001C01801828001A51801820015100A018100C0E20E000006D0702604234690700000\n\t400000604608625008604654020000431220A00009608E50220730620E000000000000000000FF4AF3000101801B01800101\n\t803811840001040801800000602600040040610620A0060061002564000C6206006400006006000200006106A02100106006002fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00008202400C\n\t00208000000000000060060000000000000000005200000280804A00000404A8000088410110508000490108010080000000\n\t000000000000000000FF8A32000001801801800001801809800125029C018800206096420000316007022006406000004000\n\t0060060063404060062A0200000010206100006016546014086006000000000000000000FF39700000018019018280219319\n\t01850009085805854008622600041604643600224608600000400000635601601015604600000035210614E2000965060164\n\t06406006000000000000000000FF908A000001801881900021001881809880003803822009602600600E02620E002106006000afe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D2AAA2AA0000\n\t00000000000000FF0A750000010000000004010001400000A00400000000004804020000000000A400010040000000004A02\n\t00000000000080000020080280000000480001000080001000000000000000000000FFF5490000AA8AA8AA8000408AA82089\n\t08C10C880680002AA2AA28C0AA2AE2AEAAA2AE2AA00041C0001C221A00200028210200033208220200200010200210240E2A\n\tA2AA000000000000000000FF90AC000000000000000002000010008040020451800000000002640600000000600000000000\n\t00002000400100000100000000040400200240000404404C4440000000000000000000000000FFBF050000000000000000C8006fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A00008224A10\n\t20002AA0020002022820133420000120022020C32AA2AA000000000000000000FF66B7000401001201000403201000022011\n\t00024000008050040040400048050010050040000840000010400C08010000008000000200200C0000008111000004805004\n\t000000000000000000FF7854000355D55D558001555558159518159159558001556556514516557557107D57556000556000\n\t01608E436000D564560015164560464160000464CF55620C557556000000000000000000FFF2A50000AA8AAAAA800088AAA9\n\t4A88088288AC888000AAA2AA2AA28A2AAAAA2AA2AA2AA00002200040B28220A80032A22A80022230A48A20A00042222222A000efe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020020000020\n\t200000000008000000020000000200C800000000004002000A1A01280000201C408004010080000000400008200000000000\n\t00000000000000FF93C300000040000000000000008203400200400000000000000004200000008810008000000000000280\n\t404A00000004A8001040000010148000490109050050800800000000000000000000FF824B00000000020000000240001000\n\t00B0000400000080000004000000080044800000000000000220010001000000000000011003032100000204044010020000\n\t0000000000000000000000FF56110006AA8AA8AA8000A88AA8208848008A8CAA80002ABAA828A0CBAAA2AA0122A82AA0002A001fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (680600000000\n\t0000000000FFD1BB000000000405001101000205004000005000000000023022C00080400404440810400000000000440010\n\t140050080040000410400D014000804004800010004004000000000000000000FF47F1000020000200800800800800C00800\n\t840A0080400028020020020020000000020020000000000020020020020020820020002800A0802000002002000000002002\n\t000000000000000000FF296600000000004200400000000000000800020200000088000000000000000A000000000008002A\n\t000000000000000000000800800000000022000000800808000000000000000000000000FF74370000000000000000800000009fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (202002002802\n\t802002002A06002A02000000802002000000002002000000000000000000FFE67400000000000000000100000C0004102000\n\t000000100C400440000040000040100040000000000040000000000000000000010040040040000040000000000010000000\n\t00000000000000FF07C8000000000000800800800A0AA00C0880080080000820024120020020020020028020000080000020\n\t0200200200280200204300301201800101A043001000002002000000000000000000FF7BF100004000002180380180180180\n\t1811821823802000E0068040070260060860060040001000280060060260060060860060042040A400602100400600002000005fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (408480180180\n\t000060002000001060060860060040100100000060060060020060060061420020C402000000410600000000601600000000\n\t0000000000FF7F70000000000000000000000000000000000000000000000000600600000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF4903000000000000000000000000000000\n\t2000000000000800006006000000000004000000000000000004000000000004004004004001000000000000800800000000\n\t000000000000000000FF703C000000000000800800000800800800801800800000200300000200200600200220000000800000dfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF21F8000100000001A518015C1011889A200019090000044826446410A86226106854286008400000006410126002\n\t40E482402902012103004010094046800040006086500000000000000000FF27BF2000000000018018010438018018028018\n\t81800040600600600606600600601610600020800002600284E00609210200308412481202600080460601880000E0060000\n\t00000000000000FFBEBB000000000001A05801081901B0024184190980000C754700044F406246446C064544004803520462\n\t8609640708000600600502400400000210400F00000000E106000000000000000000FFE7DA00000800200180182180580181003fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060020060\n\t10400101080008020011006006001000006007000000000000000000FF9328000000000001811A41101009801C04C0180A08\n\t0000600208E42001600610603540200020000000601010600240620000002001114084048021704E0012A000600620000000\n\t0000000000FF3D4F00000000002180180100380180804190180380200141061080410C600700600650020000000000600240\n\t6002806008000040A0004208028020600E000D00006007000000000000000000FF5D66400010002001805A41421B01802081\n\t821801800034630620042E00600634640E0484001004D000630308640600400200202010012B80200000608E00000000601600bfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (841801800000\n\t401610600000621601602700000000000428600611E002206C064060820020002140040150066800D0C06006000000000000\n\t000000FF10CA0000100100C18018C3021001C0000580180100000460030060068064068064C4000000000000106406006802\n\t406806006002003102204001006806800000006006000000000000000000FF67C00000800000018018010018018100218118\n\t018020006006C46000047806007906100000000004006006202800006806006004D050121060048040068000000060060800\n\t00000000000000FFE0AA000000000041841821045401801B82B09908080005416700601610E0060060850024000000000064007fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t04FFD8AA000000000001805801041011A01809801A02000004400700622E8060162060050060000800000060068022000072\n\t060072C0480C04124120902006001400026006000000000000000000FFA8DC00000800000180180140100180994180180800\n\t0002400680620000700600F405006000000004006A461020000062060060010003051140040020A600080028600600000000\n\t0000000000FFBE05000080080005801801201021810000801809000000400600620600680610600400000000000840602680\n\t6002006006007084004C00144000004146100100107806000000000000000000FF26210000000844218018A1001A1986414200ffe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (220600680600\n\t648490040801240400C804006206006006000000000000000004FF4E1D0100002A0001C21A01001C01843901801801800042\n\t000411644610608604E0C400200010000200410600201691640E007040C40002922102884004007107047006000000000000\n\t000004FFCFAD000000020001C21800001001821880C01E00000000404300E01688608650E0B4006000000000006C86440000\n\t08700E00600001018A00404000A006001080007006000000000000000004FF4728008100094105801804041641E078008418\n\t0000002040361860000060169A710C006000000014206206A2080800E00640680102880304E205012006000051806006000000001040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018000000004\n\t2060060060060064044040004000005140060460060060060060020000060200000040060060060060060000000000000000\n\t04FF48BB00000000000180180100180180180180180180000000040060000060060060040060000000040040060020060060\n\t06006000002000000004004006006000006006000000000000000004FF3BA4000000000001801801001801C01801C0180180\n\t0000000500600600600600600500600000000000400680280700600600600000480300000100400600600400600600000000\n\t0000000004FFD518000000400201803A01041811801811801A03800000000400600000600F0060040060000000044040060000801040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tEFBA000000000001801801901801840421801809940020414780E100026516006026004000000516006006002006006C5600\n\t780480400480644E000206006004006006000000000000000004FFA26F000000000021823801001A019DA051AAB809800080\n\t000600600E0660060060041040000000000040063060060064061C6000002006006000040006006800006006000000000000\n\t000004FF5892000000000001809803A01801802083889A09800002495415644828708608614E8484A0110106006016A0E546\n\t40F10640600B000C05000007000006006206006006000000000000000004FFA92E0000000000A18A3801001801800001823800401040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006406042005\n\t004004A42000044206002406006006000000000000000000FF2009600000000001801801801E01A00401801801E000A04004\n\t0081000060060060060000000000000060060048060060060000000028070024080050060028060062060000000000000000\n\t00FFB0AB000000000001801803301801821A2180180992008080AE02600000752E08622C8060000004890040068050060064\n\t4E001001000006000021004086026002006116000000000000000000FFE991000000000001801805001C0180182980180180\n\t008100BC0EE2260870461864BC22E2A020808020480E00C2A620E086200008001A064000010041060468060065160000000000c01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00A24C468308\n\t4E0262360B68A68240000288408868AE8268C6896A1684E4CAA04812050801000A0689680CA06846040000000000000000FF\n\tBD5500000000001180190188D841801921D01CC1800010D09650608640E10600620E416000000200A3620648420E4268C650\n\t2804150320486080AC894E245204106106000000000000000000FF4B2B000000000001801801001801A01801801801000000\n\t0005806000006006006004006000000000004006804006006806002000000002006000000006004000006006000000000000\n\t000000FF1970000000000101911805801801840305801801800004400640000642710600640610400010000011680694400600201040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF354D\n\t0000000084000000221004600400201800210000080000006016A088C88680000000000002000884900400C02001202AC200\n\t944000080010684588020040480080000000000000000000FF02F30000001800000000800002000002102000000000000048\n\t09E00E8008008800081000000000006002001A02001C02800108004880802000000000004000000000000000000000000000\n\t00FF81D10400000000099218118398898121C980591180002562260000204062060060060000000080000060260060060060\n\t06006012002018808000030026316004006006020000000000000000FFB170000000108401CA1A2BC2190BB2A00D80DA018000a01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (165264440542\n\t06AB40004A404600E106206006000000000000000000FFEF5C0400000C44A0D20C08C30844C50830A14CC080014034030030\n\t9280280282300340200000150120312B0A314B04310300A910303852003009013503303243003002000000000000000000FF\n\tF54000000004414024020C2C20043A82024032440000D2CD80B24880020000004B80A20000020900820940800918818C18D0\n\t14E8215061134880908A40000704A00820000000000000000000FFD37D000000000000880900800C12800A00C18880800000\n\t001200010284682680202240C00000042000200A20202202200204310482260344200004600208A00800200200000000000000601040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00202880A82A\n\t82A82A80A02000000000022A80002100007801C01800200A02100000000002A80000002A82A8000000000000000000FFAED8\n\t000000400000A00B0493280080CAA4A002028000A02A12802802802000002402852000000D0080283280AC42802852852A08\n\t808892830A02D02802002802802802800000000000000000FFD2D600000000020140123020100122020900129000008CC900\n\t824C00004004004810904000000800000B00940910848A00A00104C0404048490102C8000000048048040000000000000000\n\t00FF4907000000000001801885881A11901901881815800014E14E08C006426026006106086000000000806406006006116400e01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFE4150000\n\t000000AA0AA0AA2AA0AA0AA0080AA08400002A84002A82882A8AA8AA82A82200000002802A82082400280282082080400082\n\t882204002A02A80000002A82A8000000000000000000FF7BD10000002001541542C41101541040143543000000940B10D50D\n\t30D50550550490C10000000D00D50850CC0AB0850810C30808010C40CB0800C10D51000800D50D50800000000000000000FF\n\tF71D000800400000000000200600400042000410000100100100104100080080080100000000100000100110150128114114\n\t0011000001011001011001801001001000000000000000000000FFC4AC0008000002AA0AA0000000AA2900000AA02000000000101040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0100C0414080\n\t4900800800804804800804004000000000000000FFCBB9000000000800800810800A00804812800810800000202200244200\n\t200200200001200000050000201220200200211201220A00800A0D220010A002002002002002002000000000000000FF7172\n\t0000000000AA4AA0802AA0AA0805806AA0C000002A81582880882A8AA8AA9AA83300018000022A83420B8282282202201D20\n\t5E1A403001022202A80000002A82A8000000000000000000FF661500080000040040000824440044054000002A0000410020\n\t0000000008008010200C00000000000002800000000002000002C0AA01000004820A0000000000000000000000000000000000901040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (440001061005\n\t00100500000100100102801000004000800000000001C000061000108700005241010001000000000000000000FFB82A4000\n\t00400C00C00D00C00C50C00C90C14C00800100300300204301300B00300300200100100101200201200214204A0031030030\n\t4300300100B003001003003003002000000000000000FF09EC00000000180180180181580580180190180180200060041140\n\t0600600601600600612020008802600604601620E10600601654420E00C480006006006414006006006000000000000000FF\n\t1DB90000004010012010440010012312210002420000800A848448008000040040048800000008020009208008488488208C00501040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (95D200084000\n\t000000200200000401004808C01004200080005062161201280000082160000000000000004000082000000000000000C024\n\t00901202B0208200016000000000000000000000FF86F700000000000000000002802800000010C000002000000044600601\n\t0008010000006140200000000000054008540110004810AC0C5080820080090080004000E800000000000000000000FF869B\n\t00001000101000088084280010000C800802800002204208C02200200200600210200001018800280A002822912C22042082\n\t40200210608009200204010C002002002000000000000000FF6314400800400400400400440402400480400404000104100500d01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04012A046100\n\t004080106024006006006000000000000000FF37600000000018010018018018010010018098020800006082206006406406\n\t00600E08600000800000700600300F407006022006202000026000024554446014016016006000000000000000FF7CCF0008\n\t0000180102198185F8080060059058030C400062820000862062060260A640600000000A00600600678610640E00600019E6\n\t5A01E07200400400200C00602E006000000000000000FFBAA2000028001809043803801814088029801009000000E4460805\n\t081400CE04614600E000000090006006206006016016006000000100306100114004008284006046006000000000000000FF00301040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000060060060\n\t0611600000008080400601000E40620608000402080682410000600510A94A006006006000000000000000FFC51A20000020\n\t10AB8AB9F18AB8AA8E08ABAAB90580000D6432A88088AAEAAEAAE846A0600080010000600620244616621604031804861620\n\tE000AAE20621A3822AE2AE006000000000000000FFF9510000000010018018118018008048018018D58000436C0204000600\n\t600600642E0560000008000562060820AE08E00E023041506004086C00006056822012006006006000000000000000FF16F2\n\t000000001801001803001801009001801801000000010A0064200040060061060860000004805040AE0484064060C628A10600b01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800001801\n\t8018010018008108018018418000A820020062460060060065060060000008001148060860068065060068061110C700A801\n\t006004045040006006006000000000000004FF5D1840000020195595595595595494C955955B558000106552D56110D56D56\n\tD56D56A4600080040555644E1264C604604E4564D648F555512405336554425200556556006000000000000004FFB8AB0000\n\t002010AB8AB8050AB8AB8838ABAAB8118000000142AAE08EAAEAAEAAE816AAE0000002002244B62289162170464882442020\n\t063243002AE32C30220A2AE2AE006000000000000000FF3BC5000000001001801E01001801801801C01A018000A21002006400701040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0A0860000120\n\t4630C08C006006006000000000000000FFCBF100000000180180180100180184180180180180001120020460200040060060\n\t06154000000C8400400604640705684602F45204000011290442E006104094004006006000000000000000FF55CB00000020\n\t1801801801001800814801A018018000242002806006806806806806C060000000000044D650E0C608608608610650211604\n\t6400906002026442006006006000000000000004FF409B0000000018AB8AB8AB8AB8AA8808AB8AB8AB80018162AA28E2C82A\n\tE2AE2AE2AE0060000010062AE90640680E31630E207007008A24A070060062AE20E8022AE2AE006000000000000004FF30B000f01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E00600600600\n\t6000006000000106006006006006104014512114006000402000106016006006000000000000000000FF6A2A0000000A98A9\n\t8AB8210AB8C98A98AB805889800001210028E0AE03C2AE2AE2AE2AE00000000001400600600600600644631608802220E000\n\t2262140062062AE2AE2AE000000000000000FF212F0000000058018018030018058058018138218000122082026400106006\n\t00600600400000000444C01654601600E00601604E002480042004106110046026004006006000000000000000FFED3E0000\n\t000018058019090018418018018C1803800020A22A0060062060060060060060000000001044C6016346346356326106226000081040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000418200018\n\t22001801801801801840000000000400600002600600600600600000600040002610212612E12600C00208008C12A0000920\n\t04086086006006000000000000000000FF06F70000000AB8AA0AB8AA0AB8A38838AB8AB82200003302A42AE0AE1062AE2AE2\n\tAE2AE0000060002A820E34A30E30630E24440000222005600008220C22E2262AE2AE2A8000000000000000FF9A5400000011\n\t5912155910155915935955951915000032042C5565303065565565565560000060040C049643241640641608442444A22040\n\t60044424C0456456556556550000000000000000FF90A680000000180000180000181181180180191100000000040060060000881040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400520200400\n\t6007006806000000000000000000FFB2550008000010000018000018458120018018C000004C00D402602680600600600600\n\t60000060000004C601634634635602521424E00400400008A914116006006006000000000000000000FF8642000000001000\n\t401800001A01800001C01804000000820600620032F00680700600600000600080001614601600F006116123084114404000\n\t002424026116806006000000000000000000FFC8DA0000000AB0AA0AB8AA0AB8898E00AB8AB809000000001428E48E4462AE\n\t2AE2AE2AE0000060002A80462060460560462141400462205AC0002721442063262AE2AE2A8000000000000000FF2F98000800481040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00600E402010\n\t0060104000060060264A6096806404046004092000D00002206006002006000000000000000000FFB3678000000038004039\n\t04021831801821C01C05000001050454630000F80780600E00600800600800000600400624600600440300401400E0001040\n\t02442002007006000000000000000000FFFBC9800800021C20401882029D2D803801D018011000060004006086806A068070\n\t06006000106001109006274006117007004910A06000006400004802022007007006000000000000000000FF626200010002\n\t1620021840411C01802401801800000040000601600100620600600640600000600441080640604600610F80600442C0000800c81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180000180008\n\t9801809821811800008008000602624606400E00E2160262000060000000064C608601600602600400022200E1000824140B\n\t6014006016100000000000000000FFB8780000000018200018000218018A1801903805080000020009600000420600600620\n\t60003062001880062360060162260041140120160A640802200400600C00E006000000000000000000FF2A85800000001802\n\t001800003C41804083B29801020020000E2100A720608602601601201004600000045600620610E006006004CD4100002080\n\t20028A00E0071428AE080000000000000000FFF2E7800080003A00425820201905800221801C01080020828654040001600600281040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008008030008\n\t006000000000000000000000FF9E0380000002200000000000000000A00000000000000C0108006026008000000000006000\n\t0001000004C00003403403500484205001000004800A0100100100006000000000000000000000FF92000000000018000018\n\t0002184192C045925800080000240610000040428602600640201002620011002E0060060862260060023301061020001041\n\t040040001320C6000000000000000000FF6D0B000000001824001800093801800081801801048050000E44828600400E0162\n\t0604A2004060000004061064860060060460000024220520102440040C4004002006000000000000000000FFBD5E0000000000a81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AA2AA0002AA1\n\t2000020220A30A30230A22A2A022A2A032208022A2AA30A2AA2AA2AA000000000000000000FF627C00800000100020000000\n\t00000002000010010000000030020200000804800000020000004308000020A301201281200000B40800080402000900B010\n\t02A0000800000000000000000000FFE7D90000000880000AA8000AA8AA8A08AA8AA8AA800000602228C28A3A22AA2AE2AE2A\n\tA0002AA40000004A2420420520420820100022342BA4202022222022222AA2AA000000000000000000FF2089000000000000\n\t000000000000000000000001000021440002600600000000000000600000024200000014801000800040011005001000000200681040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0AA8000AAEAA\n\t888CAACAA48080002AA00228A08A2AA2A82AB2AA28A001AAA0000000020020020020022AA2022A220200200020222A202002\n\t28A2AA000000000000000000FF4B268008000010004010002010010204010010010000214040004040001004804804000000\n\t004000000110880000000001100004100004000020080000040000000805000000000000000000FFC1BA9000001558005558\n\t0055595594D9559558D30001554286514156557557556556516000556000000496086416406416D5640645632650E1084464\n\t06436016557556800000000000000000FFE1730000000AA8000AA8002AA8AA8928AA8AA8AA80000C248A2AA48A2322AA2AAA00e81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tA0208000000000000000FF856700000000000002000000800600000000000000008000010000000000000A00000000000000\n\t00008000000800680000000800000000808000140000000000000000000000000000000000FF29A700000000000040000020\n\t000004220020021000010005400202200010008008000000000001100004C00483403403500000900100104A048804808010\n\t0000000800000000000000000000FF58B7100000000000000000000000000000000042000000000800000000000000000004\n\t00000002000000105000100080000000400000C00080000800000304B0040000000000000000000000FFB6768080000AA80000181040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6C1441608001\n\t02B600605651405600688E00410700C0A020C006800006007825A00000000000000000FF0B3C000000101101040001001225\n\t0080100010010000004A00084800000684424000000804044440000000001100040800801001004000004400005004000014\n\t000904010000000000000000FF7E6D000100000800A00C00400800800800D040009000002002002002002052000002002002\n\t0021000002A280200282600200208A800802000040413002000012002002800000000000000000FFAE6E0000000A40800002\n\t440000000020080000020300000410400040008280200080000208228220000010000150810028000000000900000280000000981040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018008018008\n\t0080180080000020020000020020020060020028000020000000020020020020020020020020020060000020040000020020\n\t04000000000000000000FF329C00000000000000000000100060000040000100000044000040000005040410000000040000\n\t02000000000000804000000000804000880002824001000000000001000000000000000000FF5A7F000000000800A0080080\n\t0DC4810800C00800800000200210200200200200200300280300200000000280200240280280200200300208200010200200\n\t0002002002000000000000000000FFD9F9000080025801801823C09C01805801C838058C8100741640504600E0AE1269060000581040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010680001400\n\t0000000000000000FFE3DB000000005801800801801811808000041805800008600400000000200600610608000400600000\n\t000604640620220630620450014400E000202004000016000104000000000000000000FFF77F000000000000000000000000\n\t0000000000000000000000006006000000000000006000000000000000000000000000000000000000000000000000000000\n\t006000000000000000000000FF714E0000000000000000000002000000000000000000000005006006004000000000806000\n\t800000000000004000800000001001000801000000800000000000006800000000000000000000FF31C7000000000800800800d81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006010000046\n\t04240E12E02E00600635702A0004804340460001060000C2000000000000000000FF8357000002001801800009A01841A518\n\t01001805800000604E106000016046846804006016006000840A541000A48028040850B61020000400280020040801060068\n\t0C000000000000000000FF1327000000003801800001809A01881803023A1381000070A64062060060060960A60860066060\n\t000180860020063022062062068128900E800000208400000E007044000000000000000000FF1A0A000002001C11800815C0\n\t9801A8000410384180000261560002060060071070260008040060090014A700614F02B0560061440440051022A882A1241000381040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3801A0380180\n\t180580000060060060060170074070040060022060000001041000040040044041E501118E0820000241462A000600600200\n\t0000000000000000FFB877000000001901801801841A21C53801801801800000610620600002600614600400600220600002\n\t002C0000040040040040040004470460000054065400A6006002000000000000000000FFA3C10000000018819418018A1C03\n\t800000801801800000688E4000000430064970060008000060000001068420060060864168062522228100008044A6000046\n\t800002000000000000000000FFE57A000000001C09801803801809810000901C4980800C600640000600600601600600080000b81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (007842000000\n\t000000000000FF557D000000001941821801901A01900028801A858000E0E156006740202006086116006000006000400806\n\t8C610611601614600C011F870060A00CE906400306007202000000000000000000FFE992000000001801801885A51C018020\n\t4004194180000060060060064260460062040068800060040280041062040020040040570020228100040068060004460065\n\t00000000000000000000FF3A09000000001801AA1801A0580580000000180180000060360860000060268160060060100060\n\t04000006026006002106016016D46812110004046006000006006000000000000000000000FFF94C180000001801C018019000781040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000440C60\n\t04006044005C2E13220810800C006006420106006106000000000000000000FFA5F200000000190182180180B801A2580140\n\t180180005070074460A600600604600C00710600600404010500600402200C0840040150C400200400602600000600600500\n\t0000000000000004FF75150100000418A1A01883C8B80180180120182180000068268061200460460064D400700600620025\n\t00040064CC13200C0A50A400004D0160008260C6000026006045000000000000000004FFE9DF008000041801841E01A05801\n\tA00008801801800084E00600600600600610602400600000620000082400603402604400450590001610212091602600000600f81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801801801801\n\t8000806004226000006006006006006016002006006006806006006006080000100140404006006006046006006006006000\n\t000000000000FFCF6B000000001900001833A11801A01801A018018000D0402581614602400603688E007002002004046106\n\t046006826006001052852411004014006046006006006004006000000000000000FFA336000000001801A01823805DE38458\n\t01801801800000602600E00602200600E08400710F606000000005126004006014004006682000A700000068060180060060\n\t07000000000000000000FFA0FF000000001801A01A09841C01905A01841C058000046116006000006006006004006106006000041040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060020000000\n\t00000000FF2F21000000001800001801801801800800001801800000640400600601608600648600608402E0040164060064\n\t06006006000080400006000004006006006006006006002000000000000000FF5B6100000000180000180180180180180180\n\t1801800000600400600000600600600600600600200000600600600600600600000600600200200000600600600600600400\n\t4000000000000000FFF449000000001800201801C01801C01A01C01801800000600400600600600600680600600680200400\n\t6006006006806006000001000802000004006006006006007006804000000000000000FFA79B000000001800021C01801A0500841040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E21608620640\n\tE086008200201002000150006006006006006016012000000000000000FF2973000000001800001A01A01881800880401801\n\t800000681600641000650602E016006D44006444006006006046006546000000800204804204006006806006006826200000\n\t000000000000FFFF92000000001800141C01801A0194EB40051801800000400442600E00402600600600607478E404006806\n\t006006106006060886102814064004106006006006006006000000000000000000FF0387000000021800201801C018018088\n\t0000380180000068AE13612880602700603609700000604010610610600680E086008403006007002000007006806006807000441040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (81005C018001\n\t00684600000600700602E0068000140460001061060060063060060010001002100040009060070060068000060020000000\n\t00000000FF3A40000000001800001801801A0100080100180180000070060004010060060060060011000060880060060060\n\t460060070000070020008042A800600600600600002620A000000000000000FF45B3000000001800601C01801801000801C0\n\t1801800100C00C00E11000450680600E00624400644000600E00600780652600000200600200200000680700600700601600\n\t2000000000000000FF2D5F000000001800001801801A05000821C29801800001628C29E1A700E0860062AE08E0840063300000c41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000000\n\t0000FF4415000000021800413C81A09A2484024D2A192D80008B6916800906CD6026486496A00836826B408C6926C1683688\n\tE8B60202200084020C0880104284886A16A00826D0C000000000000000FF21B7000000081800121A05821D00902481A0D801\n\t800020642650601680600602602600648640E0102072060C6206A46A06801110B4090040C00042400C006107006496044000\n\t000000000000FF2EBE000000001800001801801800800201801A018000006004006000006806006006807007804000006006\n\t006006006806000802002800804000804004006006006004004000000000000000FF7C37000000041800541801801883140D00241040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00A01A21A002\n\t00106B01744701408200120400200A042002004000000000000000FF94490000002000000022800000C00000044800000000\n\t08000000618E5810211000180460200005A80000004601001200905000005402800200002204900000004060040000000000\n\t00000000FF8C2900000028000002000000000040218A40208200002080002860060490010308000064000202002000002000\n\t00000228000800A808009084000008000000000061506C8000000000000000FF44000000000318000C1801821824A0400106\n\t1B01800044406E000010024806C86206200242004010426406186066086006010406026002402040C840040862062002040200a41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1A418000C060\n\t46084006016806C8600604642E00610044640604601601600630020404422424E040A0600E00600620602642400000000000\n\t0000FFE026000000200900500D008C0E40904402A0088280010C300341351334200200A01320300300320910308348314310\n\t3032010052D12012901201002C03003003023513002000000000000000FFCBC9000000000200201103348400201241008424\n\t0001100880900C00A1000020488080081C808800140820800A00800840820A950088112C0800805008000880800CA8000000\n\t000000000000FF2B20000000200900108800A019029E0020801C49800002220241400200200600302640208020200208238200641040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF08910008000AA0AA0920AA0AA0AA0880842AA0AA0000AA80002880882A8AA8AA88002883A02A8000000010000020320020\n\t020200200220290200A202200002A8288280000000000000000000FF4A6D000000200800200200000A00C00A008002008000\n\t002C82842802802000000500842812802800802D12C52D0A8829028080308108800028000028828028028228528020000000\n\t00000000FFD2510000000014002512014010002252350010010000000830804A2080000400484C800804800C200008408808\n\t00808C08C809040C480C034820114014004804800800004000000000000000FFCDD40000000098000218018018838419410400e41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000280000090\n\t30808000000020000080000000000040000000000000000000FF93980000002AA0AA0A82AA0AA4AA0820A00AA4AA00002A92\n\tA82A84A80082A82A82A82882A02A82080002A82A82A82802A82A82A89002000080102282A80002A82882A000000000000000\n\t0000FFBF8900000035415412035415435434C3503543540001550820D50930D50550551308D50C20D50C40800C40D10CA8C0\n\t0AB0AA0500540D514A0A00D50C50800D50D30C90800000000000000000FF0DB4000800000000000000600000428012400000\n\t0001000001001001121001001001021001001001001001001001001001001800401089D4140100100100100100100000000000141040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000080400084\n\t4820900804804804800804804C108008008C0800888800800804D048008C4800004800804804800804004000000000000000\n\tFFF0BB000000000800040200800000808808800A008000002802002002232000002002022112002000002002012002002002\n\t00200000804A412010812002002002002112002000000000000000FF28EC0000002AA0AA48C0AA0AA2AA0800800AA0AA0000\n\t2A82A82882884002A82A82A82882302A80000022AA2022AA2722AA2A82A80702C00002003A02A80002A82E82300000000000\n\t00000000FF3A060000000000004020004000000000000000000000000308000200001001000040000010000000000100040000941040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF04\n\tAA00000040040040040040050040040140140000010010015402110A10810850041810050814000000000800002001400000\n\t10014018401000044001001010001001000000000000000000FFD40C0000004A0C00400C00C10C00C00C00C00C0080010432\n\t0300A00312330348300200300308300000254240240215240200300300300315100101300300340201300300200000000000\n\t0000FF120F000000001800001889801805801801001801800000600600630600600600641643630400600000600608E00620\n\t60161060041044C6006020086006006006006006004000000000000000FF9B1000000000000020300020100022504520100000541040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600640640000\n\t8410482000024016006016004042406000000000000000FFC70D000100000000000141800044022020100042000000022000\n\tE1064302C01080000060000001080000000280000002080000800302205500200A0006000000406040400000000000000000\n\tFFD9A30000000A0000000089810002000000000001000002020414E00E00020020000824E500000200000400408400000410\n\t080810888B20910000848806000200006000000000000000000000FF99DE0000000008000018008118808018048048008000\n\t006002204082002006002212002540142000802DB2802912CEA8A200201600200222402008001200200A00A504044000000000d41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (446410006000\n\t28E00600600600600600602024E0260260B64B60C600408600002008C0000040960060060062960C6000000000000000FFA7\n\tD900000000102000180180184A841821081801880002E40210200E0060160060460024461060110072CF02F0070274160060\n\t06524020054020414006006006242506046000000000000000FF1127000100001022001901811808805805061805080002E0\n\t0629010E40604E00603600010404600000602660660658600638631028018800000030C00600600E02000600600000000000\n\t0000FF1FD3000000001004001821801800801801005821800000602640400004C48610E0060040040060800060060061160000341040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF1ACF00\n\t0000001800001801801821005825801800800100600000220000600600680604320A00E0001060A62B600F0562C600400844\n\t2086082008006006006006042004000000000000000000FFB10B0000000AB8002AB8ABAAB8C92CF8C12ABAAA800048644228\n\t80880642AE2AE2AE2E822008E0005066863C600680625600606200A2862000003262262AE2AE288140240000000000000000\n\tFFE613000000001800001C01801C23001C0500180080008168A284444600680680600600491024680008600E00E20600600E\n\t006C12CA600E040821116006006006044044010000000000000000FF6545000000001000001801801800821831001801000000b41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000202226\n\t2070092AE2AE2AE2AE2AA2A8220000000000000004FF388D000000001800001A01A01A03A01800A01A000000006086006046\n\t0060060070060061000D684000600640600610640600500750A946445040006806006006006004000000000000000000FF2C\n\t780000001558003559559559159519109559540000556D56D52150556D56D575565121405460144562160062C628600E0072\n\tC711645644C0045565565565565125544D0000000000000000FF3C7F0000000AB8002AB8AB8AB88908988D8AB8AA000112E0\n\t08ACE28E48EAAEAAE2AE28E22A40600304E956816CB723688600428802220F09000222E2AE2AE2AE2AF20CA880000000000000741040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4E0060060960\n\t0600600600600E0062C032E02E43653634E12E20410011010804410008600600600600600610E000000000000000FF60EA00\n\t0000001800001C01001C4180384500180080008060068420400068068060060220A6007000C4620630600620620600490092\n\t1000906000007004006006002006816000000000000000FFB430000000001800201801A01805A41800A01A00000000600600\n\t600600600600600600620010601001681600624608688600425001211604C800006006006006006804100000000000000000\n\tFFE6700000000AB8000ABCABCABC89C89C88CABCAA00002AE2AE28A2882AC2AE2AEAAE28A00822F0000860A682E88E82E02E00f41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFE3AB000000\n\t001800001801801805801800001801800000000600400400200600600600401600610040620610600602604600400400000A\n\t002000006006006006004046100000000000000000FF8E080000000C98000AB8AB8AB8898AB8838AB80000002AE00628E0AE\n\t1042AE2AE2AE28E2062AE00000660608600604600600C2122302203840002262AE2AE2AE28E23A226000000000000000FF49\n\t5300000000180000180100182580184180191400000064060222004260060060060421260060040060860060060064061440\n\t52004000014444016004006006042106006000000000000000FF8C9800000004380000180180180180180900182080000061000c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (421022242540\n\t102AE2AE2AE2AE2AC002220000000000000000FF17E100000000180000180180182180180200192180000004260002000260\n\t060060060000160064040C60A60460A6286086000026100002002004086006004006000084000000000000000000FF18B700\n\t00000AB8000AB8AB8AB8898AB88C0AB8AB80002A82CE2AC4AC2AE2AE2AE2AE2CC2A62AE41004E00E24E20E00E20E2AC21622\n\t83202822802AE2AE2AE2AE2CC28C228000000000000000FF3053001000113800155955955915955950155815800055011655\n\t01302125565565565504C65560C42160164964160164362CC5044404C824A54444E556554556550446550000000000000000008c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400400680501\n\t700609402000E40400620600600602E00E006400416414004004106007006116105000000000000000000000FFB3BC000000\n\t001C00001C01801A41800004001821800000210E00420400600400600600410880628832E02E43653634E12E0060C8456096\n\t104110006006006806004480110000000000000000FFAE50000000201800001801A01805800000001C058000000026044045\n\t00200480600402400000600400608700600600640600600208200604C404006006006006004052000000000000000000FFB2\n\tA80000000AB8000AB8AB8AB8C98AA0E80AB88980002A820628C08C2AA2AC2AE2AE28C2202AE0001063460861465061062AE3004c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8E8000000098\n\t00005C80001809800000001801800040010610C30440600401680600400040620000640600608610621600248008200E0000\n\t0044E000007006105002000000000000000000FFBF91800000009840005C0184180980180000180180000020061440440030\n\t04106006004002006000046006106506006006006002002006000000446006007006004002000000000000000000FFE70880\n\t0002401A20011A01C2FB81801810401C01804100100603453540300480600640C002D8600002600708627610640600614230\n\tA204000000016006006806004002000000000000000000FF5C59000002401800401901C11801800000601C018000C028864000cc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000200050\n\t41100060A6004024400000000000000000FF927A000000001800001801800001801800041801820020629620408420240605\n\t800601400640629000622622E0063060860060042AC11057A1000840060060A6004184010010000000000000FF1FD7000000\n\t001800011821800023801810023801804000C00640401402220610000650404601600000608600603E056026026044004082\n\t082000104086006116004004000000000000000000FF9E1D000080401800201880291901800004501A01882008202E094004\n\t017084A2600600C00020600800601600630614640610250000244C20008820640890600600402A210008000000000000FFE4002c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (110100050000\n\t004020000000000080000000400000000008000108080080090046006000004120000000000000000000FF7E3F8000000000\n\t0000000185200002800014C00000003480000060064400000800500060000004803280284305301483280901200082400002\n\t00000006006000006010000000000000000000FFE929000000001800001900110843800004081001800000E0064140040040\n\t8620200600400400650000610E00628622622608208600044200200800420008600600400C000000000000000000FF835600\n\t010000180000184000090180000000580192404865261041042520060020060040040060000064262560560061060424064C00ac1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000AA8000A\n\tA8AA8808AACA2800108AAA80000822AA2AA2AA02B3222AA0222AA2322AA08004A00A24A20A22A20A2AA22222A12A23240022\n\t22AB2AA2AA2AA22A000000000000000000FF8371080000000000000001000001040000200001000108880400000000000100\n\t08000000840002000C00A00400A0080080480110000000080480004020000800000090000000000000000000FF5792000000\n\t0AA8000AB8A20848AA8808000408AA80004122AA2AA2AA00222A2022922AA2882AA4001023420821421021022222023A6002\n\t22A10032028A2AA2AA2AA204000000000000000000FF24610000000000000000098000000040000000000000004000004004006c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100080000040\n\t000000000000000000000000000000FF59F58800004AA8006AA8A28888AA8908000AA8AA8001A23AAA0AA0AA0022AA2222AA\n\t0AA2232AA00000260208200200200208222A2003222220002AA28A2AA2AA0AA222000000000000000000FF789D0000000010\n\t002010014480012100004022010001020804000000284809000C800001050040004002001000000000400001080044001000\n\t00014001001004000104000000000000000000FFB453000000155800355955335D55905800155D55800044655655655632C5\n\t564D6556556454D5610021601649641645643605644652C44E456000556516557556556444000000000000000000FF8A140000ec1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (288803000000\n\t00000000080400001A00800200001800000000200000000000000000001800000000000000000000FFA76800800000000000\n\t000020000000020000000000000000000000000000808200080000000000000000000000008A882800000000000000000000\n\t0000000000000000000000000000000000FF79D000000000000000000800020000800000000000000880002002002A000011\n\t0000400010000480328128430530148328200080120010010200000000001000400108000000000000000000FF2C9C000000\n\t4000000000000240000240000002000000000000000000010000000000000081000000000000000000400000030000010080001c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001801\n\t001001801801A01803800000E00600600600610E08608E006026000000086206006086226056000807006004204000006006\n\t006000000006000000000000000000FF0AE10100000000000090011030014814210011010000040004020000100444040404\n\t004004000000000000000404111400100440001005004000004000000000000004000000000000000000FF08600000000000\n\t0000000080080020080080080000008020028020020020000020000020220000000020028020822020060802428030010000\n\t00002002002000000002000000000000000000FFF37300000000000000000028000000000000008200000280008000001002009c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000008060060\n\t00000000000000000000000000FFBE0E00000000000000180000180080180100080080000020020020020020060020060020\n\t02000000002002002002002002001002002006006000004002002000000002000000000000000000FF78A500000000000000\n\t0001004001100000400001000000000400000000100080000000000000000000010000000100000400000000180180000000\n\t0000000000000000000000000000000000FFF1B4000000000000010800800C00800840800800800080200204300200300201\n\tA002002002000000002082803003002002000003002002062000003002002000000002000000000000000000FFC27B000000005c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200E00600640\n\t04208462060860A6507106020001014003002108004000006000000006000000000000000000FFF14A000000000000001800\n\t0038A9801841845801800040640E00600040C00614200600600608010010600640E0160160060000D000400400400000C080\n\t00E000000406000000000000000000FF1FF10000000000000000018000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000006006000000000000000000000000000FF59CE0000000000\n\t000000018004000000000000000000004000000800000001000000000000000000000000005000000000000004800004004000dc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018400049\n\t51801821C05C018000407216002006046026105016116016100240005A862021479060260201288160021022900060000100\n\t00010406000000000000000000FFEA79000000000000001901800001949851881C8180000240A6006C062060060230060060\n\t06010090126006001106246086000004804000850000044006080000000086020000000000000000FF3DF300000000000000\n\t1801800801A11A01821901800004600680600600E00620200611681620000008690608A00E86E04600000400500016040000\n\tC886100000010106040000000000000000FFDED3000000000000001840000801801801C818018000007146007006026046C0003c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (E84600600000\n\t0006000000000000000000FF2044000000000000001C019A000381180180180180000C500600200704600600600740600600\n\t000010400400100700401E0000050A7000000060006806806000001006000000000000000000FFFE71000000000000041801\n\t804821801ED18018018000286006086204086006206006006006008028004804000106044006000084106480450200006007\n\t006000000006000000000000000000FFED380000000000000D1800012041811B018118018000245026906006144006B15006\n\t406806000020804084003806006806000100007B04404400016040000000001006000000000000000000FF6459000000000000bc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006007800000\n\t0040241064060C6006000001906420C20100106006006000000006000000000000000000FFAB3E0000000000002018019424\n\t41801A01011901800008C8270041064040060061860062864000041044144062060061061800200968000000C50060860060\n\t00008006000000000000000000FF1245000000000000001801800801C0182304180580000060D600400400E0060068160065\n\t0601000000410401611601643601004000610410C20000710E006000010106000000000000000000FFAC2C00000000060010\n\t9B018508058A1801009801800000604780400680780609600680600600000400410600600600600600000004600380200404007c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (988994A0C380\n\t1804851905800008510600610645600E08E006006A06410006906C3400611613600600100600516080002700600622600000\n\t0106000000000000000000FF4E1C000000000140401C41C40011C49800801801800000408600600600600600600600600600\n\t001000610400611600600610040654400A832290806026006000000016000000000000000000FFF343000000000000001C01\n\tA00001A01940805841800020401600620600600700600E0060060000040060C62960060462CE00900600C4044B4224086016\n\t006000000006000000000000000000FF656F000000000000001801804001801901005841800050C00600440604600680600600fc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006000000006\n\t000000000000000000FF77B0000000000080001825800A058111018018018000806006004806006006006006007006006004\n\t006006004916006806100406100555010044046006446000000016000000000000000000FFC1CE0000000000400138118448\n\t098216018018018000886086004084006016806006006004006011006146004807046006000806C5000002029000E0460060\n\t00000006000000000000000000FFBFF4000000000000043D03990101801AE080180180000040060070840040061160060064\n\t0600000000600400600700700600000600D28000000002E01E006000000006000000000000000000FF3C7B0000000000000200021040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (048360A40565\n\t0E08641608E086030824917000006004004006006000000006000000000000000000FF3BBF00000000000000180180080180\n\t1001001803800000600640408600600600640600600600600048600640400600640600000000600200400000400600600000\n\t0006000000000000000000FFFC4E000000000000001801800801801000801801800000600600400400600600600600600600\n\t6004006006004006006006000006000000000004006006006000000006000000000000000000FFC06B000000000000001C01\n\t800801801001801801800000600680400600600700600600600600600200680600400600600600100300100000000300600600821040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800801C01001\n\t801C01802020608EB2448600E00E7862261AE20600E0A020E00E28420E88E28602802288E040004000006006006000000406\n\t000000000010000000FFB0C5000000000000001A01801801801901001C018000006006006006006006026006006006806004\n\t006006007006006006000084006906020405804006006040000006000000000000000000FFEEF4000000000000003C01A008\n\t01801C01001803800000600600600600602606600E0060060060000860060040070060060000006060010020000040060060\n\t00000006000000000000000000FF79A1000000000000403881803881A8B02900188180204260AE04C20621602EC8602E0B6400421040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000060000\n\t00000000000000FF2AFE00000000000000190000590191585180190180000470460164074060062A60060060060460010465\n\t06006007006006000087006004024000006000000000000006000000000000000000FF3AEF00000000060000180000180180\n\t1101801801800180600680400600600700600600600400600000600600600600780600100200600000400000600000000000\n\t0006000000000000000000FFEC92000000000000001C01800801801A01801801800000600608640600700680600608600600\n\t60000060060048068060060000068060C0804400006006006020000406000000000010000000FF9C0500000000000040180100c21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (604000640610\n\t6086006206000126000348804000216000006000200006000000000000000000FF7E5A0000000000A0409800209C09A81A01\n\t923A89800002E28EA06896116296206810C86C0EA06800C46816807086CD6A86000930A40022006800206C00D06010200826\n\t000000000000000000FF5E22000000000000003B45C458C585590580180380002860060B624602680690E52000610610E020\n\t09634648600E00604E001C0601030E53404000600600000000010E000000000000000000FFBF4E0000000000000018018008\n\t01801001E018018000006806004004806006006000006006006002806006004006006006000002001801806002006006000000221040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00800800000A\n\t0980000A601220200A00A88E80E28228220200200060202220200A4020020002020030040000010004020020080000020000\n\t00000000000000FFC5DE000000000000100401916202008400002040000000018008C1A040084008041800000C0005200000\n\t804000000204E0000080120020080460000206406000000008000000000000000000FF2F310000000001000404A58000C006\n\t04800000000000008000440000060800C400000000800000000281180C0000000108000018458C1117000084010628610000\n\t0020000000000000000000FFB9E500000000002000DA00001111801841AA18818000806A0E1062449060062160000060042000a21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080400000000\n\t0000000000FF7EDA000000000000301A230C1803A01941A01A4180000868165060C624600640620600600600608040611610\n\t6006556126000006546124096200026106006100000006000000000000000000FF57CF000000000080432800C0AF28CA0800\n\tC00800800100310302320B10284204B81300300300324100320344350300320200150B00AA0884104080B203402000001002\n\t000000000000000000FF4C0200000000008021104224802D5821032002020000B00804820C10884200801020800800088800\n\t880A00800D00BD8800000C00A0108120C801004800800000000880000000000000000000FF5860000000000000002801020800621040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001001020000\n\t001000000800800C48341002801041040000001000000000000000000000FF0E900008000000000AA2A20040AA0AA0880AA0\n\tAA0000800AA82200000902A82902A82A82A80000002200104002A82082A80002A02302184080002202882888000002A80000\n\t00000000000000FF0347000000000000200010A08A00200A42A00A000000402002882912C00000808802802802802A008128\n\t02B0280292280200000200A000822800112842842000800802000000000000000000FFF80F00000000000000100132200100\n\t020100100100008CC004810C2082C004844000804800004900884D30849004801000000808900144284B000048008000000000e21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000400040000\n\t000900000902000008000800000000000004000000A010100112000000009000000001048008000000000000000000000000\n\t0000000000FF46D20000000000000AA0AA0C80AA0AA0A80AA0AA00002A82A84003202A8AA82202A82A82A80002002A82A830\n\t8AA82A82A80012512A90800105012A82882880000002A8000000000000000000FF75E20000000000003541542C8354354330\n\t3541540000C40D50C40950CC0550C41550D50D50800900D50C00830550408D500014415413208A0801448D30D50800800D50\n\t000000000000000000FF935B000800000400400000402000000000400400000100100111100100080100100000100100100300121040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFCB130000000004002000112102002002000000010000004805008848800004800804004804804802804800808004\n\t8008000000A4004144280D02004800800004004804000000000000000000FFE3A6000000000000000A00884800800844A00A\n\t0000008000021423020020000820000020020024000020021228020060020000000000008220000020220020020020020000\n\t00000000000000FFB1160000000000000AA4A20204AA4AA48C0AA0AA00002A82A82400102A8AA83382A82A82A80001802A82\n\tAA2002A92AA2AA000B08AA8A09008000AA82882A80000002A8000000000000000000FFC4DE0008000000000004000000000000921040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (12012302A008\n\t420005062B000E0220000002521020C0002002000000000000000000FF74EA40080000040040041540044040040040044000\n\t0101500140040100100521100500100100100100001800000000800000000014400000100022440000000400100000000000\n\t0000000000FF77AA400000000400408D20C20D00C00C00C00C00800100328308A00300300320300300300310300304200200\n\t3042542002101023001003003003002002003003003002000000000000000000FFE95E000000000000005801001801801801\n\t801801800000604600601600601600600600620600600000E2060063060140060001144040B424600044600600610600600600521040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801025800000\n\t60060C400048010600614620600600600022600610601600E0160000020A2100000100006040006004006006000000000000\n\t000000FFA6F70008000000000001459000200A204180002000000000000800203001002500080000000000404400200A0010\n\t0100002A00003400B0240228100006006000000000000000000000000000FFED5F0000000000000101358201000000018000\n\t4000000103000882000000000040000004001000000282000049401200000808CC800940C040008000060068008000000000\n\t00000000000000FFACD5000000000000006810000820800800800801810000202624200A04200A00A002502002002000002800d21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFF4550000000000000010019208010A900180100180000060060842160060060021060060060062000060464000065062\n\t2E000342092008104300006046020004006006000000000000000000FFBB5B00000000000000180188180580580180100180\n\t8028600600602602600644600600600600600000702E00A0070070062C028401000014444000600E08004400604600000000\n\t0000000000FF030100080000000000594001980380184180100380002860060060060020060160B610618600604001E00604\n\t670600604E018004404650498090106000006004006026000000000000000000FF0ECE0000000000000018120010218A180100321040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (82AE31700600\n\t022022020A2C41002A628E28E0060062AE000000000000000000FF36C2000000000000001001901801001091801801800000\n\t70060060070070060069060060060065000060060000060262D600024800000A0AC400006006006806006006000000000000\n\t000000FFCDA22000000000002AB8B2000AABA03AC98AB2AB8000AAEAAE60E004AAEAAE2AA3262AE0162AE5802AE2164C22AE\n\t00E086000910A20066818000A262882880060062AE000000000000000000FF2437000000000400001A080138018018238010\n\t0180000060060460A600600600600E0064CE00680000608E052006047006000010004486240800116000000006006006000000b21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AB80002AE2AE\n\t2AE2AC2AE2AE2AAA262AE2AE2AF0042AE9062AE2AE00702E0002232221232810052AE28E28E0060062AE0000000000000000\n\t00FFF1F4000800000000401401855C01455401801C01800100600600614E00600600700E0061060068000065061060068465\n\t2E001003112906800C0080E046026006006006000000000000000000FFBE9E400000000000555D55815D55D55C45955D5580\n\t015565565565565565565574565565565560045564565565565160060011044D422640010455655653700600655600000000\n\t0000000000FF99870000000000000AB0A3B008AB08108D8AB8AB80002AF2AF0B64062AF2AF2AA2262AE2462AE0002AE8460000721040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t1DD700000000000012900180C80B00B001801001800000600615610600600600200600600600600000624E0CE0062064D600\n\t030020C08010E000100046046086006006000000000000000000FFCE34000000000000001211812801001021001001800000\n\t600600400600600600210600600600690400604600600620EA06000808008408036B06000006006006006006000000000000\n\t000000FF14BC000000000000201001B20A01201295801A018000806806806006006806802016006006006200006496006006\n\t946086000104900882800000806046026006006006000000000000000000FF913D0000000004000AB8A38408AB8AB8018AB800f21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (52645600048A\n\t4324D0552004556556536450550556000000000000000000FF4FE68000000000018010018808018018018018018000006000\n\t00608408400601600200000600600200414602600604E00600011200A04210200000E0260060000000060000000000000000\n\t00FFFDE00000000000000110A38008210010AB8818AB80002AE2AE0042644462AE2AA2AE2AE2AE2AE0022AE0064062AE02E0\n\t0600002008022022600222028E28E3262AE2AE000000000000000000FF6CC90000000000000050098C090114100105580180\n\t0000600640601654E00600200600600600600400610620600610600600001004001000600400800600601600600600000000000a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002AE2A82AE4\n\t062062AE1062AA2A82AE2AE0002AC0063062AE02610600002040021020200022428E2EE2A82A82AE000000000000000000FF\n\tD854000800000001841001884821801801851801800000600000E20600E00600600600000600600400600608600600E08600\n\t0046106006002006006006006000000006000000000000000000FFD42E0000000000018AB0AB8308AB8AB8AB8AB8AB80002A\n\tE2A82AE0362362AE2462AE2A82AE2AE0002AC20E20E2AE28622E0002460A228422A00032628E28E2A82A82AE000000000000\n\t000000FF784C00000000000190515584891594B95590395580005565505461161065565565525505565560045544B6056556008a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFC072\n\t000000000001A41805801C01A01801C01C018000086003006007007006016807000886006005046406006006016006000000\n\t2000100A6004404106006000000006000000000000000000FF146A000800000001801809932A01801801A01A018000006002\n\t00600400400628600700000600600000424E08E0062064D600030005095204E0000140460060000010060000000000000000\n\t00FFFD9B00000000000180100180180180180180180180010070000065360B680603600600000600600400410682680610E8\n\t06000810284002902004084006006000000006000000000000000000FFD4C60000000000018AB0A38048AB8AB8AB8AB8AB80004a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (161480001002\n\t80002000046120000000000006000000000000000000FF9B52800000008081881140001B13801800001841800000700080E0\n\t06806007016006000006006000844006002286046006080008420002022000006300000000000006000000000000000000FF\n\t9268800000010001F019518008898018018018418001017502096004044007106006101807C06000004006001D0604600610\n\t0000144002002000006006006400001806000000000000000000FFC6BF800800000101C21003800A05C01861A01A01800108\n\tF08040600602680608700708080620600000420700100600E80600101008080900200000640600620000100600000000000000ca1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600600\n\t6006002006000006016000046426506106106016000006082004000000006000006000000006000000000000000000FFF9F1\n\t0000000000018018118418858018018018018000006016046006106046000016000006006000026036002016206006000002\n\t20A45000C002006006000000000006000000000000000000FFE11F0000000000018090118208038818298018018000006404\n\t78600608600600008600010600E00200600E20008608620600000200202A18420A4060060000000000060000000000000000\n\t00FF5E39800000100001801810001821801800401C018000C0600A0260060270260260170000060060000064060C20160060002a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFBB540000\n\t0000000000800980000000001180000000000001340000002000000480040000000000004001002D40001080000001001004\n\t50110100010006006000000000000000000000000000FF51278000000000000A00018A000000000180000000000002000002\n\tD01400000800000000000003001482480000002404B0000008010000000400080046046000000000000000000000000000FF\n\t859000000000000180180000100180182000180180002060064860040240060421060000060060000060060260062062060A\n\t8006216106110410026140006000000006000000000000000000FF3D2800000008000181180000192190181000180180000000aa1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C2C54443440\n\t4400556556556000001D56000000000000000000FF8A270000000000AA8308AA8008AA8AA8A28AA8AA8000AAAB0A2AA0CA0A\n\t2AAA2A22AA0002AA2AA50002220B1522AA2A222A0002B22A2032A224802222CA2AA0000002AA000000000000000000FF95E2\n\t1000000000010000000480000010010000010000004000000000000005080200801001000001000000110800008080000104\n\t01010012C080004000000001000000000000000000000000FF00BF0000000000AA8068A300A8AB8AA8B28AA8AA80002AA002\n\t2AE00240A2AA2022AA0002AA2AA0001120020022AA00010200022223648632200032028A28A0000002AA0000000000000000006a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t1004000010000001000001010B00001000000001104B0100100000000040040000000000000000000000000000FFB9398100\n\t000000AA8AA8A2904CAA0AA8A28AACAA00002AA2232AA2AA2AA2A82220120002AA2AA0002AA0032422AA00E0020002000002\n\t002200002AA28A28A0000002AA000000000000000000FF2D4480080000000110000115400100100100140100008048400042\n\t00008804810801001005004003400140A0100400800000100400410481400200C000000001001004000000000000000000FF\n\tFC2D800000000555955955001955D55955555B5580015575565565565575564578C60015575565005564B64075565444560000ea1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0D4F00000000\n\t00000806000000020000240020100100020880000001AA80200A80208000002802A800000000000014002804100000000043\n\t02A8000000000000000884000000000000000000FFA1C5008000008000020000400000002000000000000000000000000000\n\t0000000000000000000000000000000601008000000000000000080000008000000000000018000000000000000000FF9130\n\t08000000020000000809420040000820020000000008810000000008000090D00000008004000002480008002404B0000040\n\t000048008500000000000000000800000000000000000000FF1A2A0080000000000000000400000000000000000000800010001a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (182002002000\n\t002802002000002010082000000000000000FFD0BD00000180980182300100320380B88182B88808A180608E00602E08E28E\n\t88E0060042000860A002008600408700E2080268050070078260A000E006006000004080004000000000000000FF67970100\n\t02000001101001001000200445001000000005000100400444404404404400400040441000000541044014484000D0044100\n\t00510410004000110000004010004000000000000000FF002E000000800800804800804800810C8085088010410130128020\n\t50000512000000802400002000040082C16143002400002000C12802802000002802112000003000002000000000000000FF009a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000010\n\t00000000000000000000004001000000000000000000000000000006006000000000000000000000000000FF32A800000080\n\t0801000801200800800800201000000000200200200600600700200300000000200000000200240200400001080400200200\n\t2800004002002000002000100000000000000000FFD735000004000000001400001000000001200000000100000000400000\n\t0000004004804000000000000000405000001000000000000001000800000000000000004000004000000000000000FF2049\n\t000000800800000C00800800A008008008000000002002002002002002003002002000002000000002203002003800002000005a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001805801\n\t0088000509019018005018400020086416416946517207006006004000006000120116000857016001006502810102006000\n\t006880006000007000006000000000000001FFA2BA00000180180100181000180382182A0058000000006086006406006106\n\t106106204000016000000006208006486080006000006006006100006000006000006000006000000000000000FFBF290000\n\t0180000000000180000000000180000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000006006000000000000000000000000000FF5FAF0000018010000000018002000000018000000000000004000000da1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010060000068\n\t00000000206040004000000000000000FF11EE000001805A01800808020905841954101840000000641300F3460060872060\n\t360020000060001000164040D6043880006502006104006000006900000010006000204000000000000000FFA9B1000001E0\n\t1801008001800005281011801800002000440520640628EA0600600600500010600012008610011200E00080682008A40A1A\n\t6080006006000000006801006000000000000000FF67E300000180180100080180E801C01B0180380000000860E400601E00\n\t60064860D620400000E0000000668081022C680000704010601695E000006006000010006000406000000000000000FFD322003a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600640680600\n\t2100006004000006100004006000404006404006004004004006006000002820000000000000000000FF5411000001C63809\n\t8C00018880012030018018000001004400606407607246007006002000816008000006604077007000006200002401106000\n\t006006006000007000004000000000000000FFB4C4000001803809880511808003C039018018000000004002026006026206\n\t02600600200910600A100006004107006000006400006004007802006806006000406000004000000000000000FF57E80000\n\t01C018818409080048010013000018000000006002026006047046226006002890016000000006004806002000407000A02000ba1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018010000\n\t01908001201001801000000000400010600640600600601704000000E0008080060144042460400040040000021040000040\n\t0E006000002000000000000000000000FF130800C001801C014508098888510F149981103810000460200064160068060864\n\t660001403E600010019680401C086100004064244006004001004006006000863000000000000000000000FF322800000180\n\t1A01000011A00001901923C0104400002040C004610600E00610600640201040600400020720400510621000C80C40020301\n\t4004004006006000002001000000000000000000FF6B8D000001801881000C01B04801801811801000000080600000600680007a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600080600600\n\t6000000800002000000000000000FF6F14004001001801052001E0804101100D811004100000410210610601700600640640\n\t7140006004110017C04806004020004800046806016004006816006001802000002000000000000000FFF54A000011A05805\n\t010003800401031005801000000002400100600600601600E487004000006004000016104016004000114052032C02806004\n\t006006006000002800002000000000000001FF1D2D000001001801000401A00209401441801000000042400284620E206006\n\t00601604500801600100020600CC072442D0015008006406106001006006006000002000002000000000000000FFA7A2008000fa1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (806007000006\n\t006004006007006804002006005004002806000004006006006000806006000000000000000000FF536F0000080010052008\n\t0180080100080380180000000068060060060060060060060000060060040060161060140020060060060164870020040068\n\t06000000004806000000000000000000FFFA48000001E05001012E0D808881050811801800000004680600600400600E80E4\n\t06000126006004006006006007002026116016086006800005006006006000006006000000000000000000FF25B8000001A0\n\t100100020980608100120180100000000040000060060060060061070060A00060000000060048078040000048400C68868000061040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100100380180\n\t18038008A9823820000002600655612C10600604600E48002600600104600F48688500600708400C00400500400100480600\n\t0001006006000000000000000000FF9B75000001801001000809880801000801801800000000600600600600600600600600\n\t00060860041060060060460860064040040000040A4004004006006000006006000000000000000000FF181C000000001001\n\t0008018008010000018018000000006006006006006006006006000006006000006006006004002006004004006006002000\n\t006006000000004006000000000000000000FF9E5E000001801401000801C00801000401801800000000600600600600600600861040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (806006020000\n\t006006000000010000000000FF1E6F000001801801800801800A0100081180180000000260062AE0A6086006026446280026\n\t0061000A600E206086C828063C480C402006044140007006006001006016040000010000000000FF289D000200001601001C\n\t0190580181460191380005400062560065560164560061160005560164540061068064440065560069061041441144140040\n\t06040000006086000000000000000000FF3737000001819001010801800801180001C0180000000060060060060060060060\n\t0E001006086006006006006024006006007006000004086006004006006000006006000000000000000000FF00CD0004000200461040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000060060\n\t00006006006802002006006002002006806000006006000001806806000000000000000000FF43AB000000041801815C1010\n\t1805800550445C4000000060060060170060060060060000060060000060061068070010060060062060068CE00000600000\n\t600000700E020000000000000000FF5F7E000201801C01801800105A01800C00003800008000781600600C00782600621600\n\t02860060800060060064060020060A60860021260244A0006000000000006086000000000000000000FFFE99000400001801\n\t800A0180080100C809B11C00022000622700652700E217006126000856016448806106006046A0254E00400408600680600800c61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (181000001103\n\t845002181884000040602680602480E02681610E00800600600000611E00E3000020064C4004086006204000806000000020\n\t406206000000000000000000FFF242040220333221355A00201AA1AA04020298800000906046026C1648EA2644704E048846\n\t94680080EAD6C8E230800A168C4A24930C040068A0046880806040B06A86000000000000000000FF04B30000018010090019\n\t4589380B800881905820000041628E90614602608E8164864000862060800060060271005300A70068860060A65540080060\n\t06206000016046540000000000000000FF36B4000000001401000A01800801000801A018000000006006006006006006006000261040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008000008880\n\t04810000000000000000FF31AD000020921000002A00000800801840429800000000680A00600308200E0064060400A20820\n\t00002682102840164002032402072002806000044002002000202002020000000000000000FFA8D002000180A01800020184\n\tA00013000580002000002803410010080011012292304200002200100000204900904805C080138040800004018000058600\n\t60000060C0000000000000000000FFCA480000018040000280A599007C000181A02000000110088100008000100010000020\n\t00000001400000000008012182000000300003A0818448420006606000116020780000000000000000FFA96C00000184110100a61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0004804C4000\n\t4800800905004000000050800880914800004800800001010004810000000000000000FF8DE6000001933801841823011841\n\t84114188380400000060068060068060061160064200060060400061162060262CE006426A0E04610644C010A26306006000\n\t08E002288000000000000000FFECE3000400C00488510800D40C8AC92C04800800000028214A203102002103003292001003\n\t00311120320311231200354B80B103413412003321003003402001403042000000000000000000FF48130002002902212500\n\t4320028028020120400000008088144A0301224280000080800000800880408800A20C28800038000000800C10CA0830800800661040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004224004004\n\t0040020000000010090010000010000000011010010010010010010010110000018000011011080014010010010000010010\n\t01000000000000000001FF85CC0008AA0880880020A20400000000A20A80000000800010AA82A8AA82A82A82A82000002A80\n\t000002A82A82202380002A0800080220220220A20288288000000000220000000000000000FF6A74000200A22C00AC0810A0\n\t0A80A20C10C048000000410820002802000800801000130802002800802802802812902802012482A2A81280280011282282\n\t2801542800900000000000000001FFED1D0002002012452102012CA2542934012010000000924B140048000048048048048000e61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80002B00002A\n\t0000000000000000FF46310008000AA002112400002000008010002000000000044100000000100100000002000000022200\n\t00000010810010000090C0100110000022080000020000120000000000000000000000FFB4360000AA0AA0AA0A80AA0800AA\n\t0AA0AA0AA00000012A82A02A82A92A82A92A92A82280002A80000002A84C02A02880002A8228208240AA80082A82A8288000\n\t2A00002A8000000000000000FFC1320003542003502401542902D232234435040000012D0900550D51550550550D50510800\n\t550800800D50D50450540000D40210A30C40D50A00C48D30D10800C10800D50000000000000000FFBC93000C00400400404200161040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006106\n\t31601622401400400400600600400000600600600600C002006000000000000000FFBC3C0002002012012400112042002002\n\t012010010000004890804800004804004004808804800C00800800930905044800804084A28A100048008048408400050048\n\t04814000000000000000FF8C7F00000080000008C8008D080080081080080000008000020020028000000000001000020000\n\t0800200200204A112006002810082142002010002002002002012002002000000000000000FF66160000AA0AA0AA0006A201\n\t00AA0AA0A20AA00000002A82202A82A82A82A8AA8AA82200002A84100002AA2122002410022A9320040000AA82002A82882C00961040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (880080480100\n\t180480800060122160020060860220025400022800100028028020126A480001241411211200600044000200200200240004\n\t4000000000000000FFC1C3400988401401440504480400400400400401000100100100100100100100500506100110100100\n\t1000000200018000000000000000001000444000001001005004000000000000000000FF7ED8400000C00C00C00C00C00C22\n\tC00C02C00C00800100300308B003003003003003001003401001003402003203102103003080002003043001002002003003\n\t003001002000000000000000FF574C000009801001903851089801801801801801808000600640600600608604600600004600561040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002006004000\n\t000000000000FFBB8F000009810905801004021001801829021801800000600E006004006006406006000026400400006006\n\t08640604E006004000010146016410022004014086002406046000000000000000FF772E0008099080000800218240200000\n\t3185000000000000000200000402402000500005400004000060000904001500200000000004200004300000060061000060\n\t40000000000000000000FF21CA00000180000008011380002400000380000000000000041080000000000000000000200000\n\t00006500510810800110800900004000820000C40006006000016000800000000000000000FFC80D0000008009048229310000d61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00006046A562\n\t8620222601214003020E014800016044022007003006000000000000000000FF20B900000002282593080193180C12500980\n\t1801800000600600600E0060060060060000060000000064960860260A809610000A2041464A604008600600000600600600\n\t6000000000000000FFC28100000188280190380180D840803800801803808000620604E0060064860460062A00060000B020\n\t700700611628104601041200420E10604020E002002006006026004000000000000000FFD275000800002819803952009801\n\t81980001180180800062060060060460C60260560005062000A02060060160860060060040001600040EA00000A00000E00600361040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00B0A3CAB801\n\t80002AE2AEAAE2462AE2AE2AEAAE0002AE2A90022AE32E4962A6A8D04628AAC010404E22D00232628E28E0062AE2AE806000\n\t000000000000FF198C400000401C01F01801E018000012088018018000006006006006806006806006800006000000006086\n\t0C600600600600213022400600C000006002004006006006004000000000000000FFAB4F0001AB88D88D9508A2005B809418\n\tB20AB80180002AE2AEAAE0242AE2AE2AEAAE0002AE2A80202AE00604600E042406262A10480006004000A262882880062AA2\n\tAE806000000000000000FF2C90200000201A01805A10003840A11801001C018000007006006486006006006006000006000800b61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (068060000000\n\t00000000FF09BD00002A0AA8AB8008A38418AB905AA28ABC0180002AF2AE2AEAACAAE2AEAAE2AE8002AE2A90002AE006C062\n\t2E2262062AA00C2002AC2238002AC28A28C0072AF2AE004000000000000000FF70C0000801800821801C0184180340140180\n\t1801800080600600711700680700600700000600004000700680600E00611600200604848510204101404604600600600600\n\t6000000000000000FF8EE5000154154955853D5590BD55C31D449558018000556556D56557556557556D5700055655000C55\n\t625681654E556336552C06088554542015554532554006556556804000000000000000FF644000002BCA9C898048B388982800761040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400641600602\n\t610600A000106206012084006042004006006006454000000000000000FF3A4900000182C801820801809801001001801801\n\t800000600600600E0060060060060000060004000063460A60062960360820300160D6086240096006006006006006086000\n\t000000000000FF50F1000000200A018B0A11921801213000A018018001006006006006007006006006000006000800004A46\n\t34608691680E002000026006012010006022004006006006004000000000000000FF528A00010180080180280180B8011410\n\t118018018000006006806006006006006806000006000008006096016006006146002B24108004906000804006046006006000f61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (541559540000\n\t5565565540965565545565560045560060845564864B65563563564D24445560165464C444E5505105505565561540000000\n\t00000000FFC89980010184180100100180180400000100180000000060060040040060040060060040060061000061261460\n\t060064060420800C6006006100006044004000006006004000000000000000FF91D50000AB8000AB88A8A38138190030A38A\n\tB8AB80002AE2AE2AE0A42AE2AE2AE2AE0002AE0000E02AE04E0062AE00620622238022600622600022628E2EE2AE2AE2AE00\n\t6000000000000000FF8E3C0000001008018008098C1945131008801801800000600600640600600600600600000600000400000e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF793300002B88F8AB1610A38AB8880AB0A30AB8AA00002AE2AE2AC2AE2AE2AC2AE2AE0062AE0060802AE01E0062AC26\n\t42063162B42002AC16E00024628C28C2A828E2AE400000000000000000FFBD770008800C18010AB0018C1900121000001800\n\t000000600600442600600400600600400600640000600E0060060040060020100062C6014000086000000000006006204000\n\t000000000000FF622200002B8898AB00D0AB8AB8B00AB0AB0AB8AA00002AE2AE2AC2AE2AE2AC2AE2AE0042AE0064082AE206\n\t20E2AE28C0AE20222420E2AE21420828E28C2AC2A82AE2AE0AC000000000000000FFE72E0000540159550011558038440131008e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006004616506\n\t14420400400001000004A004004000006006006000000000000000FFC7F40000440018051018458018008030010018000001\n\t0060020068078070070070060870A78060040060060061040C60060064042000800840040160040040000170060000000000\n\t00000000FF8F8400080180180108580980184000101100180000000060060040060068060060060060060064000063460A60\n\t04096036106000050000306210016024004000026006080000000000000000FF3BF000010044180101100180180480100100\n\t1800000000680300600400600500700600600600601000680741600400410605600808000400608014600404400000600645004e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180008008868\n\t0200E0268C600602E80600680700600000210608640450620600610403001021442850201400C00000000602200000000000\n\t0000FF1C10800045801801901010020808801001001800000002600B00600408680480E00600600610E00000208600632410\n\t6106006000000008014000422004004000040804002000000000000000FF3D58800000001801811809840852001001601800\n\t000008700F00C006006006006006006006006001806056016444006006004000004010000000402004004000046006006000\n\t000000000000FF7A1F800801C01801805003800820003001001800000004700698480710680501700600600711600004692F00ce1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF43A300000000180100384402180080108B001800000010600200620E10600600640600410E00600000200608602C002006\n\t006016110008404400144104004000000006006000000000000000FF71C20000018018850438918308008110031018000000\n\t00600201624E00608614620600408E00600800610600602C4264660061060442440140500060040140000060060420000000\n\t00000000FFCA1E00000000180501504380282400B001001802002010600601400600622C0860061041460060800460060160\n\t0405640E14600A4841A4184080026084004000016006002000000000000000FF12DC80000010184382185000880080109109002e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A230C2002022\n\tB02A23221540422022AA2AA0002880022AE000000000000000FFDE070000018940000000098500000C200100000000000000\n\t0650820400020800000010000000000000600001001012010000801000408C00000013000400400002611000000000000000\n\t0000FF7E2D80008184004413400190214C00800180000000000000000401280000C00000000100000003200063402A000000\n\t00300C0000010000330320000006006000006440000000000000000000FF675C000001901141001900003041803801009802\n\t082000700200600404632E0160060040060060900020060064040C200E00600200030010408020400C00400000000600600000ae1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000557906D5\n\t7556556557D565565575575565085564864B65564063544460964D7556406500546556156800554556554000000000000000\n\tFFE16100002A82ACA80CC8AA8A29088508AA8AA80000012AA2AA0A24022AA0222AAAAA22A2AA2AA2802AA20220A2222220AA\n\t2AA220A2A2222022803022AA2AA0002AA2322A2000000000000000FF73DD0081000000000000010240010810000002000000\n\t0004280000010048000000000008000000000000080008000B00000882240000001000100100002000000040000000000000\n\t00000000FF1E2500012A90088D0008A20108009040AA8AB80000002AEAAA4021422AA5022AE2AE3242AA2AA0022AA01A0022006e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF49\n\t7800000000000000000004808C1000000000000000000C000008000000008000000008000000000400000100001101000004\n\t10000110108000000400000000000000050000000000000000FFC38F90802A8AA8AA8AA8A288286480482A8AA80000012AA0\n\t222AA2AB2A82AA2A92A82AA2AA2AA00028A04A0022AA202206222003A0220225200022A0AA0AA00028A2AA20200000000000\n\t0000FFBA25800800000201000001000025001000401400000100500080801100481100480400480400402000012014109000\n\tC40000008490001000400004800000100000410000C000000000000000FF6B59800055955955955955111911049955F5580000ee1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600081220001\n\t2002002010000002000000002000802000000000000000FF2F740000000000000000A0000000000002000000000002028022\n\t82A82A80A820000000000000000000022004840000002000000800000000000000000000000000000C800000000000000000\n\tFF251C0000002004000000020000000002800000000000000000800000000000000000000000000000080081000001000000\n\t000000001008800000000000000000800000000000000000000000FF60041000800000000000080000000540804000000001\n\t0000880000008000000008000000008003100003402A00000400300881201510400403081000004000000200000800000000001e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000002002002\n\t002003002000002002002000002002002802002000802802802802002000000002000000802802002000000000000000FFBF\n\t1F000001C01001801F05001801801801800000000000008700E88F08E08E20600000680680600000600502EA0420782400E0\n\t0C80600780400800000600000000400A006000000000000000FFB91C00000000100120104100000100110500000004000404\n\t04444444444044004000004004004000100544004804000804000C0481081000400000000400000000480400000000000000\n\t0000FFF783000000800C00800C00A00800800800800000020000000000000100000000000000200200200000200300200220009e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF87D400\n\t0001800400000001800000000000000000000000000000000000000100000000000000000080600100000080000000100080\n\t0001000000000000000000006000000000000000000000FF0EE8000000800801001800000800801801000000000000000600\n\t2006002002002000003003004000002006000002001000002002002802002000000004000000000002002000000000000000\n\tFF9ECF0000000010000004010000010000000000000000000000005000004004004000000000000000800000001004004004\n\t000804000000000000000000000000004004000000000000000002FFA979000000800A00200800A00800800A008000000000005e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (184826004002\n\t31A000000124040000086006006000000000000000FF2722000000000C01111800101801809C018000000008000006046506\n\t006016006000406007404300800A0200700214000400403080680600028A020004000010000006006000000000000000FF7D\n\tA2000001880801041800001001801801800000000800000608E04641600640600000600600404000014200E00A0020120020\n\t02102006204002000044400000100006006000000000000002FF2E7200000180000000000180000000000000000000000000\n\t000000000000000000000000000000000060000000000000000000000000000000000000000000000060000000000000000000de1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (068068060060\n\t0600600100600600600000080700700420200228600308490000200000000600000000040600E000000000000000FFDF7F00\n\t000000180182180008B801C1180180000000000001161562B62060160060804060060062200002A70A608442000180501310\n\t4000802488040006020010000006006000000000000000FF6B23000004000801089803800801C81801800000000000000600\n\t6006006006006000006386A04080216002006924082001006406004042086000000084200001006006006000000040000000\n\tFF6CC1000001C98807401805815C01901801800000000000111760701600E006206100006506004000406002F4E14C40080C003e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFCCE7000002\n\t001801001E01801A018018010000000000001806006006806807807800006106004000006000004004407804204004005882\n\t006000000006000000006406004000000000000000FFA638000001C01801801801800C018018018000000000000006006007\n\t007006006000006006006000816007006004002001004001006047006000000006000000006006006000000000000000FF68\n\tBE00000040180180180180180180180182000000000000060060060060060060000060060060010060060068840020000862\n\t0210600600600000000600000000600600E000000020000000FFD863000001A01A01A01800000A018018018400000000000800be1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020261070060\n\t00020006020000006006004000000000000000FFCBDF000001845A0100380180080180180100000000000800060060061460\n\t06046080086106086110406005804080087054004052006006806000000006000000006006004000000000000000FFE82000\n\t0000081A0121BA01804899845A01000000000008001620680600620600600002600680608020601D084C7004640000618200\n\t77470660000C0006040000007006004000000000000000FF12E3000001901811001901881901911C05000000000000000640\n\t6006006506016000846006204201006100124004007002006006024002006000100406000001006006004000000000000000007e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600600\n\t6000007006806000007806005006003501046002004802006000000006000000006006004000000000000002FFDFAE000080\n\t005801401901800C01805801800000000000000600700614610681600000600610600000610600D006302001004070804042\n\t006000080406000000006006004000000000000000FFA6370000018218010018018008018018018000000000000006006106\n\t08600600600000600600400000E00200000410348002510A02680600E000000006000000006006004000000000000008FF54\n\t64000000021809001801902C01929805800000000000000E00600600600602610008608620420800680204030C022252807000fe1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (81000401C018\n\t01801401800001C0100100000000000000060060060060060040000000060008000070060070060060068040000048000060\n\t00000000000000006006000000000000000002FFD776000000001C01A0100180000180100100000000000000060060860060\n\t07004000000006000000006006816006906806004000844000006000000000000000006806000000000000000002FFD0F200\n\t0281801B01A01001800001801601000000000000000600600610600600400000100600080000E006006006A060060060D000\n\t400101600010000000000180600600000000000000000AFF742C000001C41081001E01800801C01A0080000000000000060000011040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (280400600000\n\t0000000000006044000000000000000000FF7037000000001801801801C000A1809801020000000011028622400E00622612\n\tC50008000E00009088680700700E00610E007004C02024006000010000000000006004020000000000000000FF8FA6000001\n\t8018018010098200018010010000000000000006004406006006004000000006000000006206406006406006404004002004\n\t006000000000000000006004000000000000000000FFB1460000000018018010018000018010010000000000000006006006\n\t006006004000000006000000006006006006006006006000004000006000000000000000006006000000000000000000FF1100811040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (006006026000\n\t000006000000007807006802006002006000002000006008000000000001006004000000000000000000FF7C94000401A018\n\t01801001800001801001800000000008808600421600600648E28008000E00008908600620680A80788A2048012024230060\n\t00008800000000006804020000000000000000FF0CF9000000001E01801801A00841801E0101000000000400060040060060\n\t060240000000060000000060060060060060060048060020050A601000800000000000600C000000000000000000FF92AF00\n\t020180180181100982082180900100000000000002060040060062060240000000060000000060060060062068460060060000411040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (020000100100\n\t1001800001801001800000000000000600600600780600600000080600000000600600400400600680600380400000600000\n\t0000000000006004000000000000000000FF9DF5000000401801811800000901801801840000000000000644401600604600\n\t6000001006000000000407006004006042804000003202026000000000000000000044000000000000000000FF41DB000001\n\t8018018018000000018018018000000000000006004006006006206000000006000000000006006804006802006800003000\n\t08600000800000000000080C000000000000000000FF10AA000000001801801401800C21801001808000000004000600400E00c11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0E8000000000\n\t0000002860A0000000000000000000FF895D000005801001101A0001B8018E19458000000000200086006A06A06006316000\n\t200206480000180A061044421C6004482000004000406000000048000000000004000000000000000000FF416C0002282492\n\t012A1800204C01B21D518000000000400AA6A065062C6236A06000400836080000900246814202ACEA04C8D0A8A95012C060\n\t00000080000000800844000000000000000000FF1364000201803083003B45950B2980580180000000000000061160060060\n\t0610E200000206410000206917004146806016044202005322156000200808000000D06504000000000000000000FF87360000211040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (254004008008\n\t00808000A00804049380220058850D94C08B98A00000001000000000100810800000000000000002FFA8D200000080000000\n\t0C01080821800800000000000000012610200208600A00400000000200000000202200301600240202200004204400200020\n\t0080000000804202000000000000000002FF1A6C000001808180480001864480100000000000000000100108908002100008\n\t0000000000000000016409400025018A00208268280420010000000110000000806400000000000000000000FF0A01000001\n\t822000040025900100000098000000000000100020100000180000820000002820000000708000080040010010000001000000a11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (201201200011\n\t20320140044100000000000008048008040048040040008008048100008408048000CC800880A090AC80880C004000000088\n\t000000804800800000000000000000FFE5C5000001801801841A230210018C19138000000000000006006006806006316000\n\t0000062000000062060862AC2862AE00E0C402E2B4A36000000048000000084006000000000000000000FFBEBB000404C80C\n\t80D00800D14CC0C00C20800000000040010310210300210380220000100200000111200322280304B0034A32112030010020\n\t0000090000000000340A000000000000000002FFA7770002283012030224C22010482022210000000000400200000104800300611040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000005480000\n\t00550D50540000000000000000FF9EEB00040044040000000043440000060400000000000000000000010000008010000010\n\t01000001000000001001011001001021101041010001000000000001001000000000000000000002FFF63400002A0220880A\n\tA2A20982AA0AA0C80000000000000AA82A82A8AA8AA82A80002A82A8280000288A202A02000C8010080040280280A0000000\n\t02200000002882A82A0000000000000000FFC6A3000200B10A42A00800A20800C00802800000000100000080280000000000\n\t2000000802040000802112812802A22C53042C00842840152000000000000000842802008000000000000000FFF70800030000e11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (80002A82A82A\n\t8000288211A5020022AD501402800583180000000002A80000002882A82A8000000000000002FF8855000000052000000008\n\t0204000000000000000000000001001000000000000000000000100000001000808080088080100080140040048000000000\n\t000000800000008000000000000002FF698F00012A08A0AA0AA4AA0000AA0AA03000000000000002A82A82A82A82A82A8000\n\t2A82A82A80002A82A02802C82A00002103082002002A00000012A80000002A82A82A8000000000000000FF05B10003542803\n\t543545442821543545140000000000800D50550550D51551550000550D50450000D50550540C50C00C40C30C11410C90C80000111040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (019019550018\n\t01801801800000000000610600600600600600600000008600000240E00604C11620604610400604400E0040200100400000\n\t00006006000000000000000000FFEB9200028020520120001124840120120100000000000048048048040040048050000008\n\t048000008000C408480090004900D0310050A0CC4000800800000000844800000000000000000000FF215700000080080080\n\t0A008808008008D4800000000000000000000080000000000000000200000204201204A1520022822C000232000201200000\n\t0000000000002002000000000000000000FF37F000002A0A80AA4AA0A21020AA4AA10000000000000012A92A92A82A9AA92A00911040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080000000000\n\t6800000000000000000002FFC4D20000028111100008B6000851801801004000000000600200200200200600604000000200\n\t0000002102002082A0208211C10220A522500030018100000000004002000000000000000002FF06890001AC400401400409\n\t4004004004000000000001001095005005005001001000000000400000180004608060000000000200004048000001000020\n\t000001000000000000000000000002FF4D20000000C00C00C00C00C10D20C00C00800000000100B003003083003013003001\n\t001003000000003003003002003103011213413003002001001000000001003002000000000000000000FFB225000029801800511040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000006000012\n\t00800602400E00E1C4002710002018006020000000000000000004000000000000000000FFFECE0000018050010011400018\n\t2981180180000000000060060060060060561160000000060000000043060140060460141000020325003060000081000000\n\t00004004000000000000000000FF18A300000180400400214180000000000200000000000000000000000000282000000000\n\t00000010006400210000020030000010148040008000000000000000006000088000000000000000FF877300000180000008\n\t00018080C00000000000000000008010000080000008000000800900C000004168008208080008409008108208008000000000d11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (B810001C01A5\n\t1A05000000000000600610E00600600601600000000600000000400601620E00610220A00408040600000000000000000004\n\t510C000000000000000000FFD66B0000000450210808018C3001881801800000000000600600600600600600600000000600\n\t00020460061040C40AE04404004A0120B4002000000000000000006004000000000000000000FFFD22000001811155005815\n\t8018018018018020000000006006006006006006406000000006000000012006444015016004010000102024012028000000\n\t000000002004110000000000000000FFA0BF000000181021001800001801809805800000000000600601E00600600608E04000311040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000552554\n\t000000000000000000FF8EF400012B8AB88B8808AB8830AB8B18A800000000000072AF2372AF2AF2AF2AE0000002AE000000\n\t28F2AE22F02602E22312132D2A92022AC0000010000000012CE226000000000000000000FFD3A8000080201E01800A01A210\n\t01801801000000000000780780780780780780600000000600000004300600708F3070830418970100120040000000000000\n\t01802006000000000000000000FFE2C60000AB8898898018A20098AB8038AD00000000000062AE2262AE2AE2AE2A60000002\n\tAE8000002C8AAE226D16E06A1AC80286A201162A8000000000000000288234000000000000000000FF35B2000000001803A200b11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (068000020068\n\t0600280C0960128C4094906802006000000000000000006004000000000000000004FFAB190000AA2ABAAB8ABEA3801CAB8A\n\tB8AB0000000000006AAEAAEAAEAAEAAEAAE0000002AE0000002AA2AE2AA204A462A2104A262262222AE000000000000000A8\n\tB2AC000000000000000004FF3E82000001C01C21C2AA01831201C05C01000000000100600610600600600600680000000700\n\t0000006006102005106102014006006046006000000000000000006104000000000000000000FF4C9A000054555955D55955\n\tB15955D55D55000000000000655655655655655655600000055700000051255655244400E45241644454654655600000000000711040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (925001801803\n\t000000000000600600600600600600600000000600000002200600600614601440002401200400E000000000000000022148\n\t000000000000000000FFC3D00000018218018008018090018018410000000000006006006006006006006000000006000000\n\t00600610E09240E10402A48C082088106000000000000000006000000000000000000000FF8CF2000000001801A008119414\n\t01A01A0100000000008060060060060060060070000000060000020020060060C204600421000600A0880060000008000000\n\t00042000000000000000000000FFDF440000018018018008018150018018010000000000006006006006006006006000000000f11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002CC2A60000\n\t00000000000000FF152A00005413095180195581515595591580000000005505565565565565565560060005560060005105\n\t505464B25364460101125404525460000060060000005504C6000000000000000000FF72EE00000180000182380180100180\n\t1809800000000000000600600600600600600600000600600000400000600204600611001000200204E00000600600000000\n\t4016000000000000000000FFAE730000AB88B88D8AA8A38410AB8AB88900000000002AE2AE2AE2AE2AE2AE2AE0000002AE00\n\t000028E2AE2262260062240C000622232423600000000000000028E210000000000000000000FF9CA600000000184580080900091040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200000400000\n\tE142146006012010002102084000006006000000044016000000000000000000FF177600002B8AA8AB9018A38AB0AB8AB901\n\t80000000002A82AE2AE2AE2AE2AE2AE0060002AE00200028C2A82363520062362A232632834A30400000600600000028C226\n\t000000000000000000FF884A0001000028018AB8019010018018218000000000000006006006006006006006000006004000\n\t02000000E00600608E30022000A002004000006006000000000006000000000000000000FF1CBA0000AB8AA8AB8098AB8AB0\n\tAB8AB82380000000002A82AE2AE2AE2AE2AE2AE0060002AE0060002AC2A82A620628E326220222230212206000006006000000891040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (01C018018000\n\t0000000010068070070070070060070008060020100040000061500060045820A24100020060000060060000000050060000\n\t00000000000000FFF3438000C0000801901801801C0180180180000000000010060070078070060060060010060020000050\n\t0000700600610E002146004002004000206006000000004806000000000000000000FFD5CF00000180080180180980100180\n\t1851800000000000000680600600600600600600080600000004400010600E40E09600210010602203400000600600000000\n\t4086000000000000000000FF9D8E000100000801B33801801A01A0190580000000000010060068060070068060070000060000491040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (420600000000\n\t0000000000FFCB5F0000000058018018820098018018018000000000000C0602720700610603600600000640200008400000\n\t6000556102092102014200024040006006000000004006000000000000000000FFDA5F000141803809901804001A01801801\n\t00000000000200062060060068060062060008060020080048000070A8006310202010206023006000006006000000404006\n\t000000000000000000FF2C040000040018018019458010018018018000000000040006286006006006006406000006000000\n\t004000106000046406002008102043004000086006000000404006000000000000000000FFE888000001805811C01881801400c91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00410000600C\n\t15614611400009208E000020006004000000004016000000000000000000FFE4250000000008400219000118058018018000\n\t0000080000060463060060860460060000060064000040000160042060040040060000061101000060040000080040060000\n\t00000000000000FF73F9000001880808021815801801801801800000000000000600608600600601600E0000064062001040\n\t8000E00A00602200410608048E04000000600400000800440E000000000000000000FF4A8B00000400082000184980100382\n\t180180000000080000061060060A60062860060000060040000040001060000460020040001120060880805060040000000000291040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A90080000000\n\t000002AA2AE2AE2AE2AE2AA2AE0002AA4020002AA0002AA5020020002220864160261220002AA2240000002AA2AA00000000\n\t0000000000FFE3F6000001912002000009900000000141000000000000000000000000000000000000000011000000400000\n\t0210100100100240088400100000000010000000004000000000000000000000FF0E85000001820000000001812000000014\n\t00000000000000000000000000000000000000004200000060000000C0448428010010240090208000000100000000006000\n\t000000000000000000FF7F8A000001904810001800001801841801800000000000040600600614600650601600000600600000a91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFB905000155931113D55955155B55D559558000000000001D5755655655755755655600155654C00055600055640E\n\t5565144D424444454C546001556556000000157552000000000000000000FF4DC200002A80888A8AA8AA8088AACAA84A8000\n\t0000080002AA2AB2AA2AAAAAAAA2AA0012AA0320002AA0002AA0222AA22A23204A04220A20A0002AA2AA0000002AA2AA0000\n\t00000000000000FFE58B00000000202100100000000100100000000000010000048000008000000040000000000040000010\n\t00000020000024004088088000000000000000000000200004000000000000000000FF513E0001AA9458A80AA8A30648AA8A00691040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001204480\n\t880100200A0088010001000000000000200800000000000000000000FF50E400000004000000000000020000000000000000\n\t0000080000000000000000100000000010000000000100000810004000048801000010000000000000000000000000000000\n\t0000000000FFA5E800002A88A0888AA0A28AACAA8AACAA80000000080002A82A92A92A82A82A92A80002AA2220000AA0012A\n\tA3020022022A00002002202320002AA2AA0000000AA2A8000000000000000000FF332B000000001021001001100201201000\n\t000000000900100500500500480480400400100410400000080000401000010410430410414404000000400400000000000400e91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0800000000000000000000000002002000002802002802082002510882802043020000002002000000000000000000000000\n\t000000FFD42C0000000000000000000000000000000000000000000000000209A20000000000000000000000220A90000800\n\t000000000000000800800000000000000000000204000000000000000000FF0F7F0000000000020000000000000000000000\n\t0000000000000000000000000000000000000000000000008000010008000000000000000000000000000000000000000000\n\t00000008000000FF32020000800000224000080000002004000000000000000001000800801001000000001000010000200000191040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFDCBC00000080080080000080080000000000000000000000000000020020000000000000020020018020030020028020\n\t02000002000002002000003002000000000002000000000000000000FF453000000180180580000100180000000000000000\n\t0000000000000E006000000000000006006000224A0D00600608600728D00780600602400000600600000000000200000000\n\t0000000000FF218E000000001001000001001000000000000000000000100000040444400000000000000400000080410400\n\t4000805004804100004840004000004004000000000404000000000010000000FFE16800000080080080000080080000000000991040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000002FF098F000001800000000001800000000000000000000000\n\t0000000000000000000000000000004000800801000000000000001000000000800000000000000000000000000000000000\n\t000002FF46920000008010000000010018000000000000000000000000000002002000000000000002002000006004006002\n\t806002004002804002006000002006000000000002000000000000000000FF4F440000000006010000000000000000000000\n\t000000000000000004004000000000000000000000000000000000000001800800000000800000001000000000000004000000591040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000600600000000000000640600002600404E0060261060044040020060060000060060000000000060000000000000000\n\t00FF396500020000100100040040180A00000000000000000400000001460060000000000000461064000064474064064172\n\t474A4944911456D14200007006000000000006000000000000000000FFFA6F00000180100101204000180000000000000000\n\t0000000000000600600000000000000600400004400601600402601600601422000400410010600600000000000600000000\n\t0000000000FF824A00000180000000000180000000000000000000000000000000000000000000000000000000000000000000d91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t9197000201801801800000001804000000000000000000000000000600600000000000100600400000200100600600600600\n\t2014006805002000006006000000000006000000000000000002FFE154000000001A0180C600409814000000000000000004\n\t0000000007006000000000000006106401002C4002640600F04630188C256407312000087006000000000006000000000000\n\t000000FF5ED200000040102100000982188000002000000000000000000000A7006000000000000026206001007804A06003\n\tA0628E82422408202C006280006006000000000006000000000000000000FFD9AD000001981041000031851900000040000000391040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (026106112217\n\t0A4004102000006006000000000006010000000000000000FFB66A0000002018018000018018000000000000000000000000\n\t00000600600000000000000600600080200000600600600600000F0040060020000060078000000000060000000000000000\n\t00FF7902000001C0180180040180180000000000000000000000000000060060000000000010060060010020030060060060\n\t07000004005006E00000006006000000000006000000000000000000FF2C2B00000000180180000180180200000000000000\n\t000000000000060060000000000000060060000000020060060060070008050050040000000060060000000000060000000000b91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0600600000000000000600600142640604E00E0462A62B3404B4120C000000006006000000000006008000000000000000FF\n\tD649000001805801800101801800000000000000000000000000800600600800000000000600600044240000601600600604\n\t080600C21600000000600600000000000E000000000000000000FF5ABC000400001807880401901810000080000000000000\n\t0078000206006000000000000106074000002000206207007447C0014E404004080000006006000000000006000000000000\n\t000000FF2779000001D01A01904011841800000100000000000000000008050610600000020000000600600000080045640600791040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF0295\n\t0000098018018000018018000000000000000000000000000006006000000000000006004001004007006006006006000005\n\t800205002000006006040000000006000000000000000000FFBAF00000001018818040118018000000000000000000000000\n\t1109061060100004000001060160002060060060060060070009440110060020000060060000000000160000000000000000\n\t00FF993000000180180180000180180000000000000008000000000000060060000000000000060060010060060060060060\n\t06000004000006000000006006020000000006000000000000000000FFBBB00000000038018001018A18080000000000000000f91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (040000000000\n\t04000000006000000000006006000000000000000000FF3F6B00020180180180040180000000000000000000000000000000\n\t00000000000000000006006001004007006006006003004802000001000000006000000000006006000000000000000000FF\n\tA82D000000001C01800001800000000000000000080000000000100000000000000000000600600000680600600680680200\n\t4002800000000000006000000000006806000000000000000000FF64D6000011801301800001800000000000000000000000\n\t000000000000000000000000000600600040680600600600600400000000020400000000600000000000680600000000000000051040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000006006000000004006086816064000004806004002000006000000000006006000000000000000002FF14A0\n\t00000000180180A0018020000000200000000080000000020000000000000200200006006000803214406006006004000C24\n\t016804002000006000020000006006000000000000000002FF8FAE0000018018018000018000000000000000000000000000\n\t0000000000000000000200060060000020840060860060020040060060000020000060000000000060060000000000000000\n\t00FF37960000000018018000018000000000000000000000000000000000000000000000000006006000004006006006006000851040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20FF7EA20000\n\t0000180180000180000000000000000000000000000000000000000000000018060060008020040060060044140008200068\n\t44002400006000000020006006000000000000000000FFDF7D00000180180180000180000000000000000000800000000000\n\t0000000000000000000600600000280C206006004002004A2280E800002000446000020000006406000000000010000040FF\n\t7CE9000000001801800001800000000000000000000000000000000000000000000000100600600000000400600600641200\n\t404600604000240008E008000040006006000000000000000000FFF43C00000180180180800180200000002000000000000000451040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (601310040200\n\t4000006000000000006106000000000000000000FF115C000000200801000201800000000000000000000000000000000000\n\t0000000000000006006000004007806807806804002000000006004000006000000000006006000000000000000000FFE7E9\n\t0000004018018044000000000000000000000000000000040000000000000400440006006000002504007006014002004002\n\t806000002000006800000000006006000000000008000000FF6BF40000018018018000000000000000000000000000000000\n\t0000000000000000000000060060000020040060060048050008000068040020002AF008000000006206000000000000000000c51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000008000008000000000200080041800200060000000000000000000000000000000000000000000FFABB70000\n\t018E282104220208000000000000000000000000000001000100000000000000A60060000040062060060060040020000102\n\t06004000006000080000006026000000000000000000FFCD390002102C0A2110000810000000000000000000000000000002\n\t00200000000000000906886000B2C826C26886D268228AE482A4884B12C000A8E0C808800080E846000000000000000000FF\n\t8A5D0000018128810021438000000000000000000000000000000000000000000000010826036000005C0610E0370161128000251040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (944000020020\n\t12000004D50000000000000000000000000000000001200000000000008800810000A00A04838910978920000D0880080C82\n\t0000A00820008000008884000000000040000002FF6A9B000000800801000000000000000000000000000000000000020000\n\t000000000000000200200044442000608300440280C08608300000E00008A008000000006002000000000000000002FF342B\n\t000049808080080009A0000000000000000000000000000010000000000000000000000A00001A000008002808001CDB0250\n\t4684004C0000000080000000000000000000000000000002FFA507000001800000000021800000000000000000000000000000a51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A2A42040000\n\t802800000000002000000000000800000000FF04E50002002052010000012000000000000000000000000000000000000000\n\t000000000804AA4000894904804A84804800C4C80500080D094000804800000000004804000000000000000000FF7B020000\n\t41841001840021000000000000000000000000000000000000000000000000000600E00022420600E08E02E00640600C24E0\n\t06224000006000000000006002000000000040000000FF9A72000400C00C0080061480000000000000000000000000000009\n\t00810000000000001003002001083003003002103512130523002441002001002000000001003002000000000000000000FF00651040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (505500000000\n\t00800D50C40000B10440D50420550D50050CC0D21028510000D50D50000000000550000000000800000000FFC36300040000\n\t0400000600000000000000000000000000000000000180000000000100100100000100010100110180100110000100100010\n\t0001001001000001000000000000000000000000FF405900002A0880880000A20AA00000000000000000000000000002A82A\n\t80000000000002A80080000002102A80082A82A80802302084802000002A82A80000000002A8000000000000000000FFCDED\n\t000300A20A44A000108000000000000000000000000000000000000000000000800802802000C4204A80204200280280288800e51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00002A0AA0AA\n\t0000A20AA00000000000000000000000000012A82A80000000000002A82A80002202202A80602A82A8221AA82202A8220000\n\t2A82A80000000002A8000000000000000000FFC16C0000000000004004100000000000000000000000000000000001000000\n\t000000000000108000040080000091000000A80000008100040000000000000000000000000000000000000000FFBFBD0000\n\tAA0AA0AA0000AA0AA00000000000000000000000000002A82A80000000000002A82A80002B02282A82082A82A82302A82A82\n\tA82280002A82A80000000002A8000000000000000000FFD7DE0003543343520001441540000000000000000000000000000500151040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030000010030\n\t03000001001000000000000002000000FF3F4700000980180180180180000000000000000000000000000000000060000000\n\t0040600608601000440810600000400600E046006204000000006006000000000000000000000006000002FF167400030000\n\t1201001211000000000000000000000000000000080000400000000080480480400080400080481080480088400108880408\n\t8000804804800000800000000000000000000002FFCDB0000000800800800000800000000000000000000000000000000080\n\t0000000000002002002000112110002500000002012002002000000000002002000000000000000000000002000000FF88BF00951040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000A0\n\t0800800008800A00800800B20A00840800888800800000800800800000800800000000000000000000FF4B7D000000800010\n\t001800010000040000000000000000000000000000200004000000200200200001250801608000608201C022402006000010\n\t002006000000000000000000000002000000FF0AB00001E84014014005014000000000000000000000000000001001004000\n\t000000000000080000004000080100540160040280110260000000000000000000000000000000000000000000FFE7540000\n\t00C00C00C00C00C080000000000000000000000000001001002000000001003003002001003001003001003403001283003000551040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (011010210038\n\t0000200000000000000000000000000000000060100000000060060061200060000060004060160800340220000000000060\n\t06000018000000000000000006000000FFE0C700000080110108580100C00002000000000000000000000280000960000202\n\t00006006006000004200006000006086410204042542020000016006000000000000000000000006000002FF355700000190\n\t01000A000180000000000000000000000000000500001100100002000000000001000000000000002001104004100882A044\n\t0000010000000000000000000000000000000000FF863C00000180000000010181000000000000000000000000000000000000d51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00002AE00600\n\t00002A82A8000000000006000000FF43DB000001151A05801811000000000000000000000000000000000000600000000000\n\t6006006000002108006000090406014132004014110000006006000000000000000000000006000000FF6D05000080001021\n\t001801800000000000000000000000000000000000600000000000600600600014C00000600000608E084400110082000000\n\t006006000000000000000000000006000000FF15D50000018010510418008000000000000000000000000000000000006000\n\t00000000600600602001610000E000006006084020510000400008006006000000000000000000000006000000FF9191000000351040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006556\n\t556000CD2D505565505504063464CA54CB144C8000557007000000550550000000000006000000FF202700012B80DC898018\n\tAB80000000000000000000000000000008008060000000000062AE2AE000A02AA0AAE2A8A20316A2108F22EA20A200002AE0\n\t060000002A82A8000000000006000000FFED73000100201C0180180080000000000000000000000000000008008060000000\n\t00006006006000002000006000000136008007006822000000006806800000001800000000000006000000FFAC1100002A84\n\t3889801AA200000000000000000000000000000000000060000000000062AE2AE000A52A202AE2A8230066224402A243362200b51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180180180\n\t00000000000000000000000000000000006000000000006006006000802800806000800406C0208E90641080800000600600\n\t0000000000000000000006000000FFD4CD0000AA2898ABA01AA2A00000000000000000000000000000080080600000000000\n\t62AE2AE0002A22A82AE2A82A802600222622E8222200002AE806000000AA82A8000000000006000002FFBD68000001D01845\n\tC01C01A000000000000000000000000000000000006000000000006006006000082008006000100006116022104006110000\n\t007006000001000000000000000006000000FFCE3E000054555955801B54800000000000000000000000000000080080600000751040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AE2AE000000\n\t000000000000000224000002FF7FBB0000000058038018088000000000000000000000000000000000006000000000006006\n\t00600049600000600001211400C110010100000000006006000000000000000000000004000000FF9A0E0000818218018018\n\t0180000000000000000000000000000000000060000000000060060060000260000060001020040800040824000000000060\n\t06000000000000000000000114000002FF4079000000045A0180181080000000000000000000000000000000000060000000\n\t0000600600600000E00000600000208C0C8804002102080000006006000000000000000000000004000000FFE50F0000018000f51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (002AE2AE2AE0\n\t002A40002AE0062282AC2902802282000000002AE2AE0060000060000000000002A8000020FF14FE00005413411195415400\n\t0000000000000000000000000000000655600000000055655655600001600055200654C54C5504D650008600000055655600\n\t6000006000000000000540000000FF32D1000001000001800009000000000000000000000000000000000600600000000000\n\t6006006000016000006006004004004012080156000000006006006000006000000000000000000000FF938A00002B8898ED\n\t8AB8A380000000000000000000000000000000002AE0000000002AE2AE2AE0000460002AE00022222422422027006A000000000d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800009400000\n\t00000000000000000000000010070060000000000060070060001020008020069160060A6010104044000000006806006000\n\t006800000000000000000000FFDF3C0001AB0AA0AB8AA0A300000000000000000000000000000000062AE0000000002AE2AE\n\t2AE0002220002AA0063262AE2422602242040000002AE2AE0060000060000000000002A8000020FFE6C60001000000018000\n\t0000000000000000000000000000000000060060000000000060060060002840000020060040040040000002100000000060\n\t06006000006000000000000008000000FFF36300002B0AA0AB8AA0A300000000000000000000000000000000062AE0000000008d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060060010060\n\t00000000000000000002FF5A3900002100000108000140000000000000000000000000000010070060000000000068068062\n\t00002021006007004A0600200008C00400000081E806006000007000000000000000000000FF16A900004100400180000100\n\t0000000000000000000000000000000600600000000000700604620000002000200601531214204651410600000100600600\n\t6000007000000000000000000000FFE325000001000001800001000000000000000000000000000000000600600000000000\n\t700600600001000000200600080600E08201410E000000806006006000006000000000000000000000FFECED000001000001004d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (600600600000\n\t40A80040260163041AC00200A026000200006006006000006000000000000000000000FFC393000001000109000001000000\n\t000000000000000000000004000608604001000000600680600000240080200600600620222E004086050000916026006000\n\t806100000000000000000002FFD81C0000010020010000010000000000000000000000000000000006006000000000006816\n\t12600000200000601600680E04614240430E000000006006006000006800000000000000000002FFB1790000010000011000\n\t010000000000000000000000000000000006006000000000006017106000002001007816000006006100004214000000006000cd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010040000040\n\t0000000000000000000000060060200000000060060060001142000000A60042040AC4400821042082000060460060001160\n\t00000000000000000000FFC15100000100000180000100800000000000000000000000000200060260000080000060060260\n\t0000400000020600800440008022201412000000600610E100006000000000000000000002FF4E9C00000100011180000100\n\t8000000000000000000000000000000612600000000000600602600008C15000428600A19C0000962B204E28000011600608\n\tE08008E100000000000000000002FF83E6000001000001800001002000002000000000000000000000000600600000000000002d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000000000\n\t0000000000000000FFCB790000AA8000E90000AA80000000000000000000000000000002AE2AE0000000002AA2AA2AA00021\n\t00003262AA2042223222063A02020000002AA2AA2AA0002AE000000000000000000040FF9380000001000002000001000000\n\t0000000000000000000000000000000000000000000000000000120000110000020010110010008110000000000000000000\n\t000000000000000000000022FF4D780000018000000000018000000000000000000000000000000000000000000000000000\n\t000000008000000000088080000120000020000000000000000000000000000000000000000002FF7496000001000001800000ad1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004000004000\n\t81400400400000000C004010000001005004004000004000000000000000000000FFA0840000D58001558001558000000000\n\t000000000000000000000556556000000000556557D560005540004355564540160C62045465560000005575575560005560\n\t00000000000000000000FF8D930000AA8000888000AA80000000000000000000000000000002AB2AA000000000AAA2AA2AA0\n\t00322000A222AA2AA2AA22A2A22283220000002AA2AA2AA0002AA000000000000000000000FFB25700000000000040000000\n\t000000000000000000000000000000000000000000000008000000000040000800000802A020808800400000000100080400006d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000008010008000001080002A800042802000050800010800000000000080000080000000\n\t0000000000000002FFF2D2000080000000000000000000000000000000000000000000100100000000000000000000000000\n\t0000000800000410440000088020000001000800000000000000000000000000000000FF376B00002A8000AA80002A800000\n\t00000000000000000000000012A92A80000000012AB2AA2AA0002220000022AA08208208A0602322020000012AA2AA2AA001\n\t2AA000000000000000000000FF850D000000000003400000000000000000000000000000000000000480400000000080500500ed1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF8A3A0000000000000000000200000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF34FE0000200000200000000000200000\n\t0000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF281C00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000008000000000FF69A900000000000000010000001d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000008\n\t00000000000000000000000000000000800000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF96D8000020000020000000020020000000000000080000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000008000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFF8900000000000000000000002000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFAE5A0000000000000000000000002000\n\t0000000000000000000000000000000000000000000000000000000008000000000000000000000000000000008000000000\n\t00000000000000000000FF165100000000000000000000020020000000000000000000000000000000000000000000000000005d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FFE52100000000020000000000000000000000000000000000000000000000000000000000000000000401000000\n\t00000000400410050400000000000000000000000000000000000028000000FF35EB00000000000000000000000000000000\n\t0000000000000000000000001000000000000010000000004000000000000101010040000000000000802000000010000000\n\t0000000000000000FF8218000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000100000000000000000000000000000000100000000000000000000000050000000FF409B00000000000000000000000000dd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF80E2000000000200000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFD29F0000000000000000000000000000000000000000000000000000000010000000000000080000000040\n\t080000000000000100400000000000000080000000100000000000000000000000FFA6300000000000000000000000000000\n\t000000000000000000000000000000000000000000000000020080000000000000A082080282000000000080200000000000003d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000080000000000000200800000000001000000000200000000001100000800000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000bd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFE986000000000000000000000020000000000000000000000000000000000000000000000000000000000000002008\n\t0000000000000000000000000000000000000000000000000000000020FFDDB6000000000000000000000040000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000\n\t000000000020FF9D780000000000000000400000000000000000000000000000000000000000000000000000000000080000\n\t010000100000060088000000000000400000000008100000000000000000000000FF6EDF0000000000000000000000000000007d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000800\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF008D00000000000000004000000000000000000000000000000100000000000000401000000000000000000100\n\t00000000000000000100000000400000000000100000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF241F000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000\n\t000000000000FF241F000000000000000000000000000000000000000000000000000000000000000000000000000000000000031040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008028000000\n\tFF21BA0000020000200000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000008000000000000000000FF617B0000020000000000000000000000000000000000\n\t0000000000000000000000000000000080002000000000000200004000000000000800000000000000000000080000000000\n\t00000000FF209C00000000002000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000831040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000001000000000000000000010020008000000000FF223F00000000000000000000000000000000000000200000\n\t0800000000001000000800000000000000000000000000008000000000002800002000000000000800000800000000000000\n\t0000FF1910000000000000000000000000000000000000000000000000000000000000001000000000000000000000000002\n\t0000200000000000080000000000000000000000000000000000000000FFB8EB000000000000000000000000000000000000\n\t004000001000000000001000000000000000040000000000000000010000800000005000004000000000001000000801004000431040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000008\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF68DC0000000000000000000000000000000000000000\n\t0000000000000000000000000000000100004000000000000000000080000000000000008000000000000000000000000000\n\t28000000FFE4430000000000000000000000000000000000000000000000000000000000000000000000000400000000000000c31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF10\n\t8200000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000\n\t00008000000000000000000000000000000000010000000000FF164000000200000000000000000000000004000000000000\n\t0000000000000000000000000000000001000000800000000040000000000000000000000000000000000000000000006000\n\t0008FF2868000084000020000000000024000000000000000000000000000000000000000000000000000000000000000000\n\t00000000002880000000000000000000000000000000000004C0000000FF4B6F00000000000000000000000000000000000000231040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (005044000000\n\t0000000000000000000000000000000000010000000000FF74D7000080000020000000000000000000000000000000000000\n\t0000000000000000000000000000000000100000000010000000280000000000000000000000000000000000000000000000\n\tFFF9960000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040\n\t000000000000000000000000000000000000000000000080000000FFC2CD0000000000000000000000600000000000000000\n\t000000000000000000000000000000000000400000000400000000040000050000000000000000000000000000000000000200a31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF3DA700000000000000000000002000000004000000000000\n\t0000000000000000000000000000000020000000000000000000000004800000000000000000000000000000000000004000\n\t0000FFDC0D00000000000000000000000000000000000000000000000000000000000000000000000000000080001004000000631040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF9C8600\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF9C86000000000000000000000000000000000000000000e31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000131040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000001000000000080001001000009000000000000000000000000000000200001001000000000FF59E900\n\t0000000000000000040000000000000000000000000000000000000000000000000000020001000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000931040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFE807000010\n\t0000000000000200000000000000000000000000000000000000000000000000000000800000000100000800800008800000\n\t000000000000000000000000400000800800000000FF99A90004000004000000000004000000000000000000000000000000\n\t000000000000000000000200008000900000000000800000C00000000000000000000000400000000000800800000040FF80\n\t6A00000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFBC500000080004000000000000000000000000000000000000531040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010000000000\n\t00000400000000200000000001041000000020FF786D00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000008000020000400000000000000000000000000000000000000000000FF5A1C00\n\t0000000000000000000040000000000000000000000000000000000000000000000000000000000008002000800000004020\n\t0080020020000008400000000000080000000010000000FFE03C000000000000000000000040000000000000000000000000\n\t000000000000000000000000000000000000004001000001040000030002004000020840000000000010000004001000000000d31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000680000000000000000400000000000000000000000000000000000420200000000FF7331000000\n\t0002000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000040000\n\t000000000000000000000000000000000040000000FF08B90000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000040000000000300000280000000000000000000000000000000000280100000000FF04\n\tBE0004000004000000000004000000000000000000000000000000000000000000000000000000000001000000000009010200331040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFAB3700000000040000000000040000000000000000000000000000000000\n\t000000000000000000000000000200000000000000000A00000000000000000000000000000000000004A0000000FF806A00\n\t0000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFA99B00000000000000000000000000000000000000000000000000b31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFED83000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000004000000000004000004000\n\t000000004000000000000000000000000000000004FF18DC0002000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000800000000004C00000000000000000000000000000000000000000A0000000000FF4000731040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000200000080000000000200000200000000000000000000000000000FFACC00000080000\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000\n\t00000000020000000000000000000000000000FF380A00008000000000000000009000000000000000000000000000000000\n\t00000000000000000000000000280000000000000000200000000000000000000000000000000000000000000200FFF8EB00\n\t040000020000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000f31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000A000000000000024020000020000000000000\n\t00000000000000000000000802C0000000FF6A1F000108000000000000000110000000001000001000000000000000000000\n\t0000000000000000004000400000000004100000004000000000000000020000000000000000000000000400FFA56C000000\n\t00000000000000000000000000000000000000000000000000000000000000000000004000000000000000800C0000080000\n\t000000000000000000000000000000200000000000FFFC130000000001180000000000000000000000000000000000000000000b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000A0100000000FF96830000000000000000000000000000000000000000000000000000000000000000\n\t000000000000040000000000000000000000400000000000000000000000000000000000000400000000FFCB8E0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000400000000\n\t00000000000000000000000000240020000000FF3E9100000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000080000000000400000280000000000200000400000000000000000000000000000FFFF1700008b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000100000000100000000000000000000000000000000000010000000000000000FF9A8800000000000000\n\t0000002000000000000000000000000000000000000000000000008000000000000000008000002008000000000000000000\n\t0000000000000000008000000000000000FF22B3000000000000000000002000000000000000000000000000000000000000\n\t0000000100000000000000400000000020000000000000000000000000000000000000000000000000000001FFE529000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000800000000000004A05200000A0000004b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0020000000000000000000000000000000000000000000000000000000000000000020000020000000000080000008000000\n\t000000000000000000000000000000FF093C0000000000000000000000000000000000000000000000000000000000000008\n\t000000000000000000000000000000010008000000200000000020000000000000000000000000000010FF3FDA0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000\n\t00000000000000000000000000000000000000FF43CF0000000000000000000000000000000000000000000000000000000000cb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF3D7D00000000000000000000200000000000000000000000000000000000000000000000\n\t00000000000000000020000020000000000100000008000000000000000000000000040000000008FF882000000000800000\n\t2000000000000000000000000000000000000000000000000800000000000000000000008000000000805000042840008000\n\t0020000000000000080000000020000000FF2B73000000008000002000000000000000000000000000000000000000000000\n\t0000000000000000000000000080000000000020000228000080000000000000000000080000038020000000FF0680000000002b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000100000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ab1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFB4BF00000000008000000000000000000010000008000000000000000000000000000000\n\t00000000200000000000000400000000500000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF8003000000000000000000000000000000000000000000000000000000000000006b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008000000008\n\t0000000080000000080000FFBFD8000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000200000000300000000000000000000000000000000000000000000000FF1A11000000000080000000\n\t0000000000001000000800000000000000000000000000000000000000200000000000000080000000000000000000000000\n\t000000000000000000000000000000FF54450000000000180000000000000000000000000000000000000000000000000000\n\t000000000000080000000000000100000000000000000000000000000000000000000000000000000000FF409B000000000000eb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF4CFE0000004000000004000000\n\t0040000000041004000010000000010000000010000000010000000010000000010000000010000000010000000010000000\n\t01000000001000000001000000FF706A00000000000000000000000000000000000004000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFE75600000002000000\n\t0020000000020000000020000000008000000008000000008000000008000000008000000008000000008000000008000000001b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010000000010\n\t0000000100000000040000000040000000040000000040000000040000000040000000040000000040000000040000000040\n\t0000000400000000400000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF9D2F000000008000000008\n\t0000000080000004180000000020000000020000000020000000020000000020000000020000000020000000020000000020\n\t000000020000000020000000020000FF247C0000000000000000000000000000000006100000000000000000000000000000009b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001001001000\n\t000000000000000000FF81D90000000000000000000000000000000004000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF989A2000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF8A9000000000000000000000000000000000002000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF7EFF00000010000000005b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000010000000\n\t00000000000000000000000000001000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFE8E1400400400400400400\n\t400400400400400000000100100100100100100000000100100100100100000100100100100100100100100100100100100100db1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF4BA34004004004004004004004\n\t0040040040040000010010010010010010010010010010010010010010010010010010010010010010010010010010010010\n\t01001000000000000000000000FF7BDD40000000000000000000000000000040000000000000000000000000000000000000003b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF6D0000000000000000000000000000000000000000000000000000000000000000000000000000000010\n\t01001001001001001000000000000000000000000000000000000000000000000000FF4BA340040040040040040040040040\n\t0400400400000100100100100100100100100100100100100100100100100100100100100100100100100100100100100100\n\t1000000000000000000000FF4BA3400400400400400400400400400400400400000100100100100100100100100100100100\n\t1001001001001001001001001001001001001001001001001001001000000000000000000000FF409B00000000000000000000bb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000100100100\n\t1001001001001001001001000001001001000001001000000001001000000000FF0B88000400400400400400400400400400\n\t0000000001001001001001001001001000000000000000000000000000000000000000000000000001000000000001000000\n\t000000000000000000FF87A25004004004004004004004004004004004000001001001001001001001001001001001001001\n\t001001001001001001001001001001001001001001001001001000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C0800000004\n\t0000000000000000000000000000000000000000015010000100000015015012015100000000000002000000000000000000\n\t01501501000000FFDB9240040040040040040040040040040040040000010010010010010010010010010010010010010010\n\t01001001001001001001001001001001001001001001001001000000000000000000FFA85400000000000000000000000000\n\t0000000000000000000000000000000000000000000000000100100100100100100100100100100100000100100100100100\n\t1001000000000000000000FF41A200000000000000000000000000000000000000000000000000000000000000010010010000fb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000003140\n\t1400000008FF742E00000810E2080001000000081000000003080000000400000000400000000400000000400001A00C1002\n\t0000401A01820411A20000400000000430000000400000000421821820410000FFBFE10000101A4190000000000010180000\n\t00002000000000000000000000000000000000000000000000900A00000800000A00900A0000000000000010000000000000\n\t0000800A00A0690000FF78362000101C40100000000000101C00000000000000000000000000000000000000000000000000\n\t4000100C0000000400CD02104C0000000000000210000000000000000000CC0CC0410000FF05BB00000C080348000000000000071040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D01080004001\n\t040D00C05040D04001000000001000000001000000001080C04C05080000FF99170000020904000000000000020800000000\n\t100000000000000000000000000000000000000000000000014000040000019A400140000000000082000000000000000000\n\t00004001A00000FFE58E00000601810600000800000600800000021800000000200000000200000000200000000200004008\n\t20068000060400469060468000020000008020008000020000000020460461020008FF0DC600002000C22200000000002000\n\t000000020C00000000000000000000000000000000000000014008000080000014014000014080000000000000300080000000871040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000800B4D001800000000006F11110000000000000143FFFFFFFFFFFFFF\n\tFFFFFFFFFFFFB03D000000060002000020000000060000000020000000008000000008000000008000000008000008008001\n\t00000800800901800900000800000001800000000800000000800B00B0080000FFC1D600000D03404C00000000000D000000\n\t04000404000000000000000000000000000000000000003000D0050000000300054010350000000000000010000000000000\n\t0000D00500540D0000FFA41A0000004380C1000400000000400000040410040000100000000100000000100000000100000000471040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c71040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000271040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a71040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000671040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e71040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000171040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000971040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000571040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000800B4D000400000000006FEF700000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d71040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000371040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b71040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000771040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f71040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800B4D001400\n\t000000006FD39500000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000af1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ef1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000df1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bf1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000800B4D000C00000000006FF5C900007f1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ff1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000809040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000409040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c09040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000209040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a09040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000609040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000800B4D001C00000000006FC0BB00000000000000000000000000000000e09040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000109040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000909040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000509040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d09040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000309040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b09040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000709040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f09040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000800B4D000200000000006FE6E7000000000000000000000000000000000000000000000000000000000000089040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000889040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000489040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c89040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000289040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a89040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000689040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e89040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000189040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800B4D001200\n\t000000006F7EC80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000989040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000589040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d89040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000389040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b89040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000789040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f89040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000049040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000849040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000800B4D000A00000000006F589400000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000449040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c49040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000249040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a49040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000649040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e49040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000149040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000949040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000549040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000800B4D001A00000000006F6DE6000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d49040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000349040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b49040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000749040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f49040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cc9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000800B4D000600000000006F4BBA0000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000800B4D001600000000006F77\n\t5F00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fc9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000029040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000829040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000429040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c29040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000229040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a29040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000800B4D000E00000000006F510300000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000629040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e29040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000129040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000929040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000529040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d29040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000329040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b29040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000729040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000800B4D001E00000000006F6471000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f29040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aa9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800B4D00\n\t0100000000006F422D0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000da9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007a9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000069040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000800B4D001100000000006F88670000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000869040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000469040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c69040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000269040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a69040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000669040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e69040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000169040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000969040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000800B4D000900000000006FAE3B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000569040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d69040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000369040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b69040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000769040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f69040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000800B4D001900000000006F9B49000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ce9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000800B4D00050000000000\n\t6FBD150000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000be9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000019040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000819040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000419040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c19040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000219040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000800B4D001500000000006F81F00000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a19040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000619040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e19040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000119040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000919040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000519040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d19040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000319040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b19040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000800B4D000D00000000006FA7AC00000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000719040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f19040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000099040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000899040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000499040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c99040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000299040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a99040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000699040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000800B\n\t4D001D00000000006F92DE000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e99040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000199040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000999040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000599040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d99040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000399040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b99040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000799040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f99040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6FB482000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000059040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000800B4D0003000000000000859040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000459040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c59040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000259040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a59040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000659040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e59040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000159040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000959040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000800B4D001300000000006F2CAD000000000000000000000000559040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d59040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000359040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b59040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000759040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f59040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000800B4D000B00000000006F0AF10000000000000000000000000000000000000000000000000000cd9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ad9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ed9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dd9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (EFF7FBFDFEFF\n\t7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7\n\tFBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7F\n\tBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FB\n\tFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFE00800B\n\t4D001B00000000006F3F83000000000000000000000000000000000000000000000000000000000000000000000000000000003d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF7FBFDFEFF7\n\tFBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7F\n\tBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FB\n\tFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBF\n\tDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFD\n\tFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDF00bd9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F7FBFDFEFF7F\n\tBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FB\n\tFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBF\n\tDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFD\n\tFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDF\n\tEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFE007d9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (7FBFDFEFF7FB\n\tFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBF\n\tDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFD\n\tFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDF\n\tEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFE\n\tFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEF00fd9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FBFDFEFF7FBF\n\tDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFD\n\tFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDF\n\tEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFE\n\tFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEF\n\tF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF00039040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (BFDFEFF7FBFD\n\tFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDF\n\tEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFE\n\tFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEF\n\tF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF\n\t7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF700839040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0CF2ED55BE95\n\tEDA3D2A914A83316954AE440695A0760104FEC006B003E386E1D01C3F532A956AA4084940507A83824081D205805810BCC7E\n\t0C679C1E6001BB3060EA7594DF48030004E4200C114844E11024283B040FDBAFF3A3FD4C0015BC428C021379A60821838663\n\t914901A44E04374883A7731104A645018449248A0800066CA11C46754211C8E41203C94421128054004DA21941D0612DF688\n\t42048201326B9120581E2E86AA244A0D84004038006FC0C020C2060E955203532018C8001A0659C1C6192084FF499902A626\n\tA9055CAB792B01430579CD9E00603FDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7F00439040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000F001820100800000000000000000C06030180C06030000804000080\n\t40000000000000180BA61084384236AA1D2A5272017CEE222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE\n\t222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE222EC22EE222EC22D86C361B0723\n\t91C8E48D46A351A271389C4ED86C361B072391C8E48D46A351A271389C4ED86C361B072391C8E48D46A351A271389C4ED86C\n\t361B072391C8E48D46A351A271389C4E207F83DE0FF201552AAA150000000001540AAA0500000002024102A4310C1D8C159900c39040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000239040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001002000806\n\t028006004000810000000186001833018301800C18CC6000180C060000060C1C000000300000000C0603000A801001800006\n\t000060000001400C0000C0000618000000000018000000000000180C00000000000000180C06000000001800000000003603\n\t00600000000000300001800000000000000000000C0000000000600040000000000000000000000000100007182018C81000\n\t078C0018C1E0380008140037838000E2000804488000000000180000000000018000800B4D000700000000006FAD97000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a39040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C10231808F60\n\t00184081E230000318008188000230003047A3180080623006C061820600011B0180081800004C004000788C0000C6002062\n\t00008C003C180081800046C00002180080000C00300100D8008180C0040C4000060020003000231800118000188D80000400\n\t046006008C6602062300003040C004801808860200000180000600060881C0014080043E8100004000060C00200040A00000\n\t00036602000000630840830000C00CA660CC660060000600001B0840C01000000005402C00000002018321028DC6E35000DC\n\t0001C3811803418CD80000000186000000000001000000CC79821F83C1000018000000000CC660004000600F11E00000010000639040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000300000180\n\t00600001BC000000003040000602000C00103180006000110080000000000008040280003000800000180300002000081008\n\t004800000100205000000AC07800180001800000C000000030103000608100280000000001C0000001800C0400000CC18031\n\t062301A00003001800000000001840001800000218020002301A0006000000C00C2000006488418A000800120C00000020DE\n\t000060C0000001A200000003C0600C06030180E1D338708F66021F83851A0D06834180DD080470CD1CF31C38C70E31C239C6\n\t2C0000066301020C46C0600206080000C004001E3206002062300003040C004C0618206030010311800018218008003F010000e39040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4301980C010C\n\tC46000000066000400000C0400004000000006000018006038180018000002007003000C0180C41801548F0600000000000D\n\t8603600301000000C000B80000198C058000548E0600000000720860C0400000030100000480000084002000000000040080\n\t0030000060006000000300000C1CE004000000000001802C00000000300000000C1800180000180C50AA0000000000000040\n\tA005B00000C6000018000008018000700000000600000C0000F000000003C00000000100001830000000183064204000C000\n\t001820002000000100E0000060000030000C000020000E60001000000200000850220442044201100040201C40800301800300139040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02C600018009\n\t040C0120860C0010086020700010088710000000000000000000000000000000000000200000400000000700000080002800\n\t00801200400041000403C500A040A0180000002118218000002006000000086080060300008000000000600C000001800000\n\t0C06000000C000000603060C0000000000000000000000000000003800020000005030180C6008000000003000000000C000\n\t00000000E000008100060000063018000000C10000040001820180201A000033010218008000080000018C0048C100000008\n\t118000002003010000000C000020130040006600010C81008000C00600C003005B0C600C0000010030603186300600D0000000939040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (319800003001\n\t80000001800018000600000331980C0600000000000000000000000000600000000600000000003060800100000000000066\n\t300500000E34000C1C0860000060C41A0904000000060C00000C10000600806FE040C01030000004008000E0000260330000\n\t0000C06600002000000000CC00B07938C000C0008004001980000001800C000004000000A07801000C0000C1800018200000\n\t1F081000F000004400000E00682442200630018F0560200000040A0003000880000100821400100884408C18804000000025\n\t00005430000201032002000080450C8000010001400A14000700200000040000000100A540C0000010300000C0033004001800539040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1FE576727DEA\n\t2538124A24252109280C2218004117CBFDE03F2924928106000400051A140800B103C47E0467941FA010AB3120A65700DD6E\n\t81101416B9040405E2948B1080BE0D28C008A010A044880032100201002810881028540A2320318680050F000831D00196E0\n\t65001864824AE416971A2CC4EF764200240E49200562D1088D361054199AE0C3000C10A004998C82760048943941A25FA916\n\t6A6D14424004080001C02042371E34CC4BC0C0B9C4F216219840A119B004CF38060000007B10DCFC69BDC9E20559AC4E1164\n\t88000000000000000000000300000060330180000000603186000180D80C00000000C000001060000000000000000000000000d39040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000C00B921D61A25AE832D85C0E436625830920C209B4566135888D24A201000000000001F89E15AE1046B\n\t783845AB4653010E876921DA42D3C0B4F0D243B490E78169E05A876921DA42D3C0B4F0D243B490E78169E05A876921DA42D3\n\tC0B4F0D243B490E78169E05A876921DA42D3C0B4F0D243B490E78169E05A0055155FE0055155FE0055155FE0055155FEAA00\n\t3FCAAAA003FCAAAA003FCAAAA003FCAA557F80154557F80154557F80154557F80154FF2AAA800FF2AAA800FF2AAA800FF2AA\n\tA80008392484027048000000000000000000000000000A880552AA09AA543118874897429086577EB7DE8DF7F3FDDEFC6B8C00339040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b39040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000140012\n\t20000201200010090003D00900580004086000C083C202486600000218000060017800001CD3C9C4E22020C819A092418592\n\t30EA03400D54C0C60081C6085018D86983F80C00A431284CE621B215320804341446E502C0D80011018000618049604A1523\n\t4100040204D8AB001D08A4831A1C1200000007803041A87027138E400000010110040103040000000000800402000E040200\n\t60801000D00000080000000009CE472538000000800B4D001700000000006F6E9C0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000739040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (158000000000\n\t204AC205041000000020208240000024801001000000000008068224100B00000560000000000812A890000002C004000000\n\t100501122848200000136000008000000000000E444BA02E02002C0120000008000000000809E44000440004020000200001\n\t480800001000000000461001200000000260101C482000000000000080000781000392241000510088203000000000203200\n\t080412804000140F008C3040000001000000000008018E2833A00000020001008022000048040A0000AA13039004E1F8B174\n\t8F31804A2070100000BA472815029033D5820C50BC404994CB80001B52AA0040420A005A9438B4C0A00400004C270103006000f39040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60218ACC043C\n\t01C91080252230410100071100C042C05100480000822456045484104ED48801E00366311B89A320000001018100008450C5\n\t1003710081C8A66AA01E222620190210118026013A0A4D0EA1E84100F80100000000000840800400018207F02054004F2710\n\t0005B124082C100080000040C0A4721112808803380C0021083048804180B800000000058434D001B81478049009C4E08000\n\t00000000000000000002000C0040000000000000000001000000000010208408210021040838088542002008048040000400\n\t000081C88914200400000020000000081488841000002000000100000001005044AA000000002112080000100900402C0000000b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (899CE8005B30\n\t000000000003F190CC000C000C078081206D80C0062000018460240000041C184E1148C8040C4700C060000001E0C00030C0\n\t080410240000040814E074C0D0D20A0200018C30483CB8000F00190000003012CA6888000C206BF85EC0422CC1001002C100\n\t800100000001809D1800000D0383005344E040420342E4416040020020080287139249900021001A2110C044660669900263\n\tD18019A67B099E12400108A056340E0C00E0D14028221C018446A5C08244400500A31827402008000952008623023A0C8EE0\n\t3E005022368900E6100132C3208440C1C6080104198250000060A90209508000028122860902800741010048442129028D26008b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (014007000081\n\t61342005BA0C3EB103AC826B003ACC2680D7A031EBC086FD190B07CF14180C0A2C0A00C20504984000046A090088000105D6\n\t02501C964000700118CA108214072110000602142EC78034084D84705D3841EB836AEDE6487C00DDC8B540285C327C00100F\n\t33000C6402048E080002301400204880C2004202A130E84830000004896018910890080C1081A402801630000004000D2021\n\t1029006D8662E9800473009700015004002A40201001266001E01C652800808002E84000012E410806008C0020782A024004\n\t822C1CF045A080280610300080640891420112294AC90809C42020416114A2348C828820020114AA042B81C00000E04CDC00004b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8488160A2510\n\tE84820DD832470050C801E0541E000C0005C1C040813ACB703801E203E000867239088540000000000008100002152080040\n\t800134180C1218D44942D30080034C0312C002818DE460280D89AD300200640040AA9007047A8854C80E8280000000887A28\n\t10A09F02816009C215550180CBE5122902AD0034100000920C12A830A6952533D004002C650888272421E082100208004CC0\n\t00058422010A400F0380C406000032158001809C840C003481A000031980010610418C00103580C0760C000E065831980008\n\t2A06ABC000C8024020028402004009284542000201000380E42201A002088002A0008050208C08050100002000000000004000cb9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9C5572880A03\n\t966BFDD43F3B914BAF12E81DEE552A17C8ADD2A98D348D4B8D5765559955EA456204DFA443A330E01D0EB54E27168914AE47\n\t399310A330AB38A8C40BBC50EF11A319FEDC21BF5A6CF629843C8D3A8F4BE7402B7DA0757B914E25D2E158BA7162B54A2C72\n\tE9702E550ABDCBA75389F5BA113E914B8113A974A854260D462F560854AAF422B44B86D20974AA1D3B954803520330E6511A\n\t914AA512A9508A453A0558A513F854AE572315400510E11CBEF33FBF41EDD2A84188004020042B21DA18E0EF169B0F40E130\n\t3C402201101800D6402D7C216D0297EB62600D6203020006C0000001900005AE518D93780C10C0180A010007438870A51134002b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010018080000\n\t0000000000000000000000000000000000000000000000000000000000040C728854AA510B9DCB871239740C002AAA9FEFF5\n\t51540055003FD54AA7F800AAAA7F800AA55003FD54FF5515400002AAA9FEFF5515400002AAA9FEAA7F800AA55003FD545500\n\t3FD54AA7F800AA002AAA9FEFF551540000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000143FB5546021E0000000402A\n\t8540040001000040208540000954685619BD53ED43EB09AE5C7997DFA4F3ABF0DEFE299D5E2577293C1A537695066552615400ab9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6001512C8418\n\t01620C289045C14720F06006020018003060017802041CCACA92128424C85B8CCD2B25293D0CC3198F8D64C7C201962000AA\n\tD86A31F80D1E933489932A0148E85C23080AC10CE510C1188404001020E5D8103A00420904EC01B02D4E36783C0703259BE8\n\t1CD86C361780B181F5E05555110103425905487406050009C00000C0E10181002C300209A4C81D3151831402351A8D16BFDE\n\t05F150000000800B4D000F00000000006FD17C00000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eb9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (F8C026840080\n\t19A05012C04600660006076098505013602C446001F800C03328B004001060EC04B001800EC10028B4B8C060135060266220\n\t003F00231DA040A030060C660D070C0468016003603609E402081D020067839800D401B488017601040006C3608E82001600\n\t61011A840C031800184D800300764401800280039B00000020000860B40170023323B0494805005CA621220F958010994006\n\t4064361B0780000C4A511510D002C200119E032011C901010008201807095601F19815DE076793D8E4C00361B01C28849408\n\t1043C19C5C639EC6851288959010290806A9C638740E3C798CC06002001156500003186D86C36100000A3301800098049888001b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (230205310009\n\t00004282084012EB14020B0788188FF03801E0032633DE80066130600305990C6832B0C0C8000D00D0256660510832671005\n\t650003C024136603110C00EBC030C72118CC663718C01E4B1189498B25921150405410808F01F12C980410301B04B138349C\n\t000291898006780440031FB0D9C1F180F1A0D86C02CA2871D3B432547304C00A9211C558C46408000C0301800032300CC90A\n\t10780C36070B88C8426101AC604B5110D424F508C096060001446300003C1AB0518059800462B408145000180001F879800D\n\t403B488810000D98F4000FC2CC006800EC110A160003F0000D02355800CE013140CD80B1118007E00300CCA2F00884CE8011009b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3D88244E2009\n\t81A1404DC0C126100000007824000F061404A840D0C5060E7903C86633183DE8700804C9E4010024800C06290201A1C0F1D6\n\t40121F89A6B01B3CF82B0E9808E8C601C480C418B41B0C047B3826407810402100E8D0200060361B0D81801D180C001D0B8F\n\t060348E2791A9B44E54231858400210305859529280200203754A596D014E0C72B930B4FA38011EE632CBC0F4C17A9280674\n\t2E1C1881F7FB00241D6B855689D290D4184A1997DA2294A2091A431FAC0647063BDCA6E9593000AC37AB856A58178AC604D2\n\tF8E5EA00020C0980300020200F0403C088346A342A13000001C741A9446A55291D568D4668658ACD04BCC98152A1142A304F005b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5D8CD5E335D8\n\tC53E31CF8C73E1C18EFC081D186634180CE60D0E004A0D17B8C40A547A1F49821011058E007E3C1E830071003EC32183DF8F\n\t01E3406E04040D5FE01618CD80704E34C1E3C0384DA6C07800D1EC57E0C09C306C8E006D340B04600C01BF000000403C2012\n\t1980464242003DF8D02030418221990C1A300880D90DC0010D0280023C086630180C86110804880FC660CCE0C7668C026CC0\n\t080DE0000030C801022340E8DC200C40804060CC0600008CC00006A10C78007A88060CC1820C18D06680006C0200311A0D60\n\t02C603110A2400CC5814000E20683D1202060C41835401C482010A28406D86C2C15628082A0A084198F000633188C1A2B19800db9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (063F5A3548E0\n\t37CB2198FC1C0887A333833170283E000E2A5050140260000D86C4F0103C400012000000001810080454010428C1E14CC6CD\n\t180307E4C28B8580E0603F19EF30018018000202020310D84066D8260006836690EC18300002C68044481440200103000340\n\t0341800F003F4027068814200019BC8083378B00842F6718882512000482596A2852ECC00005A8A40598082547A0DD064031\n\tB0C600058140180C010C01E0000315983D1630C18C40437580CC663CCA0E061831D832180C06C3F069C018006008DE0700F1\n\tDC78DD0E00060B000171E08F00934201C00201A000108049A00009C04000680105047081818607461000E1162319D8CD5E33003b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (402000A804A8\n\t4420114881500114004000150004000100A2440A9548A402A044221008944A251229140855021542254228508A4528954A25\n\t422910A851089048A45288548A540A954A8052A940AA5122844AA540A944A245288448A152A054AA1528950AA512A9102215\n\t2281022112215488450A854AA440A9548805008502A010A9502A142A814A80120044A21502954825502110A0500A914A2550\n\tA9540A452A800A21402900024000800A8552A0500060001843018BE1E0F51EB31E02C060142423010C0DABD6780D121B108C\n\t1E6886E00C62130620012603198C0EC019BCC40F347800A0940FBB4002078BCC9E715D90C68E3782355A4C678005EE779BCC00bb9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000408A0108840021528850A2042A00400553FCAA557FAA800AA00155FEFF2A80154FF2A\n\t80154AA00155FE557FAA80000553FCAA557FAA80000553FCAAFF2A80154AA00155FEAA00155FEFF2A8015400553FCAA557FA\n\tA800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000028550A940AA010000000000000000000005000140000000002A1\n\t00AA012A954A85520954A0002800480140014002500A804A8152014020000201082412090408140A0140A050001400042200007b9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000180C0000000000000000000000fb9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0800800C0883\n\t40000000007856040D1FAAF150400AF96628C00000A8384082109E504EF7708DE6885004D86025786C04C2762705E2013040\n\t0E0801028442E5A1F8783251331F62E19100F082410B100A81004014B810950CE72010CD9A00551541803043B0E2AA551DC0\n\t4290580828C00600002C000000A03000004080160300004800320180100280B4F507AA814552A8018000800B4D001F000000\n\t00006F3B7A000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000079040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000D8D54995C\n\t1C1300008620000001520E04BD0000310040060000240D4912001400E0000080200101C0000C0016C2A842BA18100E100402\n\t0000000D8000581548478728114400000300003481A8081041010004C002A8822210101601000A8004290090160550004000\n\t0C048E52840001400012200002241702000019200001E30100502CB0021C530CA11A0100E2042A8AAFF01001F4A57F10CC82\n\t00002D9C4507900881301B38081B018C080404214880010102020A102955FEC41180862D0002094602401B84000440110093\n\t450B074C01805050140A300001000811FC5F04800A6FF002A982402A220086000008380C201402001419006ED1080408042000879040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (20021002800E\n\t01000281800327130800003888344D07805500A0600812024180110060100504520000154022600104882300118000000180\n\t2441159FAEF208600C490980000334580028807C9FC88210181044800CAC0AA490980002E44A80044E800000280005800661\n\t11A00D40557F820B0DB010813E046180080FA3FA442820181A8764C602A0421D10800F0B2078500415019908007182A068C9\n\t4123120C941860840658300A4000600018006000860002DB95085727300C000000B00003480A808902000C60400002058000\n\t0240D413010C4000C20028203040000C8010688C00031880008005482812D419030AE11110A006254180C60040210180001000479040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000600800\n\t1300381FEC2678DC860C6701C66A82B0C5E0202220C100010008001000AA0BC9A020C0808004A2800004008C08032E290842\n\t415000005001230AA00600441200401800A8B00004080E002A8AAFF3A03C80452AA542C50400181420000018000261058000\n\t0081000A9751FD8A082010CA0004284102A250000189542185406905028B807001AC02800123540422D2000C825010000000\n\t006018481018430D4412C8B4410AA812488512806068041094001000C41E00182A40E202004188020204008C008820000508\n\t00400B32D215A2061200080514212428450808100441325000220400884000212180822C29820700090108814A82C948100100c79040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00CC00344000\n\t0018A0000C00000140000001140200001003207800A8080C17CE81006A011C7C00814105F0A0200630460D01820200108410\n\t400C0180409010181A0600C06D02C0087A756E380400C000000470158D400F12023C2081000040010100208EC860800C0000\n\t00043C004E88000E40080098400230020A82100C44001002804C1260C4080462800380021000003202000800000290680C01\n\t0500008000C40800210C400001410C00046504000000A10C08C04201082400013140CA6202400900010860DC4002880A5410\n\t218200000D8000010B000008602EC9600552C51600002A014510010918567E80C00283808C22200E28180801508D80D006A800279040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8402E8003415\n\t1E00108EA7F85426F00820054C50103028405000006080580000005420848800017026590F80028C408935C050208C058C30\n\t0185420053B30400004080660810041066A288601C200032060084D01540A319081440208000500008B28000001800000100\n\t0000000000411426271888251002800A0C21884248008844E43C058DC8640208558CB02B0E42430401795214008005811089\n\t04823006B1028C00214000640614C2240098401835002C02031228C0181021004800061940280011001A21000020BE4540A0\n\t0000C0031C10001608400011E02040C914001728060020000004000660040000180C06030180C06030180C660019800060C000a79040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C87C0819C307\n\t10CC40070602906C200210263000005C6E30993C0C4C7F310003200020884120840025100301D07470A8D82CA6784C1C8B44\n\t0401CC000239600250008C6F97C38002A347830000E0B2307E731F175E0E37196400016511870335710006B8460CC6E37070\n\tF9E6C040105C849202D8322C402009A60018002493181045CD005A109C881A0089CD25202442842602400310600800A25522\n\t094E06E09048000020008281020804440000040181800400B411048EA0A068ACD0205180D90E80200022C30100050A82B3F5\n\t9600000C410C0469288C30402DC180260174E04002101280460165884E0600920680A80440047A0208C0000004801C20280000679040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000400A530801380418302030018366498D389C31B246CC91B270C6634E0D992634E0D992C91B270C69C31B246C36649\n\t8D389C31B246C366498D38634E0D992C91B270C6C91B270C6634E0D992366498D389C31B246C000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000142AB54A6553E944AAA2150000000001502AA815000000000224082E00091689068108400850B291\n\t60A24AA194AA4129D463254128D4925809054494592896825A020402D42AA9782A6820DEED3608E1428D20360908B250C9FE00e79040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000200180000000000000000000000000000000000000000000000000000179040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2E1545A2AA94\n\t10FE6680400005BB31E000003EDD4EF6603DE6000008DE6101B83C10B07D8F01E0000000180000000000C501FC580000031F\n\t63D18300C80000020000000080D239002205430658CC1C00000001883000A060000000006006480148C00600026800000146\n\t2300004180107B1000C4001300022040000000783FDFEFF7F8008000800B4D000080000000006F8DED000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000979040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000028002B08\n\t000100000A400000000006003C10600000080001034000080000180000003C040600000280001015000000000080058018A0\n\t00000500000002C0003040000000C00001023212001000000800000001900000000000060004801804001B00000064000000\n\t36420006120000800F06E05C0E00063E490C20820002800500000000100800000000906100002104C2011C4901F1833C783B\n\t000A9000000021060900000000040000002004004F6300208018000020000442202000116008C24000000040000430800006\n\t882406001C00126AA2A9558002102804020090291044412018008618080600180A1000021041002004020600000001F8280600579040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (080004082020\n\tC40180000001D800080000800003C000000000001000200660000000000019800000000000100000064798F01ECB19800383\n\t10180000000000060000100000000980000C81800000086000C008000001E0000380000001E01404000002028D706080984D\n\t40800000000270D20C040911094183B0003F1000C3081040281402010F48035162EC18EB40031060451021040231A54A6100\n\t401C0A402000020000028000004DA0020000401000020020000B0408006010000000800010018003003FC020400021E01F00\n\t00080031D8DC0002280000800000E000FC0B81080010407006B041804200002B00800100000004001000562700004A00006000d79040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (840C3822C060\n\t000071FC107C0CCAE40083CD80280380000C0180F1A48006000001001B3C10336E0009800000000030118000000400884400\n\t40000001C0183410CC1000000007E23D80090000000F00001000180800080002391000002913000040000000070030C00000\n\t000000000011410500400000C3060000C01003A406000000C00007800008003010000000187040400880000400080000001E\n\t100800C00000028008210004100344280C08004000000041804300044084008050220F080200800002018003000000000120\n\t04400108940000400150000006004C08002121000069110200001800800000010180100320061007800E010000018083061300379040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000730C580D0100060C0070809800000C06400600000630020D01820000000030600C0180C00001000C0000C06F80\n\t00005CB26400000C0000C00040038C002400403D00F0000000000000301EFC418007820003307C001980812E401A0040C006\n\t30000007800C00201400000CF660CC000067800780061800003306001800000000780C018F0000C000CC1800618CC0030000\n\t0C000C600C000001E30C18C06603006C00003000806380400100000000C0000018000020108230060CC000001B0000006000\n\t40000000CC24020000000F0002011800000A034027B30C5C201A0010000000CDE0D267B300200063CC002C00800002A300F500b79040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (200000000410\n\t003C788020000020C0600000000000038800000C0200040200208008C1A030000C018C3000C08000780000000000E0400000\n\t0000000000EC1A001002068080000000C01180000001C0040000003800000010080007000040800008000028412888262000\n\t001A00003418A80180CDFC7C058700000000018400000D0603101001F03C6183018331990DE631063F17E80063C180CC043C\n\tC60F0190C4183F000406023078C018006000C60000000000000000100300004800000610000040013C00001E00C00001E000\n\t60C0180C07E8060000600066000663326000180C06030180C06030180C660019800063C000CC02301000461800000C20000000779040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100311E63200\n\t0BC062321B31780C10001100210928108010009100314229103C0008DC0C6463805C470D00940000518080823420940CB621\n\t31421046095C4426728066F81931C6603798CCA6036BB351033112080008400000000210C990384120C083021209F0205C89\n\t898080181124731132C7A3247AB19A0A4A08C84F25181D76A0602300080160084AF11FB389EF01F161600040000080000000\n\t000019800000000030203D01800442E0322D8000008048000000000003000002202000010000000C800C00780198301DA980\n\t800602A154A01C30020047811088C404030007B7D208000858221060000000000C0420044000003160001E0000800003004200f79040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1020C0002240\n\t800087169E1A4786921C5AD23C0B50E2D43B48F02D43B48F0D23C0B50E786921C5A87169E1A4786921C5A87169E1A42D43B4\n\t8F0D23C0B50ED23C0B50E2D43B48F087169E1A4786921C5A0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C64A252\n\t09C040000000000000000200000000000A080550AA9C3898082BC78BC7930060DC7813D988F033F19EFC1195DE6936383DFC\n\t83680807E48069241AAA6A0604235613FDB83F0D0290892600E1DA483423088051434DFE4C7E0C19E30798CC60A04609946C000f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000300180000000000000000000000000000000000000000000000000000000000000000060085902116B2008f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (31E000003058\n\t0DF6602DC6400A0CDE6301E0300030798703E000000008C001800000D603FC780000031E63D183009E000000000000000826\n\t3C0100000300600C080000000180300000600000000060043008488000000664000300C61000000180327B0C80E200011DCB\n\t3018000000603FDFEFF7F8000000800B4D001080000000006FFED90000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180026003C18\n\t30000058002080C000040000000000003C06031800018000183D800000000040078039E200000F000000038000306D031600\n\t40000086311A001803009800000301B0C00000000002000780180C001B0000006000000032000002100000814F0680D06800\n\t46304C0C0092000280020000000000080000000048E30000110A851501480020813848116080900000000186010000000004\n\t02A954C400809CE140608000000000000442200000002A0F056000000180000610C00C04002154AA0D000A6552A95406C000\n\t320101019009088C001008AC840000428C0014082020A8108808040204000000009804001D0AC552A8940CFE6600C00103FB00cf9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180001800000\n\tC00008004000000040C600000000000018E000000100080000000540801002C500800182001000000000001E600008000003\n\t1980000C40000006006000C00C30000006C00003000C01E02C00000001970F306080188E002000000001F020040205000040\n\t815000346E00DD0730783C1E0F0785D80050E1DC38F72082084084108010CD01B0006100600006C060000600000080000017\n\tB0060000003000000004000F06180000300002018000100080030033C0608000F1E00F2000180011F87C0001780000800000\n\t4000FC0983000010604006F060008600005B018003000000080010007E2F00001E000000000024000F18002100001E800000002f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C80182895036\n\t0600000C0162E9E6000400000001122804A36600150020000000B011000000200000200040000002C0000816CE0000000007\n\tA03D00090000000F100020002408000800044A2C508A50230000800000402B0130C0000000000000002A800A001000008200\n\t0403086003180600000200000780011000502000000010A024805180400C00080000301E20110060000060000030000C0000\n\tA8300C100090000002800003180A85480562A1540F50300D000000000000000200000140084002112800008002A040000402\n\t90040042108000302214009010010000000A0180A0033006A007801E0300000180030623104000100140E81800000040780000af9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (281800060C00\n\t78019800000C06000600000630060F0180000000003060040180C18001800C0600C06FC000007EF366080100000000000001\n\t8C000C00203C44F2000000020000100E3C6180078000033060001980000000180100C00600000003800C00100800000CF660\n\tCC0000678007800618000033060018000000007800018F0000C000CC1800618CC00300000C000C600C000001E30C18006603\n\t006C00000000406580800100690420C4000019803020108210020C5800001901980C618CC0600000CC66000600000F000000\n\t18000000060437FA0C16231400100002028980F047AA0080006A894431020000000600FD060E7032C0600000A1B0137008D8006f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (402800001000\n\t80078C00000402000680C06CF008D19830000C01803000F08000783300000000C06600000000000000D01820100186008000\n\t0000C01980000001800C000000300000000800000F0000C1800018000020070888243000001A00000F00E20502A95E78038F\n\t00002002010002000C040A100000E0AC6503180AA5530D64A0603E05E32142819488002E850BE1008000EA450CC400205001\n\t500B6600C7800000000600000011830000C000004632806A60413400001E00460001E00140CC100C836C0610006000740006\n\t0AA34000000C00030000C00030000C600018000003C000C002300000461800000C20000000000030000000000060006A286800ef9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2AA303A313A1\n\t11A84E498C42EF13E331A8DC31944A645229046A452B04CBAF006B75E0C56E115A6552A250AE532296CE6457E9702A570ABE\n\t4A65130BDCA6312E915E8112E9DC6E54270F47A3D26854AEDC22B44B81501974BA1D2F97C049700130E2511B934AAD36A950\n\t8865680D40A516E875BA3526B5C00F31A114FEF32FB5C1E572A8B0380060000180000000000019800000000000203D010408\n\t81C0201C80000180D80C0000000043000006600000010008000C000C00780118300923008006000C10300810020046811088\n\t4404010001121000000018000000000008000C40200540000011A0081E00000000030046E000000008E01818300000000060001f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (198CC6361B0D\n\t86C9C4E27138361B0D86C9C4E27138C964B2592633198CC69C4E27138361B0D86C633198CC6C964B2592633198CC6C964B25\n\t929C4E27138361B0D86C00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000343FB5546021E0200008402A854000000900\n\t02402085400009D5E8D4181542A542B9002A7479A7DAE4F2ABF0FEFF29975E2E77A83C0A413294022D4233540C5D36800A81\n\tB65BFDCE3F7BB34FAC10F834E077261DC0E560EB855485328552A55489982ACF62044E24C2E1F1A01D0BB7CA25138B14FAC7009f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000201F8000000\n\t000000000000000000000000000000000000000000000542A954AA552A8004D2985CEA511FB74B87106B5C18C964B2592633005f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (DE6301E03000\n\t30798F07E000000018C001800000F603FC780000031E63F183019E0000000000000000063C0000000300000C0000000001C0\n\t300000600000000060004008100C04000660000000420200008180006B1000C0000101833000000000603FDFEFF7F8000000\n\t800B4D000880000000006F021B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000df9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800000800\n\t00003C06071000038000102D0000000000800780216400000B0000000200003040020000C000000632100008020008000002\n\t01B0C00000000004000280180C001B000000600000003442000422002001EF0740E874024630940C01120004800400000000\n\t00080000000091610100AC940A600290002103385033618C000000000186030020000000000000C000009867006000100000\n\t0001000000280000000C0404008051801426840A2D51002800001C00146AA552A806C008300002019001100C000210AC8000\n\t0044880010902200A0110800000100000000009800000C150AA5502864F56780C00307FB31E0000030D80FF6603DE6C01E0C003f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00C700000000\n\t000019E0000001800C0000000200000000C800000183001800000000001E6000180000031980000CA0100106006000C00C30\n\t000046C00103000C01E00C00000002960F306080180C010000000002F04004020A00008102A0203B5400D10A3070381C0E07\n\t0F9000F1C3A8709A41831060C618C0180200B018600060300E806000C400000300000067801E000000F000000030000F0600\n\t0C00F00000078000000000010033C040000041E01E0000000011787C00005800000000006000EC0D82100010006004F06100\n\t40000038018002100000080008005E1F000096000040000018001F180011000016800000100016003D1870000098001101C000bf9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C00600000300\n\t0000000366000000004000003001800000000000000000000002C2004816CC0000000007E03C800E0000000F000000000000\n\t00000010004C00000003000000000000030180C00084000010000030C10300400000C3040C0609C003700600000280000780\n\t0000001020000000302020010180800C00100000301E00000080000040000024000800000080080000000000000000831810\n\t0000006000000F00301800000300000300030000000000000000300000000000000000000000000000000060000020000000\n\t000000000180000300060007801E0300000180030603000000000000C01800000200280008000080000040000000F8003000007f9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (060000063006\n\t0F018000000800B0602C0182C18001800C1600C16FC000007EF366000000000200000001AC000C00003C00F0000000000400\n\t301E3C6180078000033060001980000000180000C00600000007800D00301800000CF660CD00006780078006180800330620\n\t18020000007800018F0100C000CC1800618CC00304400C000C710C000001E30C18006603006C00000000C06780C203107B0C\n\t60CC080019803060318630060CD880001B11BA0D619DC0E00001CCEE000600100F00000018000000020037F80C6611100008\n\t000040C180F3078C00C0C0680C003D020000000600FD860E6033C0600000C1A0216000CD8C00800C003C0200000C0060C1E600ff9040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0B00C2ACF409\n\t619850200D09A132A8F48000781300000100C0260040000000000064183008B24600C0000002C01980000201800C00080030\n\t0000000800000F0000C1800018000020030888241000001A0420A750A00000001E50048300000000000000000F0000100000\n\t780C2001180000030C2000603401A00000218000000C000300000000C0000CC00000000000036600CFC00209402E45021551\n\tA30140C000000630006040033C00001E00C60001E00000C0000C0060060000600000000600060000000C00030000C0003000\n\t0C600018000003C000C004300000A61800000C1000000000003000000000006200600000001000060C10F0011800000C040000005040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (422950A05128\n\t9448A45288540A5508954A0052A940825420944AA542A144A2450A9448A112A054AA150A940A251221402255229502255288\n\t40A8450A84422400A954A801009408A012A95428042A814A80102100821102854824508014A25008814A25402950A8042280\n\t0A21400854021002800A05528150006000018000020040021980000000400060BF018C1983C0603DE6200180D80C01000000\n\tC300000660000000100C000C000C20780018301803008006000C003018300600E7833198CC00000000000000000018000000\n\t006000000C0600000000000080001E00010000030066700000000C70081C38006000002040380000000000078C00000D020000805040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (349A4D269349\n\tA4D269349A4D269349A48743A1D0E8743A1D0E8743A1D0E8743A1D0E2D168B45A2D168B45A2D168B45A2D168B45A00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000020550A940AA010000000000000000000004000100000000002A000AA102A950A\n\t85120840A8000001480450010000502A80480052015022500205402440091028400A00420050005000440294402400A01028\n\t5420004885528954881008104005108840AA440A9448A00200442A0028144A251029048A55221102211229108A5108914A2100405040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000201F80000000000000000000000000000000000\n\t00000000000000000000000000000004008110A944221520010220428810783C1E0F0783C1E0F0783C1E0F0783C1E0F0D26900c05040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A6C24A55365\n\t92A1A4B4112D918485915998CA4932A68D8D549244B26538AA1549932A592A000000172520E2A954552A954C4823C9B94C4E\n\t5CA592C4254328B65E52AD8B2E52F9ED2C6A0D2A5D4AA05800000048154AA552AAA8D400800B4D001880000000006F81CC00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000205040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C21149E4908A\n\t13000F25632AE5328752390422913240CE65491ECA49A00000D2965310520EE4F155EAD64B11C4C00420492264553552E656\n\t8968D06933198C2995310D74E930394C46F33265B29B332993069149ED74691D00000007EAB4AA552A9B94C933D3E4F2797D\n\t2A4F4AA2F1E9CC9972A64942D598288AA97238D96AC4800000662CA78AA550D06D4AAE159111C552AAAD74192BA55CA2D65A\n\t09D4963CA78B2D530BE8AA55749544C0000000D26A4B198CC9A4D2A54A66352BCA06A351A952A56F0AD58BD2124964A65329\n\t8B4FC53AA8D4AA2B1A4AA552AA95F4A608954F21A2A964B2C548AA4AA1A48AD1246C2A1492499350690E992C954AA520AA5D00a05040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (961280000644\n\tD299D27914BAD4C9932A5554662A954CE0A529654C974D098007916BADD2564A9654C6B331592EED6C97888C452994140000\n\t364AE5A4AA4CAA1554BB8CC552A96534255319948A74F99CBCE532A78AC9E7CBA5D2E974AA4FCEA73A65CE594F1E53C794F3\n\t9CF2F62DA55329A5B3A4F24825079246201240CE554B1B9348752390422913240CE6534879249243A91C82114898809E2A95\n\t83CA44C390CAE520A28925E4B39842294CA1D486801390AA9972950841E5239132653487926A43C920941E4928812402F155\n\t2CE6108A53287521A004E42A964D41E49248F24845098805E4AA95E89A038A4D21E492490EA43400920672A9995A7948249C00605040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (7752C880654F\n\t0A400594A9993C69251654A9921264AE7A13000000033198D8762AA552C5945168B4464B294CA66128A57CFF2B19958592A9\n\t54EA725290816B52822D682C059C56C105B8B016495B04124640595052964B2D558AC28229B4960C9652C964CA55363A648B\n\t596421689000394A2883CB71602DB2424919016690593124B700155EA8E363416C4E393756E3B6EB65BAA574394EA2600180\n\tB2A93B258D455491A12C64249594C5233018EA662B1704C5949894B296252999CAD2491108692AAC5329C4819452EA52AA0C\n\tADF15A916C5E3D16CF6EA3229994713903800F432954CC552C958AA652CA58B2995B154AA5D5C95D2CA933198CE6A0FAC0D400e05040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2B36CD6B64AA\n\t44B2E67B268DA557E2AD3269532654E59333553466333A94AA6532694C9E4999C64A873A512CA433168CA265999CD4324CAA\n\t592A41312D3478132644E002C2A9B29B4B154D2962C225EAE712A592EE53490DB49942B54D07672024CC3832A643A662AA24\n\t4E962CA25129974980EC661D2602CE54A9A12C9133A18CA642B26000604A995149A569A534A62D1553C0952290D29A532A5C\n\tC5513110AA954B9552A00001A4AAA95F155AA6624A1932000020120BD32848A29E49168CAAA4F3A93C990C9454CA674969FE\n\tE552968AA554AA94D299239984C000024142DE23118C86A6D168FEE752958AA954AB9CB24A750012A593C8D9EECA2D024E8A00105040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A9752AAB3299\n\t96CB15FA5932DD7F16804000426552DA0D9E54CA62AAD4B6994C8D956BF4B365D4AF52A41540F28AA5ACA658B654CB16C898\n\t40A4239E9D49135155B6B21627152E76EB748A922CA5D7AD36AA6C4E270031134CE2A955D2C56E27992DD6E954E8ED64AC48\n\tEBB3903CBE52740791A5F2513092E06F96C3AA428099F49F2E0A4BCB51602D2E65531557A973E148AA954C98172565519812\n\t614CA9520614CB258A950494D22504B8253099389A4CCDD3AB2DF4C27D309F4C27D309F4C21D32C74CB5D191963A7D2F4D6E\n\tB3D0AD76625B1ED74F67DBE934AE7EAF97C563D175F67229154D29B5C898B0552C998A4554C8252C653329562A52DAECB6DA00905040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9513A752C874\n\tBA592AB24A23D1F9DDAEFD799FCAA612AB719ED567955FAF438155AA122B9CCBA362FB5498B42095C8AD621B3C7AF57B9D0A\n\t845223F5BAD73A85D8C8D2AB55E05002914AED40AA54B6153A11482767A894BA652D8547E516A914AAF433BE18E571AB05AA\n\t9626969CAAE55BFDF6572AB95D49A5F09D309534A48CC9A33298AA392C864EE567B26D324653218AA0200000B805449A5489\n\tB34994CCA84C9994C2A4D264CA9A4C985346749198CC6632A14C8592CA083299532650C984A324C828331C82A89551992AEA\n\t35AA8AE552AA55329A138010079752A54E6E3F2A952A674B9DCEA62B155326C5B3259C034B29D2A477F16D3C5A34898F29E200505040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (60E48D139C9B\n\t0D83909D1A8D139C9B0D83909D1A2746B60E4726C2344E2746B60E4726C2344EBB5DAED76442211088EE773B9DC110884422\n\tBB5DAED76442211088EE773B9DC110884422BB5DAED76442211088EE773B9DC110884422BB5DAED76442211088EE773B9DC1\n\t108844220C2FBD546001F8000000402A83400400014000502003440000DC781D089DD1ADC1B9480ADB7B1BDF0470BBF4EEFD\n\t28B55E85B6B91C365246B5054957D254907544B80BA226C9FDF8DF2AB14AAF12F865EA5D2AB7D0AF53B9B8CA792D094DC553\n\t1265CA912BB902A516F9F1B8D513B7DEAF47810CFAD74BBB5CEBC4FBCC2A41239D9DAD25ABE5EE5C79970E6F329B488A0D2B00d05040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000E00D9C844F348BCD447351BCD42C050B08A22179089E0A17980926C21289C4E2713\n\t89C60416A17CFAD52F85DA042248DCB4D83909D1A8D139C9B0D83909D1A8D139C9B0726C2344E2746B60E4726C2344E2746B00305040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0B2003211E14\n\t48005280002089460A4105088304D0A0541108844ACA430144820000001201061A4098D02000070D100201EC3028001405A7\n\t7208C0812010902000904422111A8000000000010000800B4D000480000000006FCB6B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b05040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (5826820AC072\n\t40D030801A2506A2022111AE38062184A503800020000422490442E0900E890890000CA03B8008124CA200C0704B10080248\n\t90C22844688CC6246E96062C621B4008922011088140305C00000004010344884D86C32204D8244182001872210CDA2542A9\n\t45245324104824412110888C719817E2D301941C140AA6428CD668440A62749B8161622844A2000000000406100406000000\n\t8924422111A4C41C23518313084C9CC862105C8846A210264E3A040820748890284D261314845000458A1406240060000100\n\t08181180808345F381E40A0100D543111170E8D516894E030400809070738B85EA01508014D4098008A825421C402202A34300705040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2018002A0100\n\t00100500180000011012488C32191426080000800810000052400119082400724880442200DC0F0050C55C4C099440800003\n\t80680E26A309A4D18B31600F67181FA300984C26130984DA204068CC18F31830C60C318031868C0300064310E84D04D14098\n\t0EA80220D030001C30448180E820AC07240D0308049980E8200C074105603821A260002E0C01D12035040B6B105A4201C024\n\tAC13130603A8408034042007235A0600E830468049980E8484135502603A04024D11000070092B04C4C180EA10200D013812\n\t0601A98504D120821A22000048BA242C01D24603A880301D4211068180006086823A880125603A09A2412411106014010C4600f05040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (688100020021\n\t0C188024110884466271A04C220108A7322044284D18055A0040181C8811002340A0600000209027310884C620101A540835\n\tC9A740695020C7268D0E2CC0A3E4AA052283C284138904A8401AB04A84009830E2102380C2AC40992488102E910C80D2A040\n\t6C9130B2088D222204C24D08800A0450A814A29442810824120110881728901244822311824748034A21018904600529BC02\n\t04528874A0510E950A2C10A13182046894400164922090120005040240A3308A512B81500200A82490A44A08028050080000\n\tD048040224D078001A0001804000C00104083020B00060008020000000041920102955880C0404422CD1A13426D321854B8300085040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2954E4C20499\n\t810A4048A842814C00494082C980106500A240054048345009440911C1920361000019908040804200C0940E188101178844\n\t44343C00000487214414490B1A4B01A632444826070A928892C1091845019804499549443869731148C322B245128C2A9901\n\t21A2F25058264C97116885409488C427A0C22700BB1C681D020000852261318E312681C820024341984C000C846442200C66\n\t420280000804A0604011088446847671806E341A045A801321144033338D89A1C03800820F2F004000000039AC2344B30101\n\t1088C484356C265BAC418800200D27000000005104C68100054823548144300470048221900940208012908884322140624400885040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A902011208CC\n\t243018B4C300D00040080013164AA5534908AA5505090A2040190802582B118920201120024946210A2630A00042510A0842\n\t458211103C35518E0244101184920908974881001000884E528348044223885200010893E7448901C2200A0C024290AA552C\n\t11220840058521600A6572144485A2A9540000000000878488D0004010310200D2232084021002C680210048B60E213C44EE\n\t10004862366B0010244490440001201402A440A9102A442A8100005003200A002A1190844488548080242540009081504240\n\t01010AA384009028841A00028010B025C2000020468000210870800C168000A50905487550091205D14195C859049902E7A200485040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2910AA452215\n\t4A25422154AA5522954AA112895422552A9542A5502954A8452A9502A442A9548A5408950A2402A914824028804A80000140\n\t221522144A25428014A2102A9142A510A114AA452A054A2510091002400080020552A9544346084380002954A0A85D828A22\n\t4020644226411C198310406564444101930A00C990CCC820065641008845025E2A008326003A6930503927438013019D3471\n\t333404A1C18A2110C82506922A653044480224088926506159204546200D41402020541442814120000000E4300404422C30\n\t204C98806A110264C09920B24800800C08000908A0440696406CD080D4C8350B0000000000D00004403203056000A46C460000c85040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9DC442211088\n\t442211088EE773B9DCBB5DAED761108844225F0517C145F0517C14F5503D540F5503D540A07AA81EAA07AA81EA0A2F828BE0\n\tA2F828BE0A2F828BE0A2F828BEA07AA81EAA07AA81EAF5503D540F5503D5405F0517C145F0517C14285502940AA000000000\n\t0000020000000010000400020000028950A8002895488552885420002800480550015000502A804A80520100201002010825\n\t12090420142A0100A05200040051009500050028040A1528100AA1108040000500050000022100AA5528954A8400A1542A10\n\t2A954AA5122950AA552A954AA552A95488152A950A2512A95488512A944AA55229448A052A910AA5522114AA4522944AA55200285040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000E001BC1E6517914CA6A351008009151880020178BC940A30080DE67354001FE555500110AA552295428052A91022052\n\t8014110884422BB5DAED76EE773B9DC442211088442211088EE773B9DCBB5DAED76110884422110884422BB5DAED76EE773B00a85040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (211E224F8442\n\t011D000A2F829BA1F079C89E44221047482141A9401954911041600000180A1289810F0078A1042A24A5054AA7C014BEFA40\n\t9108844220000000800B4D001480000000006F6FD00000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000685040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A4B808181631\n\t8601A6F0311148866100D4002591393063500150860448385E181998878CC51808D4A810290642A102209042023C91429520\n\t985430553092E026027082140892944820B2A05028551A05A5A258A94458782202CF56E9E420D95BBD5FEFF47A5C04220416\n\t8004265B7D62FF778CDDE330892852DD0980540FD7F9FC94C71EB7C38C10422020115484146C24B808105A41088C686231A1\n\t42110D398121A04168D0A0469E5FC983381DEEA350A84AA2B222345CDA208E4884422290CAD22A110E0C300050B0F4223E40\n\t85C2A8140640020001E941FB68261400804021F68B4DA243243102008038C41A440004082083A988200000950024528A24A800e85040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (072800428502\n\tBC101448871CC3F3911D0EF84423C76F3100C1949701220000800A3C88D478094C8442202114915108546A24408894A01002\n\t8068A542A150A8541A0529A512214408450A114284528850020E2450086112A0503B13329180915200EC4441069143231A89\n\t989810200EC24143291A895918D44CC4C28000CA220099463472804AA01E398105A41289DAA4462C8C602052802089500480\n\t4CA31A881021143291AD6140EC4CCA4702550002D11104A276A9118B23180814A0080244CDA27328503B13280000A48BD022\n\t8F7926072CA462246463150A90076220C9FA2847A6546EC4C0A0762650008D047122A110B249A89989810200EC24411A89C800185040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (11C07E4014A0\n\t1FEC82FBFCBC63432E064EE12261045F0B1C1B41808904A83E3006DDCE00F2B946FE5D1C1C6CE51BF9747C71B3986275F00D\n\tC6827FA807C2B6597DFEDE46865C4CA5C24D1E997C2A17E6E5C18C523C7831D9EA37F2E9187B6789DDC38771119EE31D9106\n\t8FF3E875E6361FB75E6FF66B75B8BC7EBD068631488010581D24C2CFC419A10CA804008C43179A0CF2B701B787E195108810\n\tBE05A984ADC1C8CDE659289B1108E480857EFD5E0F4428A77A8DC41E3F8147EFF399CDEA1D1F96814A010114464524118282\n\t10C81C3285708448810549090EF91B85C063547BEC2E821017C14204528850085023C6880103453C1022910408A70075CCD700985040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9FC6AB32200D\n\tA2C06798DFED950A4184F103834E804760C8FCEA4CB61FAD32B8E4B21F7B260C20A0C1A020814114012C205A7CE0F27E309E\n\t270340FC9CCC622443A635B8204CAB22321B0330227DAAD3062FDEA987E8BC2E627FB2D8470780ED0C5D19358C2230322C52\n\t2000000E602540A114A2000453E0850284508A510A1E05111000001042001009701080005D4104422201EBD9120A2FA2900F\n\t1001548A8D44A986052668A596886C8154461101258CA00887C82504A1C058D809988445F05220D8871B1D4241A0312482A3\n\t6004CA281603DD98374D081944C1E3DCAE5C2B020E043003D0686547AA00478648ED161811145488801320802A513092E02100585040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (44B48C66005E\n\t0FF60101FA7F50841BC98203318C322A13002FC6428C50F0218FD86C03505116FB5F23CD0F262B34688F0C20D488002B3D0E\n\t63053809EFA02045DA7407B7DF8DC6E10084FC1E834CCEB0BBA81E0E7F37DEA0D1F8FC785B2583DB0F2073CC90C9079EC9EF\n\t03EB7D8E7139845D8C31E90822914488070432D008104904281004844221E8911C04D1A1042021108D1E82448CD1A1FDAA77\n\t6ABDDFEFD3FB7DFEFD7F974AA5F6A985FEFF331E0EC050FBFDFE273B07954A37D9DD1EEA743F9BA43150317C3E21044CA863\n\t408410450809484114A8200421191C0A8A12634484CD013307CD340370B87359B3C68C02A844387C78101025C13B008E140100d85040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C8E49688C866\n\t2120008582247094E22C6023D060F62850A28523231403860005708E07008080C06801406213934AA576A96114C53A1D5108\n\t2548EDE0714A35C4ED05A128E0AB3D2B81418001E4720C06131E0317D110B64708915BC477A2C10A4C08214AA8620A4C00F0\n\t00130220078331983351200000A2F82810F11E8C1EACF061C024092A05940612D91420590296516436E884446200350E6050\n\t20548A54422212CCD41BF4EA5E319FD881D6D00808372C840241108A4510897129500284D1A144591E968D0A354301C42209\n\t845923F79A211428690DD880355128BE43149DCF8CF089312A2A10081ECFC0001D00CD01871E4A5042216203058612C400A200385040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (140A05028140\n\tA0502814552ABFDFE00002A954552ABFDFE00002A954552ABFDFE00002A954552ABFDFE00002A954FF7F954AAAA5500000FF\n\t7F954AAAA5500000FF7F954AAAA5500000FF7F954AAAA550000018002800400351552AAA150000000001542AAA1500000000\n\t0064486800AB404B405B016E8C558295E8A7D2A8E4AB0128154725D32938336C0306E03178099E04701B00030558A9166A10\n\tA00964220040123456120062A1432DE02C7F0C19E0F19BC1604F480A0480A40020E80210098804110A1530B03730C5E025F8\n\t21524B70108542150010068420034000E42A246808322BD564D5A3AD86B879A210450291750E0A52B9824C9279A028014A3100b85040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000C001804000278BC5E2F179B\n\tCDE05029148A05151A88020001001E4F0542A8000000001A8FB3B124AE3421AC8881223AA1945F2F97CBE5F2F97CBE5F2F97\n\tCBE5F2F97CBEF57ABD5EAF57ABD5EAF57ABD5EAF57ABD5EAA05028140A05028140A05028140A050281400A05028140A0502800785040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A28025BEA07A\n\tA205088141A9442A55AE9002A00000108A5729806A8050A1242A452AC540A7817D540A00281EAA07A8000000800B4D000C80\n\t000000006F555800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f85040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400088429512\n\tE950A22D238446044BA8542811288508B4108954A0142A1540A113209059112891C7E5205D542A741FCAA893F1514CDF219A\n\t90082752A05028552A054AA4508944485022054AA552A84098572A954AA05154522204168060044AE92669552B8D23319995\n\t2A951F20540AB551A8CA8155229F085142A900D645821847F2A8A448EA44888C28A252A14612152A8742A130A950A1452A95\n\t4A8552E934A251289D4FE3599452AA390ACB00F2D2BD54A0550A010080C0F04C0F670143CE16F17CA81544815007C6005560\n\tBC250080CF00B00044144D0088A481601506CF52BC4C64867864769450199D2E265A1C3E2121BFCAED43131002FF2AA9552F00045040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (525914A84402\n\t844A2160A0F05514A20143A41A28C4A62E255B40F2D00D14A25138944A14308894A010A68048A542A150A8542A054AA51221\n\t4408450A114284528850221C0A1108A4B2A0D02615269142A4A209D4A0400A914A65128952A841208C40F14269148A332894\n\t4A95410814AA7A80134A2052801EA014AA800FA4028952A844999442A52281AC8350088108A51289700A1426914AA3409854\n\t9A44AA8A00A7528100A254AA11266510A948A06B00C549A45268D02655108146A1EAB1448A532A0549A452294CA20B25104E\n\tA500815068452A94499541A04CAA210A5500E052A110A65128952A841208C40F402A914022A8A4529A510A914564283CAC9A00845040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2944AAA542A1\n\tFE5528B9954641E9615E28500A954A2151A944AA553A544BA512A954E9512E954265510956AA4128154AA6D2A974BE458652\n\tC96542891496522A154EA541092AAA5A2A954A2552A912EA5509954255539974A2153DD50AA1526954281526954AA4DA6172\n\tAD552A850424A88854A834A89540A450A9042274039543A71289D8EE791A94C194D28432AA1526554A8350B954D5341A1060\n\tA5118956AA56AA8148A5528954BA75228D4AA1328954EB151614AA050251449414254A4A22A2A8A8865089540D9158892CAA\n\t113B8E42A452A854A2601554A204528950A8541A9548D14194AADA079681C885416154BA4410852A854169503214161542A100445040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8140A20D0284\n\tC5554A8954AA4D2A154A2552A9742A532A084A51C2A9508920B59D480252AD40AA5628964A8540A934884A2CC54A255080CC\n\tAA5620D5022442AD4CA2242AD5698550A854A25522914A85A0A91CAA112984622450292A2241A80D489520A114A255358742\n\t051288508A512A154ED4002844A211220105514A61105634A0D2C0E152A004FF2AA95049B1E2E9148A45028405F32B588A78\n\t4E02946A27E2954AA0488D5F0A80296030680D189825552A20B646513A4222A6529452A230B650626502A9902A5428900883\n\t52A954A945281C0AA552A9D4C7551805208400891428148E8D400112214422611FCAA290D3985422002A104D8553E9F4624300c45040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (954A9502A57C\n\tA05522144AA421094CA8410A954A02C9BD04AA5522950AE4C2E5C88A34208A8AA542A94C4252A8134AA60A0D14AC05269528\n\t85530004A8351255CAA152A9948A552E9540A150A8D4AA4D12850AE6529932AA252AC14A8552A9042A5117D50B215200BEBA\n\t0008950A25508040A94120104A8412015020000E8101815281108A152A804B916288548A552A0548A552A0548A552A954AA5\n\t538954AA552ADD45A152A9542A550A954A2552A914AA542A9548211125542A4017D562A54208507E7C829005F15881140A11\n\t289508174A99CC9A1122554A6442A05002512A85AC2779D0D0A040A152CA8172D954292F28C8C3B6899076854528954AA41200245040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (7000062FD607\n\tC408C1808F20309707301A008E624D0D8800100100E0A211B3186F7781E954C77E1F106214C0C19E00183C000C23A32580FF\n\t4FBD49E013129592F703805506615275D46A2D265748E14A851C8C322A9CCEA5118820A8442204C22572A9362654BA820FC2\n\tAA9590A6550A954AA1498842AE5C08944B65326054A6452A894AE55048221110A8944D9241A934AB4CAE544AA512A9D4AA71\n\t0A9006A550858CD54AA6CDA3D340F5108A211551428552A144EA149A950A1542A93299411F9022A512815416412B90002550\n\t29740A0DAA8548A2F821749A04048D4AA55209108A550E8B85515220BCC904860B46275261AA14441694AAA40A2154AA409400a45040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (EFF7FBFDFE55\n\t2A954AA552A954AAAA552A954AA552A954000000000000000000FF7FBFDFEFF7FBFDFE552A954AA552A954AAAA552A954AA5\n\t52A9540000000000000000000864A65209C048000000000000000000000000000A880550AADC58C600001040005B097E247E\n\tB3DEE8F7DBFC26FD19979FC736A93C08112601022010380D08003017004107C0FD9A7F43235C4437000C18424D88008A10A3\n\tF5FEF47E8419A0F08BC1200E240B0248B52A21FC6114878040301A30F6A806B281E211FA1190081D08814A01420110BC0108\n\tC040016151708B502BD100050321C08864220E4C26133D600A3E03D64841082060A0780FC180B39A381C2001225402A5000800645040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000F001BC1E2F128948A65329148A2512894CA45028148A4502814\n\t140A001000000000000F8383B1000E3461A28E0C26028416FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA8\n\t00FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF2AAA800FF7FBFDF00e45040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (108506014013\n\t8004480289002F042B8808C0280C1004028154AA5502954AA552A8000000800B4D001C80000000006FDA5500000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000145040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800800006020\n\t080120635840834281C88CC660CC6620640F0608201B0840C230154AA555402CAA552A92018364020DC6A30000DC0003C381\n\t1803038CDA0254880986020000092A400154AACC618A1FC7C218605CA60480000CC660004022600F106662C859801430870A\n\t2D561280AE554095080552A95586801C33118101800C0CCC60000CAC061A0002041C10042034A090080E0603000A903001E0\n\t002E204AA552A815000C2215C827265A84A6000B8C588400A2046821389D048117980C3821581C4E064020D03C2128054305\n\t370B08E0462C26082A32402184514284042150B01C844C6100400216001002552A95504843800000552A954081410220081000945040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A04E08006040\n\t20000081080552A9C4204E0601000050A914684522010C01430904824120804A840228448A710A14428510A114A264290542\n\t6200810426906801048042A05482550E21060010293480412005482C5610102834008149A4020900AA042AB3010050091588\n\t4C28040A044061308041180080A012A114A80123844A8040291400C5618102E0909941A0080A010A05522154784C20104600\n\t202804A8452A3C580040A010465008100AA440A81C02302090580040A0D00205009506A412A93040130A01098402088CA010\n\t2015426546288C620202A348041200D484051A288E0002A9558420062580A881E155CA94083808055089902A81003542E80000545040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (548A0401A501\n\t29948025302404B1130604C09012C24C080688904AF4008041268482410000008234220000241060606009098928213100AA\n\t4104800C09812024C48210220128204B44489A481542A96328558C100384508400884822020001588402AB1510030003C000\n\t85302444210938808041116802220500480884212110826809830034022010422A804020142A200000010018A3C04A807080\n\t41130900322A98340103970AA0527954985529950AA4D28850A23112354AA5D0094528A9231111E0000801801C20954AA450\n\t801082A10090010302385400442A9558E50039454C971C100AAA10090006500A94D4CEB2215036C52883022D10400CA0552A00d45040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018C81820040\n\tD000380805570800603018154820C40000100C01880180841800403304081808000140184C238C4400C44000102041800042\n\t0150001088050C000080430000C26602100C040030AAC50F05C363001B0C600C2815420530683586300600C085520355BA1D\n\t0A1DC0E552A928EE02101542AC40886002552A8546A0045910EC340400180A0010000823311D0180C0194008CF06140AA550\n\tA82D862269A3080552A8D40860480619AC01814082CC06150AA150E01064C0201550070209101010111410A283524880851A\n\t100AA00000000000081440A212A048B0D020154AA5544221800C00201042200000141A1120100202310C00202C22000522A900345040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A0957281802\n\tB241548696328F406430C044A6344183458944B00082402A834381C29154021840854BA1108A1CC2002E39822DC0214D0044\n\t06101A074298403845081C4A031429CC00C142900F098329642E65131541A20009D0AA1500B14005C00330A0421880C6A421\n\t8B4020122801008050A1406202021040E11620601C12070481C12070481C12070601C1807200300E20000D000682A1100200\n\t04134D26C04914A61A2D908420810420042215482100010022552881088550894048050603C0003100004000780C100001E0\n\tC1600C06080002F7000046030783060B00000C46800400D840803B3180340820006010087418CC781000833002301803110000b45040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (885603D4AA6D\n\t3A955825D22331A6510E914EA512EB54AA5D2A05D8A712B854AAC72E97C7E712A11CEEF537BE58EF77BBC0480060100D2A61\n\t483180640C988D40A0011862B351B98000C26131E6416180D98F00008000580386066542A9558248088001A000020C1E3111\n\t000084012008022418214E04812371BA9D0000D82400804042120400006210A83108400200C08110000006C060800A0552A8\n\t546630219542AF37020C1E2E60000060C6183018042A15462E14224C38540E02C2EEF161C058703111082102A9F42A0362B3\n\t07084660C8661E1902CA855288CC04305838C100C2A814A019199C150CC1904C54B30009400582D8092C0C4204C1C840990800745040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (72391C8E4D86\n\tC361B0271389C4E8D46A351AD86C361B072391C8E48D46A351A271389C4ED86C361B072391C8E48D46A351A271389C4E143F\n\tBD546021F8000000402A8540040001000040200544000B54A8541995C2A5C2A910AAF97B1FDF2C72ABF44EFE28B5DEADF708\n\t1C52425A94054D42C354145456800AA2B6B9FDAC1F6F908EEF03B815E24F1ABFD88572EAD8D4D94A8952C5631294CAD13A04\n\t4BA4C2F951B8D70B9F5A2D128B1DEE756A91C8A110A9143E4E46B448A530A134AE7468974A2452B95DAA8566954AED73E95C\n\tE27D3B935A2753ABDCFE5533B75A2436F3503AF74EBF5AADD489FCEE136B915B81D2E975BC5422968AAD925874EE5766974A00f45040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000C01FA8544A25128944A25128944A25028144A25128944A25128944A20000000000000018C76885D\n\tFA512A9F5A8512795C88C964B2592633198CC69C4E27138361B0D86CC964B2592633198CC69C4E27138361B0D86CC964B259\n\t2633198CC69C4E27138361B0D86CC964B2592633198CC69C4E27138361B0D86C72391C8E4D86C361B0271389C4E8D46A351A000c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (030080C00018\n\t00000000000000000000000000000000800B4D000280000000006F0CA9000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1000AC8608C0\n\tE814081E406004005848031000000005512000000002000324020DC020020004000043810053038C0009C3DA85CE0027125C\n\t64E0D00000C0001618070282D440794BB9840000000440D0001C1005D6B854001430870A2150628000004000408000000006\n\t401CB00000018800000C000040AC40100000402400008042A05008000013108A801001C00000200000000001001C2200CA06\n\t061845C4600B089984112164CA553A9D4A821712083201181C8E0C446094385528854229362B10E244288440083209018055\n\t00040AA400A059804C4C004000540020260000000A4153B000000000000800051220008010100608101201422828080A0B60004c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C0820C061000\n\t4120500870830082000084020100804004050844100104300408010200420840A000800864010240C603603600050000001C\n\t00060206236002301A00028001CC06236000301B001180D00014003800331B0000AA01848C069400228062301A00188D8005\n\t00020004004190000D800200C0C068360000C3180D80D800100020014000188C068006236001400080013C180D800040C603\n\t0001400280005CA2301B00182D8000C06C0028000000E00070206301841180D0018C060002801C000600806836002301A000\n\t28001C400019810100000022002815002980400140800A39008000A004080008A000445068008E006811092140000840800000cc5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4E04A1027944\n\tE03822860017B9F1AA944B0803C4A051C42A962486428164A04460010A2214E284E01800212812080204F2898029040094E0\n\t053B00887047804604D0E001A2403184480410C0542214092158A04003001003220380050411400C64223182050331088866\n\t2910408194900432166211C0003188CCE6010013020114000188102A84D80386B89CC21203064A80722A18040D3300000000\n\t7800180001800000C0000000301030000000015928A12211018014F87D800C02000001000001002460204883201800000000\n\t0018004039450C801801000A06820406080014D0CC82215000094804022110091C00000020068000E02060C5000200000000002c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (603038000085\n\tC0B9C0220D6B854B805239B4027710911861503804900E019C18A4C289D1A2050B9D468050E86CA841639D9A20528B1C2089\n\t6E1D00AC62A07800C02698C263105B4C600C0880010030603186340610D080002301980C011DC2E0000100EE022400000C02\n\t202020000000060050184062310681580A11A81000030A9D4184C29900000F2601000000015D8610610300800000C088042A\n\t25598C03A040800C0E00400000E81062F10000180306084028042A0048834441F07E00108040004000000004000000000000\n\t0004E0020000000000518C1C0020104541201014020120000210204C00002A1000E04000000044038014E700509C449E513100ac5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (6D20C044BE35\n\t0B83C50C0001408E04000F098080100088112884C32110894CA0000430088CC2210020400F00120300391C1A11081C088700\n\t81D808902894062750E01C2865131540254208C0000008300220C2033002081801C6008180042A0008100020000004605002\n\t81084116292D504B741697A5A5E9697A5A5E939504E140D89CA842005600570278C24B2C98164B4580D9242C16AB11A00300\n\t4448400000060042601040000210000000000490402E97C1247500016034700C100481E8E0C00C06080AC4F5181426430702\n\t4406002048EC00220090C0407265227904855341003030388E7014092A62687010DA00100D083500D480E240B04080060044006c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A21502950225\n\t50085480500A914A2550A954A2442A800A21400940025002900AA51021500060041608A0F14420D83BB25C20D0A03C60B731\n\tA10004806235C64541A5D9AE00408046C029150C600000010034220083221030081C750000038500400006083805160180AB\n\tB1DC6E008D900C0180318840000446420061F4A60306169B204000000C847105018000000066340300000E35034C1C4A6200\n\t42E1C49870BA0D00000E0D020A0C90000E0102EEC3C1C020703001082102A8C40042603304815450C8EE5D149280000001DC\n\t22705A39C220C00040000C1B9D4E8CF3984DBAF322000020C05801865C2A95C9A1021810200017080824B06001A2710E0C0000ec5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A003FCAA557F\n\t80154557F80154557F80154557F80154FF2AAA800FF2AAA800FF2AAA800FF2AAA800285502940AA000000000000000000000\n\t005000140000000002A000AA002A904A8052085428012001480550010000102A804A005201502244020540215001140A500A\n\t0042805000100050229500250088142A5528004AA142A8542840081040211281408A540A0548A5520044A215089048211229\n\t10A851228542255221548A5528854A2542211488410A8040A55209508A542A9548A542A944A85522144A2510A1140A552894\n\t48A552A050A254209148A51288542241229502A550A95428442A9442A440A144880502950AA41289502A4408910080500140001c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000D001A8D\n\t40A05028140A05028140A05028140A05028140A05028140A00100000000000140AA010294000012A050A2052A9005F50029E\n\tA5F50029EA5F50029EA5F50029EAF505280BEF505280BEF505280BEF505280BE0A7A97D400A7A97D400A7A97D400A7A97D40\n\tA02FBD414A02FBD414A02FBD414A02FBD4140055155FE0055155FE0055155FE0055155FEAA003FCAAAA003FCAAAA003FCAAA009c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A954AA55000\n\t0000800B4D001280000000006FC0690000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000C0B452A95\n\t4AA0024154AA5528944380002D9008050200002403284053078C040B66CA85F6037B329DEFE452A954C00014984737D23D64\n\tFF57BB85E221102900FF140C8407F6F85C003C7F8DDE63F0102150AA152A140AA552A8468259389448059021442C0129C5EC\n\t21020810E2603A51E9C3F071782010170460204001D02A5102950AA550A812DE2ABFDA6FF7FB5DE4BF3EBC9EE1C388707804\n\t7BBF01E275FBF86C3779BF1FE3F7F9F99E441C001FAF37BBCDF81166910AAF36A9319EF36290008555F279E6CF3780C00336\n\t18DD1AAA552A9A6DF6580000AA552A8542A040884420452A864280000006824D22834FC0032954C834A191022542A954AA4500dc5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800020402010\n\t08040A0000A10200403001020040841080100051AA9060800021962B613C914205522918AA4708170BC110B15E085122918E\n\tA703C914B05E08858AF04288543255339E42245889D02C17AC85082470B15E20582F0442855089500A1188854F21108100EA\n\t743C9100C658AD84F245281502A412A91C2C5788160BC110A15422543E994F205009962B412885482553FC72B05E22184F24\n\t52E17822152A9148C553F87CCB4580058AF0432C5682512A990A87522160BC410B15E0851229182A45321148A552A8000F48\n\t1F48620012A8142A1930140AA3E2895800500A950B0373E9FE8079309167F508A10428052A154E0782C0F80A022E18042320003c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (408241280782\n\t8780FC1882440200002420C160411F0A11E821E28154837933DC0A01E02984C3180A01E0A07B05C0F007AA074FF5F83DF6F2\n\t078CD98CF198FC66BE1D03D98A0553281023670B80408410A084200230810001130804220108C0008400001082642B802817\n\t9BFD7EA755229148345341FE305F2A9D4BA57A89D6DA37318F83F669FC7AC707A89540207800180001800000C0000000B000\n\t30150A2453C178FB6733198752DAF5D00E512A954020000000007002C00B04180000A8552A9D0AA07BCDDCE81D2815488700\n\t2C16A8553CDDCEC663F110031C201763B1400D44AA5502064841F229542C0000150AA550E910AE573084480400016423002800bc5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (CAC758AD46BF\n\t78341D6F357AA1D08A55BE9F83E27ABDFE9163ABD7EBC7F8A850EF5FBE97CAC7E3A80C6B773D982C26722954CA1632C46320\n\t1B0C600C5D2A940AB0F03986300620C1CAA51389982C540CD06AA550886600502A854E8170B914AA553A8743321A6562BF41\n\t2B194530B09C00A31D2E5B8CE31B04002F3F2A554AA552FDBEB062A3144AA550C8C6C22603598ED3E005802C2F2A954AA1E0\n\t30E6F7052A854B261BF0A81718AA19C0C003D12A6A11AA154A01522000A215299348A1400140CA502A954AA143F1962C0020\n\t104D01F80014020120000212617C00006C2F814A7552A9140E118A81EF21023D403C05331E0E0500F014C3780C060287FAF1007c5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A0553F9FC325\n\t52A9DC1C618CC7E3319A0CC63F07A3570C802BE180447F9CDA6F03F8DD3E1E181C0B4F9621FC10F061BE9E6FC7FBFC78EF17\n\t3FDC6F305AE954AA4532976AE5133950A21D08C74A21D0A07EA25DBA1062A542A0643007A8854336617DAA5F6A9FDFE7D3F9\n\tFDFE7D7F975AA5D6AACCFEBF130F85C84643FDFA2B3180974B27DAD914AE762F95A820530D5C0C452A954A84428444AA550A\n\t914AA552A1102A7E1FD2A21192840442753E99CC35FAD8C48C5F3CDE85F2A8843E33660010462563F81848638C0028002004\n\t18F033BCCBE12102B83CFE61A207C0076BF978DA09B00FECF2BBF4A0CA57A8144AA7128080385D2A954FE652BCD8AA5FAC9F00fc5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (26B8DDF4080D\n\t3F800F01E10180A4252A49462532C15800601007A1D7D9353E7A5B10C8C0B12214727B4DA0480005E23D86030197D88C01D2\n\t81C6EB6500006AA552A804BD770C180C3062C01C00080105C081C0440A1818949608C18BB1DCEE018DC045128890AC600288\n\t82AA2571FD3281773FCFE260000018045029954AA552A866B0502A854CB0326DD8E17F200468E058B0588E542A9F4FB778AC\n\t44A81E2207ECC113C060F860A319E3B7FACD54A8753B1DCAF000D066B30004154AA570DC60301831D384C5532950AA7F805F\n\tCCF7BA4DFEF33082804A251830543E72A7C1E2F5DA8914320728C86E3542A992FF7F9CC96B8190CC1E737DA3C00E854389D400025040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000030551A942AA2B1552AAA150000000001542AAA1500000000009408850817\n\tCB27C32A05C0A0532A9524A002A5F4AB310294C9A5B22940225A02050820D20512285C0D0042A49AA97E2A13120128202091\n\tD6F834A151ECE063D9FED86088D980261000C0A264084FC886C20044221B08D249301A391A084C811C8114811C088804B49D\n\t2525C12C8A704085CC240272C86E054200D18B805030C0862021844E7760994CB22700864050633076AA1C0C9609B618D800\n\t0207224001109B01D600058B04422060E1D4CC06298583621080684A061AD16CA01010008207939FA537F88430E24A0FC08600825040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000030018080000000000000000000000000000\n\t00000000000000000000000000000000000C0181100C64222CA00000224A880EC9318D938364E324C69C1B18D926364A706C\n\tC9318D938364E324C69C1B18D926364A706CC9318D938364E324C69C1B18D926364A706CC9318D938364E324C69C1B18D926\n\t364A706C0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000425040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000006F3C\n\t3000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c25040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (900300002D90\n\t08250200002003084053058C0002851009D6025428514A80000000C0001498471550A824A6152210A000001400A5152C8406\n\tA4D058002845089442A150280000042A0000000000464018B09040059801842C000284ACC1120060824020854284A2904802\n\t00171320000001D0000100000000008024AC5500D4080618B982807580580717B984F2595D2E5501E200045C0E182CD60C80\n\t23283899348544423653116477513B5EE035F20180A60798154BF34AA4008C70008000660030060000001442A4C000000000\n\t00050800408844064420960020020004025020840A80032954C8552291002000000000000000000000000000800B4D000A8000225040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (403841021040\n\t841080108201000968A050A1160A7028804280020010004608974A8000B854800120010C06C28804B8540005C2A400080022\n\t00331440005081802C052800002260B05480592A0002A0008000001180000A20008900C06A288000A45829C0A2012A000000\n\t1000982C1520164A8000A80020003C18AA2010A1160A500080002002AD54B81410182A2012D15000148010008002B0548B01\n\t0A0582A4022C14A00100110006022170A8000B854800120010004022000000000044A9282A89410008000002103000400550\n\tA490825500000A0552A954807120914AA4100114205028054C0693F0E825132BC84633A0A00C06040000000002800000000800a25040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (02A52088E049\n\t152A154AA540080002542A944A0552A904AA140A9540A5528550A01500840AA150A944A005089108A110A844AA1502990000\n\t0300541B5483500A24526894AA5232840A85528910AA51209102A5420854AA722644442512A9542A00221000250289542A55\n\t2A980BA5528954A245229502A452A8548A05000000047AA918AA51AA1548E510A144B2043A800000428150AA4522178AA550\n\tA9802C0080000204108010884C0091033258A9002000001800805A8954801C00000484C00906080028D54E8442A110021420\n\t1542A1402C0000000A072A657005348A000004000000C08C0E072800060400816423112880082040201008040A0000A1022000625040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (2A11AC1502E4\n\t52A954A245AA954A8550A850AA552E954A8543A814AA772A904C24502800E04F29C343141B8C600C15000000316031C63806\n\t20C140000321DC0E002EC16000026576025000100C00402000000010060195FB88747A47A999451128640053579D8BE4E69A\n\t84002F570280000001ADAE60729300200000E0B481340A5FCE57A285002C5700800001602164EA040015432412A1502A5500\n\t11028552A854801108000A81522110690302140004008000C20000000004A2A98C8E552A954A8552B954B20522814A92215C\n\t0000522A80C0A0000000084D80954A0052A944AA5522940AA502A954A2502A8502A552F954A95528154AA552A854AA250A8500e25040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (21121D442A0D\n\t2695088052A100885528944B0550A9542A102C154AA44AA810A0412A964A8552A850AA152A944A0010C0000000381440C503\n\tB0002A5800C602A1800054021028014200000070A2050A004226428854AA552A054AA552A054AA552A954AA5528954AA150A\n\t8D489642A9542A5100954A2558A914AA742A9140201209340800000400844008500004000000000001140056AB8544211288\n\t2496752E914925D2B9448C57289402E5781C5663468152CA256288B280650848C0406958A2B15528954220023058AE6B220D\n\t455552B950AA11201548A552A940CA55280040074168C0BA5D00050AC452A950AA55A895CA8558A944BB52285D4A2550015000125040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (47BC89E0A491\n\t21680060300D66A5526D50AA55349B40A1422876B753969089416139D6AA55AADD4EA55A8944C650AAC5600000015029442A\n\t15482541881AAA108213CA4120881424592A0E02815371BA9D512A910A25102150810508854A0061A94402472A9540800281\n\t9404302A814000000166B80000000CB1316CD8926D228366E158A0508A0000160E64D20D04021621056CC512C840B8510211\n\t422550C900A860378B25A452D9766A150680000022DC3C301C31CAC8C0010010085D959548A5D2AD54A24118004000182804\n\tAC4D1AD5C9A3380440284718884931400102AA552C916A811089567A538380080412895400002B150220100190284108854200925040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000003864A25209C040000000000000000000000000000A080550A9BC187C0083C703C7121074E07AAFDE6CF143F5\n\tBEFD51895EE3F6E13C80100A01000C149B00802406030060B6A3FDA23F0081000A10004918347A90186B01EB51FE506180DF\n\t80160000007102020024E4C210421C133094280102081407410007E027E020508E40000600160010660850330400A0100860\n\t00368AC40880208040EF0123C4623100BD1AC321280468C1188010520520910A810229003111228100000320708424088586\n\tC4002C4438010D860086088DF8570E2A0880A00900022313B357873778A53812460ED1E13100FDF2026C3B800E21832902F400525040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000180800000000000000000000000000000000000000000000000000000000\n\t0000000C09E1188C642024380408062BA88A78438B5A4D216A1CF0873C3485A2D691E10E873C3485A2D691E10E78438B5A4D\n\t216A1CF02D691E10E873C3485AD216A1CF078438B5A4D216A1CF078438B5A42D691E10E873C3485A00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d25040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000325040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000800B4D001A80000000006F1DFF0000000000000000b25040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000725040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f25040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aa5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000800B4D000680000000006FC289000000000000000000000000000000000000000000006a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000da5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007a5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000800B4D001680000000006FFE6C000000000000000000000000000000000000000000000000000000000000000000000000fa5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000065040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000865040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000465040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c65040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000265040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a65040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000665040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e65040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000800B4D000E80000000006FD8\n\t300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000165040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000965040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000565040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d65040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000365040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b65040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000765040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f65040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000800B4D001E80000000006FED4200000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ce5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000800B4D000180000000006FCB1E000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000be5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000015040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000815040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000415040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800B4D00\n\t1180000000006F01540000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c15040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000215040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a15040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000615040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e15040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000115040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000915040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000515040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d15040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000800B4D000980000000006F27080000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000315040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b15040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000715040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f15040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000095040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000895040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000495040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c95040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000295040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000800B4D001980000000006F127A00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a95040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000695040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e95040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000195040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000995040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000595040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d95040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000395040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b95040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000800B4D000580000000006F3426000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000795040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f95040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000055040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000855040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000455040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c55040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000255040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a55040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000655040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000800B4D00158000000000\n\t6F08C30000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e55040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000155040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000955040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000555040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d55040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000355040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b55040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000755040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f55040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000800B4D000D80000000006F2E9F0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ad5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ed5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000800B4D001D80000000006F1BED00000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dd5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bd5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007d5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd5040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000035040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000835040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 1624 TDI (FFFFFFFF0000007A3DB1000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000435040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSIR\t8\tTDI\t(FF);\nRUNTEST IDLE    100 TCK;\n\nSIR\t8\tTDI\t(26);\nRUNTEST IDLE    2 TCK   2.00E-03 SEC;\n\nSIR\t8\tTDI\t(FF);\nRUNTEST IDLE    2 TCK   1.00E-03 SEC;\n\nSIR\t8\tTDI\t(79);\nSDR\t24\tTDI\t(000000);\nRUNTEST IDLE    2 TCK   1.00E-01 SEC;\n\n//END\r\n"
  },
  {
    "path": "demo/uart_tx_9600_flash.svf",
    "content": "//ULX2S / ULX3S JTAG programmer v 3.0.92 (built Sep 19 2020 14:37:22)\n//START\r\nSTATE IDLE;\nSTATE RESET;\nSTATE IDLE;\n\nSIR\t8\tTDI\t(E0);\nSDR\t32\tTDI\t(00000000)\n\tTDO\t(41111043)\n\tMASK\t(FFFFFFFF);\n\nSIR\t8\tTDI\t(1C);\nSDR\t510\tTDI\t(3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);\n\nSIR\t8\tTDI\t(C6);\nSDR\t8\tTDI\t(00);\nRUNTEST IDLE    2 TCK;\n\nSIR\t8\tTDI\t(0e);\nSDR\t8\tTDI\t(01);\nRUNTEST IDLE\t32 TCK 1.00E-01 SEC;\n\nSIR\t8\tTDI\t(3C);\nSDR\t32\tTDI\t(00000000)\n\tTDO\t(00000000)\n\tMASK\t(0000B000);\n\nSTATE RESET;\nSTATE IDLE;\nSIR\t8\tTDI(FF);\nRUNTEST IDLE\t32 TCK;\nSIR\t8\tTDI(3A);\nSDR\t16\tTDI(68FE);\nRUNTEST IDLE\t32 TCK;\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000001B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000801B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000401B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000c01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000201B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000a01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000601B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000e01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000101B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(20);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF2B8D000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000051B889410000006200000002000000\n\t44C208888200000047000000DCFFFFFFFFCDBDFFFFFF008C1CCC82E24282C26CB462AC4CB4AAACA26232045C2E4E860A00FF00000040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000800040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000400040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000200040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000a00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000e00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000100040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000900040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000d00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000700040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000880040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000480040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000280040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000a80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000680040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000e80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FFD3590000000000000000000000000000000000000010000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000180040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000980040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000580040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000d80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000380040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000b80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF21790000000000000000000000000000000000000800000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000780040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF21790000000000000000000000\n\t0000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000080040\n\t0800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF20E4000000000000000000000000200000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000040040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF88920000000000000000000000000008000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFF8FD0000000000000000000018\n\t0000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF80CF00000000000000000000100000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF28460000000000000000840040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF4CD3000000000000400000000000000800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF82BA000000000000200000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000440040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800001800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFF0A00000000000000000000008000010000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF50DE0000000000000000000010\n\t0000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000c40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF527600000000000000000002100000180000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF98D700000000000000000000100000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF788F000000000100040000015800041800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF38A900000000000000000000240040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF2DBC000000000000000000041800001800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF38B80000000000000400000018000018000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF7F3D0000000001000000000138\n\t000218000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004018000000\n\t0008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF3D2100000000000040000000180020180000000008000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFF8FD00000000000000000000180000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFF8FD00000000000000000000180000180000000000000000000000000000000000000000000000640040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF98F5000000000000008000001800001800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF217C000000000000000200001800001800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF74A30000000000004000000018000818000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF59E1000000000000000000001800e40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFC88E0000000000000000010000000018000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF408100000000000001000100000008180000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF3B8F00000000000000040100000000\n\t180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000140040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFC88E000000000000000001000000001800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFC3B6000000000000000021020000001800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFC88E000000000000000001000000001800000000000000000000000000000000000000000000000000940040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFC88E0000000000000000010000000018000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFC88E0000000000000000010000000018000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF588300000000000000000000000000180000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFFF1A0000000000060000200000000000540040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF208900000000000000000180000000180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF1DCF000000000000000001040000001800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFC88E000000000000000001000000001800\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF55D00000000000000000010400000818000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFC36C0000000000020102000000002018000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF7BD40000000000000000538800001218000000000000000000000000000000000000000000000000000000340040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF161900000000000200016308000020000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF14B300000000000000400890400000180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF269B000000000000008001400000020000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000b40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FFE574000000000000000001280000251000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF1A2D0000000000000020010200000018000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF7EB80000000000000004A08820004008000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000740040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFB63A00000000040000040001000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF68E400000000000000000000000008600000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF765100000000020000000084C00000080000000000000000000000000000000000000000000000000000000000f40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tA9170000000000002000001440000AA000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFC035000000000000000000008000020000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF2E620000000000004000000000000AA0000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF10CB0000000002000000001440001100000000000c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF8C5A0000000000018000000400000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFCC6200000000020000020010000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF474100000000000080000003200000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t090F000000000000800000144000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF59CD000000000018000000004000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFABA6000000000000C004004000004000000000000000000000000000000000000000000000000000000000000000004c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFCC1A\n\t0000000000018000001000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF4D0F0000000000018000000440000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF591B00000000000180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF5D2F000000000001A002002420002000000000000000cc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FFF89B00000000000180002200000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t997C000000000001800008000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF591B000000000001800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF35C2\n\t0000000000018000800000000AA0000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF9F7A0000000000018000800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF2F8D0000000000018002D40000000AA0000000000000000000000000000000000000000000000000000000000000000000ac0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF99290000\n\t0000000180000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFF3A30000000000018000000000000AA00000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t3964000000000001800000000000200000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF5627000000000001800254000000154000000000000000006c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF919A000000000001000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B\n\t0000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF9CF10000000000010001300000004000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9F210000\n\t0000015580180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF8B1100000000000180180180000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t53030000000000AB800000000000000000000000000000000000000000000000000000000000000000000000000000000000001c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8B1100000000\n\t0001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF81090000000000AB801801800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8B11\n\t0000000000018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF81090000000000AB8018018000000000000000000000000000009c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF8B110000000000018018018000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB8EE0000\n\t00000001801C0180000040000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF8B1100000000000180180180000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF005c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5E1400000000\n\t0000041A01840000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF526F000000000000001801800000400000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8B11\n\t000000000001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000dc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000010400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF23D30000000000000408011000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF87100000\n\t0000000180080180000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF6D9100000000000180080188000000000000000000000000000000003c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF26660000000000A29080C680000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC80900000000\n\t0011880020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF69F1000000000001824010000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF05D700bc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA12B000000000155\n\t9159558000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF5A440000000000A28428888000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80DE0000\n\t0000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000080040\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF432100000000\n\t00A28A88AA800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF1C8800000000001001100000000000000000000000000000000000000000fc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF87BE000000000200800800000800800800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEAE3000000000200\n\t0000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF8EA40000000000004000002000002000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF389E000000020040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF47C70000000000008008\n\t0000080080080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF4DC0000000000001C01800001801C0180000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9D5700000000\n\t000020100000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000820040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF9D5A000000000001C00000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE1C6000000000000\n\t8000000008008008000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFED74000000000000000000600001001000000000000000000000000000000000420040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF05DD0000000000018018000810018618000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFE4D70000000000000018\n\t0040100180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFCF1400000000000000110010100180180000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B0000000000c20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF4FE200000000010840188010\n\t1801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF969E000000000000001880001801801800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF293A000000000001\n\t801800211041901800000000000000000000000000000000000000000000000000000000000000000000000000000000000000220040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (901800011801\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFE93D000000000101801800001801A018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF939D000000000001A019\n\t0040180180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF926F000000000011801800511841B018000000000000000000000000000000000000a20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF785F000000000001901C8001180180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFD60000000000000180180030\n\t1801A01800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF0330000000000001A019640C7A01801800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4D3F00000000000100620040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFAA97000000000001E00AC0099801\n\t9818000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF0C66000000000001801804041C01A018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF7DFE0000000000018018\n\t28201841A018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018010018008\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFF747000000000001A01801C0180180080000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF783C00000000000180191190\n\t1001A00800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF34E4000000000001801801A0182180080000000000000000000000000000000000000000120040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FFF693000000000001981001801801A01800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF2104000000000201A01001C01001\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF97740000000000018010018018018018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF814E000000000001801800920040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF3120000000000001801801801001A018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF3D7400000000000180080180180180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF9D5F000000000001801001A0\n\t100180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000520040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (11418D180000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF0779000000000001801000801801801800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF48DF000000000000001801801001\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF3CA3000000000000001801C00801801800000000000000000000000000000000000000000000d20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FFD37A0000000000018004200400201200000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFF01800000000000000180402C0010010\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF26E4000000000200341A20B2420120100000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF42B4000000000401C09002A100320040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF2FC00000000002002A800038120020000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFDB0B000000000000940840000080808800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF3CB5000000000001800102002050\n\t090000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF5CE60000000002004C40012212002000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF10960000000000018218239418018018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF8B42000000000400D00900C04C50C888000000000000000000000000000000000000000000000000720040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF48100000000003442A840031415415400000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF494600000000040041020040000040000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF39810000000000A20080000880AA0AA000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF4ECD000000000208A00800A0480000f20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF02900000000000B21000000AA0AA0AA000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFDA390000000000080020000200000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF8BA20000000000A20220000AA0AA0AA0\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFEB5200000000010180180180180000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF28F100000000020024400120000020000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF96B5000000000010888800800800000000000000000000000000000000000000000000000000000000008a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF9AD1000000000081A01A00200200200000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF410D000000000000800810000804000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFE6F20000000000601800000180000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFB59F000000000000C00C00C00C004000004a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF17890000000000000018008410000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFF8FE00000000000100190000100400000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFD11400000000000180190004002004000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF1721000000000001045803881C40010000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFBE5D0000000000118118A8835812042000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF11A10000000000008018108018400400000000000000000000000000000000000000000000000000000000002a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF16C1000000000144841911A959543320000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFA1A30000000000A38898C18AB88A0920000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFA48600000000001088B84384180000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFD3290000000000B2085805A018C02800000000aa0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF967600000000000184380190580004400000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF22250000000000AA801889801CAA088000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FFAFE9000000000001841811801800040000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF612D0000000000108011138058000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF249F0000000000018018018318000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFF54D0000000000008890258298000000000000000000000000000000000000000000000000000000000000000000ea0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFCE\n\t520000000000B30AB8C80AB80000180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFF37900000000014C15591011380000180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF83FC000000000001001800001800001800000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF3ACE0000000000A38AB821881800000000000000001a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF5B88000000000001001800001A00201800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF15520000000000AB0AB88C0AB8000018000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF24940000000000000018420418000018000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA6\n\t56000000000001001800041C0040180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF2DBC00000000000B10180001180000180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF8257000000000001001824001800001800000000000000000000000000000000000000000000000000000000000000005a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF898200\n\t0000000001000000000000001800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF5D44000000000001000010001822001800100000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFF31E0000000000151000000318000018000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF83FC000000000001001800001800001800000000000000da0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF0BCC0000000000010019000800000010000800000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF6B\n\tCA00000000000100180000000000500000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFB37700000000000100009008004406380000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA10200\n\t00000000AA8A28000CE800090800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF2BC7000000000001011800040000050000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF133A000000000001801800000000002000000000000000000000000000000000000000000000000000000000000000000000ba0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFEA460000000000559558001158001558000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF96\n\t890000000000AA8B28000888000A280000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF4A0700000000010000000002000000000000000000000000007a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF801D00000000010001000000200000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF1CA600000000002A8A28000A88000AA800000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0DC8000000\n\t000000800800A008008000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF2A9A0000000000000000002000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB0\n\tF70000000002000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000060040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFE0CC000000000200800C00C00800A0000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC16A00\n\t0000000001801801001801800000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF61E800000000000100000100000020000000000000000000000000860040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFEA9B000000000000001800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC916000000\n\t000000001A012000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF1743000000000000000800800A008000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000460040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF35E10000000000\n\t08800001181A0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF68E900000000000094580180100100000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB90200\n\t000000001000180400100100000000000000000000000000000000000000000000000000000000000000000000000000000000c60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000180\n\t1901001A01800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFFE6B000000000001800001101801800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB3B4000000\n\t0000018C0003001A018000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF6EA8000000000000802101001801800000000000000000000000000000260040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF65430000000000119058011014018000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF913A0000000000\n\t0180180111180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF03C300000000000180180100980180000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB5A00000a60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFE72C00000000000180\n\tB803305801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF0074000000000201801805005801800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0C09000000\n\t000201891A01401801800000000000000000000000000000000000000000000000000000000000000000000000000000000000660040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010240001801\n\t8018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFC16A0000000000018018010018018000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF46710000000000\n\t31809C01401C0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF8560000000010001801801001A018000000000000000000000000000000000e60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF8EF400000000000000100180180180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF28F500000000000000\n\t1801801801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF440C000000000400009001A01801801800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD48300000000160040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF90FE000000000000001801\n\t801A018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF8EF40000000000000010018018018018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF28F50000000000\n\t000018018018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000960040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000010012\n\t0180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFEEDE00000000000000100180100180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFF0D400000000000000\n\t1801801201801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF8EF400000000000000100180180180180000000000000000000000000000000000560040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF48480000000000001008AD901D418C1800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF82F5000000000000000001\n\t8018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF44DE0000000000000008018010018018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB2D3000000000000d60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF511100000000000000190C0000\n\t4008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF137800000000006400100124288190180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFAED200000000002020\n\t1A01023A03A0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000360040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C10C40C20CA\n\t0800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFEE3F000000000000200402200220021000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF1C090000000000000008B0\n\t9808018008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF9FB1000000000400081800020102040000000000000000000000000000000000000000b60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FFDA61000000000100210A20A40A00A008000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF1D930000000002342002883012\n\t2900100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFF28200000000002200190388108180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFD4FD0000000000004000760040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF3BDA00000000040C3541202C031220\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF7797000000000200410040000400000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF83D30000000000000A2002\n\t00A082000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A00800800800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF32050000000004A80A22160AA0AA0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF830E0000000000C000020A0120\n\t2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFC2790000000000CA0A22804AA0AA00000000000000000000000000000000000000000000000e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFB8D9000000000400800C00C00C00C0080000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF193700000000000184180100180180\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF99B2000000000005208089000200000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFC421000000000200800820008e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF813A000000000210021A01200200200000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF6DA50000000000000408008208008008000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF7A580000000000100000001C00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (059418000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF900800000000000080990982304082100000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF156C00000000000004B84410100080\n\t1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF67980000000000000058A208002208000000000000000000000000000000000000000000000000ce0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFF0D00000000000018A201908B8AB8AB800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF7237000000000001810025001801C01800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFBBF30000000000008001010418018018000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFAD6B0000000000008000110458002e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF83820000000000019459551499559558000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF5DD70000000000018A388508D8AB8AB80000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFB97A00000000000180980100180180\n\t180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFF15A000000000001801801089801801800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF74DC0000000000018AB8AB0058ABCAB800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF0B2E0000000000018118410212008018000000000000000000000000000000000000000000000000006e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF6A180000000001238A38030018010818000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF8AAA0000000000018118510559138558000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF65AC00000000011180188110182180180000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFE293000000000001801801025C018000ee0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF7F020000000000C98A30A10AB02B8AA00000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFECC30000000000099441490CD101914000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF3B88000000000001801011001101800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFF22D00000000000180125100104D8000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF19590000000000AF8BB0070AB0018AA0000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF8AF100000000004381000300103384000000000000000000000000000000000000000000000000000000009e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFD20000000000000180100104100180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF6BD200000000000180140512100180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF3797000000000101801001001401C00000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF7EDD000000000001801081001081000000005e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF366E000000000100801005001001802000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF7EB5000000000001801023001201A000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFEDC00000000000018010010810018000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFDD2B00000000000000104404000104000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF9F9200000000000080100180180100000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF81070000000000008010011A1019824000000000000000000000000000000000000000000000000000000000003e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tB724000000000042080482140000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFDD020000000000060AA906800800800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF544A0000000000000010511550540000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF6860000000000130001900000080000000000000be0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF81D50000000001110004110011080000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE14B00000000011185584941515580000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF24C40000000000408AA82094A82280000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t5FDD000000000020000300200000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFC7AA000000000000080050154000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF5F7D80000000008A82AC028008AA800000000000000000000000000000000000000000000000000000000000000000fe0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF9323\n\t0000000000000000000010010010000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF7641000000000000800A008008008008000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000010040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF908A00000000000000000000000000100000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t62BD000000000000800A00C00800C00800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF88DE000000000001801A01801001801800000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000810040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFBA3D0000000000000000012010004000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF9F3C000000000000800C008008018008000000000000000000000000000000000000000000000000000000000000000000410040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF3F7C0000\n\t00040009A01801C0100180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFC15D00000000001180180180100180180000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t3509000000000101C01801801801801800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF334A00000000000100110180000180180000000000000000c10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FFA25E000000000001801C01801001801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75B9\n\t000000000401801801C014018018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF8301000000000101801881C010018018000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000210040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF42440000\n\t00000001901801A0120180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFA25E000000000001801C0180100180180000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t49A800000004040180180100100180180000000000000000000000000000000000000000000000000000000000000000000000a10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D55E00000000\n\t0005801801801001801800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF2FC5000000000201901801801203801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2585\n\t000000000201E01841E010058018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF515F000000000001801801801001801800000000000000000000610040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FFCB6C0000000000040012018018018000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF515F0000\n\t0000000180180180100180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFA27B00000000000180184180140180180000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00e10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF96EC00000000\n\t0000001001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF96EC000000000000001001801801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF65ED\n\t000000000000001401801801800000000000000000000000000000000000000000000000000000000000000000000000000000110040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000400\n\t0010018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFF6C60000000000000010018010018000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF96EC0000\n\t0000000000100180180180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF96EC0000000000000010018018018000000000000000000000000000910040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF96EC00000000000000100180180180000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF96EC00000000\n\t0000001001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF561D000000000400001001801801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF561D00510040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF6444000000000000\n\t1050C58099208400000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF55110000000000000010018018008000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF96EC0000\n\t000000000010018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000d10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000280000\n\t0002058200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF28B600000000000000000008200002000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAE2400000000\n\t00800A9021959021000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFBE930000000000D022921132320300000000000000000000000000000000310040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF6383000000000020420C00D4CD00800000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2E74000000000200\n\t20228A2040002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF5CC30000000000400409008008408000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD7D6000000b10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF0D0C000000000310308B\n\t24A9080080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF365C00000000024424420844020020000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF490D00000000\n\t000000188180182180000000000000000000000000000000000000000000000000000000000000000000000000000000000000710040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00AA0AA0AA42\n\t80AA0AA000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF3AE000000000035434C294450154154000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF77DB000000000000\n\t4004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFF3130000000000000000000020AA0AA000000000000000000000000000000000f10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FFE3E7000000000000800800A908000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF72790000000000AA0AA0\n\tAA1060AA0AA00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFAB2800000000000000002008200000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3A8C0000000000090040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF866F000000000400C00800C0\n\t0C00400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFDB27000000000001801805911000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9F2F000000000001\n\t200200041000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000890040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (009883800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF80A9000000000000001803A012002000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF0C7F0000000000018008\n\t8098880000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFA26A0000000004004007000000000000000000000000000000000000000000000000490040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF113900000000000180188380110000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF2AFC00000000000181180180\n\t18A0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF2111000000000001801801900040000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF54E100000000000000c90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF8FD70000000000018AB855807080\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFA589000000000001C018118410400000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFC33F0000000000018019\n\t4590900C0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000290040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018814100000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF7D2500000000000195595595510C20000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFC8060000000004018ABC8182\n\t90A2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF2B3A00000000000180180180100020000000000000000000000000000000000000000000a90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FFE3C3000000000001801201001040000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFFCC6000000000201801801801204\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFECE2000000000001CAB8AB8AB0C80000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF6E10000000000001801800690040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF74FA0000000000AB8AB8AB8810000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF014700000000000180100101500000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF9E0400000000000180180184\n\t100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF48A00000000000AA0AB8AB833000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF462F0000000001541559558C5000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFC7C4000000000000001801901000000000000000000000000000000000000000000000000000190040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FFD50E0000000000000018018C12000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFAFBE000000000000001C01A150002000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF87FB0000000000AA0AB8AB80100000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF97940000000000000018018100990040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF6E8100000001000004180180100000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF9E61000000000000001C85D01200400000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF4B45000000000000001901841000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000590040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF550E0000000000000018058010020000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF86EB0000000000000400800010000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFBECD0000000080000200000A10000000000000000000000000000000000000000000000000000000d90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF27D800000000000000980184000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF46BF00000000000004008000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFE0E5000000000000000000001800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF9D3400000000000000180180100400390040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFE3CA000000000000001000210000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF69F40000000000000A28A30008000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF03A70000000000000018099150000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF43B200000000020000900130100000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF1C190000000000001551550C500000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFDE330000000004000A28AA83280000000000000000000000000000000000000000000000000000000000790040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF991A000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF35B5000000000000008008040000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFD19E0000000000000000001140000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF0FFC8000000000000A28A2E00800000000f90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFA29500000000000000080140000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFD096000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF915B000000000000400A00200000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF7A96000000000000001801000000000000000000000000000000000000000000000000000000000000000000850040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF92910000000000000018018000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF50B000000000000020180180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE69A0000000000000008000000000000000000450040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF624B00000000008000190180010000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF5343000000000100201855800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFB39A000000000000000400000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF625A0000000000400019018001000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFE0A10000000001200000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF70540000000000000004540000000000000000000000000000000000000000000000000000000000000000000000250040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF54\n\tF0000000000000001C0188000800000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE95100000000000040180194001000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF93BD000000000100101801800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF521800000000000008180180000000000000000000a50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF9384000000100000201881810000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFA4C1000000000000001D418200000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF5F400000000000002019418000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000650040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBA\n\t34000000101801801C0180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFB68800000000000401980180000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF43E8000000000202001C0180000000000000000000000000000000000000000000000000000000000000000000000000e50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF313000\n\t0000021801801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF8931000000001801801801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF89310000000018018018018000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF4AF0000000001C01801881810000000000000000000000150040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF89310000000018018018018000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF35\n\t80000000021C01C0180180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF7A30000000001801801C0180000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000950040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5B3B00\n\t0000001801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF8B69000000001A01A01801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF3AB1000000001801801A01A00000000000000000000000000000000000000000000000000000000000000000000000000000550040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF9225000000\n\t241A03AC02000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFC512000000011821805F418100000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF49\n\t3A00000020180180180180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF4F2C0000004018018000004000000000000000000000000000d50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFEA1900000002000008180180000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF91A100\n\t0000000000001821808000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF4DBB000000009801000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000350040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3059000000\n\t400C00C00C008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF042A0000000000222422C00000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF7C\n\t150000000018008208010000000000000000000000000000000000000000000000000000000000000000000000000000000000b50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D20000000000\n\t000A20A200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFE623000000200A00A00A01A0000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF988D00\n\t0000001000210208000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF60EA00000000180184182100000000000000000000000000000000750040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFFFB50000000000000A20AA000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB1C9000000\n\t2002003543444000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF773A0000000004004104000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3F00f50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF37CA0000000008\n\t0081080180080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF3FD20000000000000A20A200000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80FC00\n\t0000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000040041040\n\t0000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFB742000000400C00C00804C00800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC148000000\n\t0018018018010018000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF9BDB0000000002002002100010000000000000000000000000000000008d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF1D860000000000001058018000800000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF1AA20000000000\n\t0800180580000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFA676000000000800800A0100000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC03E00004d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF5D4400000000180180\n\t3800801900000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF22C4000000001801800200001800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA2A1000000\n\t001001080001001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001C01809A00\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF15F40000000ABA118A20A20018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA1BF0000000019\n\t2B80001100180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF494700000000180180980180180000000000000000000000000000000000002d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FFCF55000000001805A1180180100000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFE98300000015595594\n\t5B54801000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF4E790000002AB8C18A3AAB801800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC03A00000000ad0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF1DF4000000001801C11810\n\t8010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF896E0000002018018018018010000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB43B0000000AB8\n\tAB8A3AA280100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018118010000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF28A40000000118018A38A38A900000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF0AB500000000B92B80\n\t1808801000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFB82500000014180181180180500000000000000000000000000000000000000000ed0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FFE4160000000C4049801800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFF5E60000000AA0AB8A38A3\n\t0AA0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF6B2C0000000001039559541540000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA3060000000000001d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF63160000000000018018010000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFA3DB00000000000180181100000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF55230000000AA0AB8A\n\tB8B30AA000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000100000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF6316000000000001801801000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF6316000000000001801801\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF2B1D0000004000898018010000000000000000000000000000000000000000000000005d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF36340000000000018218011000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF63160000000000018018010000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFE39C00000020000180000108000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF990B0000000000918000dd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF929100000000000000180180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF0935000000000001820001000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFC916000000000001800001\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF5D5B0000000000010001000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF7F2B0000000000AA8A38AA8000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF1A9E0000000000000098010000000000000000000000000000000000000000000000000000bd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF15C28000000006AA8A282A80000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF9D9B00000000000100100000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF0BAE000000000155955055800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFB33A0000000000AA8B28AA007d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFEC520000000000000081000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF40A700000000100000000000000100000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFADA3000000000800800A00A00A0080\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF2A9A00000000000000000020000000000000000000000000000000000000000000000000000000030040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF6435000000001800A00800800801800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFB39A000000000000000400000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFBBE8000000000800C00A008008008000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFC2D9000000001801801A01801C00830040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFA1B90000000818810400010010018000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFEA9B00000000000000180000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFEA9B00000000000000180000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000430040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFBBB5000000041C01821807801801800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFEB70000000001881811805801801800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF58CC000000001801800201801801800000000000000000000000000000000000000000000000000000c30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFC355000000041801801A418098018000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF2E2E0000000018018018058118018000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF4C6C000000001A0180012180180180000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF58C60000000818018082018018018000230040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF332600000000185986180180180180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFD84C000000001801801C01801801800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFED2C000000001801801881801801800000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF902B0000000318018018098018418000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFF2CC000000001801801A018018018000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF954E000000001801801801E018018000000000000000000000000000000000000000000000000000000000630040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF3002000000020001C0180181000180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF0A5E00000001000180181180002180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF62C1000000001801801A00801801800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFEBCB000000001841A0180180980180000000e30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF8913000000000001801801800001800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF89130000000000018018018000018000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF89130000000000018018018000018000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000130040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF496A00000000020180180180000180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF888B00000000000198180180000180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFBBD6000000000401A0180180040180000000000000000000000000000000000000000000000000000000000000930040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t2583000000000401800081800001800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFE752000000000001C00001800001800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF4B32000000000001A018018000018000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF75C7000000000001801901800401800000000000530040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF4E6C000000000289A802018A028B8000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFAF22000000010005A0590B80200180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF496A00000000020180180180000180000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t5E3D0000000000020418820C2004000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF8AE100000000000000190002008A000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF3C7B000000008081880001800001000000000000000000000000000000000000000000000000000000000000000000330040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF48C1\n\t0000000000418418218000018000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF05E2000000000400D02C888404048000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF3ACF00000020020930625820020000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF57E00000000000408008018000008000000000000000b30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FFE0880000000AA0000AA0000020AA00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tACC0000000200030A00A10940000800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF40E9000000200283200343210200000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000730040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFCE69\n\t0000000AA0AA0A20820AA0AA0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF89760000003540103442941521540000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF93D50000000004004000504000000000000000000000000000000000000000000000000000000000000000000000000000f30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFE8D20000\n\t0000020021000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF034200000000080000091480000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t69980000000AA0AA0B20200AA0AA000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFC5130000000000A4008020000000000000000000000000000b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF934B000000440400464400400400000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF1CCF\n\t000000400C00400C00C004000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFF3860000000018400098418000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8F330000\n\t000001000098D000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF19A400000004002000984000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tD77E000000000800002800800000000000000000000000000000000000000000000000000000000000000000000000000000004b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (515A00000000\n\t1800009801800088000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF37260000000018000098A9800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9AEC\n\t0000000019000000019E00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF1357000000001000000001000000000000000000000000000000cb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF5029000000001E000118018000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF487E0000\n\t000018AA0A20AB80000200000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF05B000000000180000000180004000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF002b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF416B00000000\n\t1800201801C00002000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF49EB000000001954145955800154000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF7272\n\t0000002018AA0ABAAB8004A8000000000000000000000000000000000000000000000000000000000000000000000000000000ab0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000041800\n\t0118458000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFE770000000001800401A01A000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF50BA0000\n\t0020180000180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF241F0000000018AA0AB8AB8002AA00000000000000000000000000006b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF5BF400000000000101180000180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF67D00000008\n\t98000A3809800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF9BF1000000003800001901800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF63A300eb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB71E0000000B2001\n\t8018A00018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF2DC80000000AA0018A38AA0018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA2700000\n\t0000000195580C00180000000000000000000000000000000000000000000000000000000000000000000000000000000000001b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0004040182B9\n\t20001A0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF536500000000000180180000180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF536000000040\n\t0001811800001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF2DC80000000AA0018A38AA001800000000000000000000000000000000009b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FFE54E0000000002018520C0005800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF7983000000000001\n\t801E100038000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFA37B000000200001801800001C000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAEEF0000005b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF6B140000000000019018\n\t8000184000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF632000000004000188181000180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA51800000000\n\t000184804000184000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (014401180000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFA29A000000000008001800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3A01000000000001\n\t8500400018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF35A40000000000018001000018000000000000000000000000000000000000003b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF7EBD00000000004A8AA8000AA8000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF78D30000000001008A38000AB80000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAEB90000000000bb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF60A18000000000AA8A28006A\n\tA800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF8CCE000000000000001000001000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5450000000000155\n\t9550001558000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF85240000000000004000280000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF20930000000000000080\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000fb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF842D000000000001801929801801A0000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF184200000000000100020100\n\t1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFA1A8000000000000800880800800800000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF991A00000000000000070040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF354F000000000000A00801801800\n\tC000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF481B0000000000010002000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF67C90000000000008008\n\t008008008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000870040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF3CA700000002000185008180180100000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B00000000000000180000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF199A000000000000001C0000000000000000000000000000000000000000000000000000470040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF3165000000020001808001A01801800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF59AD000000000011821A81801841\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF2BC50000000000018018618018018000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFB24D000000000001A00400c70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFDF3B0000000000518398818018018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFFCED000000000001801801A0182180000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFC8AE00000002004180041180\n\t180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000270040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF2BE4000000000041807801881801800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF7383000000002001C11A15941801\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF5785000000020001841891801801800000000000000000000000000000000000000000000000a70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF2E41000000000041801881C418018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF4A7A000000002043801A038018418000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFE41A000000002001809815A0180180000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF2F0D000000000001E018018000670040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF5ACB00000000380580580180180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF56C0000000001841801801801820000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF8246000000000001C1BB7D801801\n\t800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFE85E0000000018019018018018000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF294F0000000018018018018018000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFEB6E000000001801A018018018000000000000000000000000000000000000000000000000000000170040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF0509000000001801C0180100180000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFF130000000001801801A2980180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF2B81000000001801AE1801801800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFDA4E000000001801801C0180180000970040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF82B1000000001801800029801800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF5ACE0000000018018002018018000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFE9BE000000001C018018018018000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000570040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFE8D6000000201A85A2C283A9380200800000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFF67A0000000B1A5180180184190002000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFF0CE000000001801801A0180180000000000000000000000000000000000000000000000000000000000d70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFD9B7000000008808866800800800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF0B79000000000002009803092080028000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF38CD0000000300200018800280120000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF8BF9000000081881000001801000000000370040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF294F0000000018018018018018000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFBEA1000000408C00C42C88C1081000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF868500000000120020031020020000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF55890000000000AA0A20AA0AA180000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF09EE000000000A00A00A00A00808000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF32E1000000001200210200200222000000000000000000000000000000000000000000000000000000000000770040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFBF5A0000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF0E140000000000AA0A20AA0AA0AA0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFAF8800000000035435435435404400000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF53D60000004004004004004004004000000000f70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FFE93C00000020020020020020020020000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFC63E000000000000808800800800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFCE040000000000AA0B20AA0AA0AA000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF580000000040040048051041A4004000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFB4A7000000400400C80C00C04C004000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFAF6E00000000000580180180180000000000000000000000000000000000000000000000000000000000000000008f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF69\n\tBF00000000000181400300104400000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF41E400000000004000384400002400000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFEA9B000000000000001800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF4231000000000002800888800800000000000000004f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF8D7D00000000002B80188B823800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFE0120000000000010018518018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFE10E0000000000418080098018000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2B\n\t6F00000000000180180180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFF72F0000002AA2058A202188180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFE3D1000000000081808001809800000000000000000000000000000000000000000000000000000000000000000000002f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFA47900\n\t00000AA0AB8A3AAB8AB800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF767B000000000001801833D11A00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF46230000003543559559559558000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF9F580000000AA131AB3C81823800200000000000000000af0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF74390000000000318099418038000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFDB\n\t6A000000000001811801801C0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE330000000000001A01801A0180020000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF335500\n\t0000001801801801801801801800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFD7A60000000000038A3901821800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFBB5700000000010180180D911800000000000000000000000000000000000000000000000000000000000000000000000000ef0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF6451000000\n\t0018AB8B38AB8AB8018018000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF319900000000184D8018218338018018000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA4\n\t410000000018AB8A38AB8AB80180180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF375700000000190195580B90180180180000000000000000001f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFAC8D000000401949801851A0188180180000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF004400\n\t0000001801811C01801801801800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFF3A4000000001C01801801801801801800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF1F57000000\n\t0419118402518019018018000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF3144000000041801901C018018018018000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9E\n\tEC000000001C218C1A01C0180180180000000000000000000000000000000000000000000000000000000000000000000000005f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (BF0000000018\n\t0180000184380180180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF131300000000180180195180380580380000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF2AA00\n\t0000001801801889801803801800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF971100000040180182204184180180180000000000000000000000df0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFE421000000000080001910008000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD835000000\n\t1120000098420220000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFF8150000000010010440000010018058000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8C003f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF25DD00000008C9\n\t508AA82A8028AA8AA80000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFE10A00000000000000802000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF36C000\n\t000006082E8A38008808AB8AB80000000000000000000000000000000000000000000000000000000000000000000000000000bf0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000001\n\t000C000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF10C70000000AA8AA8A29008AACAA8AA800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF16A6000000\n\t0000000011001500010010000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFB1B300000015595594500B955955D558000000000000000000000000007f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF80840000000000800000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF2F1400000000000000014000000020000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB0CB0000ff0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF294F00000000180180\n\t1801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF9266000000001101000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA5F6000000\n\t000800A00800800800000000000000000000000000000000000000000000000000000000000000000000000000000000000000008040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF67D70000000008008008008008000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF525B0000000010\n\t0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFA5F6000000000800A008008008000000000000000000000000000000000000808040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FFE34700000000180180800180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF736700000000181180\n\t0001801000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFEA9B000000000000001800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B00000000408040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF0B40000000001849800001\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF2EB70000000018018018A18018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF86B90000000018\n\t418099418018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018018018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFED0E000000001801C0180180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF294F00000000180180\n\t1801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF470E000000001801C0000180180000000000000000000000000000000000000000208040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF434E000000001801801801A01800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF2BF6000000001801811801\n\t8098000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFEAB20000000018018018918118000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF294F000000001800a08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFE9E4000000001801A218018098\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFE80B00000000180181183180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF2F4A00000000180180\n\t9911A0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000608040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180180180\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFECE1000000000001811811811801800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF496F000000080001801801\n\t8018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFA23E000000081801841841001800000000000000000000000000000000000000000000e08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF296D0000000000018018018018018000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF496F0000000800018018018018\n\t0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF296D00000000000180180180180180000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFEB4C000000000001A000108040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF296D00000000000180180180180180\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF296D000000000001801801801801800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF296D000000000001801801\n\t801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000908040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801801800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF646A000000100001800401C018018000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF414C000000000001A000018018\n\t0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF3D7A000000400001801801C018018000000000000000000000000000000000000000000000508040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF043900000004800100000180100100000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF4916000000000201AA0225A09A0180\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFCF1F00000021010180181194592B800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF32CD000000000001A01A0100d08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF02D8000000000080800823880880800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF5A6200000000000004180802A0220000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF165E0000000000000059000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000308040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF30B300000000000184382180180180000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF0A0F000000020400C00C80C00C0080\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF2D320000002002002A024020000800000000000000000000000000000000000000000000000000b08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF47CE000000000000400400000400000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF7BE70000000AA0AA0A2008088000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFDB3B000000200000A00B20A008008000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFAA93000000200200210205224000708040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF6B5E0000000000000100300800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF76040000000AA0AA0AA0AA0AA00000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFCD1A00000035415434430424C00000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFEF75000000000000211200001200000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFAF56000000000800000800800800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF160C0000000AA0AA0A20AA0AA000000000000000000000000000000000000000000000000000000000088040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF031A0000000008000018028018000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFA2880000004004105884044004000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF7315000000400C00400D40C00C0000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFF6C60000000018000090018018000000888040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FFBF2800000000100000100100180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF5858000000000000001900000080000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFA5620000000000080018A0000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000488040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF87780000000019100098018259240000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFC59A0000000018000008C18019000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF64B40000000019800000218618180000000000000000000000000000000000000000000000000000000000c88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFC7800000000018040B38AB8238A200000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF5CC600000000180000880180180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFA51E0000002019020A20AB989808000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF062D000000001C20001001801C0000000000288040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FFE2AD000000001CAA0AA8AB8ABCAA000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF2152000000001850201C01A118080000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF61DB0000002019541449559559540000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFFCED00000005180001180580180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF2C8D000000001800400801C0180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFE94E000000001800001A0180180000000000000000000000000000000000000000000000000000000000000000688040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t0D42000000032000154031954001800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF3692000000000000001001800001800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFAA750000000818000A38058AB8000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF3C7A0000000038000008B1801800000000000000e88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF6A1D0000000AA0000A30AB8AA0018000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF9CF000000008000000008180000180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF0A150000000AA0000AB0AB8AA00180000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000188040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t0952000000000000001501800001800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF966B000000000400009001800001800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFF687000000400000001001800001800000000000000000000000000000000000000000000000000000000000000000988040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF8A4C\n\t0000000000000010818800019000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF29720000000000000012818000018000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF369200000000000000100180000180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF36E00000002002000010018000018000000000000000588040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF8E5E00000000000000110384400180000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t04BF00000000000000100B902003800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFFC33000000000000001001820001800000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF805B\n\t0000000000000011000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF8B7C00000000000000182A0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF991C0000000000000010090000058800000000000000000000000000000000000000000000000000000000000000000000388040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF36F90000\n\t00000000055955A0015580000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF62FF0000000000000AA9088000AA80000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t43EF000000000000080000000001000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF6D5A0000000000000AA8448000AA80000000000000000000b88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF708E000000000000000000000400000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9942\n\t80000000000002A8AA8004AA8000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF57640000000000000000004000010000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000788040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF83AA0000\n\t0000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF589900000000000000200000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t801200000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000f88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (910000000000\n\t0000200A00C00C00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFEB74000000000000003821801800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF976E\n\t0000000000002012000010000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF6EB7000000000000000800800800000000000000000000000000048040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF94990000000000000000004000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA2E20000\n\t0000000000180080180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF708E00000000000000000000040000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00848040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF6AE00000000\n\t0000401801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFFF90000000000100005801041800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000448040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t201A018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFF9C80000000000800018218218000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2AED0000\n\t0000000000380180180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF02DF000000000000001C418018000000000000000000000000000000c48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FFDA4E000000000000201E0180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF32EF00000000\n\t0000001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF32EF000000000000001801801800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF294F00248040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF793000000000100\n\t011A418018080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF02410000000000000058198018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE94E0000\n\t000000002019018418000000000000000000000000000000000000000000000000000000000000000000000000000000000000a48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000004018\n\t0180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF186F00000000000000180184181000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF32EF00000000\n\t0000001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF548300000000008000BAA180180000000000000000000000000000000000648040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF24A4000000000000400000001800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E5000000000000\n\t0000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFE0E50000000000000000000018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF6AE000000e48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E50000000000000000\n\t0000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFE0E500000000000000000000180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E500000000\n\t000000000000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000148040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFE0E5000000000000000000001800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E5000000000000\n\t0000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFC8E3000000000000006000001800000000000000000000000000000000000000948040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF22C40000000000002000000018000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E50000000000000000\n\t0000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFE0E500000000000000000000180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E50000000000548040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFF05800000000000A00419A00\n\t1060000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFCBB80000001000800800102018C0000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA0E6000000010012\n\t2500C210D810000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (280200200000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF6BC70000000080800080000808080000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFD8DD0000000800000200\n\t2001210000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF3C340000001000000000000080800000000000000000000000000000000000000000348040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF512300000000000020020220000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE0E500000000000000000000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF0EE70000000800000020884108C0000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF1B300000000000000b48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF472A000000400400400400000400\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFD9280000000000000AA0400AA0000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF4EFD0000002002002003\n\t30000A000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000748040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AA0AA0000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF8C5A00000000000000010000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFBD9F0000000000000AA0AA0A\n\tA000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF56B900000020020035421415420000000000000000000000000000000000000000000000f48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF00C2000000001805801941800001800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFE37E000000201200200200000201\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFC6020000000008008008008000008000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFBD9F0000000000000AA0000c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF92C60000000008008008A08000018000\n\t0001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF5A2300000040140240641040040000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF15B1000000400C00C00C00C0\n\t0400800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF8CAF000000001901011041000001820000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF048A000000000080000000000000\n\t0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF80FC0000000000000000080000000000000000000000000000000000000000000000000000004c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF8B330000000018018018018000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF81390000000018018018018220018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFA60300000000180180180181000180000000800000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE80B0000000018018098218000cc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF3B6A000000001A01A0180182220180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF8B33000000001801801801800001800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFBA91000000201801801A01888001\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFA9110000000018018018018AA0018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFB162000000001801801801B100018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFFC7D000000201801801C019540018000000000000000000000000000000000000000000000000000ac8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF478A00000000190190193180000180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE11000000000181381380580000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF5F31000000001801801801C00001800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF3160000000001A01A01801800201006c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF0327000000155885805915800155800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF87320000000018018008018000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFA02C0000000AB8318318418000AB8000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF46150000000AB8AB8AB8AB8000AB80000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF4B970000000018418A180180000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF46150000000AB8AB8AB8AB8000AB800000000000000000000000000000000000000000000000000000001c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF5D77000000001801A01809C00001800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF2E33000000005801801801A00001800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF8B330000000018018018018000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF4F72000000001801C018018000018000009c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF8B330000000018018018018000018000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF8B3300000000180180180180000180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF4BFE00000000180180181180000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF8B33000000001801801801800001800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF8B33000000001801801801800001800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF8455000000005801801809800001800000000000000000000000000000000000000000000000000000000000dc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF646D0000001808AB9608AA8000208000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFB9CF0000000120001000000001100000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF6F7100000004000001200000000200000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFEDE100000000100180101180000100000000003c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FFA06900000015595585195580015580000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFCB850000000088AA8028AA80008A800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF6999000000400000100001000200000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF818A0000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFC9898000000AAEAA804EAA8000AA8000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF519E00000042200100800100042000000000000000000000000000000000000000000000000000000000000000007c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF58AA00000000000003200000000000000000000000fc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000828040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFFCC100\n\t0000000000402002000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF70BD0000000000000140040000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000428040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF82BA0000000000002000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF20\n\t9300000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF6A1B00\n\t0000000000000600000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000228040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80\n\tFC00000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF80560000000000000000100000000000000000000000000000a28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000628040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000128040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000928040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000528040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000d28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000328040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF77DB0000000000004004000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000728040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000f28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF5B3B0000000000002002000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF77DB00000000000040\n\t0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF77DB000000000000400400000000000000000000000000000000000000000000008a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000004a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF5B3B000000000000200200\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000002a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF77DB0000000000004004000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000aa8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF92910000000000000018018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF92910000000000000018018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000ea8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF929100000000000000180180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF929100000000000000180180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF9291000000000000001801800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF9291000000000000001801001a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF9291000000000000001801800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF92910000000000000018018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF92910000000000000018018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF929100000000000000180180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF929100000000000000180180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF9291000000000000001801800000000000000000000000000000000000000000000000000000005a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF9291000000000000001801800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF9291000000000000001801800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF92910000000000000018018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF9291000000000000001801800000da8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFD1BB0000000000000AA8AA8000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF6CDE000000000000155955800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFD1BB0000000000000AA8AA800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFDC97000000000000001001000000000000000000000000000000000000000000000000000000000000ba8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF77DB0000000000004004000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF46FA8000000000004AACAA80000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFDC9700000000000000100100000000007a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000068040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000868040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000468040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000c68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000268040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000668040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000e68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000168040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000968040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000568040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000368040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000b68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00768040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B008e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000ce8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000002e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000006e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000ee8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000009e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000005e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000003e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000be8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000fe8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000018040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000818040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF097A0000000000000000000000000000\n\t0000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF097A0000000000000000000000000000000000000008000000000000000000000000000000000000418040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000c18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000218040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000a18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000618040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000118040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000918040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000518040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000318040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000718040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000f18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000098040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000898040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000498040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000298040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000a98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000698040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000198040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000998040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000598040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000d98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000398040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000798040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF86FA000000000000000080\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000f98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF8C5A00000000000000\n\t010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000058040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000858040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000458040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000258040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000a58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000658040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000e58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000158040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000958040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000558040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000d58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000358040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000b58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000758040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000008d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000002d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ad8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000ed8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000005d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00dd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000bd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A007d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000038040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000838040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000438040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000c38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000238040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000638040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000e38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000138040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000938040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000538040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000338040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000b38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000738040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000f38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000004b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000cb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000ab8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000006b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000009b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000003b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000fb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000078040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000878040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000478040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000c78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000278040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000a78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000678040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000178040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000978040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000578040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000d78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000378040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000778040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000f78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000008f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000004f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000002f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000af8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000ef8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000001f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000005f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000df8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000bf8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000007f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ff8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000804040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000404040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000204040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000604040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000e04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00104040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000904040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000504040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00d04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000304040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000b04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000704040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000084040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000884040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000484040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000c84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000284040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000684040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000e84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000184040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000984040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000584040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000384040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000b84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000784040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000f84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000044040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000844040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000444040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000c44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000244040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000644040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000144040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000944040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000544040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000344040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000744040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000f44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40000c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000004c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000cc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000ac4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000006c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000001c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000009c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000dc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000003c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000007c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000fc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000824040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000424040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000224040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000a24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000624040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000e24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000124040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000924040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000524040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000d24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000324040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000724040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000008a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000002a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF00aa4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000ea4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE001a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000005a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000da4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000ba4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF8C5A0000000000000001000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000007a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF8C5A000000000000000100000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000064040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000864040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000464040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000c64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000264040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000664040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000e64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000164040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000964040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000564040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000364040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000b64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000764040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000f64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000ce4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0004FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000006e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000009e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000003e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000be4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000fe4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000014040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000814040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000414040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000c14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000214040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000a14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000614040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000114040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000914040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000514040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000d14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000314040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000714040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000f14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000094040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000894040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000494040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000294040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000a94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000694040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000004FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000e94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000194040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000994040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000594040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000d94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000394040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE09A8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000794040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000054040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000854040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00454040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000254040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00a54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000654040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000e54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000154040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000954040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000554040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000d54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000354040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000b54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000754040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000008d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000cd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000000000000000002d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ad4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000006d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000ed4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000009d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000005d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000003d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000bd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000034040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000834040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000434040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF75DE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000c34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75\n\tDE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000004FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000234040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000634040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF75DE000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400e34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000134040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000934040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000534040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000334040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000b34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000734040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000f34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000004b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000cb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000ab4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000006b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000001b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000009b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000db4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000003b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000007b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000fb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000074040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000874040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000474040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000274040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000004FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000a74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t04FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000674040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000174040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000974040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000574040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000d74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000374040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000774040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00f74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000008f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B004f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000002f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000af4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000ef4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000001f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000005f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000df4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000bf4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000007f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ff4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000080c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000c0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000020c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000060c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000000000000000e0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000090c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000050c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000030c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000b0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000070c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000008c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000088c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000048c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF75DE000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000c8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040028c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (DE0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000068c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF7500e8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000098c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000058c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000038c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000b8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF83AA000000000000000040\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF83AA0000000000\n\t00000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000078c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000f8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000004c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000084c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000044c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000c4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000a4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000064c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000014c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000094c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000054c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000d4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000034c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000074c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000f4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000008cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000004cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t04FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ccc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000acc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF\n\t75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ecc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000001cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000dcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF003cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000007cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00fcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000082c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000042c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000000022c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000a2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000062c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000e2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000012c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000092c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000052c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000d2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000032c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000b2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000072c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000008ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000004FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000cac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000000002ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000006ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000eac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000005ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000bac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000006c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000086c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000046c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (DE0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000004FF409B00000000000000000000000000000000000000000000000000c6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF750026c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000066c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000e6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000016c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000096c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000056c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000036c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000b6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000f6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000004ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000cec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000aec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000006ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000001ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000009ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000dec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000003ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000007ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000fec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000041c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF\n\t75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000021c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04FF75DE0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000a1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000061c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000011c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0091c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000051c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000d1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0031c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000071c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000f1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000089c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000049c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000029c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000a9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000069c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000e9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000019c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000099c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000059c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000d9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000039c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000b9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000079c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000005c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000085c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000045c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000c5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000000000000000000025c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000065c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000e5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000015c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000095c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000055c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000035c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000b5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000075c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40008dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000000000cdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00002dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000adc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000006dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000edc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000009dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000005dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ddc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000000000000000003dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000bdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000fdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF097A0000000000000000000003c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000083c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000043c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000c3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000023c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000a3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000063c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000013c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000093c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000053c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000d3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000033c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000073c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000f3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000004bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000abc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF006bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ebc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000001bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B009bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000dbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A8000003bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF80FC00000000000000000800000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF80560000000000000000100000000000000000000000000000000000000000007bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000fbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000087c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000047c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF689B600000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000027c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000a7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000067c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000e7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000017c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000097c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000057c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000d7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000037c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000b7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000077c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000008fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000002fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000afc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000efc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000005fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000bfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40007fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000002040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000802040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000402040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000c02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000202040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000602040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000e02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000102040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000902040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000502040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF80AA004000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF80820020000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000302040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000b02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000702040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000f02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000082040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000882040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000482040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000c82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000282040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000a82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000682040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000182040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000982040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000582040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000382040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000782040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000f82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF949A\n\t0000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF949A0000\n\t4000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000842040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000442040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00c42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000242040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000a42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00642040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000142040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000942040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000542040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000d42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000342040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000742040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000f42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000008c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000004c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000002c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000ac2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000ec2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF209C00000000002000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF209C000000000020000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000001c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000005c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFE09A800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000dc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000007c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF80\n\tB800000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF408500000000010002000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFC49A000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF048500000000008400000000000000000000000000822040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF4013000000000600000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000422040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF44\n\tF900000000000042000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF84DA00000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000c22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFF31B00\n\t0000000001801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF335E000000000001841800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFF31B0000000000018018000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000222040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FFF31B0000000000018018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF3\n\t1B00000000000180180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFF31B00000000000180180000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF375A00\n\t0000000001C01800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF375A000000000001C01800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFF31B000000000001801800000000000000000000000000000000000000000000000000000000000000000000000000000000622040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFF31B000000\n\t0000018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFF31B0000000000018018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF3\n\t1B00000000000180180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFF31B0000000000018018000000000000000000000000000000e22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF9D9B00000000000100100000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF614100\n\t0000000211A01800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF6E34000000000105903800000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000122040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF668C000000\n\t0000888808000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF7A960000000000420020000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80\n\tDE0000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000922040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFF31B00000000000180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2AE000\n\t0000000440C40800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000522040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF806A000000000400000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFEC3A000000000000A008000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000d22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF82BA00\n\t000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000322040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000002000000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF8CE3000000000200001000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE69A000000\n\t0000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000b22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FFE69A0000000000000008000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF482A0000000004\n\t0040100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFE22A00000000040040080000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF529A0000722040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B00000000000000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF89A000000\n\t020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000401800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFAF840000000001341358000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B0000000000\n\t0000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFEA9B00000000000000180000000000000000000000000000000000000000000a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF62B600000000002802980000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B00000000000000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF5FB2000000000104105800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2EDA000000008a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF5C620000000000AA4AB800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF2AE20000000002000018000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0FEB0000000001\n\t5415580000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFEA9B00000000000000180000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF2A6A00000000040000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFEA9B00000000000000180000000000000000000000000000000000000000000000ca2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FFA85B000000000001954000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF591B000000000001800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF923B0000000000000AB8000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B0000000000002a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF21BB0000000000018AA0000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF21BB0000000000018A\n\tA00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aa2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF591B000000000001800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF591B000000000001800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF591B0000000000018000000000000000000000000000000000000000000000000000006a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF591B0000000000018000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF591B0000000000018000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF991F00000010000180000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF691A0000000400018000ea2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF591B00000000000180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF591B000000000001800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFA91E000000140001800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000000000000000009a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF8DDA00000000055580000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF82020000000000AA80000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF82BA000000000000200000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF53030000000000AB800000005a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF80E2000000000200000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF82020000000000AA8000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF53BB0000000000012000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000da2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF809000000020000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000003a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF24EB000020000400800800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFF31B000000000001801800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF808E0000004000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF2E1B000000000000800800000000ba2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF80E20000000002000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFE41A00002000000080080000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFB727000000000105801800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF6C8E000000000001105000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000fa2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF95400000000001218018800000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFD00B0000000000039018000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF161600000001008190380000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFF31B0000000000018018000000000000062040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FFF5C90000000200D380190000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFF91800000002000B803800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFFE0F000000010001905800000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000862040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFF31B0000000000018018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFF31B0000000000018018000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF335E0000000000018418000000000000000000000000000000000000000000000000000000000000000000462040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFC31A00000004000180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFDF51000200200009C0180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF8C9B000000022001801800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFF779000000000001C2180000000000000000c62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF31B2000001801C01801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF76430000018058098018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF312D000401C01A018018000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000262040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFF14300000180180180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF39C200000180180100180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFF14300000180180180180000000000000000000000000000000000000000000000000000000000000000000000a62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tF143000001801801801800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFF143000001801801801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFF1430000018018018018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFF143000001801801801800000000000000000000662040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF3362000001801801A018000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF3362000001801801A0180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFF14300000180180180180000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t2BC0000009889801801000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFBB34000201AC1A21A23800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFEDE5000013811885909800000000000000000000000000000000000000000000000000000000000000000000000000162040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFE824\n\t00010316028220C0000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF2C9B0000008018008808000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF209C00000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF58FF0000000000000620000000000000000000000000962040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF95C800000100128428C00000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tC147000001801801805800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFDB33000480CA0C00C40800000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000562040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF407F\n\t0000004004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF089A0000000000080000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF8DAC000200A00A40A208000000000000000000000000000000000000000000000000000000000000000000000000000000d62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF32230000\n\t000000AA0AA00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF808400000000008000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t32230000000000AA0AA000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF1FE100020020024C33400000000000000000000000000000362040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF3147000001901801801800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4CE8\n\t0000002002000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF2FD30000008008008008000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4FD10000\n\t0081081080180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF443C00040040040040000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t2B74000400C00C00C0080000000000000000000000000000000000000000000000000000000000000000000000000000000000762040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (516800000180\n\t1801829800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF9C88000001011011801800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B\n\t0000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF991F000000100001800000000000000000000000000000000000f62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FFA1620000018018118218000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF605E0000\n\t018018A191580000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFF11600000180180185180000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF000e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA9EF0000ABAA\n\tB88190B800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFF1CB000001801E01801800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD6EF\n\t0002AB8AB8478018000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001A01801\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF62580000AB8AB8AB8AB8000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF63250000\n\t01801811A4180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFF77700035595595595580000000000000000000000000000000000004e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FFDDC200004184180100180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8AE100008389\n\t5801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFFD83000001801801401800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF314800ce2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF364B000140051955\n\t9540000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF5B3B0000000018018000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF417A0000\n\t098018AB8AB80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFC8200000AA0AB8AB8AA00000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF561E00000A10\n\t5801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFC8200000AA0AB8AB8AA00000000000000000000000000000000000000000ae2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FFD33B000000061801800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5CAF000000403801\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF5B3B0000000018018000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5B3B0000006e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFB4280004004038001140\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF853A00000000380000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9B3900040000\n\t180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (300011000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF42BB000000001800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF6B3F000000001801\n\t8040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF5B3B0000000018018000000000000000000000000000000000000000000000001e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FFD3E10000000008BA8000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF691A0000000400018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF0A1900000009400180000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF45DA00000000009e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF86AE00000015595520000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF62E700000012C8A2800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF919A000000000001\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF6A608000000AA8A28000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF55DB0000000000014000000000000000000000000000000000000000000000000000de2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF4989000000200A0080000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF80E200000000020000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF809A000000500000010000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF089A000000000008003e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF48D7000000300980910000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF9F7A000000001801C000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF42330000000000002800\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000be2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF991000000020000180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF49FB00000000080080000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000007e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FFE11A000000021819A02000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF82B0000000201800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF23590000000210000020000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B000000000001800000fe2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF41BF0000001418000004000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF86FA00000000180040000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF943A00000000580180000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF43330000002A1801800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF682F000000401801800400000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF943A000000005801800000000000000000000000000000000000000000000000000000000000812040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FFCB870000022418818080000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF3BB4000600101E018000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF231600018000190181000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE38E0000024218018000000000412040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFB308000000220C0180840000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF7774000080301801C00000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF591E000000101801A00000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFF13B0000000018018018000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF294F000000121A018098000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF522E000100401801801C000000000000000000000000000000000000000000000000000000000000212040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF331A000000001801A0180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF3142000000001A0180180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFF13B000000001801801800000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFF13B00000000180180180000000000a12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFF13B000000001801801800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFF56A000000001801C118000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFF13B0000000018018018000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000612040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF3142000000001A0180180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF88B300000000180000980000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF28C2000000001A0000180000000000000000000000000000000000000000000000000000000000000000e12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFF959000000000021840000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF9435000108049840001800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFD42C0000242A5A422818000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFCBFB000010011C01801840000000000000112040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FFAB280000202012020000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF3BF80000000A080080180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF613F00000200600198402000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000912040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF1C2A000000255210001000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF9E39000000025801803800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF7B9C000100400C40CC0800000000000000000000000000000000000000000000000000000000000000000000512040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF137D0002003103542002000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF806C0004001004000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF02820000000000A200000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF542D000200300A00A00A000000000000000000d12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF32830000000400A200000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF3F1B000000022000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF5B8300000000C0AA000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000312040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF854D00000190180D8018018000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF996E00020002A2080000010000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF07D00000009008008008008000000000000000000000000000000000000000000000000000000000000000000000b12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFC9\n\t1C00000010000980200000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF07D000000090080080080080000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFF535000400400402404401000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF3072000400C00C00C00C0080000000000000000000712040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF90C9000001801800001801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFF7510000011010000510018000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFA95500000000002184C0000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD8\n\tC800000180180800180180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF894900000180180180180180000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFF14C00000180182180380180000000000000000000000000000000000000000000000000000000000000000000000000092040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFB73400\n\t0001B5594D955801800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF12720002018AB8A38AB801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFA341000001801E01801E018000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFABF8000001AAB8A20AB801800000000000000000000000892040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FFBB6B000201801811A018018000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF72\n\t730000018AB8A38AB80180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFDD0A000001801811C0180180000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000492040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC91800\n\t0151901801941801800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF091F00000584D811815801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF8949000001801801801801800000000000000000000000000000000000000000000000000000000000000000000000000000c92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF3C030000AB\n\t8AA0A39480AA0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF208B0001498101558521540000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF69\n\t6700000180000180400000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF60D70000018018A38008AB8000000000000000000000000000292040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF987200000180000190000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF855C00\n\t00AB8AA0BB8000AA000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF46C90000038A2001880000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBB62000001\n\t8000038000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFAD37000001C20009C000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE1\n\t4A00000180000182A0000000000000000000000000000000000000000000000000000000000000000000000000000000000000692040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000018000\n\t0182000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF0C1F000001C0000240800002000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E000\n\t0001840010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFDD6200000180000580000000000000000000000000000000000000e92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF98A4000001800000042000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0363000001\n\t8020040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF93B10000018020018120000400000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9900192040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA5B0000AB8000\n\tA280000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC91900\n\t000000001180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000992040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000100001100\n\t0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF5590000155800145000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2A0A0000AA\n\t8000A28000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF001A000000000009000200000000000000000000000000000000000000592040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD0990000000000\n\t1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF2A088006AA8000A280000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF32C80000d92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF2FF100000020080080\n\t0800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF869A080000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0FE000000\n\t080000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000392040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000400\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFAA10000000200C049008000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF24DC1000000018\n\t01801A0800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFA2170000001000020800000000000000000000000000000000000000000000b92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF9ADA00000000100180\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF2F83000000000A00800800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB39A00000000792040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF4C6A000000021801D01800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFE9EF0000044018000018000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF85B0000000250\n\t000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF35EB00008004390020181000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF27BA00000000580000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF191800004221180188180000000000000000000000000000000000000000000000052040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF9133000000001801809800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFA5DB000090021901901810\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFDB330000480118018818000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3E3A000000005800852040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFC22A000000001801811C000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF2832000000001E01801A0000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFF13B00000000180180\n\t180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000452040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF6C3C000000431819901800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFEFB3000000009801881800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF313F000000101801801800000000000000000000000000000000000000000000000000c52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF23310000000018018000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF23310000000018018000018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF9B3000000002180180000180000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF23200000005018018000252040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFE348000000001A0180000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFE33A000000201801800001800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF2331000000001801800001\n\t800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF23310000000018018000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF22220004000018019000018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFE3330004000018018000018000000000000000000000000000000000000000000000000000652040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFEA8F000010401C5589201180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF2551000000001801E0000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF3AB1000000001800000001800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFFBA000000000180010000100e52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFA621000100004001820002000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF3CD10000000030000000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFD4C0000080323B000202038000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000152040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFACD800000029028220000100000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF337D00008802080080000080000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFC9F700000000006988A00800000000000000000000000000000000000000000000000000000000952040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFA32E00020022AA00B10000800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF82E0000000280200224001000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF18B10000000138018000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF7A16000080400C40800400800000552040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF36A80002002803442540000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF273F00040040041040040000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFB5830000000440AA00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFBBA10000000AA0A20AA000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFCE11000000008010080000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFBBA10000000AA0A20AA000000000000000000000000000000000000000000000000000000000000000352040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF17E2000400C04C80C80C000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF8BC30000098218018018000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF38D800020120120020020000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFBFD10000008008108008000000000000b52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF9B9A00000800000180000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF365300000080A800800800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF503D0004015B1480480400000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000752040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF284A0000018018000818000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF4EC20000018018000010000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF9F700000001000418000800000000000000000000000000000000000000000000000000000000000000000f52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFB4DC0002018018A2001AAA00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFD8C200000184180000180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF3AC3000001893811801800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFFC96000001881821901900000000000000000d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF90F9000201955955801B54000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF9B21000001903AAB8018AA0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFF15D000001E018018018000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFA138000001801A1180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFD55F0000018AB8A38018AA00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF5302000001829801C01800000000000000000000000000000000000000000000000000000000000000000000004d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tDB910000AB8AB8BB97D800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFF143000001801801801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF28500000018018019038000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF3362000001801801A01800000000000000000000cd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FFC2510000AB8AB8B38AB8018000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF8E3E00015595594580180180000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF48A800000180100180180180000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t4942000001A01801801801800000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF52530000AB8AB8A38AB801800000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF8949000001801801801801800000000000000000000000000000000000000000000000000000000000000000000000ad2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF9CC7\n\t000001845841801E018000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF33DC000009C218018018018000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF4C4800001180180180180180000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF194B00000180181180180180000000000000000000006d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF384F00000180D84180980180000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tD7C8000001805810003801800000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF90C9000001801800001801800000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ed2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3FE7\n\t0000010058100058018000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF90C90000018018000018018000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF155100000181186181180180000000000000000000000000000000000000000000000000000000000000000000000000001d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF80990004\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF25AA0001948088A38AB8AA80000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t8D1A000040000001800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF5CBB00000A0C2011800000000000000000000000000000009d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FFD992000400230001001000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFECB3\n\t0001559559555559558000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFBF63000020A828AA8AA8AA8000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF089A0000\n\t0000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF82BA00000000000020000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t1B498000AA8AA8A28AA8AA80000000000000000000000000000000000000000000000000000000000000000000000000000000dd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4C5B00000000\n\t5000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF2F83000000000A00800800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF871A0000000020000000000000000000000000000000000000003d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEF720000\n\t00000E0080080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFF13B00000000180180180000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00bd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B00000000\n\t0001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF591B000000000001800000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEC42\n\t000000001A008008000000000000000000000000000000000000000000000000000000000000000000000000000000000000007d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001881\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF2F48000000209A018018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF28BF0000\n\t0010180000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF50860000000099000010000000000000000000000000000000000000fd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FFF14C000000001A4180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE7C300000000\n\t5A00001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF48C0000000081A00001800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF312400032040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFCD2F000000411801\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF36BA0000000038018018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF913C0000\n\t000018218018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000832040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400018018018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF221A00000000D801A0180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF41300000000\n\t3E01A01800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFF12500000060180180180000000000000000000000000000000000000000432040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF24A2000040001201801800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEF25000000009881\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF312E0000004018018018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF253A000000c32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFF13B0000000018018018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF31CA000000001C0180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2F2E00000020\n\t988180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000232040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180180000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFF1C1000000201C01801800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF13B000000001801\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFF13B000000001801801800000000000000000000000000000000000000000000a32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FFE8BB0000000018000018000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF3142000000001A018018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFF13B00000000180180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF13B0000000000632040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF7C6700009048182182980800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF5138000600001801801800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE8BB000000001800\n\t001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (808088000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF81C50000000000018D20000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFDA270000880A18800018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFCD1D000020225A842838800000000000000000000000000000000000000000000000132040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF68BA0000404C2D40C5080000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF5CE100006030024022000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF02FB000000054802801800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFDCAF00000000212500932040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF4D64000200200A00AC0800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF96C400000020020820D0000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFAB3B0000000098058018\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000532040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFC5240002003543542D400000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFB73D00040040040040040000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFC3010000000AA0A200000000000000000000000000000000000000000000000000000000d32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF2FD3000000800800800800000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFBBA10000000AA0A20AA000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFF3A00000000AA0AA0AA000332040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFD875000400C00C00C00C000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF314700000190180180180000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFAB4A00020020021020020000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFE718000000088001800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF28F3000002802800800800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF455E000404414580400400000000000000000000000000000000000000000000000000000000732040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FFFDD90000018018418519000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF4EA50000018018200018800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFAEF800000100000200100400000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF1D1B0000000000058300040000f32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFCA7E0002019218A20AB80000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFDB33000001801C00001C00000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF4A46000001915809801800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF27350002019559459558000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF5E3A00000180B8ABCAB8000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF614100000180181180180000000000000000000000000000000000000000000000000000000000008b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FFF14300000180180180180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFF369000001A01801A0180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF71880000018ABCAB8ABC00000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF0157000001C41801801800000000004b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF545D0000018058A3807800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF6D400000018918018018000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF00A50001338458119518000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF54510000AB8038A38AB80180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFBDE00000959519558D180180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF9CAA000001831011801801800000000000000000000000000000000000000000000000000000000000002b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF72C2000001A13801801801800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFF14C000001921801801801800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF1BD50000AB9018AB8AB8018000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF5D48000041801801801801800000000000ab2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF73490000218418018018018000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF5145000001BA180180180180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF1B00000081809801C0980180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFAD48000041821809801801800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFB34E000001803824001801800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF86F8000081811800211801800000000000000000000000000000000000000000000000000000000000000000eb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF58D700000002A0018480000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF098D0000018458000410018000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF14C800000180180400180180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF196600000180185182180180000000000000001b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF89C700000100000900000100000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF29690000AA8148A28028AA800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFC994000000100011880000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF18D50000010000011020010000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF8BF3000555955945155D558000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF92440000AA9208AA8288AA80000000000000000000000000000000000000000000000000000000000000000000005b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF02\n\t820000000000A200000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF209A00020000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF0918000000000010000200000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF1B498000AA8AA8A28AA8AA80000000000000000000db2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FFC4F6000001000104000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF2FD30000008008008008000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80\n\tCA00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF2FD300000080080080080000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF513D000001801A2180180000000000000000000000000000000000000000000000000000000000000000000000000000bb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF8F2300\n\t0001801000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF591B000000000001800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF99620000000002018000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF2FD30000008008008008000000000000000000000000007b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF91DD000001C818018818000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF60\n\t5400000190181190180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE8C300000180180000180000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF14300\n\t0001801801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFFCFF000041801900001800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF60D7000001C01808001800000000000000000000000000000000000000000000000000000000000000000000000000000000072040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF3160000001\n\t8018018218000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFCD460000019118018018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC1\n\t4200000184180180180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF5D7E0000418219018018000000000000000000000000000000872040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFF14300000180180180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0E4704\n\t0001911801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFF087020001801801841800000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000472040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF60DC000000\n\t0410218018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFE9470004018218218018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF1\n\t430000018018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000c72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3B0000000018\n\t0180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFF13B00000000180180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF313900\n\t0400001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFF13B00000000180180180000000000000000000000000000000000272040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFF13B000000001801801800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF13B000000\n\t0018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFF13B0000000018018018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF100a72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE8BB0000000018\n\t0000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFF1DF000000401C0180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF13B00\n\t000000180180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000672040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0020245AA820\n\t9800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFEB2E000010109801901800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF75B000000\n\t001801E018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFE85F000000401C00001800000000000000000000000000000000000000e72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF59140000000000218080000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF870B0000000080\n\tC180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFF7B10000600E380808100000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF97F80000172040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFAF61000040400D10C0\n\t0800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF22F4000200200300200000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBD79000008\n\t000810800800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000972040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1100A2176000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF518B000000288A008008000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2CD20002002442\n\t1030800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF01340000000418418018000000000000000000000000000000000000000000572040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FFD3800000AA0AA0AA0AA00000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFEB9900015424435400\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF443C000400400400400000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF37C60000AA00d72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFD9F9000000000810800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF9B810000AA0AA0A20AA0000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000372040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF4D5C000400400C00C0000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFA3BB00000004180100\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFF00900020020120120000000000000000000000000000000000000000000000000b72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF0F8700000000200190C000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF591B000000000001800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFE77A0000000228018000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF48FC000400405400772040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF4B350000000018409100000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF44BC00000002982000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFA0BF00000005580100\n\t400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF68010002000A78A2022000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF6F27000000411801080000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF73320000000018098080000000000000000000000000000000000000000000000000000f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF1DBB000000011801AAA0000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFCC4E0002001559549540000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFB95C000000141AB380000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF8A3A00000000180080008f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFDE79000000001810C0000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF9B42000000001A01800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFB1150000004AB8A28AA000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFD8A10000000AB8A38000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF1A380000000018108000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF5B3B0000000018018000000000000000000000000000000000000000000000000000000000cf2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFE8C300000180180000180000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFBA580000018AB8A300180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF3FF6000001955954001800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF39C2000001801801001800002f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF39C2000001801801001800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF59C30002018018010018000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF625B0000018AB8BB0018000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000af2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF9CC100001188180100180000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF3B4100040980180100180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF36FE000001805901001800000000000000000000000000000000000000000000000000000000006f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFB314000001841801001900000000000000000000000800000000000000000000000000000000000000000000\n\t0000000000000000000000000002000000000000000000000000000000000000FF81A0000001921801001808000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF3EB20000018018011018800000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF3E7E000001803901001800000000ef2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000002000000000000000000000000000000000000FF750D0001200000018000000000000000000000\n\t0000080000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000\n\t00000000000000FF8ED100000100100100181000000000000000000000080000000000000000000000000000000000000000\n\t00000000000000000000000000000002000000000000000000000000000000000000FFF94B00000180180108180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0800000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF82EB0000588008AA8AB800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF67CE0000040CC0010000000000000000000000000008000000000000000000000000000000000000009f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF0AC10000AA8AA82A8AA8000000000000000000000008000000000000000000000000000000000000000000000000\n\t000000000000000000000002000000000000000000000000000000000000FFDA930000802880000010000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF5337000155955955D5580000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFDC57000002A428AA8AA80000000000005f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF80A6000000000100000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF82BA000000000000200000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000df2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFE7520000008008000008000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF401900000200000002000000000000000000000000000000000000000000000000000000000000000000003f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFE75200000080080000080000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFE752000000800800000800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFE84100000380180002180000000000000000bf2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF4F0A000001001000001000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE8C300000180180000180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF6CC200000180180400180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFE8C300000180180000180000000000000000000000000000000000000000000000000000000000000000000000ff2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tE8C3000001801800001800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF36C2000001809800001800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF14C20000018118000018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF6CC200000180180400180000000000000000000000a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FFE8C30000018018000018000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE8C300000180180000180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFE8C300000180180000180000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tE8C3000001801800001800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFE7C9000001A05800001800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFE7C9000001A0580000180000000000000000000000000000000000000000000000000000000000000000000000000040a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFEA9B\n\t0000000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFEA9B0000000000000018000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE8C300000180180000180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFE8C30000018018000018000000000000000000000000c0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FFEA9B00000000000000180000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tEA9B000000000000001800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFEA9B000000000000001800000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B\n\t0000000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFEA9B0000000000000018000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFEA9B0000000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000a0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFEA9B0000\n\t0000000000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFEA9B00000000000000180000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tEA9B000000000000001800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFEA9B0000000000000018000000000000000000000000000060a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF0E0E000010112000233800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9996\n\t0001200200901018000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFEA9B0000000000000018000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF808B0000\n\t0000014002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFE09800000002000000200000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tC58D0000800020800818000000000000000000000000000000000000000000000000000000000000000000000000000000000010a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A9C00000000\n\t0020001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFE2E6000000000100400800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF22B0\n\t0002002000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF741100002808800800980000000000000000000000000000000090a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF682C0000020000000160000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFDAE20000\n\t0001020000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFF18E00035034400032900000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0050a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD9980000AA0A\n\tA0000AA000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF9FB3000110134200140000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF807D\n\t000400400400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200200201\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF881A0000000000008000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD9980000\n\tAA0AA0000AA00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF4A3B000022000000000000000000000000000000000000000000000030a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF443C00040040040040000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBCBC00040044\n\t0400C00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF591B000000000001800000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF1E900b0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF989D000000020020\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFF89A0000000200000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B0000\n\t00000001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000070a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA91400000004\n\t0041800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000f0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF591B000000000001800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF21BB000000000001\n\t8AA0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF591B0000000000018000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B00000008a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF3B2E000200400001A000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFA85B00000000000195400000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE1C200000000\n\t02018AA0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000088a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF5D58000400000001C00000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5969000000200201\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF21BB0000000000018AA00000000000000000000000000000000000000000000048a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF5B430000018018018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF53030000000000AB8000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B0000000000c8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF5B4300000180180180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF515B0000018018AB800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4F73000001801955\n\t80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C00000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFFB428000018018018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF5B430000018018018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF515B0000018018AB8000000000000000000000000000000000000000000000000000a8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FFE34200000182180180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFB94200000180180380000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFAB46000001941801800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9F020000018018010068a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF2D55000001801801800000000000\n\t0000000000000008000000000000000000000000000000000000000000000000000000000000000000000002000000000000\n\t000000000000000000000000FF1F460000019018058000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF5873000001801801B000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000080000000000000000000000000000000000000000000000000000000000000000000000020000000000000000\n\t00000000000000000000FF96950000000000A000000000000000000000000000080000000000000000000000000000000000\n\t00000000000000000000000000000000000002000000000000000000000000000000000000FFE5D400000180180100000000\n\t0000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000200000000\n\t0000000000000000000000000000FF9BCA0000018018018800000000000000000000000000000000000000000000000000000018a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FFB4670000AA8AA80A800000000000000000000000000800000000000000000000000000000000000000\n\t0000000000000000000000000000000002000000000000000000000000000000000000FF806A000000000400000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFABDC0000AB8AB9008000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF228E00000000001400000098a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFD4630004AAEAA8AA8000000000000000\n\t0000000000080000000000000000000000000000000000000000000000000000000000000000000000020000000000000000\n\t00000000000000000000FF43F400000100144000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFCC3600015595595580000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000058a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF8099000400000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000d8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF18C30000018218020000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF10CB0001010000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF415300000080080000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFF29A000080020002000000000038a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF415300000080080000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF80CA000001000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF4153000000800800000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF83220000018010000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000078a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF42C300000180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF88C200002180180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF42C3000001801800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF96C200004180180000000000000000f8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF42C3000001801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF42C30000018018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF42C30000018018000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF5C0301000180980000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFBEC200000181180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF42C30000018018000000000000000000000000000000000000000000000000000000000000000000000084a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF8202010001801800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF42C3000001801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF82C8000001A018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF82C8000001A0180000000000000000000044a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF5B3B0000000018018000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF5B3B00000000180180000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF42C300000180180000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF5B3B000000001801800000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF5B3B000000001801800000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF5B3B00000000180180000000000000000000000000000000000000000000000000000000000000000000000024a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF5B3B0000000018018000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF5B3B0000000018018000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF5B3B00000000180180000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF5B3B0000000018018000000000000000000000a4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF5B3B00000000180180000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF5B3B000000001801800000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF5B3B000000001801800000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000064a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFA74D000000309A038000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF2C070000300219018000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF5B3B0000000018018000000000000000000000000000000000000000000000000000000000000000000000000000e4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF4B\n\t6500000800088080000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFA29A00000000000200000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFFFBA0000400218010000000000000000000000000014a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF9E3A000010001801800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF9D1E000040400C008000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF92530002302890000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000094a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF50\n\tBA0000AA04000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFB5FA00000001080080000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFBC520002002C50000000000000000000000000000000000000000000000000000000000000000000000000000000000054a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFA1380000AA0AA000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF53D90001540940000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF4068000400000400000000000000000000000000000000d4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FFE0E30002000002000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFA1380000AA0AA00000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000034a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF807D00\n\t0400400400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF807D000400400400000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF709A000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF8C9B000000\n\t0500000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF049B000000030000000000000000000000000000000000000074a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFA8820000000000A800000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFF89A000000020000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF032E0002002AA1020000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000AA0\n\tAA00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF94E100000000021400000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF37BA00\n\t0200554154000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFE11F0000000AA020000000000000000000000000000000000000008ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF806A000000\n\t0004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8B004ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF59630000018000\n\t0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000180000180\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF5963000001800001800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5963000001\n\t8000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF59630000018000018000000000000000000000000000000000000000002ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF9976000001C000018000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF59630000018000\n\t0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF996100040180000180000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF59630000aca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF9968000001A0000180\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF6962000001840001800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF26E5000219\n\t9A00018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800001810000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF59630000018000018000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF41750000018200\n\t8180800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF59630000018000018000000000000000000000000000000000000000000000eca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF81DA00000400000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFDF9A00013000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF6976000001040101800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9973000001001ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFA80A00008A8000AA800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF472B0000408000\n\tAB80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF02FB8000AA8004AA80000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF919A00000000000100\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF0D13000155800155800000000000000000000000000000000000000000000000005ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF80E20000000002000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000dca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF808E00000040000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF8090000000200000000000000000000000000000000000000000000000000000000000bca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FFBC9A0000000100000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF82100000080800000080000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000007ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF7E0F00000811000001000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000002a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF809A00006000800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFDC9D000000010020000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000082a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF8095000000000040000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000c2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000022a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF808B0000000000000100000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF209300000000000000800000000000000000000000000000000000000000000000000000000000000062a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFBC9A00000001000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000e2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF9E9A000000008000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000092a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF809000000020000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000052a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF80900000002000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF835A00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF817A00000000080000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000032a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF808E000000400000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF416F0000004008000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF42BB000000001800000000000000000000000000b2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FFFABA0000000218000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFF89A00000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000072a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t42BB000000001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF42BB000000001800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF42BB000000001800000000000000000000000000000000000000000000000000000000000000000000000000000000f2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF42BB\n\t0000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF42BB0000000018000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF42BB00000000180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF42BB00000000180000000000000000000000000000000aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF835A00000000100000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t835A000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF835A000000001000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4C5B\n\t0000000050000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF835A0000000010000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF835A00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000004aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF839E0000\n\t0015400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t85580000000A9000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF835A00000000100000000000000000000000000000000000caa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF81180000000AA000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF81180000000AA0000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aaa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (209300000000\n\t0000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000006aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF20930000000000000080000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00eaa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000009aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B005aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000daa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000003aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000baa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000faa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000006a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000086a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000046a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000c6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000026a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000a6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000066a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000016a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000096a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000056a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000d6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000036a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000076a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000f6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000008ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000004ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000002ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000aea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000001ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFE09A800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000dea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000007ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000fea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000081a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000041a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000021a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000a1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000061a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000e1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000011a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000091a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000051a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000d1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000031a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000b1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000071a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000009a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000089a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000049a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000c9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000029a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000069a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000e9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000019a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000099a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFE09A8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000059a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000039a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000b9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000079a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000005a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000085a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000045a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000c5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0025a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000065a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00e5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000015a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000095a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000055a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000035a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000b5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000075a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000f5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000004da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000cda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000ada040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000006da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000001da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000009da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000dda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000003da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000007da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000fda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000083a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000043a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000023a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000a3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000063a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000013a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000093a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000053a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000d3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF400033a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000073a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000f3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000008ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000004ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000002ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000aba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000eba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000001ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000005ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000dba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000bba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000007ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000007a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000087a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000047a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000c7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000027a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000067a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000e7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000017a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000097a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000057a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000037a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000b7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000077a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF008fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000cfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B002fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000afa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000006fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000efa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000009fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000005fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000003fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000bfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000ffa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000006040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000806040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000406040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000c06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000206040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000a06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000606040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000106040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000906040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000506040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000d06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000306040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000706040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000f06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000086040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000886040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000486040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000286040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000a86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000686040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000186040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000986040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000586040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000d86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000386040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000786040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000f86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000046040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000846040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000446040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000246040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000a46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000646040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000e46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000146040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000946040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000546040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000d46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000346040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000b46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000746040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000008c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000cc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000002c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000ec6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000005c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF097A000000000000000000000000000000000000000800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000bc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF007c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000026040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00826040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000426040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000c26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000226040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000626040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000e26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000126040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000926040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000526040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000326040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000b26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000726040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000f26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000004a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000ca6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000aa6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000006a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000001a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000009a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000da6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000003a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000fa6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000066040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000866040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000466040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000266040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000a66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000666040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000166040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000966040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000566040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000d66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000366040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000766040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000f66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000008e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000004e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ce6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000002e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000ae6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000ee6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000001e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000005e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000de6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000be6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000007e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000016040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000816040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000416040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000216040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000616040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000e16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000116040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000916040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000516040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00d16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000316040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000b16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00716040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000096040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000896040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000496040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000c96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000296040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000696040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000e96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000196040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000996040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000596040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000396040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000b96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000796040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000f96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000056040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000856040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000456040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000c56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000256040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000a56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000656040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000156040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000956040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000556040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000356040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000756040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000f56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000004d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000cd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000ad6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00006d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ed6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000001d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000009d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000dd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000003d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000007d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000fd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000036040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000836040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000436040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000236040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000a36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000636040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000e36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000136040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000936040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000536040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000d36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000336040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000b36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000736040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000008b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000002b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ab6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000eb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF001b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000005b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00db6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000bb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000007b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000076040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000876040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000476040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000c76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000276040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000676040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000e76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000176040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000976040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000576040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000376040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000b76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000776040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000f76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000004f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000cf6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000af6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000006f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ef6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000009f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000df6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000003f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bf6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000ff6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF400000e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000040e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000c0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000a0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000060e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000010e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000090e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000d0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000030e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000070e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000f0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000088e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000048e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000028e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000a8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000068e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000e8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000018e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000098e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000058e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000d8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000038e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000078e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000084e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000044e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000024e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00a4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000064e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000e4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0014e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000094e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000054e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000d4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000034e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000b4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000074e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000008ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000cce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000002ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ace040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000006ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000ece040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000009ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000005ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000003ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000bce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000fce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000002e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000082e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000c2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000062e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000092e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000052e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000032e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000b2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000072e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000f2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000004ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000cae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000aae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000006ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000001ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000009ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000dae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000003ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000007ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000fae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000086e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000046e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000026e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000a6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000066e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000e6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000016e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000096e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000056e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000d6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000036e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000076e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000008ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF004ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000002ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00aee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000eee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000001ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000005ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000dee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000bee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000007ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000001e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000081e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000c1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000021e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000061e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000e1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000091e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000051e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000031e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000b1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000071e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000009e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000089e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000049e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000c9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000029e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000069e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000019e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000099e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF400059e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000039e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000b9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000079e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000f9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000005e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000085e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000045e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000c5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000025e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000a5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000065e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000015e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000095e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000055e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000d5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000035e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000075e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000f5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000008de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000004de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000002de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000ade040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ede040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000001de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000dde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000007de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00fde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000083e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0043e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000023e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000a3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000063e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000e3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000013e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000093e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000053e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000d3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000033e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000b3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000073e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000008be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000cbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000002be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000abe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000006be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000ebe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000009be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000005be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000003be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000bbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000007e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000087e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000047e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000c7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000027e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000067e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000e7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000017e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000097e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000057e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000037e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000b7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000077e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000f7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000004fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000cfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000afe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000006fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000efe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000001fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000009fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000dfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000003fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000007fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t04FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000ffe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t04FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000801040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000401040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000201040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000a01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000601040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000101040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000901040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000501040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000d01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00301040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000701040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00f01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000881040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000481040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000281040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000a81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000681040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000e81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000181040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000981040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000581040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000d81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000381040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000b81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000781040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000041040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000841040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000441040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000c41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000241040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000641040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000e41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000141040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000941040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000541040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000341040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000b41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000741040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000cc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40002c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000006c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000ec1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000009c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000005c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000003c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000bc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000fc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000021040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000821040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000421040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000c21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000221040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000a21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000621040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000121040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000921040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000521040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000d21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000321040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000721040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000f21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000004a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000aa1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A8000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000001a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF009a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000001FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000da1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB003a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000007a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000001FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000fa1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000061040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000861040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000461040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000261040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000a61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000661040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000001FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000001FF409B00000000000000000000000000000000000000000000000000000000000000000000e61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB000000000000000000161040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000961040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000561040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000d61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000361040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000b61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000761040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000008e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000ce1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000002e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000ee1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000005e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000be1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000011040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000811040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000411040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000c11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000211040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000611040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000e11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000911040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000511040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000311040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000b11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000020000\n\t00000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000711040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF93BA0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFA6FF0000000000000000000000000000000000000000000000000000000000000000000000f11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000091040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000891040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000491040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000c91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF097A0000000000000000000000000000000000\n\t0000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF097A00000000000000000000000000\n\t000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000291040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000a91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF097A0000000000000000000000000000000000\n\t0000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000691040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF097A000000000000000000000000000000000000000800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF097A000000000000000000000000000000\n\t000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000191040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000991040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000591040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000d91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000391040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000791040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000f91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000051040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000851040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000451040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000251040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000a51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00651040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000151040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00951040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000551040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000d51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000351040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000751040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000f51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000008d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000004d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000002d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000ad1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000ed1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000001d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000005d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000dd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000bd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000007d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000031040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000200\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000831040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FFBCE300000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000002000000000000000001000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF1FDB000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000001000000000431040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFA23C0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000200FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF0159000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000231040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF607A0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000a31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9C\n\t8600000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000631040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF9C8600\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000e31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000131040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000931040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000531040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF23FF00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF23\n\tFF0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000331040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000b31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000731040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00008b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000cb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000002b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ab1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000006b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008000000008\n\t0000000080000000080000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000eb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF4CFE0000004000000004000000\n\t0040000000041004000010000000010000000010000000010000000010000000010000000010000000010000000010000000\n\t01000000001000000001000000FF706A00000000000000000000000000000000000004000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFE75600000002000000\n\t0020000000020000000020000000008000000008000000008000000008000000008000000008000000008000000008000000001b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010000000010\n\t0000000100000000040000000040000000040000000040000000040000000040000000040000000040000000040000000040\n\t0000000400000000400000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF5C6D000000008000000008\n\t0000000080000000180000000020000000020000000020000000020000000020000000020000000020000000020000000020\n\t000000020000000020000000020000FF859F0000000000000000000000000000000000100000000000000000000000000000009b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF989A2000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF8A9000000000000000000000000000000000002000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF7EFF00000010000000005b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF93C300000000040040040040040040\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFB73D0004004004004004000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF53D600000040040040040040040040000000000000000000000000000000000000000000003b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000bb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF443C0004004004004000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000fb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF7EFF000000100000000100000000100000000100000000040000000040000000040000000040000000040000\n\t0000400000000400000000400000000400000000400000000400000000400000FF997C000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000080000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000071040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001000000001\n\t000000001000000001000000001000000001000000001000000001080000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF996900000000800000000800000000800000000800000000200000000200000000200000000200000000\n\t20000000020000000020000000020000000020000000020000000020000000020000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000871040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 1832 TDI (FFFFFFFF0000007A11110000000000000143FFFFFFFFFFFFFF\n\tFFFFFFFFFFFFE756000000020000000020000000020000000020000000008000000008000000008000000008000000008000\n\t0000080000000080000000080000000080000000080000000080000000080000FF558E000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000C0000FF60EC000000400000000400000000400000000400000000100000000100000000100000000100000000471040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSIR\t8\tTDI\t(FF);\nRUNTEST IDLE    100 TCK;\n\nSIR\t8\tTDI\t(26);\nRUNTEST IDLE    2 TCK   2.00E-03 SEC;\n\nSIR\t8\tTDI\t(FF);\nRUNTEST IDLE    2 TCK   1.00E-03 SEC;\n\nSIR\t8\tTDI\t(79);\nSDR\t24\tTDI\t(000000);\nRUNTEST IDLE    2 TCK   1.00E-01 SEC;\n\n//END\r\n"
  },
  {
    "path": "demo/uart_tx_flash.svf",
    "content": "//ULX2S / ULX3S JTAG programmer v 3.0.92 (built Sep 19 2020 14:37:22)\n//START\r\nSTATE IDLE;\nSTATE RESET;\nSTATE IDLE;\n\nSIR\t8\tTDI\t(E0);\nSDR\t32\tTDI\t(00000000)\n\tTDO\t(41111043)\n\tMASK\t(FFFFFFFF);\n\nSIR\t8\tTDI\t(1C);\nSDR\t510\tTDI\t(3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);\n\nSIR\t8\tTDI\t(C6);\nSDR\t8\tTDI\t(00);\nRUNTEST IDLE    2 TCK;\n\nSIR\t8\tTDI\t(0e);\nSDR\t8\tTDI\t(01);\nRUNTEST IDLE\t32 TCK 1.00E-01 SEC;\n\nSIR\t8\tTDI\t(3C);\nSDR\t32\tTDI\t(00000000)\n\tTDO\t(00000000)\n\tMASK\t(0000B000);\n\nSTATE RESET;\nSTATE IDLE;\nSIR\t8\tTDI(FF);\nRUNTEST IDLE\t32 TCK;\nSIR\t8\tTDI(3A);\nSDR\t16\tTDI(68FE);\nRUNTEST IDLE\t32 TCK;\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000001B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000801B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000401B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000c01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000201B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000a01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000601B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000e01B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR\t16\tTDI(00A0)\n\tTDO(40FF)\n\tMASK(C100);\n\nSDR\t32\tTDI(0000101B);\nRUNTEST DRPAUSE 5.50E-01 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(20);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF2B8D000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000051B889410000006200000002000000\n\t44C208888200000047000000DCFFFFFFFFCDBDFFFFFF008C1CCC82E24282C26CB462AC4CB4AAACA26232045C2E4E860A00FF00000040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000800040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000400040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000200040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000a00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000e00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000100040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000900040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000d00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000700040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f00040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000880040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000480040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000280040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000a80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000680040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000e80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FFD3590000000000000000000000000000000000000010000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000180040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000980040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000580040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000d80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000380040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000b80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF21790000000000000000000000000000000000000800000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000780040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF21790000000000000000000000\n\t0000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f80040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000080040\n\t0800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF20E4000000000000000000000000200000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000040040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF88920000000000000000000000000008000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFF8FD0000000000000000000018\n\t0000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF80CF00000000000000000000100000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF28460000000000000000840040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF4CD3000000000000400000000000000800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF82BA000000000000200000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000440040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000800001800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFF0A00000000000000000000008000010000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF50DE0000000000000000000010\n\t0000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000c40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF527600000000000000000002100000180000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF98D700000000000000000000100000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF788F000000000100040000015800041800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF38A900000000000000000000240040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF2DBC000000000000000000041800001800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF38B80000000000000400000018000018000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF7F3D0000000001000000000138\n\t000218000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004018000000\n\t0008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF3D2100000000000040000000180020180000000008000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFF8FD00000000000000000000180000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFF8FD00000000000000000000180000180000000000000000000000000000000000000000000000640040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF98F5000000000000008000001800001800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF217C000000000000000200001800001800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF74A30000000000004000000018000818000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF59E1000000000000000000001800e40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFC88E0000000000000000010000000018000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF408100000000000001000100000008180000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF3B8F00000000000000040100000000\n\t180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000140040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFC88E000000000000000001000000001800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFC3B6000000000000000021020000001800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFC88E000000000000000001000000001800000000000000000000000000000000000000000000000000940040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFC88E0000000000000000010000000018000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFC88E0000000000000000010000000018000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF588300000000000000000000000000180000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFFF1A0000000000060000200000000000540040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF208900000000000000000180000000180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF1DCF000000000000000001040000001800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFC88E000000000000000001000000001800\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF55D00000000000000000010400000818000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFC36C0000000000020102000000002018000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF7BD40000000000000000538800001218000000000000000000000000000000000000000000000000000000340040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF161900000000000200016308000020000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF14B300000000000000400890400000180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF269B000000000000008001400000020000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000b40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FFE574000000000000000001280000251000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF1A2D0000000000000020010200000018000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF7EB80000000000000004A08820004008000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000740040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFB63A00000000040000040001000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF68E400000000000000000000000008600000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF765100000000020000000084C00000080000000000000000000000000000000000000000000000000000000000f40040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tA9170000000000002000001440000AA000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFC035000000000000000000008000020000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF2E620000000000004000000000000AA0000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF10CB0000000002000000001440001100000000000c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF8C5A0000000000018000000400000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFCC6200000000020000020010000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF474100000000000080000003200000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t090F000000000000800000144000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF59CD000000000018000000004000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFABA6000000000000C004004000004000000000000000000000000000000000000000000000000000000000000000004c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFCC1A\n\t0000000000018000001000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF4D0F0000000000018000000440000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF591B00000000000180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF5D2F000000000001A002002420002000000000000000cc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FFF89B00000000000180002200000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t997C000000000001800008000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF591B000000000001800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF35C2\n\t0000000000018000800000000AA0000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF9F7A0000000000018000800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF2F8D0000000000018002D40000000AA0000000000000000000000000000000000000000000000000000000000000000000ac0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF99290000\n\t0000000180000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFF3A30000000000018000000000000AA00000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t3964000000000001800000000000200000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF5627000000000001800254000000154000000000000000006c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF919A000000000001000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B\n\t0000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF9CF10000000000010001300000004000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9F210000\n\t0000015580180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF8B1100000000000180180180000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t53030000000000AB800000000000000000000000000000000000000000000000000000000000000000000000000000000000001c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8B1100000000\n\t0001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF81090000000000AB801801800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8B11\n\t0000000000018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF81090000000000AB8018018000000000000000000000000000009c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF8B110000000000018018018000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB8EE0000\n\t00000001801C0180000040000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF8B1100000000000180180180000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF005c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5E1400000000\n\t0000041A01840000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF526F000000000000001801800000400000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8B11\n\t000000000001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000dc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000010400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF23D30000000000000408011000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF87100000\n\t0000000180080180000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF6D9100000000000180080188000000000000000000000000000000003c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF26660000000000A29080C680000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC80900000000\n\t0011880020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF69F1000000000001824010000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF05D700bc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA12B000000000155\n\t9159558000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF5A440000000000A28428888000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80DE0000\n\t0000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000080040\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF432100000000\n\t00A28A88AA800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF1C8800000000001001100000000000000000000000000000000000000000fc0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF87BE000000000200800800000800800800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEAE3000000000200\n\t0000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF8EA40000000000004000002000002000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF389E000000020040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF47C70000000000008008\n\t0000080080080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF4DC0000000000001C01800001801C0180000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9D5700000000\n\t000020100000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000820040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF9D5A000000000001C00000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE1C6000000000000\n\t8000000008008008000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFED74000000000000000000600001001000000000000000000000000000000000420040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF05DD0000000000018018000810018618000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFE4D70000000000000018\n\t0040100180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFCF1400000000000000110010100180180000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B0000000000c20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF4FE200000000010840188010\n\t1801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF969E000000000000001880001801801800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF293A000000000001\n\t801800211041901800000000000000000000000000000000000000000000000000000000000000000000000000000000000000220040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (901800011801\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFE93D000000000101801800001801A018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF939D000000000001A019\n\t0040180180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF926F000000000011801800511841B018000000000000000000000000000000000000a20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF785F000000000001901C8001180180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFD60000000000000180180030\n\t1801A01800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF0330000000000001A019640C7A01801800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4D3F00000000000100620040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFAA97000000000001E00AC0099801\n\t9818000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF0C66000000000001801804041C01A018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF7DFE0000000000018018\n\t28201841A018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018010018008\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFF747000000000001A01801C0180180080000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF783C00000000000180191190\n\t1001A00800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF34E4000000000001801801A0182180080000000000000000000000000000000000000000120040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FFF693000000000001981001801801A01800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF2104000000000201A01001C01001\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF97740000000000018010018018018018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF814E000000000001801800920040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF3120000000000001801801801001A018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF3D7400000000000180080180180180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF9D5F000000000001801001A0\n\t100180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000520040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (11418D180000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF0779000000000001801000801801801800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF48DF000000000000001801801001\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF3CA3000000000000001801C00801801800000000000000000000000000000000000000000000d20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FFD37A0000000000018004200400201200000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFF01800000000000000180402C0010010\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF26E4000000000200341A20B2420120100000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF42B4000000000401C09002A100320040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF2FC00000000002002A800038120020000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFDB0B000000000000940840000080808800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF3CB5000000000001800102002050\n\t090000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF5CE60000000002004C40012212002000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF10960000000000018218239418018018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF8B42000000000400D00900C04C50C888000000000000000000000000000000000000000000000000720040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF48100000000003442A840031415415400000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF494600000000040041020040000040000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF39810000000000A20080000880AA0AA000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF4ECD000000000208A00800A0480000f20040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF02900000000000B21000000AA0AA0AA000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFDA390000000000080020000200000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF8BA20000000000A20220000AA0AA0AA0\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFEB5200000000010180180180180000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF28F100000000020024400120000020000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF96B5000000000010888800800800000000000000000000000000000000000000000000000000000000008a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF9AD1000000000081A01A00200200200000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF410D000000000000800810000804000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFE6F20000000000601800000180000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFB59F000000000000C00C00C00C004000004a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF17890000000000000018008410000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFF8FE00000000000100190000100400000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFD11400000000000180190004002004000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF1721000000000001045803881C40010000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFBE5D0000000000118118A8835812042000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF11A10000000000008018108018400400000000000000000000000000000000000000000000000000000000002a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF16C1000000000144841911A959543320000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFA1A30000000000A38898C18AB88A0920000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFA48600000000001088B84384180000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFD3290000000000B2085805A018C02800000000aa0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF967600000000000184380190580004400000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF22250000000000AA801889801CAA088000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FFAFE9000000000001841811801800040000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF612D0000000000108011138058000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF249F0000000000018018018318000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFF54D0000000000008890258298000000000000000000000000000000000000000000000000000000000000000000ea0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFCE\n\t520000000000B30AB8C80AB80000180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFF37900000000014C15591011380000180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF83FC000000000001001800001800001800000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF3ACE0000000000A38AB821881800000000000000001a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF5B88000000000001001800001A00201800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF15520000000000AB0AB88C0AB8000018000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF24940000000000000018420418000018000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA6\n\t56000000000001001800041C0040180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF2DBC00000000000B10180001180000180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF8257000000000001001824001800001800000000000000000000000000000000000000000000000000000000000000005a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF898200\n\t0000000001000000000000001800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF5D44000000000001000010001822001800100000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFF31E0000000000151000000318000018000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF83FC000000000001001800001800001800000000000000da0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF0BCC0000000000010019000800000010000800000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF6B\n\tCA00000000000100180000000000500000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFB37700000000000100009008004406380000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA10200\n\t00000000AA8A28000CE800090800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF2BC7000000000001011800040000050000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF133A000000000001801800000000002000000000000000000000000000000000000000000000000000000000000000000000ba0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFEA460000000000559558001158001558000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF96\n\t890000000000AA8B28000888000A280000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF4A0700000000010000000002000000000000000000000000007a0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF801D00000000010001000000200000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF1CA600000000002A8A28000A88000AA800000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0DC8000000\n\t000000800800A008008000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF2A9A0000000000000000002000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB0\n\tF70000000002000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000060040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFE0CC000000000200800C00C00800A0000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC16A00\n\t0000000001801801001801800000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF61E800000000000100000100000020000000000000000000000000860040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFEA9B000000000000001800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC916000000\n\t000000001A012000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF1743000000000000000800800A008000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000460040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF35E10000000000\n\t08800001181A0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF68E900000000000094580180100100000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB90200\n\t000000001000180400100100000000000000000000000000000000000000000000000000000000000000000000000000000000c60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000180\n\t1901001A01800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFFE6B000000000001800001101801800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB3B4000000\n\t0000018C0003001A018000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF6EA8000000000000802101001801800000000000000000000000000000260040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF65430000000000119058011014018000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF913A0000000000\n\t0180180111180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF03C300000000000180180100980180000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB5A00000a60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFE72C00000000000180\n\tB803305801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF0074000000000201801805005801800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0C09000000\n\t000201891A01401801800000000000000000000000000000000000000000000000000000000000000000000000000000000000660040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010240001801\n\t8018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFC16A0000000000018018010018018000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF46710000000000\n\t31809C01401C0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF8560000000010001801801001A018000000000000000000000000000000000e60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF8EF400000000000000100180180180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF28F500000000000000\n\t1801801801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF440C000000000400009001A01801801800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD48300000000160040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF90FE000000000000001801\n\t801A018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF8EF40000000000000010018018018018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF28F50000000000\n\t000018018018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000960040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000010012\n\t0180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFEEDE00000000000000100180100180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFF0D400000000000000\n\t1801801201801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF8EF400000000000000100180180180180000000000000000000000000000000000560040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF48480000000000001008AD901D418C1800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF82F5000000000000000001\n\t8018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF44DE0000000000000008018010018018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB2D3000000000000d60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF511100000000000000190C0000\n\t4008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF137800000000006400100124288190180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFAED200000000002020\n\t1A01023A03A0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000360040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0C10C40C20CA\n\t0800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFEE3F000000000000200402200220021000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF1C090000000000000008B0\n\t9808018008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF9FB1000000000400081800020102040000000000000000000000000000000000000000b60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FFDA61000000000100210A20A40A00A008000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF1D930000000002342002883012\n\t2900100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFF28200000000002200190388108180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFD4FD0000000000004000760040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF3BDA00000000040C3541202C031220\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF7797000000000200410040000400000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF83D30000000000000A2002\n\t00A082000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f60040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (A00800800800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF32050000000004A80A22160AA0AA0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF830E0000000000C000020A0120\n\t2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFC2790000000000CA0A22804AA0AA00000000000000000000000000000000000000000000000e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFB8D9000000000400800C00C00C00C0080000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF193700000000000184180100180180\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF99B2000000000005208089000200000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFC421000000000200800820008e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF813A000000000210021A01200200200000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF6DA50000000000000408008208008008000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF7A580000000000100000001C00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (059418000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF900800000000000080990982304082100000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF156C00000000000004B84410100080\n\t1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF67980000000000000058A208002208000000000000000000000000000000000000000000000000ce0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFF0D00000000000018A201908B8AB8AB800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF7237000000000001810025001801C01800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFBBF30000000000008001010418018018000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFAD6B0000000000008000110458002e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF83820000000000019459551499559558000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF5DD70000000000018A388508D8AB8AB80000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFB97A00000000000180980100180180\n\t180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFF15A000000000001801801089801801800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF74DC0000000000018AB8AB0058ABCAB800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF0B2E0000000000018118410212008018000000000000000000000000000000000000000000000000006e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF6A180000000001238A38030018010818000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF8AAA0000000000018118510559138558000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF65AC00000000011180188110182180180000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFE293000000000001801801025C018000ee0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF7F020000000000C98A30A10AB02B8AA00000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFECC30000000000099441490CD101914000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF3B88000000000001801011001101800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFF22D00000000000180125100104D8000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF19590000000000AF8BB0070AB0018AA0000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF8AF100000000004381000300103384000000000000000000000000000000000000000000000000000000009e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFD20000000000000180100104100180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF6BD200000000000180140512100180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF3797000000000101801001001401C00000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF7EDD000000000001801081001081000000005e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF366E000000000100801005001001802000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF7EB5000000000001801023001201A000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFEDC00000000000018010010810018000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFDD2B00000000000000104404000104000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF9F9200000000000080100180180100000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF81070000000000008010011A1019824000000000000000000000000000000000000000000000000000000000003e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tB724000000000042080482140000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFDD020000000000060AA906800800800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF544A0000000000000010511550540000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF6860000000000130001900000080000000000000be0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF81D50000000001110004110011080000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE14B00000000011185584941515580000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF24C40000000000408AA82094A82280000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t5FDD000000000020000300200000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFC7AA000000000000080050154000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF5F7D80000000008A82AC028008AA800000000000000000000000000000000000000000000000000000000000000000fe0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF9323\n\t0000000000000000000010010010000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF7641000000000000800A008008008008000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000010040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF908A00000000000000000000000000100000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t62BD000000000000800A00C00800C00800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF88DE000000000001801A01801001801800000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000810040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFBA3D0000000000000000012010004000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF9F3C000000000000800C008008018008000000000000000000000000000000000000000000000000000000000000000000410040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF3F7C0000\n\t00040009A01801C0100180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFC15D00000000001180180180100180180000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t3509000000000101C01801801801801800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF334A00000000000100110180000180180000000000000000c10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FFA25E000000000001801C01801001801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75B9\n\t000000000401801801C014018018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF8301000000000101801881C010018018000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000210040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF42440000\n\t00000001901801A0120180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFA25E000000000001801C0180100180180000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t49A800000004040180180100100180180000000000000000000000000000000000000000000000000000000000000000000000a10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D55E00000000\n\t0005801801801001801800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF2FC5000000000201901801801203801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2585\n\t000000000201E01841E010058018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF515F000000000001801801801001801800000000000000000000610040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FFCB6C0000000000040012018018018000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF515F0000\n\t0000000180180180100180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFA27B00000000000180184180140180180000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00e10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF96EC00000000\n\t0000001001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF96EC000000000000001001801801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF65ED\n\t000000000000001401801801800000000000000000000000000000000000000000000000000000000000000000000000000000110040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000400\n\t0010018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFF6C60000000000000010018010018000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF96EC0000\n\t0000000000100180180180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF96EC0000000000000010018018018000000000000000000000000000910040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF96EC00000000000000100180180180000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF96EC00000000\n\t0000001001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF561D000000000400001001801801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF561D00510040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF6444000000000000\n\t1050C58099208400000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF55110000000000000010018018008000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF96EC0000\n\t000000000010018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000d10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000280000\n\t0002058200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF28B600000000000000000008200002000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAE2400000000\n\t00800A9021959021000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFBE930000000000D022921132320300000000000000000000000000000000310040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF6383000000000020420C00D4CD00800000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2E74000000000200\n\t20228A2040002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF5CC30000000000400409008008408000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD7D6000000b10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF0D0C000000000310308B\n\t24A9080080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF365C00000000024424420844020020000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF490D00000000\n\t000000188180182180000000000000000000000000000000000000000000000000000000000000000000000000000000000000710040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00AA0AA0AA42\n\t80AA0AA000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF3AE000000000035434C294450154154000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF77DB000000000000\n\t4004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFF3130000000000000000000020AA0AA000000000000000000000000000000000f10040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FFE3E7000000000000800800A908000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF72790000000000AA0AA0\n\tAA1060AA0AA00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFAB2800000000000000002008200000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3A8C0000000000090040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF866F000000000400C00800C0\n\t0C00400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFDB27000000000001801805911000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9F2F000000000001\n\t200200041000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000890040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (009883800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF80A9000000000000001803A012002000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF0C7F0000000000018008\n\t8098880000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFA26A0000000004004007000000000000000000000000000000000000000000000000490040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF113900000000000180188380110000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF2AFC00000000000181180180\n\t18A0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF2111000000000001801801900040000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF54E100000000000000c90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF8FD70000000000018AB855807080\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFA589000000000001C018118410400000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFC33F0000000000018019\n\t4590900C0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000290040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018814100000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF7D2500000000000195595595510C20000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFC8060000000004018ABC8182\n\t90A2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF2B3A00000000000180180180100020000000000000000000000000000000000000000000a90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FFE3C3000000000001801201001040000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFFCC6000000000201801801801204\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFECE2000000000001CAB8AB8AB0C80000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF6E10000000000001801800690040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF74FA0000000000AB8AB8AB8810000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF014700000000000180100101500000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF9E0400000000000180180184\n\t100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (100000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF48A00000000000AA0AB8AB833000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF462F0000000001541559558C5000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFC7C4000000000000001801901000000000000000000000000000000000000000000000000000190040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FFD50E0000000000000018018C12000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFAFBE000000000000001C01A150002000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF87FB0000000000AA0AB8AB80100000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF97940000000000000018018100990040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF6E8100000001000004180180100000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF9E61000000000000001C85D01200400000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF4B45000000000000001901841000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000590040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF550E0000000000000018058010020000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF86EB0000000000000400800010000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFBECD0000000080000200000A10000000000000000000000000000000000000000000000000000000d90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF27D800000000000000980184000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF46BF00000000000004008000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFE0E5000000000000000000001800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF9D3400000000000000180180100400390040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFE3CA000000000000001000210000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF69F40000000000000A28A30008000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF03A70000000000000018099150000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF43B200000000020000900130100000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF1C190000000000001551550C500000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFDE330000000004000A28AA83280000000000000000000000000000000000000000000000000000000000790040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF991A000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF35B5000000000000008008040000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFD19E0000000000000000001140000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF0FFC8000000000000A28A2E00800000000f90040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFA29500000000000000080140000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFD096000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF915B000000000000400A00200000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF7A96000000000000001801000000000000000000000000000000000000000000000000000000000000000000850040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF92910000000000000018018000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF50B000000000000020180180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE69A0000000000000008000000000000000000450040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF624B00000000008000190180010000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF5343000000000100201855800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFB39A000000000000000400000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF625A0000000000400019018001000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFE0A10000000001200000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF70540000000000000004540000000000000000000000000000000000000000000000000000000000000000000000250040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF54\n\tF0000000000000001C0188000800000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE95100000000000040180194001000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF93BD000000000100101801800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF521800000000000008180180000000000000000000a50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF9384000000100000201881810000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFA4C1000000000000001D418200000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF5F400000000000002019418000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000650040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBA\n\t34000000101801801C0180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFB68800000000000401980180000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF43E8000000000202001C0180000000000000000000000000000000000000000000000000000000000000000000000000e50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF313000\n\t0000021801801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF8931000000001801801801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF89310000000018018018018000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF4AF0000000001C01801881810000000000000000000000150040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF89310000000018018018018000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF35\n\t80000000021C01C0180180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF7A30000000001801801C0180000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000950040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5B3B00\n\t0000001801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF8B69000000001A01A01801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF3AB1000000001801801A01A00000000000000000000000000000000000000000000000000000000000000000000000000000550040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF9225000000\n\t241A03AC02000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFC512000000011821805F418100000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF49\n\t3A00000020180180180180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF4F2C0000004018018000004000000000000000000000000000d50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFEA1900000002000008180180000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF91A100\n\t0000000000001821808000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF4DBB000000009801000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000350040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3059000000\n\t400C00C00C008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF042A0000000000222422C00000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF7C\n\t150000000018008208010000000000000000000000000000000000000000000000000000000000000000000000000000000000b50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (D20000000000\n\t000A20A200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFE623000000200A00A00A01A0000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF988D00\n\t0000001000210208000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF60EA00000000180184182100000000000000000000000000000000750040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFFFB50000000000000A20AA000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB1C9000000\n\t2002003543444000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF773A0000000004004104000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3F00f50040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF37CA0000000008\n\t0081080180080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF3FD20000000000000A20A200000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80FC00\n\t0000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000040041040\n\t0000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFB742000000400C00C00804C00800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC148000000\n\t0018018018010018000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF9BDB0000000002002002100010000000000000000000000000000000008d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF1D860000000000001058018000800000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF1AA20000000000\n\t0800180580000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFA676000000000800800A0100000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC03E00004d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF5D4400000000180180\n\t3800801900000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF22C4000000001801800200001800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA2A1000000\n\t001001080001001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001C01809A00\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF15F40000000ABA118A20A20018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA1BF0000000019\n\t2B80001100180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF494700000000180180980180180000000000000000000000000000000000002d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FFCF55000000001805A1180180100000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFE98300000015595594\n\t5B54801000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF4E790000002AB8C18A3AAB801800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC03A00000000ad0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF1DF4000000001801C11810\n\t8010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF896E0000002018018018018010000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB43B0000000AB8\n\tAB8A3AA280100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018118010000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF28A40000000118018A38A38A900000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF0AB500000000B92B80\n\t1808801000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFB82500000014180181180180500000000000000000000000000000000000000000ed0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FFE4160000000C4049801800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFF5E60000000AA0AB8A38A3\n\t0AA0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF6B2C0000000001039559541540000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA3060000000000001d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF63160000000000018018010000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFA3DB00000000000180181100000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF55230000000AA0AB8A\n\tB8B30AA000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000100000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF6316000000000001801801000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF6316000000000001801801\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF2B1D0000004000898018010000000000000000000000000000000000000000000000005d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF36340000000000018218011000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF63160000000000018018010000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFE39C00000020000180000108000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF990B0000000000918000dd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF929100000000000000180180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF0935000000000001820001000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFC916000000000001800001\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF5D5B0000000000010001000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF7F2B0000000000AA8A38AA8000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF1A9E0000000000000098010000000000000000000000000000000000000000000000000000bd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF15C28000000006AA8A282A80000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF9D9B00000000000100100000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF0BAE000000000155955055800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFB33A0000000000AA8B28AA007d0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFEC520000000000000081000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF40A700000000100000000000000100000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFADA3000000000800800A00A00A0080\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF2A9A00000000000000000020000000000000000000000000000000000000000000000000000000030040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF6435000000001800A00800800801800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFB39A000000000000000400000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFBBE8000000000800C00A008008008000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFC2D9000000001801801A01801C00830040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFA1B90000000818810400010010018000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFEA9B00000000000000180000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFEA9B00000000000000180000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000430040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFBBB5000000041C01821807801801800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFEB70000000001881811805801801800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF58CC000000001801800201801801800000000000000000000000000000000000000000000000000000c30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FFC355000000041801801A418098018000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF2E2E0000000018018018058118018000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF4C6C000000001A0180012180180180000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF58C60000000818018082018018018000230040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF332600000000185986180180180180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFD84C000000001801801C01801801800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFED2C000000001801801881801801800000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF902B0000000318018018098018418000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFF2CC000000001801801A018018018000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF954E000000001801801801E018018000000000000000000000000000000000000000000000000000000000630040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF3002000000020001C0180181000180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF0A5E00000001000180181180002180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF62C1000000001801801A00801801800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFEBCB000000001841A0180180980180000000e30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF8913000000000001801801800001800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF89130000000000018018018000018000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF89130000000000018018018000018000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000130040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF496A00000000020180180180000180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF888B00000000000198180180000180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFBBD6000000000401A0180180040180000000000000000000000000000000000000000000000000000000000000930040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t2583000000000401800081800001800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFE752000000000001C00001800001800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF4B32000000000001A018018000018000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF75C7000000000001801901800401800000000000530040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF4E6C000000000289A802018A028B8000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFAF22000000010005A0590B80200180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF496A00000000020180180180000180000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t5E3D0000000000020418820C2004000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF8AE100000000000000190002008A000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF3C7B000000008081880001800001000000000000000000000000000000000000000000000000000000000000000000330040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF48C1\n\t0000000000418418218000018000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF05E2000000000400D02C888404048000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF3ACF00000020020930625820020000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF57E00000000000408008018000008000000000000000b30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FFE0880000000AA0000AA0000020AA00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tACC0000000200030A00A10940000800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF40E9000000200283200343210200000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000730040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFCE69\n\t0000000AA0AA0A20820AA0AA0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF89760000003540103442941521540000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF93D50000000004004000504000000000000000000000000000000000000000000000000000000000000000000000000000f30040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFE8D20000\n\t0000020021000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF034200000000080000091480000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t69980000000AA0AA0B20200AA0AA000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFC5130000000000A4008020000000000000000000000000000b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF934B000000440400464400400400000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF1CCF\n\t000000400C00400C00C004000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFF3860000000018400098418000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8F330000\n\t000001000098D000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF19A400000004002000984000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tD77E000000000800002800800000000000000000000000000000000000000000000000000000000000000000000000000000004b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (515A00000000\n\t1800009801800088000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF37260000000018000098A9800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9AEC\n\t0000000019000000019E00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF1357000000001000000001000000000000000000000000000000cb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF5029000000001E000118018000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF487E0000\n\t000018AA0A20AB80000200000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF05B000000000180000000180004000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF002b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF416B00000000\n\t1800201801C00002000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF49EB000000001954145955800154000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF7272\n\t0000002018AA0ABAAB8004A8000000000000000000000000000000000000000000000000000000000000000000000000000000ab0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000041800\n\t0118458000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFE770000000001800401A01A000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF50BA0000\n\t0020180000180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF241F0000000018AA0AB8AB8002AA00000000000000000000000000006b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF5BF400000000000101180000180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF67D00000008\n\t98000A3809800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF9BF1000000003800001901800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF63A300eb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB71E0000000B2001\n\t8018A00018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF2DC80000000AA0018A38AA0018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA2700000\n\t0000000195580C00180000000000000000000000000000000000000000000000000000000000000000000000000000000000001b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0004040182B9\n\t20001A0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF536500000000000180180000180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF536000000040\n\t0001811800001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF2DC80000000AA0018A38AA001800000000000000000000000000000000009b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FFE54E0000000002018520C0005800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF7983000000000001\n\t801E100038000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFA37B000000200001801800001C000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAEEF0000005b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF6B140000000000019018\n\t8000184000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF632000000004000188181000180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA51800000000\n\t000184804000184000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (014401180000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFA29A000000000008001800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3A01000000000001\n\t8500400018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF35A40000000000018001000018000000000000000000000000000000000000003b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF7EBD00000000004A8AA8000AA8000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF78D30000000001008A38000AB80000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFAEB90000000000bb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF60A18000000000AA8A28006A\n\tA800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF8CCE000000000000001000001000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5450000000000155\n\t9550001558000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF85240000000000004000280000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF20930000000000000080\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000fb0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF842D000000000001801929801801A0000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF184200000000000100020100\n\t1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFA1A8000000000000800880800800800000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF991A00000000000000070040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF354F000000000000A00801801800\n\tC000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF481B0000000000010002000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF67C90000000000008008\n\t008008008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000870040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF3CA700000002000185008180180100000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B00000000000000180000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF199A000000000000001C0000000000000000000000000000000000000000000000000000470040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF3165000000020001808001A01801800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF59AD000000000011821A81801841\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF2BC50000000000018018618018018000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFB24D000000000001A00400c70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFDF3B0000000000518398818018018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFFCED000000000001801801A0182180000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFC8AE00000002004180041180\n\t180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000270040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF2BE4000000000041807801881801800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF7383000000002001C11A15941801\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF5785000000020001841891801801800000000000000000000000000000000000000000000000a70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF2E41000000000041801881C418018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF4A7A000000002043801A038018418000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFE41A000000002001809815A0180180000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF2F0D000000000001E018018000670040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF5ACB00000000380580580180180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF56C0000000001841801801801820000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF8246000000000001C1BB7D801801\n\t800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFE85E0000000018019018018018000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF294F0000000018018018018018000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFEB6E000000001801A018018018000000000000000000000000000000000000000000000000000000170040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF0509000000001801C0180100180000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFF130000000001801801A2980180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF2B81000000001801AE1801801800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFDA4E000000001801801C0180180000970040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF82B1000000001801800029801800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF5ACE0000000018018002018018000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFE9BE000000001C018018018018000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000570040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFE8D6000000201A85A2C283A9380200800000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFF67A0000000B1A5180180184190002000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFF0CE000000001801801A0180180000000000000000000000000000000000000000000000000000000000d70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFD9B7000000008808866800800800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF0B79000000000002009803092080028000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF38CD0000000300200018800280120000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF8BF9000000081881000001801000000000370040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF294F0000000018018018018018000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFBEA1000000408C00C42C88C1081000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF868500000000120020031020020000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF55890000000000AA0A20AA0AA180000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF09EE000000000A00A00A00A00808000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF32E1000000001200210200200222000000000000000000000000000000000000000000000000000000000000770040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFFBF5A0000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF0E140000000000AA0A20AA0AA0AA0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFAF8800000000035435435435404400000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF53D60000004004004004004004004000000000f70040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FFE93C00000020020020020020020020000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFC63E000000000000808800800800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFCE040000000000AA0B20AA0AA0AA000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF580000000040040048051041A4004000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFB4A7000000400400C80C00C04C004000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FFAF6E00000000000580180180180000000000000000000000000000000000000000000000000000000000000000008f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF69\n\tBF00000000000181400300104400000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF41E400000000004000384400002400000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFEA9B000000000000001800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF4231000000000002800888800800000000000000004f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF8D7D00000000002B80188B823800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFE0120000000000010018518018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFE10E0000000000418080098018000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2B\n\t6F00000000000180180180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFF72F0000002AA2058A202188180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFE3D1000000000081808001809800000000000000000000000000000000000000000000000000000000000000000000002f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFA47900\n\t00000AA0AB8A3AAB8AB800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF767B000000000001801833D11A00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF46230000003543559559559558000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF9F580000000AA131AB3C81823800200000000000000000af0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF74390000000000318099418038000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFDB\n\t6A000000000001811801801C0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE330000000000001A01801A0180020000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF335500\n\t0000001801801801801801801800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFD7A60000000000038A3901821800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFBB5700000000010180180D911800000000000000000000000000000000000000000000000000000000000000000000000000ef0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF6451000000\n\t0018AB8B38AB8AB8018018000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF319900000000184D8018218338018018000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA4\n\t410000000018AB8A38AB8AB80180180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF375700000000190195580B90180180180000000000000000001f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFAC8D000000401949801851A0188180180000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF004400\n\t0000001801811C01801801801800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFF3A4000000001C01801801801801801800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF1F57000000\n\t0419118402518019018018000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF3144000000041801901C018018018018000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9E\n\tEC000000001C218C1A01C0180180180000000000000000000000000000000000000000000000000000000000000000000000005f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (BF0000000018\n\t0180000184380180180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF131300000000180180195180380580380000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF2AA00\n\t0000001801801889801803801800000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF971100000040180182204184180180180000000000000000000000df0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFE421000000000080001910008000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD835000000\n\t1120000098420220000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFF8150000000010010440000010018058000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8C003f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF25DD00000008C9\n\t508AA82A8028AA8AA80000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFE10A00000000000000802000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF36C000\n\t000006082E8A38008808AB8AB80000000000000000000000000000000000000000000000000000000000000000000000000000bf0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000001\n\t000C000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF10C70000000AA8AA8A29008AACAA8AA800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF16A6000000\n\t0000000011001500010010000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFB1B300000015595594500B955955D558000000000000000000000000007f0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF80840000000000800000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF2F1400000000000000014000000020000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB0CB0000ff0040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF294F00000000180180\n\t1801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF9266000000001101000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA5F6000000\n\t000800A00800800800000000000000000000000000000000000000000000000000000000000000000000000000000000000000008040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF67D70000000008008008008008000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF525B0000000010\n\t0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFA5F6000000000800A008008008000000000000000000000000000000000000808040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FFE34700000000180180800180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF736700000000181180\n\t0001801000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFEA9B000000000000001800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B00000000408040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF0B40000000001849800001\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF2EB70000000018018018A18018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF86B90000000018\n\t418099418018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018018018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFED0E000000001801C0180180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF294F00000000180180\n\t1801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF470E000000001801C0000180180000000000000000000000000000000000000000208040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF434E000000001801801801A01800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF2BF6000000001801811801\n\t8098000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFEAB20000000018018018918118000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF294F000000001800a08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFE9E4000000001801A218018098\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFE80B00000000180181183180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF2F4A00000000180180\n\t9911A0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000608040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180180180\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFECE1000000000001811811811801800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF496F000000080001801801\n\t8018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFA23E000000081801841841001800000000000000000000000000000000000000000000e08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF296D0000000000018018018018018000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF496F0000000800018018018018\n\t0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF296D00000000000180180180180180000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFEB4C000000000001A000108040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF296D00000000000180180180180180\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF296D000000000001801801801801800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF296D000000000001801801\n\t801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000908040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (801801800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF646A000000100001800401C018018000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF414C000000000001A000018018\n\t0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF3D7A000000400001801801C018018000000000000000000000000000000000000000000000508040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF043900000004800100000180100100000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF4916000000000201AA0225A09A0180\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFCF1F00000021010180181194592B800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF32CD000000000001A01A0100d08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF02D8000000000080800823880880800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF5A6200000000000004180802A0220000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF165E0000000000000059000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000308040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF30B300000000000184382180180180000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF0A0F000000020400C00C80C00C0080\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF2D320000002002002A024020000800000000000000000000000000000000000000000000000000b08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF47CE000000000000400400000400000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF7BE70000000AA0AA0A2008088000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFDB3B000000200000A00B20A008008000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFAA93000000200200210205224000708040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF6B5E0000000000000100300800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF76040000000AA0AA0AA0AA0AA00000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFCD1A00000035415434430424C00000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f08040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFEF75000000000000211200001200000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFAF56000000000800000800800800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF160C0000000AA0AA0A20AA0AA000000000000000000000000000000000000000000000000000000000088040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF031A0000000008000018028018000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFA2880000004004105884044004000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF7315000000400C00400D40C00C0000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFF6C60000000018000090018018000000888040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FFBF2800000000100000100100180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF5858000000000000001900000080000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFA5620000000000080018A0000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000488040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF87780000000019100098018259240000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFC59A0000000018000008C18019000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF64B40000000019800000218618180000000000000000000000000000000000000000000000000000000000c88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFC7800000000018040B38AB8238A200000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF5CC600000000180000880180180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFA51E0000002019020A20AB989808000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF062D000000001C20001001801C0000000000288040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FFE2AD000000001CAA0AA8AB8ABCAA000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF2152000000001850201C01A118080000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF61DB0000002019541449559559540000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFFCED00000005180001180580180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF2C8D000000001800400801C0180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFE94E000000001800001A0180180000000000000000000000000000000000000000000000000000000000000000688040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t0D42000000032000154031954001800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF3692000000000000001001800001800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFAA750000000818000A38058AB8000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF3C7A0000000038000008B1801800000000000000e88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF6A1D0000000AA0000A30AB8AA0018000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF9CF000000008000000008180000180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF0A150000000AA0000AB0AB8AA00180000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000188040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t0952000000000000001501800001800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF966B000000000400009001800001800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFF687000000400000001001800001800000000000000000000000000000000000000000000000000000000000000000988040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF8A4C\n\t0000000000000010818800019000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF29720000000000000012818000018000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF369200000000000000100180000180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF36E00000002002000010018000018000000000000000588040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF8E5E00000000000000110384400180000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t04BF00000000000000100B902003800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFFC33000000000000001001820001800000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF805B\n\t0000000000000011000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF8B7C00000000000000182A0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF991C0000000000000010090000058800000000000000000000000000000000000000000000000000000000000000000000388040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF36F90000\n\t00000000055955A0015580000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF62FF0000000000000AA9088000AA80000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t43EF000000000000080000000001000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF6D5A0000000000000AA8448000AA80000000000000000000b88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF708E000000000000000000000400000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9942\n\t80000000000002A8AA8004AA8000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF57640000000000000000004000010000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000788040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF83AA0000\n\t0000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF589900000000000000200000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t801200000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000f88040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (910000000000\n\t0000200A00C00C00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFEB74000000000000003821801800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF976E\n\t0000000000002012000010000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF6EB7000000000000000800800800000000000000000000000000048040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF94990000000000000000004000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA2E20000\n\t0000000000180080180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF708E00000000000000000000040000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00848040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF6AE00000000\n\t0000401801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFFF90000000000100005801041800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000448040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t201A018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFF9C80000000000800018218218000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2AED0000\n\t0000000000380180180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF02DF000000000000001C418018000000000000000000000000000000c48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FFDA4E000000000000201E0180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF32EF00000000\n\t0000001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF32EF000000000000001801801800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF294F00248040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF793000000000100\n\t011A418018080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF02410000000000000058198018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE94E0000\n\t000000002019018418000000000000000000000000000000000000000000000000000000000000000000000000000000000000a48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000004018\n\t0180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF186F00000000000000180184181000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF32EF00000000\n\t0000001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF548300000000008000BAA180180000000000000000000000000000000000648040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF24A4000000000000400000001800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E5000000000000\n\t0000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFE0E50000000000000000000018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF6AE000000e48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E50000000000000000\n\t0000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFE0E500000000000000000000180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E500000000\n\t000000000000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000148040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFE0E5000000000000000000001800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E5000000000000\n\t0000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFC8E3000000000000006000001800000000000000000000000000000000000000948040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF22C40000000000002000000018000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E50000000000000000\n\t0000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFE0E500000000000000000000180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E50000000000548040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFF05800000000000A00419A00\n\t1060000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFCBB80000001000800800102018C0000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA0E6000000010012\n\t2500C210D810000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (280200200000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF6BC70000000080800080000808080000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFD8DD0000000800000200\n\t2001210000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF3C340000001000000000000080800000000000000000000000000000000000000000348040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF512300000000000020020220000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE0E500000000000000000000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF0EE70000000800000020884108C0000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF1B300000000000000b48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF472A000000400400400400000400\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFD9280000000000000AA0400AA0000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF4EFD0000002002002003\n\t30000A000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000748040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (AA0AA0000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF8C5A00000000000000010000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFBD9F0000000000000AA0AA0A\n\tA000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF56B900000020020035421415420000000000000000000000000000000000000000000000f48040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF00C2000000001805801941800001800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFE37E000000201200200200000201\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFC6020000000008008008008000008000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFBD9F0000000000000AA0000c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF92C60000000008008008A08000018000\n\t0001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF5A2300000040140240641040040000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF15B1000000400C00C00C00C0\n\t0400800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF8CAF000000001901011041000001820000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF048A000000000080000000000000\n\t0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF80FC0000000000000000080000000000000000000000000000000000000000000000000000004c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF8B330000000018018018018000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF81390000000018018018018220018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFA60300000000180180180181000180000000800000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE80B0000000018018098218000cc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF3B6A000000001A01A0180182220180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF8B33000000001801801801800001800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFBA91000000201801801A01888001\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFA9110000000018018018018AA0018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFB162000000001801801801B100018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFFC7D000000201801801C019540018000000000000000000000000000000000000000000000000000ac8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF478A00000000190190193180000180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE11000000000181381380580000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF5F31000000001801801801C00001800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF3160000000001A01A01801800201006c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF0327000000155885805915800155800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF87320000000018018008018000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFA02C0000000AB8318318418000AB8000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF46150000000AB8AB8AB8AB8000AB80000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF4B970000000018418A180180000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF46150000000AB8AB8AB8AB8000AB800000000000000000000000000000000000000000000000000000001c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF5D77000000001801A01809C00001800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF2E33000000005801801801A00001800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF8B330000000018018018018000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF4F72000000001801C018018000018000009c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF8B330000000018018018018000018000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF8B3300000000180180180180000180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF4BFE00000000180180181180000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF8B33000000001801801801800001800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF8B33000000001801801801800001800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF8455000000005801801809800001800000000000000000000000000000000000000000000000000000000000dc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF646D0000001808AB9608AA8000208000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFB9CF0000000120001000000001100000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF6F7100000004000001200000000200000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFEDE100000000100180101180000100000000003c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FFA06900000015595585195580015580000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFCB850000000088AA8028AA80008A800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF6999000000400000100001000200000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF818A0000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFC9898000000AAEAA804EAA8000AA8000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF519E00000042200100800100042000000000000000000000000000000000000000000000000000000000000000007c8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF58AA00000000000003200000000000000000000000fc8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000828040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFFCC100\n\t0000000000402002000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF70BD0000000000000140040000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000428040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF82BA0000000000002000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF20\n\t9300000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF6A1B00\n\t0000000000000600000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000228040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80\n\tFC00000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF80560000000000000000100000000000000000000000000000a28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000628040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000128040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000928040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000528040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000d28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000328040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF77DB0000000000004004000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000728040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000f28040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF5B3B0000000000002002000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF77DB00000000000040\n\t0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF77DB000000000000400400000000000000000000000000000000000000000000008a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000004a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF5B3B000000000000200200\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000002a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF77DB0000000000004004000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000aa8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF92910000000000000018018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF92910000000000000018018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000ea8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF929100000000000000180180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF929100000000000000180180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF9291000000000000001801800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF9291000000000000001801001a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF9291000000000000001801800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF92910000000000000018018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF92910000000000000018018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF929100000000000000180180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF929100000000000000180180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF9291000000000000001801800000000000000000000000000000000000000000000000000000005a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF9291000000000000001801800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF9291000000000000001801800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF92910000000000000018018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF9291000000000000001801800000da8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFD1BB0000000000000AA8AA8000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF6CDE000000000000155955800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFD1BB0000000000000AA8AA800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFDC97000000000000001001000000000000000000000000000000000000000000000000000000000000ba8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF77DB0000000000004004000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF46FA8000000000004AACAA80000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFDC9700000000000000100100000000007a8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000068040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000868040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000468040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000c68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000268040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000668040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000e68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000168040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000968040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000568040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000368040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000b68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00768040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f68040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B008e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000ce8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000002e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000006e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000ee8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000009e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000005e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000003e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000be8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000fe8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000018040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000818040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF097A0000000000000000000000000000\n\t0000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF097A0000000000000000000000000000000000000008000000000000000000000000000000000000418040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000c18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000218040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000a18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000618040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000118040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000918040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000518040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000318040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000718040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000f18040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000098040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000898040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000498040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000298040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000a98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000698040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000198040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000998040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000598040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000d98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000398040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000798040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF86FA000000000000000080\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000f98040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF8C5A00000000000000\n\t010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000058040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000858040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000458040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000258040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000a58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000658040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000e58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000158040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000958040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000558040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000d58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000358040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000b58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000758040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f58040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000008d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000002d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ad8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000ed8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000005d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00dd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000bd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A007d8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000038040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000838040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000438040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000c38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000238040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000638040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000e38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000138040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000938040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000538040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000338040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000b38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000738040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000f38040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000004b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000cb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000ab8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000006b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000009b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000003b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000fb8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000078040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000878040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000478040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000c78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000278040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000a78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000678040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000178040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000978040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000578040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000d78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000378040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000778040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000f78040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000008f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000004f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000002f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000af8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000ef8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000001f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000005f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000df8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000bf8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000007f8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ff8040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000804040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000404040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000204040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000604040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000e04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00104040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000904040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000504040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00d04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000304040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000b04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000704040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f04040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000084040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000884040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000484040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000c84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000284040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000684040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000e84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000184040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000984040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000584040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000384040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000b84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000784040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000f84040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000044040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000844040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000444040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000c44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000244040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000644040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000144040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000944040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000544040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000344040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000744040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000f44040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40000c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000004c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000cc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000ac4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000006c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ec4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000001c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000009c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000dc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000003c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000007c4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000fc4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000824040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000424040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000224040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000a24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000624040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000e24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000124040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000924040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000524040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000d24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000324040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000724040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f24040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000008a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000002a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF00aa4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000ea4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE001a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000005a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000da4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000ba4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF8C5A0000000000000001000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000007a4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF8C5A000000000000000100000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000064040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000864040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000464040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000c64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000264040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000664040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000e64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000164040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000964040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000564040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000364040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000b64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000764040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000f64040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000ce4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0004FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000006e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000009e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000003e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000be4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000fe4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000014040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000814040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000414040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000c14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000214040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000a14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000614040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000114040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000914040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000514040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000d14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000314040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000714040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000f14040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000094040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000894040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000494040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000294040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000a94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000694040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000004FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000e94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000194040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000994040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000594040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000d94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000394040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE09A8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000794040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f94040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000054040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000854040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00454040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000254040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00a54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000654040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000e54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000154040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000954040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000554040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000d54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000354040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000b54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000754040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f54040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000008d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000cd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000000000000000002d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ad4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000006d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000ed4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000009d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000005d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000003d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000bd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007d4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000034040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000834040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000434040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF75DE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000c34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75\n\tDE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000004FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000234040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000634040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF75DE000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400e34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000134040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000934040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000534040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000334040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000b34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000734040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000f34040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000004b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000cb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000ab4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000006b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000001b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000009b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000db4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000003b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000007b4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000fb4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000074040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000874040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000474040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000274040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000004FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000a74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t04FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000674040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000174040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000974040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000574040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000d74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000374040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000774040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00f74040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000008f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B004f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000002f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000af4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000ef4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000001f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000005f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000df4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000bf4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000007f4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ff4040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000080c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000c0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000020c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000060c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000000000000000e0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000090c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000050c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000030c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000b0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000070c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000008c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000088c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000048c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF75DE000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000c8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040028c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (DE0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000068c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF7500e8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000098c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000058c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000038c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000b8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF83AA000000000000000040\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF83AA0000000000\n\t00000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000078c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000f8c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000004c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000084c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000044c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000c4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000a4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000064c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000014c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000094c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000054c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000d4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000034c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000074c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000f4c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000008cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000004cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t04FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ccc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000acc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF\n\t75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ecc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000001cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000dcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF003cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000007cc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00fcc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000082c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000042c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000000022c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000a2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000062c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000e2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000012c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000092c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000052c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000d2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000032c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000b2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000072c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f2c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000008ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000004FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000cac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000000002ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000006ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000eac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000005ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000bac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007ac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fac040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000006c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000086c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000046c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (DE0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000004FF409B00000000000000000000000000000000000000000000000000c6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF750026c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000004FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF75DE000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000066c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000e6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000016c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000096c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000056c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000036c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000b6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000f6c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000004ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000cec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000004FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000aec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000006ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000001ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000009ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000dec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000003ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000007ec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000fec040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000004FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000041c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF\n\t75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000021c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (04FF75DE0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000a1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000061c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000011c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0091c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000051c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000d1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0031c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000071c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000f1c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000089c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000049c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000029c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000004FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000a9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000069c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000e9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000019c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000099c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000059c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000d9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000039c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000b9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000079c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f9c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000005c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000085c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000045c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000c5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE000000000000000000000000000000000025c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF75DE0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000065c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000e5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000015c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000095c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000055c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000035c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000b5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000075c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f5c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40008dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000000000cdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF75DE00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00002dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000adc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF75DE0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000000000000000000000006dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000edc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000009dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000005dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ddc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000000000000000003dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000bdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007dc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000fdc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF097A0000000000000000000003c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000083c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000043c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000c3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000023c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000a3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000063c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000013c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000093c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000053c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000d3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000033c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000073c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000f3c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000004bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000abc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF006bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ebc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000001bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B009bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000dbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A8000003bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF80FC00000000000000000800000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF80560000000000000000100000000000000000000000000000000000000000007bc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000fbc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000087c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000047c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF689B600000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000027c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000a7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000067c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000e7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000017c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000097c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000057c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000d7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000037c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000b7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000077c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f7c040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000008fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000002fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000afc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000efc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000005fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000bfc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40007fc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffc040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000002040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000802040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000402040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000c02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000202040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000602040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000e02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000102040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000902040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000502040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF80AA004000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF80820020000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000302040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000b02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000702040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000f02040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000082040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000882040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000482040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000c82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000282040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000a82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000682040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000182040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000982040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000582040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tE09A800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000382040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000782040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000f82040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF949A\n\t0000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF949A0000\n\t4000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000842040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000442040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00c42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000242040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000a42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00642040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000142040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000942040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000542040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000d42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000342040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000742040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000f42040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000008c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000004c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000002c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000ac2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000ec2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF209C00000000002000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF209C000000000020000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000001c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000005c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFE09A800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000dc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000bc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000007c2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fc2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF80\n\tB800000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF408500000000010002000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFC49A000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF048500000000008400000000000000000000000000822040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF4013000000000600000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000422040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF44\n\tF900000000000042000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF84DA00000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000c22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFF31B00\n\t0000000001801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF335E000000000001841800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFF31B0000000000018018000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000222040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FFF31B0000000000018018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF3\n\t1B00000000000180180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFF31B00000000000180180000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF375A00\n\t0000000001C01800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF375A000000000001C01800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFF31B000000000001801800000000000000000000000000000000000000000000000000000000000000000000000000000000622040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FFF31B000000\n\t0000018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFF31B0000000000018018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF3\n\t1B00000000000180180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFF31B0000000000018018000000000000000000000000000000e22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF9D9B00000000000100100000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF614100\n\t0000000211A01800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF6E34000000000105903800000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000122040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF668C000000\n\t0000888808000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF7A960000000000420020000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80\n\tDE0000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000922040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFF31B00000000000180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2AE000\n\t0000000440C40800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000522040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF806A000000000400000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFEC3A000000000000A008000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000d22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF82BA00\n\t000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000322040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000002000000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF8CE3000000000200001000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE69A000000\n\t0000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000b22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FFE69A0000000000000008000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF482A0000000004\n\t0040100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFE22A00000000040040080000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF529A0000722040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B00000000000000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF89A000000\n\t020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f22040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000401800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFAF840000000001341358000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B0000000000\n\t0000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFEA9B00000000000000180000000000000000000000000000000000000000000a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF62B600000000002802980000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B00000000000000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF5FB2000000000104105800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2EDA000000008a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF5C620000000000AA4AB800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF2AE20000000002000018000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0FEB0000000001\n\t5415580000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFEA9B00000000000000180000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF2A6A00000000040000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFEA9B00000000000000180000000000000000000000000000000000000000000000ca2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FFA85B000000000001954000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF591B000000000001800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF923B0000000000000AB8000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B0000000000002a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF21BB0000000000018AA0000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF21BB0000000000018A\n\tA00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aa2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF591B000000000001800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF591B000000000001800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF591B0000000000018000000000000000000000000000000000000000000000000000006a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF591B0000000000018000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF591B0000000000018000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF991F00000010000180000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF691A0000000400018000ea2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF591B00000000000180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF591B000000000001800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFA91E000000140001800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000000000000000009a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF8DDA00000000055580000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF82020000000000AA80000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF82BA000000000000200000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF53030000000000AB800000005a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF80E2000000000200000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF82020000000000AA8000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF53BB0000000000012000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000da2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF809000000020000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000003a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF24EB000020000400800800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFF31B000000000001801800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF808E0000004000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF2E1B000000000000800800000000ba2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF80E20000000002000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFE41A00002000000080080000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007a2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFB727000000000105801800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF6C8E000000000001105000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000fa2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF95400000000001218018800000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFD00B0000000000039018000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF161600000001008190380000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFF31B0000000000018018000000000000062040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FFF5C90000000200D380190000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFF91800000002000B803800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFFE0F000000010001905800000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000862040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFF31B0000000000018018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFF31B0000000000018018000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF335E0000000000018418000000000000000000000000000000000000000000000000000000000000000000462040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFC31A00000004000180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFDF51000200200009C0180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF8C9B000000022001801800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFF779000000000001C2180000000000000000c62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF31B2000001801C01801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF76430000018058098018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF312D000401C01A018018000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000262040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFF14300000180180180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF39C200000180180100180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFF14300000180180180180000000000000000000000000000000000000000000000000000000000000000000000a62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tF143000001801801801800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFF143000001801801801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFF1430000018018018018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFF143000001801801801800000000000000000000662040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF3362000001801801A018000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF3362000001801801A0180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFF14300000180180180180000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t2BC0000009889801801000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFBB34000201AC1A21A23800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFEDE5000013811885909800000000000000000000000000000000000000000000000000000000000000000000000000162040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFE824\n\t00010316028220C0000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF2C9B0000008018008808000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF209C00000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF58FF0000000000000620000000000000000000000000962040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF95C800000100128428C00000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tC147000001801801805800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFDB33000480CA0C00C40800000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000562040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF407F\n\t0000004004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF089A0000000000080000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF8DAC000200A00A40A208000000000000000000000000000000000000000000000000000000000000000000000000000000d62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF32230000\n\t000000AA0AA00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF808400000000008000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t32230000000000AA0AA000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF1FE100020020024C33400000000000000000000000000000362040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF3147000001901801801800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4CE8\n\t0000002002000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF2FD30000008008008008000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4FD10000\n\t0081081080180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF443C00040040040040000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t2B74000400C00C00C0080000000000000000000000000000000000000000000000000000000000000000000000000000000000762040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (516800000180\n\t1801829800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF9C88000001011011801800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B\n\t0000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF991F000000100001800000000000000000000000000000000000f62040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FFA1620000018018118218000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF605E0000\n\t018018A191580000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFF11600000180180185180000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF000e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA9EF0000ABAA\n\tB88190B800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFF1CB000001801E01801800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD6EF\n\t0002AB8AB8478018000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000001A01801\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF62580000AB8AB8AB8AB8000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF63250000\n\t01801811A4180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFF77700035595595595580000000000000000000000000000000000004e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FFDDC200004184180100180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8AE100008389\n\t5801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFFD83000001801801401800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF314800ce2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF364B000140051955\n\t9540000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF5B3B0000000018018000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF417A0000\n\t098018AB8AB80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000018018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFC8200000AA0AB8AB8AA00000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF561E00000A10\n\t5801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFC8200000AA0AB8AB8AA00000000000000000000000000000000000000000ae2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FFD33B000000061801800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5CAF000000403801\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF5B3B0000000018018000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5B3B0000006e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFB4280004004038001140\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF853A00000000380000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9B3900040000\n\t180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (300011000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF42BB000000001800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF6B3F000000001801\n\t8040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF5B3B0000000018018000000000000000000000000000000000000000000000001e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FFD3E10000000008BA8000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF691A0000000400018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF0A1900000009400180000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF45DA00000000009e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF86AE00000015595520000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF62E700000012C8A2800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF919A000000000001\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF6A608000000AA8A28000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF55DB0000000000014000000000000000000000000000000000000000000000000000de2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF4989000000200A0080000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF80E200000000020000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF809A000000500000010000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF089A000000000008003e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF48D7000000300980910000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF9F7A000000001801C000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF42330000000000002800\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000be2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF991000000020000180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF49FB00000000080080000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000007e2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FFE11A000000021819A02000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF82B0000000201800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF23590000000210000020000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B000000000001800000fe2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF41BF0000001418000004000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF86FA00000000180040000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF943A00000000580180000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF43330000002A1801800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF682F000000401801800400000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF943A000000005801800000000000000000000000000000000000000000000000000000000000812040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FFCB870000022418818080000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF3BB4000600101E018000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF231600018000190181000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE38E0000024218018000000000412040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFB308000000220C0180840000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF7774000080301801C00000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF591E000000101801A00000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFF13B0000000018018018000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF294F000000121A018098000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF522E000100401801801C000000000000000000000000000000000000000000000000000000000000212040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF331A000000001801A0180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF3142000000001A0180180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFF13B000000001801801800000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFF13B00000000180180180000000000a12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFF13B000000001801801800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFF56A000000001801C118000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFF13B0000000018018018000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000612040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF3142000000001A0180180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF88B300000000180000980000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF28C2000000001A0000180000000000000000000000000000000000000000000000000000000000000000e12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FFF959000000000021840000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF9435000108049840001800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FFD42C0000242A5A422818000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFCBFB000010011C01801840000000000000112040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FFAB280000202012020000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF3BF80000000A080080180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF613F00000200600198402000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000912040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF1C2A000000255210001000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF9E39000000025801803800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF7B9C000100400C40CC0800000000000000000000000000000000000000000000000000000000000000000000512040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF137D0002003103542002000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF806C0004001004000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF02820000000000A200000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF542D000200300A00A00A000000000000000000d12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF32830000000400A200000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF3F1B000000022000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF5B8300000000C0AA000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000312040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF854D00000190180D8018018000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF996E00020002A2080000010000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF07D00000009008008008008000000000000000000000000000000000000000000000000000000000000000000000b12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FFC9\n\t1C00000010000980200000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF07D000000090080080080080000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFF535000400400402404401000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF3072000400C00C00C00C0080000000000000000000712040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF90C9000001801800001801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFF7510000011010000510018000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFA95500000000002184C0000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f12040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD8\n\tC800000180180800180180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF894900000180180180180180000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFF14C00000180182180380180000000000000000000000000000000000000000000000000000000000000000000000000092040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FFB73400\n\t0001B5594D955801800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF12720002018AB8A38AB801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFA341000001801E01801E018000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFABF8000001AAB8A20AB801800000000000000000000000892040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FFBB6B000201801811A018018000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF72\n\t730000018AB8A38AB80180000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFDD0A000001801811C0180180000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000492040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC91800\n\t0151901801941801800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF091F00000584D811815801800000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF8949000001801801801801800000000000000000000000000000000000000000000000000000000000000000000000000000c92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF3C030000AB\n\t8AA0A39480AA0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF208B0001498101558521540000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF69\n\t6700000180000180400000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF60D70000018018A38008AB8000000000000000000000000000292040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF987200000180000190000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF855C00\n\t00AB8AA0BB8000AA000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF46C90000038A2001880000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBB62000001\n\t8000038000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFAD37000001C20009C000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE1\n\t4A00000180000182A0000000000000000000000000000000000000000000000000000000000000000000000000000000000000692040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400000018000\n\t0182000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF0C1F000001C0000240800002000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0E000\n\t0001840010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFDD6200000180000580000000000000000000000000000000000000e92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF98A4000001800000042000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0363000001\n\t8020040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF93B10000018020018120000400000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9900192040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA5B0000AB8000\n\tA280000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC91900\n\t000000001180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000992040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000100001100\n\t0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF5590000155800145000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2A0A0000AA\n\t8000A28000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF001A000000000009000200000000000000000000000000000000000000592040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD0990000000000\n\t1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF2A088006AA8000A280000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF32C80000d92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF2FF100000020080080\n\t0800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF869A080000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE0FE000000\n\t080000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000392040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000400\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFAA10000000200C049008000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF24DC1000000018\n\t01801A0800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFA2170000001000020800000000000000000000000000000000000000000000b92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF9ADA00000000100180\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF2F83000000000A00800800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB39A00000000792040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF4C6A000000021801D01800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFE9EF0000044018000018000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF85B0000000250\n\t000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f92040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (018018000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF35EB00008004390020181000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF27BA00000000580000\n\t1800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF191800004221180188180000000000000000000000000000000000000000000000052040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF9133000000001801809800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFA5DB000090021901901810\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFDB330000480118018818000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3E3A000000005800852040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFC22A000000001801811C000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF2832000000001E01801A0000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFF13B00000000180180\n\t180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000452040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF6C3C000000431819901800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFEFB3000000009801881800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF313F000000101801801800000000000000000000000000000000000000000000000000c52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF23310000000018018000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF23310000000018018000018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF9B3000000002180180000180000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF23200000005018018000252040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFE348000000001A0180000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFE33A000000201801800001800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF2331000000001801800001\n\t800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF23310000000018018000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF22220004000018019000018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFE3330004000018018000018000000000000000000000000000000000000000000000000000652040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFEA8F000010401C5589201180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF2551000000001801E0000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF3AB1000000001800000001800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFFBA000000000180010000100e52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFA621000100004001820002000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF3CD10000000030000000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFD4C0000080323B000202038000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000152040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFACD800000029028220000100000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF337D00008802080080000080000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFC9F700000000006988A00800000000000000000000000000000000000000000000000000000000952040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFA32E00020022AA00B10000800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF82E0000000280200224001000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF18B10000000138018000018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF7A16000080400C40800400800000552040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF36A80002002803442540000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF273F00040040041040040000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFB5830000000440AA00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFBBA10000000AA0A20AA000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFCE11000000008010080000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFBBA10000000AA0A20AA000000000000000000000000000000000000000000000000000000000000000352040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF17E2000400C04C80C80C000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF8BC30000098218018018000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF38D800020120120020020000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFBFD10000008008108008000000000000b52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF9B9A00000800000180000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF365300000080A800800800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF503D0004015B1480480400000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000752040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF284A0000018018000818000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF4EC20000018018000010000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF9F700000001000418000800000000000000000000000000000000000000000000000000000000000000000f52040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFB4DC0002018018A2001AAA00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFD8C200000184180000180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF3AC3000001893811801800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFFC96000001881821901900000000000000000d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF90F9000201955955801B54000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF9B21000001903AAB8018AA0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFF15D000001E018018018000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFA138000001801A1180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFD55F0000018AB8A38018AA00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF5302000001829801C01800000000000000000000000000000000000000000000000000000000000000000000004d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tDB910000AB8AB8BB97D800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFF143000001801801801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF28500000018018019038000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF3362000001801801A01800000000000000000000cd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FFC2510000AB8AB8B38AB8018000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF8E3E00015595594580180180000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF48A800000180100180180180000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t4942000001A01801801801800000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF52530000AB8AB8A38AB801800000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF8949000001801801801801800000000000000000000000000000000000000000000000000000000000000000000000ad2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF9CC7\n\t000001845841801E018000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF33DC000009C218018018018000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF4C4800001180180180180180000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF194B00000180181180180180000000000000000000006d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF384F00000180D84180980180000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tD7C8000001805810003801800000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF90C9000001801800001801800000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ed2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF3FE7\n\t0000010058100058018000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF90C90000018018000018018000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF155100000181186181180180000000000000000000000000000000000000000000000000000000000000000000000000001d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF80990004\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF25AA0001948088A38AB8AA80000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t8D1A000040000001800000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF5CBB00000A0C2011800000000000000000000000000000009d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FFD992000400230001001000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFECB3\n\t0001559559555559558000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFBF63000020A828AA8AA8AA8000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF089A0000\n\t0000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF82BA00000000000020000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t1B498000AA8AA8A28AA8AA80000000000000000000000000000000000000000000000000000000000000000000000000000000dd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (4C5B00000000\n\t5000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF2F83000000000A00800800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF871A0000000020000000000000000000000000000000000000003d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEF720000\n\t00000E0080080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFF13B00000000180180180000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00bd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B00000000\n\t0001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF591B000000000001800000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEC42\n\t000000001A008008000000000000000000000000000000000000000000000000000000000000000000000000000000000000007d2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000001881\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF2F48000000209A018018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF28BF0000\n\t0010180000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF50860000000099000010000000000000000000000000000000000000fd2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FFF14C000000001A4180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE7C300000000\n\t5A00001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF48C0000000081A00001800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF312400032040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFCD2F000000411801\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF36BA0000000038018018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF913C0000\n\t000018218018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000832040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (400018018018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF221A00000000D801A0180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF41300000000\n\t3E01A01800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFF12500000060180180180000000000000000000000000000000000000000432040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF24A2000040001201801800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEF25000000009881\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF312E0000004018018018000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF253A000000c32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFF13B0000000018018018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF31CA000000001C0180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2F2E00000020\n\t988180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000232040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (180180180000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFF1C1000000201C01801800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF13B000000001801\n\t8018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFF13B000000001801801800000000000000000000000000000000000000000000a32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FFE8BB0000000018000018000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF3142000000001A018018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFF13B00000000180180180000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF13B0000000000632040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF7C6700009048182182980800\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF5138000600001801801800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE8BB000000001800\n\t001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (808088000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF81C50000000000018D20000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFDA270000880A18800018\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFCD1D000020225A842838800000000000000000000000000000000000000000000000132040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF68BA0000404C2D40C5080000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF5CE100006030024022000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF02FB000000054802801800000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFDCAF00000000212500932040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF4D64000200200A00AC0800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF96C400000020020820D0000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFAB3B0000000098058018\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000532040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFC5240002003543542D400000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFB73D00040040040040040000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFC3010000000AA0A200000000000000000000000000000000000000000000000000000000d32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF2FD3000000800800800800000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FFBBA10000000AA0A20AA000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFF3A00000000AA0AA0AA000332040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFD875000400C00C00C00C000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF314700000190180180180000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFAB4A00020020021020020000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFE718000000088001800000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF28F3000002802800800800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF455E000404414580400400000000000000000000000000000000000000000000000000000000732040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FFFDD90000018018418519000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF4EA50000018018200018800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FFAEF800000100000200100400000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF1D1B0000000000058300040000f32040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFCA7E0002019218A20AB80000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FFDB33000001801C00001C00000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF4A46000001915809801800000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF27350002019559459558000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF5E3A00000180B8ABCAB8000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF614100000180181180180000000000000000000000000000000000000000000000000000000000008b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FFF14300000180180180180000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFF369000001A01801A0180000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF71880000018ABCAB8ABC00000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF0157000001C41801801800000000004b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF545D0000018058A3807800000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF6D400000018918018018000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF00A50001338458119518000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF54510000AB8038A38AB80180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFBDE00000959519558D180180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF9CAA000001831011801801800000000000000000000000000000000000000000000000000000000000002b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF72C2000001A13801801801800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFF14C000001921801801801800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF1BD50000AB9018AB8AB8018000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF5D48000041801801801801800000000000ab2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF73490000218418018018018000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF5145000001BA180180180180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF1B00000081809801C0980180000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFAD48000041821809801801800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFB34E000001803824001801800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF86F8000081811800211801800000000000000000000000000000000000000000000000000000000000000000eb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF58D700000002A0018480000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF098D0000018458000410018000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF14C800000180180400180180000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF196600000180185182180180000000000000001b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF89C700000100000900000100000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF29690000AA8148A28028AA800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFC994000000100011880000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF18D50000010000011020010000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF8BF3000555955945155D558000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF92440000AA9208AA8288AA80000000000000000000000000000000000000000000000000000000000000000000005b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF02\n\t820000000000A200000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF209A00020000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF0918000000000010000200000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF1B498000AA8AA8A28AA8AA80000000000000000000db2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FFC4F6000001000104000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF2FD30000008008008008000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80\n\tCA00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF2FD300000080080080080000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF513D000001801A2180180000000000000000000000000000000000000000000000000000000000000000000000000000bb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF8F2300\n\t0001801000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF591B000000000001800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF99620000000002018000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF2FD30000008008008008000000000000000000000000007b2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF91DD000001C818018818000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF60\n\t5400000190181190180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE8C300000180180000180000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fb2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF14300\n\t0001801801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFFCFF000041801900001800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF60D7000001C01808001800000000000000000000000000000000000000000000000000000000000000000000000000000000072040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF3160000001\n\t8018018218000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFCD460000019118018018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFC1\n\t4200000184180180180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF5D7E0000418219018018000000000000000000000000000000872040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFF14300000180180180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0E4704\n\t0001911801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFF087020001801801841800000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000472040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF60DC000000\n\t0410218018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFE9470004018218218018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF1\n\t430000018018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000c72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (3B0000000018\n\t0180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFF13B00000000180180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF313900\n\t0400001801801800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFF13B00000000180180180000000000000000000000000000000000272040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFF13B000000001801801800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF13B000000\n\t0018018018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFF13B0000000018018018000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF100a72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE8BB0000000018\n\t0000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFF1DF000000401C0180180000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF13B00\n\t000000180180180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000672040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0020245AA820\n\t9800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFEB2E000010109801901800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF75B000000\n\t001801E018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFE85F000000401C00001800000000000000000000000000000000000000e72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF59140000000000218080000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF870B0000000080\n\tC180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FFF7B10000600E380808100000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF97F80000172040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFAF61000040400D10C0\n\t0800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF22F4000200200300200000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBD79000008\n\t000810800800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000972040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (1100A2176000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF518B000000288A008008000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF2CD20002002442\n\t1030800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF01340000000418418018000000000000000000000000000000000000000000572040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FFD3800000AA0AA0AA0AA00000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFEB9900015424435400\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF443C000400400400400000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF37C60000AA00d72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFD9F9000000000810800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF9B810000AA0AA0A20AA0000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000372040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (004000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF4D5C000400400C00C0000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFA3BB00000004180100\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFF00900020020120120000000000000000000000000000000000000000000000000b72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF0F8700000000200190C000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF591B000000000001800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FFE77A0000000228018000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF48FC000400405400772040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF4B350000000018409100000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF44BC00000002982000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFA0BF00000005580100\n\t400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f72040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF68010002000A78A2022000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF6F27000000411801080000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF73320000000018098080000000000000000000000000000000000000000000000000000f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF1DBB000000011801AAA0000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFCC4E0002001559549540000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFB95C000000141AB380000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF8A3A00000000180080008f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFDE79000000001810C0000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF9B42000000001A01800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFB1150000004AB8A28AA000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FFD8A10000000AB8A38000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF1A380000000018108000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF5B3B0000000018018000000000000000000000000000000000000000000000000000000000cf2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FFE8C300000180180000180000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFBA580000018AB8A300180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF3FF6000001955954001800000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF39C2000001801801001800002f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF39C2000001801801001800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF59C30002018018010018000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF625B0000018AB8BB0018000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000af2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF9CC100001188180100180000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF3B4100040980180100180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF36FE000001805901001800000000000000000000000000000000000000000000000000000000006f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FFB314000001841801001900000000000000000000000800000000000000000000000000000000000000000000\n\t0000000000000000000000000002000000000000000000000000000000000000FF81A0000001921801001808000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF3EB20000018018011018800000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF3E7E000001803901001800000000ef2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000002000000000000000000000000000000000000FF750D0001200000018000000000000000000000\n\t0000080000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000\n\t00000000000000FF8ED100000100100100181000000000000000000000080000000000000000000000000000000000000000\n\t00000000000000000000000000000002000000000000000000000000000000000000FFF94B00000180180108180000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0800000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF82EB0000588008AA8AB800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF67CE0000040CC0010000000000000000000000000008000000000000000000000000000000000000009f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF0AC10000AA8AA82A8AA8000000000000000000000008000000000000000000000000000000000000000000000000\n\t000000000000000000000002000000000000000000000000000000000000FFDA930000802880000010000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF5337000155955955D5580000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FFDC57000002A428AA8AA80000000000005f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF80A6000000000100000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF82BA000000000000200000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000df2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FFE7520000008008000008000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF401900000200000002000000000000000000000000000000000000000000000000000000000000000000003f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFE75200000080080000080000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFE752000000800800000800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FFE84100000380180002180000000000000000bf2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF4F0A000001001000001000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007f2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE8C300000180180000180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF6CC200000180180400180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FFE8C300000180180000180000000000000000000000000000000000000000000000000000000000000000000000ff2040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\tE8C3000001801800001800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF36C2000001809800001800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF14C20000018118000018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF6CC200000180180400180000000000000000000000a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FFE8C30000018018000018000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE8C300000180180000180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFE8C300000180180000180000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tE8C3000001801800001800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFE7C9000001A05800001800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFE7C9000001A0580000180000000000000000000000000000000000000000000000000000000000000000000000000040a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FFEA9B\n\t0000000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFEA9B0000000000000018000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE8C300000180180000180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FFE8C30000018018000018000000000000000000000000c0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FFEA9B00000000000000180000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tEA9B000000000000001800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFEA9B000000000000001800000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFEA9B\n\t0000000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFEA9B0000000000000018000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFEA9B0000000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000a0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FFEA9B0000\n\t0000000000180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFEA9B00000000000000180000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tEA9B000000000000001800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FFEA9B0000000000000018000000000000000000000000000060a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF0E0E000010112000233800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9996\n\t0001200200901018000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FFEA9B0000000000000018000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF808B0000\n\t0000014002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFE09800000002000000200000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\tC58D0000800020800818000000000000000000000000000000000000000000000000000000000000000000000000000000000010a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (8A9C00000000\n\t0020001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FFE2E6000000000100400800000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF22B0\n\t0002002000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF741100002808800800980000000000000000000000000000000090a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF682C0000020000000160000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFDAE20000\n\t0001020000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FFF18E00035034400032900000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0050a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD9980000AA0A\n\tA0000AA000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF9FB3000110134200140000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF807D\n\t000400400400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000200200201\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF881A0000000000008000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFD9980000\n\tAA0AA0000AA00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF4A3B000022000000000000000000000000000000000000000000000030a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF443C00040040040040000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBCBC00040044\n\t0400C00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF591B000000000001800000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFF1E900b0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF989D000000020020\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FFF89A0000000200000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B0000\n\t00000001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000070a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFA91400000004\n\t0041800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000f0a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF591B000000000001800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF21BB000000000001\n\t8AA0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF591B0000000000018000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B00000008a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF3B2E000200400001A000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FFA85B00000000000195400000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE1C200000000\n\t02018AA0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000088a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF5D58000400000001C00000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5969000000200201\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF21BB0000000000018AA00000000000000000000000000000000000000000000048a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF5B430000018018018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF53030000000000AB8000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF591B00000000000180000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF591B0000000000c8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF5B4300000180180180000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF515B0000018018AB800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4F73000001801955\n\t80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (C00000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFFB428000018018018000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF5B430000018018018000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF515B0000018018AB8000000000000000000000000000000000000000000000000000a8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FFE34200000182180180000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFB94200000180180380000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FFAB46000001941801800000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9F020000018018010068a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF2D55000001801801800000000000\n\t0000000000000008000000000000000000000000000000000000000000000000000000000000000000000002000000000000\n\t000000000000000000000000FF1F460000019018058000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF5873000001801801B000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000080000000000000000000000000000000000000000000000000000000000000000000000020000000000000000\n\t00000000000000000000FF96950000000000A000000000000000000000000000080000000000000000000000000000000000\n\t00000000000000000000000000000000000002000000000000000000000000000000000000FFE5D400000180180100000000\n\t0000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000200000000\n\t0000000000000000000000000000FF9BCA0000018018018800000000000000000000000000000000000000000000000000000018a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FFB4670000AA8AA80A800000000000000000000000000800000000000000000000000000000000000000\n\t0000000000000000000000000000000002000000000000000000000000000000000000FF806A000000000400000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FFABDC0000AB8AB9008000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF228E00000000001400000098a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FFD4630004AAEAA8AA8000000000000000\n\t0000000000080000000000000000000000000000000000000000000000000000000000000000000000020000000000000000\n\t00000000000000000000FF43F400000100144000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFCC3600015595595580000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000058a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF8099000400000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000d8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF18C30000018218020000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF10CB0001010000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF415300000080080000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFF29A000080020002000000000038a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF415300000080080000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF80CA000001000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF4153000000800800000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF83220000018010000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000078a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF42C300000180180000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF88C200002180180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF42C3000001801800000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF96C200004180180000000000000000f8a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF42C3000001801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF42C30000018018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF42C30000018018000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF5C0301000180980000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFBEC200000181180000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF42C30000018018000000000000000000000000000000000000000000000000000000000000000000000084a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF8202010001801800000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF42C3000001801800000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF82C8000001A018000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF82C8000001A0180000000000000000000044a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF5B3B0000000018018000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF5B3B00000000180180000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF42C300000180180000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF5B3B000000001801800000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF5B3B000000001801800000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF5B3B00000000180180000000000000000000000000000000000000000000000000000000000000000000000024a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF5B3B0000000018018000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF5B3B0000000018018000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF5B3B00000000180180000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF5B3B0000000018018000000000000000000000a4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF5B3B00000000180180000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF5B3B000000001801800000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF5B3B000000001801800000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000064a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFFA74D000000309A038000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF2C070000300219018000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF5B3B0000000018018000000000000000000000000000000000000000000000000000000000000000000000000000e4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF4B\n\t6500000800088080000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFA29A00000000000200000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FFFFBA0000400218010000000000000000000000000014a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF9E3A000010001801800000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF9D1E000040400C008000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF92530002302890000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000094a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF50\n\tBA0000AA04000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFB5FA00000001080080000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FFBC520002002C50000000000000000000000000000000000000000000000000000000000000000000000000000000000054a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFA1380000AA0AA000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF53D90001540940000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF4068000400000400000000000000000000000000000000d4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FFE0E30002000002000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFA1380000AA0AA00000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000034a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF807D00\n\t0400400400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF807D000400400400000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF709A000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF8C9B000000\n\t0500000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF049B000000030000000000000000000000000000000000000074a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FFA8820000000000A800000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFF89A000000020000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f4a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF032E0002002AA1020000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000AA0\n\tAA00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF94E100000000021400000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF37BA00\n\t0200554154000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFE11F0000000AA020000000000000000000000000000000000000008ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF806A000000\n\t0004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF8B004ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF59630000018000\n\t0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000180000180\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF5963000001800001800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF5963000001\n\t8000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF59630000018000018000000000000000000000000000000000000000002ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF9976000001C000018000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF59630000018000\n\t0180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF996100040180000180000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF59630000aca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF9968000001A0000180\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF6962000001840001800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF26E5000219\n\t9A00018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (800001810000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF59630000018000018000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF41750000018200\n\t8180800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF59630000018000018000000000000000000000000000000000000000000000eca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF81DA00000400000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFDF9A00013000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF6976000001040101800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9973000001001ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FFA80A00008A8000AA800000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF472B0000408000\n\tAB80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF02FB8000AA8004AA80000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF919A00000000000100\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF0D13000155800155800000000000000000000000000000000000000000000000005ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF80E20000000002000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000dca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF808E00000040000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF8090000000200000000000000000000000000000000000000000000000000000000000bca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FFBC9A0000000100000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF82100000080800000080000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000007ca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF7E0F00000811000001000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fca040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000002a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF809A00006000800000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFDC9D000000010020000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000082a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF8095000000000040000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000c2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000022a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF808B0000000000000100000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF209300000000000000800000000000000000000000000000000000000000000000000000000000000062a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFBC9A00000001000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000e2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF9E9A000000008000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000092a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF809000000020000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000052a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF80900000002000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF835A00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF817A00000000080000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000032a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF808E000000400000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF416F0000004008000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF42BB000000001800000000000000000000000000b2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FFFABA0000000218000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFF89A00000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000072a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t42BB000000001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF42BB000000001800000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF42BB000000001800000000000000000000000000000000000000000000000000000000000000000000000000000000f2a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF42BB\n\t0000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF42BB0000000018000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF42BB00000000180000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF42BB00000000180000000000000000000000000000000aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF835A00000000100000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t835A000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF835A000000001000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4C5B\n\t0000000050000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF835A0000000010000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF835A00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000004aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF839E0000\n\t0015400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t85580000000A9000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF835A00000000100000000000000000000000000000000000caa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF81180000000AA000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF81180000000AA0000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aaa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (209300000000\n\t0000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000006aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF20930000000000000080000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00eaa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000009aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B005aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000daa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000003aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000baa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007aa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000faa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000006a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000086a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000046a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000c6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000026a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000a6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000066a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000016a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000096a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000056a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000d6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000036a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000076a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000f6a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000008ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000004ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000002ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000aea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000001ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FFE09A800000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000dea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000007ea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000fea040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000081a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000041a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000021a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000a1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000061a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000e1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000011a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000091a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000051a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000d1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000031a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000b1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000071a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f1a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000009a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000089a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000049a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000c9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000029a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000069a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000e9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000019a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000099a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FFE09A8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000059a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000039a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000b9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000079a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f9a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000005a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000085a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000045a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000c5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF0025a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000065a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00e5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000015a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000095a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000055a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000035a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000b5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000075a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000f5a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000004da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000cda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000ada040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000006da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000001da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000009da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000dda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000003da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000007da040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000fda040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000083a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000043a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000023a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000a3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000063a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000013a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000093a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000053a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000d3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF400033a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000073a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000f3a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000008ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000004ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000002ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000aba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000eba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000001ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000005ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000dba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000bba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000007ba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fba040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000007a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000087a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000047a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000c7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000027a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000067a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000e7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000017a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000097a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000057a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000037a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000b7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000077a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f7a040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF008fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000cfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B002fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000afa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000006fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000efa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000009fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000005fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000003fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000bfa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007fa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000ffa040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000006040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000806040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000406040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000c06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000206040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000a06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000606040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000106040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000906040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000506040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000d06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000306040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000706040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000f06040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000086040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000886040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000486040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000286040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000a86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000686040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000186040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000986040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000586040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000d86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000386040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000786040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000f86040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000046040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000846040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000446040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000246040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000a46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000646040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000e46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000146040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000946040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000546040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000d46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000346040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000b46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000746040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f46040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000008c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000cc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000002c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000ec6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A\n\t8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000005c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF097A000000000000000000000000000000000000000800000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000bc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF007c6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fc6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000026040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00826040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000426040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000c26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000226040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000626040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000e26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000126040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000926040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000526040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000326040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000b26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000726040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000f26040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000004a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000ca6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000aa6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000006a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000001a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000009a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000da6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000003a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007a6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000fa6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000066040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000866040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000466040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000266040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000a66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000666040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000166040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000966040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000566040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000d66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000366040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000766040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000f66040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000008e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000004e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ce6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000002e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000ae6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000ee6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000001e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000005e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000de6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000be6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000007e6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000016040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000816040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000416040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000216040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000616040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000e16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000116040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000916040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000516040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00d16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000316040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000b16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00716040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f16040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000096040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000896040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000496040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000c96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000296040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000696040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000e96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000196040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000996040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000596040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000396040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000b96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000796040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000f96040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000056040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000856040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000456040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000c56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000256040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000a56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000656040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000156040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000956040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000556040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000356040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000756040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000f56040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000004d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000cd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000ad6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00006d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ed6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000001d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000009d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000dd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000003d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000007d6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000fd6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000036040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000836040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000436040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000236040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000a36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000636040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000e36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000136040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000936040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000536040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000d36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000336040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000b36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000736040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f36040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000008b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000002b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ab6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000eb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF001b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000005b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00db6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000bb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000007b6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fb6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000076040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000876040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000476040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000c76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000276040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000676040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000e76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000176040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000976040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000576040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000376040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000b76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000776040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000f76040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000004f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000cf6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000af6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000006f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ef6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000009f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000df6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000003f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bf6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007f6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000ff6040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF400000e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000040e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000c0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000a0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000060e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000010e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000090e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000d0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000030e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000070e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000f0e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000088e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000048e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000028e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000a8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000068e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000e8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000018e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000098e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000058e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000d8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000038e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000078e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f8e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000084e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000044e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000024e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00a4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000064e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000e4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0014e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000094e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000054e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000d4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000034e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000b4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000074e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f4e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000008ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000cce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000002ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ace040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000006ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000ece040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000009ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000005ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000003ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000bce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007ce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000fce040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000002e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000082e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000c2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000062e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000092e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000052e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000032e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000b2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000072e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000f2e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000004ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000cae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000aae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000006ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FFE09A800000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000001ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000009ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000dae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000003ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000007ae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000fae040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000086e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000046e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000026e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000a6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000066e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000e6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000016e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000096e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000056e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000d6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000036e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000076e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f6e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000008ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF004ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000002ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00aee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000eee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A800000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000001ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000005ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000dee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000bee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000007ee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fee040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000001e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000081e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000c1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000021e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000061e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000e1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000091e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000051e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000031e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000b1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000071e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f1e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000009e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000089e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000049e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000c9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000029e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000069e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000019e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000099e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF400059e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000039e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000b9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000079e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000f9e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000005e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000085e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000045e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000c5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000025e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000a5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000065e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000015e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000095e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000055e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000d5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000035e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000075e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000f5e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000008de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000004de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000002de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000ade040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ede040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FFE09A80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000001de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000dde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000007de040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00fde040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000083e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0043e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000023e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000a3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000063e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000e3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000013e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000093e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000053e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000d3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000033e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000b3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000073e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f3e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000008be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000cbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000002be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000abe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000006be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000ebe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000009be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000005be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000003be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000bbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007be040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fbe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000007e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000087e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000047e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000c7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000027e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000067e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000e7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000017e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000097e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000057e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000037e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000b7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000077e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000f7e040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000004fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000cfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000afe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000006fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000efe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000001fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000009fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000dfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000003fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bfe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000007fe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t04FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000ffe040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000004FF75DE0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t04FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000004FF75DE00000000000000000000000000000000000000000000000000000000000000000000000000000000000000801040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000004FF75DE0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000401040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000201040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000a01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000601040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000101040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000901040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000501040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000d01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00301040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000004FF75DE0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000701040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF75DE00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000004FF75DE000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004FF75DE00f01040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000881040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000481040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000281040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000a81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000681040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000e81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A80000000000000181040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000981040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000581040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000d81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000381040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000b81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000781040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF75DE00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000004FF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000004FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f81040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000041040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000841040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000441040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000c41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000241040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000641040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000e41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000141040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000941040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000541040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000341040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000b41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000004FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000741040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF75DE000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f41040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000cc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40002c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000006c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FFE09A8000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000ec1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000009c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000005c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000003c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000bc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000fc1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000021040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000821040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000421040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000c21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000221040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000a21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000621040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000121040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000921040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000521040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000d21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000321040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000721040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000f21040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000004a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000aa1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFE09A8000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000001a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF009a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000001FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000da1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB003a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ba1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000007a1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000001FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000fa1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000061040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000861040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000461040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000261040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000a61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000661040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000001FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000001FF409B00000000000000000000000000000000000000000000000000000000000000000000e61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FFBDCB000000000000000000161040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000961040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000561040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000d61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000361040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000b61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000761040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f61040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000008e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000ce1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000002e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ae1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FFE09A80000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000ee1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000005e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000be1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007e1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000011040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000811040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000411040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000c11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000211040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000611040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000e11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000911040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000511040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000311040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000b11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000020000\n\t00000000000000000000000000000000000000000000000000000000000000000004FF75DE00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000004FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000711040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF93BA0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000\n\t00000000000000000000000000FFA6FF0000000000000000000000000000000000000000000000000000000000000000000000f11040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000091040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000891040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000491040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000c91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF097A0000000000000000000000000000000000\n\t0000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF097A00000000000000000000000000\n\t000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000291040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000a91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF097A0000000000000000000000000000000000\n\t0000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000691040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF097A000000000000000000000000000000000000000800000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF097A000000000000000000000000000000\n\t000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000191040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000991040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000591040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000d91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000391040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000791040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000f91040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000051040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000851040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000451040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000251040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000a51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF00651040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000151040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00951040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000551040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000d51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000351040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000751040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000f51040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000008d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000004d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000002d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000ad1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000ed1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000001d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000005d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000dd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000bd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000007d1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000031040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000200\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000831040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000FFBCE300000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000002000000000000000001000000000000000\n\t0000FF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000FF1FDB000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000001000000000431040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FFA23C0000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000200FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (00000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF0159000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000\n\t0000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000231040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF607A0000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000a31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF9C\n\t8600000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000631040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (0000FF9C8600\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000e31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000131040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\tFF409B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000931040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF40\n\t9B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000531040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000FF23FF00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF23\n\tFF0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000331040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (9B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000b31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF4000731040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f31040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00008b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000cb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000002b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ab1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000006b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (008000000008\n\t0000000080000000080000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000eb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF4CFE0000004000000004000000\n\t0040000000041004000010000000010000000010000000010000000010000000010000000010000000010000000010000000\n\t01000000001000000001000000FF706A00000000000000000000000000000000000004000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FFE75600000002000000\n\t0020000000020000000020000000008000000008000000008000000008000000008000000008000000008000000008000000001b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (010000000010\n\t0000000100000000040000000040000000040000000040000000040000000040000000040000000040000000040000000040\n\t0000000400000000400000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF5C6D000000008000000008\n\t0000000080000000180000000020000000020000000020000000020000000020000000020000000020000000020000000020\n\t000000020000000020000000020000FF859F0000000000000000000000000000000000100000000000000000000000000000009b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF989A2000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF8A9000000000000000000000000000000000002000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000000000000000FF7EFF00000010000000005b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF93C300000000040040040040040040\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FFB73D0004004004004004000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000FF53D600000040040040040040040040000000000000000000000000000000000000000000003b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000bb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000FF443C0004004004004000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B0000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000000000000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000000000000FF409B00000000000000000000000000000000000000000000000000000000000000000000000000fb1040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (000000000000\n\t0000000000FF7EFF000000100000000100000000100000000100000000040000000040000000040000000040000000040000\n\t0000400000000400000000400000000400000000400000000400000000400000FF997C000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000080000FF409B0000000000000000000000000000000000000000000000000000000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000FF409B000000000000000000000000071040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 2080 TDI (001000000001\n\t000000001000000001000000001000000001000000001000000001080000FF409B0000000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t00000000000000FF996900000000800000000800000000800000000800000000200000000200000000200000000200000000\n\t20000000020000000020000000020000000020000000020000000020000000020000FF409B00000000000000000000000000\n\t000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000871040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSDR\t8\tTDI(60);\nSDR 1832 TDI (FFFFFFFF0000007A11110000000000000143FFFFFFFFFFFFFF\n\tFFFFFFFFFFFFE756000000020000000020000000020000000020000000008000000008000000008000000008000000008000\n\t0000080000000080000000080000000080000000080000000080000000080000FF558E000000000000000000000000000000\n\t0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t0000000000000C0000FF60EC000000400000000400000000400000000400000000100000000100000000100000000100000000471040);\n\nRUNTEST DRPAUSE 2.00E-03 SEC;\nSDR\t16\tTDI(00A0)\n\tTDO(00FF)\n\tMASK(C100);\n\nSIR\t8\tTDI\t(FF);\nRUNTEST IDLE    100 TCK;\n\nSIR\t8\tTDI\t(26);\nRUNTEST IDLE    2 TCK   2.00E-03 SEC;\n\nSIR\t8\tTDI\t(FF);\nRUNTEST IDLE    2 TCK   1.00E-03 SEC;\n\nSIR\t8\tTDI\t(79);\nSDR\t24\tTDI\t(000000);\nRUNTEST IDLE    2 TCK   1.00E-01 SEC;\n\n//END\r\n"
  },
  {
    "path": "doc/ECP5U25Pinout.csv",
    "content": "# Pin Out For ECP5U-25,,,,,,,,,\n# Revision 1.1 - Include CABGA256 package,,,,,,,,,\n\"# Revised Oct. 17, 2017\",,,,,,,,,\n,,,,,,,,,\nPAD,Pin/Ball Function,Bank,Dual Function,Differential,High Speed,DQS,CABGA381,CSFBGA285,CABGA256\n1,PL2A,7,-,True_OF_PL2B,TRUE,LDQ8,A4,C12,B1\n2,PL2B,7,-,Comp_OF_PL2A,TRUE,LDQ8,A5,B12,B2\n3,VSSIO7,-,-,-,-,-,-,-,-\n4,PL2C,7,-,True_OF_PL2D,-,LDQ8,B5,-,C3\n5,VCCIO7,-,-,-,-,-,-,-,-\n6,PL2D,7,-,Comp_OF_PL2C,-,LDQ8,C5,-,D3\n7,PL5A,7,-,True_OF_PL5B,TRUE,LDQ8,C4,A12,C1\n8,VCCAUX,-,-,-,-,-,-,-,-\n9,PL5C,7,-,True_OF_PL5D,-,LDQ8,A3,-,E3\n10,PL5B,7,-,Comp_OF_PL5A,TRUE,LDQ8,B4,-,C2\n11,VSS,-,-,-,-,-,-,-,-\n12,PL5D,7,-,Comp_OF_PL5C,-,LDQ8,B3,-,F3\n13,PL8A,7,-,True_OF_PL8B,TRUE,LDQS8,E4,D13,D1\n14,VCC,-,-,-,-,-,-,-,-\n15,PL8C,7,-,True_OF_PL8D,-,LDQ8,C3,-,F4\n16,PL8B,7,-,Comp_OF_PL8A,TRUE,LDQSN8,D5,C13,E2\n17,VSS,-,-,-,-,-,-,-,-\n18,PL8D,7,-,Comp_OF_PL8C,-,LDQ8,D3,-,F5\n19,PL11A,7,-,True_OF_PL11B,TRUE,LDQ8,F4,-,G5\n20,VSSIO7,-,-,-,-,-,-,-,-\n21,PL11C,7,-,True_OF_PL11D,-,LDQ8,E5,-,F2\n22,PL11B,7,-,Comp_OF_PL11A,TRUE,LDQ8,E3,-,G4\n23,VCCIO7,-,-,-,-,-,-,-,-\n24,PL11D,7,-,Comp_OF_PL11C,-,LDQ8,F5,-,E1\n25,PL14A,7,-,True_OF_PL14B,TRUE,LDQ20,A2,B13,F1\n26,VSSIO7,-,-,-,-,-,-,-,-\n27,PL14C,7,VREF1_7,True_OF_PL14D,-,LDQ20,B2,C15,G3\n28,PL14B,7,-,Comp_OF_PL14A,TRUE,LDQ20,B1,A13,G2\n29,VCCIO7,-,-,-,-,-,-,-,-\n30,PL14D,7,-,Comp_OF_PL14C,-,LDQ20,C2,A15,H3\n31,PL17A,7,-,True_OF_PL17B,TRUE,LDQ20,C1,D15,H5\n32,VCCAUX,-,-,-,-,-,-,-,-\n33,PL17C,7,-,True_OF_PL17D,-,LDQ20,D2,-,J4\n34,PL17B,7,-,Comp_OF_PL17A,TRUE,LDQ20,D1,D16,H4\n35,VSS,-,-,-,-,-,-,-,-\n36,PL17D,7,-,Comp_OF_PL17C,-,LDQ20,E1,-,J5\n37,PL20A,7,GR_PCLK7_1,True_OF_PL20B,TRUE,LDQS20,H4,B15,G1\n38,VCC,-,-,-,-,-,-,-,-\n39,PL20C,7,GR_PCLK7_0,True_OF_PL20D,-,LDQ20,H5,C16,J3\n40,PL20B,7,-,Comp_OF_PL20A,TRUE,LDQSN20,G5,A16,H2\n41,VSS,-,-,-,-,-,-,-,-\n42,PL20D,7,-,Comp_OF_PL20C,-,LDQ20,H3,-,K3\n43,PL23A,7,PCLKT7_1,True_OF_PL23B,TRUE,LDQ20,G3,A17,J1\n44,VSSIO7,-,-,-,-,-,-,-,-\n45,PL23C,7,PCLKT7_0,True_OF_PL23D,-,LDQ20,F2,B18,K1\n46,PL23B,7,PCLKC7_1,Comp_OF_PL23A,TRUE,LDQ20,F3,B17,J2\n47,VCCIO7,-,-,-,-,-,-,-,-\n48,PL23D,7,PCLKC7_0,Comp_OF_PL23C,-,LDQ20,E2,C17,K2\n49,PL26A,6,PCLKT6_1,True_OF_PL26B,TRUE,LDQ32,G2,D17,L1\n50,VSSIO6,-,-,-,-,-,-,-,-\n51,PL26C,6,PCLKT6_0,True_OF_PL26D,-,LDQ32,H2,D18,M1\n52,PL26B,6,PCLKC6_1,Comp_OF_PL26A,TRUE,LDQ32,F1,C18,L2\n53,VCCIO6,-,-,-,-,-,-,-,-\n54,PL26D,6,PCLKC6_0,Comp_OF_PL26C,-,LDQ32,G1,F18,M2\n55,PL29A,6,GR_PCLK6_0,True_OF_PL29B,TRUE,LDQ32,J4,F17,K4\n56,VCCAUX,-,-,-,-,-,-,-,-\n57,PL29C,6,GR_PCLK6_1,True_OF_PL29D,-,LDQ32,J3,F15,L4\n58,PL29B,6,-,Comp_OF_PL29A,TRUE,LDQ32,J5,F16,K5\n59,VSS,-,-,-,-,-,-,-,-\n60,PL29D,6,-,Comp_OF_PL29C,-,LDQ32,K3,G16,L5\n61,PL32A,6,-,True_OF_PL32B,TRUE,LDQS32,K2,G18,N1\n62,VCC,-,-,-,-,-,-,-,-\n63,PL32C,6,-,True_OF_PL32D,-,LDQ32,H1,-,L3\n64,PL32B,6,-,Comp_OF_PL32A,TRUE,LDQSN32,J1,H17,P2\n65,VSS,-,-,-,-,-,-,-,-\n66,PL32D,6,-,Comp_OF_PL32C,-,LDQ32,K1,-,M3\n67,PL35A,6,-,True_OF_PL35B,TRUE,LDQ32,K4,G15,P1\n68,VSSIO6,-,-,-,-,-,-,-,-\n69,PL35C,6,-,True_OF_PL35D,-,LDQ32,L4,H16,M4\n70,PL35B,6,VREF1_6,Comp_OF_PL35A,TRUE,LDQ32,K5,H15,R1\n71,VCCIO6,-,-,-,-,-,-,-,-\n72,PL35D,6,-,Comp_OF_PL35C,-,LDQ32,L5,J16,N3\n73,PL38A,6,-,True_OF_PL38B,TRUE,LDQ44,M4,-,N4\n74,VSSIO6,-,-,-,-,-,-,-,-\n75,PL38C,6,-,True_OF_PL38D,-,LDQ44,N4,J17,R2\n76,PL38B,6,-,Comp_OF_PL38A,TRUE,LDQ44,N5,-,P3\n77,VCCIO6,-,-,-,-,-,-,-,-\n78,PL38D,6,-,Comp_OF_PL38C,-,LDQ44,P5,H18,T2\n79,PL41A,6,-,True_OF_PL41B,TRUE,LDQ44,N3,J18,P4\n80,VCCAUX,-,-,-,-,-,-,-,-\n81,PL41C,6,-,True_OF_PL41D,-,LDQ44,L3,K16,R4\n82,PL41B,6,-,Comp_OF_PL41A,TRUE,LDQ44,M3,K18,R3\n83,VSS,-,-,-,-,-,-,-,-\n84,PL41D,6,-,Comp_OF_PL41C,-,LDQ44,L2,K15,T3\n85,PL44A,6,-,True_OF_PL44B,TRUE,LDQS44,N2,K17,R5\n86,VCC,-,-,-,-,-,-,-,-\n87,PL44C,6,-,True_OF_PL44D,-,LDQ44,L1,L15,M5\n88,PL44B,6,-,Comp_OF_PL44A,TRUE,LDQSN44,M1,L18,T4\n89,VSS,-,-,-,-,-,-,-,-\n90,PL44D,6,-,Comp_OF_PL44C,-,LDQ44,N1,L16,N5\n91,PL47A,6,-,True_OF_PL47B,TRUE,LDQ44,P1,-,M6\n92,VSSIO6,-,-,-,-,-,-,-,-\n93,PL47B,6,-,Comp_OF_PL47A,TRUE,LDQ44,P2,-,N6\n94,VCCIO6,-,-,-,-,-,-,-,-\n95,PL47C,6,LLC_GPLL0T_IN,True_OF_PL47D,-,LDQ44,P3,M16,P6\n96,PL47D,6,LLC_GPLL0C_IN,Comp_OF_PL47C,-,LDQ44,P4,M17,P5\n97,NC,-,-,-,-,-,-,-,-\n98,NC,-,-,-,-,-,-,-,-\n99,GND,-,-,-,-,-,-,-,-\n100,VCC,-,-,-,-,-,-,-,-\n101,VCC,-,-,-,-,-,-,-,-\n102,VSS,-,-,-,-,-,-,-,-\n103,PB4A,8,D7/IO7,True_OF_PB4B,-,-,R1,N15,T6\n104,PB6A,8,D5/MISO2/IO5,True_OF_PB6B,-,-,U1,N17,R7\n105,VCC,-,-,-,-,-,-,-,-\n106,PB4B,8,D6/IO6,Comp_OF_PB4A,-,-,T1,N16,R6\n107,PB6B,8,D4/MOSI2/IO4,Comp_OF_PB6A,-,-,V1,M18,P7\n108,VSS,-,-,-,-,-,-,-,-\n109,PB9A,8,D3/IO3,True_OF_PB9B,-,-,W1,N18,N7\n110,PB11A,8,D1/MISO/IO1,True_OF_PB11B,-,-,V2,T18,T7\n111,VSSIO8,-,-,-,-,-,-,-,-\n112,PB9B,8,D2/IO2,Comp_OF_PB9A,-,-,Y2,R18,M7\n113,PB11B,8,D0/MOSI/IO0,Comp_OF_PB11A,-,-,W2,U18,T8\n114,VCCIO8,-,-,-,-,-,-,-,-\n115,PB13A,8,SN/CSN,True_OF_PB13B,-,-,T2,R17,R8\n116,PB15A,8,HOLDN/DI/BUSY/CSSPIN/CEN,True_OF_PB15B,-,-,R2,U17,N8\n117,VSSIO8,-,-,-,-,-,-,-,-\n118,PB13B,8,CS1N,Comp_OF_PB13A,-,-,U2,T17,P8\n119,PB15B,8,DOUT/CSON,Comp_OF_PB15A,-,-,R3,V17,M8\n120,VCCIO8,-,-,-,-,-,-,-,-\n121,PB18A,8,WRITEN,-,-,-,T3,R16,M9\n122,INITN,8,-,-,-,-,V3,V16,T9\n123,VCCAUX,-,-,-,-,-,-,-,-\n124,CCLK,8,MCLK/SCK,-,-,-,U3,U16,N9\n125,PROGRAMN,8,-,-,-,-,W3,T15,R9\n126,VSS,-,-,-,-,-,-,-,-\n127,DONE,8,-,-,-,-,Y3,U15,P9\n128,CFG_1,8,-,-,-,-,T4,T14,P10\n129,VCC,-,-,-,-,-,-,-,-\n130,CFG_2,8,-,-,-,-,R4,V15,R10\n131,CFG_0,8,-,-,-,-,U4,U14,N10\n132,VSS,-,-,-,-,-,-,-,-\n133,TDO,40,-,-,-,-,V4,V14,M10\n134,TCK,40,-,-,-,-,T5,U13,T10\n135,VSSIO8,-,-,-,-,-,-,-,-\n136,TDI,40,-,-,-,-,R5,T13,R11\n137,TMS,40,-,-,-,-,U5,V13,T11\n138,VCCIO8,-,-,-,-,-,-,-,-\n139,VCC,-,-,-,-,-,-,-,-\n140,VCC,-,-,-,-,-,-,-,-\n141,VSS,-,-,-,-,-,-,-,-\n142,VSS,-,-,-,-,-,-,-,-\n143,VCC,-,-,-,-,-,-,-,-\n144,VCC,-,-,-,-,-,-,-,-\n145,GND,-,-,-,-,-,-,-,-\n146,GND,-,-,-,-,-,-,-,-\n147,RESERVED,-,-,-,-,-,W4,V12,-\n148,GND,-,-,-,-,-,T7,U12,-\n149,RESERVED,-,-,-,-,-,W5,V11,-\n150,GND,-,-,-,-,-,-,-,-\n151,GND,-,-,-,-,-,-,-,-\n152,GND,-,-,-,-,-,Y5,V9,-\n153,GND,-,-,-,-,-,-,-,-\n154,GND,-,-,-,-,-,T8,U8,-\n155,GND,-,-,-,-,-,Y6,V8,-\n156,GND,-,-,-,-,-,-,-,-\n157,GND,-,-,-,-,-,-,-,-\n158,GND,-,-,-,-,-,Y7,V6,-\n159,GND,-,-,-,-,-,-,-,-\n160,GND,-,-,-,-,-,T9,U6,-\n161,GND,-,-,-,-,-,Y8,V5,-\n162,GND,-,-,-,-,-,-,-,-\n163,GND,-,-,-,-,-,-,-,-\n164,RESERVED,-,-,-,-,-,W8,V3,-\n165,GND,-,-,-,-,-,T10,T5,-\n166,RESERVED,-,-,-,-,-,W9,V2,-\n167,GND,-,-,-,-,-,-,-,-\n168,GND,-,-,-,-,-,-,-,-\n169,RESERVED,-,-,-,-,-,W10,-,-\n170,GND,-,-,-,-,-,-,-,-\n171,RESERVED,-,-,-,-,-,W11,-,-\n172,GND,-,-,-,-,-,-,-,-\n173,GND,-,-,-,-,-,-,-,-\n174,GND,-,-,-,-,-,Y11,U1,-\n175,GND,-,-,-,-,-,-,-,-\n176,GND,-,-,-,-,-,Y12,T1,-\n177,VCC,-,-,-,-,-,-,-,-\n178,VSS,-,-,-,-,-,-,-,-\n179,VCC,-,-,-,-,-,-,-,-\n180,GND,-,-,-,-,-,-,-,-\n181,NC,-,-,-,-,-,-,-,-\n182,NC,-,-,-,-,-,-,-,-\n183,PR47D,3,LRC_GPLL0C_IN,Comp_OF_PR47C,-,RDQ44,T17,N1,P12\n184,PR47C,3,LRC_GPLL0T_IN,True_OF_PR47D,-,RDQ44,U16,M1,P11\n185,VCCIO3,-,-,-,-,-,-,-,-\n186,PR47B,3,-,Comp_OF_PR47A,TRUE,RDQ44,U17,-,N11\n187,VSSIO3,-,-,-,-,-,-,-,-\n188,PR47A,3,-,True_OF_PR47B,TRUE,RDQ44,U18,-,M11\n189,PR44D,3,-,Comp_OF_PR44C,-,RDQ44,T18,N2,N12\n190,VSS,-,-,-,-,-,-,-,-\n191,PR44B,3,-,Comp_OF_PR44A,TRUE,RDQSN44,R18,L1,T13\n192,PR44C,3,-,True_OF_PR44D,-,RDQ44,U19,M2,M12\n193,VCC,-,-,-,-,-,-,-,-\n194,PR44A,3,-,True_OF_PR44B,TRUE,RDQS44,T19,K2,R12\n195,PR41D,3,-,Comp_OF_PR41C,-,RDQ44,U20,K1,T14\n196,VSS,-,-,-,-,-,-,-,-\n197,PR41B,3,-,Comp_OF_PR41A,TRUE,RDQ44,R20,L3,R14\n198,PR41C,3,-,True_OF_PR41D,-,RDQ44,T20,K3,R13\n199,VCCAUX,-,-,-,-,-,-,-,-\n200,PR41A,3,-,True_OF_PR41B,TRUE,RDQ44,P20,M3,P13\n201,PR38D,3,-,Comp_OF_PR38C,-,RDQ44,P18,N3,T15\n202,VCCIO3,-,-,-,-,-,-,-,-\n203,PR38B,3,-,Comp_OF_PR38A,TRUE,RDQ44,N20,L4,P14\n204,PR38C,3,-,True_OF_PR38D,-,RDQ44,P19,N4,R15\n205,VSSIO3,-,-,-,-,-,-,-,-\n206,PR38A,3,-,True_OF_PR38B,TRUE,RDQ44,N19,K4,N13\n207,PR35D,3,-,Comp_OF_PR35C,-,RDQ32,R17,H1,N14\n208,VCCIO3,-,-,-,-,-,-,-,-\n209,PR35B,3,VREF1_3,Comp_OF_PR35A,TRUE,RDQ32,P16,J1,R16\n210,PR35C,3,-,True_OF_PR35D,-,RDQ32,R16,F1,M13\n211,VSSIO3,-,-,-,-,-,-,-,-\n212,PR35A,3,-,True_OF_PR35B,TRUE,RDQ32,N17,J2,P16\n213,PR32D,3,-,Comp_OF_PR32C,-,RDQ32,P17,-,M14\n214,VSS,-,-,-,-,-,-,-,-\n215,PR32B,3,-,Comp_OF_PR32A,TRUE,RDQSN32,M17,G1,P15\n216,PR32C,3,-,True_OF_PR32D,-,RDQ32,N18,-,L14\n217,VCC,-,-,-,-,-,-,-,-\n218,PR32A,3,-,True_OF_PR32B,TRUE,RDQS32,N16,F2,N16\n219,PR29D,3,-,Comp_OF_PR29C,-,RDQ32,M18,H2,L12\n220,VSS,-,-,-,-,-,-,-,-\n221,PR29B,3,-,Comp_OF_PR29A,TRUE,RDQ32,L17,G3,K12\n222,PR29C,3,GR_PCLK3_1,True_OF_PR29D,-,RDQ32,L18,J3,L13\n223,VCCAUX,-,-,-,-,-,-,-,-\n224,PR29A,3,GR_PCLK3_0,True_OF_PR29B,TRUE,RDQ32,L16,H3,K13\n225,PR26D,3,PCLKC3_0,Comp_OF_PR26C,-,RDQ32,M19,F3,M15\n226,VCCIO3,-,-,-,-,-,-,-,-\n227,PR26B,3,PCLKC3_1,Comp_OF_PR26A,TRUE,RDQ32,M20,G4,L15\n228,PR26C,3,PCLKT3_0,True_OF_PR26D,-,RDQ32,L19,F4,M16\n229,VSSIO3,-,-,-,-,-,-,-,-\n230,PR26A,3,PCLKT3_1,True_OF_PR26B,TRUE,RDQ32,L20,H4,L16\n231,PR23D,2,PCLKC2_0,Comp_OF_PR23C,-,RDQ20,K20,D1,K15\n232,VCCIO2,-,-,-,-,-,-,-,-\n233,PR23B,2,PCLKC2_1,Comp_OF_PR23A,TRUE,RDQ20,K19,B1,J15\n234,PR23C,2,PCLKT2_0,True_OF_PR23D,-,RDQ20,J20,C1,K16\n235,VSSIO2,-,-,-,-,-,-,-,-\n236,PR23A,2,PCLKT2_1,True_OF_PR23B,TRUE,RDQ20,J19,D2,J16\n237,PR20D,2,-,Comp_OF_PR20C,-,RDQ20,K18,-,K14\n238,VSS,-,-,-,-,-,-,-,-\n239,PR20B,2,-,Comp_OF_PR20A,TRUE,RDQSN20,H20,B2,H15\n240,PR20C,2,GR_PCLK2_0,True_OF_PR20D,-,RDQ20,J18,A2,J14\n241,VCC,-,-,-,-,-,-,-,-\n242,PR20A,2,GR_PCLK2_1,True_OF_PR20B,TRUE,RDQS20,G19,A3,G16\n243,PR17D,2,-,Comp_OF_PR17C,-,RDQ20,G20,-,J12\n244,VSS,-,-,-,-,-,-,-,-\n245,PR17B,2,-,Comp_OF_PR17A,TRUE,RDQ20,F19,C2,H13\n246,PR17C,2,-,True_OF_PR17D,-,RDQ20,F20,-,J13\n247,VCCAUX,-,-,-,-,-,-,-,-\n248,PR17A,2,-,True_OF_PR17B,TRUE,RDQ20,E20,D3,H12\n249,PR14D,2,-,Comp_OF_PR14C,-,RDQ20,E19,C3,H14\n250,VCCIO2,-,-,-,-,-,-,-,-\n251,PR14B,2,-,Comp_OF_PR14A,TRUE,RDQ20,D19,C4,G15\n252,PR14C,2,VREF1_2,True_OF_PR14D,-,RDQ20,D20,B4,G14\n253,VSSIO2,-,-,-,-,-,-,-,-\n254,PR14A,2,-,True_OF_PR14B,TRUE,RDQ20,C20,D4,F16\n255,PR11D,2,-,Comp_OF_PR11C,-,RDQ8,J16,-,E16\n256,VCCIO2,-,-,-,-,-,-,-,-\n257,PR11B,2,-,Comp_OF_PR11A,TRUE,RDQ8,H17,A4,G13\n258,PR11C,2,-,True_OF_PR11D,-,RDQ8,J17,-,F15\n259,VSSIO2,-,-,-,-,-,-,-,-\n260,PR11A,2,-,True_OF_PR11B,TRUE,RDQ8,H18,A6,G12\n261,PR8D,2,-,Comp_OF_PR8C,-,RDQ8,H16,-,F12\n262,VSS,-,-,-,-,-,-,-,-\n263,PR8B,2,-,Comp_OF_PR8A,TRUE,RDQSN8,G18,A7,E15\n264,PR8C,2,-,True_OF_PR8D,-,RDQ8,G16,-,F13\n265,VCC,-,-,-,-,-,-,-,-\n266,PR8A,2,-,True_OF_PR8B,TRUE,RDQS8,F17,B6,D16\n267,PR5D,2,-,Comp_OF_PR5C,-,RDQ8,F18,-,F14\n268,VSS,-,-,-,-,-,-,-,-\n269,PR5B,2,-,Comp_OF_PR5A,TRUE,RDQ8,E17,C6,C15\n270,PR5C,2,-,True_OF_PR5D,-,RDQ8,E18,-,E14\n271,VCCAUX,-,-,-,-,-,-,-,-\n272,PR5A,2,-,True_OF_PR5B,TRUE,RDQ8,D18,D6,C16\n273,PR2D,2,-,Comp_OF_PR2C,-,RDQ8,F16,-,D14\n274,VCCIO2,-,-,-,-,-,-,-,-\n275,PR2C,2,-,True_OF_PR2D,-,RDQ8,E16,-,C14\n276,VSSIO2,-,-,-,-,-,-,-,-\n277,PR2B,2,S0_IN,Comp_OF_PR2A,TRUE,RDQ8,D17,B7,B15\n278,PR2A,2,-,True_OF_PR2B,TRUE,RDQ8,C18,C7,B16\n279,GND,-,-,-,-,-,-,-,-\n280,VCC,-,-,-,-,-,-,-,-\n281,VSS,-,-,-,-,-,-,-,-\n282,VCC,-,-,-,-,-,-,-,-\n283,PT67B,1,-,Comp_OF_PT67A,-,-,B20,C8,A15\n284,VCCIO1,-,-,-,-,-,-,-,-\n285,PT65B,1,-,Comp_OF_PT65A,-,-,B19,-,A14\n286,PT67A,1,-,True_OF_PT67B,-,-,A19,B8,B14\n287,VSSIO1,-,-,-,-,-,-,-,-\n288,PT65A,1,-,True_OF_PT65B,-,-,A18,-,A13\n289,PT62B,1,-,Comp_OF_PT62A,-,-,B18,-,E13\n290,VSS,-,-,-,-,-,-,-,-\n291,PT60B,1,-,Comp_OF_PT60A,-,-,C17,-,C13\n292,PT62A,1,-,True_OF_PT62B,-,-,A17,-,D13\n293,VCC,-,-,-,-,-,-,-,-\n294,PT60A,1,-,True_OF_PT60B,-,-,B17,-,B13\n295,PT58B,1,-,Comp_OF_PT58A,-,-,D16,-,E12\n296,VSS,-,-,-,-,-,-,-,-\n297,PT56B,1,-,Comp_OF_PT56A,-,-,B16,-,C12\n298,PT58A,1,-,True_OF_PT58B,-,-,C16,-,D12\n299,VCCAUX,-,-,-,-,-,-,-,-\n300,PT56A,1,-,True_OF_PT56B,-,-,A16,-,B12\n301,PT53B,1,-,Comp_OF_PT53A,-,-,E15,-,A12\n302,VCCIO1,-,-,-,-,-,-,-,-\n303,PT51B,1,-,Comp_OF_PT51A,-,-,C15,-,E11\n304,PT53A,1,-,True_OF_PT53B,-,-,D15,-,A11\n305,VSSIO1,-,-,-,-,-,-,-,-\n306,PT51A,1,-,True_OF_PT51B,-,-,B15,-,D11\n307,PT49B,1,-,Comp_OF_PT49A,-,-,E14,-,C11\n308,VCCIO1,-,-,-,-,-,-,-,-\n309,PT47B,1,-,Comp_OF_PT47A,-,-,C14,-,E10\n310,PT49A,1,-,True_OF_PT49B,-,-,D14,-,B11\n311,VSSIO1,-,-,-,-,-,-,-,-\n312,PT47A,1,-,True_OF_PT47B,-,-,A14,-,D10\n313,PT44B,1,-,Comp_OF_PT44A,-,-,E13,-,C10\n314,VSS,-,-,-,-,-,-,-,-\n315,PT42B,1,-,Comp_OF_PT42A,-,-,C13,-,A10\n316,PT44A,1,-,True_OF_PT44B,-,-,D13,-,B10\n317,VCC,-,-,-,-,-,-,-,-\n318,PT42A,1,-,True_OF_PT42B,-,-,B13,-,A9\n319,PT40B,1,-,Comp_OF_PT40A,-,-,A13,-,E9\n320,VSS,-,-,-,-,-,-,-,-\n321,PT38B,1,GR_PCLK1_1,Comp_OF_PT38A,-,-,E12,-,C9\n322,PT40A,1,-,True_OF_PT40B,-,-,A12,-,D9\n323,VCCAUX,-,-,-,-,-,-,-,-\n324,PT38A,1,GR_PCLK1_0,True_OF_PT38B,-,-,D12,-,B9\n325,PT35B,1,PCLKC1_0,Comp_OF_PT35A,-,-,C12,A8,B8\n326,VCCIO1,-,-,-,-,-,-,-,-\n327,PT33B,1,PCLKC1_1,Comp_OF_PT33A,-,-,E11,C9,D8\n328,PT35A,1,PCLKT1_0,True_OF_PT35B,-,-,B12,A9,C8\n329,VSSIO1,-,-,-,-,-,-,-,-\n330,PT33A,1,PCLKT1_1,True_OF_PT33B,-,-,D11,B9,E8\n331,VSS,-,-,-,-,-,-,-,-\n332,VCC,-,-,-,-,-,-,-,-\n333,PT29B,0,PCLKC0_0,Comp_OF_PT29A,-,-,C11,C10,A8\n334,VCCIO0,-,-,-,-,-,-,-,-\n335,PT27B,0,PCLKC0_1,Comp_OF_PT27A,-,-,A11,A10,B7\n336,PT29A,0,PCLKT0_0,True_OF_PT29B,-,-,B11,B10,A7\n337,VSSIO0,-,-,-,-,-,-,-,-\n338,PT27A,0,PCLKT0_1,True_OF_PT27B,-,-,A10,A11,C7\n339,PT24B,0,GR_PCLK0_0,Comp_OF_PT24A,-,-,B10,-,D7\n340,VSS,-,-,-,-,-,-,-,-\n341,PT22B,0,-,Comp_OF_PT22A,-,-,C10,-,B6\n342,PT24A,0,GR_PCLK0_1,True_OF_PT24B,-,-,A9,-,E7\n343,VCC,-,-,-,-,-,-,-,-\n344,PT22A,0,-,True_OF_PT22B,-,-,B9,-,C6\n345,PT20B,0,-,Comp_OF_PT20A,-,-,E9,-,D6\n346,VSS,-,-,-,-,-,-,-,-\n347,PT18B,0,-,Comp_OF_PT18A,-,-,A8,-,A6\n348,PT20A,0,-,True_OF_PT20B,-,-,D9,-,E6\n349,VCCAUX,-,-,-,-,-,-,-,-\n350,PT18A,0,-,True_OF_PT18B,-,-,A7,-,A5\n351,PT15B,0,-,Comp_OF_PT15A,-,-,B8,-,B5\n352,VCCIO0,-,-,-,-,-,-,-,-\n353,PT13B,0,-,Comp_OF_PT13A,-,-,D8,-,D5\n354,PT15A,0,-,True_OF_PT15B,-,-,C8,-,C5\n355,VSSIO0,-,-,-,-,-,-,-,-\n356,PT13A,0,-,True_OF_PT13B,-,-,E8,-,E5\n357,PT11B,0,-,Comp_OF_PT11A,-,-,C7,-,B4\n358,VCCIO0,-,-,-,-,-,-,-,-\n359,PT9B,0,-,Comp_OF_PT9A,-,-,D7,-,D4\n360,PT11A,0,-,True_OF_PT11B,-,-,C6,-,C4\n361,VSSIO0,-,-,-,-,-,-,-,-\n362,PT9A,0,-,True_OF_PT9B,-,-,E7,-,E4\n363,PT6B,0,-,Comp_OF_PT6A,-,-,D6,-,A4\n364,VSS,-,-,-,-,-,-,-,-\n365,PT4B,0,-,Comp_OF_PT4A,-,-,B6,C11,B3\n366,PT6A,0,-,True_OF_PT6B,-,-,E6,-,A3\n367,VCC,-,-,-,-,-,-,-,-\n368,PT4A,0,-,True_OF_PT4B,-,-,A6,B11,A2\n369,VSS,-,-,-,-,-,-,-,-\n370,VCC,-,-,-,-,-,-,-,-\n371,VCC,-,-,-,-,-,-,-,-\n372,GND,-,-,-,-,-,-,-,-\n0,NC,-,-,-,-,-,-,-,-\n0,GND,-,-,-,-,-,C19,G2,A16\n0,GND,-,-,-,-,-,H19,L2,H16\n0,GND,-,-,-,-,-,R19,B3,T16\n0,GND,-,-,-,-,-,G17,E5,D15\n0,GND,-,-,-,-,-,M16,F5,N15\n0,GND,-,-,-,-,-,G15,K5,T12\n0,GND,-,-,-,-,-,K15,L5,G10\n0,GND,-,-,-,-,-,N15,F6,H10\n0,GND,-,-,-,-,-,B14,G6,J10\n0,GND,-,-,-,-,-,F14,H6,K10\n0,GND,-,-,-,-,-,G14,J6,F9\n0,GND,-,-,-,-,-,J14,K6,H9\n0,GND,-,-,-,-,-,K14,L6,J9\n0,GND,-,-,-,-,-,M14,M6,K9\n0,GND,-,-,-,-,-,N14,E7,F8\n0,GND,-,-,-,-,-,P14,F7,G8\n0,GND,-,-,-,-,-,F13,G7,H8\n0,GND,-,-,-,-,-,G13,H7,J8\n0,GND,-,-,-,-,-,P13,J7,K8\n0,GND,-,-,-,-,-,G12,K7,K7\n0,GND,-,-,-,-,-,J12,L7,K6\n0,GND,-,-,-,-,-,K12,M7,T5\n0,GND,-,-,-,-,-,L12,N7,D2\n0,GND,-,-,-,-,-,M12,E8,N2\n0,GND,-,-,-,-,-,P12,F8,A1\n0,GND,-,-,-,-,-,G11,G8,H1\n0,GND,-,-,-,-,-,J11,H8,T1\n0,GND,-,-,-,-,-,K11,J8,-\n0,GND,-,-,-,-,-,L11,K8,-\n0,GND,-,-,-,-,-,M11,L8,-\n0,GND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  },
  {
    "path": "doc/LFE5U-25F-5BG256-Pinout.csv",
    "content": "# Pin Out For ECP5U-25,,,,,,,,,,\n# Revision 1.1 - Include CABGA256 package,,,,,,,,,,\n\"# Revised Oct. 17, 2017\",,,,,,,,,,\n,,,,,,,,,,\nPAD,Bank,Pin/Ball Function,,Dual Function,,High Speed,,DQS,DESC,CABGA256\n1,7,PL2A,,,/,HS+,/,LDQ8,PL2A/HS+/LDQ8,B1\n2,7,PL2B,,,/,HS-,/,LDQ8,PL2B/HS-/LDQ8,B2\n4,7,PL2C,,,/,+,/,LDQ8,PL2C/+/LDQ8,C3\n6,7,PL2D,,,/,-,/,LDQ8,PL2D/-/LDQ8,D3\n7,7,PL5A,,,/,HS+,/,LDQ8,PL5A/HS+/LDQ8,C1\n9,7,PL5C,,,/,-,/,LDQ8,PL5C/-/LDQ8,E3\n10,7,PL5B,,,/,HS-,/,LDQ8,PL5B/HS-/LDQ8,C2\n12,7,PL5D,,,/,-,/,LDQ8,PL5D/-/LDQ8,F3\n13,7,PL8A,,,/,HS+,/,LDQS8,PL8A/HS+/LDQS8,D1\n15,7,PL8C,,,/,+,/,LDQ8,PL8C/+/LDQ8,F4\n16,7,PL8B,,,/,HS-,/,LDQSN8,PL8B/HS-/LDQSN8,E2\n18,7,PL8D,,,/,-,/,LDQ8,PL8D/-/LDQ8,F5\n19,7,PL11A,,,/,HS+,/,LDQ8,PL11A/HS+/LDQ8,G5\n21,7,PL11C,,,/,-,/,LDQ8,PL11C/-/LDQ8,F2\n22,7,PL11B,,,/,HS-,/,LDQ8,PL11B/HS-/LDQ8,G4\n24,7,PL11D,,,/,-,/,LDQ8,PL11D/-/LDQ8,E1\n25,7,PL14A,,,/,HS+,/,LDQ20,PL14A/HS+/LDQ20,F1\n27,7,PL14C,/,VREF1_7,/,+,/,LDQ20,PL14C/VREF1_7/+/LDQ20,G3\n28,7,PL14B,,,/,HS-,/,LDQ20,PL14B/HS-/LDQ20,G2\n30,7,PL14D,,,/,-,/,LDQ20,PL14D/-/LDQ20,H3\n31,7,PL17A,,,/,HS+,/,LDQ20,PL17A/HS+/LDQ20,H5\n33,7,PL17C,,,/,+,/,LDQ20,PL17C/+/LDQ20,J4\n34,7,PL17B,,,/,HS-,/,LDQ20,PL17B/HS-/LDQ20,H4\n36,7,PL17D,,,/,-,/,LDQ20,PL17D/-/LDQ20,J5\n37,7,PL20A,/,GR_PCLK7_1,/,HS+,/,LDQS20,PL20A/GR_PCLK7_1/HS+/LDQS20,G1\n39,7,PL20C,/,GR_PCLK7_0,/,+,/,LDQ20,PL20C/GR_PCLK7_0/+/LDQ20,J3\n40,7,PL20B,,,/,HS-,/,LDQSN20,PL20B/HS-/LDQSN20,H2\n42,7,PL20D,,,/,-,/,LDQ20,PL20D/-/LDQ20,K3\n43,7,PL23A,/,PCLKT7_1,/,HS+,/,LDQ20,PL23A/PCLKT7_1/HS+/LDQ20,J1\n45,7,PL23C,/,PCLKT7_0,/,+,/,LDQ20,PL23C/PCLKT7_0/+/LDQ20,K1\n46,7,PL23B,/,PCLKC7_1,/,HS-,/,LDQ20,PL23B/PCLKC7_1/HS-/LDQ20,J2\n48,7,PL23D,/,PCLKC7_0,/,-,/,LDQ20,PL23D/PCLKC7_0/-/LDQ20,K2\n49,6,PL26A,/,PCLKT6_1,/,HS+,/,LDQ32,PL26A/PCLKT6_1/HS+/LDQ32,L1\n51,6,PL26C,/,PCLKT6_0,/,+,/,LDQ32,PL26C/PCLKT6_0/+/LDQ32,M1\n52,6,PL26B,/,PCLKC6_1,/,HS-,/,LDQ32,PL26B/PCLKC6_1/HS-/LDQ32,L2\n54,6,PL26D,/,PCLKC6_0,/,-,/,LDQ32,PL26D/PCLKC6_0/-/LDQ32,M2\n55,6,PL29A,/,GR_PCLK6_0,/,HS+,/,LDQ32,PL29A/GR_PCLK6_0/HS+/LDQ32,K4\n57,6,PL29C,/,GR_PCLK6_1,/,+,/,LDQ32,PL29C/GR_PCLK6_1/+/LDQ32,L4\n58,6,PL29B,,,/,HS-,/,LDQ32,PL29B/HS-/LDQ32,K5\n60,6,PL29D,,,/,-,/,LDQ32,PL29D/-/LDQ32,L5\n61,6,PL32A,,,/,HS+,/,LDQS32,PL32A/HS+/LDQS32,N1\n63,6,PL32C,,,/,+,/,LDQ32,PL32C/+/LDQ32,L3\n64,6,PL32B,,,/,HS-,/,LDQSN32,PL32B/HS-/LDQSN32,P2\n66,6,PL32D,,,/,-,/,LDQ32,PL32D/-/LDQ32,M3\n67,6,PL35A,,,/,HS+,/,LDQ32,PL35A/HS+/LDQ32,P1\n69,6,PL35C,,,/,+,/,LDQ32,PL35C/+/LDQ32,M4\n70,6,PL35B,/,VREF1_6,/,HS-,/,LDQ32,PL35B/VREF1_6/HS-/LDQ32,R1\n72,6,PL35D,,,/,-,/,LDQ32,PL35D/-/LDQ32,N3\n73,6,PL38A,,,/,HS+,/,LDQ44,PL38A/HS+/LDQ44,N4\n75,6,PL38C,,,/,+,/,LDQ44,PL38C/+/LDQ44,R2\n76,6,PL38B,,,/,HS-,/,LDQ44,PL38B/HS-/LDQ44,P3\n78,6,PL38D,,,/,-,/,LDQ44,PL38D/-/LDQ44,T2\n79,6,PL41A,,,/,HS+,/,LDQ44,PL41A/HS+/LDQ44,P4\n81,6,PL41C,,,/,+,/,LDQ44,PL41C/+/LDQ44,R4\n82,6,PL41B,,,/,HS-,/,LDQ44,PL41B/HS-/LDQ44,R3\n84,6,PL41D,,,/,-,/,LDQ44,PL41D/-/LDQ44,T3\n85,6,PL44A,,,/,HS+,/,LDQS44,PL44A/HS+/LDQS44,R5\n87,6,PL44C,,,/,+,/,LDQ44,PL44C/+/LDQ44,M5\n88,6,PL44B,,,/,HS-,/,LDQSN44,PL44B/HS-/LDQSN44,T4\n90,6,PL44D,,,/,-,/,LDQ44,PL44D/-/LDQ44,N5\n91,6,PL47A,,,/,HS+,/,LDQ44,PL47A/HS+/LDQ44,M6\n93,6,PL47B,,,/,HS-,/,LDQ44,PL47B/HS-/LDQ44,N6\n95,6,PL47C,/,LLC_GPLL0T_IN,/,+,/,LDQ44,PL47C/LLC_GPLL0T_IN/+/LDQ44,P6\n96,6,PL47D,/,LLC_GPLL0C_IN,/,-,/,LDQ44,PL47D/LLC_GPLL0C_IN/-/LDQ44,P5\n103,8,PB4A,/,D7/IO7,/,+,,,PB4A/D7/IO7/+,T6\n104,8,PB6A,/,D5/MISO2/IO5,/,+,,,PB6A/D5/MISO2/IO5/+,R7\n106,8,PB4B,/,D6/IO6,/,-,,,PB4B/D6/IO6/-,R6\n107,8,PB6B,/,D4/MOSI2/IO4,/,-,,,PB6B/D4/MOSI2/IO4/-,P7\n109,8,PB9A,/,D3/IO3,/,+,,,PB9A/D3/IO3/+,N7\n110,8,PB11A,/,D1/MISO/IO1,/,+,,,PB11A/D1/MISO/IO1/+,T7\n112,8,PB9B,/,D2/IO2,/,-,,,PB9B/D2/IO2/-,M7\n113,8,PB11B,/,D0/MOSI/IO0,/,-,,,PB11B/D0/MOSI/IO0/-,T8\n115,8,PB13A,/,SN/CSN,/,+,,,PB13A/SN/CSN/+,R8\n116,8,PB15A,/,HOLDN/DI/BUSY/CSSPIN/CEN,/,+,,,PB15A/HOLDN/DI/BUSY/CSSPIN/CEN/+,N8\n118,8,PB13B,/,CS1N,/,-,,,PB13B/CS1N/-,P8\n119,8,PB15B,/,DOUT/CSON,/,-,,,PB15B/DOUT/CSON/-,M8\n121,8,PB18A,/,WRITEN,,,,,PB18A/WRITEN,M9\n122,8,INITN,,,,,,,INITN,T9\n124,8,CCLK,/,MCLK/SCK,,,,,CCLK/MCLK/SCK,N9\n125,8,PROGRAMN,,,,,,,PROGRAMN,R9\n127,8,DONE,,,,,,,DONE,P9\n128,8,CFG_1,,,,,,,CFG_1,P10\n130,8,CFG_2,,,,,,,CFG_2,R10\n131,8,CFG_0,,,,,,,CFG_0,N10\n133,40,TDO,,,,,,,TDO,M10\n134,40,TCK,,,,,,,TCK,T10\n136,40,TDI,,,,,,,TDI,R11\n137,40,TMS,,,,,,,TMS,T11\n183,3,PR47D,/,LRC_GPLL0C_IN,/,-,/,RDQ44,PR47D/LRC_GPLL0C_IN/-/RDQ44,P12\n184,3,PR47C,/,LRC_GPLL0T_IN,/,+,/,RDQ44,PR47C/LRC_GPLL0T_IN/+/RDQ44,P11\n186,3,PR47B,,,/,HS-,/,RDQ44,PR47B/HS-/RDQ44,N11\n188,3,PR47A,,,/,HS+,/,RDQ44,PR47A/HS+/RDQ44,M11\n189,3,PR44D,,,/,-,/,RDQ44,PR44D/-/RDQ44,N12\n191,3,PR44B,,,/,HS-,/,RDQSN44,PR44B/HS-/RDQSN44,T13\n192,3,PR44C,,,/,+,/,RDQ44,PR44C/+/RDQ44,M12\n194,3,PR44A,,,/,HS+,/,RDQS44,PR44A/HS+/RDQS44,R12\n195,3,PR41D,,,/,-,/,RDQ44,PR41D/-/RDQ44,T14\n197,3,PR41B,,,/,HS-,/,RDQ44,PR41B/HS-/RDQ44,R14\n198,3,PR41C,,,/,+,/,RDQ44,PR41C/+/RDQ44,R13\n200,3,PR41A,,,/,HS+,/,RDQ44,PR41A/HS+/RDQ44,P13\n201,3,PR38D,,,/,-,/,RDQ44,PR38D/-/RDQ44,T15\n203,3,PR38B,,,/,HS,/,RDQ44,PR38B/HS/RDQ44,P14\n204,3,PR38C,,,/,+,/,RDQ44,PR38C/+/RDQ44,R15\n206,3,PR38A,,,/,HS+,/,RDQ44,PR38A/HS+/RDQ44,N13\n207,3,PR35D,,,/,-,/,RDQ32,PR35D/-/RDQ32,N14\n209,3,PR35B,/,VREF1_3,/,HS-,/,RDQ32,PR35B/VREF1_3/HS-/RDQ32,R16\n210,3,PR35C,,,/,+,/,RDQ32,PR35C/+/RDQ32,M13\n212,3,PR35A,,,/,HS+,/,RDQ32,PR35A/HS+/RDQ32,P16\n213,3,PR32D,,,/,-,/,RDQ32,PR32D/-/RDQ32,M14\n215,3,PR32B,,,/,HS-,/,RDQSN32,PR32B/HS-/RDQSN32,P15\n216,3,PR32C,,,/,+,/,RDQ32,PR32C/+/RDQ32,L14\n218,3,PR32A,,,/,HS+,/,RDQS32,PR32A/HS+/RDQS32,N16\n219,3,PR29D,,,/,-,/,RDQ32,PR29D/-/RDQ32,L12\n221,3,PR29B,,,/,HS-,/,RDQ32,PR29B/HS-/RDQ32,K12\n222,3,PR29C,/,GR_PCLK3_1,/,+,/,RDQ32,PR29C/GR_PCLK3_1/+/RDQ32,L13\n224,3,PR29A,/,GR_PCLK3_0,/,HS+,/,RDQ32,PR29A/GR_PCLK3_0/HS+/RDQ32,K13\n225,3,PR26D,/,PCLKC3_0,/,-,/,RDQ32,PR26D/PCLKC3_0/-/RDQ32,M15\n227,3,PR26B,/,PCLKC3_1,/,HS-,/,RDQ32,PR26B/PCLKC3_1/HS-/RDQ32,L15\n228,3,PR26C,/,PCLKT3_0,/,+,/,RDQ32,PR26C/PCLKT3_0/+/RDQ32,M16\n230,3,PR26A,/,PCLKT3_1,/,HS+,/,RDQ32,PR26A/PCLKT3_1/HS+/RDQ32,L16\n231,2,PR23D,/,PCLKC2_0,/,-,/,RDQ20,PR23D/PCLKC2_0/-/RDQ20,K15\n233,2,PR23B,/,PCLKC2_1,/,HS-,/,RDQ20,PR23B/PCLKC2_1/HS-/RDQ20,J15\n234,2,PR23C,/,PCLKT2_0,/,+,/,RDQ20,PR23C/PCLKT2_0/+/RDQ20,K16\n236,2,PR23A,/,PCLKT2_1,/,HS+,/,RDQ20,PR23A/PCLKT2_1/HS+/RDQ20,J16\n237,2,PR20D,,,/,-,/,RDQ20,PR20D/-/RDQ20,K14\n239,2,PR20B,,,/,HS,/,RDQSN20,PR20B/HS/RDQSN20,H15\n240,2,PR20C,/,GR_PCLK2_0,/,+,/,RDQ20,PR20C/GR_PCLK2_0/+/RDQ20,J14\n242,2,PR20A,/,GR_PCLK2_1,/,HS+,/,RDQS20,PR20A/GR_PCLK2_1/HS+/RDQS20,G16\n243,2,PR17D,,,/,-,/,RDQ20,PR17D/-/RDQ20,J12\n245,2,PR17B,,,/,HS-,/,RDQ20,PR17B/HS-/RDQ20,H13\n246,2,PR17C,,,/,+,/,RDQ20,PR17C/+/RDQ20,J13\n248,2,PR17A,,,/,HS+,/,RDQ20,PR17A/HS+/RDQ20,H12\n249,2,PR14D,,,/,-,/,RDQ20,PR14D/-/RDQ20,H14\n251,2,PR14B,,,/,HS-,/,RDQ20,PR14B/HS-/RDQ20,G15\n252,2,PR14C,/,VREF1_2,/,+,/,RDQ20,PR14C/VREF1_2/+/RDQ20,G14\n254,2,PR14A,,,/,HS+,/,RDQ20,PR14A/HS+/RDQ20,F16\n255,2,PR11D,,,/,-,/,RDQ8,PR11D/-/RDQ8,E16\n257,2,PR11B,,,/,HS-,/,RDQ8,PR11B/HS-/RDQ8,G13\n258,2,PR11C,,,/,+,/,RDQ8,PR11C/+/RDQ8,F15\n260,2,PR11A,,,/,HS+,/,RDQ8,PR11A/HS+/RDQ8,G12\n261,2,PR8D,,,/,-,/,RDQ8,PR8D/-/RDQ8,F12\n263,2,PR8B,,,/,HS-,/,RDQSN8,PR8B/HS-/RDQSN8,E15\n264,2,PR8C,,,/,+,/,RDQ8,PR8C/+/RDQ8,F13\n266,2,PR8A,,,/,HS+,/,RDQS8,PR8A/HS+/RDQS8,D16\n267,2,PR5D,,,/,-,/,RDQ8,PR5D/-/RDQ8,F14\n269,2,PR5B,,,/,HS-,/,RDQ8,PR5B/HS-/RDQ8,C15\n270,2,PR5C,,,/,+,/,RDQ8,PR5C/+/RDQ8,E14\n272,2,PR5A,,,/,HS+,/,RDQ8,PR5A/HS+/RDQ8,C16\n273,2,PR2D,,,/,-,/,RDQ8,PR2D/-/RDQ8,D14\n275,2,PR2C,,,/,+,/,RDQ8,PR2C/+/RDQ8,C14\n277,2,PR2B,/,S0_IN,/,HS-,/,RDQ8,PR2B/S0_IN/HS-/RDQ8,B15\n278,2,PR2A,,,/,HS+,/,RDQ8,PR2A/HS+/RDQ8,B16\n283,1,PT67B,,,/,-,,,PT67B/-,A15\n285,1,PT65B,,,/,-,,,PT65B/-,A14\n286,1,PT67A,,,/,+,,,PT67A/+,B14\n288,1,PT65A,,,/,+,,,PT65A/+,A13\n289,1,PT62B,,,/,-,,,PT62B/-,E13\n291,1,PT60B,,,/,-,,,PT60B/-,C13\n292,1,PT62A,,,/,+,,,PT62A/+,D13\n294,1,PT60A,,,/,+,,,PT60A/+,B13\n295,1,PT58B,,,/,-,,,PT58B/-,E12\n297,1,PT56B,,,/,-,,,PT56B/-,C12\n298,1,PT58A,,,/,+,,,PT58A/+,D12\n300,1,PT56A,,,/,+,,,PT56A/+,B12\n301,1,PT53B,,,/,-,,,PT53B/-,A12\n303,1,PT51B,,,/,-,,,PT51B/-,E11\n304,1,PT53A,,,/,+,,,PT53A/+,A11\n306,1,PT51A,,,/,+,,,PT51A/+,D11\n307,1,PT49B,,,/,-,,,PT49B/-,C11\n309,1,PT47B,,,/,-,,,PT47B/-,E10\n310,1,PT49A,,,/,+,,,PT49A/+,B11\n312,1,PT47A,,,/,+,,,PT47A/+,D10\n313,1,PT44B,,,/,-,,,PT44B/-,C10\n315,1,PT42B,,,/,-,,,PT42B/-,A10\n316,1,PT44A,,,/,+,,,PT44A/+,B10\n318,1,PT42A,,,/,+,,,PT42A/+,A9\n319,1,PT40B,,,/,-,,,PT40B/-,E9\n321,1,PT38B,/,GR_PCLK1_1,/,-,,,PT38B/GR_PCLK1_1/-,C9\n322,1,PT40A,,,/,+,,,PT40A/+,D9\n324,1,PT38A,/,GR_PCLK1_0,/,+,,,PT38A/GR_PCLK1_0/+,B9\n325,1,PT35B,/,PCLKC1_0,/,-,,,PT35B/PCLKC1_0/-,B8\n327,1,PT33B,/,PCLKC1_1,/,-,,,PT33B/PCLKC1_1/-,D8\n328,1,PT35A,/,PCLKT1_0,/,+,,,PT35A/PCLKT1_0/+,C8\n330,1,PT33A,/,PCLKT1_1,/,+,,,PT33A/PCLKT1_1/+,E8\n333,0,PT29B,/,PCLKC0_0,/,-,,,PT29B/PCLKC0_0/-,A8\n335,0,PT27B,/,PCLKC0_1,/,-,,,PT27B/PCLKC0_1/-,B7\n336,0,PT29A,/,PCLKT0_0,/,+,,,PT29A/PCLKT0_0/+,A7\n338,0,PT27A,/,PCLKT0_1,/,+,,,PT27A/PCLKT0_1/+,C7\n339,0,PT24B,/,GR_PCLK0_0,/,-,,,PT24B/GR_PCLK0_0/-,D7\n341,0,PT22B,,,/,-,,,PT22B/-,B6\n342,0,PT24A,/,GR_PCLK0_1,/,+,,,PT24A/GR_PCLK0_1/+,E7\n344,0,PT22A,,,/,+,,,PT22A/+,C6\n345,0,PT20B,,,/,-,,,PT20B/-,D6\n347,0,PT18B,,,/,-,,,PT18B/-,A6\n348,0,PT20A,,,/,+,,,PT20A/+,E6\n350,0,PT18A,,,/,+,,,PT18A/+,A5\n351,0,PT15B,,,/,-,,,PT15B/-,B5\n353,0,PT13B,,,/,-,,,PT13B/-,D5\n354,0,PT15A,,,/,+,,,PT15A/+,C5\n356,0,PT13A,,,/,+,,,PT13A/+,E5\n357,0,PT11B,,,/,-,,,PT11B/-,B4\n359,0,PT9B,,,/,-,,,PT9B/-,D4\n360,0,PT11A,,,/,+,,,PT11A/+,C4\n362,0,PT9A,,,/,+,,,PT9A/+,E4\n363,0,PT6B,,,/,-,,,PT6B/-,A4\n365,0,PT4B,,,/,-,,,PT4B/-,B3\n366,0,PT6A,,,/,+,,,PT6A/+,A3\n368,0,PT4A,,,/,+,,,PT4A/+,A2\n0,-,GND,,,,,,,GND,A16\n0,-,GND,,,,,,,GND,H16\n0,-,GND,,,,,,,GND,T16\n0,-,GND,,,,,,,GND,D15\n0,-,GND,,,,,,,GND,N15\n0,-,GND,,,,,,,GND,T12\n0,-,GND,,,,,,,GND,G10\n0,-,GND,,,,,,,GND,H10\n0,-,GND,,,,,,,GND,J10\n0,-,GND,,,,,,,GND,K10\n0,-,GND,,,,,,,GND,F9\n0,-,GND,,,,,,,GND,H9\n0,-,GND,,,,,,,GND,J9\n0,-,GND,,,,,,,GND,K9\n0,-,GND,,,,,,,GND,F8\n0,-,GND,,,,,,,GND,G8\n0,-,GND,,,,,,,GND,H8\n0,-,GND,,,,,,,GND,J8\n0,-,GND,,,,,,,GND,K8\n0,-,GND,,,,,,,GND,K7\n0,-,GND,,,,,,,GND,K6\n0,-,GND,,,,,,,GND,T5\n0,-,GND,,,,,,,GND,D2\n0,-,GND,,,,,,,GND,N2\n0,-,GND,,,,,,,GND,A1\n0,-,GND,,,,,,,GND,H1\n0,-,GND,,,,,,,GND,T1\n0,-,VCC,,,,,,,VCC,L10\n0,-,VCC,,,,,,,VCC,G9\n0,-,VCC,,,,,,,VCC,L9\n0,-,VCC,,,,,,,VCC,L8\n0,-,VCC,,,,,,,VCC,G7\n0,-,VCC,,,,,,,VCC,G6\n0,-,VCCAUX,,,,,,,VCCAUX,G11\n0,-,VCCAUX,,,,,,,VCCAUX,L7\n0,0,VCCIO0,,,,,,,VCCIO0,F7\n0,0,VCCIO0,,,,,,,VCCIO0,F6\n0,1,VCCIO1,,,,,,,VCCIO1,F11\n0,1,VCCIO1,,,,,,,VCCIO1,F10\n0,2,VCCIO2,,,,,,,VCCIO2,H11\n0,2,VCCIO2,,,,,,,VCCIO2,J11\n0,3,VCCIO3,,,,,,,VCCIO3,K11\n0,3,VCCIO3,,,,,,,VCCIO3,L11\n0,8,VCCIO8,,,,,,,VCCIO8,L6\n0,6,VCCIO6,,,,,,,VCCIO6,J7\n0,6,VCCIO6,,,,,,,VCCIO6,J6\n0,7,VCCIO7,,,,,,,VCCIO7,H7\n0,7,VCCIO7,,,,,,,VCCIO7,H6\n"
  },
  {
    "path": "firmware/README.md",
    "content": "this 128KB firmware include usb-hid & usb-cdc device\n"
  },
  {
    "path": "linux/README.md",
    "content": "## How-To-Boot-Linux\n\n1. program the bitstream  \n`$icesprog ../demo/linux-with-litex.bit`\n\n2. put system files into the rootdir of sdcard (the sdcard should be formatted as fat32 file system before)\n`$cp * ${YOUR_USB_DISK}`\n\n3. power on iCESugar-pro, open the serial port to check the linux start up\n`$picocom -b 1000000 /dev/ttyACM0`\n\n## Boot Log\n```\n        __   _ __      _  __\n       / /  (_) /____ | |/_/\n      / /__/ / __/ -_)>  <\n     /____/_/\\__/\\__/_/|_|\n   Build your hardware, easily!\n\n (c) Copyright 2012-2020 Enjoy-Digital\n (c) Copyright 2007-2015 M-Labs\n\n BIOS built on Nov 11 2020 09:43:40\n BIOS CRC passed (9f19f473)\n\n Migen git sha1: cc6e76e\n LiteX git sha1: 275932f5\n\n--=============== SoC ==================--\nCPU:            VexRiscv_Linux @ 50MHz\nBUS:            WISHBONE 32-bit @ 4GiB\nCSR:            8-bit data\nROM:            64KiB\nSRAM:           8KiB\nL2:             8KiB\nSDRAM:          32768KiB 16-bit @ 50MT/s (CL-2 CWL-2)\n\n--========== Initialization ============--\nInitializing SDRAM @0x40000000...\nSwitching SDRAM to software control.\nSwitching SDRAM to hardware control.\nMemtest at 0x40000000 (2MiB)...\n  Write: 0x40000000-0x40200000 2MiB\n   Read: 0x40000000-0x40200000 2MiB\nMemtest OK\nMemspeed at 0x40000000 (2MiB)...\n  Write speed: 11MiB/s\n   Read speed: 10MiB/s\n\n--============== Boot ==================--\nBooting from serial...\nPress Q or ESC to abort boot completely.\nsL5DdSMmkekro\n             Timeout\nBooting from SDCard in SPI-Mode...\nBooting from boot.json...\nCopying Image to 0x40000000 (4545524 bytes)...\n[########################################]\nCopying rootfs.cpio to 0x40800000 (8029184 bytes)...\n[########################################]\nCopying rv32.dtb to 0x41000000 (1987 bytes)...\n[########################################]\nCopying emulator.bin to 0x41100000 (9600 bytes)...\n[########################################]\nExecuting booted program at 0x41100000\n\n--============= Liftoff! ===============--\nVexRiscv Machine Mode software built Mar 23 2020 16:55:03\n--========== Booting Linux =============--\n[    0.000000] No DTB passed to the kernel                                          \n[    0.000000] Linux version 5.0.13 (florent@lab) (gcc version 8.3.0 (Buildroot 2019.08-rc2-00011-gad9efda578)) #1 Thu Sep 12 14:20:26 CEST 2019\n[    0.000000] earlycon: sbi0 at I/O port 0x0 (options '')\n[    0.000000] printk: bootconsole [sbi0] enabled\n[    0.000000] Initial ramdisk at: 0x(ptrval) (8388608 bytes)\n[    0.000000] Zone ranges:\n[    0.000000]   Normal   [mem 0x0000000040000000-0x0000000041ffffff]\n[    0.000000] Movable zone start for each node\n[    0.000000] Early memory node ranges\n[    0.000000]   node   0: [mem 0x0000000040000000-0x0000000041ffffff]\n[    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x0000000041ffffff]\n[    0.000000] elf_hwcap is 0x1101\n[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 8128\n[    0.000000] Kernel command line: mem=32M@0x40000000 rootwait console=liteuart earlycon=sbi root=/dev/ram0 init=/sbin/init swiotlb=32\n[    0.000000] Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)\n[    0.000000] Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)\n[    0.000000] Sorting __ex_table...\n[    0.000000] Memory: 19812K/32768K available (3415K kernel code, 148K rwdata, 509K rodata, 140K init, 216K bss, 12956K reserved, 0K cma-reserved)\n[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1\n[    0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0\n[    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0xb8812736b, max_idle_ns: 440795202655 ns\n[    0.000422] sched_clock: 64 bits at 50MHz, resolution 20ns, wraps every 4398046511100ns\n[    0.004800] Console: colour dummy device 80x25\n[    0.007486] Calibrating delay loop (skipped), value calculated using timer frequency.. 100.00 BogoMIPS (lpj=200000)\n[    0.009456] pid_max: default: 32768 minimum: 301\n[    0.026679] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)\n[    0.028428] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)\n[    0.121644] devtmpfs: initialized\n[    0.189497] random: get_random_bytes called from setup_net+0x4c/0x188 with crng_init=0\n[    0.200282] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns\n[    0.202998] futex hash table entries: 256 (order: -1, 3072 bytes)\n[    0.220630] NET: Registered protocol family 16\n[    0.579278] clocksource: Switched to clocksource riscv_clocksource\n[    1.118845] NET: Registered protocol family 2\n[    1.149705] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes)\n[    1.152735] TCP established hash table entries: 1024 (order: 0, 4096 bytes)\n[    1.154585] TCP bind hash table entries: 1024 (order: 0, 4096 bytes)\n[    1.156926] TCP: Hash tables configured (established 1024 bind 1024)\n[    1.164153] UDP hash table entries: 256 (order: 0, 4096 bytes)\n[    1.165932] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)\n[    1.197310] Unpacking initramfs...\n[    5.478529] Initramfs unpacking failed: junk in compressed archive\n[    5.518894] workingset: timestamp_bits=30 max_order=13 bucket_order=0\n[    6.441722] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)\n[    6.443061] io scheduler mq-deadline registered\n[    6.444868] io scheduler kyber registered\n[    9.806243] f0001000.serial: ttyLXU0 at MMIO 0xf0001000 (irq = 0, base_baud = 0) is a liteuart\n[    9.809098] printk: console [liteuart0] enabled\n[    9.809098] printk: console [liteuart0] enabled\n[    9.810562] printk: bootconsole [sbi0] disabled\n[    9.810562] printk: bootconsole [sbi0] disabled\n[    9.863872] libphy: Fixed MDIO Bus: probed\n[    9.874843] i2c /dev entries driver\n[    9.993741] NET: Registered protocol family 10\n[   10.037459] Segment Routing with IPv6\n[   10.042318] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver\n[   10.141414] Freeing unused kernel memory: 140K\n[   10.142302] This architecture does not have kernel memory protection.\n[   10.144239] Run /init as init process\nmount: mounting tmpfs on /dev/shm failed: Invalid argument\nmount: mounting tmpfs on /tmp failed: Invalid argument\nmount: mounting tmpfs on /run failed: Invalid argument\nStarting syslogd: OK\nStarting klogd: OK\nRunning sysctl: OK\nInitializing random number generator... [   16.221885] random: dd: uninitialized urandom read (512 bytes read)\ndone.\nStarting network: OK\nStarting dropbear sshd: [   19.262912] random: dropbear: uninitialized urandom read (32 bytes read)\nOK\n\nWelcome to Buildroot\nbuildroot login: root\n                __   _\n               / /  (_)__  __ ____ __\n              / /__/ / _ \\/ // /\\ \\ /\n             /____/_/_//_/\\_,_//_\\_\\\n                   / _ \\/ _ \\\n   __   _ __      _\\___/_//_/ __             _\n  / /  (_) /____ | |/_/__| | / /____ __ ____(_)__ _____  __\n / /__/ / __/ -_)>  </___/ |/ / -_) \\ // __/ (_-</ __/ |/ /\n/____/_/\\__/\\__/_/|_|    |___/\\__/_\\_\\/_/ /_/___/\\__/|___/\n\n 32-bit VexRiscv CPU with MMU integrated in a LiteX SoC\n\nlogin[81]: root login on 'console'\nroot@buildroot:~# uname -a\nLinux buildroot 5.0.13 #1 Thu Sep 12 14:20:26 CEST 2019 riscv32 GNU/Linux\nroot@buildroot:~# cat /proc/cpuinfo\nprocessor       : 0\nhart            : 0\nisa             : rv32ima\nmmu             : sv32\nuarch           : spinalhdl,vexriscv\n\nroot@buildroot:~# cat /proc/meminfo\nMemTotal:          19952 kB\nMemFree:            7756 kB\nMemAvailable:       7208 kB\nBuffers:               0 kB\nCached:             9260 kB\nSwapCached:            0 kB\nActive:              380 kB\nInactive:              0 kB\nActive(anon):        380 kB\nInactive(anon):        0 kB\nActive(file):          0 kB\nInactive(file):        0 kB\nUnevictable:        9260 kB\nMlocked:               0 kB\nSwapTotal:             0 kB\nSwapFree:              0 kB\nDirty:                 0 kB\nWriteback:             0 kB\nAnonPages:           408 kB\nMapped:             2236 kB\nShmem:                 0 kB\nKReclaimable:        584 kB\nSlab:               2124 kB\nSReclaimable:        584 kB\nSUnreclaim:         1540 kB\nKernelStack:         176 kB\nPageTables:           60 kB\nNFS_Unstable:          0 kB\nBounce:                0 kB\nWritebackTmp:          0 kB\nCommitLimit:        9976 kB\nCommitted_AS:       1672 kB\nVmallocTotal:     524287 kB\nVmallocUsed:           0 kB\nVmallocChunk:          0 kB\nPercpu:               32 kB\nroot@buildroot:~#\n```\n## reference \n- linux-on-litex-vexriscv  \n[https://github.com/litex-hub/linux-on-litex-vexriscv](https://github.com/litex-hub/linux-on-litex-vexriscv)\n- linux-on-litex-vexriscv-prebuilt  \n[https://github.com/antmicro/linux-on-litex-vexriscv-prebuilt](https://github.com/antmicro/linux-on-litex-vexriscv-prebuilt)\n"
  },
  {
    "path": "linux/boot.json",
    "content": "{\n\t\"Image\":        \"0x40000000\",\n\t\"rootfs.cpio\":  \"0x40800000\",\n\t\"rv32.dtb\":     \"0x41000000\",\n\t\"emulator.bin\":  \"0x41100000\"\n}\n"
  },
  {
    "path": "schematic/README.md",
    "content": "## DDR-SODIMM-200P\n| Function | Top-Pin | Bot-Pin | Function |\n|----------|---------|---------|----------|\n|   GND    |    1    |    2    |   5V     |\n|   GND    |    3    |    4    |   5V     |\n|   GND    |    5    |    6    |   5V     |\n|   GND    |    7    |    8    |   5V     |\n|   GND    |    9    |    10   |   5V     |\n|   GND    |    11   |    12   |   5V     |\n|   NC     |    13   |    14   |   NC     |\n|   NC     |    15   |    16   |   NC     |\n|   NC     |    17   |    18   |   NC     |\n|   NC     |    19   |    20   |   NC     |\n|   NC     |    21   |    22   |   NC     |\n|   NC     |    23   |    24   |   NC     |\n|   NC     |    25   |    26   |   NC     |\n|   NC     |    27   |    28   |   NC     |\n|   NC     |    29   |    30   |   NC     |\n|   NC     |    31   |    32   |   NC     |\n|   NC     |    33   |    34   |   NC     |\n|   NC     |    35   |    36   |   NC     |\n|   NC     |    37   |    38   |   NC     |\n|   GND    |    39   |    40   |   GND    |\n|          |         |         |          |\n|          |         |         |          |\n|   A8     |    41   |    42   |   P11    |\n|   NC     |    43   |    44   |   P12    |\n|   NC     |    45   |    46   |   N12    |\n|   NC     |    47   |    48   |   P13    |\n|   B8     |    49   |    50   |   N13    |\n|   A7     |    51   |    52   |   P14    |\n|   NC     |    53   |    54   |   M12    |\n|   GND    |    55   |    56   |   GND    |\n|   B7     |    57   |    58   |   M13    |\n|   A6     |    59   |    60   |   L14    |\n|   B6     |    61   |    62   |   L13    |\n|   A5     |    63   |    64   |   K14    |\n|   B5     |    65   |    66   |   K13    |\n|   A4     |    67   |    68   |   J14    |\n|   B4     |    69   |    70   |   J13    |\n|   A3     |    71   |    72   |   H14    |\n|   B3     |    73   |    74   |   H13    |\n|   A2     |    75   |    76   |   G14    |\n|   B1     |    77   |    78   |   G13    |\n|   B2     |    79   |    80   |   F14    |\n|   C1     |    81   |    82   |   F13    |\n|   C2     |    83   |    84   |   E14    |\n|   D1     |    85   |    86   |   E13    |\n|   D3     |    87   |    88   |   E12    |\n|   E1     |    89   |    90   |   C13    |\n|   E2     |    91   |    92   |   D13    |\n|   F1     |    93   |    94   |   C12    |\n|   F2     |    95   |    96   |   D12    |\n|   G1     |    97   |    98   |   C11    |\n|   G2     |    99   |    100  |   D11    |\n|   H2     |    101  |    102  |   C10    |\n|   J1     |    103  |    104  |   D10    |\n|   GND    |    105  |    106  |   GND    |\n|   GND    |    107  |    108  |   GND    |\n|   J2     |    109  |    110  |   C9     |\n|   K1     |    111  |    112  |   D9     |\n|   K2     |    113  |    114  |   C8     |\n|   L1     |    115  |    116  |   D8     |\n|   L2     |    117  |    118  |   C7     |\n|   M1     |    119  |    120  |   D7     |\n|   M2     |    121  |    122  |   C6     |\n|   N1     |    123  |    124  |   D6     |\n|   N3     |    125  |    126  |   C5     |\n|   P1     |    127  |    128  |   D5     |\n|   P2     |    129  |    130  |   C4     |\n|   R1     |    131  |    132  |   D4     |\n|   R2     |    133  |    134  |   C3     |\n|   T2     |    135  |    136  |   E4     |\n|   R3     |    137  |    138  |   E3     |\n|   T3     |    139  |    140  |   F4     |\n|   R4     |    141  |    142  |   F3     |\n|   T4     |    143  |    144  |   G4     |\n|   R5     |    145  |    146  |   G3     |\n|   R6     |    147  |    148  |   H3     |\n|   T6     |    149  |    150  |   J4     |\n|   P7     |    151  |    152  |   J3     |\n|   R7     |    153  |    154  |   K4     |\n|   R8     |    155  |    156  |   K3     |\n|   GND    |    157  |    158  |   GND    |\n|   NC     |    159  |    160  |   NC     |\n|   NC     |    161  |    162  |   NC     |\n|   NC     |    163  |    164  |   NC     |\n|   NC     |    165  |    166  |   NC     |\n|   NC     |    167  |    168  |   NC     |\n|   NC     |    169  |    170  |   NC     |\n|   NC     |    171  |    172  |   NC     |\n|   NC     |    173  |    174  |   NC     |\n|   NC     |    175  |    176  |   NC     |\n|   NC     |    177  |    178  |   NC     |\n|   NC     |    179  |    180  |   NC     |\n|   NC     |    181  |    182  |   NC     |\n|   NC     |    183  |    184  |   NC     |\n|   NC     |    185  |    186  |   NC     |\n|   NC     |    187  |    188  |   NC     |\n|   NC     |    189  |    190  |   NC     |\n|   NC     |    191  |    192  |   NC     |\n|   NC     |    193  |    194  |   NC     |\n|   NC     |    195  |    196  |   NC     |\n|   NC     |    197  |    198  |   NC     |\n|   GND    |    199  |    200  |   GND    |\n\n## Ext-Board Pin map\nthe Ext-Board is origin designed for Colorlight i5 module, in [Colorlight-FPGA-Projects](https://github.com/wuxx/Colorlight-FPGA-Projects), there is a on-board DAPLink to do the flash work, the iCESugar-Pro doesn't need it, so the Ext-Board actually is a \"real\" breakout board.  \n![iCESugar-pro-pinmap](https://github.com/wuxx/icesugar-pro/blob/master/doc/iCESugar-pro-pinmap.png)\n\n### Notes\nPlease note that some pins of P5 are shared with Ext-Board DAPLink, include {D12, C11, D13, C12, E12, C13, E14, E13}, if you have enough pins, just don't use these pins. if you want to use these pins, one simple way is force the Ext-Board DAPLink run into bootloader. just create a file named `START_BL.ACT` in root directory of DAPLink. for example, type `$cd /media/pi/DAPLink && touch START_BL.ACT`\n"
  },
  {
    "path": "src/blink/Makefile",
    "content": "TARGET=blink\nTOP=blink\n\nOBJS+=blink.v rst_gen.v\n\nall: ${TARGET}.bit\n\n$(TARGET).json: $(OBJS)\n\tyosys -p \"synth_ecp5 -json $@\" $(OBJS)\n\n$(TARGET)_out.config: $(TARGET).json\n\tnextpnr-ecp5 --25k --package CABGA256 --speed 6 --json $< --textcfg $@ --lpf $(TARGET).lpf --freq 65\n\n$(TARGET).bit: $(TARGET)_out.config\n\tecppack --svf ${TARGET}.svf $< $@\n\n${TARGET}.svf : ${TARGET}.bit\n\nprog: ${TARGET}.svf\n\topenFPGALoader -c digilent_hs2 $(TARGET).bit\n\nclean:\n\trm -f *.svf *.bit *.config *.ys\n\n.PHONY: prog clean\n"
  },
  {
    "path": "src/blink/blink.json",
    "content": "{\n  \"creator\": \"Yosys 0.9+3672 (git sha1 924f1713, gcc 8.3.0-6+rpi1 -fPIC -Os)\",\n  \"modules\": {\n    \"\\\\$__ABC9_LUT5\": {\n      \"attributes\": {\n        \"blackbox\": \"00000000000000000000000000000001\",\n        \"abc9_lut\": \"00000000000000000000000000000010\",\n        \"cells_not_processed\": \"00000000000000000000000000000001\",\n        \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_sim.v:22.1-30.10\"\n      },\n      \"ports\": {\n        \"M0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 2 ]\n        },\n        \"D\": {\n          \"direction\": \"input\",\n          \"bits\": [ 3 ]\n        },\n        \"C\": {\n          \"direction\": \"input\",\n          \"bits\": [ 4 ]\n        },\n        \"B\": {\n          \"direction\": \"input\",\n          \"bits\": [ 5 ]\n        },\n        \"A\": {\n          \"direction\": \"input\",\n          \"bits\": [ 6 ]\n        },\n        \"Z\": {\n          \"direction\": \"output\",\n          \"bits\": [ 7 ]\n        }\n      },\n      \"cells\": {\n        \"$specify$15\": {\n          \"hide_name\": 1,\n          \"type\": \"$specify2\",\n          \"parameters\": {\n            \"DST_WIDTH\": \"00000000000000000000000000000001\",\n            \"FULL\": \"0\",\n            \"SRC_DST_PEN\": \"0\",\n            \"SRC_DST_POL\": \"0\",\n            \"SRC_WIDTH\": \"00000000000000000000000000000001\",\n            \"T_FALL_MAX\": \"00000000000000000000000010010111\",\n            \"T_FALL_MIN\": \"00000000000000000000000010010111\",\n            \"T_FALL_TYP\": \"00000000000000000000000010010111\",\n            \"T_RISE_MAX\": \"00000000000000000000000010010111\",\n            \"T_RISE_MIN\": \"00000000000000000000000010010111\",\n            \"T_RISE_TYP\": \"00000000000000000000000010010111\"\n          },\n          \"attributes\": {\n            \"module_not_derived\": \"00000000000000000000000000000001\",\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_sim.v:24.9-24.25\"\n          },\n          \"port_directions\": {\n            \"DST\": \"input\",\n            \"EN\": \"input\",\n            \"SRC\": \"input\"\n          },\n          \"connections\": {\n            \"DST\": [ 7 ],\n            \"EN\": [ \"1\" ],\n            \"SRC\": [ 2 ]\n          }\n        },\n        \"$specify$16\": {\n          \"hide_name\": 1,\n          \"type\": \"$specify2\",\n          \"parameters\": {\n            \"DST_WIDTH\": \"00000000000000000000000000000001\",\n            \"FULL\": \"0\",\n            \"SRC_DST_PEN\": \"0\",\n            \"SRC_DST_POL\": \"0\",\n            \"SRC_WIDTH\": \"00000000000000000000000000000001\",\n            \"T_FALL_MAX\": \"00000000000000000000000011101111\",\n            \"T_FALL_MIN\": \"00000000000000000000000011101111\",\n            \"T_FALL_TYP\": \"00000000000000000000000011101111\",\n            \"T_RISE_MAX\": \"00000000000000000000000011101111\",\n            \"T_RISE_MIN\": \"00000000000000000000000011101111\",\n            \"T_RISE_TYP\": \"00000000000000000000000011101111\"\n          },\n          \"attributes\": {\n            \"module_not_derived\": \"00000000000000000000000000000001\",\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_sim.v:25.9-25.24\"\n          },\n          \"port_directions\": {\n            \"DST\": \"input\",\n            \"EN\": \"input\",\n            \"SRC\": \"input\"\n          },\n          \"connections\": {\n            \"DST\": [ 7 ],\n            \"EN\": [ \"1\" ],\n            \"SRC\": [ 3 ]\n          }\n        },\n        \"$specify$17\": {\n          \"hide_name\": 1,\n          \"type\": \"$specify2\",\n          \"parameters\": {\n            \"DST_WIDTH\": \"00000000000000000000000000000001\",\n            \"FULL\": \"0\",\n            \"SRC_DST_PEN\": \"0\",\n            \"SRC_DST_POL\": \"0\",\n            \"SRC_WIDTH\": \"00000000000000000000000000000001\",\n            \"T_FALL_MAX\": \"00000000000000000000000101110101\",\n            \"T_FALL_MIN\": \"00000000000000000000000101110101\",\n            \"T_FALL_TYP\": \"00000000000000000000000101110101\",\n            \"T_RISE_MAX\": \"00000000000000000000000101110101\",\n            \"T_RISE_MIN\": \"00000000000000000000000101110101\",\n            \"T_RISE_TYP\": \"00000000000000000000000101110101\"\n          },\n          \"attributes\": {\n            \"module_not_derived\": \"00000000000000000000000000000001\",\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_sim.v:26.9-26.24\"\n          },\n          \"port_directions\": {\n            \"DST\": \"input\",\n            \"EN\": \"input\",\n            \"SRC\": \"input\"\n          },\n          \"connections\": {\n            \"DST\": [ 7 ],\n            \"EN\": [ \"1\" ],\n            \"SRC\": [ 4 ]\n          }\n        },\n        \"$specify$18\": {\n          \"hide_name\": 1,\n          \"type\": \"$specify2\",\n          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  \"CH0_MATCH_2_ENABLE\": \"0b0\",\n        \"CH0_MATCH_4_ENABLE\": \"0b0\",\n        \"CH0_MIN_IPG_CNT\": \"0b00\",\n        \"CH0_PCIE_EI_EN\": \"0b0\",\n        \"CH0_PCIE_MODE\": \"0b0\",\n        \"CH0_PCS_DET_TIME_SEL\": \"0b00\",\n        \"CH0_PDEN_SEL\": \"0b0\",\n        \"CH0_PRBS_ENABLE\": \"0b0\",\n        \"CH0_PRBS_LOCK\": \"0b0\",\n        \"CH0_PRBS_SELECTION\": \"0b0\",\n        \"CH0_PROTOCOL\": \"8B10B\",\n        \"CH0_RATE_MODE_RX\": \"0b0\",\n        \"CH0_RATE_MODE_TX\": \"0b0\",\n        \"CH0_RCV_DCC_EN\": \"0b0\",\n        \"CH0_REG_BAND_OFFSET\": \"0b0000\",\n        \"CH0_REG_BAND_SEL\": \"0b000000\",\n        \"CH0_REG_IDAC_EN\": \"0b0\",\n        \"CH0_REG_IDAC_SEL\": \"0b0000000000\",\n        \"CH0_REQ_EN\": \"0b0\",\n        \"CH0_REQ_LVL_SET\": \"0b00\",\n        \"CH0_RIO_MODE\": \"0b0\",\n        \"CH0_RLOS_SEL\": \"0b0\",\n        \"CH0_RPWDNB\": \"0b0\",\n        \"CH0_RTERM_RX\": \"0b00000\",\n        \"CH0_RTERM_TX\": \"0b00000\",\n        \"CH0_RXIN_CM\": \"0b00\",\n        \"CH0_RXTERM_CM\": \"0b00\",\n        \"CH0_RX_DCO_CK_DIV\": \"0b000\",\n        \"CH0_RX_DIV11_SEL\": \"0b0\",\n        \"CH0_RX_GEAR_BYPASS\": \"0b0\",\n        \"CH0_RX_GEAR_MODE\": \"0b0\",\n        \"CH0_RX_LOS_CEQ\": \"0b00\",\n        \"CH0_RX_LOS_EN\": \"0b0\",\n        \"CH0_RX_LOS_HYST_EN\": \"0b0\",\n        \"CH0_RX_LOS_LVL\": \"0b000\",\n        \"CH0_RX_RATE_SEL\": \"0b0000\",\n        \"CH0_RX_SB_BYPASS\": \"0b0\",\n        \"CH0_SB_BYPASS\": \"0b0\",\n        \"CH0_SEL_SD_RX_CLK\": \"0b0\",\n        \"CH0_TDRV_DAT_SEL\": \"0b00\",\n        \"CH0_TDRV_POST_EN\": \"0b0\",\n        \"CH0_TDRV_PRE_EN\": \"0b0\",\n        \"CH0_TDRV_SLICE0_CUR\": \"0b000\",\n        \"CH0_TDRV_SLICE0_SEL\": \"0b00\",\n        \"CH0_TDRV_SLICE1_CUR\": \"0b000\",\n        \"CH0_TDRV_SLICE1_SEL\": \"0b00\",\n        \"CH0_TDRV_SLICE2_CUR\": \"0b00\",\n        \"CH0_TDRV_SLICE2_SEL\": \"0b00\",\n        \"CH0_TDRV_SLICE3_CUR\": \"0b00\",\n        \"CH0_TDRV_SLICE3_SEL\": \"0b00\",\n        \"CH0_TDRV_SLICE4_CUR\": \"0b00\",\n        \"CH0_TDRV_SLICE4_SEL\": \"0b00\",\n        \"CH0_TDRV_SLICE5_CUR\": \"0b00\",\n        \"CH0_TDRV_SLICE5_SEL\": \"0b00\",\n        \"CH0_TPWDNB\": \"0b0\",\n        \"CH0_TXAMPLITUDE\": \"0d1300\",\n        \"CH0_TXDEPOST\": \"DISABLED\",\n        \"CH0_TXDEPRE\": \"DISABLED\",\n        \"CH0_TX_CM_SEL\": \"0b00\",\n        \"CH0_TX_DIV11_SEL\": \"0b0\",\n        \"CH0_TX_GEAR_BYPASS\": \"0b0\",\n        \"CH0_TX_GEAR_MODE\": \"0b0\",\n        \"CH0_TX_POST_SIGN\": \"0b0\",\n        \"CH0_TX_PRE_SIGN\": \"0b0\",\n        \"CH0_UC_MODE\": \"0b0\",\n        \"CH0_UDF_COMMA_A\": \"0b0000000000\",\n        \"CH0_UDF_COMMA_B\": \"0b0000000000\",\n        \"CH0_UDF_COMMA_MASK\": \"0b0000000000\",\n        \"CH0_WA_BYPASS\": \"0b0\",\n        \"CH0_WA_MODE\": \"0b0\",\n        \"CH1_AUTO_CALIB_EN\": \"0b0\",\n        \"CH1_AUTO_FACQ_EN\": \"0b0\",\n        \"CH1_BAND_THRESHOLD\": \"0b000000\",\n        \"CH1_CALIB_CK_MODE\": \"0b0\",\n        \"CH1_CC_MATCH_1\": \"0b0000000000\",\n        \"CH1_CC_MATCH_2\": \"0b0000000000\",\n        \"CH1_CC_MATCH_3\": \"0b0000000000\",\n        \"CH1_CC_MATCH_4\": \"0b0000000000\",\n        \"CH1_CDR_CNT4SEL\": \"0b00\",\n        \"CH1_CDR_CNT8SEL\": \"0b00\",\n        \"CH1_CDR_MAX_RATE\": \"2.5\",\n        \"CH1_CTC_BYPASS\": \"0b0\",\n        \"CH1_DCOATDCFG\": \"0b00\",\n        \"CH1_DCOATDDLY\": \"0b00\",\n        \"CH1_DCOBYPSATD\": \"0b0\",\n        \"CH1_DCOCALDIV\": \"0b000\",\n        \"CH1_DCOCTLGI\": \"0b000\",\n        \"CH1_DCODISBDAVOID\": \"0b0\",\n        \"CH1_DCOFLTDAC\": \"0b00\",\n        \"CH1_DCOFTNRG\": \"0b000\",\n        \"CH1_DCOIOSTUNE\": \"0b000\",\n        \"CH1_DCOITUNE\": \"0b00\",\n        \"CH1_DCOITUNE4LSB\": \"0b000\",\n        \"CH1_DCOIUPDNX2\": \"0b0\",\n        \"CH1_DCONUOFLSB\": \"0b000\",\n        \"CH1_DCOSCALEI\": \"0b00\",\n        \"CH1_DCOSTARTVAL\": \"0b000\",\n        \"CH1_DCOSTEP\": \"0b00\",\n        \"CH1_DEC_BYPASS\": \"0b0\",\n        \"CH1_ENABLE_CG_ALIGN\": \"0b0\",\n        \"CH1_ENC_BYPASS\": \"0b0\",\n        \"CH1_FF_RX_F_CLK_DIS\": \"0b0\",\n        \"CH1_FF_RX_H_CLK_EN\": \"0b0\",\n        \"CH1_FF_TX_F_CLK_DIS\": \"0b0\",\n        \"CH1_FF_TX_H_CLK_EN\": \"0b0\",\n        \"CH1_GE_AN_ENABLE\": \"0b0\",\n        \"CH1_INVERT_RX\": \"0b0\",\n        \"CH1_INVERT_TX\": \"0b0\",\n        \"CH1_LDR_CORE2TX_SEL\": \"0b0\",\n        \"CH1_LDR_RX2CORE_SEL\": \"0b0\",\n        \"CH1_LEQ_OFFSET_SEL\": \"0b0\",\n        \"CH1_LEQ_OFFSET_TRIM\": \"0b000\",\n        \"CH1_LSM_DISABLE\": \"0b0\",\n        \"CH1_MATCH_2_ENABLE\": \"0b0\",\n        \"CH1_MATCH_4_ENABLE\": \"0b0\",\n        \"CH1_MIN_IPG_CNT\": \"0b00\",\n        \"CH1_PCIE_EI_EN\": \"0b0\",\n        \"CH1_PCIE_MODE\": \"0b0\",\n        \"CH1_PCS_DET_TIME_SEL\": \"0b00\",\n        \"CH1_PDEN_SEL\": \"0b0\",\n        \"CH1_PRBS_ENABLE\": \"0b0\",\n        \"CH1_PRBS_LOCK\": \"0b0\",\n        \"CH1_PRBS_SELECTION\": \"0b0\",\n        \"CH1_PROTOCOL\": \"8B10B\",\n        \"CH1_RATE_MODE_RX\": \"0b0\",\n        \"CH1_RATE_MODE_TX\": \"0b0\",\n        \"CH1_RCV_DCC_EN\": \"0b0\",\n        \"CH1_REG_BAND_OFFSET\": \"0b0000\",\n        \"CH1_REG_BAND_SEL\": \"0b000000\",\n        \"CH1_REG_IDAC_EN\": \"0b0\",\n        \"CH1_REG_IDAC_SEL\": \"0b0000000000\",\n        \"CH1_REQ_EN\": \"0b0\",\n        \"CH1_REQ_LVL_SET\": \"0b00\",\n        \"CH1_RIO_MODE\": \"0b0\",\n        \"CH1_RLOS_SEL\": \"0b0\",\n        \"CH1_RPWDNB\": \"0b0\",\n        \"CH1_RTERM_RX\": \"0b00000\",\n        \"CH1_RTERM_TX\": \"0b00000\",\n        \"CH1_RXIN_CM\": \"0b00\",\n        \"CH1_RXTERM_CM\": \"0b00\",\n        \"CH1_RX_DCO_CK_DIV\": \"0b000\",\n        \"CH1_RX_DIV11_SEL\": \"0b0\",\n        \"CH1_RX_GEAR_BYPASS\": \"0b0\",\n        \"CH1_RX_GEAR_MODE\": \"0b0\",\n        \"CH1_RX_LOS_CEQ\": \"0b00\",\n        \"CH1_RX_LOS_EN\": \"0b0\",\n        \"CH1_RX_LOS_HYST_EN\": \"0b0\",\n        \"CH1_RX_LOS_LVL\": \"0b000\",\n        \"CH1_RX_RATE_SEL\": \"0b0000\",\n        \"CH1_RX_SB_BYPASS\": \"0b0\",\n        \"CH1_SB_BYPASS\": \"0b0\",\n        \"CH1_SEL_SD_RX_CLK\": \"0b0\",\n        \"CH1_TDRV_DAT_SEL\": \"0b00\",\n        \"CH1_TDRV_POST_EN\": \"0b0\",\n        \"CH1_TDRV_PRE_EN\": \"0b0\",\n        \"CH1_TDRV_SLICE0_CUR\": \"0b000\",\n        \"CH1_TDRV_SLICE0_SEL\": \"0b00\",\n        \"CH1_TDRV_SLICE1_CUR\": \"0b000\",\n        \"CH1_TDRV_SLICE1_SEL\": \"0b00\",\n        \"CH1_TDRV_SLICE2_CUR\": \"0b00\",\n        \"CH1_TDRV_SLICE2_SEL\": \"0b00\",\n        \"CH1_TDRV_SLICE3_CUR\": \"0b00\",\n        \"CH1_TDRV_SLICE3_SEL\": \"0b00\",\n        \"CH1_TDRV_SLICE4_CUR\": \"0b00\",\n        \"CH1_TDRV_SLICE4_SEL\": \"0b00\",\n        \"CH1_TDRV_SLICE5_CUR\": \"0b00\",\n        \"CH1_TDRV_SLICE5_SEL\": \"0b00\",\n        \"CH1_TPWDNB\": \"0b0\",\n        \"CH1_TXAMPLITUDE\": \"0d1300\",\n        \"CH1_TXDEPOST\": \"DISABLED\",\n        \"CH1_TXDEPRE\": \"DISABLED\",\n        \"CH1_TX_CM_SEL\": \"0b00\",\n        \"CH1_TX_DIV11_SEL\": \"0b0\",\n        \"CH1_TX_GEAR_BYPASS\": \"0b0\",\n        \"CH1_TX_GEAR_MODE\": \"0b0\",\n        \"CH1_TX_POST_SIGN\": \"0b0\",\n        \"CH1_TX_PRE_SIGN\": \"0b0\",\n        \"CH1_UC_MODE\": \"0b0\",\n        \"CH1_UDF_COMMA_A\": \"0b0000000000\",\n        \"CH1_UDF_COMMA_B\": \"0b0000000000\",\n        \"CH1_UDF_COMMA_MASK\": \"0b0000000000\",\n        \"CH1_WA_BYPASS\": \"0b0\",\n        \"CH1_WA_MODE\": \"0b0\",\n        \"D_BITCLK_FROM_ND_EN\": \"0b0\",\n        \"D_BITCLK_LOCAL_EN\": \"0b0\",\n        \"D_BITCLK_ND_EN\": \"0b0\",\n        \"D_BUS8BIT_SEL\": \"0b0\",\n        \"D_CDR_LOL_SET\": \"0b00\",\n        \"D_CMUSETBIASI\": \"0b00\",\n        \"D_CMUSETI4CPP\": \"0b0000\",\n        \"D_CMUSETI4CPZ\": \"0b0000\",\n        \"D_CMUSETI4VCO\": \"0b00\",\n        \"D_CMUSETICP4P\": \"0b00\",\n        \"D_CMUSETICP4Z\": \"0b000\",\n        \"D_CMUSETINITVCT\": \"0b00\",\n        \"D_CMUSETISCL4VCO\": \"0b000\",\n        \"D_CMUSETP1GM\": \"0b000\",\n        \"D_CMUSETP2AGM\": \"0b000\",\n        \"D_CMUSETZGM\": \"0b000\",\n        \"D_DCO_CALIB_TIME_SEL\": \"0b00\",\n        \"D_HIGH_MARK\": \"0b0000\",\n        \"D_IB_PWDNB\": \"0b0\",\n        \"D_ISETLOS\": \"0b00000000\",\n        \"D_LOW_MARK\": \"0b0000\",\n        \"D_MACROPDB\": \"0b0\",\n        \"D_PD_ISET\": \"0b00\",\n        \"D_PLL_LOL_SET\": \"0b00\",\n        \"D_REFCK_MODE\": \"0b000\",\n        \"D_REQ_ISET\": \"0b000\",\n        \"D_RG_EN\": \"0b0\",\n        \"D_RG_SET\": \"0b00\",\n        \"D_RX_MAX_RATE\": \"2.5\",\n        \"D_SETICONST_AUX\": \"0b00\",\n        \"D_SETICONST_CH\": \"0b00\",\n        \"D_SETIRPOLY_AUX\": \"0b00\",\n        \"D_SETIRPOLY_CH\": \"0b00\",\n        \"D_SETPLLRC\": \"0b000000\",\n        \"D_SYNC_LOCAL_EN\": \"0b0\",\n        \"D_SYNC_ND_EN\": \"0b0\",\n        \"D_TXPLL_PWDNB\": \"0b0\",\n        \"D_TX_MAX_RATE\": \"2.5\",\n        \"D_TX_VCO_CK_DIV\": \"0b000\",\n        \"D_XGE_MODE\": \"0b0\"\n      },\n      \"ports\": {\n        \"CH0_HDINP\": {\n          \"direction\": \"input\",\n          \"bits\": [ 2 ]\n        },\n        \"CH1_HDINP\": {\n          \"direction\": \"input\",\n          \"bits\": [ 3 ]\n        },\n        \"CH0_HDINN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 4 ]\n        },\n        \"CH1_HDINN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 5 ]\n        },\n        \"D_TXBIT_CLKP_FROM_ND\": {\n          \"direction\": \"input\",\n          \"bits\": [ 6 ]\n        },\n        \"D_TXBIT_CLKN_FROM_ND\": {\n          \"direction\": \"input\",\n          \"bits\": [ 7 ]\n        },\n        \"D_SYNC_ND\": {\n          \"direction\": \"input\",\n          \"bits\": [ 8 ]\n        },\n        \"D_TXPLL_LOL_FROM_ND\": {\n          \"direction\": \"input\",\n          \"bits\": [ 9 ]\n        },\n        \"CH0_RX_REFCLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 10 ]\n        },\n        \"CH1_RX_REFCLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 11 ]\n        },\n        \"CH0_FF_RXI_CLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 12 ]\n        },\n        \"CH1_FF_RXI_CLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 13 ]\n        },\n        \"CH0_FF_TXI_CLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 14 ]\n        },\n        \"CH1_FF_TXI_CLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 15 ]\n        },\n        \"CH0_FF_EBRD_CLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 16 ]\n        },\n        \"CH1_FF_EBRD_CLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 17 ]\n        },\n        \"CH0_FF_TX_D_0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 18 ]\n        },\n        \"CH1_FF_TX_D_0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 19 ]\n        },\n        \"CH0_FF_TX_D_1\": {\n          \"direction\": \"input\",\n          \"bits\": [ 20 ]\n        },\n        \"CH1_FF_TX_D_1\": {\n          \"direction\": \"input\",\n          \"bits\": [ 21 ]\n        },\n        \"CH0_FF_TX_D_2\": {\n          \"direction\": \"input\",\n          \"bits\": [ 22 ]\n        },\n        \"CH1_FF_TX_D_2\": {\n          \"direction\": \"input\",\n          \"bits\": [ 23 ]\n        },\n        \"CH0_FF_TX_D_3\": {\n          \"direction\": \"input\",\n          \"bits\": [ 24 ]\n        },\n        \"CH1_FF_TX_D_3\": {\n          \"direction\": \"input\",\n          \"bits\": [ 25 ]\n        },\n        \"CH0_FF_TX_D_4\": {\n          \"direction\": \"input\",\n          \"bits\": [ 26 ]\n        },\n        \"CH1_FF_TX_D_4\": {\n          \"direction\": \"input\",\n          \"bits\": [ 27 ]\n        },\n        \"CH0_FF_TX_D_5\": {\n          \"direction\": \"input\",\n          \"bits\": [ 28 ]\n        },\n        \"CH1_FF_TX_D_5\": {\n          \"direction\": \"input\",\n          \"bits\": [ 29 ]\n        },\n        \"CH0_FF_TX_D_6\": {\n          \"direction\": \"input\",\n          \"bits\": [ 30 ]\n        },\n        \"CH1_FF_TX_D_6\": {\n          \"direction\": \"input\",\n          \"bits\": [ 31 ]\n        },\n        \"CH0_FF_TX_D_7\": {\n          \"direction\": \"input\",\n          \"bits\": [ 32 ]\n        },\n        \"CH1_FF_TX_D_7\": {\n          \"direction\": \"input\",\n          \"bits\": [ 33 ]\n        },\n        \"CH0_FF_TX_D_8\": {\n          \"direction\": \"input\",\n          \"bits\": [ 34 ]\n        },\n        \"CH1_FF_TX_D_8\": {\n          \"direction\": \"input\",\n          \"bits\": [ 35 ]\n        },\n        \"CH0_FF_TX_D_9\": {\n          \"direction\": \"input\",\n          \"bits\": [ 36 ]\n        },\n        \"CH1_FF_TX_D_9\": {\n          \"direction\": \"input\",\n          \"bits\": [ 37 ]\n        },\n        \"CH0_FF_TX_D_10\": {\n          \"direction\": \"input\",\n          \"bits\": [ 38 ]\n        },\n        \"CH1_FF_TX_D_10\": {\n          \"direction\": \"input\",\n          \"bits\": [ 39 ]\n        },\n        \"CH0_FF_TX_D_11\": {\n          \"direction\": \"input\",\n          \"bits\": [ 40 ]\n        },\n        \"CH1_FF_TX_D_11\": {\n          \"direction\": \"input\",\n          \"bits\": [ 41 ]\n        },\n        \"CH0_FF_TX_D_12\": {\n          \"direction\": \"input\",\n          \"bits\": [ 42 ]\n        },\n        \"CH1_FF_TX_D_12\": {\n          \"direction\": \"input\",\n          \"bits\": [ 43 ]\n        },\n        \"CH0_FF_TX_D_13\": {\n          \"direction\": \"input\",\n          \"bits\": [ 44 ]\n        },\n        \"CH1_FF_TX_D_13\": {\n          \"direction\": \"input\",\n          \"bits\": [ 45 ]\n        },\n        \"CH0_FF_TX_D_14\": {\n          \"direction\": \"input\",\n          \"bits\": [ 46 ]\n        },\n        \"CH1_FF_TX_D_14\": {\n          \"direction\": \"input\",\n          \"bits\": [ 47 ]\n        },\n        \"CH0_FF_TX_D_15\": {\n          \"direction\": \"input\",\n          \"bits\": [ 48 ]\n        },\n        \"CH1_FF_TX_D_15\": {\n          \"direction\": \"input\",\n          \"bits\": [ 49 ]\n        },\n        \"CH0_FF_TX_D_16\": {\n          \"direction\": \"input\",\n          \"bits\": [ 50 ]\n        },\n        \"CH1_FF_TX_D_16\": {\n          \"direction\": \"input\",\n          \"bits\": [ 51 ]\n        },\n        \"CH0_FF_TX_D_17\": {\n          \"direction\": \"input\",\n          \"bits\": [ 52 ]\n        },\n        \"CH1_FF_TX_D_17\": {\n          \"direction\": \"input\",\n          \"bits\": [ 53 ]\n        },\n        \"CH0_FF_TX_D_18\": {\n          \"direction\": \"input\",\n          \"bits\": [ 54 ]\n        },\n        \"CH1_FF_TX_D_18\": {\n          \"direction\": \"input\",\n          \"bits\": [ 55 ]\n        },\n        \"CH0_FF_TX_D_19\": {\n          \"direction\": \"input\",\n          \"bits\": [ 56 ]\n        },\n        \"CH1_FF_TX_D_19\": {\n          \"direction\": \"input\",\n          \"bits\": [ 57 ]\n        },\n        \"CH0_FF_TX_D_20\": {\n          \"direction\": \"input\",\n          \"bits\": [ 58 ]\n        },\n        \"CH1_FF_TX_D_20\": {\n          \"direction\": \"input\",\n          \"bits\": [ 59 ]\n        },\n        \"CH0_FF_TX_D_21\": {\n          \"direction\": \"input\",\n          \"bits\": [ 60 ]\n        },\n        \"CH1_FF_TX_D_21\": {\n          \"direction\": \"input\",\n          \"bits\": [ 61 ]\n        },\n        \"CH0_FF_TX_D_22\": {\n          \"direction\": \"input\",\n          \"bits\": [ 62 ]\n        },\n        \"CH1_FF_TX_D_22\": {\n          \"direction\": \"input\",\n          \"bits\": [ 63 ]\n        },\n        \"CH0_FF_TX_D_23\": {\n          \"direction\": \"input\",\n          \"bits\": [ 64 ]\n        },\n        \"CH1_FF_TX_D_23\": {\n          \"direction\": \"input\",\n          \"bits\": [ 65 ]\n        },\n        \"CH0_FFC_EI_EN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 66 ]\n        },\n        \"CH1_FFC_EI_EN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 67 ]\n        },\n        \"CH0_FFC_PCIE_DET_EN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 68 ]\n        },\n        \"CH1_FFC_PCIE_DET_EN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 69 ]\n        },\n        \"CH0_FFC_PCIE_CT\": {\n          \"direction\": \"input\",\n          \"bits\": [ 70 ]\n        },\n        \"CH1_FFC_PCIE_CT\": {\n          \"direction\": \"input\",\n          \"bits\": [ 71 ]\n        },\n        \"CH0_FFC_SB_INV_RX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 72 ]\n        },\n        \"CH1_FFC_SB_INV_RX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 73 ]\n        },\n        \"CH0_FFC_ENABLE_CGALIGN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 74 ]\n        },\n        \"CH1_FFC_ENABLE_CGALIGN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 75 ]\n        },\n        \"CH0_FFC_SIGNAL_DETECT\": {\n          \"direction\": \"input\",\n          \"bits\": [ 76 ]\n        },\n        \"CH1_FFC_SIGNAL_DETECT\": {\n          \"direction\": \"input\",\n          \"bits\": [ 77 ]\n        },\n        \"CH0_FFC_FB_LOOPBACK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 78 ]\n        },\n        \"CH1_FFC_FB_LOOPBACK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 79 ]\n        },\n        \"CH0_FFC_SB_PFIFO_LP\": {\n          \"direction\": \"input\",\n          \"bits\": [ 80 ]\n        },\n        \"CH1_FFC_SB_PFIFO_LP\": {\n          \"direction\": \"input\",\n          \"bits\": [ 81 ]\n        },\n        \"CH0_FFC_PFIFO_CLR\": {\n          \"direction\": \"input\",\n          \"bits\": [ 82 ]\n        },\n        \"CH1_FFC_PFIFO_CLR\": {\n          \"direction\": \"input\",\n          \"bits\": [ 83 ]\n        },\n        \"CH0_FFC_RATE_MODE_RX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 84 ]\n        },\n        \"CH1_FFC_RATE_MODE_RX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 85 ]\n        },\n        \"CH0_FFC_RATE_MODE_TX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 86 ]\n        },\n        \"CH1_FFC_RATE_MODE_TX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 87 ]\n        },\n        \"CH0_FFC_DIV11_MODE_RX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 88 ]\n        },\n        \"CH1_FFC_DIV11_MODE_RX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 89 ]\n        },\n        \"CH0_FFC_RX_GEAR_MODE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 90 ]\n        },\n        \"CH1_FFC_RX_GEAR_MODE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 91 ]\n        },\n        \"CH0_FFC_TX_GEAR_MODE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 92 ]\n        },\n        \"CH1_FFC_TX_GEAR_MODE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 93 ]\n        },\n        \"CH0_FFC_DIV11_MODE_TX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 94 ]\n        },\n        \"CH1_FFC_DIV11_MODE_TX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 95 ]\n        },\n        \"CH0_FFC_LDR_CORE2TX_EN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 96 ]\n        },\n        \"CH1_FFC_LDR_CORE2TX_EN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 97 ]\n        },\n        \"CH0_FFC_LANE_TX_RST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 98 ]\n        },\n        \"CH1_FFC_LANE_TX_RST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 99 ]\n        },\n        \"CH0_FFC_LANE_RX_RST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 100 ]\n        },\n        \"CH1_FFC_LANE_RX_RST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 101 ]\n        },\n        \"CH0_FFC_RRST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 102 ]\n        },\n        \"CH1_FFC_RRST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 103 ]\n        },\n        \"CH0_FFC_TXPWDNB\": {\n          \"direction\": \"input\",\n          \"bits\": [ 104 ]\n        },\n        \"CH1_FFC_TXPWDNB\": {\n          \"direction\": \"input\",\n          \"bits\": [ 105 ]\n        },\n        \"CH0_FFC_RXPWDNB\": {\n          \"direction\": \"input\",\n          \"bits\": [ 106 ]\n        },\n        \"CH1_FFC_RXPWDNB\": {\n          \"direction\": \"input\",\n          \"bits\": [ 107 ]\n        },\n        \"CH0_LDR_CORE2TX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 108 ]\n        },\n        \"CH1_LDR_CORE2TX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 109 ]\n        },\n        \"D_SCIWDATA0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 110 ]\n        },\n        \"D_SCIWDATA1\": {\n          \"direction\": \"input\",\n          \"bits\": [ 111 ]\n        },\n        \"D_SCIWDATA2\": {\n          \"direction\": \"input\",\n          \"bits\": [ 112 ]\n        },\n        \"D_SCIWDATA3\": {\n          \"direction\": \"input\",\n          \"bits\": [ 113 ]\n        },\n        \"D_SCIWDATA4\": {\n          \"direction\": \"input\",\n          \"bits\": [ 114 ]\n        },\n        \"D_SCIWDATA5\": {\n          \"direction\": \"input\",\n          \"bits\": [ 115 ]\n        },\n        \"D_SCIWDATA6\": {\n          \"direction\": \"input\",\n          \"bits\": [ 116 ]\n        },\n        \"D_SCIWDATA7\": {\n          \"direction\": \"input\",\n          \"bits\": [ 117 ]\n        },\n        \"D_SCIADDR0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 118 ]\n        },\n        \"D_SCIADDR1\": {\n          \"direction\": \"input\",\n          \"bits\": [ 119 ]\n        },\n        \"D_SCIADDR2\": {\n          \"direction\": \"input\",\n          \"bits\": [ 120 ]\n        },\n        \"D_SCIADDR3\": {\n          \"direction\": \"input\",\n          \"bits\": [ 121 ]\n        },\n        \"D_SCIADDR4\": {\n          \"direction\": \"input\",\n          \"bits\": [ 122 ]\n        },\n        \"D_SCIADDR5\": {\n          \"direction\": \"input\",\n          \"bits\": [ 123 ]\n        },\n        \"D_SCIENAUX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 124 ]\n        },\n        \"D_SCISELAUX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 125 ]\n        },\n        \"CH0_SCIEN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 126 ]\n        },\n        \"CH1_SCIEN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 127 ]\n        },\n        \"CH0_SCISEL\": {\n          \"direction\": \"input\",\n          \"bits\": [ 128 ]\n        },\n        \"CH1_SCISEL\": {\n          \"direction\": \"input\",\n          \"bits\": [ 129 ]\n        },\n        \"D_SCIRD\": {\n          \"direction\": \"input\",\n          \"bits\": [ 130 ]\n        },\n        \"D_SCIWSTN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 131 ]\n        },\n        \"D_CYAWSTN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 132 ]\n        },\n        \"D_FFC_SYNC_TOGGLE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 133 ]\n        },\n        \"D_FFC_DUAL_RST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 134 ]\n        },\n        \"D_FFC_MACRO_RST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 135 ]\n        },\n        \"D_FFC_MACROPDB\": {\n          \"direction\": \"input\",\n          \"bits\": [ 136 ]\n        },\n        \"D_FFC_TRST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 137 ]\n        },\n        \"CH0_FFC_CDR_EN_BITSLIP\": {\n          \"direction\": \"input\",\n          \"bits\": [ 138 ]\n        },\n        \"CH1_FFC_CDR_EN_BITSLIP\": {\n          \"direction\": \"input\",\n          \"bits\": [ 139 ]\n        },\n        \"D_SCAN_ENABLE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 140 ]\n        },\n        \"D_SCAN_IN_0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 141 ]\n        },\n        \"D_SCAN_IN_1\": {\n          \"direction\": \"input\",\n          \"bits\": [ 142 ]\n        },\n        \"D_SCAN_IN_2\": {\n          \"direction\": \"input\",\n          \"bits\": [ 143 ]\n        },\n        \"D_SCAN_IN_3\": {\n          \"direction\": \"input\",\n          \"bits\": [ 144 ]\n        },\n        \"D_SCAN_IN_4\": {\n          \"direction\": \"input\",\n          \"bits\": [ 145 ]\n        },\n        \"D_SCAN_IN_5\": {\n          \"direction\": \"input\",\n          \"bits\": [ 146 ]\n        },\n        \"D_SCAN_IN_6\": {\n          \"direction\": \"input\",\n          \"bits\": [ 147 ]\n        },\n        \"D_SCAN_IN_7\": {\n          \"direction\": \"input\",\n          \"bits\": [ 148 ]\n        },\n        \"D_SCAN_MODE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 149 ]\n        },\n        \"D_SCAN_RESET\": {\n          \"direction\": \"input\",\n          \"bits\": [ 150 ]\n        },\n        \"D_CIN0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 151 ]\n        },\n        \"D_CIN1\": {\n          \"direction\": \"input\",\n          \"bits\": [ 152 ]\n        },\n        \"D_CIN2\": {\n          \"direction\": \"input\",\n          \"bits\": [ 153 ]\n        },\n        \"D_CIN3\": {\n          \"direction\": \"input\",\n          \"bits\": [ 154 ]\n        },\n        \"D_CIN4\": {\n          \"direction\": \"input\",\n          \"bits\": [ 155 ]\n        },\n        \"D_CIN5\": {\n          \"direction\": \"input\",\n          \"bits\": [ 156 ]\n        },\n        \"D_CIN6\": {\n          \"direction\": \"input\",\n          \"bits\": [ 157 ]\n        },\n        \"D_CIN7\": {\n          \"direction\": \"input\",\n          \"bits\": [ 158 ]\n        },\n        \"D_CIN8\": {\n          \"direction\": \"input\",\n          \"bits\": [ 159 ]\n        },\n        \"D_CIN9\": {\n          \"direction\": \"input\",\n          \"bits\": [ 160 ]\n        },\n        \"D_CIN10\": {\n          \"direction\": \"input\",\n          \"bits\": [ 161 ]\n        },\n        \"D_CIN11\": {\n          \"direction\": \"input\",\n          \"bits\": [ 162 ]\n        },\n        \"CH0_HDOUTP\": {\n          \"direction\": \"output\",\n          \"bits\": [ 163 ]\n        },\n        \"CH1_HDOUTP\": {\n          \"direction\": \"output\",\n          \"bits\": [ 164 ]\n        },\n        \"CH0_HDOUTN\": {\n          \"direction\": \"output\",\n          \"bits\": [ 165 ]\n        },\n        \"CH1_HDOUTN\": {\n          \"direction\": \"output\",\n          \"bits\": [ 166 ]\n        },\n        \"D_TXBIT_CLKP_TO_ND\": {\n          \"direction\": \"output\",\n          \"bits\": [ 167 ]\n        },\n        \"D_TXBIT_CLKN_TO_ND\": {\n          \"direction\": \"output\",\n          \"bits\": [ 168 ]\n        },\n        \"D_SYNC_PULSE2ND\": {\n          \"direction\": \"output\",\n          \"bits\": [ 169 ]\n        },\n        \"D_TXPLL_LOL_TO_ND\": {\n          \"direction\": \"output\",\n          \"bits\": [ 170 ]\n        },\n        \"CH0_FF_RX_F_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 171 ]\n        },\n        \"CH1_FF_RX_F_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 172 ]\n        },\n        \"CH0_FF_RX_H_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 173 ]\n        },\n        \"CH1_FF_RX_H_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 174 ]\n        },\n        \"CH0_FF_TX_F_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 175 ]\n        },\n        \"CH1_FF_TX_F_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 176 ]\n        },\n        \"CH0_FF_TX_H_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 177 ]\n        },\n        \"CH1_FF_TX_H_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 178 ]\n        },\n        \"CH0_FF_RX_PCLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 179 ]\n        },\n        \"CH1_FF_RX_PCLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 180 ]\n        },\n        \"CH0_FF_TX_PCLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 181 ]\n        },\n        \"CH1_FF_TX_PCLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 182 ]\n        },\n        \"CH0_FF_RX_D_0\": {\n          \"direction\": \"output\",\n          \"bits\": [ 183 ]\n        },\n        \"CH1_FF_RX_D_0\": {\n          \"direction\": \"output\",\n          \"bits\": [ 184 ]\n        },\n        \"CH0_FF_RX_D_1\": {\n          \"direction\": \"output\",\n          \"bits\": [ 185 ]\n        },\n        \"CH1_FF_RX_D_1\": {\n          \"direction\": \"output\",\n          \"bits\": [ 186 ]\n        },\n        \"CH0_FF_RX_D_2\": {\n          \"direction\": \"output\",\n          \"bits\": [ 187 ]\n        },\n        \"CH1_FF_RX_D_2\": {\n          \"direction\": \"output\",\n          \"bits\": [ 188 ]\n        },\n        \"CH0_FF_RX_D_3\": {\n          \"direction\": \"output\",\n          \"bits\": [ 189 ]\n        },\n        \"CH1_FF_RX_D_3\": {\n          \"direction\": \"output\",\n          \"bits\": [ 190 ]\n        },\n        \"CH0_FF_RX_D_4\": {\n          \"direction\": \"output\",\n          \"bits\": [ 191 ]\n        },\n        \"CH1_FF_RX_D_4\": {\n          \"direction\": \"output\",\n          \"bits\": [ 192 ]\n        },\n        \"CH0_FF_RX_D_5\": {\n          \"direction\": \"output\",\n          \"bits\": [ 193 ]\n        },\n        \"CH1_FF_RX_D_5\": {\n          \"direction\": \"output\",\n          \"bits\": [ 194 ]\n        },\n        \"CH0_FF_RX_D_6\": {\n          \"direction\": \"output\",\n          \"bits\": [ 195 ]\n        },\n        \"CH1_FF_RX_D_6\": {\n          \"direction\": \"output\",\n          \"bits\": [ 196 ]\n        },\n        \"CH0_FF_RX_D_7\": {\n          \"direction\": \"output\",\n          \"bits\": [ 197 ]\n        },\n        \"CH1_FF_RX_D_7\": {\n          \"direction\": \"output\",\n          \"bits\": [ 198 ]\n        },\n        \"CH0_FF_RX_D_8\": {\n          \"direction\": \"output\",\n          \"bits\": [ 199 ]\n        },\n        \"CH1_FF_RX_D_8\": {\n          \"direction\": \"output\",\n          \"bits\": [ 200 ]\n        },\n        \"CH0_FF_RX_D_9\": {\n          \"direction\": \"output\",\n          \"bits\": [ 201 ]\n        },\n        \"CH1_FF_RX_D_9\": {\n          \"direction\": \"output\",\n          \"bits\": [ 202 ]\n        },\n        \"CH0_FF_RX_D_10\": {\n          \"direction\": \"output\",\n          \"bits\": [ 203 ]\n        },\n        \"CH1_FF_RX_D_10\": {\n          \"direction\": \"output\",\n          \"bits\": [ 204 ]\n        },\n        \"CH0_FF_RX_D_11\": {\n          \"direction\": \"output\",\n          \"bits\": [ 205 ]\n        },\n        \"CH1_FF_RX_D_11\": {\n          \"direction\": \"output\",\n          \"bits\": [ 206 ]\n        },\n        \"CH0_FF_RX_D_12\": {\n          \"direction\": \"output\",\n          \"bits\": [ 207 ]\n        },\n        \"CH1_FF_RX_D_12\": {\n          \"direction\": \"output\",\n          \"bits\": [ 208 ]\n        },\n        \"CH0_FF_RX_D_13\": {\n          \"direction\": \"output\",\n          \"bits\": [ 209 ]\n        },\n        \"CH1_FF_RX_D_13\": {\n          \"direction\": \"output\",\n          \"bits\": [ 210 ]\n        },\n        \"CH0_FF_RX_D_14\": {\n          \"direction\": \"output\",\n          \"bits\": [ 211 ]\n        },\n        \"CH1_FF_RX_D_14\": {\n          \"direction\": \"output\",\n          \"bits\": [ 212 ]\n        },\n        \"CH0_FF_RX_D_15\": {\n          \"direction\": \"output\",\n          \"bits\": [ 213 ]\n        },\n        \"CH1_FF_RX_D_15\": {\n          \"direction\": \"output\",\n          \"bits\": [ 214 ]\n        },\n        \"CH0_FF_RX_D_16\": {\n          \"direction\": \"output\",\n          \"bits\": [ 215 ]\n        },\n        \"CH1_FF_RX_D_16\": {\n          \"direction\": \"output\",\n          \"bits\": [ 216 ]\n        },\n        \"CH0_FF_RX_D_17\": {\n          \"direction\": \"output\",\n          \"bits\": [ 217 ]\n        },\n        \"CH1_FF_RX_D_17\": {\n          \"direction\": \"output\",\n          \"bits\": [ 218 ]\n        },\n        \"CH0_FF_RX_D_18\": {\n          \"direction\": \"output\",\n          \"bits\": [ 219 ]\n        },\n        \"CH1_FF_RX_D_18\": {\n          \"direction\": \"output\",\n          \"bits\": [ 220 ]\n        },\n        \"CH0_FF_RX_D_19\": {\n          \"direction\": \"output\",\n          \"bits\": [ 221 ]\n        },\n        \"CH1_FF_RX_D_19\": {\n          \"direction\": \"output\",\n          \"bits\": [ 222 ]\n        },\n        \"CH0_FF_RX_D_20\": {\n          \"direction\": \"output\",\n          \"bits\": [ 223 ]\n        },\n        \"CH1_FF_RX_D_20\": {\n          \"direction\": \"output\",\n          \"bits\": [ 224 ]\n        },\n        \"CH0_FF_RX_D_21\": {\n          \"direction\": \"output\",\n          \"bits\": [ 225 ]\n        },\n        \"CH1_FF_RX_D_21\": {\n          \"direction\": \"output\",\n          \"bits\": [ 226 ]\n        },\n        \"CH0_FF_RX_D_22\": {\n          \"direction\": \"output\",\n          \"bits\": [ 227 ]\n        },\n        \"CH1_FF_RX_D_22\": {\n          \"direction\": \"output\",\n          \"bits\": [ 228 ]\n        },\n        \"CH0_FF_RX_D_23\": {\n          \"direction\": \"output\",\n          \"bits\": [ 229 ]\n        },\n        \"CH1_FF_RX_D_23\": {\n          \"direction\": \"output\",\n          \"bits\": [ 230 ]\n        },\n        \"CH0_FFS_PCIE_DONE\": {\n          \"direction\": \"output\",\n          \"bits\": [ 231 ]\n        },\n        \"CH1_FFS_PCIE_DONE\": {\n          \"direction\": \"output\",\n          \"bits\": [ 232 ]\n        },\n        \"CH0_FFS_PCIE_CON\": {\n          \"direction\": \"output\",\n          \"bits\": [ 233 ]\n        },\n        \"CH1_FFS_PCIE_CON\": {\n          \"direction\": \"output\",\n          \"bits\": [ 234 ]\n        },\n        \"CH0_FFS_RLOS\": {\n          \"direction\": \"output\",\n          \"bits\": [ 235 ]\n        },\n        \"CH1_FFS_RLOS\": {\n          \"direction\": \"output\",\n          \"bits\": [ 236 ]\n        },\n        \"CH0_FFS_LS_SYNC_STATUS\": {\n          \"direction\": \"output\",\n          \"bits\": [ 237 ]\n        },\n        \"CH1_FFS_LS_SYNC_STATUS\": {\n          \"direction\": \"output\",\n          \"bits\": [ 238 ]\n        },\n        \"CH0_FFS_CC_UNDERRUN\": {\n          \"direction\": \"output\",\n          \"bits\": [ 239 ]\n        },\n        \"CH1_FFS_CC_UNDERRUN\": {\n          \"direction\": \"output\",\n          \"bits\": [ 240 ]\n        },\n        \"CH0_FFS_CC_OVERRUN\": {\n          \"direction\": \"output\",\n          \"bits\": [ 241 ]\n        },\n        \"CH1_FFS_CC_OVERRUN\": {\n          \"direction\": \"output\",\n          \"bits\": [ 242 ]\n        },\n        \"CH0_FFS_RXFBFIFO_ERROR\": {\n          \"direction\": \"output\",\n          \"bits\": [ 243 ]\n        },\n        \"CH1_FFS_RXFBFIFO_ERROR\": {\n          \"direction\": \"output\",\n          \"bits\": [ 244 ]\n        },\n        \"CH0_FFS_TXFBFIFO_ERROR\": {\n          \"direction\": \"output\",\n          \"bits\": [ 245 ]\n        },\n        \"CH1_FFS_TXFBFIFO_ERROR\": {\n          \"direction\": \"output\",\n          \"bits\": [ 246 ]\n        },\n        \"CH0_FFS_RLOL\": {\n          \"direction\": \"output\",\n          \"bits\": [ 247 ]\n        },\n        \"CH1_FFS_RLOL\": {\n          \"direction\": \"output\",\n          \"bits\": [ 248 ]\n        },\n        \"CH0_FFS_SKP_ADDED\": {\n          \"direction\": \"output\",\n          \"bits\": [ 249 ]\n        },\n        \"CH1_FFS_SKP_ADDED\": {\n          \"direction\": \"output\",\n          \"bits\": [ 250 ]\n        },\n        \"CH0_FFS_SKP_DELETED\": {\n          \"direction\": \"output\",\n          \"bits\": [ 251 ]\n        },\n        \"CH1_FFS_SKP_DELETED\": {\n          \"direction\": \"output\",\n          \"bits\": [ 252 ]\n        },\n        \"CH0_LDR_RX2CORE\": {\n          \"direction\": \"output\",\n          \"bits\": [ 253 ]\n        },\n        \"CH1_LDR_RX2CORE\": {\n          \"direction\": \"output\",\n          \"bits\": [ 254 ]\n        },\n        \"D_SCIRDATA0\": {\n          \"direction\": \"output\",\n          \"bits\": [ 255 ]\n        },\n        \"D_SCIRDATA1\": {\n          \"direction\": \"output\",\n          \"bits\": [ 256 ]\n        },\n        \"D_SCIRDATA2\": {\n          \"direction\": \"output\",\n          \"bits\": [ 257 ]\n        },\n        \"D_SCIRDATA3\": {\n          \"direction\": \"output\",\n          \"bits\": [ 258 ]\n        },\n        \"D_SCIRDATA4\": {\n          \"direction\": \"output\",\n          \"bits\": [ 259 ]\n        },\n        \"D_SCIRDATA5\": {\n          \"direction\": \"output\",\n          \"bits\": [ 260 ]\n        },\n        \"D_SCIRDATA6\": {\n          \"direction\": \"output\",\n          \"bits\": [ 261 ]\n        },\n        \"D_SCIRDATA7\": {\n          \"direction\": \"output\",\n          \"bits\": [ 262 ]\n        },\n        \"D_SCIINT\": {\n          \"direction\": \"output\",\n          \"bits\": [ 263 ]\n        },\n        \"D_SCAN_OUT_0\": {\n          \"direction\": \"output\",\n          \"bits\": [ 264 ]\n        },\n        \"D_SCAN_OUT_1\": {\n          \"direction\": \"output\",\n          \"bits\": [ 265 ]\n        },\n        \"D_SCAN_OUT_2\": {\n          \"direction\": \"output\",\n          \"bits\": [ 266 ]\n        },\n        \"D_SCAN_OUT_3\": {\n          \"direction\": \"output\",\n          \"bits\": [ 267 ]\n        },\n        \"D_SCAN_OUT_4\": {\n          \"direction\": \"output\",\n          \"bits\": [ 268 ]\n        },\n        \"D_SCAN_OUT_5\": {\n          \"direction\": \"output\",\n          \"bits\": [ 269 ]\n        },\n        \"D_SCAN_OUT_6\": {\n          \"direction\": \"output\",\n          \"bits\": [ 270 ]\n        },\n        \"D_SCAN_OUT_7\": {\n          \"direction\": \"output\",\n          \"bits\": [ 271 ]\n        },\n        \"D_COUT0\": {\n          \"direction\": \"output\",\n          \"bits\": [ 272 ]\n        },\n        \"D_COUT1\": {\n          \"direction\": \"output\",\n          \"bits\": [ 273 ]\n        },\n        \"D_COUT2\": {\n          \"direction\": \"output\",\n          \"bits\": [ 274 ]\n        },\n        \"D_COUT3\": {\n          \"direction\": \"output\",\n          \"bits\": [ 275 ]\n        },\n        \"D_COUT4\": {\n          \"direction\": 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  },
  {
    "path": "src/blink/blink.v",
    "content": "module blink (\n    input      clk_i,\n    output reg led_o\n);\nlocalparam MAX = 2_500_000;\nlocalparam WIDTH = $clog2(MAX);\n\nwire rst_s;\nwire clk_s;\n\nassign clk_s = clk_i;\n//pll_12_16 pll_inst (.clki(clk_i), .clko(clk_s), .rst(rst_s));\nrst_gen rst_inst (.clk_i(clk_s), .rst_i(1'b0), .rst_o(rst_s));\n\nreg  [WIDTH-1:0] cpt_s;\nwire [WIDTH-1:0] cpt_next_s = cpt_s + 1'b1;\n\nwire             end_s = cpt_s == MAX-1;\n\nalways @(posedge clk_s) begin\n    cpt_s <= (rst_s || end_s) ? {WIDTH{1'b0}} : cpt_next_s;\n\n    if (rst_s)\n        led_o <= 1'b0;\n    else if (end_s)\n        led_o <= ~led_o;\nend\nendmodule\n"
  },
  {
    "path": "src/blink/blink_out.config",
    "content": ".device LFE5U-25F\n\n.comment Part: LFE5U-25F-6CABGA256\n\n.tile CIB_R1C54:CIB\narc: JA0 S1_V02N0701\nenum: CIB.JB0MUX 0\n\n.tile CIB_R29C1:CIB_LR\narc: JD7 V00B0000\narc: V00B0000 S1_V02N0201\n\n.tile CIB_R31C1:CIB_LR\narc: N1_V02N0201 S3_V06N0103\n\n.tile CIB_R37C1:CIB_LR_S\narc: N3_V06N0103 S3_V06N0003\n\n.tile CIB_R43C1:CIB_LR\narc: N3_V06N0003 S3_V06N0303\n\n.tile CIB_R49C1:CIB_LR_S\narc: N3_V06N0303 JF5\n\n.tile CIB_R49C3:CIB_PLL3\nenum: CIB.JA3MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R49C42:VCIB_DCU0\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C43:VCIB_DCUA\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C44:VCIB_DCUB\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C45:VCIB_DCUC\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C46:VCIB_DCUD\nenum: CIB.JA1MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C47:VCIB_DCUF\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C48:VCIB_DCU3\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C49:VCIB_DCU2\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C50:VCIB_DCUG\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C51:VCIB_DCUH\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C52:VCIB_DCUI\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C53:VCIB_DCU1\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\n\n.tile CIB_R49C69:CIB_PLL3\nenum: CIB.JA3MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R49C6:CIB_EFB0\nenum: CIB.JB3MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C7:CIB_EFB1\nenum: CIB.JA3MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JC3MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\n\n.tile MIB_R0C54:PIOT1\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS25\n\n.tile MIB_R0C69:BANKREF1\nenum: BANK.VCCIO 2V5\n\n.tile MIB_R13C31:CMUX_UL_0\narc: G_DCS0CLK0 G_VPFN0000\narc: G_ULPCLK0 G_HPFE0000\n\n.tile MIB_R13C32:CMUX_UR_0\narc: G_DCS0CLK1 G_VPFN0000\narc: G_URPCLK0 G_HPFE0000\n\n.tile MIB_R13C3:DSP_SPINE_UL1\nunknown: F2B0\nunknown: F3B0\nunknown: F5B0\nunknown: F11B0\nunknown: F13B0\n\n.tile MIB_R13C59:DSP_SPINE_UR1\narc: G_VPTX0000 G_HPRX0000\n\n.tile MIB_R1C54:PICT1\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS25\n\n.tile MIB_R25C3:LMID_0\narc: G_LDCC0CLKI G_JLLQPCLKCIB0\n\n.tile MIB_R37C31:CMUX_LL_0\narc: G_DCS1CLK0 G_VPFN0000\narc: G_LLPCLK0 G_HPFE0000\n\n.tile MIB_R37C32:CMUX_LR_0\narc: G_DCS1CLK1 G_VPFN0000\narc: G_LRPCLK0 G_HPFE0000\n\n.tile MIB_R48C0:PICL1\nenum: PIOC.BASE_TYPE INPUT_LVCMOS33\nenum: PIOC.HYSTERESIS ON\n\n.tile MIB_R49C0:MIB_CIB_LR\nenum: PIOC.BASE_TYPE INPUT_LVCMOS33\n\n.tile MIB_R50C4:EFB0_PICB0\nunknown: F54B1\nunknown: F56B1\nunknown: F82B1\nunknown: F94B1\n\n.tile R2C52:PLC2\narc: H00L0000 H02W0001\narc: H00L0100 E1_H02W0301\narc: H00R0000 H02W0601\narc: H00R0100 E1_H02W0501\narc: S1_V02S0501 H06W0303\narc: V00B0000 E1_H02W0601\narc: A0 H00L0000\narc: A1 H00L0100\narc: B0 E1_H01W0100\narc: B1 V00B0000\narc: C0 E1_H01W0000\narc: C1 H00R0100\narc: D0 H00R0000\narc: D1 E1_H02W0001\narc: E1_H02E0701 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: S1_V02S0001 F0\narc: S1_V02S0101 F1\narc: V01S0100 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R2C53:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0501 V02N0501\narc: S1_V02S0501 E1_H02W0501\narc: V00T0100 V02N0501\narc: A0 H02E0701\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V01S0000\narc: B6 V00B0000\narc: B7 V00B0100\narc: CLK0 G_HPBX0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: H01W0100 Q3\narc: LSR1 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: V00B0000 Q6\narc: V00B0100 Q7\narc: V01S0000 Q5\narc: V01S0100 Q7\narc: W1_H02W0001 Q2\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R2C54:PLC2\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0401 H02W0401\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0501 E1_H01W0100\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 H02E0101\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0100 Q7\narc: LSR1 H02E0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: S1_V02S0201 Q0\narc: S1_V02S0301 Q3\narc: S1_V02S0501 Q7\narc: S1_V02S0601 Q6\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V00T0000 Q0\narc: V01S0000 Q5\narc: V01S0100 Q2\narc: W1_H02W0301 Q1\narc: W1_H02W0601 Q4\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R2C55:PLC2\narc: W1_H02W0501 E1_H01W0100\narc: W3_H06W0303 E1_H01W0100\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V02N0701\narc: B6 V00B0000\narc: B7 V00B0100\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q7\narc: H01W0100 Q3\narc: LSR0 W1_H02E0501\narc: LSR1 W1_H02E0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: S1_V02S0201 Q0\narc: V00B0000 Q6\narc: V00B0100 Q7\narc: V00T0000 Q0\narc: V01S0000 Q4\narc: V01S0100 Q5\narc: W1_H02W0001 Q2\narc: W1_H02W0101 Q1\narc: W1_H02W0401 Q6\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R2C56:PLC2\narc: B2 H00R0000\narc: B7 V00B0000\narc: C2 H00L0100\narc: C3 N1_V01N0001\narc: C7 V00T0100\narc: CE1 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 Q2\narc: D3 V00T0100\narc: D6 V00B0000\narc: D7 H01W0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: H00R0000 Q6\narc: H00R0100 F7\narc: H01W0000 Q2\narc: H01W0100 Q2\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: V00B0000 Q6\narc: V00T0100 Q3\nword: SLICEB.K0.INIT 0011111111000000\nword: SLICEB.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 1111110011111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C52:PLC2\narc: H00L0100 V02S0101\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02S0501\narc: V00B0000 V02S0001\narc: V00B0100 E1_H02W0501\narc: V00T0100 E1_H02W0301\narc: A1 H00R0000\narc: A5 V00T0100\narc: B1 V02S0101\narc: B5 V00B0100\narc: C1 N1_V01S0100\narc: C5 E1_H02W0601\narc: D1 V00T0100\narc: D5 H00L0100\narc: E1_H01E0101 F1\narc: E1_H02E0401 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: M0 V00B0100\narc: M1 H00R0100\narc: M2 V00B0100\narc: M4 V00B0000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 0111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R3C53:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0701 N1_V01S0100\narc: H00R0000 H02E0401\narc: H00R0100 V02S0501\narc: N1_V02N0501 H01E0101\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 H00R0100\narc: E1_H01E0101 Q4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: LSR0 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: V00B0000 Q4\narc: V00B0100 F5\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R3C54:PLC2\narc: H00L0000 V02S0001\narc: N1_V02N0701 H01E0101\narc: V00B0000 V02S0201\narc: V00B0100 H02W0501\narc: V00T0000 V02S0601\narc: V00T0100 V02S0501\narc: A1 H02E0701\narc: A4 V02S0301\narc: A5 V02S0101\narc: B1 V00B0000\narc: B4 N1_V01S0000\narc: B5 H00L0000\narc: C1 N1_V01S0100\narc: C4 V00T0000\narc: C5 V00B0100\narc: D1 V00T0100\narc: D4 H02W0201\narc: D5 V02S0401\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: M0 H02W0601\narc: M1 H02E0001\narc: M2 H02W0601\narc: W1_H02W0301 F1\narc: W1_H02W0501 F5\narc: W1_H02W0601 F4\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R3C55:PLC2\narc: N1_V02N0701 N1_V01S0100\narc: W1_H02W0201 V02S0201\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 N1_V01S0000\n\n.tile R45C37:PLC2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile TAP_R2C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R3C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n"
  },
  {
    "path": "src/blink/rst_gen.v",
    "content": "module rst_gen (\n\tinput \t\t\tclk_i,\n\tinput \t\t\trst_i,\n\toutput\t\t\trst_o\n);\n\n/* try to generate a reset */\nreg [2:0]\trst_cpt;\nalways @(posedge clk_i) begin\n\tif (rst_i)\n\t\trst_cpt = 3'b0;\n\telse begin\n\t\tif (rst_cpt == 3'b100)\n\t\t\trst_cpt = rst_cpt;\n\t\telse\n\t\t\trst_cpt = rst_cpt + 3'b1;\n\tend\nend\n\nassign rst_o = !rst_cpt[2];\n\nendmodule\n"
  },
  {
    "path": "src/hdmi_test_pattern/Makefile",
    "content": "YOSYS=yosys\nNEXTPNR=nextpnr-ecp5\nECPPACK=ecppack\nHDMICODE=DVI_3x3.v\nHDMICODE=llhdmi.v vgatestsrc.v\nENCODER=TMDS_encoder.v\n\n.PHONY: all\nall: ulx3s_25f_ULX3S_25F.bit\n\nULX3S_25F.ys: ULX3S_25F.v $(HDMICODE) $(ENCODER) clock.v OBUFDS.v\n\tchmod +x ysgen.sh\n\t./ysgen.sh ULX3S_25F.v  $(HDMICODE) $(ENCODER) clock.v \\\n\t\tOBUFDS.v  > ULX3S_25F.ys\n\techo \"hierarchy -top ULX3S_25F\" >> ULX3S_25F.ys\n\techo \"synth_ecp5 -json ULX3S_25F.json\" >> ULX3S_25F.ys\n\nULX3S_25F.json: ULX3S_25F.ys\n\t$(YOSYS) -q ULX3S_25F.ys\n\nulx3s_25f_ULX3S_25F.config: ULX3S_25F.json\n\t#$(NEXTPNR) --25k --package CABGA381 --json ULX3S_25F.json --lpf ulx3s_v20_segpdi.lpf --textcfg ulx3s_25f_ULX3S_25F.config\n\t$(NEXTPNR) --25k --package CABGA256 --json ULX3S_25F.json --lpf icesugar_pro.lpf \\\n\t--textcfg ulx3s_25f_ULX3S_25F.config\n\nulx3s_25f_ULX3S_25F.bit: ulx3s_25f_ULX3S_25F.config\n\t$(ECPPACK) --input ulx3s_25f_ULX3S_25F.config \\\n\t\t--bit ulx3s_25f_ULX3S_25F.bit\n        \n.PHONY: clean\nclean:\n\trm -f ULX3S_25F.ys ULX3S_25F.json ulx3s_25f_ULX3S_25F.config \\\n\t\tulx3s_25f_ULX3S_25F.bit\n"
  },
  {
    "path": "src/hdmi_test_pattern/Makefile.sim",
    "content": "##\n## Verilator Rules\n##\n.PHONY: all\n#.DELETE_ON_ERROR:\nTOPMOD  := DVI_3x3\nTOPMOD  := llhdmi\nTOPMOD  := pattern\nVLOGFIL := $(TOPMOD).v\nVCDFILE := $(TOPMOD).vcd\nSIMPROG := $(TOPMOD)_tb\nSIMFILE := $(SIMPROG).cpp\nVDIRFB  := ./obj_dir\nall: $(VCDFILE)\n\nGCC := g++\nCFLAGS = -g -Wall -I$(VINC) -I $(VDIRFB)\n#\n# Modern versions of Verilator and C++ may require an -faligned-new flag\n# CFLAGS = -g -Wall -faligned-new -I$(VINC) -I $(VDIRFB)\n\nVERILATOR=verilator\nVFLAGS := -O3 -MMD --trace -Wall\n\n## Find the directory containing the Verilog sources.  This is given from\n## calling: \"verilator -V\" and finding the VERILATOR_ROOT output line from\n## within it.  From this VERILATOR_ROOT value, we can find all the components\n## we need here--in particular, the verilator include directory\nVERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1 | sed -e \"s/^.*=\\s*//\"')\n##\n## The directory containing the verilator includes\nVINC := $(VERILATOR_ROOT)/include\n\n$(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v \n\t$(VERILATOR) $(VFLAGS) -cc --top-module $(TOPMOD) $(VLOGFIL)\n\n$(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp\n\tmake --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk\n\n$(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS)\n\t$(GCC) $(CFLAGS) $(VINC)/verilated.cpp\t\t\t\t\\\n\t\t$(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS)\t\\\n\t\t$(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG)\n\ntest: $(VCDFILE)\n\n$(VCDFILE): $(SIMPROG)\n\t./$(SIMPROG) > image.ppm\n\n## \n.PHONY: clean\nclean:\n\trm -rf $(VDIRFB)/ $(SIMPROG) $(VCDFILE) image.ppm\n\n##\n## Find all of the Verilog dependencies and submodules\n##\nDEPS := $(wildcard $(VDIRFB)/*.d)\n\n## Include any of these submodules in the Makefile\n## ... but only if we are not building the \"clean\" target\n## which would (oops) try to build those dependencies again\n##\nifneq ($(MAKECMDGOALS),clean)\nifneq ($(DEPS),)\ninclude $(DEPS)\nendif\nendif\n"
  },
  {
    "path": "src/hdmi_test_pattern/OBUFDS.v",
    "content": "// (c) fpga4fun.com & KNJN LLC 2013\r\n\r\n////////////////////////////////////////////////////////////////////////\r\nmodule OBUFDS(\r\n\tinput I, // input\r\n\toutput O, // positive output\r\n\toutput OB // negative output\r\n);\r\n\r\nassign O = I;\r\nassign OB = ~I;\r\n\r\nendmodule\r\n////////////////////////////////////////////////////////////////////////\r\n"
  },
  {
    "path": "src/hdmi_test_pattern/README.md",
    "content": "# ULX3S HDMI Test Patterm Generator\n\nI've taken the idea of a low-level video generator from Dan Gisselquist's\n[llvga.v](https://github.com/ZipCPU/vgasim/blob/master/rtl/llvga.v) module\nand also the\n[HDMI code from Emard](https://github.com/DoctorWkt/Verilog_tic-tac-toe/tree/master/HDMI), and I've created a _llhdmi.v_ video generating module.\n\nI have also taken Dan Gisselquist's\n[vgatestsrc.v](https://github.com/ZipCPU/vgasim/blob/master/rtl/vgatestsrc.v)\ntest pattern generator, and built a ULX3S project that displays the test\npattern on the HDMI output.\n\nTo do this, ```make -f UMakefile```.\n\nThere is also a make with Verilator, ```make -f Makefile```. This uses the\ntest pattern generator and produces the image file ```image.ppm```.\n\nThe _dec_6_2018.jpg_ image is a photo of the first output from the project.\nOn Dec 10, 2018, I updated the _vgatestsrc.v_ from ZipCPU, added a reset\nline and re-imported _TMDS_encoder.v_. This time, I decorated the file\nwith some ```/* verilator lint_off UNOPTFLAT */``` lines because the\ncode that sets ```q_m``` really isn't right. I've fixed this by creating\nseparate wires and bundling them together afterwards. The _dec_10_2018.jpg_\nimage shows the current HDMI output from the project.\n\n"
  },
  {
    "path": "src/hdmi_test_pattern/TMDS_encoder.v",
    "content": "// (c) fpga4fun.com & KNJN LLC 2013\n\n////////////////////////////////////////////////////////////////////////\nmodule TMDS_encoder(\n\tinput clk, // 250 MHz\n\tinput [7:0] VD,  // video data (red, green or blue)\n\tinput [1:0] CD,  // control data\n\tinput VDE,  // video data enable, to choose between CD (when VDE=0) and VD (when VDE=1)\n\toutput reg [9:0] TMDS = 0\n);\n\nwire [3:0] Nb1s = {3'b0, VD[0]} + {3'b0, VD[1]} + {3'b0, VD[2]}\n\t+ {3'b0, VD[3]} + {3'b0, VD[4]} + {3'b0, VD[5]}\n\t+ {3'b0, VD[6]} + {3'b0, VD[7]};\nwire XNOR = (Nb1s>4'd4) || (Nb1s==4'd4 && VD[0]==1'b0);\n\n// To keep Verilator happy, we create individual wires, determine\n// their values and then merge them into q_m[]\nwire QM0, QM1, QM2, QM3, QM4, QM5, QM6, QM7, QM8;\nassign QM0= VD[0];\nassign QM1= QM0 ^ VD[1] ^ XNOR;\nassign QM2= QM1 ^ VD[2] ^ XNOR;\nassign QM3= QM2 ^ VD[3] ^ XNOR;\nassign QM4= QM3 ^ VD[4] ^ XNOR;\nassign QM5= QM4 ^ VD[5] ^ XNOR;\nassign QM6= QM5 ^ VD[6] ^ XNOR;\nassign QM7= QM6 ^ VD[7] ^ XNOR;\nassign QM8= ~XNOR;\nwire [8:0] q_m = { QM8, QM7, QM6, QM5, QM4, QM3, QM2, QM1, QM0 };\n\nreg [3:0] balance_acc = 0;\nwire [3:0] balance = {3'b0, q_m[0]} + {3'b0, q_m[1]} + {3'b0, q_m[2]}\n\t+ {3'b0, q_m[3]} + {3'b0, q_m[4]} + {3'b0, q_m[5]}\n\t+ {3'b0, q_m[6]} + {3'b0, q_m[7]} - 4'd4;\nwire balance_sign_eq = (balance[3] == balance_acc[3]);\nwire invert_q_m = (balance==0 || balance_acc==0) ? ~q_m[8] : balance_sign_eq;\n\nwire [3:0] balance_acc_inc = balance\n\t- {3'b0,\n\t   ({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0)) };\nwire [3:0] balance_acc_new = invert_q_m ? balance_acc-balance_acc_inc : balance_acc+balance_acc_inc;\nwire [9:0] TMDS_data = {invert_q_m, q_m[8], q_m[7:0] ^ {8{invert_q_m}}};\nwire [9:0] TMDS_code = CD[1] ? (CD[0] ? 10'b1010101011 : 10'b0101010100) : (CD[0] ? 10'b0010101011 : 10'b1101010100);\n\nalways @(posedge clk) TMDS <= VDE ? TMDS_data : TMDS_code;\nalways @(posedge clk) balance_acc <= VDE ? balance_acc_new : 4'h0;\nendmodule\n\n////////////////////////////////////////////////////////////////////////\n"
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\"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_bb.v:323.9-323.14\"\n          }\n        },\n        \"CLKI\": {\n          \"hide_name\": 0,\n          \"bits\": [ 2 ],\n          \"attributes\": {\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_bb.v:322.8-322.12\"\n          }\n        },\n        \"RST\": {\n          \"hide_name\": 0,\n          \"bits\": [ 3 ],\n          \"attributes\": {\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_bb.v:322.14-322.17\"\n          }\n        }\n      }\n    },\n    \"DCCA\": {\n      \"attributes\": {\n        \"blackbox\": \"00000000000000000000000000000001\",\n        \"cells_not_processed\": \"00000000000000000000000000000001\",\n        \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_bb.v:344.1-348.10\"\n      },\n      \"ports\": {\n        \"CLKI\": {\n          \"direction\": \"input\",\n          \"bits\": [ 2 ]\n        },\n        \"CE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 3 ]\n        },\n        \"CLKO\": {\n          \"direction\": \"output\",\n          \"bits\": [ 4 ]\n        }\n      },\n      \"cells\": {\n      },\n      \"netnames\": {\n        \"CE\": {\n          \"hide_name\": 0,\n          \"bits\": [ 3 ],\n          \"attributes\": {\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_bb.v:345.14-345.16\"\n          }\n        },\n        \"CLKI\": {\n          \"hide_name\": 0,\n          \"bits\": [ 2 ],\n          \"attributes\": {\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_bb.v:345.8-345.12\"\n          }\n        },\n        \"CLKO\": {\n          \"hide_name\": 0,\n          \"bits\": [ 4 ],\n          \"attributes\": {\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_bb.v:346.9-346.13\"\n          }\n        }\n      }\n    },\n    \"DCUA\": {\n      \"attributes\": {\n        \"keep\": \"00000000000000000000000000000001\",\n        \"blackbox\": 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\"CH0_DCOFLTDAC\": \"0b00\",\n        \"CH0_DCOFTNRG\": \"0b000\",\n        \"CH0_DCOIOSTUNE\": \"0b000\",\n        \"CH0_DCOITUNE\": \"0b00\",\n        \"CH0_DCOITUNE4LSB\": \"0b000\",\n        \"CH0_DCOIUPDNX2\": \"0b0\",\n        \"CH0_DCONUOFLSB\": \"0b000\",\n        \"CH0_DCOSCALEI\": \"0b00\",\n        \"CH0_DCOSTARTVAL\": \"0b000\",\n        \"CH0_DCOSTEP\": \"0b00\",\n        \"CH0_DEC_BYPASS\": \"0b0\",\n        \"CH0_ENABLE_CG_ALIGN\": \"0b0\",\n        \"CH0_ENC_BYPASS\": \"0b0\",\n        \"CH0_FF_RX_F_CLK_DIS\": \"0b0\",\n        \"CH0_FF_RX_H_CLK_EN\": \"0b0\",\n        \"CH0_FF_TX_F_CLK_DIS\": \"0b0\",\n        \"CH0_FF_TX_H_CLK_EN\": \"0b0\",\n        \"CH0_GE_AN_ENABLE\": \"0b0\",\n        \"CH0_INVERT_RX\": \"0b0\",\n        \"CH0_INVERT_TX\": \"0b0\",\n        \"CH0_LDR_CORE2TX_SEL\": \"0b0\",\n        \"CH0_LDR_RX2CORE_SEL\": \"0b0\",\n        \"CH0_LEQ_OFFSET_SEL\": \"0b0\",\n        \"CH0_LEQ_OFFSET_TRIM\": \"0b000\",\n        \"CH0_LSM_DISABLE\": \"0b0\",\n        \"CH0_MATCH_2_ENABLE\": \"0b0\",\n        \"CH0_MATCH_4_ENABLE\": \"0b0\",\n        \"CH0_MIN_IPG_CNT\": \"0b00\",\n        \"CH0_PCIE_EI_EN\": \"0b0\",\n        \"CH0_PCIE_MODE\": \"0b0\",\n        \"CH0_PCS_DET_TIME_SEL\": \"0b00\",\n        \"CH0_PDEN_SEL\": \"0b0\",\n        \"CH0_PRBS_ENABLE\": \"0b0\",\n        \"CH0_PRBS_LOCK\": \"0b0\",\n        \"CH0_PRBS_SELECTION\": \"0b0\",\n        \"CH0_PROTOCOL\": \"8B10B\",\n        \"CH0_RATE_MODE_RX\": \"0b0\",\n        \"CH0_RATE_MODE_TX\": \"0b0\",\n        \"CH0_RCV_DCC_EN\": \"0b0\",\n        \"CH0_REG_BAND_OFFSET\": \"0b0000\",\n        \"CH0_REG_BAND_SEL\": \"0b000000\",\n        \"CH0_REG_IDAC_EN\": \"0b0\",\n        \"CH0_REG_IDAC_SEL\": \"0b0000000000\",\n        \"CH0_REQ_EN\": \"0b0\",\n        \"CH0_REQ_LVL_SET\": \"0b00\",\n        \"CH0_RIO_MODE\": \"0b0\",\n        \"CH0_RLOS_SEL\": \"0b0\",\n        \"CH0_RPWDNB\": \"0b0\",\n        \"CH0_RTERM_RX\": \"0b00000\",\n        \"CH0_RTERM_TX\": \"0b00000\",\n        \"CH0_RXIN_CM\": \"0b00\",\n        \"CH0_RXTERM_CM\": \"0b00\",\n        \"CH0_RX_DCO_CK_DIV\": \"0b000\",\n        \"CH0_RX_DIV11_SEL\": \"0b0\",\n        \"CH0_RX_GEAR_BYPASS\": \"0b0\",\n        \"CH0_RX_GEAR_MODE\": \"0b0\",\n        \"CH0_RX_LOS_CEQ\": \"0b00\",\n        \"CH0_RX_LOS_EN\": \"0b0\",\n        \"CH0_RX_LOS_HYST_EN\": \"0b0\",\n        \"CH0_RX_LOS_LVL\": \"0b000\",\n        \"CH0_RX_RATE_SEL\": \"0b0000\",\n        \"CH0_RX_SB_BYPASS\": \"0b0\",\n        \"CH0_SB_BYPASS\": \"0b0\",\n        \"CH0_SEL_SD_RX_CLK\": \"0b0\",\n        \"CH0_TDRV_DAT_SEL\": \"0b00\",\n        \"CH0_TDRV_POST_EN\": \"0b0\",\n        \"CH0_TDRV_PRE_EN\": \"0b0\",\n        \"CH0_TDRV_SLICE0_CUR\": \"0b000\",\n        \"CH0_TDRV_SLICE0_SEL\": \"0b00\",\n        \"CH0_TDRV_SLICE1_CUR\": \"0b000\",\n        \"CH0_TDRV_SLICE1_SEL\": \"0b00\",\n        \"CH0_TDRV_SLICE2_CUR\": \"0b00\",\n        \"CH0_TDRV_SLICE2_SEL\": \"0b00\",\n        \"CH0_TDRV_SLICE3_CUR\": \"0b00\",\n        \"CH0_TDRV_SLICE3_SEL\": \"0b00\",\n        \"CH0_TDRV_SLICE4_CUR\": \"0b00\",\n        \"CH0_TDRV_SLICE4_SEL\": \"0b00\",\n        \"CH0_TDRV_SLICE5_CUR\": \"0b00\",\n        \"CH0_TDRV_SLICE5_SEL\": \"0b00\",\n        \"CH0_TPWDNB\": \"0b0\",\n        \"CH0_TXAMPLITUDE\": \"0d1300\",\n        \"CH0_TXDEPOST\": \"DISABLED\",\n        \"CH0_TXDEPRE\": \"DISABLED\",\n        \"CH0_TX_CM_SEL\": \"0b00\",\n        \"CH0_TX_DIV11_SEL\": \"0b0\",\n        \"CH0_TX_GEAR_BYPASS\": \"0b0\",\n        \"CH0_TX_GEAR_MODE\": \"0b0\",\n        \"CH0_TX_POST_SIGN\": \"0b0\",\n        \"CH0_TX_PRE_SIGN\": \"0b0\",\n        \"CH0_UC_MODE\": \"0b0\",\n        \"CH0_UDF_COMMA_A\": \"0b0000000000\",\n        \"CH0_UDF_COMMA_B\": \"0b0000000000\",\n        \"CH0_UDF_COMMA_MASK\": \"0b0000000000\",\n        \"CH0_WA_BYPASS\": \"0b0\",\n        \"CH0_WA_MODE\": \"0b0\",\n        \"CH1_AUTO_CALIB_EN\": \"0b0\",\n        \"CH1_AUTO_FACQ_EN\": \"0b0\",\n        \"CH1_BAND_THRESHOLD\": \"0b000000\",\n        \"CH1_CALIB_CK_MODE\": \"0b0\",\n        \"CH1_CC_MATCH_1\": \"0b0000000000\",\n        \"CH1_CC_MATCH_2\": \"0b0000000000\",\n        \"CH1_CC_MATCH_3\": \"0b0000000000\",\n        \"CH1_CC_MATCH_4\": \"0b0000000000\",\n        \"CH1_CDR_CNT4SEL\": \"0b00\",\n        \"CH1_CDR_CNT8SEL\": \"0b00\",\n        \"CH1_CDR_MAX_RATE\": \"2.5\",\n        \"CH1_CTC_BYPASS\": \"0b0\",\n        \"CH1_DCOATDCFG\": \"0b00\",\n        \"CH1_DCOATDDLY\": \"0b00\",\n        \"CH1_DCOBYPSATD\": \"0b0\",\n        \"CH1_DCOCALDIV\": \"0b000\",\n        \"CH1_DCOCTLGI\": \"0b000\",\n        \"CH1_DCODISBDAVOID\": \"0b0\",\n        \"CH1_DCOFLTDAC\": \"0b00\",\n        \"CH1_DCOFTNRG\": \"0b000\",\n        \"CH1_DCOIOSTUNE\": \"0b000\",\n        \"CH1_DCOITUNE\": \"0b00\",\n        \"CH1_DCOITUNE4LSB\": \"0b000\",\n        \"CH1_DCOIUPDNX2\": \"0b0\",\n        \"CH1_DCONUOFLSB\": \"0b000\",\n        \"CH1_DCOSCALEI\": \"0b00\",\n        \"CH1_DCOSTARTVAL\": \"0b000\",\n        \"CH1_DCOSTEP\": \"0b00\",\n  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\"0b0\",\n        \"CH1_PROTOCOL\": \"8B10B\",\n        \"CH1_RATE_MODE_RX\": \"0b0\",\n        \"CH1_RATE_MODE_TX\": \"0b0\",\n        \"CH1_RCV_DCC_EN\": \"0b0\",\n        \"CH1_REG_BAND_OFFSET\": \"0b0000\",\n        \"CH1_REG_BAND_SEL\": \"0b000000\",\n        \"CH1_REG_IDAC_EN\": \"0b0\",\n        \"CH1_REG_IDAC_SEL\": \"0b0000000000\",\n        \"CH1_REQ_EN\": \"0b0\",\n        \"CH1_REQ_LVL_SET\": \"0b00\",\n        \"CH1_RIO_MODE\": \"0b0\",\n        \"CH1_RLOS_SEL\": \"0b0\",\n        \"CH1_RPWDNB\": \"0b0\",\n        \"CH1_RTERM_RX\": \"0b00000\",\n        \"CH1_RTERM_TX\": \"0b00000\",\n        \"CH1_RXIN_CM\": \"0b00\",\n        \"CH1_RXTERM_CM\": \"0b00\",\n        \"CH1_RX_DCO_CK_DIV\": \"0b000\",\n        \"CH1_RX_DIV11_SEL\": \"0b0\",\n        \"CH1_RX_GEAR_BYPASS\": \"0b0\",\n        \"CH1_RX_GEAR_MODE\": \"0b0\",\n        \"CH1_RX_LOS_CEQ\": \"0b00\",\n        \"CH1_RX_LOS_EN\": \"0b0\",\n        \"CH1_RX_LOS_HYST_EN\": \"0b0\",\n        \"CH1_RX_LOS_LVL\": \"0b000\",\n        \"CH1_RX_RATE_SEL\": \"0b0000\",\n        \"CH1_RX_SB_BYPASS\": \"0b0\",\n        \"CH1_SB_BYPASS\": \"0b0\",\n        \"CH1_SEL_SD_RX_CLK\": \"0b0\",\n        \"CH1_TDRV_DAT_SEL\": \"0b00\",\n        \"CH1_TDRV_POST_EN\": \"0b0\",\n        \"CH1_TDRV_PRE_EN\": \"0b0\",\n        \"CH1_TDRV_SLICE0_CUR\": \"0b000\",\n        \"CH1_TDRV_SLICE0_SEL\": \"0b00\",\n        \"CH1_TDRV_SLICE1_CUR\": \"0b000\",\n        \"CH1_TDRV_SLICE1_SEL\": \"0b00\",\n        \"CH1_TDRV_SLICE2_CUR\": \"0b00\",\n        \"CH1_TDRV_SLICE2_SEL\": \"0b00\",\n        \"CH1_TDRV_SLICE3_CUR\": \"0b00\",\n        \"CH1_TDRV_SLICE3_SEL\": \"0b00\",\n        \"CH1_TDRV_SLICE4_CUR\": \"0b00\",\n        \"CH1_TDRV_SLICE4_SEL\": \"0b00\",\n        \"CH1_TDRV_SLICE5_CUR\": \"0b00\",\n        \"CH1_TDRV_SLICE5_SEL\": \"0b00\",\n        \"CH1_TPWDNB\": \"0b0\",\n        \"CH1_TXAMPLITUDE\": \"0d1300\",\n        \"CH1_TXDEPOST\": \"DISABLED\",\n        \"CH1_TXDEPRE\": \"DISABLED\",\n        \"CH1_TX_CM_SEL\": \"0b00\",\n        \"CH1_TX_DIV11_SEL\": \"0b0\",\n        \"CH1_TX_GEAR_BYPASS\": \"0b0\",\n        \"CH1_TX_GEAR_MODE\": \"0b0\",\n        \"CH1_TX_POST_SIGN\": \"0b0\",\n        \"CH1_TX_PRE_SIGN\": \"0b0\",\n        \"CH1_UC_MODE\": \"0b0\",\n        \"CH1_UDF_COMMA_A\": \"0b0000000000\",\n        \"CH1_UDF_COMMA_B\": \"0b0000000000\",\n        \"CH1_UDF_COMMA_MASK\": \"0b0000000000\",\n        \"CH1_WA_BYPASS\": \"0b0\",\n        \"CH1_WA_MODE\": \"0b0\",\n        \"D_BITCLK_FROM_ND_EN\": \"0b0\",\n        \"D_BITCLK_LOCAL_EN\": \"0b0\",\n        \"D_BITCLK_ND_EN\": \"0b0\",\n        \"D_BUS8BIT_SEL\": \"0b0\",\n        \"D_CDR_LOL_SET\": \"0b00\",\n        \"D_CMUSETBIASI\": \"0b00\",\n        \"D_CMUSETI4CPP\": \"0b0000\",\n        \"D_CMUSETI4CPZ\": \"0b0000\",\n        \"D_CMUSETI4VCO\": \"0b00\",\n        \"D_CMUSETICP4P\": \"0b00\",\n        \"D_CMUSETICP4Z\": \"0b000\",\n        \"D_CMUSETINITVCT\": \"0b00\",\n        \"D_CMUSETISCL4VCO\": \"0b000\",\n        \"D_CMUSETP1GM\": \"0b000\",\n        \"D_CMUSETP2AGM\": \"0b000\",\n        \"D_CMUSETZGM\": \"0b000\",\n        \"D_DCO_CALIB_TIME_SEL\": \"0b00\",\n        \"D_HIGH_MARK\": \"0b0000\",\n        \"D_IB_PWDNB\": \"0b0\",\n        \"D_ISETLOS\": \"0b00000000\",\n        \"D_LOW_MARK\": \"0b0000\",\n        \"D_MACROPDB\": \"0b0\",\n        \"D_PD_ISET\": \"0b00\",\n        \"D_PLL_LOL_SET\": \"0b00\",\n        \"D_REFCK_MODE\": \"0b000\",\n        \"D_REQ_ISET\": \"0b000\",\n        \"D_RG_EN\": \"0b0\",\n        \"D_RG_SET\": \"0b00\",\n        \"D_RX_MAX_RATE\": \"2.5\",\n        \"D_SETICONST_AUX\": \"0b00\",\n        \"D_SETICONST_CH\": \"0b00\",\n        \"D_SETIRPOLY_AUX\": \"0b00\",\n        \"D_SETIRPOLY_CH\": \"0b00\",\n        \"D_SETPLLRC\": \"0b000000\",\n        \"D_SYNC_LOCAL_EN\": \"0b0\",\n        \"D_SYNC_ND_EN\": \"0b0\",\n        \"D_TXPLL_PWDNB\": \"0b0\",\n        \"D_TX_MAX_RATE\": \"2.5\",\n        \"D_TX_VCO_CK_DIV\": \"0b000\",\n        \"D_XGE_MODE\": \"0b0\"\n      },\n      \"ports\": {\n        \"CH0_HDINP\": {\n          \"direction\": \"input\",\n          \"bits\": [ 2 ]\n        },\n        \"CH1_HDINP\": {\n          \"direction\": \"input\",\n          \"bits\": [ 3 ]\n        },\n        \"CH0_HDINN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 4 ]\n        },\n        \"CH1_HDINN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 5 ]\n        },\n        \"D_TXBIT_CLKP_FROM_ND\": {\n          \"direction\": \"input\",\n          \"bits\": [ 6 ]\n        },\n        \"D_TXBIT_CLKN_FROM_ND\": {\n          \"direction\": \"input\",\n          \"bits\": [ 7 ]\n        },\n        \"D_SYNC_ND\": {\n          \"direction\": \"input\",\n          \"bits\": [ 8 ]\n        },\n        \"D_TXPLL_LOL_FROM_ND\": {\n          \"direction\": \"input\",\n          \"bits\": [ 9 ]\n        },\n        \"CH0_RX_REFCLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 10 ]\n        },\n        \"CH1_RX_REFCLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 11 ]\n        },\n        \"CH0_FF_RXI_CLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 12 ]\n        },\n        \"CH1_FF_RXI_CLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 13 ]\n        },\n        \"CH0_FF_TXI_CLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 14 ]\n        },\n        \"CH1_FF_TXI_CLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 15 ]\n        },\n        \"CH0_FF_EBRD_CLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 16 ]\n        },\n        \"CH1_FF_EBRD_CLK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 17 ]\n        },\n        \"CH0_FF_TX_D_0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 18 ]\n        },\n        \"CH1_FF_TX_D_0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 19 ]\n        },\n        \"CH0_FF_TX_D_1\": {\n          \"direction\": \"input\",\n          \"bits\": [ 20 ]\n        },\n        \"CH1_FF_TX_D_1\": {\n          \"direction\": \"input\",\n          \"bits\": [ 21 ]\n        },\n        \"CH0_FF_TX_D_2\": {\n          \"direction\": \"input\",\n          \"bits\": [ 22 ]\n        },\n        \"CH1_FF_TX_D_2\": {\n          \"direction\": \"input\",\n          \"bits\": [ 23 ]\n        },\n        \"CH0_FF_TX_D_3\": {\n          \"direction\": \"input\",\n          \"bits\": [ 24 ]\n        },\n        \"CH1_FF_TX_D_3\": {\n          \"direction\": \"input\",\n          \"bits\": [ 25 ]\n        },\n        \"CH0_FF_TX_D_4\": {\n          \"direction\": \"input\",\n          \"bits\": [ 26 ]\n        },\n        \"CH1_FF_TX_D_4\": {\n          \"direction\": \"input\",\n          \"bits\": [ 27 ]\n        },\n        \"CH0_FF_TX_D_5\": {\n          \"direction\": \"input\",\n          \"bits\": [ 28 ]\n        },\n        \"CH1_FF_TX_D_5\": {\n          \"direction\": \"input\",\n          \"bits\": [ 29 ]\n        },\n        \"CH0_FF_TX_D_6\": {\n          \"direction\": \"input\",\n          \"bits\": [ 30 ]\n        },\n        \"CH1_FF_TX_D_6\": {\n          \"direction\": \"input\",\n          \"bits\": [ 31 ]\n        },\n        \"CH0_FF_TX_D_7\": {\n          \"direction\": \"input\",\n          \"bits\": [ 32 ]\n        },\n        \"CH1_FF_TX_D_7\": {\n          \"direction\": \"input\",\n          \"bits\": [ 33 ]\n        },\n        \"CH0_FF_TX_D_8\": {\n          \"direction\": \"input\",\n          \"bits\": [ 34 ]\n        },\n        \"CH1_FF_TX_D_8\": {\n          \"direction\": \"input\",\n          \"bits\": [ 35 ]\n        },\n        \"CH0_FF_TX_D_9\": {\n          \"direction\": \"input\",\n          \"bits\": [ 36 ]\n        },\n        \"CH1_FF_TX_D_9\": {\n          \"direction\": \"input\",\n          \"bits\": [ 37 ]\n        },\n        \"CH0_FF_TX_D_10\": {\n          \"direction\": \"input\",\n          \"bits\": [ 38 ]\n        },\n        \"CH1_FF_TX_D_10\": {\n          \"direction\": \"input\",\n          \"bits\": [ 39 ]\n        },\n        \"CH0_FF_TX_D_11\": {\n          \"direction\": \"input\",\n          \"bits\": [ 40 ]\n        },\n        \"CH1_FF_TX_D_11\": {\n          \"direction\": \"input\",\n          \"bits\": [ 41 ]\n        },\n        \"CH0_FF_TX_D_12\": {\n          \"direction\": \"input\",\n          \"bits\": [ 42 ]\n        },\n        \"CH1_FF_TX_D_12\": {\n          \"direction\": \"input\",\n          \"bits\": [ 43 ]\n        },\n        \"CH0_FF_TX_D_13\": {\n          \"direction\": \"input\",\n          \"bits\": [ 44 ]\n        },\n        \"CH1_FF_TX_D_13\": {\n          \"direction\": \"input\",\n          \"bits\": [ 45 ]\n        },\n        \"CH0_FF_TX_D_14\": {\n          \"direction\": \"input\",\n          \"bits\": [ 46 ]\n        },\n        \"CH1_FF_TX_D_14\": {\n          \"direction\": \"input\",\n          \"bits\": [ 47 ]\n        },\n        \"CH0_FF_TX_D_15\": {\n          \"direction\": \"input\",\n          \"bits\": [ 48 ]\n        },\n        \"CH1_FF_TX_D_15\": {\n          \"direction\": \"input\",\n          \"bits\": [ 49 ]\n        },\n        \"CH0_FF_TX_D_16\": {\n          \"direction\": \"input\",\n          \"bits\": [ 50 ]\n        },\n        \"CH1_FF_TX_D_16\": {\n          \"direction\": \"input\",\n          \"bits\": [ 51 ]\n        },\n        \"CH0_FF_TX_D_17\": {\n          \"direction\": \"input\",\n          \"bits\": [ 52 ]\n        },\n        \"CH1_FF_TX_D_17\": {\n          \"direction\": \"input\",\n          \"bits\": [ 53 ]\n        },\n        \"CH0_FF_TX_D_18\": {\n          \"direction\": \"input\",\n          \"bits\": [ 54 ]\n        },\n        \"CH1_FF_TX_D_18\": {\n          \"direction\": \"input\",\n          \"bits\": [ 55 ]\n        },\n        \"CH0_FF_TX_D_19\": {\n          \"direction\": \"input\",\n          \"bits\": [ 56 ]\n        },\n        \"CH1_FF_TX_D_19\": {\n          \"direction\": \"input\",\n          \"bits\": [ 57 ]\n        },\n        \"CH0_FF_TX_D_20\": {\n          \"direction\": \"input\",\n          \"bits\": [ 58 ]\n        },\n        \"CH1_FF_TX_D_20\": {\n          \"direction\": \"input\",\n          \"bits\": [ 59 ]\n        },\n        \"CH0_FF_TX_D_21\": {\n          \"direction\": \"input\",\n          \"bits\": [ 60 ]\n        },\n        \"CH1_FF_TX_D_21\": {\n          \"direction\": \"input\",\n          \"bits\": [ 61 ]\n        },\n        \"CH0_FF_TX_D_22\": {\n          \"direction\": \"input\",\n          \"bits\": [ 62 ]\n        },\n        \"CH1_FF_TX_D_22\": {\n          \"direction\": \"input\",\n          \"bits\": [ 63 ]\n        },\n        \"CH0_FF_TX_D_23\": {\n          \"direction\": \"input\",\n          \"bits\": [ 64 ]\n        },\n        \"CH1_FF_TX_D_23\": {\n          \"direction\": \"input\",\n          \"bits\": [ 65 ]\n        },\n        \"CH0_FFC_EI_EN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 66 ]\n        },\n        \"CH1_FFC_EI_EN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 67 ]\n        },\n        \"CH0_FFC_PCIE_DET_EN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 68 ]\n        },\n        \"CH1_FFC_PCIE_DET_EN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 69 ]\n        },\n        \"CH0_FFC_PCIE_CT\": {\n          \"direction\": \"input\",\n          \"bits\": [ 70 ]\n        },\n        \"CH1_FFC_PCIE_CT\": {\n          \"direction\": \"input\",\n          \"bits\": [ 71 ]\n        },\n        \"CH0_FFC_SB_INV_RX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 72 ]\n        },\n        \"CH1_FFC_SB_INV_RX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 73 ]\n        },\n        \"CH0_FFC_ENABLE_CGALIGN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 74 ]\n        },\n        \"CH1_FFC_ENABLE_CGALIGN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 75 ]\n        },\n        \"CH0_FFC_SIGNAL_DETECT\": {\n          \"direction\": \"input\",\n          \"bits\": [ 76 ]\n        },\n        \"CH1_FFC_SIGNAL_DETECT\": {\n          \"direction\": \"input\",\n          \"bits\": [ 77 ]\n        },\n        \"CH0_FFC_FB_LOOPBACK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 78 ]\n        },\n        \"CH1_FFC_FB_LOOPBACK\": {\n          \"direction\": \"input\",\n          \"bits\": [ 79 ]\n        },\n        \"CH0_FFC_SB_PFIFO_LP\": {\n          \"direction\": \"input\",\n          \"bits\": [ 80 ]\n        },\n        \"CH1_FFC_SB_PFIFO_LP\": {\n          \"direction\": \"input\",\n          \"bits\": [ 81 ]\n        },\n        \"CH0_FFC_PFIFO_CLR\": {\n          \"direction\": \"input\",\n          \"bits\": [ 82 ]\n        },\n        \"CH1_FFC_PFIFO_CLR\": {\n          \"direction\": \"input\",\n          \"bits\": [ 83 ]\n        },\n        \"CH0_FFC_RATE_MODE_RX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 84 ]\n        },\n        \"CH1_FFC_RATE_MODE_RX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 85 ]\n        },\n        \"CH0_FFC_RATE_MODE_TX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 86 ]\n        },\n        \"CH1_FFC_RATE_MODE_TX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 87 ]\n        },\n        \"CH0_FFC_DIV11_MODE_RX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 88 ]\n        },\n        \"CH1_FFC_DIV11_MODE_RX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 89 ]\n        },\n        \"CH0_FFC_RX_GEAR_MODE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 90 ]\n        },\n        \"CH1_FFC_RX_GEAR_MODE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 91 ]\n        },\n        \"CH0_FFC_TX_GEAR_MODE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 92 ]\n        },\n        \"CH1_FFC_TX_GEAR_MODE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 93 ]\n        },\n        \"CH0_FFC_DIV11_MODE_TX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 94 ]\n        },\n        \"CH1_FFC_DIV11_MODE_TX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 95 ]\n        },\n        \"CH0_FFC_LDR_CORE2TX_EN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 96 ]\n        },\n        \"CH1_FFC_LDR_CORE2TX_EN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 97 ]\n        },\n        \"CH0_FFC_LANE_TX_RST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 98 ]\n        },\n        \"CH1_FFC_LANE_TX_RST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 99 ]\n        },\n        \"CH0_FFC_LANE_RX_RST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 100 ]\n        },\n        \"CH1_FFC_LANE_RX_RST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 101 ]\n        },\n        \"CH0_FFC_RRST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 102 ]\n        },\n        \"CH1_FFC_RRST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 103 ]\n        },\n        \"CH0_FFC_TXPWDNB\": {\n          \"direction\": \"input\",\n          \"bits\": [ 104 ]\n        },\n        \"CH1_FFC_TXPWDNB\": {\n          \"direction\": \"input\",\n          \"bits\": [ 105 ]\n        },\n        \"CH0_FFC_RXPWDNB\": {\n          \"direction\": \"input\",\n          \"bits\": [ 106 ]\n        },\n        \"CH1_FFC_RXPWDNB\": {\n          \"direction\": \"input\",\n          \"bits\": [ 107 ]\n        },\n        \"CH0_LDR_CORE2TX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 108 ]\n        },\n        \"CH1_LDR_CORE2TX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 109 ]\n        },\n        \"D_SCIWDATA0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 110 ]\n        },\n        \"D_SCIWDATA1\": {\n          \"direction\": \"input\",\n          \"bits\": [ 111 ]\n        },\n        \"D_SCIWDATA2\": {\n          \"direction\": \"input\",\n          \"bits\": [ 112 ]\n        },\n        \"D_SCIWDATA3\": {\n          \"direction\": \"input\",\n          \"bits\": [ 113 ]\n        },\n        \"D_SCIWDATA4\": {\n          \"direction\": \"input\",\n          \"bits\": [ 114 ]\n        },\n        \"D_SCIWDATA5\": {\n          \"direction\": \"input\",\n          \"bits\": [ 115 ]\n        },\n        \"D_SCIWDATA6\": {\n          \"direction\": \"input\",\n          \"bits\": [ 116 ]\n        },\n        \"D_SCIWDATA7\": {\n          \"direction\": \"input\",\n          \"bits\": [ 117 ]\n        },\n        \"D_SCIADDR0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 118 ]\n        },\n        \"D_SCIADDR1\": {\n          \"direction\": \"input\",\n          \"bits\": [ 119 ]\n        },\n        \"D_SCIADDR2\": {\n          \"direction\": \"input\",\n          \"bits\": [ 120 ]\n        },\n        \"D_SCIADDR3\": {\n          \"direction\": \"input\",\n          \"bits\": [ 121 ]\n        },\n        \"D_SCIADDR4\": {\n          \"direction\": \"input\",\n          \"bits\": [ 122 ]\n        },\n        \"D_SCIADDR5\": {\n          \"direction\": \"input\",\n          \"bits\": [ 123 ]\n        },\n        \"D_SCIENAUX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 124 ]\n        },\n        \"D_SCISELAUX\": {\n          \"direction\": \"input\",\n          \"bits\": [ 125 ]\n        },\n        \"CH0_SCIEN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 126 ]\n        },\n        \"CH1_SCIEN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 127 ]\n        },\n        \"CH0_SCISEL\": {\n          \"direction\": \"input\",\n          \"bits\": [ 128 ]\n        },\n        \"CH1_SCISEL\": {\n          \"direction\": \"input\",\n          \"bits\": [ 129 ]\n        },\n        \"D_SCIRD\": {\n          \"direction\": \"input\",\n          \"bits\": [ 130 ]\n        },\n        \"D_SCIWSTN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 131 ]\n        },\n        \"D_CYAWSTN\": {\n          \"direction\": \"input\",\n          \"bits\": [ 132 ]\n        },\n        \"D_FFC_SYNC_TOGGLE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 133 ]\n        },\n        \"D_FFC_DUAL_RST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 134 ]\n        },\n        \"D_FFC_MACRO_RST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 135 ]\n        },\n        \"D_FFC_MACROPDB\": {\n          \"direction\": \"input\",\n          \"bits\": [ 136 ]\n        },\n        \"D_FFC_TRST\": {\n          \"direction\": \"input\",\n          \"bits\": [ 137 ]\n        },\n        \"CH0_FFC_CDR_EN_BITSLIP\": {\n          \"direction\": \"input\",\n          \"bits\": [ 138 ]\n        },\n        \"CH1_FFC_CDR_EN_BITSLIP\": {\n          \"direction\": \"input\",\n          \"bits\": [ 139 ]\n        },\n        \"D_SCAN_ENABLE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 140 ]\n        },\n        \"D_SCAN_IN_0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 141 ]\n        },\n        \"D_SCAN_IN_1\": {\n          \"direction\": \"input\",\n          \"bits\": [ 142 ]\n        },\n        \"D_SCAN_IN_2\": {\n          \"direction\": \"input\",\n          \"bits\": [ 143 ]\n        },\n        \"D_SCAN_IN_3\": {\n          \"direction\": \"input\",\n          \"bits\": [ 144 ]\n        },\n        \"D_SCAN_IN_4\": {\n          \"direction\": \"input\",\n          \"bits\": [ 145 ]\n        },\n        \"D_SCAN_IN_5\": {\n          \"direction\": \"input\",\n          \"bits\": [ 146 ]\n        },\n        \"D_SCAN_IN_6\": {\n          \"direction\": \"input\",\n          \"bits\": [ 147 ]\n        },\n        \"D_SCAN_IN_7\": {\n          \"direction\": \"input\",\n          \"bits\": [ 148 ]\n        },\n        \"D_SCAN_MODE\": {\n          \"direction\": \"input\",\n          \"bits\": [ 149 ]\n        },\n        \"D_SCAN_RESET\": {\n          \"direction\": \"input\",\n          \"bits\": [ 150 ]\n        },\n        \"D_CIN0\": {\n          \"direction\": \"input\",\n          \"bits\": [ 151 ]\n        },\n        \"D_CIN1\": {\n          \"direction\": \"input\",\n          \"bits\": [ 152 ]\n        },\n        \"D_CIN2\": {\n          \"direction\": \"input\",\n          \"bits\": [ 153 ]\n        },\n        \"D_CIN3\": {\n          \"direction\": \"input\",\n          \"bits\": [ 154 ]\n        },\n        \"D_CIN4\": {\n          \"direction\": \"input\",\n          \"bits\": [ 155 ]\n        },\n        \"D_CIN5\": {\n          \"direction\": \"input\",\n          \"bits\": [ 156 ]\n        },\n        \"D_CIN6\": {\n          \"direction\": \"input\",\n          \"bits\": [ 157 ]\n        },\n        \"D_CIN7\": {\n          \"direction\": \"input\",\n          \"bits\": [ 158 ]\n        },\n        \"D_CIN8\": {\n          \"direction\": \"input\",\n          \"bits\": [ 159 ]\n        },\n        \"D_CIN9\": {\n          \"direction\": \"input\",\n          \"bits\": [ 160 ]\n        },\n        \"D_CIN10\": {\n          \"direction\": \"input\",\n          \"bits\": [ 161 ]\n        },\n        \"D_CIN11\": {\n          \"direction\": \"input\",\n          \"bits\": [ 162 ]\n        },\n        \"CH0_HDOUTP\": {\n          \"direction\": \"output\",\n          \"bits\": [ 163 ]\n        },\n        \"CH1_HDOUTP\": {\n          \"direction\": \"output\",\n          \"bits\": [ 164 ]\n        },\n        \"CH0_HDOUTN\": {\n          \"direction\": \"output\",\n          \"bits\": [ 165 ]\n        },\n        \"CH1_HDOUTN\": {\n          \"direction\": \"output\",\n          \"bits\": [ 166 ]\n        },\n        \"D_TXBIT_CLKP_TO_ND\": {\n          \"direction\": \"output\",\n          \"bits\": [ 167 ]\n        },\n        \"D_TXBIT_CLKN_TO_ND\": {\n          \"direction\": \"output\",\n          \"bits\": [ 168 ]\n        },\n        \"D_SYNC_PULSE2ND\": {\n          \"direction\": \"output\",\n          \"bits\": [ 169 ]\n        },\n        \"D_TXPLL_LOL_TO_ND\": {\n          \"direction\": \"output\",\n          \"bits\": [ 170 ]\n        },\n        \"CH0_FF_RX_F_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 171 ]\n        },\n        \"CH1_FF_RX_F_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 172 ]\n        },\n        \"CH0_FF_RX_H_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 173 ]\n        },\n        \"CH1_FF_RX_H_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 174 ]\n        },\n        \"CH0_FF_TX_F_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 175 ]\n        },\n        \"CH1_FF_TX_F_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 176 ]\n        },\n        \"CH0_FF_TX_H_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 177 ]\n        },\n        \"CH1_FF_TX_H_CLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 178 ]\n        },\n        \"CH0_FF_RX_PCLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 179 ]\n        },\n        \"CH1_FF_RX_PCLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 180 ]\n        },\n        \"CH0_FF_TX_PCLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 181 ]\n        },\n        \"CH1_FF_TX_PCLK\": {\n          \"direction\": \"output\",\n          \"bits\": [ 182 ]\n        },\n        \"CH0_FF_RX_D_0\": {\n          \"direction\": \"output\",\n          \"bits\": [ 183 ]\n        },\n        \"CH1_FF_RX_D_0\": {\n          \"direction\": \"output\",\n          \"bits\": [ 184 ]\n        },\n        \"CH0_FF_RX_D_1\": {\n          \"direction\": \"output\",\n          \"bits\": [ 185 ]\n        },\n        \"CH1_FF_RX_D_1\": {\n          \"direction\": \"output\",\n          \"bits\": [ 186 ]\n        },\n        \"CH0_FF_RX_D_2\": {\n          \"direction\": \"output\",\n          \"bits\": [ 187 ]\n        },\n        \"CH1_FF_RX_D_2\": {\n          \"direction\": \"output\",\n          \"bits\": [ 188 ]\n        },\n        \"CH0_FF_RX_D_3\": {\n          \"direction\": \"output\",\n          \"bits\": [ 189 ]\n        },\n        \"CH1_FF_RX_D_3\": {\n          \"direction\": \"output\",\n          \"bits\": [ 190 ]\n        },\n        \"CH0_FF_RX_D_4\": {\n          \"direction\": \"output\",\n          \"bits\": [ 191 ]\n        },\n        \"CH1_FF_RX_D_4\": {\n          \"direction\": \"output\",\n          \"bits\": [ 192 ]\n        },\n        \"CH0_FF_RX_D_5\": {\n          \"direction\": \"output\",\n          \"bits\": [ 193 ]\n        },\n        \"CH1_FF_RX_D_5\": {\n          \"direction\": \"output\",\n          \"bits\": [ 194 ]\n        },\n        \"CH0_FF_RX_D_6\": {\n          \"direction\": \"output\",\n          \"bits\": [ 195 ]\n        },\n        \"CH1_FF_RX_D_6\": {\n          \"direction\": \"output\",\n          \"bits\": [ 196 ]\n        },\n        \"CH0_FF_RX_D_7\": {\n          \"direction\": \"output\",\n          \"bits\": [ 197 ]\n        },\n        \"CH1_FF_RX_D_7\": {\n          \"direction\": \"output\",\n          \"bits\": [ 198 ]\n        },\n        \"CH0_FF_RX_D_8\": {\n          \"direction\": \"output\",\n          \"bits\": [ 199 ]\n        },\n        \"CH1_FF_RX_D_8\": {\n          \"direction\": \"output\",\n          \"bits\": [ 200 ]\n        },\n        \"CH0_FF_RX_D_9\": {\n          \"direction\": \"output\",\n          \"bits\": [ 201 ]\n        },\n        \"CH1_FF_RX_D_9\": {\n          \"direction\": \"output\",\n          \"bits\": [ 202 ]\n        },\n        \"CH0_FF_RX_D_10\": {\n          \"direction\": \"output\",\n          \"bits\": [ 203 ]\n        },\n        \"CH1_FF_RX_D_10\": {\n          \"direction\": \"output\",\n          \"bits\": [ 204 ]\n        },\n        \"CH0_FF_RX_D_11\": {\n          \"direction\": \"output\",\n          \"bits\": [ 205 ]\n        },\n        \"CH1_FF_RX_D_11\": {\n          \"direction\": \"output\",\n          \"bits\": [ 206 ]\n        },\n        \"CH0_FF_RX_D_12\": {\n          \"direction\": \"output\",\n          \"bits\": [ 207 ]\n        },\n        \"CH1_FF_RX_D_12\": {\n          \"direction\": \"output\",\n          \"bits\": [ 208 ]\n        },\n        \"CH0_FF_RX_D_13\": {\n          \"direction\": \"output\",\n          \"bits\": [ 209 ]\n        },\n        \"CH1_FF_RX_D_13\": {\n          \"direction\": \"output\",\n          \"bits\": [ 210 ]\n        },\n        \"CH0_FF_RX_D_14\": {\n          \"direction\": \"output\",\n          \"bits\": [ 211 ]\n        },\n        \"CH1_FF_RX_D_14\": {\n          \"direction\": \"output\",\n          \"bits\": [ 212 ]\n        },\n        \"CH0_FF_RX_D_15\": {\n          \"direction\": \"output\",\n          \"bits\": [ 213 ]\n        },\n        \"CH1_FF_RX_D_15\": {\n          \"direction\": \"output\",\n          \"bits\": [ 214 ]\n        },\n        \"CH0_FF_RX_D_16\": {\n          \"direction\": \"output\",\n          \"bits\": [ 215 ]\n        },\n        \"CH1_FF_RX_D_16\": {\n          \"direction\": \"output\",\n          \"bits\": [ 216 ]\n        },\n        \"CH0_FF_RX_D_17\": {\n          \"direction\": \"output\",\n          \"bits\": [ 217 ]\n        },\n        \"CH1_FF_RX_D_17\": {\n          \"direction\": \"output\",\n          \"bits\": [ 218 ]\n        },\n        \"CH0_FF_RX_D_18\": {\n          \"direction\": \"output\",\n          \"bits\": [ 219 ]\n        },\n        \"CH1_FF_RX_D_18\": {\n          \"direction\": \"output\",\n          \"bits\": [ 220 ]\n        },\n        \"CH0_FF_RX_D_19\": {\n          \"direction\": \"output\",\n          \"bits\": [ 221 ]\n        },\n        \"CH1_FF_RX_D_19\": {\n          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\"1\", \"1\", \"1\", \"1\", \"1\", \"1\", \"1\" ],\n          \"attributes\": {\n            \"hdlname\": \"vgatestsrc_instance white\",\n            \"src\": \"ULX3S_25F.v:43.5-47.23|vgatestsrc.v:63.17-63.22\"\n          }\n        },\n        \"vgatestsrc_instance.yedge\": {\n          \"hide_name\": 0,\n          \"bits\": [ \"0\", 1448, 1464, 1462, 1460, 1458, 1456, 1454, 1452, 1450, 1446, 1444 ],\n          \"attributes\": {\n            \"hdlname\": \"vgatestsrc_instance yedge\",\n            \"src\": \"ULX3S_25F.v:43.5-47.23|vgatestsrc.v:92.21-92.26\"\n          }\n        },\n        \"vgatestsrc_instance.yedge_TRELLIS_FF_Q_CE\": {\n          \"hide_name\": 0,\n          \"bits\": [ 1442 ],\n          \"attributes\": {\n          }\n        },\n        \"vgatestsrc_instance.yedge_TRELLIS_FF_Q_CE_LUT4_Z_A\": {\n          \"hide_name\": 0,\n          \"bits\": [ 1465, 1466, 1467, 236 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_map.v:109.23-109.24\"\n          }\n        },\n        \"vgatestsrc_instance.yedge_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_Z_1_A\": {\n          \"hide_name\": 0,\n          \"bits\": [ 1468, 1469, 1470, 1471 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_map.v:109.23-109.24\"\n          }\n        },\n        \"vgatestsrc_instance.yedge_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_Z_1_A_LUT4_Z_2_C\": {\n          \"hide_name\": 0,\n          \"bits\": [ 945, 1452, 1472, 1473 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_map.v:109.23-109.24\"\n          }\n        },\n        \"vgatestsrc_instance.yedge_TRELLIS_FF_Q_CE_LUT4_Z_A_LUT4_Z_1_A_LUT4_Z_3_D\": {\n          \"hide_name\": 0,\n          \"bits\": [ 946, 1450, 1474 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_map.v:109.23-109.24\"\n          }\n        },\n        \"vgatestsrc_instance.yedge_TRELLIS_FF_Q_CE_LUT4_Z_C\": {\n          \"hide_name\": 0,\n          \"bits\": [ 1652, 1487, 1653, 1484, 1654, 1481, 1655, 1478, 1656, 1475, 1657, 1467 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"ULX3S_25F.v:43.5-47.23|vgatestsrc.v:120.7-120.20|/usr/local/bin/../share/yosys/ecp5/arith_map.v:38.23-38.25\",\n            \"unused_bits\": \"0 2 4 6 8 10\"\n          }\n        },\n        \"vgatestsrc_instance.yedge_TRELLIS_FF_Q_CE_LUT4_Z_C_CCU2C_COUT_S0\": {\n          \"hide_name\": 0,\n          \"bits\": [ 1490, 1491, 1488, 1489, 1485, 1486, 1482, 1483, 1479, 1480, 1476, 1477 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"ULX3S_25F.v:43.5-47.23|vgatestsrc.v:120.7-120.20|/usr/local/bin/../share/yosys/ecp5/arith_map.v:34.26-34.27\",\n            \"unused_bits\": \"0 1 2 3 4 5 6 7 8 9 10 11\"\n          }\n        },\n        \"vgatestsrc_instance.yedge_TRELLIS_FF_Q_CE_LUT4_Z_C_CCU2C_COUT_S0_CCU2C_S0_COUT\": {\n          \"hide_name\": 0,\n          \"bits\": [ \"1\", 1658, 1487, 1653, 1484, 1654, 1481, 1655, 1478, 1656, 1475, 1657 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"ULX3S_25F.v:43.5-47.23|vgatestsrc.v:120.7-120.20|/usr/local/bin/../share/yosys/ecp5/arith_map.v:63.22-63.23\",\n            \"unused_bits\": \"1 3 5 7 9 11\"\n          }\n        },\n        \"vgatestsrc_instance.yedge_TRELLIS_FF_Q_DI\": {\n          \"hide_name\": 0,\n          \"bits\": [ 1447, 1463, 1461, 1459, 1457, 1455, 1453, 1451, 1449, 1445, 1443 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"ULX3S_25F.v:43.5-47.23|vgatestsrc.v:123.13-123.49|/usr/local/bin/../share/yosys/ecp5/arith_map.v:34.26-34.27\"\n          }\n        },\n        \"vgatestsrc_instance.yedge_TRELLIS_FF_Q_DI_CCU2C_S0_4_COUT\": {\n          \"hide_name\": 0,\n          \"bits\": [ 1496, 1659, 1495, 1660, 1494, 1661, 1492, 1662, 1493, 1663, 1497, 1664 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"ULX3S_25F.v:43.5-47.23|vgatestsrc.v:123.13-123.49|/usr/local/bin/../share/yosys/ecp5/arith_map.v:65.22-65.25\",\n            \"unused_bits\": \"1 3 5 7 9 10 11\"\n          }\n        },\n        \"vgatestsrc_instance.yedge_TRELLIS_FF_Q_DI_CCU2C_S0_4_S1\": {\n          \"hide_name\": 0,\n          \"bits\": [ 1463, 1665, 1459, 1666, 1455, 1667, 1451, 1668, 1445, 1669, 1498, 1670 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"ULX3S_25F.v:43.5-47.23|vgatestsrc.v:123.13-123.49|/usr/local/bin/../share/yosys/ecp5/arith_map.v:65.27-65.29\",\n            \"unused_bits\": \"1 3 5 7 9 10 11\"\n          }\n        },\n        \"vgatestsrc_instance.yedge_TRELLIS_FF_Q_DI_CCU2C_S0_COUT\": {\n          \"hide_name\": 0,\n          \"bits\": [ \"0\", 1448, 1496, 1671, 1495, 1672, 1494, 1673, 1492, 1674, 1493, 1675 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"ULX3S_25F.v:43.5-47.23|vgatestsrc.v:123.13-123.49|/usr/local/bin/../share/yosys/ecp5/arith_map.v:63.22-63.23\",\n            \"unused_bits\": \"3 5 7 9 11\"\n          }\n        },\n        \"vgatestsrc_instance.yline\": {\n          \"hide_name\": 0,\n          \"bits\": [ 1354, 1353, 1352, 1355 ],\n          \"attributes\": {\n            \"hdlname\": \"vgatestsrc_instance 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956, 957, 951, 952, 945, 946, 965, 966 ],\n          \"attributes\": {\n            \"hdlname\": \"vgatestsrc_instance ypos\",\n            \"src\": \"ULX3S_25F.v:43.5-47.23|vgatestsrc.v:92.15-92.19\"\n          }\n        },\n        \"vgatestsrc_instance.ypos_LUT4_A_1_Z\": {\n          \"hide_name\": 0,\n          \"bits\": [ 1504, 956, 951, 952 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_map.v:109.23-109.24\"\n          }\n        },\n        \"vgatestsrc_instance.ypos_LUT4_A_2_Z\": {\n          \"hide_name\": 0,\n          \"bits\": [ 956, 951, 952, 1505 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_map.v:109.23-109.24\"\n          }\n        },\n        \"vgatestsrc_instance.ypos_LUT4_B_Z\": {\n          \"hide_name\": 0,\n          \"bits\": [ 1506, 1507, 962, 1503 ],\n          \"attributes\": {\n            \"force_downto\": \"00000000000000000000000000000001\",\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_map.v:109.23-109.24\"\n          }\n        },\n        \"wifi_gpio0\": {\n          \"hide_name\": 0,\n          \"bits\": [ \"1\" ],\n          \"attributes\": {\n            \"src\": \"ULX3S_25F.v:6.9-6.19\"\n          }\n        }\n      }\n    },\n    \"USRMCLK\": {\n      \"attributes\": {\n        \"keep\": \"00000000000000000000000000000001\",\n        \"blackbox\": \"00000000000000000000000000000001\",\n        \"cells_not_processed\": \"00000000000000000000000000000001\",\n        \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_bb.v:160.1-164.10\"\n      },\n      \"ports\": {\n        \"USRMCLKI\": {\n          \"direction\": \"input\",\n          \"bits\": [ 2 ]\n        },\n        \"USRMCLKTS\": {\n          \"direction\": \"input\",\n          \"bits\": [ 3 ]\n        },\n        \"USRMCLKO\": {\n          \"direction\": \"output\",\n          \"bits\": [ 4 ]\n        }\n      },\n      \"cells\": {\n      },\n      \"netnames\": {\n        \"USRMCLKI\": {\n          \"hide_name\": 0,\n          \"bits\": [ 2 ],\n          \"attributes\": {\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_bb.v:161.8-161.16\"\n          }\n        },\n        \"USRMCLKO\": {\n          \"hide_name\": 0,\n          \"bits\": [ 4 ],\n          \"attributes\": {\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_bb.v:162.9-162.17\"\n          }\n        },\n        \"USRMCLKTS\": {\n          \"hide_name\": 0,\n          \"bits\": [ 3 ],\n          \"attributes\": {\n            \"src\": \"/usr/local/bin/../share/yosys/ecp5/cells_bb.v:161.18-161.27\"\n          }\n        }\n      }\n    }\n  }\n}\n"
  },
  {
    "path": "src/hdmi_test_pattern/ULX3S_25F.v",
    "content": "`default_nettype none\n\nmodule ULX3S_25F (\n\tinput clk_25mhz,\n        output [3:0] gpdi_dp, gpdi_dn,\n\toutput wifi_gpio0);\n\n  // Tie gpio0 high, this keeps the board from rebooting\n  assign wifi_gpio0 = 1'b1;\n\n  wire clk_25MHz, clk_250MHz;\n  clock clock_instance(\n      .clkin_25MHz(clk_25mhz),\n      .clk_25MHz(clk_25MHz),\n      .clk_250MHz(clk_250MHz)\n  );\n\n  wire [7:0] red, grn, blu;\n  wire [23:0] pixel;\n  assign red= pixel[23:16];\n  assign grn= pixel[15:8];\n  assign blu= pixel[7:0];\n\n  wire o_red;\n  wire o_grn;\n  wire o_blu;\n  wire o_rd, o_newline, o_newframe;\n\n  // A reset line that goes low after 16 ticks\n  reg [2:0] reset_cnt = 0;\n  wire reset = ~reset_cnt[2];\n  always @(posedge clk_25mhz)\n    if (reset) reset_cnt <= reset_cnt + 1;\n\n\n  llhdmi llhdmi_instance(\n    .i_tmdsclk(clk_250MHz), .i_pixclk(clk_25MHz),\n    .i_reset(reset), .i_red(red), .i_grn(grn), .i_blu(blu),\n    .o_rd(o_rd), .o_newline(o_newline), .o_newframe(o_newframe),\n    .o_red(o_red), .o_grn(o_grn), .o_blu(o_blu));\n\n  vgatestsrc #(.BITS_PER_COLOR(8))\n    vgatestsrc_instance(\n      .i_pixclk(clk_25MHz), .i_reset(reset),\n      .i_width(640), .i_height(480),\n      .i_rd(o_rd), .i_newline(o_newline), .i_newframe(o_newframe),\n      .o_pixel(pixel));\n\n  OBUFDS OBUFDS_red(.I(o_red), .O(gpdi_dp[2]), .OB(gpdi_dn[2]));\n  OBUFDS OBUFDS_grn(.I(o_grn), .O(gpdi_dp[1]), .OB(gpdi_dn[1]));\n  OBUFDS OBUFDS_blu(.I(o_blu), .O(gpdi_dp[0]), .OB(gpdi_dn[0]));\n  OBUFDS OBUFDS_clock(.I(clk_25MHz), .O(gpdi_dp[3]), .OB(gpdi_dn[3]));\n\nendmodule\n"
  },
  {
    "path": "src/hdmi_test_pattern/ULX3S_25F.ys",
    "content": "read_verilog ULX3S_25F.v\nread_verilog llhdmi.v\nread_verilog vgatestsrc.v\nread_verilog TMDS_encoder.v\nread_verilog clock.v\nread_verilog OBUFDS.v\nhierarchy -top ULX3S_25F\nsynth_ecp5 -json ULX3S_25F.json\n"
  },
  {
    "path": "src/hdmi_test_pattern/clock.v",
    "content": "module clock\n(\n  input clkin_25MHz,\n  output clk_125MHz,\n  output clk_250MHz,\n  output clk_25MHz,\n  output clk_83M333Hz,\n  output locked\n);\n    wire int_locked;\n\n    (* ICP_CURRENT=\"9\" *) (* LPF_RESISTOR=\"8\" *) (* MFG_ENABLE_FILTEROPAMP=\"1\" *) (* MFG_GMCREF_SEL=\"2\" *)\n    EHXPLLL\n    #(\n        .PLLRST_ENA(\"DISABLED\"),\n        .INTFB_WAKE(\"DISABLED\"),\n        .STDBY_ENABLE(\"DISABLED\"),\n        .DPHASE_SOURCE(\"DISABLED\"),\n        .CLKOS_FPHASE(0),\n        .CLKOP_FPHASE(0),\n        .CLKOS3_CPHASE(5),\n        .CLKOS2_CPHASE(0),\n        .CLKOS_CPHASE(1),\n        .CLKOP_CPHASE(3),\n        .OUTDIVIDER_MUXD(\"DIVD\"),\n        .OUTDIVIDER_MUXC(\"DIVC\"),\n        .OUTDIVIDER_MUXB(\"DIVB\"),\n        .OUTDIVIDER_MUXA(\"DIVA\"),\n        .CLKOS3_ENABLE(\"ENABLED\"),\n        .CLKOS2_ENABLE(\"ENABLED\"),\n        .CLKOS_ENABLE(\"ENABLED\"),\n        .CLKOP_ENABLE(\"ENABLED\"),\n        .CLKOS3_DIV(0),\n        .CLKOS2_DIV(20),\n        .CLKOS_DIV(2),\n        .CLKOP_DIV(4),\n        .CLKFB_DIV(5),\n        .CLKI_DIV(1),\n        .FEEDBK_PATH(\"CLKOP\")\n    )\n    pll_i\n    (\n        .CLKI(clkin_25MHz),\n        .CLKFB(clk_125MHz),\n        .CLKOP(clk_125MHz),\n        .CLKOS(clk_250MHz),\n        .CLKOS2(clk_25MHz), \n        .CLKOS3(clk_83M333Hz),\n        .RST(1'b0),\n        .STDBY(1'b0),\n        .PHASESEL0(1'b0),\n        .PHASESEL1(1'b0),\n        .PHASEDIR(1'b0),\n        .PHASESTEP(1'b0),\n        .PLLWAKESYNC(1'b0),\n        .ENCLKOP(1'b0),\n        .ENCLKOS(1'b0),\n        .ENCLKOS2(1'b0),\n        .ENCLKOS3(1'b0),\n        .LOCK(locked),\n        .INTLOCK(int_locked)\n    );\nendmodule\n\n"
  },
  {
    "path": "src/hdmi_test_pattern/icesugar_pro.lpf",
    "content": "BLOCK RESETPATHS;\nBLOCK ASYNCPATHS;\n## ULX3S v2.x.x and v3.0.x\n\n# The clock \"usb\" and \"gpdi\" sheet\n\n#ULX3S\n#LOCATE COMP \"clk_25mhz\" SITE \"G2\"; \n\n#i5-v6.0\nLOCATE COMP \"clk_25mhz\" SITE \"P6\";\nIOBUF  PORT \"clk_25mhz\" PULLMODE=NONE IO_TYPE=LVCMOS33;\nFREQUENCY PORT \"clk_25mhz\" 25 MHZ;\n\n\n#iCESugar-pro HDMI\nLOCATE COMP \"gpdi_dp[0]\" SITE \"G1\"; # Blue +\nLOCATE COMP \"gpdi_dn[0]\" SITE \"F1\"; # Blue -\nLOCATE COMP \"gpdi_dp[1]\" SITE \"J1\"; # Green +\nLOCATE COMP \"gpdi_dn[1]\" SITE \"H2\"; # Green -\nLOCATE COMP \"gpdi_dp[2]\" SITE \"L1\"; # Red +\nLOCATE COMP \"gpdi_dn[2]\" SITE \"K2\"; # Red -\nLOCATE COMP \"gpdi_dp[3]\" SITE \"E2\"; # Clock +\nLOCATE COMP \"gpdi_dn[3]\" SITE \"D3\"; # Clock -\n\nIOBUF PORT \"gpdi_dp[0]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dn[0]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dp[1]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dn[1]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dp[2]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dn[2]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dp[3]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dn[3]\" IO_TYPE=LVCMOS33 DRIVE=4;\n\nLOCATE COMP \"wifi_gpio0\" SITE \"A11\";\nIOBUF  PORT \"wifi_gpio0\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n\n"
  },
  {
    "path": "src/hdmi_test_pattern/llhdmi.v",
    "content": "`default_nettype none\n//\nmodule llhdmi(\n  i_tmdsclk, i_pixclk,\n  i_reset, i_red, i_grn, i_blu,\n  o_rd, o_newline, o_newframe,\n`ifdef VERILATOR\n  o_TMDS_red, o_TMDS_grn, o_TMDS_blu,\n`endif\n  o_red, o_grn, o_blu);\n\n  input wire i_tmdsclk;\t\t// TMDS clock\n  input wire i_pixclk;\t\t// Pixel clock, 10 times slower than i_tmdsclk\n  input wire i_reset;\t\t// Reset this module when strobed high\n  input wire [7:0] i_red;\t// Red green and blue colour values\n  input wire [7:0] i_grn;\t// for each pixel\n  input wire [7:0] i_blu;\n  output wire o_rd;\t\t// True when we can accept pixel data\n  output reg o_newline;\t\t// True on last pixel of each line\n  output reg o_newframe;\t// True on last pixel of each frame\n  output wire o_red;\t\t// Red TMDS pixel stream\n  output wire o_grn;\t\t// Green TMDS pixel stream\n  output wire o_blu;\t\t// Blue TMDS pixel stream\n`ifdef VERILATOR\n  output wire [9:0] o_TMDS_red, o_TMDS_grn, o_TMDS_blu;\n  assign o_TMDS_red= TMDS_red;\n  assign o_TMDS_grn= TMDS_grn;\n  assign o_TMDS_blu= TMDS_blu;\n`endif\n\n  reg [9:0] CounterX, CounterY;\n  reg hSync, vSync, DrawArea;\n\n  // Keep track of the current X/Y pixel position\n  always @(posedge i_pixclk)\n    if (i_reset)\n      CounterX <= 0;\n    else\n      CounterX <= (CounterX==799) ? 0 : CounterX+1;\n\n  always @(posedge i_pixclk)\n    if (i_reset)\n      CounterY <= 0;\n    else if (CounterX==799) begin\n      CounterY <= (CounterY==524) ? 0 : CounterY+1;\n    end\n\n  // Signal end of line, end of frame\n  always @(posedge i_pixclk) begin\n    o_newline  <= (CounterX==639) ? 1 : 0;\n    o_newframe <= (CounterX==639) && (CounterY==479) ? 1 : 0;\n  end\n\n  // Determine when we are in a drawable area\n  always @(posedge i_pixclk)\n    DrawArea <= (CounterX<640) && (CounterY<480);\n\n  assign o_rd= ~i_reset & DrawArea;\n\n  // Generate horizontal and vertical sync pulses\n  always @(posedge i_pixclk)\n    hSync <= (CounterX>=656) && (CounterX<752);\n\n  always @(posedge i_pixclk)\n    vSync <= (CounterY>=490) && (CounterY<492);\n\n  // Convert the 8-bit colours into 10-bit TMDS values\n  wire [9:0] TMDS_red, TMDS_grn, TMDS_blu;\n  TMDS_encoder encode_R(.clk(i_pixclk), .VD(i_red), .CD(2'b00),\n                                        .VDE(DrawArea), .TMDS(TMDS_red));\n  TMDS_encoder encode_G(.clk(i_pixclk), .VD(i_grn), .CD(2'b00),\n                                        .VDE(DrawArea), .TMDS(TMDS_grn));\n  TMDS_encoder encode_B(.clk(i_pixclk), .VD(i_blu), .CD({vSync,hSync}),\n                                        .VDE(DrawArea), .TMDS(TMDS_blu));\n\n  // Strobe the TMDS_shift_load once every 10 i_tmdsclks\n  // i.e. at the start of new pixel data\n  reg [3:0] TMDS_mod10=0;\n  reg TMDS_shift_load=0;\n  always @(posedge i_tmdsclk) begin\n    if (i_reset) begin\n      TMDS_mod10 <= 0;\n      TMDS_shift_load <= 0;\n    end else begin\n      TMDS_mod10 <= (TMDS_mod10==4'd9) ? 4'd0 : TMDS_mod10+4'd1;\n      TMDS_shift_load <= (TMDS_mod10==4'd9);\n    end\n  end\n\n  // Latch the TMDS colour values into three shift registers\n  // at the start of the pixel, then shift them one bit each i_tmdsclk.\n  // We will then output the LSB on each i_tmdsclk.\n  reg [9:0] TMDS_shift_red=0, TMDS_shift_grn=0, TMDS_shift_blu=0;\n  always @(posedge i_tmdsclk) begin\n    if (i_reset) begin\n      TMDS_shift_red <= 0;\n      TMDS_shift_grn <= 0;\n      TMDS_shift_blu <= 0;\n    end else begin\n      TMDS_shift_red <= TMDS_shift_load ? TMDS_red: {1'b0, TMDS_shift_red[9:1]};\n      TMDS_shift_grn <= TMDS_shift_load ? TMDS_grn: {1'b0, TMDS_shift_grn[9:1]};\n      TMDS_shift_blu <= TMDS_shift_load ? TMDS_blu: {1'b0, TMDS_shift_blu[9:1]};\n    end\n  end\n\n  // Finally output the LSB of each color bitstream\n  assign o_red= TMDS_shift_red[0];\n  assign o_grn= TMDS_shift_grn[0];\n  assign o_blu= TMDS_shift_blu[0];\n\nendmodule\n"
  },
  {
    "path": "src/hdmi_test_pattern/llhdmi_tb.cpp",
    "content": "#include <verilatedos.h>\n#include <stdio.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <string.h>\n#include <time.h>\n#include <sys/types.h>\n#include <signal.h>\n#include \"verilated.h\"\n#include \"Vllhdmi.h\"\n#include \"testb.h\"\n\nint\tmain(int argc, char **argv) {\n\tVerilated::commandArgs(argc, argv);\n\tTESTB<Vllhdmi>\t*tb\n\t\t= new TESTB<Vllhdmi>;\n\n\ttb->opentrace(\"llhdmi.vcd\");\n\ttb->m_core->i_red= 0xf0;\n\ttb->m_core->i_grn= 0x80;\n\ttb->m_core->i_blu= 0x20;\n\ttb->m_core->i_reset= 0;\n\n\tfor (unsigned clocks=0; clocks < 4400000; clocks++) {\n\t\ttb->tick();\n\t}\n\tprintf(\"\\n\\nSimulation complete\\n\");\n}\n"
  },
  {
    "path": "src/hdmi_test_pattern/pattern.v",
    "content": "`default_nettype none\n\nmodule pattern(input i_tmdsclk, i_pixclk, output red, grn, blu, o_rd,\n\to_TMDS_red, o_TMDS_grn, o_TMDS_blu);\n\n  wire [7:0] red, grn, blu;\n  wire [23:0] pixel;\n  assign red= pixel[23:16];\n  assign grn= pixel[15:8];\n  assign blu= pixel[7:0];\n\n/* verilator lint_off UNUSED */\n  wire o_red;\n  wire o_grn;\n  wire o_blu;\n  wire [9:0] o_TMDS_red, o_TMDS_grn, o_TMDS_blu;\n/* verilator lint_on UNUSED */\n  wire o_rd, o_newline, o_newframe;\n\n  // A reset line that goes low after 16 ticks\n  reg [2:0] reset_cnt = 0;\n  wire reset = ~reset_cnt[2];\n  always @(posedge i_pixclk)\n    if (reset) reset_cnt <= reset_cnt + 1;\n\n\n  llhdmi llhdmi_instance(\n    .i_tmdsclk(i_tmdsclk), .i_pixclk(i_pixclk),\n    .i_reset(reset), .i_red(red), .i_grn(grn), .i_blu(blu),\n    .o_rd(o_rd), .o_newline(o_newline), .o_newframe(o_newframe),\n    .o_TMDS_red(o_TMDS_red), .o_TMDS_grn(o_TMDS_grn), .o_TMDS_blu(o_TMDS_blu),\n    .o_red(o_red), .o_grn(o_grn), .o_blu(o_blu));\n\n  vgatestsrc #(.BITS_PER_COLOR(8))\n    vgatestsrc_instance(\n      .i_pixclk(i_pixclk), .i_reset(reset),\n      .i_width(640), .i_height(480),\n      .i_rd(o_rd), .i_newline(o_newline), .i_newframe(o_newframe),\n      .o_pixel(pixel));\n\nendmodule\n"
  },
  {
    "path": "src/hdmi_test_pattern/pattern_tb.cpp",
    "content": "#include <verilatedos.h>\n#include <stdio.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <string.h>\n#include <time.h>\n#include <sys/types.h>\n#include <signal.h>\n#include \"verilated.h\"\n#include \"Vpattern.h\"\n#include \"testb.h\"\n\nint\tmain(int argc, char **argv) {\n\tVerilated::commandArgs(argc, argv);\n\tTESTB<Vpattern>\t*tb\n\t\t= new TESTB<Vpattern>;\n\n\ttb->opentrace(\"pattern.vcd\");\n\tint oldpixclk=0;\n\n\tprintf(\"P3\\n640 480\\n255\\n\");\n\n\tfor (unsigned clocks=0; clocks < 4400000; clocks++) {\n\t\ttb->tick();\n\t\tif (tb->m_core->i_pixclk &&\n\t\t\t\t(tb->m_core->i_pixclk != oldpixclk)) {\n\t\t  if (tb->m_core->o_rd) {\n#if 1\n\t\t    printf(\"%d %d %d\\n\",\n\t\t\ttb->m_core->red,\n\t\t\ttb->m_core->grn,\n\t\t\ttb->m_core->blu);\n\t\t  }\n#else\n                    printf(\"%x %x %x => %x %x %x\\n\",\n                        tb->m_core->red,\n                        tb->m_core->grn,\n                        tb->m_core->blu,\n                        tb->m_core->o_TMDS_red,\n                        tb->m_core->o_TMDS_grn,\n                        tb->m_core->o_TMDS_blu);\n                  }\n#endif\n\t\t}\n\t\toldpixclk= tb->m_core->i_pixclk;\n\t}\n}\n"
  },
  {
    "path": "src/hdmi_test_pattern/testb.h",
    "content": "////////////////////////////////////////////////////////////////////////////////\n//\n// Filename: \ttestb.h\n//\n// Project:\tVerilog Tutorial Example file\n//\n// Purpose:\tA wrapper providing a common interface to a clocked FPGA core\n//\t\tbeing exercised by Verilator.\n//\n// Creator:\tDan Gisselquist, Ph.D.\n//\t\tGisselquist Technology, LLC\n//\n////////////////////////////////////////////////////////////////////////////////\n//\n// Written and distributed by Gisselquist Technology, LLC\n//\n// This program is hereby granted to the public domain.\n//\n// This program is distributed in the hope that it will be useful, but WITHOUT\n// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or\n// FITNESS FOR A PARTICULAR PURPOSE.\n//\n////////////////////////////////////////////////////////////////////////////////\n//\n//\n#ifndef\tTESTB_H\n#define\tTESTB_H\n\n#include <stdio.h>\n#include <stdint.h>\n#include <verilated_vcd_c.h>\n\n#define\tTBASSERT(TB,A) do { if (!(A)) { (TB).closetrace(); } assert(A); } while(0);\n\ntemplate <class VA>\tclass TESTB {\npublic:\n\tVA\t\t*m_core;\n\tVerilatedVcdC*\tm_trace;\n\tuint64_t\tm_tickcount;\n\n\tTESTB(void) : m_trace(NULL), m_tickcount(0l) {\n\t\tm_core = new VA;\n\t\tVerilated::traceEverOn(true);\n\t\tm_core->i_tmdsclk = 0;\n\t\teval(); // Get our initial values set properly.\n\t}\n\tvirtual ~TESTB(void) {\n\t\tclosetrace();\n\t\tdelete m_core;\n\t\tm_core = NULL;\n\t}\n\n\tvirtual\tvoid\topentrace(const char *vcdname) {\n\t\tif (!m_trace) {\n\t\t\tm_trace = new VerilatedVcdC;\n\t\t\tm_core->trace(m_trace, 99);\n\t\t\tm_trace->open(vcdname);\n\t\t}\n\t}\n\n\tvirtual\tvoid\tclosetrace(void) {\n\t\tif (m_trace) {\n\t\t\tm_trace->close();\n\t\t\tdelete m_trace;\n\t\t\tm_trace = NULL;\n\t\t}\n\t}\n\n\tvirtual\tvoid\teval(void) {\n\t\tm_core->eval();\n\t}\n\n\tvirtual\tvoid\ttick(void) {\n\t\tm_tickcount++;\n\n\t\t// Make sure we have our evaluations straight before the top\n\t\t// of the clock.  This is necessary since some of the \n\t\t// connection modules may have made changes, for which some\n\t\t// logic depends.  This forces that logic to be recalculated\n\t\t// before the top of the clock.\n\t\teval();\n\t\tif (m_trace) m_trace->dump((vluint64_t)(10*m_tickcount-2));\n\t\tm_core->i_pixclk = (((m_tickcount-1)%10)<5) ? 1 : 0;\n\t\tm_core->i_tmdsclk = 1;\n\t\teval();\n\t\tif (m_trace) m_trace->dump((vluint64_t)(10*m_tickcount));\n\t\tm_core->i_tmdsclk = 0;\n\t\teval();\n\t\tif (m_trace) {\n\t\t\tm_trace->dump((vluint64_t)(10*m_tickcount+5));\n\t\t\tm_trace->flush();\n\t\t}\n\t}\n\n\tunsigned long\ttickcount(void) {\n\t\treturn m_tickcount;\n\t}\n};\n\n#endif\n"
  },
  {
    "path": "src/hdmi_test_pattern/ulx3s_25f_ULX3S_25F.config",
    "content": ".device LFE5U-25F\n\n.comment Part: LFE5U-25F-6CABGA256\n\n.tile CIB_R10C1:CIB_LR\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 S1_V02N0701\n\n.tile CIB_R12C1:CIB_LR\narc: E1_H02E0001 S1_V02N0001\narc: N1_V02N0701 S1_V02N0701\n\n.tile CIB_R13C10:CIB_DSP\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E1_H02W0601\narc: W1_H02W0201 N1_V02S0201\narc: W3_H06W0103 V01N0101\n\n.tile CIB_R13C11:CIB_DSP\narc: E1_H02E0701 V06S0203\narc: N1_V02N0301 H06W0003\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 H06W0303\narc: S1_V02S0701 H06W0203\narc: S3_V06S0103 H06W0103\n\n.tile CIB_R13C12:CIB_DSP\narc: E1_H02E0501 V06S0303\narc: S1_V02S0701 H02E0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0301 V06S0003\narc: W1_H02W0601 N1_V01S0000\n\n.tile CIB_R13C13:CIB_DSP\narc: N1_V02N0501 H02E0501\n\n.tile CIB_R13C14:CIB_DSP\narc: W1_H02W0501 V06S0303\narc: W3_H06W0003 V06S0003\narc: W3_H06W0103 V06S0103\narc: W3_H06W0203 V06S0203\narc: W3_H06W0303 V06S0303\n\n.tile CIB_R13C15:CIB_DSP\narc: S1_V02S0301 V01N0101\n\n.tile CIB_R13C2:CIB_DSP\narc: N3_V06N0003 S3_V06N0003\n\n.tile CIB_R13C3:CIB_DSP\narc: N1_V02N0601 S1_V02N0301\n\n.tile CIB_R13C4:CIB_DSP\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 E1_H02W0601\n\n.tile CIB_R13C5:CIB_DSP\narc: E1_H02E0001 N3_V06S0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02W0601\narc: S1_V02S0001 V01N0001\n\n.tile CIB_R13C6:CIB_DSP\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 N1_V01S0000\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S1_V02N0601\n\n.tile CIB_R13C7:CIB_DSP\narc: E1_H02E0701 V06S0203\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 H06W0103\narc: N1_V02N0501 S1_V02N0501\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0601 N1_V01S0000\narc: W1_H02W0501 S1_V02N0501\n\n.tile CIB_R13C8:CIB_DSP\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 E3_H06W0303\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 H02E0701\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 E3_H06W0003\n\n.tile CIB_R13C9:CIB_DSP\narc: E1_H02E0201 V06S0103\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02W0201\narc: S1_V02S0001 V01N0001\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N1_V02S0701\n\n.tile CIB_R14C1:CIB_LR\narc: JA0 V02N0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0701 E3_H06W0203\narc: S3_V06S0303 E1_H01W0100\nenum: CIB.JB0MUX 0\n\n.tile CIB_R15C1:CIB_LR\narc: E1_H02E0201 E1_H01W0000\narc: N1_V02N0701 S1_V02N0601\n\n.tile CIB_R16C1:CIB_LR\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 E3_H06W0003\narc: S1_V02S0001 E3_H06W0003\n\n.tile CIB_R17C1:CIB_LR\narc: E1_H02E0001 V02S0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0701 E3_H06W0203\narc: N1_V02N0601 H06W0303\n\n.tile CIB_R18C1:CIB_LR\narc: E1_H02E0001 N1_V02S0001\n\n.tile CIB_R19C1:CIB_LR\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 S3_V06N0203\narc: N1_V02N0301 E3_H06W0003\n\n.tile CIB_R1C11:CIB\narc: E3_H06E0303 V06N0303\n\n.tile CIB_R1C17:CIB\narc: E3_H06E0303 W3_H06E0303\n\n.tile CIB_R1C23:CIB\narc: E3_H06E0003 W3_H06E0303\n\n.tile CIB_R1C29:CIB\narc: E3_H06E0103 W3_H06E0003\n\n.tile CIB_R1C2:CIB\narc: V01S0000 S3_V06N0103\n\n.tile CIB_R1C35:CIB\narc: E3_H06E0103 W3_H06E0103\n\n.tile CIB_R1C41:CIB\narc: E3_H06E0103 W3_H06E0103\n\n.tile CIB_R1C47:CIB\narc: E3_H06E0203 W3_H06E0103\n\n.tile CIB_R1C53:CIB\narc: JA0 H02W0701\narc: E1_H01E0101 W3_H06E0203\nenum: CIB.JB0MUX 0\n\n.tile CIB_R1C54:CIB\narc: W1_H02W0701 H01E0101\n\n.tile CIB_R20C1:CIB_LR\narc: JA0 H02W0701\narc: JA3 V02N0501\narc: V01S0100 N3_V06S0303\nenum: CIB.JB3MUX 0\nenum: CIB.JB0MUX 0\n\n.tile CIB_R21C1:CIB_LR\narc: N1_V02N0501 N1_V01S0100\n\n.tile CIB_R23C1:CIB_LR\narc: H00L0000 H02W0201\narc: JA0 H00L0000\narc: S1_V02S0501 E1_H02W0501\nenum: CIB.JB0MUX 0\n\n.tile CIB_R25C1:CIB_LR_S\narc: JA3 N1_V02S0501\narc: N3_V06N0203 S3_V06N0103\nenum: CIB.JB3MUX 0\n\n.tile CIB_R25C2:CIB_EBR\narc: N3_V06N0003 S3_V06N0003\n\n.tile CIB_R25C4:CIB_EBR\narc: N3_V06N0003 S3_V06N0003\n\n.tile CIB_R26C1:CIB_LR\narc: JA0 E1_H02W0701\nenum: CIB.JB0MUX 0\n\n.tile CIB_R2C1:CIB_LR\narc: S1_V02S0701 E1_H01W0100\n\n.tile CIB_R31C1:CIB_LR\narc: N3_V06N0103 S3_V06N0103\n\n.tile CIB_R37C1:CIB_LR_S\narc: N3_V06N0103 S3_V06N0003\n\n.tile CIB_R37C2:CIB_EBR\narc: N3_V06N0003 S3_V06N0303\n\n.tile CIB_R37C4:CIB_EBR\narc: N3_V06N0003 S3_V06N0303\n\n.tile CIB_R43C1:CIB_LR\narc: N3_V06N0003 S3_V06N0303\n\n.tile CIB_R49C1:CIB_LR_S\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0303 JF5\narc: N3_V06N0303 JF5\n\n.tile CIB_R49C2:CIB_PLL2\narc: H00R0100 V02S0701\narc: H01W0000 JF0\narc: JA3 V00B0000\narc: JA4 V00B0000\narc: JB1 V00B0000\narc: JB3 H00R0100\narc: JB4 V02S0701\narc: JC2 H00R0100\narc: JC3 H00R0100\narc: JC4 V02S0201\narc: JD2 V02S0201\narc: JD4 V00B0000\narc: JLSR0 V00B0000\narc: N3_V06N0203 JF4\narc: V00B0000 V02S0201\narc: PLLCSOUT_PLLREFCS CLK1_PLLREFCS\n\n.tile CIB_R49C3:CIB_PLL3\narc: JCLK0 V00B0000\narc: V00B0000 W1_H02E0601\nenum: CIB.JA3MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R49C42:VCIB_DCU0\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C43:VCIB_DCUA\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C44:VCIB_DCUB\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C45:VCIB_DCUC\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C46:VCIB_DCUD\nenum: CIB.JA1MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C47:VCIB_DCUF\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C48:VCIB_DCU3\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C49:VCIB_DCU2\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C4:CIB\narc: N3_V06N0303 H06E0303\n\n.tile CIB_R49C50:VCIB_DCUG\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C51:VCIB_DCUH\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C52:VCIB_DCUI\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C53:VCIB_DCU1\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\n\n.tile CIB_R49C69:CIB_PLL3\nenum: CIB.JA3MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R49C6:CIB_EFB0\nenum: CIB.JB3MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C7:CIB_EFB1\nenum: CIB.JA3MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JC3MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R4C1:CIB_LR\narc: JA3 N1_V02S0701\nenum: CIB.JB3MUX 0\n\n.tile CIB_R7C1:CIB_LR\narc: E1_H02E0301 E3_H06W0003\narc: S1_V02S0001 E3_H06W0003\n\n.tile CIB_R8C1:CIB_LR\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0701 E3_H06W0203\narc: JA3 E1_H02W0501\narc: S3_V06S0003 E3_H06W0003\nenum: CIB.JB3MUX 0\n\n.tile CIB_R9C1:CIB_LR\narc: E1_H02E0001 N1_V02S0001\n\n.tile MIB_R0C53:PIOT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.PULLMODE UP\nenum: PIOA.DRIVE 4\n\n.tile MIB_R0C69:BANKREF1\nenum: BANK.VCCIO 3V3\n\n.tile MIB_R13C21:DSP_SPINE_UL0\narc: G_VPTX0000 G_HPRX0000\n\n.tile MIB_R13C31:CMUX_UL_0\narc: G_DCS0CLK0 G_VPFN0000\narc: G_ULPCLK0 G_HPFE0000\narc: G_ULPCLK1 G_HPFE0600\n\n.tile MIB_R13C32:CMUX_UR_0\narc: G_DCS0CLK1 G_VPFN0000\narc: G_URPCLK0 G_HPFE0000\narc: G_URPCLK1 G_HPFE0600\n\n.tile MIB_R13C3:DSP_SPINE_UL1\narc: G_VPTX0000 G_HPRX0000\narc: G_VPTX0100 G_HPRX0100\nunknown: F2B0\nunknown: F3B0\nunknown: F5B0\nunknown: F11B0\nunknown: F13B0\n\n.tile MIB_R14C0:PICL0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R15C0:PICL1\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DRIVE 4\n\n.tile MIB_R1C0:BANKREF7A\nenum: BANK.VCCIO 3V3\n\n.tile MIB_R1C53:PICT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R20C0:PICL0_DQS2\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R21C0:PICL1_DQS3\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.DRIVE 4\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DRIVE 4\n\n.tile MIB_R23C0:PICL0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R24C0:PICL1\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOD.DRIVE 4\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DRIVE 4\n\n.tile MIB_R25C0:MIB_CIB_LR\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R25C3:LMID_0\narc: G_LDCC0CLKI G_JLLCPLL0CLKOS2\narc: G_LDCC6CLKI G_JLLCPLL0CLKOS\n\n.tile MIB_R26C0:PICL0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R27C0:PICL1\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DRIVE 4\n\n.tile MIB_R37C31:CMUX_LL_0\narc: G_DCS1CLK0 G_VPFN0000\narc: G_LLPCLK0 G_HPFE0000\narc: G_LLPCLK1 G_HPFE0600\n\n.tile MIB_R37C32:CMUX_LR_0\narc: G_DCS1CLK1 G_VPFN0000\narc: G_LRPCLK0 G_HPFE0000\narc: G_LRPCLK1 G_HPFE0600\n\n.tile MIB_R3C0:PICL1\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOD.DRIVE 4\n\n.tile MIB_R48C0:PICL1\nenum: PIOC.BASE_TYPE INPUT_LVCMOS33\nenum: PIOC.HYSTERESIS ON\nenum: PIOC.PULLMODE NONE\n\n.tile MIB_R49C0:MIB_CIB_LR\nenum: PIOC.BASE_TYPE INPUT_LVCMOS33\n\n.tile MIB_R4C0:PICL2\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R50C1:BANKREF6\nenum: BANK.VCCIO 3V3\n\n.tile MIB_R50C2:PLL0_LL\narc: N1_CLKFB N1_JCLKFB3\narc: N1_REFCLK1 N1_JREFCLK1_3\n\n.tile MIB_R50C4:EFB0_PICB0\nunknown: F54B1\nunknown: F56B1\nunknown: F82B1\nunknown: F94B1\n\n.tile MIB_R8C0:PICL0_DQS2\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R9C0:PICL1_DQS3\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.DRIVE 4\n\n.tile R10C10:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 H01E0001\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H02W0601\narc: V00B0000 H02E0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 H01E0101\narc: W1_H02W0701 E1_H02W0701\narc: A2 V00B0000\narc: A3 V00B0000\narc: B2 E1_H02W0301\narc: B3 E1_H02W0301\narc: C2 V02N0601\narc: C3 V02N0601\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 V00T0100\narc: D5 H02E0001\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q2\narc: LSR1 V00B0100\narc: M2 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00B0100 F5\narc: V00T0000 Q2\narc: W1_H02W0201 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0100000110111110\nword: SLICEB.K1.INIT 1011111001000001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R10C11:PLC2\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 H02W0201\narc: H00R0000 H02W0401\narc: H00R0100 H02W0701\narc: N1_V02N0701 H02W0701\narc: S1_V02S0601 V01N0001\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 E1_H02W0701\narc: H01W0000 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: A1 H00L0000\narc: B1 H00R0100\narc: C1 V02N0601\narc: C2 H02W0601\narc: C3 N1_V01N0001\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: D2 H02E0001\narc: D3 H00R0000\narc: E1_H01E0001 F2\narc: E1_H01E0101 F7\narc: E1_H02E0101 F1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q7\narc: LSR1 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F2\narc: N1_V01N0101 F7\narc: N1_V02N0001 F2\narc: N3_V06N0203 F7\narc: S3_V06S0203 F7\narc: V00T0100 F3\narc: W1_H02W0001 F2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000100000000\nword: SLICEB.K0.INIT 1111000011111111\nword: SLICEB.K1.INIT 1111111111110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R10C12:PLC2\narc: E1_H02E0701 H01E0101\narc: H00L0000 E1_H02W0001\narc: H00L0100 H02E0101\narc: H00R0000 E1_H02W0401\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 H02W0701\narc: S1_V02S0501 H01E0101\narc: S3_V06S0003 H06W0003\narc: S3_V06S0303 H01E0101\narc: V00B0000 H02W0601\narc: V00B0100 H02W0501\narc: V00T0000 E1_H02W0201\narc: V00T0100 E1_H02W0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 E1_H02W0601\narc: W3_H06W0003 E1_H02W0001\narc: W3_H06W0103 E1_H02W0201\narc: W3_H06W0303 E1_H02W0501\narc: A1 H00R0000\narc: A2 E1_H01E0001\narc: A3 V00T0000\narc: A5 E1_H01W0000\narc: A7 H02E0701\narc: B1 H02W0101\narc: B2 H00R0100\narc: B3 V02S0101\narc: B5 V02S0701\narc: B7 S1_V02N0501\narc: C1 H00L0000\narc: C2 H00L0100\narc: C3 H02W0401\narc: C5 V00B0100\narc: C7 V02N0001\narc: D1 V00T0100\narc: D2 V01S0100\narc: D3 H02W0001\narc: D5 V00B0000\narc: D7 V02S0601\narc: E1_H01E0001 F3\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00R0100 F5\narc: H01W0100 F2\narc: M6 N1_V01N0101\narc: N1_V02N0601 F6\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000100000000\nword: SLICEB.K0.INIT 1000000000000000\nword: SLICEB.K1.INIT 0000000000000001\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000001001111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R10C13:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 E1_H01W0100\narc: H00L0000 V02N0001\narc: H00R0100 V02S0701\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 H02W0701\narc: V00B0000 V02S0001\narc: V00B0100 V02N0301\narc: V00T0000 E1_H02W0201\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: A0 V02N0501\narc: A2 E1_H01E0001\narc: A3 H00L0100\narc: A4 N1_V01N0101\narc: A5 Q5\narc: A6 H00R0000\narc: A7 Q7\narc: B2 N1_V02S0101\narc: B3 H00R0100\narc: B4 V02S0501\narc: B5 H02W0301\narc: B6 V00T0000\narc: B7 V00B0000\narc: CE1 H00L0000\narc: CE2 S1_V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: H00R0000 Q6\narc: H01W0000 Q3\narc: H01W0100 Q2\narc: LSR1 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q4\narc: S1_V02S0101 Q3\narc: S1_V02S0201 Q2\narc: S1_V02S0401 Q4\narc: S1_V02S0501 Q5\narc: S1_V02S0601 Q6\narc: S1_V02S0701 Q7\narc: V01S0000 Q7\narc: V01S0100 Q5\narc: W1_H02W0001 Q2\narc: W1_H02W0301 Q3\narc: W1_H02W0501 Q5\narc: W1_H02W0601 Q6\narc: W1_H02W0701 Q7\narc: W3_H06W0203 Q7\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R10C14:PLC2\narc: E1_H02E0301 V06S0003\narc: E1_H02E0701 W1_H02E0701\narc: H00L0000 V02N0001\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 H06E0203\narc: V00B0100 E1_H02W0701\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: A0 H02E0501\narc: A1 E1_H01E0001\narc: A2 V00T0000\narc: A3 H00L0100\narc: A4 V00B0000\narc: A5 Q5\narc: A6 H00R0000\narc: A7 Q7\narc: B0 H00R0100\narc: B1 E1_H02W0301\narc: B2 N1_V02S0101\narc: B3 E1_H02W0101\narc: B4 V02S0501\narc: B5 V00B0100\narc: B6 N1_V01S0000\narc: B7 H02W0301\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q1\narc: E1_H01E0101 Q3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: H00R0000 Q6\narc: H01W0000 Q5\narc: H01W0100 Q0\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q4\narc: S1_V02S0001 Q2\narc: S1_V02S0101 Q1\narc: S1_V02S0201 Q0\narc: S1_V02S0301 Q3\narc: S1_V02S0401 Q4\narc: S1_V02S0501 Q7\narc: S1_V02S0601 Q6\narc: S1_V02S0701 Q5\narc: S3_V06S0003 Q3\narc: S3_V06S0103 Q2\narc: S3_V06S0203 Q7\narc: S3_V06S0303 Q6\narc: V00B0000 Q4\narc: V00T0000 Q2\narc: V01S0000 Q4\narc: V01S0100 Q5\narc: W1_H02W0001 Q0\narc: W1_H02W0101 Q1\narc: W1_H02W0201 Q2\narc: W1_H02W0501 Q5\narc: W1_H02W0601 Q6\narc: W1_H02W0701 Q7\narc: W3_H06W0003 Q3\narc: W3_H06W0103 Q1\narc: W3_H06W0203 Q7\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R10C15:PLC2\narc: E1_H02E0201 V02N0201\narc: H00R0000 H02W0601\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 H02E0701\narc: S1_V02S0501 H01E0101\narc: V00B0100 V02N0301\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0701 H01E0101\narc: A0 H00L0000\narc: A1 E1_H01E0001\narc: B0 E1_H02W0301\narc: B1 E1_H02W0101\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: H00L0000 Q0\narc: H01W0000 Q0\narc: H01W0100 Q1\narc: LSR1 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: S1_V02S0101 Q1\narc: S1_V02S0201 Q0\narc: W1_H02W0101 Q1\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q1\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R10C16:PLC2\narc: H00R0000 E1_H02W0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 E1_H01W0100\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0601 E1_H02W0601\narc: V00T0000 N1_V02S0601\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V01N0101\narc: B0 V00T0000\narc: C0 H00R0100\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 H02W0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: H01W0100 Q0\narc: LSR0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V02N0001 Q0\narc: N1_V02N0201 Q0\narc: V00T0100 F1\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R10C17:PLC2\narc: H00R0000 H02W0601\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 V06S0003\narc: H01W0000 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0701 W3_H06E0203\narc: W1_H02W0201 W3_H06E0103\narc: B6 V02S0501\narc: C6 N1_V02S0001\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D6 W1_H02E0201\narc: D7 H01W0000\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q6\narc: LSR1 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: V00B0100 F7\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R10C18:PLC2\narc: W1_H02W0601 W3_H06E0303\n\n.tile R10C2:PLC2\narc: E1_H02E0001 V02N0001\narc: H00R0100 V02S0501\narc: V00B0000 V02N0001\narc: V00T0100 N1_V02S0701\narc: A0 H02E0701\narc: A1 H02E0701\narc: A2 H02E0701\narc: A3 H02E0701\narc: B0 V02S0301\narc: B1 V02S0301\narc: B2 V02S0301\narc: B3 V02S0301\narc: C0 H02W0601\narc: C1 H02W0601\narc: C2 H02W0601\narc: C3 H02W0601\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 V00T0100\narc: D3 V00T0100\narc: D7 V00B0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q1\narc: LSR1 V00B0100\narc: M0 H02E0601\narc: M1 H00R0100\narc: M2 N1_V01N0001\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0001 Q1\narc: N1_V02N0101 Q1\narc: N1_V02N0301 Q1\narc: V00B0100 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1011111001000001\nword: SLICEA.K1.INIT 0100000110111110\nword: SLICEB.K0.INIT 1101011100101000\nword: SLICEB.K1.INIT 0010100011010111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R10C3:PLC2\narc: H00L0100 V02S0301\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0401 H06W0203\narc: V00T0100 V02S0501\narc: W1_H02W0601 V02S0601\narc: A7 E1_H02W0701\narc: B7 H02W0301\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D6 H02E0001\narc: D7 H00L0100\narc: E1_H01E0101 Q7\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00B0000 F6\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 1001011001101001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\n\n.tile R10C4:PLC2\narc: E1_H02E0401 V01N0001\narc: H00L0100 V02S0301\narc: N1_V02N0301 S1_V02N0201\narc: W1_H02W0301 V06S0003\narc: B0 E1_H01W0100\narc: C0 H00L0100\narc: CLK0 G_HPBX0100\narc: D0 H01E0101\narc: D1 H02W0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V02N0001 Q0\narc: V00T0100 F1\nword: SLICEA.K0.INIT 1111110000001100\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R10C5:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0401 V01N0001\narc: E1_H02E0701 V01N0101\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 V02S0001\narc: H00R0000 H02W0601\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 V01N0001\narc: N1_V02N0601 E1_H02W0601\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 N1_V01S0100\narc: B2 H00R0000\narc: C2 H00L0000\narc: CLK0 G_HPBX0100\narc: D2 N1_V01S0000\narc: D3 V02N0001\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0100 Q2\narc: LSR1 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00T0100 F3\nword: SLICEB.K0.INIT 1111110000001100\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R10C6:PLC2\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 S3_V06N0203\narc: H00L0000 V02S0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02N0401\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 H02E0401\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0601 N1_V02S0301\narc: V00B0100 N1_V02S0301\narc: V00T0000 S1_V02N0601\narc: W1_H02W0601 N1_V02S0601\narc: W3_H06W0203 E1_H01W0000\narc: A4 V02N0301\narc: A5 V00T0000\narc: A6 V02N0101\narc: A7 V02N0101\narc: B2 V02S0101\narc: B4 E1_H02W0301\narc: B5 H00R0000\narc: B6 H02W0101\narc: B7 H02W0101\narc: C2 H00L0000\narc: C4 V00B0100\narc: C5 W1_H02E0401\narc: C6 V02N0001\narc: C7 V02N0001\narc: CLK0 G_HPBX0100\narc: D2 H02W0201\narc: D3 H02E0201\narc: D4 H00L0100\narc: D5 V00B0000\narc: D6 V02N0601\narc: D7 V02N0601\narc: E1_H01E0101 F4\narc: E1_H02E0601 F4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: LSR1 V00T0100\narc: M6 H02W0401\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V02N0601 F6\narc: S3_V06S0103 Q2\narc: S3_V06S0303 F5\narc: V00B0000 F4\narc: V00T0100 F3\narc: V01S0000 F4\narc: V01S0100 F4\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 0000000011101111\nword: SLICEB.K0.INIT 1111110000001100\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1110101011111000\nword: SLICED.K1.INIT 1000111110101110\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R10C7:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 E1_H02W0001\narc: H00L0100 V02S0301\narc: H00R0000 S1_V02N0401\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 N1_V01S0100\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 H02E0601\narc: V00B0100 V02N0301\narc: V00T0000 S1_V02N0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 E1_H02W0301\narc: A0 W1_H02E0701\narc: A3 W1_H02E0701\narc: A5 W1_H02E0701\narc: A6 W1_H02E0701\narc: B0 V02N0301\narc: B3 V02N0301\narc: B5 V00B0100\narc: B6 V00B0100\narc: C0 S1_V02N0401\narc: C3 S1_V02N0401\narc: C5 V00T0000\narc: C6 V00T0000\narc: D0 H01E0101\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H01E0101\narc: D4 S1_V02N0401\narc: D5 V00B0000\narc: D6 V00B0000\narc: D7 S1_V02N0401\narc: E1_H02E0101 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00T0100\narc: M1 H00L0100\narc: M2 V00T0100\narc: M3 H00L0000\narc: M4 V00T0100\narc: M5 H00L0100\narc: M6 V00T0100\narc: W1_H02W0101 F3\nword: SLICEA.K0.INIT 0000111111110100\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000111111110100\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 0000111111110100\nword: SLICED.K0.INIT 0000111111110100\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R10C8:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0701 E3_H06W0203\narc: H00R0000 V02N0601\narc: H00R0100 H02E0701\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02E0701\narc: V00T0000 H02E0001\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E1_H02W0201\narc: A4 V02N0301\narc: A5 V02N0301\narc: A6 V02N0301\narc: A7 V02N0301\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 V00B0100\narc: B6 V00B0100\narc: B7 V00B0100\narc: C0 W1_H02E0601\narc: C1 W1_H02E0601\narc: C2 W1_H02E0601\narc: C3 W1_H02E0601\narc: C4 W1_H02E0601\narc: C5 W1_H02E0601\narc: C6 W1_H02E0601\narc: C7 W1_H02E0601\narc: D0 S1_V02N0001\narc: D1 S1_V02N0001\narc: D2 S1_V02N0001\narc: D3 S1_V02N0001\narc: D4 V00B0000\narc: D5 V00B0000\narc: D6 V00B0000\narc: D7 V00B0000\narc: E1_H02E0101 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H02W0001\narc: M2 V00T0000\narc: M3 H00R0000\narc: M4 V00T0000\narc: M5 H02W0001\narc: M6 V00T0000\narc: V01S0100 F3\nword: SLICEC.K0.INIT 1111111011111111\nword: SLICEC.K1.INIT 1111111111111110\nword: SLICED.K0.INIT 1111111111111110\nword: SLICED.K1.INIT 1111111011111111\nword: SLICEA.K0.INIT 0000001100000000\nword: SLICEA.K1.INIT 0000000000000011\nword: SLICEB.K0.INIT 0000000000000011\nword: SLICEB.K1.INIT 0000001100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R10C9:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V02N0001\narc: E1_H02E0401 W1_H02E0101\narc: H00L0000 H02E0001\narc: H00R0000 V02N0401\narc: H00R0100 H02W0701\narc: N1_V02N0101 H06W0103\narc: N1_V02N0301 H06W0003\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 V01N0101\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 H06W0303\narc: V00B0000 H02E0401\narc: V00B0100 H02E0701\narc: V00T0000 V02N0601\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0401 E1_H01W0000\narc: A0 V01N0101\narc: A2 V01N0101\narc: A4 H02E0501\narc: B0 V02N0301\narc: B1 V00B0000\narc: B2 H00R0100\narc: B3 H02W0301\narc: B4 V02S0701\narc: B5 V02S0501\narc: C0 H00L0000\narc: C1 E1_H02W0401\narc: C2 H00L0100\narc: C3 V02N0601\narc: C4 V00B0100\narc: C5 V00T0000\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H02W0001\narc: D2 H02E0201\narc: D3 H00R0000\narc: D4 H02W0001\narc: D5 V02N0401\narc: E1_H01E0101 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0100 F1\narc: H01W0000 Q3\narc: H01W0100 Q0\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q4\narc: V01S0000 F1\narc: V01S0100 F1\narc: W1_H02W0301 F1\nword: SLICEA.K0.INIT 1111010001000100\nword: SLICEA.K1.INIT 0000001100000000\nword: SLICEB.K0.INIT 1111010001000100\nword: SLICEB.K1.INIT 1100000011111111\nword: SLICEC.K0.INIT 0000111000000000\nword: SLICEC.K1.INIT 1100000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R11C10:PLC2\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 V06N0303\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 E3_H06W0203\narc: H00R0000 V02S0401\narc: N1_V02N0001 H02W0001\narc: N1_V02N0601 H01E0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0401 E1_H01W0000\narc: V00B0000 V02S0001\narc: V00T0000 V02S0401\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0701 H01E0101\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0203 E1_H01W0000\narc: A0 H00R0000\narc: A2 E1_H01E0001\narc: A5 V00T0000\narc: A6 V00T0100\narc: B0 H01W0100\narc: B1 H01W0100\narc: B2 H01W0100\narc: B5 H02E0301\narc: B6 H02E0301\narc: C0 H00R0100\narc: C1 H00L0100\narc: C2 N1_V01N0001\narc: C5 V00T0100\narc: C6 V00B0100\narc: C7 E1_H01E0101\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 H00R0000\narc: D2 V00B0100\narc: D3 V00T0100\narc: D5 H00R0100\narc: D6 V02S0401\narc: D7 H00L0100\narc: E1_H01E0001 Q3\narc: E1_H01E0101 Q7\narc: E1_H02E0201 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: H00R0100 Q5\narc: H01W0000 F2\narc: H01W0100 Q7\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q1\narc: N1_V01N0101 Q3\narc: S1_V02S0201 F2\narc: S1_V02S0301 Q1\narc: S1_V02S0501 Q7\narc: S1_V02S0601 F6\narc: S1_V02S0701 Q5\narc: S3_V06S0103 F2\narc: S3_V06S0303 F6\narc: V00B0100 Q5\narc: V00T0100 Q3\narc: V01S0000 F0\narc: V01S0100 F6\narc: W1_H02W0201 F2\narc: W1_H02W0601 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0111111110000000\nword: SLICEA.K0.INIT 0001000000000000\nword: SLICEA.K1.INIT 0011111111000000\nword: SLICEB.K0.INIT 1110001111111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 0100000000000000\nword: SLICED.K1.INIT 0000111111110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R11C11:PLC2\narc: H00R0100 H02E0701\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0301 H06E0003\narc: V00T0000 H02E0201\narc: W1_H02W0001 S3_V06N0003\narc: W3_H06W0003 S3_V06N0003\narc: A5 V00T0100\narc: A6 V02N0301\narc: B0 H01W0100\narc: B5 H00R0000\narc: B6 V02N0701\narc: C0 H02E0601\narc: C1 H00L0100\narc: C5 E1_H01E0101\narc: C6 V00T0000\narc: CE0 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 Q0\narc: D1 H00R0000\narc: D4 V00B0000\narc: D5 V02S0601\narc: D6 E1_H01W0100\narc: E1_H01E0101 Q0\narc: E1_H02E0101 F1\narc: E1_H02E0701 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 Q1\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: H01W0100 Q1\narc: LSR1 E1_H02W0301\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0001 Q5\narc: S1_V02S0001 Q0\narc: S1_V02S0101 Q1\narc: S1_V02S0501 Q5\narc: S1_V02S0601 Q4\narc: V00B0000 Q4\narc: V00T0100 Q1\narc: V01S0000 Q0\narc: V01S0100 F1\narc: W1_H02W0201 Q0\narc: W1_H02W0301 Q1\narc: W1_H02W0401 F6\narc: W1_H02W0501 Q5\narc: W1_H02W0601 Q4\narc: W3_H06W0303 Q5\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 0111111110000000\nword: SLICEA.K0.INIT 0011111111000000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 0000011101110111\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R11C12:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0501 V02S0501\narc: H00L0100 H02E0101\narc: N1_V02N0001 E1_H02W0001\narc: V00B0100 H02E0701\narc: C1 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: F1 F1_SLICE\narc: H01W0100 Q1\narc: MUXCLK0 CLK0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R11C13:PLC2\narc: E1_H02E0601 V02N0601\narc: H00L0100 V02S0101\narc: H00R0000 V02S0601\narc: N1_V02N0001 H02E0001\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0501 H02W0501\narc: V00B0000 V02S0201\narc: V00T0000 V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0601 N1_V01S0000\narc: A0 H02E0501\narc: A2 V00B0000\narc: A3 H00L0100\narc: A4 V00T0000\narc: A5 N1_V01S0100\narc: A6 H00R0000\narc: A7 V00T0100\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R11C14:PLC2\narc: H00L0000 V02S0201\narc: H00L0100 V02S0101\narc: H00R0000 V02S0601\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 H02E0601\narc: V00B0000 V02S0001\narc: V00T0000 V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0501 V06N0303\narc: W3_H06W0103 N1_V01S0100\narc: W3_H06W0203 N1_V01S0000\narc: A0 H00L0000\narc: A1 H00L0100\narc: A2 V00B0000\narc: A3 H02W0501\narc: A4 V00T0000\narc: A5 N1_V01S0100\narc: A6 H00R0000\narc: A7 V00T0100\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R11C15:PLC2\narc: H00L0000 V02S0201\narc: H00L0100 V02S0101\narc: N1_V02N0301 S3_V06N0003\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0501 V02S0501\narc: A0 H00L0000\narc: A1 H00L0100\narc: E1_H02E0201 F2\narc: F2 F2_SLICE\narc: H01W0000 F2\narc: N1_V02N0001 F2\narc: N1_V02N0201 F2\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R11C16:PLC2\narc: W3_H06W0203 S3_V06N0203\narc: B6 N1_V02S0501\narc: C6 V02S0001\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D6 H02E0201\narc: D7 V02S0401\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q6\narc: N1_V02N0601 Q6\narc: V00B0100 F7\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R11C2:PLC2\narc: N1_V02N0001 H06W0003\n\n.tile R11C3:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V02N0701\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0401 E1_H02W0401\narc: C3 V02S0401\narc: CLK0 G_HPBX0000\narc: D2 E1_H02W0001\narc: D3 V01S0100\narc: E1_H02E0301 Q3\narc: E3_H06E0003 Q3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR1 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00T0000 F2\narc: V01S0100 Q3\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 1111000000001111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R11C4:PLC2\narc: H00R0000 H02E0601\narc: H00R0100 V02N0501\narc: S1_V02S0701 E1_H02W0701\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02E0701\narc: V00T0000 S1_V02N0601\narc: A2 E1_H02W0701\narc: A3 E1_H02W0701\narc: A4 E1_H02W0701\narc: A5 E1_H02W0701\narc: A6 E1_H02W0701\narc: A7 E1_H02W0701\narc: B1 V00B0000\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 V02N0501\narc: B5 V02N0501\narc: B6 V02N0501\narc: B7 V02N0501\narc: C1 H00R0100\narc: C2 H02E0401\narc: C3 H02E0401\narc: C4 H02E0401\narc: C5 H02E0401\narc: C6 H02E0401\narc: C7 H02E0401\narc: D1 V00B0100\narc: D2 E1_H02W0001\narc: D3 E1_H02W0001\narc: D4 E1_H02W0001\narc: D5 E1_H02W0001\narc: D6 E1_H02W0001\narc: D7 E1_H02W0001\narc: E1_H02E0101 F3\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 E1_H02W0601\narc: M1 H02E0001\narc: M2 E1_H02W0601\narc: M3 H00R0000\narc: M4 V00T0000\narc: M5 H02E0001\narc: M6 V00T0000\narc: N1_V01N0001 F3\nword: SLICED.K0.INIT 1111111101110001\nword: SLICED.K1.INIT 0111000100000000\nword: SLICEC.K0.INIT 1110111111110111\nword: SLICEC.K1.INIT 1111011100010000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0011111100000011\nword: SLICEB.K0.INIT 1110111111110111\nword: SLICEB.K1.INIT 1111011100010000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R11C5:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 H02W0001\narc: H00R0000 S1_V02N0601\narc: H00R0100 E1_H02W0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 N1_V01S0000\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 H02W0001\narc: S1_V02S0401 H02W0401\narc: S1_V02S0701 H02W0701\narc: V00B0000 W1_H02E0601\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02W0001\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0401 E1_H01W0000\narc: W3_H06W0003 S3_V06N0003\narc: A0 H02W0701\narc: A1 H02W0701\narc: A2 H02W0701\narc: A3 H02W0701\narc: A4 H02W0701\narc: A5 H02W0701\narc: A6 H02W0701\narc: A7 H02W0701\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 V00B0100\narc: B6 V00B0100\narc: B7 V00B0100\narc: C0 H00L0000\narc: C1 H00L0000\narc: C2 H00L0000\narc: C3 H00L0000\narc: C4 V00T0000\narc: C5 V00T0000\narc: C6 V00T0000\narc: C7 V00T0000\narc: D0 V02N0001\narc: D1 W1_H02E0001\narc: D2 V02N0001\narc: D3 W1_H02E0001\narc: D4 V02N0401\narc: D5 V02N0401\narc: D6 V02N0401\narc: D7 V02N0401\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 W1_H02E0601\narc: M1 E1_H02W0001\narc: M2 W1_H02E0601\narc: M3 H00R0000\narc: M4 V00B0000\narc: M5 E1_H02W0001\narc: M6 V00B0000\narc: N1_V01N0101 F3\nword: SLICEA.K0.INIT 0001111010000111\nword: SLICEA.K1.INIT 1000100000011110\nword: SLICED.K0.INIT 0111100000011110\nword: SLICED.K1.INIT 0001000101111000\nword: SLICEC.K0.INIT 1110000101111000\nword: SLICEC.K1.INIT 0111011111100001\nword: SLICEB.K0.INIT 1000011111100001\nword: SLICEB.K1.INIT 1110111010000111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R11C6:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 H01E0001\narc: H00R0000 V02S0601\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 H02E0601\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 H01E0001\narc: V00B0000 V02S0201\narc: V00B0100 V02N0101\narc: V00T0100 H02E0301\narc: W1_H02W0001 V02N0001\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 S3_V06N0203\narc: A0 E1_H02W0501\narc: A3 E1_H02W0501\narc: A5 E1_H02W0501\narc: A6 E1_H02W0501\narc: B0 V02N0101\narc: B1 E1_H02W0301\narc: B2 E1_H02W0101\narc: B3 V02N0101\narc: B4 E1_H02W0101\narc: B5 V00B0100\narc: B6 V00B0100\narc: B7 E1_H02W0301\narc: C0 V02S0401\narc: C1 S1_V02N0401\narc: C2 S1_V02N0401\narc: C3 V02S0401\narc: C4 V00B0100\narc: C5 V02S0001\narc: C6 V02S0001\narc: C7 V00B0100\narc: D0 V02S0201\narc: D1 V02S0201\narc: D2 V02S0201\narc: D3 V02S0201\narc: D4 V00B0000\narc: D5 V00B0000\narc: D6 V00B0000\narc: D7 V00B0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 H02E0601\narc: M1 E1_H02W0001\narc: M2 H02E0601\narc: M3 H00R0000\narc: M4 V00T0100\narc: M5 E1_H02W0001\narc: M6 V00T0100\nword: SLICEA.K0.INIT 0011001000100000\nword: SLICEA.K1.INIT 0000111100001100\nword: SLICEB.K0.INIT 1100111111111111\nword: SLICEB.K1.INIT 1011001111111011\nword: SLICEC.K0.INIT 1100000011110000\nword: SLICEC.K1.INIT 1000000011001000\nword: SLICED.K0.INIT 1111111011101100\nword: SLICED.K1.INIT 1111111111111100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R11C7:PLC2\narc: H00L0000 N1_V02S0001\narc: H00L0100 H02E0301\narc: H00R0000 H02E0401\narc: H00R0100 V02N0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 E1_H01W0100\narc: S1_V02S0701 H06W0203\narc: V00B0000 H02E0401\narc: V00T0000 V02N0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0501 S1_V02N0501\narc: A0 H00R0000\narc: A3 V00B0000\narc: A5 V00B0000\narc: A6 H00R0000\narc: B0 V00T0000\narc: B3 H00R0100\narc: B5 V02N0701\narc: B6 V02N0701\narc: C0 H02E0601\narc: C3 H02E0601\narc: C5 H02E0601\narc: C6 H02E0601\narc: D0 H02E0001\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H02E0001\narc: D4 V00B0000\narc: D5 H02E0001\narc: D6 H02E0001\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00L0000\narc: M2 V00T0100\narc: M3 H00L0100\narc: M4 V00T0100\narc: M5 H00L0000\narc: M6 V00T0100\nword: SLICEA.K0.INIT 0101010101010100\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 0101010101010100\nword: SLICED.K0.INIT 0101010101010100\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0101010101010100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R11C8:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 V02S0001\narc: E1_H02E0401 V02S0401\narc: H00L0000 E1_H02W0201\narc: H00L0100 E1_H02W0101\narc: H00R0000 H02W0601\narc: H00R0100 H02W0501\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0001 H06W0003\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 V02S0001\narc: V00B0100 H02W0501\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02W0101\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0501 N1_V01S0100\narc: A0 V02N0701\narc: A1 V02N0501\narc: A2 E1_H02W0501\narc: A4 E1_H02W0501\narc: A5 V02N0301\narc: A7 V02N0101\narc: B0 H00R0100\narc: B1 E1_H01W0100\narc: B2 H00R0000\narc: B4 V00B0100\narc: B5 V02S0501\narc: B7 V00B0000\narc: C0 H00L0100\narc: C1 H00L0000\narc: C2 H00R0100\narc: C3 H00L0000\narc: C4 H02W0601\narc: C5 V00T0000\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 V02S0201\narc: D2 H02W0201\narc: D3 V01S0100\narc: D4 H02W0201\narc: D5 H02W0001\narc: D7 V02N0401\narc: E1_H01E0001 Q4\narc: E1_H02E0101 F3\narc: E3_H06E0003 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q5\narc: H01W0100 F3\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N1_V02N0101 Q1\narc: V01S0000 Q7\narc: V01S0100 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0100111101000100\nword: SLICEC.K0.INIT 0101001100001000\nword: SLICEC.K1.INIT 1000111110001000\nword: SLICEA.K0.INIT 0001001100111010\nword: SLICEA.K1.INIT 1000111110001000\nword: SLICEB.K0.INIT 0000011100000000\nword: SLICEB.K1.INIT 0000111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R11C9:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 E1_H01W0100\narc: H00L0000 V02S0201\narc: H00L0100 V02S0301\narc: H00R0000 H02W0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 H02W0601\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 V01N0001\narc: V00B0000 H02E0401\narc: V00B0100 V02S0101\narc: V00T0000 V02S0601\narc: V00T0100 V02N0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 E1_H02W0601\narc: E1_H01E0001 W3_H06E0003\narc: A0 H02W0701\narc: A5 V00T0100\narc: A7 H00R0000\narc: B0 V00T0000\narc: B1 V00B0000\narc: B5 H00L0000\narc: B6 E1_H02W0301\narc: B7 V01S0000\narc: C0 V02N0401\narc: C1 H00L0100\narc: C5 E1_H01E0101\narc: C6 V02N0201\narc: C7 S1_V02N0201\narc: CLK0 G_HPBX0000\narc: D0 N1_V01S0000\narc: D1 V00B0100\narc: D5 H02E0001\narc: D6 H00R0100\narc: D7 V02S0401\narc: E1_H01E0101 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q0\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 F1\narc: S1_V02S0701 Q7\narc: S3_V06S0103 F1\narc: S3_V06S0303 Q6\narc: V01S0000 Q5\narc: V01S0100 F1\narc: W1_H02W0101 F1\narc: W1_H02W0401 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0100111101000100\nword: SLICED.K0.INIT 0000001111110000\nword: SLICED.K1.INIT 1000111110001000\nword: SLICEA.K0.INIT 1111010001000100\nword: SLICEA.K1.INIT 1100001111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\n\n.tile R12C10:PLC2\narc: E1_H02E0601 N1_V01S0000\narc: H00L0000 N1_V02S0201\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0203 H01E0001\narc: V00B0000 V02N0001\narc: V00B0100 V02S0101\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 V02S0601\narc: A0 H00L0000\narc: A1 H00R0000\narc: A3 V02N0501\narc: A5 V00T0000\narc: A6 V02S0301\narc: A7 N1_V01N0101\narc: B0 V00B0000\narc: B1 V02N0301\narc: B3 H01W0100\narc: B5 H02E0301\narc: B6 V02S0501\narc: B7 H02W0101\narc: C0 V02N0401\narc: C1 E1_H02W0601\narc: C3 V02N0601\narc: C5 H02W0401\narc: C6 V00T0100\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 N1_V01S0000\narc: D3 H02E0201\narc: D5 N1_V02S0601\narc: D6 H00R0100\narc: D7 H00L0100\narc: E1_H01E0101 F6\narc: E1_H02E0401 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0000 F6\narc: H01W0100 Q5\narc: M2 H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F6\narc: S1_V02S0201 Q2\narc: S1_V02S0501 Q7\narc: V01S0100 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000001111111110\nword: SLICEA.K0.INIT 0000101100000000\nword: SLICEA.K1.INIT 0000011101110111\nword: SLICED.K0.INIT 0000000111111110\nword: SLICED.K1.INIT 1111100011111111\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 1111010001000100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R12C11:PLC2\narc: E1_H02E0701 N1_V01S0100\narc: H00R0100 V02S0501\narc: N1_V02N0301 H01E0101\narc: V00B0000 H02E0401\narc: V00B0100 V02S0301\narc: V00T0000 V02S0601\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 E1_H01W0000\narc: W3_H06W0203 N1_V01S0000\narc: A4 V00B0000\narc: A7 V02S0101\narc: B1 V02S0101\narc: B4 V01S0000\narc: B7 V00T0000\narc: C1 V02S0601\narc: C3 N1_V01S0100\narc: C4 H02E0601\narc: C7 V02S0001\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D3 V02S0001\narc: D4 H01W0000\narc: D7 H00R0100\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q3\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0701 Q7\narc: S1_V02S0401 F4\narc: V01S0000 Q1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000111111110\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000001111111100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0000011101110111\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R12C12:PLC2\narc: N1_V02N0501 E1_H02W0501\narc: V00B0100 H02E0701\narc: N1_V02N0301 W3_H06E0003\narc: S3_V06S0003 W3_H06E0003\narc: W3_H06W0203 E1_H02W0401\narc: CLK0 G_HPBX0000\narc: H01W0000 Q6\narc: H01W0100 Q0\narc: M0 V00B0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: V01S0000 Q0\narc: W1_H02W0601 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R12C13:PLC2\narc: H00L0000 N1_V02S0201\narc: H00R0000 N1_V02S0401\narc: N1_V02N0601 S1_V02N0601\narc: V00T0000 N1_V02S0601\narc: A0 V02N0501\narc: B2 H00L0000\narc: B3 N1_V02S0101\narc: B4 H00R0000\narc: B5 N1_V02S0501\narc: B6 V00T0000\narc: B7 N1_V02S0701\nword: SLICED.K0.INIT 0011110000000000\nword: SLICED.K1.INIT 0011110000000000\nword: SLICEC.K0.INIT 0011110000000000\nword: SLICEC.K1.INIT 0011110000000000\nword: SLICEB.K0.INIT 0011110000000000\nword: SLICEB.K1.INIT 0011110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R12C14:PLC2\narc: H00L0000 N1_V02S0001\narc: H00R0000 N1_V02S0401\narc: V00B0000 N1_V02S0201\narc: V00T0000 N1_V02S0601\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 E1_H01W0100\narc: B0 V00B0000\narc: B1 N1_V02S0101\narc: B2 H00L0000\narc: B3 N1_V02S0301\narc: B4 H00R0000\narc: B5 N1_V02S0701\narc: B6 V00T0000\narc: B7 N1_V02S0501\nword: SLICED.K0.INIT 0011110000000000\nword: SLICED.K1.INIT 0011110000000000\nword: SLICEC.K0.INIT 0011110000000000\nword: SLICEC.K1.INIT 0011110000000000\nword: SLICEB.K0.INIT 0011110000000000\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 0011110000000000\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R12C15:PLC2\narc: V00B0000 N1_V02S0201\narc: B0 V00B0000\narc: B1 N1_V02S0101\narc: F2 F2_SLICE\narc: H01W0100 F2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 0011110000000000\nword: SLICEA.K1.INIT 0011110000000000\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R12C16:PLC2\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0601 S1_V02N0601\n\n.tile R12C2:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02W0701\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D6 V00B0000\narc: D7 H02E0001\narc: E1_H01E0101 F6\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 H02W0301\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: S1_V02S0701 Q7\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 1111000000001111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R12C3:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0601 V02N0601\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0401 H06W0203\narc: N1_V02N0701 H06W0203\narc: W1_H02W0301 H01E0101\narc: W1_H02W0701 E1_H02W0701\narc: C3 V02S0401\narc: CLK0 G_HPBX0000\narc: D2 V02S0001\narc: D3 E1_H02W0201\narc: E1_H01E0001 Q3\narc: E1_H02E0101 Q3\narc: E3_H06E0003 Q3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR1 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00T0000 F2\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 1111000000001111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R12C4:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0701 V02S0701\narc: H00L0100 H02E0101\narc: N1_V02N0501 H02W0501\narc: V00B0000 H02E0601\narc: V00B0100 S1_V02N0101\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02S0701\narc: A4 V00T0100\narc: A5 V00T0100\narc: B4 V02N0501\narc: B5 V02N0501\narc: C4 H02W0401\narc: C5 H02W0401\narc: C7 E1_H02W0601\narc: CLK0 G_HPBX0100\narc: D4 V00B0000\narc: D5 V00B0000\narc: D7 H00L0100\narc: E1_H01E0001 F7\narc: E1_H02E0501 F7\narc: E1_H02E0601 F4\narc: E3_H06E0203 F4\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00B0100\narc: M2 V00T0000\narc: M4 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V02N0201 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 0110100110010110\nword: SLICEC.K1.INIT 1001011001101001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R12C5:PLC2\narc: E1_H02E0401 V06S0203\narc: H00R0000 V02N0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0401 E1_H02W0401\narc: V00B0000 V02S0001\narc: V00B0100 E1_H02W0501\narc: V00T0000 V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 V06N0303\narc: W1_H02W0701 V06S0203\narc: A0 V02S0701\narc: A2 V02S0701\narc: A3 V02S0701\narc: A4 V00T0100\narc: A6 H02E0701\narc: A7 V00T0100\narc: B0 H02W0301\narc: B1 V00T0000\narc: B2 H02W0301\narc: B3 H02W0301\narc: B4 H02W0301\narc: B6 H02W0301\narc: B7 H02W0301\narc: C0 H00R0100\narc: C1 H02W0401\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 V00B0100\narc: C6 V00B0100\narc: C7 V00B0100\narc: D0 V02S0001\narc: D1 V00B0100\narc: D2 V02S0001\narc: D3 V02S0001\narc: D4 V00B0000\narc: D6 V00B0000\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: E1_H02E0101 F3\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 E1_H02W0601\narc: M1 H02W0001\narc: M2 E1_H02W0601\narc: M3 H00R0000\narc: M4 E1_H02W0401\narc: M5 H02W0001\narc: M6 E1_H02W0401\narc: N1_V02N0101 F3\nword: SLICEC.K0.INIT 0000000000100000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1011001011111111\nword: SLICEB.K1.INIT 0010000011111011\nword: SLICEA.K0.INIT 0010000011111011\nword: SLICEA.K1.INIT 1100111100001100\nword: SLICED.K0.INIT 0000000010110010\nword: SLICED.K1.INIT 0000000000100000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R12C6:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0401 E3_H06W0203\narc: H00R0000 W1_H02E0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0301 H06E0003\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0501 W1_H02E0501\narc: V00B0000 W1_H02E0601\narc: V00B0100 V02S0101\narc: V00T0100 H02E0101\narc: W1_H02W0001 V02N0001\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 H01E0001\narc: W3_H06W0203 E1_H01W0000\narc: A4 V02N0301\narc: A5 V02N0301\narc: A6 V02N0301\narc: A7 V02N0301\narc: B4 H00R0000\narc: B5 H00R0000\narc: B6 V00B0000\narc: B7 V00B0000\narc: C4 V00B0100\narc: C5 V00B0100\narc: C6 V00B0100\narc: C7 V00B0100\narc: D0 V02N0201\narc: D1 V02N0201\narc: D2 V02N0201\narc: D3 V02N0201\narc: D4 V02S0601\narc: D5 V02S0601\narc: D6 V02S0601\narc: D7 V02S0601\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 W1_H02E0001\narc: M2 V00T0100\narc: M3 H00R0100\narc: M4 V00T0100\narc: M5 W1_H02E0001\narc: M6 V00T0100\narc: N1_V01N0001 F3\narc: N1_V02N0101 F3\narc: S3_V06S0003 F3\narc: V01S0000 F3\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 1111111111011111\nword: SLICEC.K1.INIT 0000000000010000\nword: SLICED.K0.INIT 0000000000010000\nword: SLICED.K1.INIT 1111111111011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R12C7:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0701 V02S0701\narc: H00L0100 S1_V02N0101\narc: H00R0100 H02W0701\narc: N1_V02N0401 H06E0203\narc: N1_V02N0701 H06E0203\narc: S1_V02S0201 V01N0001\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02W0501\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: A3 V00T0000\narc: B2 H00R0100\narc: B3 S1_V02N0301\narc: C2 H02W0601\narc: C3 H00L0100\narc: CE1 V02N0201\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 S1_V02N0201\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q2\narc: LSR0 V00B0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: S1_V02S0001 Q2\narc: S1_V02S0301 F3\narc: S3_V06S0103 Q2\narc: V00T0000 Q2\narc: V01S0000 Q2\nword: SLICEB.K0.INIT 1111111111111100\nword: SLICEB.K1.INIT 0111111011101000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R12C8:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 N1_V02S0701\narc: H00L0000 V02S0201\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02S0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 H06W0203\narc: V00B0000 E1_H02W0601\narc: V00T0100 H02W0301\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 V06S0203\narc: A0 H02W0501\narc: A1 H00R0000\narc: A4 V02S0301\narc: A5 V00B0000\narc: A6 H02W0701\narc: A7 H00R0000\narc: B0 H02E0101\narc: B1 V00T0000\narc: B4 H02W0101\narc: B5 N1_V01S0000\narc: B6 V02N0701\narc: B7 V01S0000\narc: C0 H02W0601\narc: C1 H00L0000\narc: C3 H02E0401\narc: C4 E1_H02W0401\narc: C5 V02S0201\narc: C6 V00T0100\narc: C7 V02S0201\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 V01S0100\narc: D3 V02S0001\narc: D4 H00R0100\narc: D5 H01W0000\narc: D6 H00L0100\narc: D7 V02S0401\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0701 Q5\narc: S3_V06S0103 Q1\narc: V00T0000 Q0\narc: V01S0000 Q6\narc: V01S0100 Q4\narc: W1_H02W0501 Q7\narc: W3_H06W0003 Q3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111111111111\nword: SLICEC.K0.INIT 0101001111001100\nword: SLICEC.K1.INIT 1000111110001000\nword: SLICEA.K0.INIT 1111010001000100\nword: SLICEA.K1.INIT 1000111110001000\nword: SLICED.K0.INIT 0100111101000100\nword: SLICED.K1.INIT 1000111110001000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R12C9:PLC2\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 V02S0301\narc: E1_H02E0601 V02S0601\narc: H00L0000 E1_H02W0201\narc: H00L0100 N1_V02S0101\narc: H00R0000 N1_V02S0601\narc: H00R0100 V02S0501\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H06W0203\narc: S1_V02S0001 N1_V02S0001\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0601\narc: V00T0100 N1_V02S0501\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 E1_H02W0301\narc: N1_V02N0001 W3_H06E0003\narc: A0 F7\narc: A1 H02W0501\narc: A2 N1_V02S0501\narc: A3 H02W0501\narc: A4 W1_H02E0701\narc: A5 H02W0501\narc: A6 F7\narc: A7 H02E0701\narc: B0 V00T0000\narc: B1 V02S0101\narc: B2 H00R0000\narc: B3 V02N0101\narc: B4 H00L0000\narc: B5 H02W0101\narc: B6 W1_H02E0101\narc: B7 V00B0000\narc: C0 N1_V01S0100\narc: C1 E1_H02W0601\narc: C2 H02E0401\narc: C3 V02S0401\narc: C4 V00B0100\narc: C5 V02S0001\narc: C6 V00T0100\narc: C7 H02E0601\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 H02W0001\narc: D2 H02W0201\narc: D3 H02E0001\narc: D4 H00R0100\narc: D5 H01W0000\narc: D6 N1_V02S0601\narc: D7 H00L0100\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: H01W0100 F7\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q0\narc: N1_V02N0701 F7\narc: S3_V06S0003 Q3\narc: V01S0000 Q5\narc: V01S0100 Q2\narc: W1_H02W0701 F7\nword: SLICEC.K0.INIT 0000011111001100\nword: SLICEC.K1.INIT 1000111110001000\nword: SLICEA.K0.INIT 0100111101000100\nword: SLICEA.K1.INIT 0000011101110111\nword: SLICED.K0.INIT 0100111101000100\nword: SLICED.K1.INIT 1111111001111111\nword: SLICEB.K0.INIT 1111010001000100\nword: SLICEB.K1.INIT 1000111110001000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R14C10:PLC2\narc: E1_H02E0601 V06S0303\narc: N1_V02N0201 H01E0001\narc: S1_V02S0001 H01E0001\narc: S1_V02S0601 H01E0001\narc: S3_V06S0203 H01E0001\narc: V00B0000 N1_V02S0201\narc: V00T0100 N1_V02S0501\narc: W1_H02W0101 V01N0101\narc: B3 W1_H02E0301\narc: B7 W1_H02E0301\narc: C3 W1_H02E0601\narc: C5 V02N0001\narc: C7 W1_H02E0601\narc: CE1 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D5 S1_V02N0401\narc: D7 V00B0000\narc: E1_H01E0101 F5\narc: E3_H06E0303 F5\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0000 Q7\narc: H01W0100 Q3\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 F5\narc: N3_V06N0303 F5\narc: S3_V06S0303 F5\narc: W1_H02W0301 Q3\narc: W1_H02W0501 Q7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111111111111100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R14C11:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: H00L0100 W1_H02E0101\narc: H00R0000 N1_V02S0401\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0701 V01N0101\narc: S3_V06S0103 E3_H06W0103\narc: V00T0100 V02S0701\narc: W1_H02W0301 H01E0101\narc: W1_H02W0501 S1_V02N0501\narc: A2 V02S0501\narc: B2 V02S0301\narc: B3 H00L0000\narc: C2 H00L0100\narc: C3 H02E0601\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 H00R0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H00L0000 Q2\narc: MUXCLK1 CLK0\narc: W1_H02W0101 Q3\nword: SLICEB.K0.INIT 0000000111000000\nword: SLICEB.K1.INIT 1100000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R14C12:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: H00R0000 S1_V02N0601\narc: S1_V02S0501 V01N0101\narc: S3_V06S0003 E1_H01W0000\narc: A0 V02S0701\narc: B2 E1_H02W0101\narc: B3 H00R0000\narc: B4 V02N0501\narc: B5 H02W0101\narc: B6 H02E0101\narc: B7 V02N0701\nword: SLICEC.K0.INIT 0011110000000000\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 0011110000000000\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICED.K0.INIT 0011110000000000\nword: SLICED.K1.INIT 1001011010101010\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R14C13:PLC2\narc: E1_H02E0401 V01N0001\narc: N1_V02N0601 H06E0303\narc: V00T0000 E1_H02W0201\narc: W1_H02W0101 E1_H01W0100\narc: B0 E1_H02W0101\narc: B1 V00T0000\narc: B2 V02N0101\narc: B3 V02N0301\narc: F4 F4_SLICE\narc: H01W0000 F4\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0011110000000000\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000001010\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R14C14:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 E1_H01W0100\narc: H00L0000 W1_H02E0001\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0601 S3_V06N0303\narc: W1_H02W0101 S1_V02N0101\narc: C4 E1_H02W0401\narc: C5 H02E0401\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D3 S1_V02N0201\narc: D4 V01N0001\narc: D5 V00B0000\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q4\narc: LSR0 V00T0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: S1_V02S0501 F5\narc: S3_V06S0203 Q4\narc: V00B0000 Q4\narc: V00T0100 F3\narc: V01S0000 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000111100000000\nword: SLICEC.K1.INIT 1111000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R14C15:PLC2\narc: E1_H02E0201 V01N0001\narc: H00L0000 S1_V02N0001\narc: H00L0100 S1_V02N0301\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 E1_H02W0201\narc: V00B0100 H02W0701\narc: W1_H02W0101 E1_H01W0100\narc: A1 V02N0501\narc: B1 S1_V02N0101\narc: C0 H02W0401\narc: C1 H00L0100\narc: CE0 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 V00B0100\narc: D7 H02E0201\narc: E1_H01E0001 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR0 H02E0301\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0101 Q0\narc: S1_V02S0301 F1\narc: S3_V06S0003 Q0\narc: V01S0000 F1\narc: V01S0100 Q0\narc: W1_H02W0201 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000111100000000\nword: SLICEA.K1.INIT 0001000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\n\n.tile R14C16:PLC2\narc: E1_H02E0401 H01E0001\narc: H00L0100 E1_H02W0301\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0401 H01E0001\narc: N1_V02N0601 W3_H06E0303\narc: A5 E1_H01W0000\narc: B5 H00R0000\narc: C4 H01E0001\narc: C5 V02N0201\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D4 H02E0201\narc: D5 V02N0601\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0000 Q4\narc: H01W0100 Q4\narc: LSR1 V00T0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: S3_V06S0203 Q4\narc: V00T0100 F1\narc: V01S0100 Q4\narc: W1_H02W0701 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000111100000000\nword: SLICEC.K1.INIT 0000000100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R14C17:PLC2\narc: H00L0100 H02W0301\narc: H00R0000 V02N0601\narc: C2 H02E0401\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D2 H00R0000\narc: D3 S1_V02N0201\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0000 Q2\narc: LSR0 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: V00T0100 F3\narc: W1_H02W0201 Q2\narc: W3_H06W0103 Q2\nword: SLICEB.K0.INIT 0000111100000000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R14C18:PLC2\narc: W1_H02W0301 S1_V02N0301\n\n.tile R14C2:PLC2\narc: E1_H02E0301 E1_H01W0100\narc: H00L0100 E1_H02W0301\narc: N1_V02N0001 H06W0003\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 S1_V02N0201\narc: V00T0100 N1_V02S0701\narc: B2 V02N0101\narc: C2 H00L0100\narc: CLK0 G_HPBX0100\narc: D2 V00T0100\narc: D3 V01S0100\narc: D5 V00B0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0100 F3\narc: LSR0 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: V00B0100 F5\narc: V01S0100 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R14C3:PLC2\narc: H00R0000 S1_V02N0601\narc: N1_V02N0001 H06W0003\narc: V00B0000 S1_V02N0201\narc: V00T0100 V02N0501\narc: B4 V02N0701\narc: B5 H00R0000\narc: C4 V00T0100\narc: C5 F4\narc: CLK0 G_HPBX0000\narc: D3 V02N0001\narc: D4 V00B0000\narc: D5 H00R0100\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0100 Q5\narc: H01W0000 Q5\narc: H01W0100 F3\narc: LSR0 H02E0301\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: S1_V02S0601 F4\narc: S1_V02S0701 Q5\narc: S3_V06S0203 F4\narc: S3_V06S0303 Q5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0011110011000011\nword: SLICEC.K1.INIT 1100001100111100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R14C4:PLC2\narc: N1_V02N0101 V01N0101\narc: V00B0000 V02N0001\narc: W1_H02W0301 E1_H02W0201\narc: A1 H00L0100\narc: B1 Q1\narc: B2 H01W0100\narc: C1 H00L0000\narc: C2 V02N0601\narc: C3 H00L0100\narc: CLK0 G_HPBX0100\narc: D0 Q0\narc: D1 V02N0201\narc: D2 Q2\narc: D3 V02N0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H00L0000 Q2\narc: H00L0100 Q3\narc: H01W0100 Q3\narc: LSR1 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: S1_V02S0101 Q1\narc: S1_V02S0301 Q3\narc: V01S0000 Q0\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0110110011001100\nword: SLICEB.K0.INIT 0011111111000000\nword: SLICEB.K1.INIT 0000111111110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R14C5:PLC2\narc: E1_H02E0001 V02N0001\narc: V00B0000 V02S0001\narc: V00B0100 V02N0301\narc: W3_H06W0003 V06N0003\narc: B4 V00B0100\narc: C4 S1_V02N0201\narc: CLK0 G_HPBX0100\narc: D4 V02N0401\narc: D5 V02N0601\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: LSR1 V00B0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F5\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R14C6:PLC2\narc: E1_H02E0001 V02S0001\narc: H00L0000 S1_V02N0201\narc: N1_V02N0501 E1_H02W0501\narc: N3_V06N0103 E1_H01W0100\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 E1_H02W0601\narc: V00B0100 S1_V02N0301\narc: W3_H06W0003 E1_H01W0000\narc: B2 V02N0301\narc: C2 H00L0000\narc: CLK0 G_HPBX0100\narc: D1 H02E0001\narc: D2 E1_H02W0201\narc: D3 V00B0100\narc: E1_H02E0301 F1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR1 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00T0100 F3\narc: W1_H02W0201 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R14C7:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: H00L0000 N1_V02S0001\narc: H00L0100 E1_H02W0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S1_V02N0301\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H02W0701\narc: V00B0000 N1_V02S0001\narc: V00B0100 E1_H02W0701\narc: V00T0100 H02W0101\narc: A0 H00L0000\narc: A1 H00L0000\narc: A2 V00B0000\narc: A3 V00B0000\narc: B0 S1_V02N0101\narc: B1 S1_V02N0101\narc: B2 S1_V02N0101\narc: B3 S1_V02N0301\narc: B4 E1_H02W0301\narc: B6 V01S0000\narc: B7 F1\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 N1_V02S0201\narc: C5 F4\narc: C6 E1_H02W0401\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 E1_H02W0001\narc: D2 E1_H02W0001\narc: D3 E1_H02W0001\narc: D4 H02E0001\narc: D5 H02W0001\narc: D6 E1_H02W0201\narc: D7 H00R0100\narc: E1_H01E0001 Q5\narc: E1_H02E0701 F7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: H01W0100 F4\narc: LSR0 H02E0301\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V02N0401 F6\narc: N1_V02N0601 F6\narc: S1_V02S0301 F1\narc: S3_V06S0203 F7\narc: V01S0000 F7\narc: V01S0100 F1\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 0011110011000011\nword: SLICED.K1.INIT 1100001100111100\nword: SLICEC.K0.INIT 0011110000000000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 1001011001101001\nword: SLICEA.K1.INIT 0110100110010110\nword: SLICEB.K0.INIT 0110100110010110\nword: SLICEB.K1.INIT 1001011001101001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R14C8:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 N1_V02S0701\narc: H00L0000 V02N0201\narc: H00R0100 S1_V02N0501\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0601 H02W0601\narc: V00B0000 S1_V02N0201\narc: V00B0100 S1_V02N0301\narc: V00T0100 H02W0101\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 H01E0001\narc: W1_H02W0701 E1_H01W0100\narc: A0 E1_H02W0501\narc: A1 E1_H02W0501\narc: A2 E1_H02W0501\narc: A3 E1_H02W0501\narc: A5 H02E0701\narc: B0 E1_H02W0301\narc: B1 E1_H02W0301\narc: B2 E1_H02W0301\narc: B3 E1_H02W0301\narc: B5 S1_V02N0701\narc: B6 E1_H02W0101\narc: C0 H00L0000\narc: C1 H00L0000\narc: C2 H00L0000\narc: C3 H00L0000\narc: C5 V00B0100\narc: C6 V02N0001\narc: CLK0 G_HPBX0100\narc: D0 V00B0100\narc: D1 V00B0100\narc: D2 V00B0100\narc: D3 V00B0100\narc: D5 V02N0401\narc: D6 V01N0001\narc: D7 V00B0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 F7\narc: LSR1 H02E0501\narc: M0 V00T0100\narc: M1 H00R0100\narc: M2 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: W1_H02W0501 F5\narc: W1_H02W0601 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010010000010\nword: SLICED.K0.INIT 1111110000001100\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0001011101110001\nword: SLICEA.K1.INIT 0111000100010111\nword: SLICEB.K0.INIT 0111000100010111\nword: SLICEB.K1.INIT 0001011101110001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R14C9:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: H00L0100 E1_H02W0301\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: N1_V02N0401 S1_V02N0401\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 E1_H02W0101\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0701\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 E1_H01W0100\narc: A3 V00B0000\narc: B1 H02E0301\narc: B3 S1_V02N0101\narc: B5 H02E0301\narc: B7 H02E0301\narc: C1 H02E0601\narc: C3 H02E0401\narc: C5 H02E0601\narc: C7 H02E0601\narc: CE0 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D3 H00R0000\narc: D5 V02S0401\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q1\narc: H01W0100 Q7\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q7\narc: S1_V02S0301 Q1\narc: V01S0000 Q5\narc: V01S0100 Q5\narc: W1_H02W0101 Q1\narc: W1_H02W0501 Q5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111111100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111111111111100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000100010000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R15C10:PLC2\narc: H00L0000 H02E0001\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0401 S1_V02N0101\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 E1_H01W0100\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 W1_H02E0601\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V06S0203\narc: E1_H01E0001 W3_H06E0003\narc: S3_V06S0003 W3_H06E0003\narc: W1_H02W0001 W3_H06E0003\narc: B4 H00L0000\narc: C4 H02W0601\narc: CLK0 G_HPBX0100\narc: D4 V00B0000\narc: D5 V02N0601\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: LSR0 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q4\narc: V00B0100 F5\nword: SLICEC.K0.INIT 1111110000001100\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R15C11:PLC2\narc: E1_H02E0301 E3_H06W0003\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 E1_H01W0100\narc: W1_H02W0201 V01N0001\narc: W1_H02W0601 H01E0001\narc: A0 H02W0701\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 V01S0000\narc: CLK0 G_HPBX0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0100 Q6\narc: LSR1 H02W0501\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q3\narc: S1_V02S0001 Q2\narc: S1_V02S0401 Q6\narc: S1_V02S0601 Q4\narc: S1_V02S0701 Q7\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V01S0000 Q7\narc: V01S0100 Q6\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R15C12:PLC2\narc: E1_H02E0001 V01N0001\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0701 H06W0203\narc: S3_V06S0303 E1_H01W0100\narc: V00B0100 V02N0301\narc: W1_H02W0501 V01N0101\narc: W1_H02W0701 E1_H02W0601\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H01W0100\narc: B3 Q3\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q2\narc: LSR1 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: N1_V01N0101 Q1\narc: S1_V02S0001 Q0\narc: S1_V02S0101 Q3\narc: S1_V02S0301 Q1\narc: S3_V06S0003 Q3\narc: S3_V06S0103 Q1\narc: V00T0000 Q0\narc: V01S0000 Q2\narc: V01S0100 Q2\narc: W1_H02W0001 Q0\narc: W1_H02W0101 Q1\narc: W1_H02W0301 Q3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000001010\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C13:PLC2\narc: H00L0100 V02N0101\narc: H00R0100 E1_H02W0701\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 W1_H02E0301\narc: S1_V02S0701 H02W0701\narc: W1_H02W0301 W3_H06E0003\narc: B7 V02N0501\narc: C6 E1_H02W0401\narc: C7 E1_H01E0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D5 H02W0201\narc: D6 E1_H01W0100\narc: D7 H00R0100\narc: E1_H01E0101 Q6\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q6\narc: LSR0 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: V00B0100 F5\narc: V01S0000 Q6\narc: V01S0100 F1\narc: W1_H02W0501 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 0000111100000000\nword: SLICED.K1.INIT 0000001100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R15C14:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: H00R0000 V02S0601\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 H06W0003\narc: V00B0000 V02S0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 E1_H01W0100\narc: A0 H00R0000\narc: B2 V02N0101\narc: B3 V01N0001\narc: B4 H01E0101\narc: B5 N1_V01S0000\narc: B6 V00B0000\narc: B7 E1_H02W0301\narc: E1_H01E0001 F3\narc: E1_H02E0701 F7\narc: E3_H06E0303 F6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F4\narc: N1_V01N0001 F5\narc: V01S0000 F2\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C15:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0401 N1_V01S0000\narc: H00L0000 V02N0001\narc: H00R0000 H02W0401\narc: H00R0100 H02E0701\narc: N1_V02N0501 N1_V01S0100\narc: S1_V02S0601 N1_V01S0000\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 H01E0001\narc: B0 V02S0101\narc: B1 N1_V02S0301\narc: B2 E1_H01W0100\narc: B3 H00R0000\narc: B7 V00B0000\narc: C6 V00B0100\narc: C7 E1_H01E0101\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D6 H00R0100\narc: D7 E1_H02W0201\narc: E1_H01E0001 F3\narc: E1_H01E0101 Q6\narc: E1_H02E0001 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q6\narc: LSR1 E1_H02W0501\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F0\narc: S3_V06S0303 Q6\narc: V01S0000 F1\narc: V01S0100 Q6\narc: W1_H02W0701 F7\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 0000111100000000\nword: SLICED.K1.INIT 0011000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R15C16:PLC2\narc: E1_H02E0201 H01E0001\narc: H00L0000 H02W0001\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0301 V01N0101\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 E1_H01W0000\narc: A1 H00L0000\narc: B1 H02E0101\narc: C0 H02E0401\narc: C1 N1_V01S0100\narc: CE0 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 V01S0100\narc: D3 V02N0201\narc: D7 V02N0401\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V02N0201 Q0\narc: S3_V06S0003 Q0\narc: V00T0100 F3\narc: V01S0000 F1\narc: V01S0100 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000111100000000\nword: SLICEA.K1.INIT 0100000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\n\n.tile R15C17:PLC2\narc: H00L0100 H02W0301\narc: N1_V02N0601 H06E0303\narc: W1_H02W0201 H01E0001\narc: W1_H02W0501 H01E0101\narc: C0 W1_H02E0401\narc: CE0 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 V02N0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: H01W0000 Q0\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: V00T0100 F1\narc: W1_H02W0001 Q0\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 0000111100000000\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R15C18:PLC2\narc: W1_H02W0301 V02N0301\n\n.tile R15C2:PLC2\narc: H00R0000 V02N0601\narc: N1_V02N0101 E1_H02W0101\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0103 N1_V01S0100\narc: V00B0000 S1_V02N0201\narc: V00T0000 V02N0601\narc: A0 H00R0000\narc: A1 H00R0000\narc: A2 V00T0000\narc: A3 V00T0000\narc: B0 S1_V02N0101\narc: B1 S1_V02N0101\narc: B2 S1_V02N0301\narc: B3 S1_V02N0301\narc: C0 V02N0401\narc: C1 V02N0401\narc: C2 V02N0401\narc: C3 V02N0401\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02N0001\narc: D2 V02N0001\narc: D3 V02N0001\narc: D5 V00B0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q1\narc: LSR0 V00B0100\narc: M0 H02W0601\narc: M1 E1_H02W0001\narc: M2 H02W0601\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V00B0100 F5\narc: V01S0000 Q1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0011000011110101\nword: SLICEA.K1.INIT 0000010100111111\nword: SLICEB.K0.INIT 1100111100001010\nword: SLICEB.K1.INIT 1111101011000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R15C3:PLC2\narc: H00L0100 V02N0301\narc: H00R0000 V02N0401\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 S1_V02N0701\narc: V00B0100 S1_V02N0101\narc: V00T0100 S1_V02N0701\narc: W1_H02W0601 V01N0001\narc: A0 E1_H02W0501\narc: A3 E1_H02W0501\narc: A4 E1_H02W0501\narc: A7 E1_H02W0501\narc: B0 S1_V02N0101\narc: B2 S1_V02N0101\narc: B3 S1_V02N0101\narc: B4 V00B0100\narc: B6 V00B0100\narc: B7 V00B0100\narc: C0 S1_V02N0401\narc: C1 S1_V02N0401\narc: C2 S1_V02N0401\narc: C3 S1_V02N0401\narc: C4 S1_V02N0001\narc: C5 S1_V02N0201\narc: C6 S1_V02N0001\narc: C7 S1_V02N0201\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 V02N0401\narc: D5 V02N0401\narc: D6 V02N0401\narc: D7 V02N0401\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00T0100\narc: M1 H00L0100\narc: M2 V00T0100\narc: M3 W1_H02E0201\narc: M4 V00T0100\narc: M5 H00L0100\narc: M6 V00T0100\narc: S3_V06S0003 F3\narc: V01S0100 F3\nword: SLICEA.K0.INIT 1111111111010100\nword: SLICEA.K1.INIT 1111111111110000\nword: SLICEB.K0.INIT 1111111111000000\nword: SLICEB.K1.INIT 1111111111010100\nword: SLICEC.K0.INIT 0000000000101011\nword: SLICEC.K1.INIT 0000000000001111\nword: SLICED.K0.INIT 0000000000111111\nword: SLICED.K1.INIT 0000000000101011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R15C4:PLC2\narc: H00L0100 V02S0301\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0601 N1_V01S0000\narc: W1_H02W0001 H01E0001\narc: A3 H00L0100\narc: B3 V02S0101\narc: C2 V02N0401\narc: C3 N1_V01S0100\narc: C7 V02N0201\narc: CLK0 G_HPBX0100\narc: D2 V00T0100\narc: D3 N1_V01S0000\narc: D5 V02N0401\narc: D7 H01W0000\narc: E1_H02E0301 Q3\narc: E3_H06E0003 Q3\narc: E3_H06E0203 F7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q3\narc: LSR0 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 F7\narc: N1_V02N0001 F2\narc: N3_V06N0003 Q3\narc: S1_V02S0301 Q3\narc: S3_V06S0003 Q3\narc: V00B0100 F5\narc: V00T0100 F3\narc: W1_H02W0101 Q3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111111111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 0000010000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R15C5:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 V01N0001\narc: N3_V06N0303 H06W0303\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0501 E1_H02W0401\narc: B0 H02E0301\narc: C0 N1_V01S0100\narc: CLK0 G_HPBX0100\narc: D0 H02W0201\narc: D1 S1_V02N0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: S1_V02S0201 Q0\narc: V00T0100 F1\nword: SLICEA.K0.INIT 1111110000110000\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R15C6:PLC2\narc: E1_H02E0301 V06S0003\narc: H00L0000 V02S0001\narc: H00L0100 V02N0101\narc: H00R0000 V02N0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 E1_H02W0501\narc: S1_V02S0301 W1_H02E0301\narc: V00B0100 V02N0101\narc: V00T0000 H02W0201\narc: V00T0100 E1_H02W0101\narc: A2 H02W0701\narc: A4 H02W0701\narc: A6 V00T0100\narc: B2 F3\narc: B3 H00L0000\narc: B4 V02S0501\narc: B5 H02W0101\narc: B6 V01S0000\narc: C2 V02N0401\narc: C3 E1_H01W0000\narc: C4 N1_V02S0201\narc: C5 V00B0100\narc: C6 E1_H02W0401\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D2 H02E0001\narc: D3 H00R0000\narc: D4 H02E0001\narc: D5 H00R0100\narc: D6 H00L0100\narc: D7 H00R0100\narc: E1_H02E0701 F5\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: H01W0100 F6\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 F5\narc: N1_V02N0601 F6\narc: V01S0000 F7\narc: W1_H02W0201 Q2\nword: SLICEB.K0.INIT 0011110010101010\nword: SLICEB.K1.INIT 1100001100000000\nword: SLICED.K0.INIT 1100101010100011\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 1100001101010101\nword: SLICEC.K1.INIT 1100001100111100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R15C7:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 V02S0401\narc: E1_H02E0701 V02N0701\narc: H00L0100 V02S0301\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: N1_V02N0501 H02W0501\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 E1_H01W0000\narc: S3_V06S0003 H06E0003\narc: S3_V06S0203 H06E0203\narc: V00B0000 V02S0001\narc: V00B0100 V02S0101\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 V02N0701\narc: A0 H00L0100\narc: A3 H00L0100\narc: A4 N1_V01S0100\narc: A5 N1_V01S0100\narc: A6 N1_V01S0100\narc: B0 H00R0100\narc: B3 H00R0100\narc: B4 V02S0701\narc: B5 V02S0701\narc: B6 V02S0701\narc: C0 E1_H02W0401\narc: C3 E1_H02W0401\narc: C4 E1_H02W0601\narc: C5 E1_H02W0601\narc: C6 E1_H02W0601\narc: D0 N1_V02S0001\narc: D3 V00B0100\narc: D4 N1_V02S0601\narc: D5 N1_V02S0601\narc: D6 N1_V02S0601\narc: E1_H01E0001 F3\narc: E1_H02E0101 F3\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M3 H02W0201\narc: M4 V00B0000\narc: M5 H00R0000\narc: M6 V00B0000\narc: N3_V06N0003 F3\narc: S1_V02S0101 F3\nword: SLICED.K0.INIT 1000000011101000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111011111111\nword: SLICEC.K1.INIT 1000000011101000\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 1111111011111111\nword: SLICEA.K0.INIT 1111111011111111\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C8:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0701 W1_H02E0701\narc: H00L0000 S1_V02N0201\narc: H00L0100 V02S0101\narc: H00R0000 V02S0601\narc: H00R0100 W1_H02E0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 H01E0001\narc: S1_V02S0201 H02E0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 H02W0601\narc: V00T0100 H02E0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0401 H01E0001\narc: A0 H02E0701\narc: A2 S1_V02N0701\narc: A3 E1_H02W0501\narc: A4 H02E0701\narc: A5 V00T0100\narc: A6 E1_H02W0701\narc: A7 E1_H02W0501\narc: B0 W1_H02E0301\narc: B1 H00R0100\narc: B2 N1_V02S0301\narc: B3 H01W0100\narc: B4 W1_H02E0301\narc: B5 E1_H02W0101\narc: B6 H02W0301\narc: B7 V01S0000\narc: C0 H02E0401\narc: C1 H00L0100\narc: C2 E1_H02W0601\narc: C3 H00L0000\narc: C4 V00B0100\narc: C5 V02S0201\narc: C6 V02N0001\narc: C7 S1_V02N0201\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 V02S0201\narc: D2 N1_V02S0201\narc: D3 H00R0000\narc: D4 H02E0001\narc: D5 V00B0000\narc: D6 E1_H02W0201\narc: D7 V02S0601\narc: E1_H01E0001 F1\narc: E1_H02E0601 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q3\narc: H01W0100 Q2\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: S1_V02S0501 Q7\narc: V00B0100 F5\narc: V01S0000 Q6\narc: V01S0100 F1\narc: W1_H02W0101 F1\narc: W1_H02W0501 F5\narc: W3_H06W0303 F5\nword: SLICED.K0.INIT 0100111101000100\nword: SLICED.K1.INIT 1000111110001000\nword: SLICEB.K0.INIT 1111010001000100\nword: SLICEB.K1.INIT 1000111110001000\nword: SLICEA.K0.INIT 0011110001010101\nword: SLICEA.K1.INIT 0011110011000011\nword: SLICEC.K0.INIT 0011110010101010\nword: SLICEC.K1.INIT 1001011001101001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R15C9:PLC2\narc: H00R0000 V02N0601\narc: H00R0100 H02E0701\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H01E0001\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0701 V01N0101\narc: V00B0000 S1_V02N0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 N1_V01S0000\narc: A3 E1_H01E0001\narc: B0 V00B0000\narc: B3 V02S0301\narc: C0 E1_H02W0601\narc: C2 H00R0100\narc: C3 N1_V01S0100\narc: CLK0 G_HPBX0100\narc: D0 H00R0000\narc: D1 H02E0201\narc: D2 N1_V02S0001\narc: D3 V02S0001\narc: E1_H01E0001 F2\narc: E1_H01E0101 F2\narc: E1_H02E0001 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V00T0100 F1\narc: V01S0000 F3\narc: W1_H02W0201 F2\narc: W3_H06W0003 F3\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0110100110010110\nword: SLICEA.K0.INIT 1111110000001100\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R16C10:PLC2\narc: H00R0000 H02W0401\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 H01E0101\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H01W0000\narc: V00B0000 V02S0001\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 H01E0101\narc: A0 H00R0000\narc: A2 V02S0501\narc: A3 H02W0701\narc: A4 V00B0000\narc: A5 V02S0101\narc: A6 E1_H02W0701\narc: A7 V02S0301\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R16C11:PLC2\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 V02S0701\narc: E3_H06E0203 N3_V06S0203\narc: H00L0000 V02S0001\narc: N1_V02N0501 H02W0501\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: V00T0000 V02S0601\narc: V00T0100 H02W0101\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0701 V02S0701\narc: E1_H02E0201 W3_H06E0103\narc: H01W0000 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: A4 H02W0701\narc: A5 V00B0000\narc: A6 H00L0000\narc: A7 H00L0000\narc: B4 V01S0000\narc: B5 N1_V02S0701\narc: B6 N1_V01S0000\narc: B7 N1_V02S0701\narc: C4 V00T0100\narc: C5 V00T0000\narc: C6 V00B0100\narc: C7 V00T0000\narc: D4 H02W0201\narc: D5 N1_V02S0401\narc: D6 V02S0401\narc: D7 N1_V02S0401\narc: E1_H01E0001 F6\narc: E1_H01E0101 F7\narc: E1_H02E0501 F7\narc: F0 F0_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F4\narc: N1_V01N0001 F0\narc: V01S0000 F5\nword: SLICED.K0.INIT 0001000000000000\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0100000000000000\nword: SLICEC.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R16C12:PLC2\narc: H00L0000 V02S0001\narc: H00L0100 V02S0101\narc: H00R0100 H02E0501\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H02W0601\narc: V00B0000 V02S0001\narc: V00B0100 V02S0101\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0701 N1_V01S0100\narc: A0 N1_V02S0501\narc: A3 H02E0701\narc: A5 V02S0301\narc: A6 F7\narc: A7 N1_V01S0100\narc: B0 F3\narc: B3 H00L0000\narc: B5 H02E0301\narc: B6 V02N0501\narc: B7 V01S0000\narc: C0 H02E0401\narc: C1 N1_V01N0001\narc: C3 H00L0100\narc: C5 H02E0601\narc: C6 E1_H02W0401\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D0 H01E0101\narc: D1 H02E0201\narc: D3 N1_V01S0000\narc: D5 V00B0000\narc: D6 H02W0201\narc: D7 H00R0100\narc: E1_H01E0101 F0\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F0\narc: N1_V01N0101 F1\narc: N1_V02N0001 F0\narc: N1_V02N0301 F1\narc: N3_V06N0203 Q7\narc: N3_V06N0303 Q6\narc: V01S0000 F5\narc: V01S0100 Q7\narc: W1_H02W0501 Q7\narc: W3_H06W0203 Q7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0100000000000000\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0100000000000000\nword: SLICEA.K0.INIT 1011111111111111\nword: SLICEA.K1.INIT 0000111111111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R16C13:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0601 V01N0001\narc: H00R0100 H02W0501\narc: N1_V02N0101 H01E0101\narc: N1_V02N0501 H02W0501\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 H02W0701\narc: V00B0000 V02N0201\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0601 E1_H01W0000\narc: A0 E1_H02W0701\narc: B2 H00R0100\narc: B3 E1_H01W0100\narc: B4 N1_V01S0000\narc: B5 V02N0701\narc: B6 V00B0000\narc: B7 V02S0701\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 0011110000000000\nword: SLICEC.K1.INIT 0011110000000000\nword: SLICED.K0.INIT 0011110000000000\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 0011110000000000\nword: SLICEB.K1.INIT 0011110000000000\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R16C14:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 S1_V02N0701\narc: H00R0100 V02N0701\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H06E0103\narc: S1_V02S0401 V01N0001\narc: S1_V02S0701 H06E0203\narc: V00T0000 V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0701 S1_V02N0701\narc: W3_H06W0303 N3_V06S0303\narc: A7 V00T0100\narc: B0 H00R0100\narc: B1 V02N0301\narc: B2 V02S0101\narc: B3 V02S0301\narc: B7 N1_V02S0501\narc: C6 V00T0000\narc: C7 E1_H02W0401\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D6 V02S0601\narc: D7 V00B0000\narc: E1_H02E0601 Q6\narc: F4 F4_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 Q6\narc: LSR1 H02E0301\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: V00B0000 Q6\narc: V01S0100 F7\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 0000111100000000\nword: SLICED.K1.INIT 0100000000000000\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0011110000000000\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R16C15:PLC2\narc: E1_H02E0101 V01N0101\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 N1_V01S0000\narc: S1_V02S0201 V01N0001\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 W1_H02E0601\narc: V00B0100 H02E0501\narc: W1_H02W0701 E1_H02W0701\narc: B1 V00T0000\narc: C0 V02S0601\narc: C1 H02E0601\narc: CE0 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 V00B0100\narc: D3 E1_H02W0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q0\narc: LSR0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V02N0301 F1\narc: V00T0000 Q0\narc: V00T0100 F3\narc: W1_H02W0101 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000111100000000\nword: SLICEA.K1.INIT 0000001100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R16C16:PLC2\narc: E1_H02E0401 V02N0401\narc: H00R0000 V02N0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 E1_H01W0000\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0601 V01N0001\narc: V00T0000 V02N0401\narc: W1_H02W0401 N1_V01S0000\narc: A0 W1_H02E0701\narc: B2 H00R0100\narc: B3 Q3\narc: B4 H02E0101\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 V02N0501\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q6\narc: H01W0100 F4\narc: LSR0 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 F2\narc: S1_V02S0101 Q3\narc: S1_V02S0501 Q7\narc: S1_V02S0701 Q5\narc: S3_V06S0303 Q6\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V01S0000 Q3\narc: V01S0100 Q7\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R16C17:PLC2\narc: H00R0100 V02N0501\narc: V00B0000 H02E0401\narc: H01W0000 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H01W0100\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: H01W0100 Q2\narc: LSR1 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: S1_V02S0001 Q0\narc: S1_V02S0301 Q1\narc: V00T0000 Q0\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000001010\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R16C18:PLC2\narc: N1_V02N0301 W3_H06E0003\n\n.tile R16C2:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0201 V02N0201\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 V02N0001\narc: H00R0000 V02N0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 H06W0103\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0401 H01E0001\narc: V00T0000 V02N0401\narc: V00T0100 V02N0701\narc: A0 S1_V02N0701\narc: A3 S1_V02N0701\narc: A5 H02W0701\narc: A6 H02W0701\narc: B0 V00T0000\narc: B2 H00R0000\narc: B3 H00R0000\narc: B4 H00R0000\narc: B5 H00R0000\narc: B6 V00T0000\narc: C0 V02S0601\narc: C1 V02S0601\narc: C2 V02S0601\narc: C3 V02S0601\narc: C4 V02S0001\narc: C5 V02S0001\narc: C6 V02S0001\narc: C7 V02S0001\narc: D0 H02E0001\narc: D1 H02E0001\narc: D2 H02E0001\narc: D3 H02E0001\narc: D4 H02E0001\narc: D5 H02E0001\narc: D6 H02E0001\narc: D7 H02E0001\narc: E1_H02E0101 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00L0000\narc: M2 V00T0100\narc: M3 H00R0100\narc: M4 V00T0100\narc: M5 H00L0000\narc: M6 V00T0100\nword: SLICEA.K0.INIT 0111111001110111\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 1111110011111111\nword: SLICEB.K1.INIT 0111001001110111\nword: SLICEC.K0.INIT 1100111111111111\nword: SLICEC.K1.INIT 0001101110111011\nword: SLICED.K0.INIT 1101101110111011\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R16C3:PLC2\narc: E1_H02E0601 V02N0601\narc: H00L0000 E1_H02W0001\narc: H00L0100 H02E0101\narc: H00R0100 S1_V02N0501\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 V01N0001\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0701 N1_V02S0601\narc: V00T0000 E1_H02W0001\narc: V00T0100 N1_V02S0701\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 N1_V02S0701\narc: A1 H00L0000\narc: A3 V00T0000\narc: A6 V00T0100\narc: B1 V00B0000\narc: B3 H00R0000\narc: B6 S1_V02N0701\narc: C1 V02N0601\narc: C3 V02N0601\narc: C6 E1_H01E0101\narc: C7 E1_H02W0401\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 H02E0001\narc: D2 E1_H02W0201\narc: D3 H02E0001\narc: D5 H02E0201\narc: D6 H02E0001\narc: D7 H00L0100\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q7\narc: E1_H02E0501 Q7\narc: E3_H06E0303 F6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H01W0000 F1\narc: H01W0100 F6\narc: LSR1 V00B0100\narc: M0 E1_H02W0601\narc: M1 H00R0100\narc: M2 E1_H02W0601\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q7\narc: V00B0000 F6\narc: V00B0100 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 0000000000000001\nword: SLICED.K1.INIT 1111000000001111\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0101010001000101\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1000101010101000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R16C4:PLC2\narc: E1_H02E0601 S1_V02N0601\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02W0601\narc: H00R0100 H02E0501\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 E1_H01W0000\narc: V00B0000 H02W0601\narc: V00T0000 H02W0001\narc: A0 H01E0001\narc: A3 H01E0001\narc: A4 W1_H02E0701\narc: A7 W1_H02E0701\narc: B0 E1_H01W0100\narc: B3 E1_H01W0100\narc: B4 H00R0000\narc: B7 V00B0000\narc: C0 V02N0601\narc: C3 V02N0601\narc: C4 H02E0601\narc: C7 H02E0601\narc: D0 W1_H02E0001\narc: D3 W1_H02E0001\narc: D4 W1_H02E0001\narc: D7 W1_H02E0001\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H00L0100\narc: M2 V00T0000\narc: M3 H00R0100\narc: M4 V00T0000\narc: M5 H00L0100\narc: M6 V00T0000\nword: SLICEA.K0.INIT 0000010001000000\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 0100000000000100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1011111111111011\nword: SLICEC.K0.INIT 1111101110111111\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R16C5:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: H00L0100 V02N0301\narc: H00R0000 V02N0601\narc: N1_V02N0201 E1_H01W0000\narc: S1_V02S0201 E1_H02W0201\narc: V00B0000 H02E0601\narc: V00B0100 S1_V02N0301\narc: V00T0000 E1_H02W0001\narc: W1_H02W0401 H01E0001\narc: A2 E1_H02W0701\narc: A3 E1_H02W0501\narc: A6 E1_H02W0701\narc: A7 E1_H02W0501\narc: B1 V02N0101\narc: B2 H00R0000\narc: B3 H00R0000\narc: B6 V00T0000\narc: B7 V00T0000\narc: C1 H00L0100\narc: C2 V02N0401\narc: C3 V02N0401\narc: C6 S1_V02N0201\narc: C7 S1_V02N0201\narc: CLK0 V00B0000\narc: D0 V02N0201\narc: D1 V02N0201\narc: D2 E1_H02W0001\narc: D3 E1_H02W0001\narc: D6 V02N0601\narc: D7 V02N0601\narc: E1_H02E0301 Q1\narc: E3_H06E0103 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q1\narc: H01W0100 F6\narc: M2 V00B0100\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: N1_V01N0001 Q1\narc: N3_V06N0103 Q1\narc: S3_V06S0103 Q1\narc: V01S0000 Q1\narc: V01S0100 F0\narc: W1_H02W0001 F2\narc: W1_H02W0201 F2\narc: W1_H02W0601 F6\narc: W3_H06W0103 Q1\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 1111111111000000\nword: SLICED.K0.INIT 0001010000101000\nword: SLICED.K1.INIT 1100001000000001\nword: SLICEB.K0.INIT 0111000101110111\nword: SLICEB.K1.INIT 0011001101110001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R16C6:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0701 E3_H06W0203\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 E1_H01W0000\narc: V00T0100 H02E0301\narc: W3_H06W0203 E1_H01W0000\narc: B2 V02S0301\narc: C2 N1_V02S0601\narc: CLK0 G_HPBX0100\narc: D2 S1_V02N0001\narc: D3 V00T0100\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0000 Q2\narc: H01W0100 F3\narc: LSR0 H02E0501\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R16C7:PLC2\narc: E1_H02E0301 H01E0101\narc: H00L0000 V02N0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 V02N0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0001 V01N0001\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H02E0701\narc: V00B0000 V02N0001\narc: V00B0100 S1_V02N0101\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 V02N0701\narc: A0 E1_H02W0501\narc: A2 E1_H02W0501\narc: A3 E1_H02W0501\narc: A4 E1_H02W0501\narc: A6 E1_H02W0501\narc: A7 E1_H02W0501\narc: B0 V02N0101\narc: B1 H00R0100\narc: B2 V02N0101\narc: B3 V02N0301\narc: B4 V02N0501\narc: B6 V02N0701\narc: B7 V02N0701\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V00B0100\narc: C6 V00B0100\narc: C7 V00B0100\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 V02N0401\narc: D5 H00R0100\narc: D6 V02N0601\narc: D7 V02N0601\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00B0000\narc: M1 H02W0001\narc: M2 V00B0000\narc: M3 H00L0000\narc: M4 V00B0000\narc: M5 H02W0001\narc: M6 V00B0000\narc: W3_H06W0003 F3\nword: SLICEC.K0.INIT 0101010101010001\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 0100010101010101\nword: SLICED.K1.INIT 0101010101010001\nword: SLICEA.K0.INIT 0101010101010100\nword: SLICEA.K1.INIT 0011000000110011\nword: SLICEB.K0.INIT 0101000101010101\nword: SLICEB.K1.INIT 0101010101010100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R16C8:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0601 E3_H06W0303\narc: H00L0100 H02W0101\narc: H00R0000 V02N0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 E1_H01W0000\narc: V00B0000 V02S0201\narc: V00T0000 V02S0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0401 E1_H01W0000\narc: A2 V00B0000\narc: B1 V00T0000\narc: B2 H01W0100\narc: B3 N1_V02S0301\narc: B5 V02S0701\narc: B7 V02S0701\narc: C1 S1_V02N0601\narc: C2 N1_V02S0401\narc: C3 S1_V02N0601\narc: C5 V00T0100\narc: C7 V00T0100\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D2 V00B0100\narc: D3 H02W0001\narc: D5 H00L0100\narc: D7 H00R0100\narc: E1_H01E0001 Q3\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: H01W0100 Q3\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F2\narc: N1_V02N0301 Q3\narc: N1_V02N0501 Q7\narc: S1_V02S0301 Q1\narc: S1_V02S0501 Q5\narc: V00B0100 Q7\narc: V01S0000 Q1\narc: W1_H02W0101 Q3\narc: W1_H02W0301 Q1\narc: W1_H02W0701 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111111111111100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111111100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111100\nword: SLICEB.K0.INIT 1000000000000000\nword: SLICEB.K1.INIT 1111111111111100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R16C9:PLC2\narc: H00L0000 H02E0201\narc: H00L0100 V02N0101\narc: H00R0000 V02N0601\narc: H00R0100 V02N0501\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H06W0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 N3_V06S0003\narc: V00B0000 H02E0601\narc: V00B0100 E1_H02W0501\narc: V00T0100 V02N0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0501 W3_H06E0303\narc: A0 H00L0100\narc: A2 H00L0100\narc: A3 V02N0501\narc: A4 V02S0301\narc: A5 V00T0100\narc: A6 H02W0501\narc: B0 V00B0000\narc: B1 V00T0000\narc: B2 S1_V02N0101\narc: B3 H01W0100\narc: B4 H02E0101\narc: B5 V02S0701\narc: B6 N1_V01S0000\narc: B7 H02W0101\narc: C0 V02N0401\narc: C1 H00R0100\narc: C2 H00L0000\narc: C3 H02W0401\narc: C4 V02N0201\narc: C5 H02W0401\narc: C6 S1_V02N0001\narc: C7 V02S0201\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V00B0100\narc: D2 H02W0001\narc: D3 H00R0000\narc: D4 E1_H02W0201\narc: D5 V02N0601\narc: D6 S1_V02N0601\narc: D7 E1_H02W0001\narc: E1_H01E0001 Q7\narc: E1_H01E0101 Q7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: H01W0100 Q2\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q4\narc: N1_V02N0601 Q6\narc: V00T0000 Q0\narc: V01S0000 Q3\narc: W1_H02W0701 Q7\narc: W3_H06W0103 Q1\nword: SLICED.K0.INIT 1100001101010101\nword: SLICED.K1.INIT 0000000011111100\nword: SLICEC.K0.INIT 0100111101000100\nword: SLICEC.K1.INIT 1000111110001000\nword: SLICEA.K0.INIT 1111010001000100\nword: SLICEA.K1.INIT 1100000011111111\nword: SLICEB.K0.INIT 1111010001000100\nword: SLICEB.K1.INIT 1000111110001000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R17C10:PLC2\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V02S0401\narc: E3_H06E0303 V06S0303\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0501 N3_V06S0303\narc: S1_V02S0701 H02W0701\narc: S3_V06S0203 E1_H01W0000\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 V06S0303\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0303 V06S0303\narc: B6 W1_H02E0301\narc: C6 S1_V02N0001\narc: CLK0 G_HPBX0100\narc: D6 E1_H01W0100\narc: D7 V02S0601\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q6\narc: LSR1 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: V00B0100 F7\nword: SLICED.K0.INIT 1111110000001100\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R17C11:PLC2\narc: E1_H02E0201 V06S0103\narc: H00L0000 H02W0201\narc: H00R0000 V02N0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 V01N0001\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 H02W0201\narc: V00T0100 V02S0701\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 N1_V02S0701\narc: A0 H00L0000\narc: A2 V00B0000\narc: A3 H02W0701\narc: A5 V00T0000\narc: A7 V00T0100\narc: B0 V02S0301\narc: B1 N1_V02S0301\narc: B2 H02E0301\narc: B3 V02S0101\narc: B5 N1_V02S0501\narc: B7 H02W0301\narc: C0 H00R0100\narc: C1 H02E0401\narc: C2 H00L0100\narc: C3 N1_V01N0001\narc: C5 H02W0601\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H02E0201\narc: D2 H02E0201\narc: D3 H00R0000\narc: D5 H02W0001\narc: D7 V02S0601\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: H01W0000 Q0\narc: H01W0100 Q1\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F5\narc: N3_V06N0003 Q0\narc: V01S0000 Q0\narc: V01S0100 F7\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0111111100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001111100000000\nword: SLICEB.K0.INIT 0101010111000011\nword: SLICEB.K1.INIT 0000011100000000\nword: SLICEA.K0.INIT 1110111100000000\nword: SLICEA.K1.INIT 0011001100001111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\n\n.tile R17C12:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 E1_H01W0100\narc: N1_V02N0501 E1_H02W0501\narc: S1_V02S0701 E1_H02W0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 N1_V02S0701\n\n.tile R17C13:PLC2\narc: H00R0000 V02N0601\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0701 H02W0701\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0701 H06W0203\narc: V00T0000 E1_H02W0001\narc: A0 V02S0701\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H02E0301\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 V02S0501\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q3\narc: E1_H02E0001 Q2\narc: E1_H02E0301 Q3\narc: E1_H02E0401 Q4\narc: E1_H02E0501 Q7\narc: E1_H02E0601 Q6\narc: E1_H02E0701 Q5\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0100 Q4\narc: LSR1 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q7\narc: S1_V02S0501 Q7\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V01S0000 Q6\narc: V01S0100 Q2\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R17C14:PLC2\narc: E1_H02E0401 W1_H02E0101\narc: H00R0100 E1_H02W0501\narc: N1_V02N0301 H02W0301\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 H01E0101\narc: S1_V02S0701 H02E0701\narc: V00B0000 E1_H02W0601\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0701 V06S0203\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H01W0100\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q1\narc: E1_H01E0101 Q0\narc: E1_H02E0001 Q0\narc: E1_H02E0101 Q1\narc: E1_H02E0201 Q2\narc: E1_H02E0301 Q3\narc: E1_H02E0601 Q4\narc: E1_H02E0701 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q3\narc: H01W0100 Q2\narc: LSR0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q2\narc: S1_V02S0101 Q1\narc: S1_V02S0201 Q0\narc: V00B0100 Q5\narc: V00T0000 Q0\narc: V01S0000 Q4\narc: V01S0100 Q5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001010\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R17C15:PLC2\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 W1_H02E0601\narc: H00L0000 H02W0201\narc: H00R0000 H02W0401\narc: H00R0100 W1_H02E0501\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 W1_H02E0701\narc: V00B0000 H02E0601\narc: V00B0100 W1_H02E0701\narc: V00T0000 W1_H02E0001\narc: V00T0100 W1_H02E0301\narc: W1_H02W0301 V06S0003\narc: A1 V02S0501\narc: A3 H00L0100\narc: A4 E1_H01W0000\narc: A5 V00B0000\narc: B1 Q1\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 E1_H02W0301\narc: B7 V00T0000\narc: C0 H02E0401\narc: C1 H02W0601\narc: C3 H00L0000\narc: C4 H01E0001\narc: C5 E1_H01E0101\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 H00R0000\narc: D3 V02S0201\narc: D4 V02S0401\narc: D5 H01W0000\narc: D7 V02S0601\narc: E1_H01E0001 F0\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: H01W0000 F4\narc: M2 E1_H02W0601\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q1\narc: N3_V06N0003 F0\narc: S1_V02S0201 F2\narc: V01S0100 Q1\narc: W1_H02W0001 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000011\nword: SLICEA.K0.INIT 1111000011111111\nword: SLICEA.K1.INIT 1111101011111100\nword: SLICEC.K0.INIT 1001000000001001\nword: SLICEC.K1.INIT 1001000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1001000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R17C16:PLC2\narc: H00L0000 W1_H02E0201\narc: H00L0100 W1_H02E0301\narc: H00R0100 V02S0701\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 N1_V01S0100\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 W1_H02E0701\narc: V00B0100 V02S0101\narc: V00T0000 H02W0001\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 V06S0203\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0203 V06S0203\narc: A1 H00L0100\narc: A2 V00T0000\narc: A5 N1_V02S0301\narc: A6 H02E0501\narc: A7 W1_H02E0701\narc: B1 V00T0000\narc: B2 W1_H02E0301\narc: B3 H00L0000\narc: B4 V01S0000\narc: B5 H02E0301\narc: B6 V02S0701\narc: B7 H02W0101\narc: C1 H00R0100\narc: C2 H02E0601\narc: C3 N1_V01S0100\narc: C4 S1_V02N0001\narc: C5 H01E0001\narc: C6 V00B0100\narc: C7 V02N0201\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0001\narc: D2 N1_V01S0000\narc: D3 V00T0100\narc: D4 V02N0601\narc: D5 V00B0000\narc: D6 V02N0401\narc: D7 V02S0601\narc: E1_H01E0001 F3\narc: E1_H01E0101 F4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q5\narc: H01W0100 Q5\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F6\narc: N1_V02N0601 F4\narc: N1_V02N0701 Q5\narc: N3_V06N0203 F4\narc: V00B0000 F4\narc: V00T0100 F1\narc: V01S0000 F7\narc: W1_H02W0201 F2\narc: W1_H02W0401 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1011000010111011\nword: SLICEC.K0.INIT 1100111100000000\nword: SLICEC.K1.INIT 1111101011111100\nword: SLICED.K0.INIT 1011000010111011\nword: SLICED.K1.INIT 1001000000000000\nword: SLICEB.K0.INIT 1011000010111011\nword: SLICEB.K1.INIT 1100001100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R17C17:PLC2\narc: N1_V02N0501 H01E0101\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 V02S0301\narc: W1_H02W0601 H01E0001\n\n.tile R17C2:PLC2\narc: E1_H02E0601 E1_H01W0000\narc: H00R0000 H02W0401\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 H06W0103\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0201 H06W0103\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 E1_H01W0100\narc: V00B0000 N1_V02S0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02E0001\narc: A0 H02W0501\narc: A1 H02W0501\narc: A2 H02W0501\narc: A3 H02W0501\narc: A4 H02W0501\narc: A5 H02W0501\narc: A6 H02W0501\narc: A7 H02W0501\narc: B0 H02W0301\narc: B1 H02W0301\narc: B2 H02W0301\narc: B3 H02W0301\narc: B4 H02W0301\narc: B5 H02W0301\narc: B6 H02W0301\narc: B7 H02W0301\narc: C0 V02S0401\narc: C1 V02S0401\narc: C2 V02S0401\narc: C3 V02S0401\narc: C4 V02N0001\narc: C5 V00T0000\narc: C6 V00T0000\narc: C7 V00T0000\narc: D0 N1_V02S0001\narc: D1 N1_V02S0001\narc: D2 N1_V02S0001\narc: D3 N1_V02S0001\narc: D4 V00B0000\narc: D5 N1_V02S0601\narc: D6 V00B0000\narc: D7 V00B0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: M3 E1_H02W0201\narc: M4 V00B0100\narc: M5 H00R0000\narc: M6 V00B0100\narc: N1_V02N0101 F3\narc: N1_V02N0301 F3\nword: SLICEA.K0.INIT 1100111011101110\nword: SLICEA.K1.INIT 1110111011001110\nword: SLICEB.K0.INIT 1000110011001100\nword: SLICEB.K1.INIT 1100110010001100\nword: SLICED.K0.INIT 1110000000000000\nword: SLICED.K1.INIT 0000000011100000\nword: SLICEC.K0.INIT 0000100010001000\nword: SLICEC.K1.INIT 1000100000001000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R17C3:PLC2\narc: E1_H02E0601 S1_V02N0601\narc: H00L0100 H02W0101\narc: H00R0000 V02N0401\narc: H00R0100 V02S0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H06W0203\narc: V00T0000 V02N0401\narc: V00T0100 W1_H02E0301\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 V06S0303\narc: A0 H02W0501\narc: A1 H02W0501\narc: A2 H02W0501\narc: A3 H02W0501\narc: A4 W1_H02E0701\narc: A5 W1_H02E0701\narc: B0 V00T0000\narc: B1 V00T0000\narc: B2 H00R0000\narc: B3 H00R0000\narc: B4 E1_H02W0301\narc: B5 E1_H02W0101\narc: B6 V02S0501\narc: C0 V02N0601\narc: C1 V02N0601\narc: C2 V02N0601\narc: C3 V02N0601\narc: C4 V02N0201\narc: C5 V02N0201\narc: C6 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 H02W0201\narc: D2 H02W0201\narc: D3 H02W0201\narc: D4 H00L0100\narc: D5 H00L0100\narc: D6 V02S0401\narc: D7 E1_H02W0001\narc: E1_H01E0001 F4\narc: E1_H01E0101 F6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q1\narc: H01W0100 F4\narc: LSR1 V00B0100\narc: M0 H02E0601\narc: M1 H00R0100\narc: M2 H02E0601\narc: M4 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0001 F6\narc: V00B0100 F7\narc: V01S0100 Q1\narc: W1_H02W0301 Q1\nword: SLICED.K0.INIT 0011110000000000\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1011111001000001\nword: SLICEA.K1.INIT 0100000110111110\nword: SLICEB.K0.INIT 1101011100101000\nword: SLICEB.K1.INIT 0010100011010111\nword: SLICEC.K0.INIT 1110101111010100\nword: SLICEC.K1.INIT 0001010000101011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R17C4:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0501 E3_H06W0303\narc: H00L0000 E1_H02W0201\narc: H00L0100 V02N0101\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02N0701\narc: N1_V02N0601 H02E0601\narc: S1_V02S0001 H02W0001\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 H02W0601\narc: V00B0000 E1_H02W0401\narc: V00B0100 N1_V02S0301\narc: V00T0000 H02W0201\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0501 H01E0101\narc: A0 V02N0701\narc: A3 V02N0701\narc: B0 V00B0000\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0000\narc: B4 V00B0100\narc: C0 H00L0000\narc: C1 E1_H02W0401\narc: C2 E1_H02W0601\narc: C3 H00L0000\narc: C4 V00T0000\narc: CLK0 G_HPBX0100\narc: D0 V02N0201\narc: D1 E1_H02W0001\narc: D2 E1_H02W0001\narc: D3 V02N0201\narc: D4 E1_H01W0100\narc: D5 V02N0401\narc: E1_H01E0001 F1\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F1\narc: LSR1 H02W0501\narc: M0 H02E0601\narc: M1 H00L0100\narc: M2 H02E0601\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: S3_V06S0203 Q4\narc: V01S0000 Q4\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0001011111101000\nword: SLICEA.K1.INIT 1100111111110011\nword: SLICEB.K0.INIT 0011111111111100\nword: SLICEB.K1.INIT 1101010000101011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R17C5:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0601 E1_H01W0000\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 H01E0001\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0001 E3_H06W0003\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 V02S0201\narc: V00B0100 V02N0101\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 E1_H02W0301\narc: W3_H06W0103 E3_H06W0003\narc: A5 V00B0000\narc: B5 H02W0301\narc: C5 V00B0100\narc: CLK0 G_HPBX0000\narc: D5 H02E0001\narc: F5 F5_SLICE\narc: H01W0100 Q5\narc: MUXCLK2 CLK0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100001110101010\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R17C6:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 V02S0201\narc: H00L0100 H02W0301\narc: H00R0000 V02S0401\narc: H00R0100 V02N0701\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0301 E1_H01W0100\narc: V00B0000 H02W0601\narc: V00B0100 V02N0301\narc: V00T0100 H02W0101\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 E1_H01W0000\narc: A0 S1_V02N0501\narc: A1 S1_V02N0501\narc: A2 S1_V02N0501\narc: A3 S1_V02N0701\narc: A4 V02N0101\narc: A5 V02N0101\narc: A6 H00R0000\narc: B0 V01N0001\narc: B1 V01N0001\narc: B2 V01N0001\narc: B3 V01N0001\narc: B4 S1_V02N0701\narc: B5 S1_V02N0701\narc: B6 V00B0100\narc: C0 V02N0601\narc: C1 V02N0601\narc: C2 V02N0401\narc: C3 V02N0601\narc: C4 V01N0101\narc: C5 V01N0101\narc: C6 H02E0601\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 V02N0201\narc: D2 V02N0201\narc: D3 V02N0201\narc: D4 H00R0100\narc: D5 H00R0100\narc: D6 H02E0001\narc: D7 H02W0201\narc: E1_H01E0001 F4\narc: E1_H01E0101 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F4\narc: M0 H02W0601\narc: M1 H00L0100\narc: M2 H02W0601\narc: M4 V00B0000\narc: MUXCLK3 CLK0\narc: N3_V06N0203 F7\narc: V01S0000 Q6\narc: W1_H02W0101 F1\narc: W3_H06W0103 F1\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 0011110010101010\nword: SLICED.K1.INIT 1111000000001111\nword: SLICEC.K0.INIT 0110100110010110\nword: SLICEC.K1.INIT 1001011001101001\nword: SLICEB.K0.INIT 0000011001100000\nword: SLICEB.K1.INIT 0110000000000110\nword: SLICEA.K0.INIT 1001000000001001\nword: SLICEA.K1.INIT 0000100110010000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R17C7:PLC2\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 H02E0001\narc: H00R0000 H02W0401\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 H01E0101\narc: S1_V02S0701 V01N0101\narc: V00B0000 V02N0201\narc: V00B0100 H02W0501\narc: V00T0000 V02N0401\narc: V00T0100 V02S0701\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0601 V02S0601\narc: A6 N1_V01N0101\narc: B0 V00B0000\narc: B1 V00T0000\narc: B4 V02N0701\narc: B5 H00R0000\narc: B6 V00B0100\narc: B7 V00T0000\narc: C0 H00L0100\narc: C1 H02W0601\narc: C4 V02N0001\narc: C5 H02W0601\narc: C6 V02N0001\narc: C7 H02W0601\narc: CE0 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 E1_H02W0001\narc: D4 H00R0100\narc: D5 N1_V02S0401\narc: D6 H02W0201\narc: D7 H02E0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: H00R0100 Q5\narc: H01W0000 F0\narc: H01W0100 Q5\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q7\narc: N1_V01N0101 Q7\narc: N1_V02N0401 F4\narc: N1_V02N0601 F4\narc: S1_V02S0101 Q1\narc: S1_V02S0401 F6\narc: S1_V02S0501 Q5\narc: S1_V02S0601 F4\narc: V01S0000 Q1\narc: V01S0100 Q5\narc: W1_H02W0301 Q1\narc: W1_H02W0401 F4\narc: W3_H06W0203 F4\nword: SLICEA.K0.INIT 1100001100111100\nword: SLICEA.K1.INIT 1111111111111100\nword: SLICEC.K0.INIT 1100001100111100\nword: SLICEC.K1.INIT 1111111111111100\nword: SLICED.K0.INIT 0111000100010111\nword: SLICED.K1.INIT 1111111111111100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R17C8:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0701 N3_V06S0203\narc: H00R0000 H02W0601\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0101 H06W0103\narc: V00B0100 V02S0101\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 V02N0601\narc: B0 H02W0301\narc: C0 H02E0601\narc: CLK0 G_HPBX0100\narc: D0 H00R0000\narc: D1 V00B0100\narc: E1_H02E0001 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: V00T0100 F1\nword: SLICEA.K0.INIT 1111110000001100\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R17C9:PLC2\narc: H00L0000 H02W0201\narc: H00L0100 N1_V02S0101\narc: H00R0000 H02W0401\narc: H00R0100 V02N0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0601 N1_V01S0000\narc: V00B0000 V02S0001\narc: V00B0100 V02N0301\narc: V00T0000 H02W0201\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V01N0001\narc: W1_H02W0301 E1_H01W0100\narc: A2 V02N0501\narc: A3 H02W0501\narc: A4 H02E0701\narc: A5 H02W0501\narc: B2 V02S0301\narc: B3 V02S0101\narc: B4 H02W0101\narc: B5 H02E0101\narc: B7 V00B0100\narc: C2 V02N0401\narc: C3 H00L0000\narc: C4 H02W0401\narc: C5 V00T0000\narc: C7 W1_H02E0401\narc: CLK0 G_HPBX0000\narc: D2 H00R0000\narc: D3 V01S0100\narc: D4 V00B0000\narc: D5 H00R0100\narc: D6 H02E0201\narc: D7 H00L0100\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q4\narc: M6 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q3\narc: N1_V01N0101 Q2\narc: V01S0000 Q5\narc: W1_H02W0601 Q6\nword: SLICEB.K0.INIT 1111010001000100\nword: SLICEB.K1.INIT 1000111110001000\nword: SLICEC.K0.INIT 1111010001000100\nword: SLICEC.K1.INIT 1000111110001000\nword: SLICED.K0.INIT 1111111100000000\nword: SLICED.K1.INIT 0011110011000011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R18C10:PLC2\narc: H00R0000 V02N0401\narc: N1_V02N0401 N1_V01S0000\narc: V00T0000 E1_H02W0201\narc: V00T0100 E1_H02W0301\narc: W1_H02W0501 N1_V02S0501\narc: A0 H00R0000\narc: A2 V02N0701\narc: A3 V02S0701\narc: A4 H02W0701\narc: A5 V00T0000\narc: A6 H02W0501\narc: A7 V00T0100\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R18C11:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: N1_V02N0001 H02W0001\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 E1_H02W0601\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 V06S0203\narc: F0 F0_SLICE\narc: N1_V01N0001 F0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R18C12:PLC2\narc: H00R0000 N1_V02S0601\narc: H00R0100 N1_V02S0501\narc: V00B0100 H02W0701\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 V06S0003\narc: A0 V02N0701\narc: B2 H00R0100\narc: B3 H00R0000\narc: B4 V02N0501\narc: B5 V02S0701\narc: B6 H02E0101\narc: B7 V00B0100\nword: SLICED.K0.INIT 0011110000000000\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 0011110000000000\nword: SLICEB.K1.INIT 0011110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R18C13:PLC2\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0203 N1_V01S0000\narc: H00R0100 V02S0701\narc: N1_V02N0601 S1_V02N0601\narc: W1_H02W0701 E1_H02W0601\narc: B0 H00R0100\narc: B1 E1_H02W0301\narc: B2 H02W0101\narc: B3 H02W0301\narc: F4 F4_SLICE\narc: W1_H02W0601 F4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0011110000000000\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R18C14:PLC2\narc: E1_H02E0701 N1_V02S0701\narc: H00R0100 H02E0701\narc: N1_V02N0701 S1_V02N0601\narc: V00B0000 V02S0201\narc: V00B0100 H02E0501\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 V06S0003\narc: A2 V02S0501\narc: A4 N1_V01S0100\narc: A5 V00T0100\narc: B2 V02S0101\narc: B3 H00L0000\narc: B4 V02S0701\narc: B5 H00R0000\narc: C2 N1_V02S0401\narc: C3 H00R0100\narc: C4 H02E0601\narc: C5 H02E0401\narc: D2 N1_V01S0000\narc: D3 V00B0100\narc: D4 V02S0401\narc: D5 V00B0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0000 F2\narc: H00R0000 F4\narc: V00T0100 F3\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 0100000000000000\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000001\nword: SLICEB.K1.INIT 1100000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R18C15:PLC2\narc: E1_H02E0201 V02S0201\narc: H00R0000 V02S0401\narc: V00T0000 V02S0601\narc: V00T0100 H02W0101\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 V06S0303\narc: A0 H02E0701\narc: A5 V02S0101\narc: A6 V00T0100\narc: A7 N1_V01S0100\narc: B2 W1_H02E0301\narc: B3 V02S0301\narc: B4 H00R0000\narc: B5 V02S0701\narc: B6 V00T0000\narc: B7 V02S0501\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 0011110000000000\nword: SLICEB.K1.INIT 0011110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 0011110000000000\nword: SLICEC.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R18C16:PLC2\narc: H00L0000 V02S0201\narc: H00R0000 V02S0601\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 S1_V02N0601\narc: V00B0000 V02S0001\narc: V00T0000 H02W0001\narc: V00T0100 H02W0301\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 N1_V02S0101\narc: A0 N1_V02S0701\narc: A1 S1_V02N0501\narc: A2 N1_V02S0501\narc: A3 V00T0000\narc: A4 V00T0100\narc: A5 N1_V02S0301\narc: B0 V00B0000\narc: B1 V02S0101\narc: B2 H00L0000\narc: B3 V02S0301\narc: B4 H00R0000\narc: B5 V02S0701\narc: F6 F6_SLICE\narc: V01S0000 F6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R18C17:PLC2\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0301 N1_V02S0301\n\n.tile R18C2:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0201 V02S0201\narc: H00L0000 H02E0001\narc: H00R0000 V02S0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0701 S1_V02N0701\narc: V00B0100 V02N0301\narc: V00T0000 H02E0001\narc: A0 S1_V02N0701\narc: A1 S1_V02N0701\narc: A2 S1_V02N0701\narc: A3 S1_V02N0701\narc: A4 S1_V02N0301\narc: A5 S1_V02N0301\narc: A6 S1_V02N0301\narc: A7 S1_V02N0301\narc: B0 H02W0101\narc: B1 H02W0101\narc: B2 H02W0101\narc: B3 H02W0101\narc: B4 H02W0101\narc: B5 H02W0101\narc: B6 H02W0101\narc: B7 H02W0101\narc: C0 H00L0000\narc: C1 H00L0000\narc: C2 H00L0000\narc: C3 H00L0000\narc: C4 V00T0000\narc: C5 V00T0000\narc: C6 V00T0000\narc: C7 V00T0000\narc: D0 H02W0001\narc: D1 H02W0001\narc: D2 H02W0001\narc: D3 H02W0001\narc: D4 H02W0001\narc: D5 H02W0001\narc: D6 H02W0001\narc: D7 H02W0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: M3 H00R0100\narc: M4 V00B0100\narc: M5 H00R0000\narc: M6 V00B0100\narc: N1_V02N0301 F3\nword: SLICEA.K0.INIT 0011011101110111\nword: SLICEA.K1.INIT 0111011100110111\nword: SLICEB.K0.INIT 0001001100110011\nword: SLICEB.K1.INIT 0011001100010011\nword: SLICEC.K0.INIT 0000000100010001\nword: SLICEC.K1.INIT 0001000100000001\nword: SLICED.K0.INIT 0111000000000000\nword: SLICED.K1.INIT 0000000001110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R18C3:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 V06S0003\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 E3_H06W0203\narc: H00R0100 H02W0701\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0401 H06W0203\narc: S3_V06S0203 E3_H06W0203\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 N1_V01S0100\narc: B1 H00R0100\narc: C0 E1_H02W0601\narc: C1 V02N0401\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 F0\narc: D3 H02E0201\narc: E1_H02E0201 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: S1_V02S0101 Q1\narc: V00T0100 F3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 1100001100111100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R18C4:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 V06S0003\narc: H00R0000 V02S0401\narc: H00R0100 H02E0701\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 E1_H02W0701\narc: V00B0000 H02E0601\narc: V00T0000 V02S0401\narc: W1_H02W0701 E1_H02W0601\narc: A0 E1_H02W0501\narc: A3 E1_H02W0701\narc: A7 V02N0101\narc: B0 V00T0000\narc: B1 E1_H02W0101\narc: B2 E1_H02W0301\narc: B3 H00R0000\narc: B7 V00B0000\narc: C0 H02W0401\narc: C1 V02S0401\narc: C2 V02S0401\narc: C3 H02W0401\narc: C7 H02W0401\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 H02W0001\narc: D2 H02W0001\narc: D3 H02E0201\narc: D6 W1_H02E0201\narc: D7 V02S0601\narc: E1_H01E0101 F6\narc: E1_H02E0701 Q7\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F1\narc: LSR0 H02W0301\narc: M0 H02E0601\narc: M1 H00R0100\narc: M2 H02E0601\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V02N0301 F1\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 1001011001101001\nword: SLICEA.K0.INIT 0000000000010111\nword: SLICEA.K1.INIT 0000000000001100\nword: SLICEB.K0.INIT 0000000000000011\nword: SLICEB.K1.INIT 0010101100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R18C5:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0501 E1_H01W0100\narc: H00R0100 H02E0701\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 E1_H02W0301\narc: S1_V02S0001 H06W0003\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0701 H02W0701\narc: V00B0000 S1_V02N0201\narc: V00T0100 H02E0301\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 E1_H02W0301\narc: B4 V02N0701\narc: C4 V00T0100\narc: CLK0 G_HPBX0100\narc: D4 H00R0100\narc: D5 V00B0000\narc: E1_H02E0401 Q4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: LSR1 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: V00B0100 F5\nword: SLICEC.K0.INIT 1111110000001100\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R18C6:PLC2\narc: E3_H06E0003 N3_V06S0003\narc: H00L0100 N1_V02S0301\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H06W0203\narc: V00B0100 V02S0301\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0701 E1_H01W0100\narc: B4 H02E0101\narc: B5 H00R0000\narc: B6 V00B0000\narc: B7 W1_H02E0101\narc: C4 V02N0201\narc: C5 V02S0001\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D4 N1_V02S0601\narc: D5 H02E0001\narc: D6 H02E0001\narc: D7 H00L0100\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: E1_H02E0601 F4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H01W0000 F7\narc: H01W0100 Q6\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 F7\narc: S1_V02S0601 F4\narc: V00B0000 F4\narc: V01S0000 Q5\narc: V01S0100 F4\narc: W1_H02W0601 F4\narc: W3_H06W0203 F4\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0011110011111111\nword: SLICED.K0.INIT 0011110011111111\nword: SLICED.K1.INIT 0011110011000011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R18C7:PLC2\narc: E1_H02E0401 V06S0203\narc: H00L0100 H02W0101\narc: H00R0000 W1_H02E0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 H02W0401\narc: N1_V02N0701 V01N0101\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02W0501\narc: V00T0000 V02N0601\narc: V00T0100 V02S0701\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E1_H02W0201\narc: A2 V00B0000\narc: B2 H02W0301\narc: B3 H00L0000\narc: B4 H00R0000\narc: C2 N1_V02S0401\narc: C3 N1_V01S0100\narc: C4 V00T0000\narc: CLK0 G_HPBX0100\narc: D2 V00B0100\narc: D3 N1_V01S0000\narc: D4 H00R0100\narc: D5 H00L0100\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0000 F2\narc: H01W0000 F3\narc: H01W0100 F3\narc: LSR0 V00T0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 F5\narc: S1_V02S0001 F2\narc: S1_V02S0601 Q4\narc: V01S0100 F2\nword: SLICEB.K0.INIT 0110100110010110\nword: SLICEB.K1.INIT 1100001100111100\nword: SLICEC.K0.INIT 1111110000001100\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R18C8:PLC2\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 V06S0203\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 E3_H06W0303\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 W1_H02E0601\narc: V00B0000 H02E0401\narc: V00B0100 V02S0101\narc: V00T0100 V02N0501\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 N1_V02S0501\narc: W3_H06W0003 E1_H01W0000\narc: CLK0 G_HPBX0100\narc: LSR1 V00B0000\narc: M2 V00T0100\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q6\narc: S1_V02S0001 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R18C9:PLC2\narc: H00L0100 H02E0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 H02E0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 N1_V01S0100\narc: V00B0000 H02E0401\narc: V00T0100 H02E0301\narc: A3 V00T0000\narc: A6 H00L0000\narc: B1 V00B0000\narc: B2 H00R0100\narc: B3 H01W0100\narc: B6 V00B0100\narc: B7 V00B0000\narc: C1 H02E0601\narc: C2 H02E0601\narc: C3 H00L0100\narc: C6 V00T0100\narc: C7 H02E0601\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D1 N1_V01S0000\narc: D2 N1_V02S0201\narc: D3 V01S0100\narc: D6 H01W0000\narc: D7 V02S0601\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 Q1\narc: H01W0100 Q7\narc: LSR0 H02W0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: V00B0100 Q7\narc: V00T0000 Q2\narc: V01S0000 F6\narc: V01S0100 Q1\narc: W1_H02W0001 Q2\narc: W1_H02W0101 F3\narc: W1_H02W0201 Q2\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111111100\nword: SLICEB.K0.INIT 1111111111111100\nword: SLICEB.K1.INIT 0000000100010111\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 1111111111111100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R19C10:PLC2\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0401 H02W0401\narc: N1_V02N0701 S1_V02N0601\n\n.tile R19C11:PLC2\narc: E1_H02E0701 V06S0203\narc: W1_H02W0401 V06S0203\n\n.tile R19C12:PLC2\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0701 H02E0701\n\n.tile R19C16:PLC2\narc: N1_V02N0001 N1_V01S0000\n\n.tile R19C2:PLC2\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H01E0001\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0201 N1_V02S0201\narc: V00B0000 H02E0401\narc: C2 H00L0100\narc: CE1 H02W0101\narc: CLK0 V00B0000\narc: D2 Q2\narc: D3 V01S0100\narc: E3_H06E0003 Q3\narc: E3_H06E0103 Q2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H00L0100 Q3\narc: MUXCLK1 CLK0\narc: V01S0100 Q3\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R19C3:PLC2\narc: H00L0100 V02S0101\narc: N1_V02N0401 H06W0203\narc: N1_V02N0601 H06W0303\narc: V00T0000 H02W0001\narc: V00T0100 H02W0301\narc: W1_H02W0101 E1_H02W0101\narc: B6 V00T0000\narc: C6 V00T0100\narc: CLK0 G_HPBX0100\narc: D6 H00L0100\narc: D7 E1_H02W0201\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00B0100 F7\narc: V01S0000 Q6\nword: SLICED.K0.INIT 1111110000001100\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R19C4:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: H00L0100 S1_V02N0301\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 E1_H02W0101\narc: S1_V02S0001 N1_V02S0001\narc: V00B0000 V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: B0 V00B0000\narc: C0 H00L0100\narc: CLK0 G_HPBX0100\narc: D0 V02N0001\narc: D1 H02W0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: V00T0100 F1\narc: W1_H02W0001 Q0\nword: SLICEA.K0.INIT 1111110000001100\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R19C5:PLC2\narc: E1_H02E0201 V06S0103\narc: H00L0100 H02E0301\narc: N1_V02N0101 H06E0103\narc: N1_V02N0301 H06E0003\narc: N1_V02N0701 E1_H01W0100\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V06S0103\narc: B0 E1_H02W0101\narc: C0 H00L0100\narc: CLK0 G_HPBX0100\narc: D0 S1_V02N0001\narc: D1 V02N0201\narc: E1_H02E0001 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: V00T0100 F1\nword: SLICEA.K0.INIT 1111110000001100\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R19C6:PLC2\narc: H00L0000 H02E0001\narc: H00L0100 H02W0301\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 E1_H01W0100\narc: W1_H02W0101 N1_V01S0100\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: B2 H00L0000\narc: C2 H00L0100\narc: CLK0 G_HPBX0100\narc: D2 N1_V01S0000\narc: D3 H02E0201\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0100 Q2\narc: LSR1 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00T0100 F3\nword: SLICEB.K0.INIT 1111110000001100\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R19C7:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: H00L0000 V02S0201\narc: H00R0000 N1_V02S0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0601 N1_V02S0601\narc: V00B0100 N1_V02S0101\narc: V00T0000 N1_V02S0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 S1_V02N0301\narc: A4 V02S0101\narc: A5 V02S0101\narc: A6 V02S0101\narc: A7 V02S0101\narc: B0 V00T0000\narc: B4 H00R0000\narc: B5 H00R0000\narc: B6 V00T0000\narc: B7 V00T0000\narc: C0 N1_V01S0100\narc: C4 V02S0001\narc: C5 V02S0001\narc: C6 V02S0001\narc: C7 V02S0001\narc: D0 V00T0100\narc: D4 H00R0100\narc: D5 H00R0100\narc: D6 H00R0100\narc: D7 H00R0100\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: H01W0100 F3\narc: M0 V00B0100\narc: M1 H00L0000\narc: M2 V00B0100\narc: M3 E1_H02W0201\narc: M4 V00B0100\narc: M5 H00L0000\narc: M6 V00B0100\narc: N1_V01N0101 F3\narc: V01S0000 F3\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000001100\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1110111011101111\nword: SLICEC.K1.INIT 1000111011101110\nword: SLICED.K0.INIT 1000111011101110\nword: SLICED.K1.INIT 1000100010001110\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R19C8:PLC2\narc: H00L0100 H02E0301\narc: H00R0000 V02S0401\narc: N1_V02N0501 V01N0101\narc: V00B0000 V02S0001\narc: B0 V00B0000\narc: C0 H00L0100\narc: CLK0 G_HPBX0100\narc: D0 S1_V02N0001\narc: D1 H00R0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: H01W0100 Q0\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: V00T0100 F1\nword: SLICEA.K0.INIT 1111110000001100\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R19C9:PLC2\narc: W1_H02W0201 N1_V01S0000\n\n.tile R20C10:PLC2\narc: E3_H06E0303 N3_V06S0303\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 V06S0203\n\n.tile R20C11:PLC2\narc: N1_V02N0101 N3_V06S0103\narc: N3_V06N0203 S3_V06N0203\n\n.tile R20C13:PLC2\narc: N1_V02N0601 H06E0303\n\n.tile R20C14:PLC2\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0303 S3_V06N0303\n\n.tile R20C15:PLC2\narc: N1_V02N0301 N3_V06S0003\n\n.tile R20C16:PLC2\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 W3_H06E0303\n\n.tile R20C2:PLC2\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0701 N3_V06S0203\narc: W1_H02W0701 E1_H02W0701\narc: C1 H02W0401\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 H02W0201\narc: E1_H02E0301 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: LSR0 V00T0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V00T0000 F0\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 1111000000001111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R20C3:PLC2\narc: E1_H02E0401 N1_V02S0401\narc: H00L0100 H02E0301\narc: N1_V02N0601 N3_V06S0303\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 N1_V02S0401\narc: B4 N1_V01S0000\narc: C4 V02N0001\narc: CLK0 G_HPBX0100\narc: D4 H00L0100\narc: D5 V00B0000\narc: D7 E1_H02W0201\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: LSR1 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: S3_V06S0203 Q4\narc: S3_V06S0303 F5\narc: V00B0000 Q4\narc: V00B0100 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 1111110000001100\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R20C4:PLC2\narc: H00R0000 H02E0401\narc: N1_V02N0201 E1_H02W0201\narc: W1_H02W0701 V06S0203\narc: B2 H00R0000\narc: B3 H02W0301\narc: C2 H00L0100\narc: C3 V02N0401\narc: CLK0 G_HPBX0000\narc: D2 V02S0001\narc: D3 H02W0001\narc: E3_H06E0003 F3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H00L0100 F3\narc: MUXCLK1 CLK0\narc: N1_V02N0001 Q2\narc: N1_V02N0101 F3\nword: SLICEB.K0.INIT 1100001111111111\nword: SLICEB.K1.INIT 1100001100111100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R20C5:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0201 S1_V02N0201\narc: H00R0000 H02W0601\narc: N1_V02N0201 S1_V02N0201\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 N1_V02S0301\narc: B5 H00R0000\narc: C5 V00T0100\narc: CLK0 G_HPBX0000\narc: D4 V02N0601\narc: D5 E1_H02W0201\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: LSR1 V00B0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: V00B0000 F4\narc: V01S0000 Q5\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 1100001100111100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R20C6:PLC2\narc: H00L0100 V02N0301\narc: H00R0000 H02W0601\narc: V00B0100 H02W0701\narc: W1_H02W0601 N1_V02S0601\narc: B2 H00R0000\narc: C2 H00L0100\narc: CLK0 G_HPBX0100\narc: D2 V00B0100\narc: D3 H02E0201\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: V00T0100 F3\narc: W1_H02W0201 Q2\nword: SLICEB.K0.INIT 1111110000001100\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R20C7:PLC2\narc: E1_H02E0601 N1_V01S0000\narc: N1_V02N0001 H06E0003\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0601 N1_V02S0601\narc: C5 H02W0601\narc: CLK0 G_HPBX0000\narc: D4 W1_H02E0001\narc: D5 V02S0601\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: LSR0 V00B0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: V00B0000 F4\narc: W1_H02W0701 Q5\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 0000111111110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R20C8:PLC2\narc: V00B0100 E1_H02W0701\narc: W1_H02W0601 N1_V02S0601\narc: C1 N1_V02S0601\narc: C3 H02E0601\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D3 V00B0100\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0101 Q1\narc: V01S0000 Q3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000111111111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R20C9:PLC2\narc: N1_V02N0601 H02W0601\n\n.tile R21C10:PLC2\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0601 N3_V06S0303\n\n.tile R21C12:PLC2\narc: N1_V02N0501 N3_V06S0303\n\n.tile R21C2:PLC2\narc: S1_V02S0201 N3_V06S0103\n\n.tile R21C3:PLC2\narc: E1_H02E0401 V06S0203\narc: N1_V02N0001 H02W0001\n\n.tile R21C4:PLC2\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H02E0401\narc: W1_H02W0001 N3_V06S0003\n\n.tile R21C5:PLC2\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0601 S1_V02N0301\n\n.tile R21C6:PLC2\narc: N1_V02N0301 H02W0301\n\n.tile R21C7:PLC2\narc: N1_V02N0301 N3_V06S0003\narc: W1_H02W0301 N3_V06S0003\n\n.tile R21C8:PLC2\narc: N1_V02N0001 N1_V01S0000\n\n.tile R22C16:PLC2\narc: N1_V02N0501 N3_V06S0303\n\n.tile R22C5:PLC2\narc: N1_V02N0201 N3_V06S0103\n\n.tile R23C2:PLC2\narc: W1_H02W0201 N1_V02S0201\n\n.tile R23C3:PLC2\narc: W1_H02W0501 V06S0303\n\n.tile R23C5:PLC2\narc: N1_V02N0301 N3_V06S0003\n\n.tile R26C11:PLC2\narc: N3_V06N0203 S3_V06N0203\n\n.tile R26C14:PLC2\narc: N3_V06N0303 S3_V06N0203\n\n.tile R26C3:PLC2\narc: W1_H02W0701 N3_V06S0203\n\n.tile R2C2:PLC2\narc: D1 N1_V01S0000\narc: F1 F1_SLICE\narc: H01W0100 F1\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R31C2:PLC2\narc: N3_V06N0003 S3_V06N0003\n\n.tile R31C4:PLC2\narc: N3_V06N0003 S3_V06N0003\n\n.tile R32C11:PLC2\narc: N3_V06N0203 H06W0203\n\n.tile R32C14:PLC2\narc: F7 F7_SLICE\narc: N3_V06N0203 F7\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R32C2:PLC2\narc: S3_V06S0303 E3_H06W0303\n\n.tile R32C8:PLC2\narc: W3_H06W0303 E3_H06W0203\n\n.tile R38C2:PLC2\narc: S3_V06S0303 N3_V06S0303\n\n.tile R43C2:PLC2\narc: N3_V06N0303 S3_V06N0203\n\n.tile R43C4:PLC2\narc: N3_V06N0303 S3_V06N0303\n\n.tile R44C2:PLC2\narc: S1_V02S0601 N3_V06S0303\n\n.tile R46C2:PLC2\narc: S1_V02S0701 N1_V02S0601\n\n.tile R48C2:PLC2\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0701 N1_V02S0701\n\n.tile R4C11:PLC2\narc: N3_V06N0303 S3_V06N0203\n\n.tile R5C15:PLC2\narc: S1_V02S0001 V01N0001\n\n.tile R5C5:PLC2\narc: S1_V02S0201 S3_V06N0103\n\n.tile R6C15:PLC2\narc: E1_H02E0701 S1_V02N0701\narc: V00B0000 V02S0001\narc: V00B0100 V02N0301\narc: B4 V00B0100\narc: C4 H02W0601\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D4 V02N0401\narc: D5 E1_H02W0201\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: LSR0 V00B0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0001 F5\narc: S1_V02S0401 Q4\narc: S3_V06S0203 Q4\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R6C16:PLC2\narc: H00R0100 H02E0701\narc: W1_H02W0601 S1_V02N0601\narc: B2 V02N0301\narc: C2 V02N0601\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 V02N0201\narc: D3 H02W0201\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR1 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: S1_V02S0201 Q2\narc: S3_V06S0103 Q2\narc: V00T0100 F3\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R6C17:PLC2\narc: W1_H02W0201 S1_V02N0201\n\n.tile R6C3:PLC2\narc: H00R0000 S1_V02N0601\narc: V00B0000 V02N0001\narc: V00B0100 S1_V02N0101\narc: A0 S1_V02N0701\narc: A1 S1_V02N0701\narc: A2 S1_V02N0701\narc: A3 S1_V02N0701\narc: B0 V02N0301\narc: B1 V02N0301\narc: B2 V02N0301\narc: B3 V02N0301\narc: C0 E1_H02W0401\narc: C1 E1_H02W0401\narc: C2 E1_H02W0401\narc: C3 E1_H02W0401\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 V02N0201\narc: D2 V02N0201\narc: D3 V02N0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: LSR0 V00B0100\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: S1_V02S0101 Q1\narc: S1_V02S0301 Q1\narc: V01S0000 Q1\nword: SLICEA.K0.INIT 1100000011110101\nword: SLICEA.K1.INIT 0000010111001111\nword: SLICEB.K0.INIT 0011111100001010\nword: SLICEB.K1.INIT 1111101000110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R6C5:PLC2\narc: W1_H02W0401 V02N0401\n\n.tile R6C9:PLC2\narc: S1_V02S0201 V01N0001\n\n.tile R7C10:PLC2\narc: H00R0000 S1_V02N0401\narc: S1_V02S0301 V01N0101\narc: V00T0000 S1_V02N0601\narc: V00T0100 V02N0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 V01N0001\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V01N0101\narc: W1_H02W0601 V02N0601\narc: A0 H02W0701\narc: A3 V01N0101\narc: A4 V02N0101\narc: A5 S1_V02N0301\narc: A6 V00T0100\narc: A7 H02E0701\narc: B2 V02N0301\narc: B3 S1_V02N0101\narc: B4 H00R0000\narc: B5 S1_V02N0501\narc: B6 V00T0000\narc: B7 S1_V02N0701\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 0011110000000000\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R7C11:PLC2\narc: H00L0000 V02N0201\narc: H00R0000 S1_V02N0401\narc: V00B0000 S1_V02N0201\narc: V00T0000 V02N0401\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 V06N0203\narc: A0 V02N0501\narc: A1 H00L0000\narc: A2 V01N0101\narc: A3 S1_V02N0701\narc: A4 V02N0301\narc: A5 V00T0000\narc: B0 V00B0000\narc: B1 S1_V02N0301\narc: B2 V02N0101\narc: B3 S1_V02N0101\narc: B4 H00R0000\narc: B5 S1_V02N0501\narc: F6 F6_SLICE\narc: W1_H02W0601 F6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R7C13:PLC2\narc: V00B0000 E1_H02W0601\narc: B6 V00B0000\narc: C6 E1_H02W0401\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D6 E1_H02W0201\narc: D7 H02W0201\narc: E1_H02E0601 Q6\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR1 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: S1_V02S0401 Q6\narc: V00B0100 F7\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R7C14:PLC2\narc: H00R0100 H02W0701\narc: W1_H02W0201 V02N0201\narc: B0 S1_V02N0301\narc: C0 V02N0401\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 V02N0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: LSR0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: S3_V06S0003 Q0\narc: V00T0100 F1\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R7C15:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0701 V02N0701\narc: H00R0000 V02N0601\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0101\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0601 W1_H02E0601\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02N0701\narc: B2 V02N0101\narc: C2 V02N0401\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 S1_V02N0001\narc: D3 E1_H02W0201\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: S1_V02S0201 Q2\narc: S3_V06S0103 Q2\narc: V00T0100 F3\narc: V01S0000 Q2\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R7C16:PLC2\narc: H00R0100 H02E0701\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0601 V01N0001\narc: S1_V02S0101 N1_V01S0100\narc: V00B0000 S1_V02N0001\narc: B6 V00B0000\narc: C6 V02N0201\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D6 H02E0201\narc: D7 H02W0201\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: S1_V02S0401 Q6\narc: S3_V06S0303 Q6\narc: V00B0100 F7\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R7C17:PLC2\narc: H00R0100 W1_H02E0701\narc: V00B0000 S1_V02N0201\narc: W1_H02W0201 V02N0201\narc: B0 V00B0000\narc: C0 S1_V02N0401\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0201\narc: D1 V02N0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: S1_V02S0201 Q0\narc: S3_V06S0003 Q0\narc: V00T0100 F1\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R7C2:PLC2\narc: E1_H02E0001 V02N0001\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02N0501\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0201 H06W0103\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 H02W0501\narc: V00B0100 V02N0101\narc: V00T0100 H02E0301\narc: A0 H02W0501\narc: A1 H02W0501\narc: A2 H02W0501\narc: A3 H02W0501\narc: A4 H02W0501\narc: A5 H02W0501\narc: A6 H02W0501\narc: A7 H02W0501\narc: B0 V02N0101\narc: B1 V02N0101\narc: B2 V02N0101\narc: B3 V02N0101\narc: B4 V00B0100\narc: B5 V00B0100\narc: B6 V00B0100\narc: B7 V00B0100\narc: C0 E1_H02W0401\narc: C1 E1_H02W0401\narc: C2 E1_H02W0401\narc: C3 E1_H02W0401\narc: C4 E1_H02W0401\narc: C5 E1_H02W0401\narc: C6 E1_H02W0401\narc: C7 E1_H02W0401\narc: D0 S1_V02N0201\narc: D1 S1_V02N0001\narc: D2 S1_V02N0001\narc: D3 S1_V02N0201\narc: D4 S1_V02N0401\narc: D5 S1_V02N0401\narc: D6 S1_V02N0401\narc: D7 S1_V02N0401\narc: E1_H02E0301 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00R0000\narc: M2 V00T0100\narc: M3 H00R0100\narc: M4 V00T0100\narc: M5 H00R0000\narc: M6 V00T0100\nword: SLICEA.K0.INIT 0011000100010001\nword: SLICEA.K1.INIT 0001000100110001\nword: SLICEB.K0.INIT 0111001100110011\nword: SLICEB.K1.INIT 0011001101110011\nword: SLICEC.K0.INIT 1111011101110111\nword: SLICEC.K1.INIT 0111011111110111\nword: SLICED.K0.INIT 0001111111111111\nword: SLICED.K1.INIT 1111111100011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R7C3:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V02N0201\narc: H00L0100 V02S0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H02E0301\narc: V00B0000 V02N0001\narc: V00B0100 V02S0101\narc: W1_H02W0501 S1_V02N0501\narc: A0 V01N0101\narc: A3 V01N0101\narc: A4 S1_V02N0101\narc: A7 S1_V02N0101\narc: B0 H00R0100\narc: B3 H00R0100\narc: B4 V02N0501\narc: B7 V02N0501\narc: C0 E1_H02W0401\narc: C3 E1_H02W0401\narc: C4 E1_H02W0401\narc: C7 E1_H02W0401\narc: D0 V00B0100\narc: D3 V00B0100\narc: D4 H00L0100\narc: D7 H00L0100\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0000\narc: M1 H02E0001\narc: M2 V00B0000\narc: M3 H00R0000\narc: M4 V00B0000\narc: M5 H02E0001\narc: M6 V00B0000\narc: V01S0100 F3\nword: SLICEA.K0.INIT 0000010001000000\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 0100000000000100\nword: SLICEC.K0.INIT 1111101110111111\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1011111111111011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R7C4:PLC2\narc: S3_V06S0003 H06W0003\narc: V00T0000 V02N0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 E1_H02W0601\narc: A1 V01N0101\narc: A3 V01N0101\narc: B1 H02E0101\narc: B3 H02E0101\narc: C1 H02W0401\narc: C3 H02W0401\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 H02E0001\narc: D2 V02N0201\narc: D3 H02E0001\narc: D6 H02W0201\narc: D7 H02E0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: LSR0 V00B0000\narc: M0 V00T0000\narc: M1 W1_H02E0001\narc: M2 V00T0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00B0000 F6\narc: V01S0000 Q7\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0101010001000101\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1000101010101000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0000111111110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R7C5:PLC2\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0401 S1_V02N0401\narc: H00L0000 V02N0001\narc: H00R0000 E1_H02W0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0401 S1_V02N0401\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 V02N0601\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 E1_H02W0101\narc: W3_H06W0103 E1_H02W0101\narc: A0 H00L0000\narc: A2 V00B0000\narc: A3 V00B0000\narc: A4 V00B0000\narc: A6 H00L0000\narc: A7 H00L0000\narc: B0 V02N0101\narc: B1 V00B0000\narc: B2 V02N0101\narc: B3 V02N0101\narc: B4 V00B0100\narc: B6 V00B0100\narc: B7 V00B0100\narc: C0 V02N0401\narc: C1 V02N0401\narc: C2 V02N0401\narc: C3 V02N0401\narc: C4 V02N0201\narc: C6 V02N0201\narc: C7 V02N0201\narc: D0 W1_H02E0201\narc: D1 W1_H02E0201\narc: D2 W1_H02E0201\narc: D3 W1_H02E0201\narc: D4 W1_H02E0201\narc: D5 V00B0000\narc: D6 W1_H02E0201\narc: D7 W1_H02E0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00T0000\narc: M1 H00R0100\narc: M2 V00T0000\narc: M3 H00R0000\narc: M4 V00T0000\narc: M5 H00R0100\narc: M6 V00T0000\narc: S1_V02S0301 F3\narc: S3_V06S0003 F3\nword: SLICEC.K0.INIT 0101010101010001\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 0100010101010101\nword: SLICED.K1.INIT 0101010101010001\nword: SLICEA.K0.INIT 0101010101010100\nword: SLICEA.K1.INIT 0011000000110011\nword: SLICEB.K0.INIT 0101000101010101\nword: SLICEB.K1.INIT 0101010101010100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R7C6:PLC2\narc: H00R0000 H02E0401\narc: H00R0100 V02N0501\narc: V00T0100 H02W0101\narc: W1_H02W0601 S1_V02N0601\narc: B3 H00R0000\narc: C3 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 H02E0201\narc: D3 V00T0100\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR1 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: S1_V02S0301 Q3\narc: V00T0000 F2\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 1100001100111100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R7C7:PLC2\narc: H00L0000 V02N0201\narc: H00R0000 V02N0601\narc: S1_V02S0601 H02W0601\narc: V00T0100 H02W0101\narc: W1_H02W0501 V01N0101\narc: W1_H02W0601 S1_V02N0601\narc: A4 V02N0101\narc: A5 V02N0301\narc: A6 V02N0101\narc: A7 V02N0301\narc: B0 S1_V02N0301\narc: B4 S1_V02N0701\narc: B5 S1_V02N0501\narc: B6 S1_V02N0501\narc: B7 S1_V02N0701\narc: C0 V02N0401\narc: C4 V02N0001\narc: C5 V02N0001\narc: C6 V02N0001\narc: C7 V02N0001\narc: D0 S1_V02N0001\narc: D4 V01N0001\narc: D5 V01N0001\narc: D6 V01N0001\narc: D7 V01N0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00L0000\narc: M2 V00T0100\narc: M3 H00R0000\narc: M4 V00T0100\narc: M5 H00L0000\narc: M6 V00T0100\narc: S3_V06S0003 F3\narc: V01S0000 F3\narc: V01S0100 F3\narc: W1_H02W0101 F3\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000001100\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1110111011101111\nword: SLICEC.K1.INIT 1000111011101110\nword: SLICED.K0.INIT 1000111011101110\nword: SLICED.K1.INIT 1000100010001110\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R7C8:PLC2\narc: S1_V02S0601 E1_H02W0601\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0601 E1_H02W0601\n\n.tile R7C9:PLC2\narc: E1_H02E0701 V02N0701\narc: H00L0000 E1_H02W0001\narc: H00R0000 H02W0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H02W0601\narc: V00B0100 E1_H02W0501\narc: A0 H00L0000\narc: A1 H00R0000\narc: A5 H02W0501\narc: B0 E1_H02W0301\narc: B1 V02N0301\narc: B3 E1_H02W0101\narc: B4 S1_V02N0501\narc: B5 S1_V02N0701\narc: C0 H00L0100\narc: C1 S1_V02N0601\narc: C3 E1_H02W0401\narc: C4 V02N0201\narc: C5 V00B0100\narc: D0 V01S0100\narc: D1 H02W0201\narc: D3 V02S0201\narc: D4 H02W0001\narc: D5 V02N0601\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0100 F1\narc: N1_V01N0001 F5\narc: S1_V02S0001 F0\narc: S1_V02S0301 F3\narc: V01S0100 F4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100001100000000\nword: SLICEC.K0.INIT 0000000011001111\nword: SLICEC.K1.INIT 1011000000001011\nword: SLICEA.K0.INIT 1001000000000000\nword: SLICEA.K1.INIT 1001000000001001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R8C10:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0601 S3_V06N0303\narc: H00L0000 H02E0001\narc: N1_V02N0301 V01N0101\narc: N1_V02N0601 S3_V06N0303\narc: S1_V02S0501 H02W0501\narc: V00T0000 E1_H02W0201\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 V02N0701\narc: A0 H02W0501\narc: B2 V02S0301\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 V01S0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q7\narc: E1_H01E0101 Q6\narc: E1_H02E0501 Q7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q2\narc: H01W0100 Q3\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q2\narc: N1_V02N0101 Q3\narc: N1_V02N0701 Q5\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V01S0000 Q7\narc: V01S0100 Q4\narc: W1_H02W0401 Q4\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R8C11:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: N1_V02N0101 V01N0101\narc: N1_V02N0501 H02E0501\narc: S1_V02S0601 H02E0601\narc: V00B0000 S1_V02N0001\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0701 H01E0101\narc: B0 H01W0100\narc: B1 Q1\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q3\narc: H01W0100 Q0\narc: LSR0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q1\narc: N1_V02N0201 Q0\narc: N1_V02N0301 Q3\narc: N1_V02N0401 Q4\narc: V01S0100 Q2\narc: W1_H02W0201 Q0\narc: W1_H02W0601 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001010\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R8C12:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: H00L0100 H02W0301\narc: W1_H02W0201 S1_V02N0201\narc: B4 E1_H02W0301\narc: C4 V02N0201\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D4 H00L0100\narc: D5 H02E0201\narc: E1_H01E0101 Q4\narc: E1_H02E0401 Q4\narc: E3_H06E0203 Q4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: LSR0 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: V00B0100 F5\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R8C13:PLC2\narc: H00R0000 H02E0601\narc: N1_V02N0601 H02E0601\narc: S1_V02S0101 H01E0101\narc: V00B0100 E1_H02W0701\narc: W1_H02W0301 E1_H02W0201\narc: B6 V02N0501\narc: C6 V00B0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D6 E1_H02W0201\narc: D7 H02W0201\narc: E1_H02E0601 Q6\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR0 H02E0501\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V01S0000 Q6\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R8C14:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 W1_H02E0401\narc: H00R0000 H02W0601\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 E1_H01W0000\narc: S1_V02S0101 E1_H02W0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E1_H01W0100\narc: B2 E1_H02W0301\narc: C2 E1_H02W0401\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 H02W0201\narc: D3 S1_V02N0201\narc: E1_H02E0201 Q2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: V00T0100 F3\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R8C15:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 H02E0001\narc: H00R0000 V02S0601\narc: H00R0100 H02E0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H06E0203\narc: V00B0000 W1_H02E0601\narc: W1_H02W0201 V02N0201\narc: W1_H02W0601 S1_V02N0601\narc: A0 H00L0000\narc: B2 H00R0100\narc: B3 V02S0301\narc: B4 H00R0000\narc: B5 H02E0101\narc: B6 N1_V01S0000\narc: B7 V00B0000\narc: E1_H01E0001 F3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: H01W0100 F2\narc: N1_V01N0001 F4\narc: N1_V02N0401 F6\narc: W1_H02W0701 F7\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R8C16:PLC2\narc: H00L0000 W1_H02E0201\narc: N1_V02N0601 H01E0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0601 V01N0001\narc: V00B0000 S1_V02N0201\narc: V00T0000 V02S0401\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 V01N0101\narc: B0 V00T0000\narc: B1 S1_V02N0301\narc: B2 E1_H01W0100\narc: B3 V02S0101\narc: B4 H00L0000\narc: B5 V02N0701\narc: B6 W1_H02E0301\narc: B7 V00B0000\narc: E1_H01E0001 F1\narc: E1_H02E0201 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V01N0001 F3\narc: N1_V02N0201 F0\narc: S1_V02S0501 F5\narc: S1_V02S0701 F7\narc: V01S0000 F6\narc: W1_H02W0401 F4\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R8C17:PLC2\narc: H00L0000 V02N0001\narc: H00R0000 W1_H02E0601\narc: N1_V02N0201 S1_V02N0701\narc: S1_V02S0001 H01E0001\narc: V00B0000 V02S0201\narc: V00T0000 H02E0201\narc: B0 V00B0000\narc: B1 V01N0001\narc: B4 H00L0000\narc: C4 V00T0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 W1_H02E0201\narc: D5 S1_V02N0401\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q4\narc: LSR1 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: S1_V02S0301 F1\narc: V00B0100 F5\narc: V01S0000 F0\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R8C2:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: H00R0000 V02N0601\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0501 E1_H01W0100\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 V02S0201\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02S0401\narc: V00T0100 V02S0501\narc: A0 V02S0501\narc: A1 V02S0501\narc: A2 V02S0501\narc: A3 V02S0501\narc: A4 V00T0100\narc: A5 V00T0100\narc: A6 V00T0100\narc: A7 V00T0100\narc: B0 S1_V02N0301\narc: B1 S1_V02N0301\narc: B2 S1_V02N0101\narc: B3 S1_V02N0301\narc: B4 V00B0100\narc: B5 V00B0100\narc: B6 V00B0100\narc: B7 V00B0100\narc: C0 V02S0401\narc: C1 V02S0401\narc: C2 V02S0401\narc: C3 V02S0401\narc: C4 V00T0000\narc: C5 V00T0000\narc: C6 V00T0000\narc: C7 V00T0000\narc: D0 V02N0201\narc: D1 V02N0001\narc: D2 V02N0201\narc: D3 V02N0001\narc: D4 V02N0401\narc: D5 V02N0401\narc: D6 V02N0401\narc: D7 V02N0401\narc: E1_H01E0101 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M3 E1_H02W0201\narc: M4 V00B0000\narc: M5 H00R0000\narc: M6 V00B0000\nword: SLICEA.K0.INIT 0011011101110111\nword: SLICEA.K1.INIT 0111011100110111\nword: SLICEB.K0.INIT 0001001100110011\nword: SLICEB.K1.INIT 0011001100010011\nword: SLICEC.K0.INIT 0000000100010001\nword: SLICEC.K1.INIT 0001000100000001\nword: SLICED.K0.INIT 0111000000000000\nword: SLICED.K1.INIT 0000000001110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R8C3:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 W1_H02E0301\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 H06W0103\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H01E0101\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H06W0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0601 N1_V02S0301\narc: V00B0000 E1_H02W0601\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02N0601\narc: V00T0100 W1_H02E0301\narc: W1_H02W0501 E1_H01W0100\narc: A2 V02N0501\narc: A6 H02W0701\narc: A7 H02W0701\narc: B2 H02E0101\narc: B6 V00B0000\narc: B7 V00B0000\narc: C2 H00L0100\narc: C3 N1_V01S0100\narc: C6 V00T0100\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D2 V00B0100\narc: D3 V02N0001\narc: D5 S1_V02N0601\narc: D6 H02W0001\narc: D7 H02W0001\narc: E1_H01E0001 F6\narc: E1_H01E0101 F5\narc: E1_H02E0001 F2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 Q3\narc: H01W0100 F6\narc: LSR1 H02W0301\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 Q3\narc: N1_V01N0101 F2\narc: N1_V02N0101 F1\narc: V01S0000 Q3\narc: V01S0100 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1110101111010100\nword: SLICED.K1.INIT 0001010000101011\nword: SLICEB.K0.INIT 0000000000000001\nword: SLICEB.K1.INIT 1111000000001111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R8C4:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 V01N0101\narc: H00L0100 V02N0301\narc: H00R0100 E1_H02W0701\narc: H01W0100 G_HPBX0000\narc: S1_V02S0001 H06W0003\narc: V00B0100 E1_H02W0701\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 H01E0101\narc: W1_H02W0701 E1_H02W0701\narc: A2 V02N0701\narc: A3 V02N0701\narc: A4 E1_H01W0000\narc: A5 E1_H01W0000\narc: B0 E1_H01W0100\narc: B2 V02N0101\narc: B3 V02N0101\narc: B4 E1_H02W0301\narc: B5 E1_H02W0301\narc: C0 H00L0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 H02E0601\narc: C5 H02E0601\narc: CLK0 G_HPBX0100\narc: D0 N1_V01S0000\narc: D1 H02W0201\narc: D2 E1_H02W0201\narc: D3 E1_H02W0201\narc: D4 E1_H02W0001\narc: D5 E1_H02W0001\narc: E1_H01E0101 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: H01W0000 F2\narc: LSR1 V00T0100\narc: M2 H02E0601\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0101 F2\narc: N1_V02N0201 F2\narc: N1_V02N0401 F4\narc: V00T0100 F1\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 1111110000001100\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0001010000101000\nword: SLICEC.K1.INIT 1100001000000001\nword: SLICEB.K0.INIT 0111000101110111\nword: SLICEB.K1.INIT 0011001101110001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R8C5:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 E1_H01W0100\narc: H00R0000 H02W0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 E1_H01W0000\narc: S1_V02S0001 E1_H02W0001\narc: V00B0000 S1_V02N0201\narc: V00T0000 H02E0001\narc: V00T0100 H02W0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0501 H01E0101\narc: W3_H06W0003 E1_H01W0000\narc: A0 E1_H02W0701\narc: A1 E1_H02W0701\narc: A2 E1_H02W0701\narc: A3 E1_H02W0701\narc: A4 H02W0501\narc: A5 H02W0501\narc: B0 V01N0001\narc: B1 V01N0001\narc: B2 V01N0001\narc: B3 V01N0001\narc: B4 E1_H02W0301\narc: B5 E1_H02W0101\narc: B6 V00T0000\narc: C0 E1_H02W0601\narc: C1 E1_H02W0401\narc: C2 E1_H02W0401\narc: C3 E1_H02W0601\narc: C4 V01N0101\narc: C5 V01N0101\narc: C6 V02N0001\narc: CLK0 G_HPBX0100\narc: D0 W1_H02E0201\narc: D1 W1_H02E0201\narc: D2 W1_H02E0201\narc: D3 W1_H02E0201\narc: D4 H00R0100\narc: D5 H00R0100\narc: D6 V02N0601\narc: D7 V00B0000\narc: E1_H01E0001 F4\narc: E1_H01E0101 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q6\narc: LSR1 V00B0100\narc: M0 V00T0100\narc: M1 H00R0000\narc: M2 V00T0100\narc: M4 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V02N0101 F1\narc: N1_V02N0301 F1\narc: N1_V02N0601 F4\narc: V00B0100 F7\narc: V01S0000 F4\narc: V01S0100 F1\narc: W1_H02W0301 F1\narc: W1_H02W0601 F4\nword: SLICED.K0.INIT 1111110000001100\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0110100110010110\nword: SLICEC.K1.INIT 1001011001101001\nword: SLICEA.K0.INIT 1001000000001001\nword: SLICEA.K1.INIT 0000100110010000\nword: SLICEB.K0.INIT 0000011001100000\nword: SLICEB.K1.INIT 0110000000000110\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R8C6:PLC2\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 V02N0201\narc: H00L0100 V02S0301\narc: H00R0000 V02N0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0501 E1_H02W0501\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0701 H02W0701\narc: V00B0000 V02N0201\narc: V00T0000 H02W0001\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 E1_H01W0100\narc: W3_H06W0103 E1_H01W0100\narc: A0 E1_H02W0501\narc: A3 E1_H02W0501\narc: B0 V00B0000\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00L0000\narc: B6 W1_H02E0301\narc: C0 V02N0401\narc: C1 H00L0000\narc: C2 H00L0000\narc: C3 V02N0401\narc: C6 V02N0001\narc: CLK0 G_HPBX0100\narc: D0 E1_H02W0001\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 E1_H02W0001\narc: D6 H00L0100\narc: D7 H02E0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 F7\narc: LSR0 H02E0301\narc: M0 V00T0000\narc: M1 H02E0001\narc: M2 V00T0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: S1_V02S0601 Q6\nword: SLICED.K0.INIT 1111110000001100\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000000010111\nword: SLICEA.K1.INIT 0000000000001100\nword: SLICEB.K0.INIT 0000000000000011\nword: SLICEB.K1.INIT 0010101100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R8C7:PLC2\narc: H00R0000 V02S0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0401 E1_H02W0401\narc: V00B0000 V02N0001\narc: V00T0000 S1_V02N0401\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 N1_V01S0100\narc: A1 H00L0000\narc: A6 H00L0000\narc: B0 E1_H02W0101\narc: B1 H00R0100\narc: B3 E1_H02W0101\narc: B4 N1_V01S0000\narc: B5 E1_H02W0101\narc: B6 V00B0100\narc: B7 E1_H02W0101\narc: C0 H02W0601\narc: C1 V02N0401\narc: C2 H00L0000\narc: C3 H02W0601\narc: C4 V01N0101\narc: C5 H02W0601\narc: C6 V02N0201\narc: C7 H02W0601\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 V00T0100\narc: D2 V00T0100\narc: D3 S1_V02N0001\narc: D4 V00B0000\narc: D5 V01N0001\narc: D6 H00L0100\narc: D7 H02W0201\narc: E1_H01E0001 F2\narc: E1_H02E0701 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00L0100 Q3\narc: H00R0100 Q7\narc: H01W0000 F2\narc: H01W0100 F4\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q0\narc: N1_V02N0101 F1\narc: N1_V02N0201 Q0\narc: N1_V02N0301 F1\narc: N1_V02N0601 F6\narc: S1_V02S0001 Q0\narc: S1_V02S0101 Q3\narc: S1_V02S0201 Q0\narc: S1_V02S0701 Q5\narc: V00B0100 Q7\narc: V00T0100 Q3\narc: V01S0000 Q5\narc: V01S0100 Q7\narc: W1_H02W0501 Q7\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q7\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1111111111111100\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 1111111111111100\nword: SLICEA.K0.INIT 1111111111111100\nword: SLICEA.K1.INIT 0000000100010111\nword: SLICEC.K0.INIT 1100001100111100\nword: SLICEC.K1.INIT 1111111111111100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R8C8:PLC2\narc: H00L0100 V02N0101\narc: H00R0000 W1_H02E0601\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0401 E1_H01W0000\narc: S3_V06S0003 H01E0001\narc: V00B0100 H02E0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0601 S1_V02N0601\narc: A6 V02N0301\narc: B3 H00R0000\narc: B6 S1_V02N0701\narc: B7 V00B0000\narc: C3 V02N0401\narc: C6 S1_V02N0001\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D2 V02N0001\narc: D3 V00T0100\narc: D6 V01N0001\narc: D7 H00L0100\narc: E1_H01E0001 F6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: LSR1 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00B0000 F6\narc: V00T0000 F2\narc: V00T0100 Q3\narc: W1_H02W0301 Q3\narc: W1_H02W0501 F7\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0011110011000011\nword: SLICED.K0.INIT 0110100110010110\nword: SLICED.K1.INIT 1100001100111100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R8C9:PLC2\narc: H00L0000 V02S0001\narc: H00L0100 V02S0301\narc: H00R0000 H02W0401\narc: H00R0100 V02S0501\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: V00B0100 E1_H02W0701\narc: V00T0000 E1_H02W0201\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0401 H01E0001\narc: A0 S1_V02N0501\narc: A1 H02W0501\narc: A2 E1_H01E0001\narc: A3 H00L0100\narc: A6 H02W0701\narc: A7 H02W0701\narc: B0 V00T0000\narc: B1 E1_H02W0301\narc: B2 H01W0100\narc: B3 H00L0000\narc: B6 V00B0100\narc: B7 E1_H02W0101\narc: C0 V02N0401\narc: C1 H02W0601\narc: C2 V02S0601\narc: C3 N1_V01N0001\narc: C6 E1_H02W0401\narc: C7 E1_H02W0401\narc: D0 E1_H02W0001\narc: D1 H00R0000\narc: D2 V02N0201\narc: D3 V01S0100\narc: D6 H02W0201\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 F2\narc: E1_H02E0001 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F0\narc: N1_V01N0001 F1\narc: S3_V06S0103 F2\narc: V01S0100 F6\nword: SLICEA.K0.INIT 1011000000001011\nword: SLICEA.K1.INIT 1011000000001011\nword: SLICEB.K0.INIT 1000111100000000\nword: SLICEB.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 1001000000001001\nword: SLICED.K1.INIT 0000000000000001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R9C10:PLC2\narc: N1_V02N0301 N1_V01S0100\narc: V00B0000 E1_H02W0401\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 V02N0701\narc: A0 V02S0501\narc: A2 V02N0501\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V01S0000\narc: B6 V02N0701\narc: B7 V00B0100\narc: CE1 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q6\narc: H01W0100 Q3\narc: LSR0 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q2\narc: N1_V02N0001 Q2\narc: N1_V02N0101 Q3\narc: N1_V02N0401 Q4\narc: N1_V02N0501 Q5\narc: N1_V02N0601 Q6\narc: N1_V02N0701 Q7\narc: V00B0100 Q7\narc: V01S0000 Q5\narc: V01S0100 Q6\narc: W1_H02W0301 Q3\narc: W1_H02W0601 Q4\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R9C11:PLC2\narc: E1_H02E0501 V01N0101\narc: N1_V02N0701 N1_V01S0100\narc: V00B0000 V02N0001\narc: W1_H02W0001 H01E0001\narc: W1_H02W0301 H01E0101\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02N0701\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q0\narc: LSR0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q2\narc: N1_V02N0001 Q2\narc: N1_V02N0101 Q3\narc: N1_V02N0201 Q0\narc: N1_V02N0301 Q1\narc: N1_V02N0401 Q4\narc: N1_V02N0501 Q5\narc: V00B0100 Q5\narc: V00T0000 Q0\narc: V01S0100 Q1\narc: W1_H02W0201 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001010\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R9C12:PLC2\narc: E1_H02E0601 V02N0601\narc: N1_V02N0201 E1_H02W0201\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 H02W0701\narc: V00B0000 H02W0401\narc: W1_H02W0101 V01N0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V01N0101\narc: W3_H06W0103 V01N0101\narc: A0 H02E0501\narc: B2 V02N0101\narc: B3 V02N0301\narc: B4 H02W0301\narc: B5 V02N0501\narc: B6 V00B0000\narc: B7 V02N0701\nword: SLICEC.K0.INIT 0011110000000000\nword: SLICEC.K1.INIT 0011110000000000\nword: SLICEB.K0.INIT 0011110000000000\nword: SLICEB.K1.INIT 0011110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICED.K0.INIT 0011110000000000\nword: SLICED.K1.INIT 0011110000000000\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R9C13:PLC2\narc: H00L0000 V02N0201\narc: N1_V02N0501 E1_H02W0501\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0701 E1_H02W0701\narc: V00B0000 H02W0401\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 V01N0101\narc: B0 V02N0301\narc: B1 V02N0101\narc: B2 H00L0000\narc: B3 E1_H02W0101\narc: B4 H02W0101\narc: B5 V02N0501\narc: B6 V00B0000\narc: B7 V02N0701\nword: SLICEB.K0.INIT 0011110000000000\nword: SLICEB.K1.INIT 0011110000000000\nword: SLICED.K0.INIT 0011110000000000\nword: SLICED.K1.INIT 0011110000000000\nword: SLICEC.K0.INIT 0011110000000000\nword: SLICEC.K1.INIT 0011110000000000\nword: SLICEA.K0.INIT 0011110000000000\nword: SLICEA.K1.INIT 0011110000000000\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R9C14:PLC2\narc: E1_H02E0701 N1_V01S0100\narc: H00R0000 W1_H02E0601\narc: N1_V02N0301 E1_H01W0100\narc: S1_V02S0501 N1_V01S0100\narc: V00B0000 V02N0001\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0401 V01N0001\narc: B0 V00B0000\narc: B1 V02N0301\narc: B4 H02W0301\narc: C4 E1_H02W0401\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 S1_V02N0401\narc: D5 V02N0401\narc: E1_H01E0101 Q4\narc: F2 F2_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F2\narc: LSR0 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q4\narc: V00B0100 F5\narc: V01S0000 Q4\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 0011110000000000\nword: SLICEA.K1.INIT 0011110000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R9C15:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 V02N0601\narc: H00L0000 N1_V02S0201\narc: H00R0000 V02S0601\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S1_V02N0201\narc: V00T0000 N1_V02S0601\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0701 V06S0203\narc: A0 V02N0701\narc: A2 V02S0701\narc: A3 V02S0501\narc: A4 V00T0000\narc: A5 V02N0301\narc: A6 H00L0000\narc: A7 H00R0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: H01W0100 F5\narc: N1_V01N0101 F6\narc: N1_V02N0301 F3\narc: N1_V02N0601 F4\narc: W1_H02W0501 F7\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R9C16:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: H00L0000 V02N0001\narc: H00R0000 N1_V02S0401\narc: N1_V02N0701 S1_V02N0601\narc: V00B0000 V02S0201\narc: V00T0000 S1_V02N0601\narc: W1_H02W0401 N1_V01S0000\narc: A0 H00R0000\narc: A1 V02N0501\narc: A2 H02W0501\narc: A3 V00B0000\narc: A4 W1_H02E0701\narc: A5 V00T0000\narc: A6 H02E0501\narc: A7 H00L0000\narc: E1_H01E0001 F2\narc: E1_H01E0101 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F6\narc: N1_V01N0001 F7\narc: N1_V01N0101 F4\narc: N1_V02N0001 F0\narc: N1_V02N0301 F3\narc: S1_V02S0501 F5\nword: SLICEB.K0.INIT 0101101010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R9C17:PLC2\narc: H00L0000 N1_V02S0201\narc: H00R0000 W1_H02E0601\narc: N1_V02N0001 H01E0001\narc: N1_V02N0401 N1_V01S0000\narc: S1_V02S0501 H01E0101\narc: V00B0100 V02S0301\narc: W1_H02W0501 N1_V01S0100\narc: A0 H00L0000\narc: A1 E1_H01E0001\narc: B6 F1\narc: C6 V00B0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D6 W1_H02E0201\narc: D7 V02N0401\narc: E1_H01E0001 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR1 H02E0501\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V02N0201 F0\narc: V01S0100 Q6\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R9C2:PLC2\narc: E1_H02E0301 E3_H06W0003\narc: H00L0000 H02E0001\narc: H00L0100 V02N0301\narc: H00R0000 N1_V02S0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 H06W0303\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 E1_H02W0501\narc: V00B0100 E1_H02W0501\narc: V00T0100 V02S0701\narc: A0 E1_H02W0701\narc: A3 E1_H02W0701\narc: A5 E1_H02W0701\narc: A6 E1_H02W0701\narc: B0 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 V00B0100\narc: B6 V00B0100\narc: C0 E1_H01W0000\narc: C1 E1_H01W0000\narc: C2 E1_H01W0000\narc: C3 E1_H01W0000\narc: C4 E1_H02W0401\narc: C5 E1_H02W0401\narc: C6 E1_H02W0401\narc: C7 E1_H02W0401\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 N1_V02S0401\narc: D5 N1_V02S0401\narc: D6 N1_V02S0401\narc: D7 N1_V02S0401\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00L0100\narc: M2 V00T0100\narc: M3 H00L0000\narc: M4 V00T0100\narc: M5 H00L0100\narc: M6 V00T0100\nword: SLICEA.K0.INIT 0111111001110111\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 1111110011111111\nword: SLICEB.K1.INIT 0111001001110111\nword: SLICEC.K0.INIT 1100111111111111\nword: SLICEC.K1.INIT 0001101110111011\nword: SLICED.K0.INIT 1101101110111011\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R9C3:PLC2\narc: E1_H02E0301 E1_H01W0100\narc: H00L0100 V02S0101\narc: H00R0000 V02S0601\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 H02W0601\narc: S1_V02S0301 H02E0301\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H06W0303\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: A0 H00L0100\narc: A3 H00L0100\narc: A4 V02S0101\narc: A7 V02S0101\narc: B0 V02S0301\narc: B2 V02S0301\narc: B3 V02S0301\narc: B4 V00B0100\narc: B6 V00B0100\narc: B7 V00B0100\narc: C0 H02W0601\narc: C1 H02W0601\narc: C2 H02W0601\narc: C3 H02W0601\narc: C4 H02W0601\narc: C5 H02W0601\narc: C6 H02W0601\narc: C7 H02W0601\narc: D0 V02S0001\narc: D1 V02S0001\narc: D2 V02S0001\narc: D3 V02S0001\narc: D4 V00B0000\narc: D5 V00B0000\narc: D6 V00B0000\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: E1_H02E0101 F3\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 E1_H02W0601\narc: M1 H02W0001\narc: M2 E1_H02W0601\narc: M3 H00R0000\narc: M4 E1_H02W0401\narc: M5 H02W0001\narc: M6 E1_H02W0401\narc: N1_V01N0001 F3\nword: SLICEA.K0.INIT 1111111111010100\nword: SLICEA.K1.INIT 1111111111110000\nword: SLICEC.K0.INIT 0000000000101011\nword: SLICEC.K1.INIT 0000000000001111\nword: SLICED.K0.INIT 0000000000111111\nword: SLICED.K1.INIT 0000000000101011\nword: SLICEB.K0.INIT 1111111111000000\nword: SLICEB.K1.INIT 1111111111010100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R9C4:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0401 E1_H01W0000\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 H02W0701\narc: S1_V02S0301 S3_V06N0003\narc: V00T0100 H02W0101\narc: W1_H02W0001 V02S0001\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 E1_H02W0701\narc: B0 V02N0301\narc: C0 N1_V01N0001\narc: CLK0 G_HPBX0100\narc: D0 V00T0100\narc: D1 H02W0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: H01W0100 F1\narc: LSR0 H02E0301\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0101 Q0\nword: SLICEA.K0.INIT 1111110000001100\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R9C5:PLC2\narc: E1_H02E0601 V02N0601\narc: H00L0000 V02S0001\narc: H00L0100 N1_V02S0301\narc: N1_V02N0001 H02E0001\narc: S1_V02S0001 H02E0001\narc: V00B0100 E1_H02W0701\narc: V00T0000 H02W0201\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 N1_V01S0100\narc: W3_H06W0303 E1_H01W0100\narc: B4 W1_H02E0101\narc: B5 H00R0000\narc: B6 V00B0000\narc: B7 E1_H02W0301\narc: C3 H00L0000\narc: C4 V02S0001\narc: C5 V00T0000\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D3 V02N0001\narc: D4 H00L0100\narc: D5 V02N0401\narc: D6 V02N0401\narc: D7 E1_H02W0201\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: E1_H02E0401 F4\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H01W0000 F7\narc: H01W0100 F4\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 F7\narc: N1_V02N0401 F4\narc: N1_V02N0601 Q6\narc: S3_V06S0203 F4\narc: V00B0000 F4\narc: V01S0000 Q5\narc: V01S0100 F4\narc: W1_H02W0101 Q3\narc: W1_H02W0501 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0011110011111111\nword: SLICED.K0.INIT 0011110011111111\nword: SLICED.K1.INIT 0011110011000011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R9C6:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0601 E1_H01W0000\narc: H00L0000 E1_H02W0201\narc: H00L0100 H02W0101\narc: H00R0000 V02S0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H01E0001\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 W1_H02E0101\narc: V00B0100 V02S0101\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02S0701\narc: W1_H02W0201 E1_H02W0201\narc: A0 V02S0501\narc: A3 V02S0501\narc: B0 V00T0000\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00L0000\narc: B4 H00R0000\narc: B5 N1_V01S0000\narc: C0 W1_H02E0401\narc: C1 H00L0000\narc: C2 H00L0000\narc: C3 W1_H02E0401\narc: C4 V00B0100\narc: C5 F4\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 H01E0101\narc: D2 H01E0101\narc: D3 V02S0001\narc: D4 H02W0001\narc: D5 H01W0000\narc: D7 V02N0401\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q5\narc: H01W0100 F4\narc: LSR1 H02W0501\narc: M0 V00T0100\narc: M1 H00L0100\narc: M2 V00T0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F1\narc: N1_V02N0601 F4\narc: W1_H02W0101 F1\narc: W1_H02W0301 F1\narc: W1_H02W0401 F4\narc: W1_H02W0701 Q5\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0011110011000011\nword: SLICEC.K1.INIT 1100001100111100\nword: SLICEA.K0.INIT 0001011111101000\nword: SLICEA.K1.INIT 1100111111110011\nword: SLICEB.K0.INIT 0011111111111100\nword: SLICEB.K1.INIT 1101010000101011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R9C7:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: H00L0000 V02S0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 W1_H02E0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0301 S3_V06N0003\narc: V00B0000 V02N0201\narc: V00B0100 V02S0101\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0501 H01E0101\narc: W1_H02W0701 V02S0701\narc: A0 H00L0100\narc: A4 S1_V02N0101\narc: A6 S1_V02N0101\narc: B0 H02W0301\narc: B1 V00T0000\narc: B2 H00R0000\narc: B3 H00L0000\narc: B4 E1_H02W0101\narc: B5 V02N0701\narc: B6 V00B0000\narc: B7 H02E0301\narc: C0 W1_H02E0601\narc: C1 E1_H02W0601\narc: C2 H02E0601\narc: C3 N1_V01S0100\narc: C4 V02N0201\narc: C5 E1_H02W0601\narc: C6 W1_H02E0601\narc: C7 E1_H02W0601\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 V00T0100\narc: D2 H02W0001\narc: D3 V00B0100\narc: D4 E1_H02W0201\narc: D5 H00R0100\narc: D6 V02N0601\narc: D7 H00R0100\narc: E1_H01E0001 Q5\narc: E1_H02E0301 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 Q6\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q1\narc: N1_V01N0101 F3\narc: S1_V02S0201 Q2\narc: V00T0000 Q0\narc: V01S0000 Q7\narc: V01S0100 Q4\narc: W1_H02W0301 F3\nword: SLICEB.K0.INIT 1100001111111111\nword: SLICEB.K1.INIT 1100001100111100\nword: SLICEC.K0.INIT 1111010001000100\nword: SLICEC.K1.INIT 1111111111000000\nword: SLICEA.K0.INIT 1111010001000100\nword: SLICEA.K1.INIT 1111111111000000\nword: SLICED.K0.INIT 1111010001000100\nword: SLICED.K1.INIT 1111111111000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R9C8:PLC2\narc: E1_H02E0101 V02N0101\narc: H00R0000 N1_V02S0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 S1_V02N0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0601\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0301 V02N0301\narc: A0 E1_H01E0001\narc: A7 E1_H01W0000\narc: B0 H00R0100\narc: B1 H02W0301\narc: B2 W1_H02E0101\narc: B3 H02W0301\narc: B5 H02W0301\narc: B6 H02W0301\narc: B7 E1_H02W0101\narc: C0 W1_H02E0601\narc: C1 V02N0601\narc: C2 H00L0100\narc: C3 V02N0601\narc: C5 V00T0000\narc: C6 V00T0000\narc: C7 V02S0001\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 N1_V02S0601\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V02N0201\narc: D2 V00T0100\narc: D3 V00B0100\narc: D5 H02W0001\narc: D6 H02E0001\narc: D7 V02S0401\narc: E1_H01E0001 Q1\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: H00R0100 Q5\narc: H01W0000 Q6\narc: H01W0100 F0\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q5\narc: N1_V02N0101 Q3\narc: S3_V06S0203 F7\narc: V00T0100 Q1\narc: V01S0000 Q1\narc: V01S0100 Q6\narc: W1_H02W0101 Q1\narc: W1_H02W0201 F2\narc: W3_H06W0003 Q3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111111111111100\nword: SLICEA.K0.INIT 0111000100010111\nword: SLICEA.K1.INIT 1111111111111100\nword: SLICEB.K0.INIT 1100001100111100\nword: SLICEB.K1.INIT 1111111111111100\nword: SLICED.K0.INIT 1111111111111100\nword: SLICED.K1.INIT 1100101000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R9C9:PLC2\narc: H00L0000 E1_H02W0201\narc: H00L0100 H02W0301\narc: H00R0000 H02W0401\narc: H00R0100 V02N0501\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H06W0103\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 E1_H02W0701\narc: V00B0000 H02W0601\narc: V00B0100 S1_V02N0101\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02W0301\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0601 S1_V02N0601\narc: S3_V06S0003 W3_H06E0003\narc: A0 V02N0701\narc: A2 V00T0000\narc: A3 H02W0701\narc: A6 H00L0000\narc: A7 N1_V01N0101\narc: B0 V02N0301\narc: B1 H01W0100\narc: B2 E1_H02W0301\narc: B3 H00R0000\narc: B6 E1_H02W0301\narc: B7 H02E0101\narc: C0 E1_H02W0601\narc: C1 S1_V02N0601\narc: C2 H00L0100\narc: C3 H00R0100\narc: C6 V00T0100\narc: C7 H02W0401\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 V00B0100\narc: D2 E1_H02W0001\narc: D3 F2\narc: D6 V00B0000\narc: D7 H00R0100\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 Q0\narc: MUXCLK0 CLK0\narc: N1_V01N0001 Q1\narc: N1_V01N0101 F6\nword: SLICEA.K0.INIT 1111010001000100\nword: SLICEA.K1.INIT 1111111111000000\nword: SLICEB.K0.INIT 0000000000000001\nword: SLICEB.K1.INIT 0000000100000000\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile TAP_R10C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R10C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R11C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R11C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R12C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R14C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R14C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: L_HPBX0100 G_VPTX0100\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R15C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R15C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R16C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R16C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R17C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R17C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R18C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R19C4:TAP_DRIVE\narc: L_HPBX0100 G_VPTX0100\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R20C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: L_HPBX0100 G_VPTX0100\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R6C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R6C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R7C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R7C4:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R8C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R8C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R9C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R9C4:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile_group MIB_R50C2:PLL0_LL MIB_R50C3:BANKREF8\nword: CLKI_DIV 0000000\nword: CLKFB_DIV 0000100\nword: CLKOP_DIV 0000011\nword: CLKOP_CPHASE 0000011\nword: CLKOP_FPHASE 000\nword: CLKOS_DIV 0000001\nword: CLKOS_CPHASE 0000001\nword: CLKOS_FPHASE 000\nword: CLKOS2_DIV 0010011\nword: CLKOS2_CPHASE 0000000\nword: CLKOS2_FPHASE 000\nword: CLKOS3_DIV 1111111\nword: CLKOS3_CPHASE 0000101\nword: CLKOS3_FPHASE 000\nword: PLL_LOCK_MODE 000\nword: KVCO 000\nword: LPF_CAPACITOR 00\nword: LPF_RESISTOR 0001000\nword: ICP_CURRENT 01001\nword: FREQ_LOCK_ACCURACY 00\nword: MFG_GMC_GAIN 000\nword: MFG_GMC_TEST 1110\nword: MFG1_TEST 000\nword: MFG2_TEST 000\nword: MFG_FORCE_VFILTER 0\nword: MFG_ICP_TEST 0\nword: MFG_EN_UP 0\nword: MFG_FLOAT_ICP 0\nword: MFG_GMC_PRESET 0\nword: MFG_LF_PRESET 0\nword: MFG_GMC_RESET 0\nword: MFG_LF_RESET 0\nword: MFG_LF_RESGRND 0\nword: MFG_GMCREF_SEL 10\nword: MFG_ENABLE_FILTEROPAMP 1\nenum: MODE EHXPLLL\nenum: CLKOP_ENABLE ENABLED\nenum: CLKOS_ENABLE ENABLED\nenum: CLKOS2_ENABLE ENABLED\nenum: CLKOS3_ENABLE ENABLED\nenum: FEEDBK_PATH CLKOP\nenum: CLKOP_TRIM_POL RISING\nenum: CLKOP_TRIM_DELAY 0\nenum: CLKOS_TRIM_POL RISING\nenum: CLKOS_TRIM_DELAY 0\nenum: OUTDIVIDER_MUXA DIVA\nenum: OUTDIVIDER_MUXB DIVB\nenum: OUTDIVIDER_MUXC DIVC\nenum: OUTDIVIDER_MUXD DIVD\nenum: STDBY_ENABLE DISABLED\nenum: REFIN_RESET DISABLED\nenum: SYNC_ENABLE DISABLED\nenum: INT_LOCK_STICKY ENABLED\nenum: DPHASE_SOURCE DISABLED\nenum: PLLRST_ENA DISABLED\nenum: INTFB_WAKE DISABLED\n\n"
  },
  {
    "path": "src/hdmi_test_pattern/ulx3s_v20_segpdi.lpf",
    "content": "BLOCK RESETPATHS;\nBLOCK ASYNCPATHS;\n## ULX3S v2.x.x and v3.0.x\n\n# The clock \"usb\" and \"gpdi\" sheet\n\n#ULX3S\n#LOCATE COMP \"clk_25mhz\" SITE \"G2\"; \n\n#i5-v6.0\nLOCATE COMP \"clk_25mhz\" SITE \"P3\";\nIOBUF  PORT \"clk_25mhz\" PULLMODE=NONE IO_TYPE=LVCMOS33;\nFREQUENCY PORT \"clk_25mhz\" 25 MHZ;\n\n# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash\n# write to FLASH possible any time from JTAG:\nSYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;\n# write to FLASH possible from user bitstream:\n# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;\n\n## USBSERIAL FTDI-FPGA serial port \"usb\" sheet\nLOCATE COMP \"ftdi_rxd\" SITE \"L4\"; # FPGA transmits to ftdi\nLOCATE COMP \"ftdi_txd\" SITE \"M1\"; # FPGA receives from ftdi\nLOCATE COMP \"ftdi_nrts\" SITE \"M3\"; # FPGA receives\nLOCATE COMP \"ftdi_ndtr\" SITE \"N1\"; # FPGA receives\nLOCATE COMP \"ftdi_txden\" SITE \"L3\"; # FPGA receives\nIOBUF  PORT \"ftdi_rxd\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"ftdi_txd\" PULLMODE=UP IO_TYPE=LVCMOS33;\nIOBUF  PORT \"ftdi_nrts\" PULLMODE=UP IO_TYPE=LVCMOS33;\nIOBUF  PORT \"ftdi_ndtr\" PULLMODE=UP IO_TYPE=LVCMOS33;\nIOBUF  PORT \"ftdi_txden\" PULLMODE=UP IO_TYPE=LVCMOS33;\n\n## LED indicators \"blinkey\" and \"gpio\" sheet\n#LOCATE COMP \"led[7]\" SITE \"H3\";\n#LOCATE COMP \"led[6]\" SITE \"E1\";\n#LOCATE COMP \"led[5]\" SITE \"E2\";\n#LOCATE COMP \"led[4]\" SITE \"D1\";\n#LOCATE COMP \"led[3]\" SITE \"D2\";\n#LOCATE COMP \"led[2]\" SITE \"C1\";\n#LOCATE COMP \"led[1]\" SITE \"C2\";\n#LOCATE COMP \"led[0]\" SITE \"B2\";\n#IOBUF  PORT \"led[0]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"led[1]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"led[2]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"led[3]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"led[4]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"led[5]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"led[6]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"led[7]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;\n\n## Pushbuttons \"blinkey\", \"flash\", \"power\", \"gpdi\" sheet\nLOCATE COMP \"btn[0]\" SITE \"D6\";  # BTN_PWRn (inverted logic)\nLOCATE COMP \"btn[1]\" SITE \"R1\";  # FIRE1\nLOCATE COMP \"btn[2]\" SITE \"T1\";  # FIRE2\nLOCATE COMP \"btn[3]\" SITE \"R18\"; # UP W1->R18\nLOCATE COMP \"btn[4]\" SITE \"V1\";  # DOWN\nLOCATE COMP \"btn[5]\" SITE \"U1\";  # LEFT\nLOCATE COMP \"btn[6]\" SITE \"H16\"; # RIGHT Y2->H16\nIOBUF  PORT \"btn[0]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"btn[1]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"btn[2]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"btn[3]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"btn[4]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"btn[5]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"btn[6]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\n\n## DIP switch \"blinkey\", \"gpio\" sheet\nLOCATE COMP \"sw[0]\" SITE \"E8\"; # SW1\nLOCATE COMP \"sw[1]\" SITE \"D8\"; # SW2\nLOCATE COMP \"sw[2]\" SITE \"D7\"; # SW3\nLOCATE COMP \"sw[3]\" SITE \"E7\"; # SW4\nIOBUF  PORT \"sw[0]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"sw[1]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"sw[2]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"sw[3]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\n\n## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) \"blinkey\", \"usb\" sheet\nLOCATE COMP \"oled_clk\" SITE \"P4\";\nLOCATE COMP \"oled_mosi\" SITE \"P3\";\nLOCATE COMP \"oled_dc\" SITE \"P1\";\nLOCATE COMP \"oled_resn\" SITE \"P2\";\nLOCATE COMP \"oled_csn\" SITE \"N2\";\nIOBUF  PORT \"oled_clk\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"oled_mosi\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"oled_dc\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"oled_resn\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"oled_csn\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n\n## SPI Flash chip \"flash\" sheet\nLOCATE COMP \"flash_csn\" SITE \"R2\";\nLOCATE COMP \"flash_clk\" SITE \"U3\";\nLOCATE COMP \"flash_mosi\" SITE \"W2\";\nLOCATE COMP \"flash_miso\" SITE \"V2\";\nLOCATE COMP \"flash_holdn\" SITE \"W1\";\nLOCATE COMP \"flash_wpn\" SITE \"Y2\";\n#LOCATE COMP \"flash_csspin\" SITE \"AJ3\";\n#LOCATE COMP \"flash_initn\" SITE \"AG4\";\n#LOCATE COMP \"flash_done\" SITE \"AJ4\";\n#LOCATE COMP \"flash_programn\" SITE \"AH4\";\n#LOCATE COMP \"flash_cfg_select[0]\" SITE \"AM4\";\n#LOCATE COMP \"flash_cfg_select[1]\" SITE \"AL4\";\n#LOCATE COMP \"flash_cfg_select[2]\" SITE \"AK4\";\nIOBUF  PORT \"flash_csn\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"flash_clk\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"flash_mosi\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"flash_miso\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"flash_holdn\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"flash_wpn\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"flash_csspin\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"flash_initn\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"flash_done\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"flash_programn\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"flash_cfg_select[0]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"flash_cfg_select[1]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"flash_cfg_select[2]\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\n\n## SD card \"sdcard\", \"usb\" sheet\nLOCATE COMP \"sd_clk\" SITE \"H2\"; # sd_clk WiFi_GPIO14\nLOCATE COMP \"sd_cmd\" SITE \"J1\"; # sd_cmd_di (MOSI) WiFi GPIO15\nLOCATE COMP \"sd_d[0]\" SITE \"J3\"; # sd_dat0_do (MISO) WiFi GPIO2\nLOCATE COMP \"sd_d[1]\" SITE \"H1\"; # sd_dat1_irq WiFi GPIO4\nLOCATE COMP \"sd_d[2]\" SITE \"K1\"; # sd_dat2 WiFi_GPIO12\nLOCATE COMP \"sd_d[3]\" SITE \"K2\"; # sd_dat3_csn WiFi_GPIO13\nLOCATE COMP \"sd_wp\" SITE \"P5\"; # not connected\nLOCATE COMP \"sd_cdn\" SITE \"N5\"; # not connected\nIOBUF  PORT \"sd_clk\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"sd_cmd\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"sd_d[0]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"sd_d[1]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"sd_d[2]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement\nIOBUF  PORT \"sd_d[3]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"sd_wp\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"sd_cdn\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n\n## ADC SPI (MAX11123) \"analog\", \"ram\" sheet\nLOCATE COMP \"adc_csn\" SITE \"R17\";\nLOCATE COMP \"adc_mosi\" SITE \"R16\";\nLOCATE COMP \"adc_miso\" SITE \"U16\";\nLOCATE COMP \"adc_sclk\" SITE \"P17\";\nIOBUF  PORT \"adc_csn\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"adc_mosi\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"adc_miso\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"adc_sclk\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n\n## Audio 4-bit DAC \"analog\", \"gpio\" sheet\n# 4-bit mode can drive down to 75 ohm load impedance.\n# Lower impedance leads to IO overload, \n# FPGA will stop working and need reboot.\n# For standard 17 ohm earphones on PCB v1.7:\n# use bits 2,3 as input (High-Z) and drive only bits 0,1.\n# PCB v2.1.2 can use full 4 bits and 16mA drive for 17 ohm earphones.\n#LOCATE COMP \"audio_l[3]\" SITE \"B3\"; # JACK TIP (left audio)\n#LOCATE COMP \"audio_l[2]\" SITE \"C3\";\n#LOCATE COMP \"audio_l[1]\" SITE \"D3\";\n#LOCATE COMP \"audio_l[0]\" SITE \"E4\";\n#LOCATE COMP \"audio_r[3]\" SITE \"C5\"; # JACK RING1 (right audio)\n#LOCATE COMP \"audio_r[2]\" SITE \"D5\";\n#LOCATE COMP \"audio_r[1]\" SITE \"B5\";\n#LOCATE COMP \"audio_r[0]\" SITE \"A3\";\n#LOCATE COMP \"audio_v[3]\" SITE \"E5\"; # JACK RING2 (video or digital audio)\n#LOCATE COMP \"audio_v[2]\" SITE \"F5\";\n#LOCATE COMP \"audio_v[1]\" SITE \"F2\";\n#LOCATE COMP \"audio_v[0]\" SITE \"H5\";\n#IOBUF  PORT \"audio_l[3]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n#IOBUF  PORT \"audio_l[2]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n#IOBUF  PORT \"audio_l[1]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n#IOBUF  PORT \"audio_l[0]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n#IOBUF  PORT \"audio_r[3]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n#IOBUF  PORT \"audio_r[2]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n#IOBUF  PORT \"audio_r[1]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n#IOBUF  PORT \"audio_r[0]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n#IOBUF  PORT \"audio_v[3]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n#IOBUF  PORT \"audio_v[2]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n#IOBUF  PORT \"audio_v[1]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n#IOBUF  PORT \"audio_v[0]\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n\n## WiFi ESP-32 \"wifi\", \"usb\", \"flash\" sheet\n# other pins are shared with GP/GN, SD card and JTAG\nLOCATE COMP \"wifi_en\" SITE \"F1\"; # enable/reset WiFi\nLOCATE COMP \"wifi_rxd\" SITE \"K3\"; # FPGA transmits to WiFi\nLOCATE COMP \"wifi_txd\" SITE \"K4\"; # FPGA receives from WiFi\nLOCATE COMP \"wifi_gpio0\" SITE \"L2\";\nLOCATE COMP \"wifi_gpio5\" SITE \"N4\"; # WIFI LED\nLOCATE COMP \"wifi_gpio16\" SITE \"L1\"; # Serial1 RX\nLOCATE COMP \"wifi_gpio17\" SITE \"N3\"; # Serial1 TX\n# LOCATE COMP \"prog_done\" SITE \"Y3\"; # not GPIO, always active\nIOBUF  PORT \"wifi_en\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"wifi_rxd\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"wifi_txd\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"wifi_gpio0\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"wifi_gpio16\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF  PORT \"wifi_gpio17\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n# IOBUF  PORT \"prog_done\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n\n## PCB antenna 433 MHz (may be also used for FM) \"usb\" sheet\nLOCATE COMP \"ant_433mhz\" SITE \"G1\";\nIOBUF  PORT \"ant_433mhz\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;\n\n## Second USB port \"US2\" going directly into FPGA \"usb\", \"ram\" sheet\nLOCATE COMP \"usb_fpga_dp\" SITE \"E16\"; # single ended or differential input only\nLOCATE COMP \"usb_fpga_dn\" SITE \"F16\";\nIOBUF  PORT \"usb_fpga_dp\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\nIOBUF  PORT \"usb_fpga_dn\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\nLOCATE COMP \"usb_fpga_bd_dp\" SITE \"D15\"; # differential bidirectional\nLOCATE COMP \"usb_fpga_bd_dn\" SITE \"E15\";\nIOBUF  PORT \"usb_fpga_bd_dp\" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4;\nIOBUF  PORT \"usb_fpga_bd_dn\" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4;\nLOCATE COMP \"usb_fpga_pu_dp\" SITE \"B12\"; # pull up/down control\nLOCATE COMP \"usb_fpga_pu_dn\" SITE \"C12\";\nIOBUF  PORT \"usb_fpga_pu_dp\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\nIOBUF  PORT \"usb_fpga_pu_dn\" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;\n\n## JTAG ESP-32 \"usb\" sheet\n# connected to FT231X and ESP-32\n# commented out because those are dedicated pins, not directly useable as GPIO\n# but could be used by some vendor-specific JTAG bridging (boundary scan) module\n#LOCATE COMP \"jtag_tdi\" SITE \"R5\"; # FTDI_nRI   FPGA receives\n#LOCATE COMP \"jtag_tdo\" SITE \"V4\"; # FTDI_nCTS  FPGA transmits\n#LOCATE COMP \"jtag_tck\" SITE \"T5\"; # FTDI_nDSR  FPGA receives\n#LOCATE COMP \"jtag_tms\" SITE \"U5\"; # FTDI_nDCD  FPGA receives\n#IOBUF  PORT \"jtag_tdi\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"jtag_tdo\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"jtag_tck\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF  PORT \"jtag_tms\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n\n## SDRAM \"ram\" sheet\n\n# GPDI differential interface (Video) \"gpdi\" sheet\n#LOCATE COMP \"gpdi_dp[0]\" SITE \"A16\"; # Blue +\n#LOCATE COMP \"gpdi_dn[0]\" SITE \"B16\"; # Blue -\n#LOCATE COMP \"gpdi_dp[1]\" SITE \"A14\"; # Green +\n#LOCATE COMP \"gpdi_dn[1]\" SITE \"C14\"; # Green -\n#LOCATE COMP \"gpdi_dp[2]\" SITE \"A12\"; # Red +\n#LOCATE COMP \"gpdi_dn[2]\" SITE \"A13\"; # Red -\n#LOCATE COMP \"gpdi_dp[3]\" SITE \"A17\"; # Clock +\n#LOCATE COMP \"gpdi_dn[3]\" SITE \"B18\"; # Clock -\n\n#i5-v6.0 HDMI\nLOCATE COMP \"gpdi_dp[0]\" SITE \"G19\"; # Blue +\nLOCATE COMP \"gpdi_dn[0]\" SITE \"H20\"; # Blue -\nLOCATE COMP \"gpdi_dp[1]\" SITE \"E20\"; # Green +\nLOCATE COMP \"gpdi_dn[1]\" SITE \"F19\"; # Green -\nLOCATE COMP \"gpdi_dp[2]\" SITE \"C20\"; # Red +\nLOCATE COMP \"gpdi_dn[2]\" SITE \"D19\"; # Red -\nLOCATE COMP \"gpdi_dp[3]\" SITE \"J19\"; # Clock +\nLOCATE COMP \"gpdi_dn[3]\" SITE \"K19\"; # Clock -\n\n#i5-v6.0 PMOD-HDMI-P3a\n#LOCATE COMP \"gpdi_dp[0]\" SITE \"C2\"; # Blue +\n#LOCATE COMP \"gpdi_dn[0]\" SITE \"E3\"; # Blue -\n#LOCATE COMP \"gpdi_dp[1]\" SITE \"E2\"; # Green +\n#LOCATE COMP \"gpdi_dn[1]\" SITE \"D2\"; # Green -\n#LOCATE COMP \"gpdi_dp[2]\" SITE \"D1\"; # Red +\n#LOCATE COMP \"gpdi_dn[2]\" SITE \"C1\"; # Red -\n#LOCATE COMP \"gpdi_dp[3]\" SITE \"B1\"; # Clock +\n#LOCATE COMP \"gpdi_dn[3]\" SITE \"A3\"; # Clock -\n\n#i5-v6.0 PMOD-HDMI-P3b\n#LOCATE COMP \"gpdi_dp[0]\" SITE \"B20\"; # Blue +\n#LOCATE COMP \"gpdi_dn[0]\" SITE \"F20\"; # Blue -\n#LOCATE COMP \"gpdi_dp[1]\" SITE \"A18\"; # Green +\n#LOCATE COMP \"gpdi_dn[1]\" SITE \"A19\"; # Green -\n#LOCATE COMP \"gpdi_dp[2]\" SITE \"C17\"; # Red +\n#LOCATE COMP \"gpdi_dn[2]\" SITE \"B18\"; # Red -\n#LOCATE COMP \"gpdi_dp[3]\" SITE \"B19\"; # Clock +\n#LOCATE COMP \"gpdi_dn[3]\" SITE \"D20\"; # Clock -\n\n#LOCATE COMP \"gpdi_ethp\" SITE \"A19\"; # Ethernet +\n#LOCATE COMP \"gpdi_ethn\" SITE \"B20\"; # Ethernet -\n#LOCATE COMP \"gpdi_cec\" SITE \"A18\";\n#LOCATE COMP \"gpdi_sda\" SITE \"B19\"; # I2C shared with RTC\n#LOCATE COMP \"gpdi_scl\" SITE \"E12\"; # I2C shared with RTC C12->E12\nIOBUF PORT \"gpdi_dp[0]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dn[0]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dp[1]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dn[1]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dp[2]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dn[2]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dp[3]\" IO_TYPE=LVCMOS33 DRIVE=4;\nIOBUF PORT \"gpdi_dn[3]\" IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT \"gpdi_ethp\" IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT \"gpdi_ethn\" IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT \"gpdi_cec\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT \"gpdi_sda\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT \"gpdi_scl\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n\n# GPIO (default single-ended) \"gpio\", \"ram\", \"gpdi\" sheet\n# Pins enumerated gp[0-27], gn[0-27].\n# With differential mode enabled on Lattice,\n# gp[] (+) are used, gn[] (-) are ignored from design\n# as they handle inverted signal by default.\n# To enable differential, rename LVCMOS33->LVCMOS33D\n#LOCATE COMP \"gp[0]\"  SITE \"B11\"; # J1_5+  GP0\n#LOCATE COMP \"gn[0]\"  SITE \"C11\"; # J1_5-  GN0\n#LOCATE COMP \"gp[1]\"  SITE \"A10\"; # J1_7+  GP1\n#LOCATE COMP \"gn[1]\"  SITE \"A11\"; # J1_7-  GN1\n#LOCATE COMP \"gp[2]\"  SITE \"A9\";  # J1_9+  GP2\n#LOCATE COMP \"gn[2]\"  SITE \"B10\"; # J1_9-  GN2\n#LOCATE COMP \"gp[3]\"  SITE \"B9\";  # J1_11+ GP3\n#LOCATE COMP \"gn[3]\"  SITE \"C10\"; # J1_11- GN3\n#LOCATE COMP \"gp[4]\"  SITE \"A7\";  # J1_13+ GP4\n#LOCATE COMP \"gn[4]\"  SITE \"A8\";  # J1_13- GN4\n#LOCATE COMP \"gp[5]\"  SITE \"C8\";  # J1_15+ GP5\n#LOCATE COMP \"gn[5]\"  SITE \"B8\";  # J1_15- GN5\n#LOCATE COMP \"gp[6]\"  SITE \"C6\";  # J1_17+ GP6\n#LOCATE COMP \"gn[6]\"  SITE \"C7\";  # J1_17- GN6\n#IOBUF PORT  \"gp[0]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[0]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[1]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[1]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[2]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[2]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[3]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[3]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[4]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[4]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[5]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[5]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[6]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[6]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#LOCATE COMP \"gp[7]\"  SITE \"A6\";  # J1_23+ GP7\n#LOCATE COMP \"gn[7]\"  SITE \"B6\";  # J1_23- GN7\n#LOCATE COMP \"gp[8]\"  SITE \"A4\";  # J1_25+ GP8\n#LOCATE COMP \"gn[8]\"  SITE \"A5\";  # J1_25- GN8\n#LOCATE COMP \"gp[9]\"  SITE \"A2\";  # J1_27+ GP9\n#LOCATE COMP \"gn[9]\"  SITE \"B1\";  # J1_27- GN9\n#LOCATE COMP \"gp[10]\" SITE \"C4\";  # J1_29+ GP10  WIFI_GPIO27\n#LOCATE COMP \"gn[10]\" SITE \"B4\";  # J1_29- GN10\n#LOCATE COMP \"gp[11]\" SITE \"F4\";  # J1_31+ GP11  WIFI_GPIO25\n#LOCATE COMP \"gn[11]\" SITE \"E3\";  # J1_31- GN11  WIFI_GPIO26\n#LOCATE COMP \"gp[12]\" SITE \"G3\";  # J1_33+ GP12  WIFI_GPIO32\n#LOCATE COMP \"gn[12]\" SITE \"F3\";  # J1_33- GN12  WIFI_GPIO33\n#LOCATE COMP \"gp[13]\" SITE \"H4\";  # J1_35+ GP13  WIFI_GPIO34\n#LOCATE COMP \"gn[13]\" SITE \"G5\";  # J1_35- GN13  WIFI_GPIO35\n#IOBUF PORT  \"gp[7]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[7]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[8]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[8]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[9]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[9]\"  PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[10]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[10]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[11]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[11]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[12]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[12]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[13]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[13]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#LOCATE COMP \"gp[14]\" SITE \"U18\"; # J2_5+  GP14\n#LOCATE COMP \"gn[14]\" SITE \"U17\"; # J2_5-  GN14\n#LOCATE COMP \"gp[15]\" SITE \"N17\"; # J2_7+  GP15\n#LOCATE COMP \"gn[15]\" SITE \"P16\"; # J2_7-  GN15\n#LOCATE COMP \"gp[16]\" SITE \"N16\"; # J2_9+  GP16\n#LOCATE COMP \"gn[16]\" SITE \"M17\"; # J2_9-  GN16\n#LOCATE COMP \"gp[17]\" SITE \"L16\"; # J2_11+ GP17\n#LOCATE COMP \"gn[17]\" SITE \"L17\"; # J2_11- GN17\n#LOCATE COMP \"gp[18]\" SITE \"H18\"; # J2_13+ GP18\n#LOCATE COMP \"gn[18]\" SITE \"H17\"; # J2_13- GN18\n#LOCATE COMP \"gp[19]\" SITE \"F17\"; # J2_15+ GP19\n#LOCATE COMP \"gn[19]\" SITE \"G18\"; # J2_15- GN19\n#LOCATE COMP \"gp[20]\" SITE \"D18\"; # J2_17+ GP20\n#LOCATE COMP \"gn[20]\" SITE \"E17\"; # J2_17- GN20\n#IOBUF PORT  \"gp[14]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[14]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[15]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[15]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[16]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[16]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[17]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[17]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[18]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[18]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[19]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[19]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[20]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[20]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#LOCATE COMP \"gp[21]\" SITE \"C18\"; # J2_23+ GP21\n#LOCATE COMP \"gn[21]\" SITE \"D17\"; # J2_23- GN21\n#LOCATE COMP \"gp[22]\" SITE \"B15\"; # J2_25+ GP22 D15->B15\n#LOCATE COMP \"gn[22]\" SITE \"C15\"; # J2_25- GN22 E15->C15\n#LOCATE COMP \"gp[23]\" SITE \"B17\"; # J2_27+ GP23\n#LOCATE COMP \"gn[23]\" SITE \"C17\"; # J2_27- GN23\n#LOCATE COMP \"gp[24]\" SITE \"C16\"; # J2_29+ GP24\n#LOCATE COMP \"gn[24]\" SITE \"D16\"; # J2_29- GN24\n#LOCATE COMP \"gp[25]\" SITE \"D14\"; # J2_31+ GP25 B15->D14\n#LOCATE COMP \"gn[25]\" SITE \"E14\"; # J2_31- GN25 C15->E14\n#LOCATE COMP \"gp[26]\" SITE \"B13\"; # J2_33+ GP26\n#LOCATE COMP \"gn[26]\" SITE \"C13\"; # J2_33- GN26\n#LOCATE COMP \"gp[27]\" SITE \"D13\"; # J2_35+ GP27\n#LOCATE COMP \"gn[27]\" SITE \"E13\"; # J2_35- GN27\n#IOBUF PORT  \"gp[21]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[21]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[22]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[22]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[23]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[23]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[24]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[24]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[25]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[25]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[26]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[26]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gp[27]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n#IOBUF PORT  \"gn[27]\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n\n## PROGRAMN (reload bitstream from FLASH, exit from bootloader)\n# PCB v2.0.5 and higher\nLOCATE COMP \"user_programn\" SITE \"M4\";\nIOBUF  PORT \"user_programn\" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;\n\n## SHUTDOWN \"power\", \"ram\" sheet (connected from PCB v1.7.5)\n# on PCB v1.7 shutdown is not connected to FPGA\nLOCATE COMP \"shutdown\" SITE \"G16\"; # FPGA receives\nIOBUF  PORT \"shutdown\" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;\n"
  },
  {
    "path": "src/hdmi_test_pattern/vgatestsrc.v",
    "content": "////////////////////////////////////////////////////////////////////////////////\n//\n// Filename: \tvgatestsrc.v\n//\n// Project:\tvgasim, a Verilator based VGA simulator demonstration\n//\n// Purpose:\tTo create a series of colorbars, as a testing pattern.\n//\n// Creator:\tDan Gisselquist, Ph.D.\n//\t\tGisselquist Technology, LLC\n//\n////////////////////////////////////////////////////////////////////////////////\n//\n// Copyright (C) 2017-2018, Gisselquist Technology, LLC\n//\n// This program is free software (firmware): you can redistribute it and/or\n// modify it under the terms of  the GNU General Public License as published\n// by the Free Software Foundation, either version 3 of the License, or (at\n// your option) any later version.\n//\n// This program is distributed in the hope that it will be useful, but WITHOUT\n// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or\n// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License\n// for more details.\n//\n// You should have received a copy of the GNU General Public License along\n// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no\n// target there if the PDF file isn't present.)  If not, see\n// <http://www.gnu.org/licenses/> for a copy.\n//\n// License:\tGPL, v3, as defined and found on www.gnu.org,\n//\t\thttp://www.gnu.org/licenses/gpl.html\n//\n//\n////////////////////////////////////////////////////////////////////////////////\n//\n//\n`default_nettype\tnone\n//\nmodule\tvgatestsrc(i_pixclk, i_reset,\n\t\t// External connections\n\t\ti_width, i_height,\n\t\ti_rd, i_newline, i_newframe,\n\t\t// VGA connections\n\t\to_pixel);\n\tparameter\tBITS_PER_COLOR = 4,\n\t\t\tHW=12, VW=12;\n\t\t//HW=13,VW=11;\n\tlocalparam\tBPC = BITS_PER_COLOR,\n\t\t\tBITS_PER_PIXEL = 3 * BPC,\n\t\t\tBPP = BITS_PER_PIXEL;\n\t//\n\tinput\twire\t\t\ti_pixclk, i_reset;\n\tinput\twire\t[HW-1:0]\ti_width;\n\tinput\twire\t[VW-1:0]\ti_height;\n\t//\n\tinput\twire\t\ti_rd, i_newline, i_newframe;\n\t//\n\toutput\treg\t[(BPP-1):0]\to_pixel;\n\n\n\n\twire\t[BPP-1:0]\twhite, black, purplish_blue, purple, dark_gray,\n\t\t\t\tdarkest_gray, mid_white, mid_cyan, mid_magenta,\n\t\t\t\tmid_red, mid_green, mid_blue, mid_yellow;\n\twire\t[BPC-1:0]\tmidv, mid_off;\n\n\tassign\tmidv    = { 2'b11, {(BPC-2){1'b0}} };\n\tassign\tmid_off = { (BPC){1'b0} };\n\n\tassign\twhite = {(BPP){1'b1}};\n\tassign\tblack = {(BPP){1'b0}};\n\tassign\tpurplish_blue = {\n\t\t\t\t{(BPC){1'b0}},\n\t\t\t\t3'b001,  {(BPC-3){1'b0}},\n\t\t\t\t2'b01, {(BPC-2){1'b0}} };\n\tassign\tpurple = { {2'b00, {(BPC-2){1'b1}} }, {(BPC){1'b0}},\n\t\t\t{ 1'b0, {(BPC-1){1'b1}} } };\n\n\tassign\tdark_gray    = {(3){  { 4'b0010, {(BPC-4){1'b0}} } }};\n\tassign\tdarkest_gray = {(3){  { 4'b0001, {(BPC-4){1'b0}} } }};\n\n\tassign\tmid_white   = { midv,    midv,    midv    };\n\tassign\tmid_yellow  = { midv,    midv,    mid_off };\n\tassign\tmid_red     = { midv,    mid_off, mid_off };\n\tassign\tmid_green   = { mid_off, midv,    mid_off };\n\tassign\tmid_blue    = { mid_off, mid_off, midv    };\n\tassign\tmid_cyan    = { mid_off, midv,    midv    };\n\tassign\tmid_magenta = { midv,    mid_off, midv    };\n\n\treg\t[HW-1:0]\thpos, hedge;\n\treg\t[VW-1:0]\typos, yedge;\n\treg\t[3:0]\t\tyline, hbar;\n\t//\n\t//\n\t// 1 Border\n\t// 8 BARS\n\t// 1 short bar\n\t// 3 fat bars\n\t// 1 border\n\t// 1 gradient bar\n\t// 1 border\n\t//\n\treg\tdline;\n\talways @(posedge i_pixclk)\n\tif ((i_reset)||(i_newframe)||(i_newline))\n\t\tdline <= 1'b0;\n\telse if (i_rd)\n\t\tdline <= 1'b1;\n\t\n\talways @(posedge i_pixclk)\n\tif ((i_reset)||(i_newframe))\n\tbegin\n\t\typos  <= 0;\n\t\tyline <= 0;\n\t\tyedge <= { 4'h0, i_height[(VW-1):4] };\n\tend else if (i_newline)\n\tbegin\n\t\typos <= ypos + { {(VW-1){1'h0}}, dline };\n\t\tif (ypos >= yedge)\n\t\tbegin\n\t\t\tyline <= yline + 1'b1;\n\t\t\tyedge <= yedge + { 4'h0, i_height[(VW-1):4] };\n\t\tend\n\tend\n\n\tinitial\thpos  = 0;\n\tinitial\thbar  = 0;\n\tinitial\thedge = 0; // { 4'h0, i_width[(HW-1):4] };\n\talways @(posedge i_pixclk)\n\tif ((i_reset)||(i_newline))\n\tbegin\n\t\thpos <= 0;\n\t\thbar <= 0;\n\t\thedge <= { 4'h0, i_width[(HW-1):4] };\n\tend else if (i_rd)\n\tbegin\n\t\thpos <= hpos + 1'b1;\n\t\tif (hpos >= hedge)\n\t\tbegin\n\t\t\thbar <= hbar + 1'b1;\n\t\t\thedge <= hedge + { 4'h0, i_width[(HW-1):4] };\n\t\tend\n\tend\n\n\treg\t[BPP-1:0]\ttopbar, midbar, fatbar, gradient, pattern;\n\talways @(posedge i_pixclk)\n\tcase(hbar[3:0])\n\t4'h0: topbar <= black;\n\t4'h1: topbar <= mid_white;\n\t4'h2: topbar <= mid_white;\n\t4'h3: topbar <= mid_yellow;\n\t4'h4: topbar <= mid_yellow;\n\t4'h5: topbar <= mid_cyan;\n\t4'h6: topbar <= mid_cyan;\n\t4'h7: topbar <= mid_green;\n\t4'h8: topbar <= mid_green;\n\t4'h9: topbar <= mid_magenta;\n\t4'ha: topbar <= mid_magenta;\n\t4'hb: topbar <= mid_red;\n\t4'hc: topbar <= mid_red;\n\t4'hd: topbar <= mid_blue;\n\t4'he: topbar <= mid_blue;\n\t4'hf: topbar <= black;\n\tendcase\n\n\talways @(posedge i_pixclk)\n\tcase(hbar[3:0])\n\t4'h0: midbar <= black;\n\t4'h1: midbar <= mid_blue;\n\t4'h2: midbar <= mid_blue;\n\t4'h3: midbar <= black;\n\t4'h4: midbar <= black;\n\t4'h5: midbar <= mid_magenta;\n\t4'h6: midbar <= mid_magenta;\n\t4'h7: midbar <= black;\n\t4'h8: midbar <= black;\n\t4'h9: midbar <= mid_cyan;\n\t4'ha: midbar <= mid_cyan;\n\t4'hb: midbar <= black;\n\t4'hc: midbar <= black;\n\t4'hd: midbar <= mid_white;\n\t4'he: midbar <= mid_white;\n\t4'hf: midbar <= black;\n\tendcase\n\n\talways @(posedge i_pixclk)\n\tcase(hbar[3:0])\n\t4'h0: fatbar <= black;\n\t4'h1: fatbar <= purplish_blue;\n\t4'h2: fatbar <= purplish_blue;\n\t4'h3: fatbar <= purplish_blue;\n\t4'h4: fatbar <=\twhite;\n\t4'h5: fatbar <= white;\n\t4'h6: fatbar <= white;\n\t4'h7: fatbar <= purple;\n\t4'h8: fatbar <= purple;\n\t4'h9: fatbar <= purple;\n\t4'ha: fatbar <= darkest_gray;\n\t4'hb: fatbar <= black;\n\t4'hc: fatbar <= dark_gray;\n\t4'hd: fatbar <= darkest_gray;\n\t4'he: fatbar <= black;\n\t4'hf: fatbar <= black;\n\tendcase\n\n\treg\t[(HW-1):0]\tlast_width;\n\talways @(posedge i_pixclk)\n\t\tlast_width <= i_width;\n\n\t// Attempt to discover 1/i_width in h_step\n\tlocalparam\tFRACB=16;\n\t//\n\treg\t[(FRACB-1):0]\thfrac, h_step;\n\talways @(posedge i_pixclk)\n\tif ((i_reset)||(i_newline))\n\t\thfrac <= 0;\n\telse if (i_rd)\n\t\thfrac <= hfrac + h_step;\n\n\talways @(posedge i_pixclk)\n\tif ((i_reset)||(i_width != last_width))\n\t\th_step <= 1;\n\telse if ((i_newline)&&(hfrac > 0))\n\tbegin\n\t\tif (hfrac < {(FRACB){1'b1}} - { {(FRACB-HW){1'b0}}, i_width })\n\t\t\th_step <= h_step + 1'b1;\n\t\telse if (hfrac < { {(FRACB-HW){1'b0}}, i_width })\n\t\t\th_step <= h_step - 1'b1;\n\tend\n\n\talways @(posedge i_pixclk)\n\tcase(hfrac[FRACB-1:FRACB-4])\n\t4'h0: gradient <= black;\n\t// Red\n\t4'h1: gradient <= { 1'b0, hfrac[(FRACB-5):(FRACB-3-BPC)], {(2){mid_off}} };\n\t4'h2: gradient <= { 1'b1, hfrac[(FRACB-5):(FRACB-3-BPC)], {(2){mid_off}} };\n\t4'h3: gradient <= black;\n\t// Green\n\t4'h4: gradient <= { mid_off, 1'b0, hfrac[(FRACB-5):(FRACB-3-BPC)], mid_off };\n\t4'h5: gradient <= { mid_off, 1'b1, hfrac[(FRACB-5):(FRACB-3-BPC)], mid_off };\n\t4'h6: gradient <= black;\n\t// Blue\n\t4'h7: gradient <= { {(2){mid_off}}, 1'b0, hfrac[(FRACB-5):(FRACB-3-BPC)] };\n\t4'h8: gradient <= { {(2){mid_off}}, 1'b1, hfrac[(FRACB-5):(FRACB-3-BPC)] };\n\t4'h9: gradient <= black;\n\t// Gray\n\t4'ha: gradient <= {(3){ 2'b00, hfrac[(FRACB-5):(FRACB-2-BPC)] }};\n\t4'hb: gradient <= {(3){ 2'b01, hfrac[(FRACB-5):(FRACB-2-BPC)] }};\n\t4'hc: gradient <= {(3){ 2'b10, hfrac[(FRACB-5):(FRACB-2-BPC)] }};\n\t4'hd: gradient <= {(3){ 2'b11, hfrac[(FRACB-5):(FRACB-2-BPC)] }};\n\t4'he: gradient <= black;\n\t//\n\t4'hf: gradient <= black;\n\tendcase\n\n\talways @(posedge i_pixclk)\n\tcase(yline)\n\t4'h0: pattern <= black;\n\t4'h1: pattern <= topbar; //\n\t4'h2: pattern <= topbar;\n\t4'h3: pattern <= topbar;\n\t4'h4: pattern <= topbar;\n\t4'h5: pattern <= topbar;\n\t4'h6: pattern <= topbar;\n\t4'h7: pattern <= topbar;\n\t4'h8: pattern <= topbar;\n\t4'h9: pattern <= midbar; //\n\t4'ha: pattern <= fatbar; //\n\t4'hb: pattern <= fatbar;\n\t4'hc: pattern <= fatbar;\n\t4'hd: pattern <= black;\n\t4'he: pattern <= gradient;\n\t4'hf: pattern <= black;\n\tendcase\n\n\talways @(posedge i_pixclk)\n\tif (i_newline)\n\t\to_pixel <= white;\n\telse if (i_rd)\n\tbegin\n\t\tif (hpos == i_width-12'd3)\n\t\t\to_pixel <= white;\n\t\telse if ((ypos == 0)||(ypos == i_height-1))\n\t\t\to_pixel <= white;\n\t\telse\n\t\t\to_pixel <= pattern;\n\tend\n\nendmodule\n\n"
  },
  {
    "path": "src/hdmi_test_pattern/ysgen.sh",
    "content": "#!/bin/sh\n# first file is toplevel file\n\nfor file in $*\ndo\n  echo \"read_verilog ${file}\"\ndone\n"
  },
  {
    "path": "src/litex_linux/README.md",
    "content": "# source code\nhttps://github.com/litex-hub/linux-on-litex-vexriscv.git\n\n# how to build\njust pick a ECP5 type board and generate the verilog source files, enter the build directory and do some little modify of the Makefile and lpf file  \nthis project is borrowed from ULX3S board in linux-on-litex-vexriscv\n\n"
  },
  {
    "path": "src/litex_linux/build_top.sh",
    "content": "# Autogenerated by LiteX / git: 275932f5\nset -e\nyosys -l top.rpt top.ys\nnextpnr-ecp5 --json top.json --lpf top_bg256.lpf --textcfg top.config --25k --package CABGA256 --speed 6 --timing-allow-fail  --seed 1\necppack top.config --svf top.svf --bit top.bit --bootaddr 0 \n"
  },
  {
    "path": "src/litex_linux/mem.init",
    "content": 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na50ab56b\n35b5a8fa\n42b2986c\ndbbbc9d6\nacbcf940\n32d86ce3\n45df5c75\ndcd60dcf\nabd13d59\n26d930ac\n51de003a\nc8d75180\nbfd06116\n21b4f4b5\n56b3c423\ncfba9599\nb8bda50f\n2802b89e\n5f058808\nc60cd9b2\nb10be924\n2f6f7c87\n58684c11\nc1611dab\nb6662d3d\n76dc4190\n1db7106\n98d220bc\nefd5102a\n71b18589\n6b6b51f\n9fbfe4a5\ne8b8d433\n7807c9a2\nf00f934\n9609a88e\ne10e9818\n7f6a0dbb\n86d3d2d\n91646c97\ne6635c01\n6b6b51f4\n1c6c6162\n856530d8\nf262004e\n6c0695ed\n1b01a57b\n8208f4c1\nf50fc457\n65b0d9c6\n12b7e950\n8bbeb8ea\nfcb9887c\n62dd1ddf\n15da2d49\n8cd37cf3\nfbd44c65\n4db26158\n3ab551ce\na3bc0074\nd4bb30e2\n4adfa541\n3dd895d7\na4d1c46d\nd3d6f4fb\n4369e96a\n346ed9fc\nad678846\nda60b8d0\n44042d73\n33031de5\naa0a4c5f\ndd0d7cc9\n5005713c\n270241aa\nbe0b1010\nc90c2086\n5768b525\n206f85b3\nb966d409\nce61e49f\n5edef90e\n29d9c998\nb0d09822\nc7d7a8b4\n59b33d17\n2eb40d81\nb7bd5c3b\nc0ba6cad\nedb88320\n9abfb3b6\n3b6e20c\n74b1d29a\nead54739\n9dd277af\n4db2615\n73dc1683\ne3630b12\n94643b84\nd6d6a3e\n7a6a5aa8\ne40ecf0b\n9309ff9d\na00ae27\n7d079eb1\nf00f9344\n8708a3d2\n1e01f268\n6906c2fe\nf762575d\n806567cb\n196c3671\n6e6b06e7\nfed41b76\n89d32be0\n10da7a5a\n67dd4acc\nf9b9df6f\n8ebeeff9\n17b7be43\n60b08ed5\nd6d6a3e8\na1d1937e\n38d8c2c4\n4fdff252\nd1bb67f1\na6bc5767\n3fb506dd\n48b2364b\nd80d2bda\naf0a1b4c\n36034af6\n41047a60\ndf60efc3\na867df55\n316e8eef\n4669be79\ncb61b38c\nbc66831a\n256fd2a0\n5268e236\ncc0c7795\nbb0b4703\n220216b9\n5505262f\nc5ba3bbe\nb2bd0b28\n2bb45a92\n5cb36a04\nc2d7ffa7\nb5d0cf31\n2cd99e8b\n5bdeae1d\n9b64c2b0\nec63f226\n756aa39c\n26d930a\n9c0906a9\neb0e363f\n72076785\n5005713\n95bf4a82\ne2b87a14\n7bb12bae\ncb61b38\n92d28e9b\ne5d5be0d\n7cdcefb7\nbdbdf21\n86d3d2d4\nf1d4e242\n68ddb3f8\n1fda836e\n81be16cd\nf6b9265b\n6fb077e1\n18b74777\n88085ae6\nff0f6a70\n66063bca\n11010b5c\n8f659eff\nf862ae69\n616bffd3\n166ccf45\na00ae278\nd70dd2ee\n4e048354\n3903b3c2\na7672661\nd06016f7\n4969474d\n3e6e77db\naed16a4a\nd9d65adc\n40df0b66\n37d83bf0\na9bcae53\ndebb9ec5\n47b2cf7f\n30b5ffe9\nbdbdf21c\ncabac28a\n53b39330\n24b4a3a6\nbad03605\ncdd70693\n54de5729\n23d967bf\nb3667a2e\nc4614ab8\n5d681b02\n2a6f2b94\nb40bbe37\nc30c8ea1\n5a05df1b\n2d02ef8d\n86325\n23\n732a255b\n5b0d5d\n42756c25\n0\n4b756c25\n4269\n4d756c25\n4269\n47756c25\n4269\n30207325\n2d782578\n78257830\n20\nd202020\n0\n72572020\n3a657469\n0\n52202020\n3a646165\n0\n736d654d\n64656570\n20746120\n70257830\n2820\n2e2e2e29\na\n72572020\n20657469\n65657073\n203a64\n732f\n52202020\n20646165\n65657073\n203a64\n746d654d\n20747365\n30207461\n20702578\n28\n75622020\n72652073\n73726f72\n2520203a\n6c252f64\na64\n64612020\n65207264\n726f7272\n25203a73\n6c252f64\na64\n61642020\n65206174\n726f7272\n25203a73\n6c252f64\na64\n746d654d\n20747365\na4f4b\n746d654d\n20747365\na4b4f\n4c554e3c\n3e4c\n0\nf0003020\nf0003018\n10000000\n10000010\n10000020\n10000030\n10000040\n10000050\n10000060\n10000070\n10000080\n10000090\n100000a0\n100000b0\n100000c0\n100000d0\n100000e0\n1348\n65f8\n6600\n0\n4c74\n6610\n6620\n0\n1238\n6630\n6644\n0\n13c4\n665c\n6660\n0\n130c\n6690\n6698\n0\n1240\n66b4\n66bc\n0\n17d8\n67fc\n6808\n2\n1724\n681c\n6828\n2\n156c\n683c\n6848\n2\n1474\n685c\n6868\n2\n166c\n687c\n6888\n2\ned0\n689c\n68a8\n1\nb94\n68bc\n68c8\n1\n18c0\n68e0\n68e8\n1\n18d0\n68f0\n68fc\n5\n1\n0\n9f19f473\n"
  },
  {
    "path": "src/litex_linux/mem_1.init",
    "content": ""
  },
  {
    "path": "src/litex_linux/mem_2.init",
    "content": "4c\n69\n74\n65\n58\n20\n53\n6f\n43\n20\n6f\n6e\n20\n55\n4c\n58\n33\n53\n20\n32\n30\n32\n30\n2d\n31\n31\n2d\n31\n31\n20\n30\n39\n3a\n34\n33\n3a\n33\n34\n0\n"
  },
  {
    "path": "src/litex_linux/top.config",
    "content": ".device LFE5U-25F\n\n.comment Part: LFE5U-25F-6CABGA256\n\n.tile CIB_R10C1:CIB_LR\narc: E1_H02E0601 E3_H06W0303\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0003 H06W0003\narc: S3_V06S0303 E3_H06W0303\n\n.tile CIB_R10C71:CIB_LR\narc: N1_V01N0001 N3_V06S0003\narc: S3_V06S0103 H06E0103\n\n.tile CIB_R11C1:CIB_LR\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V02S0601\n\n.tile CIB_R11C71:CIB_LR\narc: H00R0000 W1_H02E0601\narc: JA0 H00R0000\narc: S1_V02S0501 N1_V02S0401\narc: S3_V06S0103 N3_V06S0003\narc: W3_H06W0203 V06N0203\nenum: CIB.JB0MUX 0\n\n.tile CIB_R12C1:CIB_LR\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 E1_H01W0000\narc: S3_V06S0003 E3_H06W0003\n\n.tile CIB_R12C71:CIB_LR\narc: S1_V02S0501 H06E0303\narc: S3_V06S0103 N3_V06S0103\n\n.tile CIB_R13C10:CIB_DSP\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0501 N1_V01S0100\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 N3_V06S0103\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 H06W0303\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 V01N0101\narc: E1_H02E0301 W3_H06E0003\n\n.tile CIB_R13C11:CIB_DSP\narc: N1_V02N0101 V01N0101\narc: N1_V02N0401 W1_H02E0401\narc: S1_V02S0101 V01N0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0601 E1_H02W0601\narc: W1_H02W0301 V02N0301\narc: E1_H02E0101 W3_H06E0103\n\n.tile CIB_R13C12:CIB_DSP\narc: E1_H02E0701 V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 V01N0001\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 N1_V01S0100\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V01N0101\narc: W3_H06W0303 V06S0303\n\n.tile CIB_R13C13:CIB_DSP\narc: E1_H02E0501 V06N0303\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0101 H02W0101\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0501 N3_V06S0303\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0203\narc: W1_H02W0301 V01N0101\narc: W1_H02W0601 N3_V06S0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0203\n\n.tile CIB_R13C14:CIB_DSP\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0501 V01N0101\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 N3_V06S0103\narc: W3_H06W0003 V06S0003\n\n.tile CIB_R13C15:CIB_DSP\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 S3_V06N0203\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0301 S1_V02N0301\narc: S1_V02S0501 V01N0101\narc: S3_V06S0103 N1_V02S0201\narc: N1_V02N0601 W3_H06E0303\narc: W1_H02W0401 W3_H06E0203\n\n.tile CIB_R13C16:CIB_DSP\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 S3_V06N0103\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 H06W0303\narc: W1_H02W0201 N3_V06S0103\n\n.tile CIB_R13C17:CIB_DSP\narc: E1_H02E0201 S1_V02N0201\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0301 E1_H02W0301\narc: W1_H02W0001 N1_V01S0000\n\n.tile CIB_R13C18:CIB_DSP\narc: E1_H02E0101 V06S0103\narc: E1_H02E0601 V06S0303\narc: E3_H06E0103 V06N0103\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0101 H02W0101\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0601 V01N0001\narc: V01S0000 N3_V06S0103\narc: E3_H06E0003 W3_H06E0303\n\n.tile CIB_R13C19:CIB_DSP\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0701 V06S0203\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 S3_V06N0203\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 E1_H02W0701\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0501 N3_V06S0303\narc: N1_V02N0401 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\n\n.tile CIB_R13C1:CIB_LR_S\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0303 E3_H06W0303\n\n.tile CIB_R13C20:CIB_DSP\narc: E1_H02E0701 N3_V06S0203\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H02E0701\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0501 N1_V02S0501\n\n.tile CIB_R13C21:CIB_DSP\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S3_V06N0103\narc: S1_V02S0701 H02E0701\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: W1_H02W0701 N1_V02S0701\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\n\n.tile CIB_R13C22:CIB_DSP\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0601 V06S0303\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0201 S3_V06N0103\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 N1_V02S0101\narc: S1_V02S0001 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\n\n.tile CIB_R13C23:CIB_DSP\narc: E1_H02E0001 W1_H02E0501\narc: E3_H06E0303 W1_H02E0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02W0701\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0401 H02W0401\narc: S1_V02S0701 H06W0203\n\n.tile CIB_R13C24:CIB_DSP\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 V06S0203\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 V01N0001\narc: N1_V02N0601 V01N0001\narc: S1_V02S0001 H02E0001\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0501 H06W0303\narc: W1_H02W0401 V06S0203\narc: W1_H02W0701 N1_V01S0100\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\n\n.tile CIB_R13C25:CIB_DSP\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0203 S3_V06N0203\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0101 H06E0103\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0303 N1_V01S0100\narc: W1_H02W0001 S1_V02N0001\narc: E1_H01E0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\n\n.tile CIB_R13C26:CIB_DSP\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0601 V06S0303\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02E0601\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 V01N0101\narc: S3_V06S0203 N3_V06S0203\narc: W3_H06W0203 N3_V06S0203\n\n.tile CIB_R13C27:CIB_DSP\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H02E0601\narc: W1_H02W0501 V06S0303\narc: E1_H02E0501 W3_H06E0303\narc: W3_H06W0303 V06S0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\n\n.tile CIB_R13C28:CIB_DSP\narc: E1_H02E0601 V06S0303\narc: E3_H06E0103 V06S0103\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 S1_V02N0501\narc: W1_H02W0001 V02S0001\narc: E3_H06E0203 W3_H06E0203\n\n.tile CIB_R13C29:CIB_DSP\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 N1_V01S0100\narc: W1_H02W0401 E1_H02W0101\narc: E3_H06E0303 W3_H06E0303\n\n.tile CIB_R13C2:CIB_DSP\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 V06S0303\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 H02W0401\n\n.tile CIB_R13C30:CIB_DSP\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 S3_V06N0203\narc: W1_H02W0101 N3_V06S0103\narc: N1_V02N0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\n\n.tile CIB_R13C31:CIB_DSP\narc: E1_H02E0501 S1_V02N0501\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 S3_V06N0303\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 N3_V06S0103\narc: E1_H02E0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\n\n.tile CIB_R13C32:CIB_DSP\narc: E3_H06E0203 S3_V06N0203\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H02W0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: S3_V06S0103 N1_V02S0101\n\n.tile CIB_R13C33:CIB_DSP\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 V01N0001\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 H02W0001\narc: S1_V02S0401 N1_V02S0101\narc: W1_H02W0601 N1_V02S0601\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\n\n.tile CIB_R13C34:CIB_DSP\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0601 V01N0001\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 V01N0001\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V02S0701\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 V06S0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\n\n.tile CIB_R13C35:CIB_DSP\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 V01N0101\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0301 S1_V02N0301\narc: E3_H06E0003 W3_H06E0303\n\n.tile CIB_R13C36:CIB_DSP\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 S3_V06N0103\narc: E3_H06E0003 S3_V06N0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0601 H06W0303\narc: S3_V06S0203 N1_V01S0000\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 V01N0101\narc: W1_H02W0301 N1_V01S0100\narc: E1_H02E0401 W3_H06E0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\n\n.tile CIB_R13C37:CIB_DSP\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0203 S3_V06N0203\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0401 N1_V02S0101\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0501 V06N0303\narc: E1_H02E0101 W3_H06E0103\narc: W3_H06W0303 N3_V06S0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\n\n.tile CIB_R13C38:CIB_DSP\narc: E1_H02E0201 V02N0201\narc: E1_H02E0501 W1_H02E0401\narc: E3_H06E0103 N1_V01S0100\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 V01N0101\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 H06E0203\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 H02W0701\narc: S3_V06S0303 N1_V02S0501\narc: W1_H02W0301 S1_V02N0301\narc: E3_H06E0203 W3_H06E0203\n\n.tile CIB_R13C39:CIB_DSP\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 V01N0101\narc: E3_H06E0003 S3_V06N0003\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 V01N0101\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 H06E0103\narc: S1_V02S0701 S3_V06N0203\narc: W1_H02W0701 V02N0701\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: S1_V02S0401 W3_H06E0203\narc: W3_H06W0303 N1_V01S0100\narc: E3_H06E0103 W3_H06E0003\n\n.tile CIB_R13C3:CIB_DSP\narc: N1_V02N0001 H06W0003\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H02E0601\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 V06S0203\n\n.tile CIB_R13C40:CIB_DSP\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0701 S3_V06N0203\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0303 V06S0303\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 E1_H01W0000\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 H02E0301\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\n\n.tile CIB_R13C41:CIB_DSP\narc: E1_H02E0201 S1_V02N0201\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 H06E0103\narc: S1_V02S0501 W1_H02E0501\narc: H01W0000 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\n\n.tile CIB_R13C42:CIB_DSP\narc: E1_H02E0101 V02N0101\narc: E1_H02E0501 S1_V02N0501\narc: E3_H06E0203 W1_H02E0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0501 V01N0101\narc: S3_V06S0103 N1_V02S0201\narc: V01S0100 S3_V06N0303\narc: N1_V02N0601 W3_H06E0303\n\n.tile CIB_R13C43:CIB_DSP\narc: E1_H02E0001 V02N0001\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 S3_V06N0203\narc: E3_H06E0203 S3_V06N0203\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 V01N0001\narc: S3_V06S0203 N1_V02S0701\narc: W1_H02W0601 N1_V01S0000\narc: E1_H01E0101 W3_H06E0203\narc: N3_V06N0103 W3_H06E0103\narc: N3_V06N0303 W3_H06E0303\narc: W3_H06W0003 N1_V01S0000\narc: W3_H06W0303 V06S0303\narc: E3_H06E0103 W3_H06E0003\n\n.tile CIB_R13C44:CIB_DSP\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0701 S3_V06N0203\narc: E3_H06E0303 W1_H02E0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H06W0203\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0601 V01N0001\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: E1_H02E0401 W3_H06E0203\n\n.tile CIB_R13C45:CIB_DSP\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0003 V06N0003\narc: E3_H06E0203 W1_H02E0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 H06W0103\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 H02W0501\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0303 E1_H01W0100\narc: W1_H02W0001 V06S0003\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0301 W3_H06E0003\narc: W3_H06W0003 E1_H02W0301\narc: E3_H06E0103 W3_H06E0103\n\n.tile CIB_R13C46:CIB_DSP\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 V02N0701\narc: E3_H06E0203 W1_H02E0701\narc: E3_H06E0303 JQ6\narc: H01W0000 JQ7\narc: H01W0100 JQ4\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 V01N0001\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 JQ5\narc: W1_H02W0101 V01N0101\narc: W1_H02W0501 N1_V01S0100\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: W3_H06W0003 E1_H02W0301\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\n\n.tile CIB_R13C47:CIB_DSP\narc: E1_H01E0101 JQ7\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V06N0203\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 JQ4\narc: E3_H06E0303 W1_H02E0501\narc: H01W0000 JQ1\narc: H01W0100 JQ3\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 JQ6\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 JQ0\narc: S3_V06S0103 JQ2\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 E1_H01W0100\narc: V01S0000 JQ5\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 H01E0001\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0501 W3_H06E0303\narc: W3_H06W0103 N1_V01S0100\narc: W3_H06W0203 V06N0203\narc: E3_H06E0003 W3_H06E0003\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JA0MUX 0\nenum: CIB.JC3MUX 0\nenum: CIB.JA2MUX 0\n\n.tile CIB_R13C48:CIB_DSP\narc: E1_H01E0001 JQ2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V06N0303\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0103 V01N0101\narc: E3_H06E0203 V01N0001\narc: H00L0100 H02E0301\narc: H00R0100 S1_V02N0501\narc: H01W0000 JQ1\narc: H01W0100 JQ0\narc: JB6 V00T0000\narc: JB7 V02N0701\narc: JD6 H00L0100\narc: JD7 H00R0100\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 H02E0601\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 JQ3\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0401 JQ6\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 JQ7\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 JQ5\narc: V00T0000 V02S0601\narc: V01S0000 JQ4\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0701 E1_H02W0701\narc: E1_H01E0101 W3_H06E0203\narc: W3_H06W0103 N1_V01S0100\narc: E3_H06E0303 W3_H06E0203\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JC1MUX 0\n\n.tile CIB_R13C49:CIB_DSP\narc: E1_H01E0001 JQ7\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V06N0103\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 H01E0101\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 V02N0001\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02N0701\narc: H01W0000 JQ6\narc: JB0 V02N0301\narc: JB1 H02W0101\narc: JB2 S1_V02N0301\narc: JB3 H02E0301\narc: JB4 H02E0101\narc: JB5 H00L0000\narc: JB6 H02W0301\narc: JB7 V00B0100\narc: JD0 S1_V02N0001\narc: JD1 V02N0201\narc: JD2 H00R0000\narc: JD3 V00T0100\narc: JD4 W1_H02E0201\narc: JD5 H02W0001\narc: JD6 V02N0401\narc: JD7 H00R0100\narc: JLSR1 V00B0000\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 V01N0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 JQ2\narc: S1_V02S0301 JQ3\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 H01E0001\narc: S3_V06S0003 JQ0\narc: S3_V06S0103 JQ1\narc: S3_V06S0203 JQ4\narc: S3_V06S0303 JQ5\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02E0501\narc: V00T0100 V02N0501\narc: E1_H01E0101 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\n\n.tile CIB_R13C4:CIB_DSP\narc: E1_H02E0701 S3_V06N0203\narc: E3_H06E0003 V06S0003\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0301 N1_V01S0100\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 N3_V06S0203\narc: W1_H02W0701 N3_V06S0203\n\n.tile CIB_R13C50:CIB_DSP\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V02S0401\narc: E3_H06E0203 W1_H02E0401\narc: E3_H06E0303 V06N0303\narc: H00L0100 H02W0101\narc: H00R0000 S1_V02N0601\narc: H00R0100 V02N0701\narc: JB0 S1_V02N0101\narc: JB1 V02S0301\narc: JB2 H01W0100\narc: JB3 V02N0301\narc: JB4 V02N0501\narc: JB5 H02E0101\narc: JB6 H02W0101\narc: JB7 V02N0701\narc: JCE3 E1_H02W0101\narc: JD0 S1_V02N0201\narc: JD1 H00R0000\narc: JD2 H01E0101\narc: JD3 V00B0100\narc: JD4 H02W0001\narc: JD5 H02E0201\narc: JD6 H00R0100\narc: JD7 H00L0100\narc: JLSR0 H02W0501\narc: JLSR1 V00B0000\narc: N1_V01N0001 JQ1\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 JQ0\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 H06W0303\narc: V00B0000 H02E0601\narc: V00B0100 H02W0701\narc: V01S0000 JQ2\narc: V01S0100 JQ3\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0501 W3_H06E0303\narc: H01W0100 W3_H06E0303\nenum: CIB.JA7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA3MUX 0\n\n.tile CIB_R13C51:CIB_DSP\narc: E1_H01E0001 JQ5\narc: E1_H01E0101 JF3\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 JQ6\narc: E3_H06E0103 JQ2\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02N0601\narc: H00R0100 S1_V02N0701\narc: H01W0000 JF0\narc: H01W0100 JQ4\narc: JB0 H02W0301\narc: JB1 V00T0000\narc: JB2 H00R0100\narc: JB3 N1_V02S0101\narc: JB4 V00B0100\narc: JB5 V02N0701\narc: JB6 W1_H02E0301\narc: JB7 E1_H02W0301\narc: JCE0 H00R0000\narc: JD0 V02N0001\narc: JD1 V00T0100\narc: JD2 H02W0201\narc: JD3 S1_V02N0001\narc: JD4 V02N0401\narc: JD5 V01N0001\narc: JD6 E1_H02W0001\narc: JD7 H00L0100\narc: JLSR0 E1_H02W0501\narc: JLSR1 E1_H02W0501\narc: N1_V01N0001 JF6\narc: N1_V01N0101 JF7\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0201\narc: S1_V02S0001 JQ0\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 JF2\narc: S1_V02S0301 JQ1\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 JF5\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 H06W0203\narc: S3_V06S0003 JQ3\narc: S3_V06S0103 JF1\narc: S3_V06S0203 JF4\narc: S3_V06S0303 E1_H01W0100\narc: V00B0100 S1_V02N0101\narc: V00T0000 W1_H02E0001\narc: V00T0100 H02E0301\narc: V01S0000 JQ7\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 V02N0101\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 S3_V06N0203\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0201 W3_H06E0103\narc: W1_H02W0001 W3_H06E0003\narc: W3_H06W0003 N3_V06S0003\narc: W3_H06W0103 N3_V06S0103\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JA0MUX 0\nenum: CIB.JC3MUX 0\nenum: CIB.JA2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA3MUX 0\n\n.tile CIB_R13C52:CIB_DSP\narc: E1_H01E0001 JQ5\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0701 V06N0203\narc: E3_H06E0103 JQ2\narc: E3_H06E0203 JQ7\narc: E3_H06E0303 JQ6\narc: H00L0100 N1_V02S0101\narc: H00R0000 W1_H02E0401\narc: H00R0100 V02N0501\narc: H01W0100 JF3\narc: JB0 H00R0100\narc: JB1 V02N0301\narc: JB2 S1_V02N0101\narc: JB3 N1_V02S0301\narc: JB4 V00B0100\narc: JB5 N1_V02S0701\narc: JB6 V00T0000\narc: JB7 H02W0101\narc: JD0 S1_V02N0201\narc: JD1 V00T0100\narc: JD2 W1_H02E0201\narc: JD3 H00R0000\narc: JD4 V00B0000\narc: JD5 S1_V02N0601\narc: JD6 H00L0100\narc: JD7 V01N0001\narc: JLSR1 H02W0501\narc: N1_V01N0001 JF4\narc: N1_V01N0101 JQ0\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H02W0601\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 JF2\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 JF0\narc: S1_V02S0301 JQ3\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 JF7\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 JF5\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 JF1\narc: S3_V06S0203 JQ4\narc: S3_V06S0303 H01E0101\narc: V00B0000 V02N0201\narc: V00B0100 H02E0501\narc: V00T0000 H02W0201\narc: V00T0100 S1_V02N0501\narc: V01S0000 JF6\narc: V01S0100 JQ1\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 V06N0303\narc: E1_H02E0101 W3_H06E0103\narc: H01W0000 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA3MUX 0\n\n.tile CIB_R13C53:CIB_DSP\narc: E1_H01E0001 JQ0\narc: E1_H01E0101 JQ4\narc: E1_H02E0101 V06N0103\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 JQ6\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 S3_V06N0303\narc: E3_H06E0203 JQ7\narc: H00L0000 H02W0001\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02E0701\narc: H01W0000 JF3\narc: JB2 H00L0000\narc: JB3 H01W0100\narc: JB4 W1_H02E0101\narc: JB5 N1_V02S0701\narc: JB6 V00B0000\narc: JB7 W1_H02E0301\narc: JD2 W1_H02E0001\narc: JD3 H00R0000\narc: JD4 N1_V02S0401\narc: JD5 H00R0100\narc: JD6 W1_H02E0201\narc: JD7 V02N0601\narc: JLSR0 V00B0100\narc: JLSR1 V00B0100\narc: N1_V01N0001 JF7\narc: N1_V01N0101 JQ2\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H02W0601\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 JF1\narc: S1_V02S0201 JF2\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 JF5\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 JQ3\narc: S3_V06S0103 JQ1\narc: S3_V06S0203 JF4\narc: S3_V06S0303 JF6\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02S0301\narc: V01S0000 N3_V06S0103\narc: V01S0100 JF0\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0001 W3_H06E0003\narc: H01W0100 W3_H06E0303\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0303 JQ5\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\n\n.tile CIB_R13C54:CIB_DSP\narc: E1_H01E0101 JF6\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 JQ5\narc: E1_H02E0701 S3_V06N0203\narc: E3_H06E0103 JQ1\narc: E3_H06E0203 JQ7\narc: E3_H06E0303 JQ6\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02W0401\narc: H00R0100 E1_H02W0501\narc: H01W0100 JF2\narc: JB0 V02S0101\narc: JB1 H02E0301\narc: JB2 H00R0100\narc: JB3 W1_H02E0301\narc: JB4 S1_V02N0501\narc: JB5 N1_V02S0501\narc: JB6 V00T0000\narc: JB7 H02W0101\narc: JD0 H02E0201\narc: JD1 N1_V02S0001\narc: JD2 H00R0000\narc: JD3 V00B0100\narc: JD4 W1_H02E0201\narc: JD5 V00B0000\narc: JD6 H02W0201\narc: JD7 H00L0100\narc: N1_V01N0001 JQ2\narc: N1_V01N0101 JQ0\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0101 JQ3\narc: S1_V02S0201 H01E0001\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 JF7\narc: S3_V06S0003 JF0\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 JF5\narc: V00B0000 H02E0601\narc: V00B0100 H02W0701\narc: V00T0000 W1_H02E0001\narc: V01S0000 JQ4\narc: V01S0100 JF3\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0301 V01N0101\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 N1_V02S0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0401 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: W3_H06W0103 JF1\narc: W3_H06W0203 JF4\narc: E3_H06E0003 W3_H06E0303\nenum: CIB.JA7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA3MUX 0\n\n.tile CIB_R13C55:CIB_DSP\narc: E1_H01E0001 JF4\narc: E1_H01E0101 JF6\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 S3_V06N0003\narc: E3_H06E0103 JQ1\narc: E3_H06E0203 W1_H02E0401\narc: H00L0000 H02E0001\narc: H00R0100 V02N0701\narc: H01W0000 JF7\narc: H01W0100 E3_H06W0303\narc: JB0 H00R0100\narc: JB1 V02N0101\narc: JB2 V02S0101\narc: JB4 H02E0301\narc: JB5 H00L0000\narc: JB6 S1_V02N0501\narc: JB7 W1_H02E0101\narc: JCE0 H02E0101\narc: JCE1 H02E0101\narc: JCE2 H02E0101\narc: JCE3 H02E0101\narc: JD0 V02S0001\narc: JD1 V02S0201\narc: JD3 V00B0100\narc: JD4 W1_H02E0001\narc: JD5 V02N0601\narc: JD6 H02W0201\narc: JD7 H02E0201\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 JF5\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 H01E0101\narc: V00B0100 V02S0101\narc: V01S0000 JQ0\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 V02S0401\narc: W1_H02W0701 N1_V02S0701\narc: W1_H02W0601 W3_H06E0303\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R13C56:CIB_DSP\narc: E1_H01E0001 JF3\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 N1_V02S0301\narc: H00L0000 H02W0201\narc: H00L0100 H02E0301\narc: H00R0000 W1_H02E0401\narc: H01W0000 JF4\narc: JB0 V00T0000\narc: JB1 V00B0000\narc: JB2 E1_H02W0301\narc: JB3 H02E0101\narc: JB4 H00L0000\narc: JB5 S1_V02N0501\narc: JB6 E1_H02W0101\narc: JB7 V00B0100\narc: JD0 V02S0001\narc: JD1 H00R0000\narc: JD2 V02N0001\narc: JD3 S1_V02N0201\narc: JD4 H02E0201\narc: JD5 N1_V02S0401\narc: JD6 H00L0100\narc: JD7 V02S0401\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 JF7\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 V01N0001\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 JF5\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 H06E0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 S1_V02N0401\narc: V01S0000 JF2\narc: V01S0100 JF6\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 JF1\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 S1_V02N0601\narc: E1_H01E0101 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: W3_H06W0003 JF0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA3MUX 0\n\n.tile CIB_R13C57:CIB_DSP\narc: E1_H01E0001 JF6\narc: E1_H02E0001 V01N0001\narc: H00L0000 S1_V02N0001\narc: H01W0000 JF2\narc: JB0 V00T0000\narc: JB1 H02E0301\narc: JB2 H02E0101\narc: JB3 S1_V02N0301\narc: JB5 H00L0000\narc: JD0 W1_H02E0001\narc: JD1 E1_H02W0201\narc: JD2 V00T0100\narc: JD3 V02N0201\narc: JD4 V00B0000\narc: JLSR0 H02W0501\narc: JLSR1 H02W0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 H01E0101\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 JF4\narc: S1_V02S0701 JF5\narc: S3_V06S0003 JF3\narc: S3_V06S0103 JF1\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 H06E0303\narc: V00B0000 S1_V02N0001\narc: V00T0000 V02N0601\narc: V00T0100 S1_V02N0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 JF0\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 JF7\narc: W1_H02W0601 V06N0303\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA3MUX 0\n\n.tile CIB_R13C58:CIB_DSP\narc: E1_H01E0001 JF2\narc: E1_H01E0101 JF0\narc: H01W0000 JF4\narc: H01W0100 JF7\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 S1_V02N0401\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0401 H06E0203\narc: S1_V02S0701 JF5\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 E1_H01W0100\narc: V01S0100 JF3\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 JF6\narc: W1_H02W0701 S3_V06N0203\narc: S1_V02S0601 W3_H06E0303\narc: W3_H06W0103 JF1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\n\n.tile CIB_R13C59:CIB_DSP\narc: H01W0000 JF3\narc: H01W0100 JF2\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0301 N3_V06S0003\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 JF4\narc: S3_V06S0303 JF5\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 JF1\narc: W3_H06W0003 JF0\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0303 E3_H06W0203\n\n.tile CIB_R13C5:CIB_DSP\narc: E3_H06E0103 V06S0103\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 H02W0101\narc: S1_V02S0001 H02W0001\narc: S1_V02S0501 V01N0101\n\n.tile CIB_R13C60:CIB_DSP\narc: N1_V02N0001 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: W1_H02W0501 S3_V06N0303\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\n\n.tile CIB_R13C61:CIB_DSP\narc: W3_H06W0303 E3_H06W0203\n\n.tile CIB_R13C65:CIB_DSP\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\n\n.tile CIB_R13C67:CIB_DSP\narc: W3_H06W0203 S3_V06N0203\n\n.tile CIB_R13C69:CIB_DSP\narc: E1_H02E0601 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V01S0100 N3_V06S0303\n\n.tile CIB_R13C6:CIB_DSP\narc: E1_H02E0701 V02S0701\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0303\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0701 V06S0203\narc: W3_H06W0003 E3_H06W0303\n\n.tile CIB_R13C70:CIB_DSP\narc: E1_H02E0301 V02S0301\narc: S1_V02S0301 N3_V06S0003\n\n.tile CIB_R13C71:CIB_LR_S\narc: H00R0000 W1_H02E0601\narc: JA0 V02S0501\narc: JA3 N1_V02S0501\narc: JB0 V00B0000\narc: JB3 H00R0000\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 H02E0301\narc: JLSR1 H02E0301\narc: N3_V06N0203 JF4\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 W1_H02E0601\narc: S1_V02S0501 W3_H06E0303\narc: W3_H06W0203 JQ4\n\n.tile CIB_R13C7:CIB_DSP\narc: E1_H02E0501 V06S0303\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 H02W0701\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: W3_H06W0003 V06S0003\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\n\n.tile CIB_R13C8:CIB_DSP\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0701 H02W0701\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0303 V06S0303\n\n.tile CIB_R13C9:CIB_DSP\narc: E1_H02E0401 V01N0001\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0301 H02W0301\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 N3_V06S0303\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V01N0101\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 V02N0701\n\n.tile CIB_R14C71:CIB_LR\narc: H00L0100 H02E0301\narc: JA0 H00L0100\narc: JA3 V02S0501\narc: JB0 W1_H02E0301\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 H02E0501\narc: JLSR1 H02E0501\narc: N3_V06N0203 JF4\narc: S3_V06S0003 N3_V06S0003\nenum: CIB.JB3MUX 0\n\n.tile CIB_R15C1:CIB_LR\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 N1_V02S0701\n\n.tile CIB_R15C71:CIB_LR\narc: S3_V06S0003 N3_V06S0303\n\n.tile CIB_R16C1:CIB_LR\narc: E1_H02E0601 E3_H06W0303\narc: N1_V02N0601 N3_V06S0303\narc: S3_V06S0003 N3_V06S0003\n\n.tile CIB_R16C71:CIB_LR\narc: S3_V06S0203 N3_V06S0103\n\n.tile CIB_R17C1:CIB_LR\narc: E1_H02E0301 E3_H06W0003\narc: S3_V06S0003 H06W0003\n\n.tile CIB_R17C71:CIB_LR\narc: JA0 W1_H02E0701\narc: S1_V02S0501 H02E0501\narc: S3_V06S0203 N3_V06S0103\nenum: CIB.JB0MUX 0\n\n.tile CIB_R18C1:CIB_LR\narc: S3_V06S0003 N3_V06S0003\n\n.tile CIB_R18C71:CIB_LR\narc: S3_V06S0203 N3_V06S0103\narc: S1_V02S0201 W3_H06E0103\n\n.tile CIB_R19C1:CIB_LR\narc: E1_H02E0301 V06S0003\narc: S3_V06S0003 N3_V06S0303\n\n.tile CIB_R19C71:CIB_LR\narc: JA3 N1_V02S0501\narc: S3_V06S0203 N3_V06S0103\nenum: CIB.JB3MUX 0\n\n.tile CIB_R1C15:CIB\narc: E3_H06E0003 V06N0003\narc: E3_H06E0203 V06N0203\n\n.tile CIB_R1C17:CIB\narc: S1_V02S0201 V01N0001\n\n.tile CIB_R1C19:CIB\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 S3_V06N0003\narc: V01S0000 S3_V06N0103\n\n.tile CIB_R1C21:CIB\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\n\n.tile CIB_R1C23:CIB\narc: S1_V02S0301 H06W0003\n\n.tile CIB_R1C24:CIB\narc: S1_V02S0001 H02W0001\n\n.tile CIB_R1C25:CIB\narc: V01S0000 S3_V06N0103\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S3_V06N0003\n\n.tile CIB_R1C26:CIB\narc: W3_H06W0003 S3_V06N0003\n\n.tile CIB_R1C27:CIB\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\n\n.tile CIB_R1C28:CIB\narc: E1_H02E0301 S3_V06N0003\narc: E3_H06E0103 V06N0103\narc: E3_H06E0203 S3_V06N0203\n\n.tile CIB_R1C29:CIB\narc: E3_H06E0003 V06N0003\narc: E3_H06E0103 S3_V06N0103\n\n.tile CIB_R1C30:CIB\narc: E1_H02E0201 E3_H06W0103\narc: E3_H06E0003 W1_H02E0301\n\n.tile CIB_R1C31:CIB\narc: S1_V02S0201 H02E0201\n\n.tile CIB_R1C33:CIB\narc: S1_V02S0701 S3_V06N0203\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\n\n.tile CIB_R1C34:CIB\narc: S1_V02S0601 H02W0601\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\n\n.tile CIB_R1C35:CIB\narc: E1_H02E0601 V06N0303\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0601 S3_V06N0303\narc: V01S0100 S3_V06N0303\narc: W1_H02W0601 S3_V06N0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\n\n.tile CIB_R1C36:CIB\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0601 H02E0601\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\n\n.tile CIB_R1C37:CIB\narc: E1_H02E0201 S1_V02N0201\n\n.tile CIB_R1C38:CIB\narc: H00L0000 H02E0201\narc: JA0 H00L0000\narc: S1_V02S0101 V01N0101\narc: S1_V02S0601 H02W0601\nenum: CIB.JB0MUX 0\n\n.tile CIB_R1C39:CIB\narc: W1_H02W0601 S3_V06N0303\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\n\n.tile CIB_R1C40:CIB\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\n\n.tile CIB_R1C41:CIB\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\n\n.tile CIB_R1C42:CIB\narc: W3_H06W0003 JQ0\narc: E3_H06E0003 W3_H06E0003\n\n.tile CIB_R1C44:CIB\narc: E3_H06E0103 V06N0103\n\n.tile CIB_R1C45:CIB\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\n\n.tile CIB_R1C46:CIB\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\n\n.tile CIB_R1C47:CIB\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\n\n.tile CIB_R1C48:CIB\narc: E3_H06E0003 W3_H06E0003\n\n.tile CIB_R1C49:CIB\narc: JA0 H02W0501\nenum: CIB.JB0MUX 0\n\n.tile CIB_R1C4:CIB\narc: S1_V02S0101 V01N0101\n\n.tile CIB_R1C50:CIB\narc: W1_H02W0501 V02N0501\narc: E3_H06E0103 W3_H06E0103\n\n.tile CIB_R1C51:CIB\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\n\n.tile CIB_R1C52:CIB\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\n\n.tile CIB_R1C53:CIB\narc: E1_H02E0701 W1_H02E0601\narc: H00L0100 W1_H02E0301\narc: JA0 H00L0100\narc: E1_H02E0301 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\nenum: CIB.JB0MUX 0\n\n.tile CIB_R1C54:CIB\narc: JA0 H02E0701\narc: E3_H06E0103 W3_H06E0003\nenum: CIB.JB0MUX 0\n\n.tile CIB_R1C55:CIB\narc: E1_H02E0601 W1_H02E0301\n\n.tile CIB_R1C56:CIB\narc: H00R0000 H02E0601\narc: JA0 H00R0000\narc: JCLK0 G_HPBX0000\narc: JLSR0 V00B0100\narc: V00B0100 E1_H02W0701\narc: E3_H06E0103 W3_H06E0103\nenum: CIB.JB0MUX 0\n\n.tile CIB_R1C58:CIB\narc: E1_H02E0401 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\n\n.tile CIB_R1C59:CIB\narc: E1_H02E0701 W3_H06E0203\n\n.tile CIB_R1C60:CIB\narc: JA0 H02E0701\narc: JCLK0 G_HPBX0000\narc: JLSR0 V00B0000\narc: V00B0000 W1_H02E0401\narc: E3_H06E0203 W3_H06E0103\nenum: CIB.JB0MUX 0\n\n.tile CIB_R1C62:CIB\narc: E3_H06E0203 W3_H06E0103\n\n.tile CIB_R1C64:CIB\narc: E1_H02E0501 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\n\n.tile CIB_R1C65:CIB\narc: JA0 H02W0701\narc: JCLK0 G_HPBX0000\narc: JLSR0 H02E0501\nenum: CIB.JB0MUX 0\n\n.tile CIB_R1C66:CIB\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0701 V02N0701\narc: JA0 E1_H02W0701\narc: JCLK0 G_HPBX0000\narc: JLSR0 W1_H02E0501\narc: W1_H02W0701 W3_H06E0203\nenum: CIB.JB0MUX 0\n\n.tile CIB_R1C67:CIB\narc: H00L0000 V02N0201\narc: JA0 H00L0000\narc: JCLK0 G_HPBX0000\narc: JLSR0 H02E0501\nenum: CIB.JB0MUX 0\n\n.tile CIB_R1C68:CIB\narc: JA0 W1_H02E0701\narc: JCLK0 G_HPBX0000\narc: JLSR0 W1_H02E0501\narc: W1_H02W0701 W3_H06E0203\nenum: CIB.JB0MUX 0\n\n.tile CIB_R1C70:CIB\narc: S1_V02S0701 W3_H06E0203\n\n.tile CIB_R1C7:CIB\narc: S1_V02S0301 S3_V06N0003\narc: V01S0000 S3_V06N0103\n\n.tile CIB_R20C71:CIB_LR\narc: JA0 S1_V02N0701\narc: JA3 V00B0000\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 W1_H02E0301\narc: JLSR1 W1_H02E0301\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 N1_V02S0201\narc: W3_H06W0203 S3_V06N0203\nenum: CIB.JB3MUX 0\nenum: CIB.JB0MUX 0\n\n.tile CIB_R21C1:CIB_LR\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 V01N0001\n\n.tile CIB_R21C71:CIB_LR\narc: S3_V06S0103 N3_V06S0003\n\n.tile CIB_R22C1:CIB_LR\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0201 V01N0001\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 V01N0001\narc: E1_H02E0701 E3_H06W0203\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 S3_V06N0203\n\n.tile CIB_R22C71:CIB_LR\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0301 H02E0301\narc: W3_H06W0203 S3_V06N0203\n\n.tile CIB_R23C1:CIB_LR\narc: N1_V01N0001 N3_V06S0003\n\n.tile CIB_R23C71:CIB_LR\narc: H00L0100 V02S0301\narc: JA0 H00L0100\narc: JA3 V00T0000\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 H02E0301\narc: JLSR1 H02E0301\narc: S1_V02S0701 H02E0701\narc: S3_V06S0203 N3_V06S0203\narc: V00T0000 H02E0201\nenum: CIB.JB3MUX 0\nenum: CIB.JB0MUX 0\n\n.tile CIB_R24C1:CIB_LR\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0401 S1_V02N0401\narc: N1_V02N0401 S1_V02N0101\narc: S3_V06S0003 N3_V06S0003\n\n.tile CIB_R24C71:CIB_LR\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0501 H06E0303\narc: S3_V06S0203 N3_V06S0203\n\n.tile CIB_R25C10:CIB_EBR\narc: E1_H01E0001 JF7\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 V02S0701\narc: H01W0000 JF6\narc: JB6 H02E0301\narc: JB7 V00B0100\narc: JD6 V00B0000\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 V01N0101\narc: N3_V06N0203 JQ7\narc: S1_V02S0001 V01N0001\narc: S1_V02S0701 H02W0701\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02N0101\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E1_H01W0100\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 JQ7\narc: W3_H06W0303 JQ6\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD7MUX 0\n\n.tile CIB_R25C11:CIB_EBR\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 V06S0003\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 V06S0203\narc: H00L0000 H02E0001\narc: H00R0000 V02S0401\narc: H00R0100 W1_H02E0501\narc: H01W0000 JQ0\narc: H01W0100 JF2\narc: JA0 V02N0701\narc: JA1 H02E0701\narc: JA2 H02W0701\narc: JA3 N1_V02S0701\narc: JA5 V02S0101\narc: JB0 V00T0000\narc: JB1 S1_V02N0101\narc: JB3 W1_H02E0101\narc: JB5 H00R0000\narc: JB7 V00B0000\narc: JC2 N1_V01S0100\narc: JC3 H00L0000\narc: JC4 V00B0100\narc: JC6 V00B0100\narc: JCLK0 G_HPBX0000\narc: JD0 V01S0100\narc: JD1 E1_H02W0201\narc: JD2 V02N0001\narc: JD4 H00R0100\narc: JD6 W1_H02E0001\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H06W0103\narc: N1_V02N0401 H01E0001\narc: N1_V02N0701 JF7\narc: N3_V06N0003 JF0\narc: N3_V06N0203 JF4\narc: N3_V06N0303 JF5\narc: S3_V06S0003 JF3\narc: V00B0000 W1_H02E0401\narc: V00B0100 V02S0101\narc: V00T0000 H02W0201\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 JF1\narc: W1_H02W0701 V02S0701\narc: W3_H06W0003 JF0\narc: W3_H06W0103 JQ1\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 JF6\nenum: CIB.JCE0MUX 1\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC1MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C12:CIB_EBR\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0501 V06S0303\narc: H00R0000 H02E0401\narc: H00R0100 V02S0701\narc: H01W0000 JF1\narc: JA4 V00T0000\narc: JA5 H02E0501\narc: JA6 V00T0100\narc: JA7 H00R0000\narc: JB1 V00B0000\narc: JB3 N1_V02S0301\narc: JB5 S1_V02N0701\narc: JB7 H02E0301\narc: JC4 V02S0001\narc: JC5 S1_V02N0201\narc: JC6 H02E0601\narc: JC7 E1_H02W0601\narc: JCE1 W1_H02E0101\narc: JCLK0 G_HPBX0000\narc: JD0 W1_H02E0201\narc: JD2 E1_H02W0201\narc: JD4 N1_V02S0601\narc: JD6 H00R0100\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0003 JF0\narc: N3_V06N0203 JF7\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 W1_H02E0601\narc: V00B0000 W1_H02E0401\narc: V00T0000 S1_V02N0401\narc: V00T0100 V02S0501\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0501 JF5\narc: W1_H02W0701 H01E0101\narc: W3_H06W0003 JF3\narc: W3_H06W0103 JF2\narc: W3_H06W0203 JF4\narc: W3_H06W0303 JF6\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JA0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\n\n.tile CIB_R25C13:CIB_EBR\narc: E1_H01E0001 JF2\narc: E1_H01E0101 JF4\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0103 JQ2\narc: H00L0100 S1_V02N0301\narc: H00R0100 V02S0701\narc: H01W0000 JF1\narc: H01W0100 JF0\narc: JA0 V02N0701\narc: JA1 V02N0701\narc: JA2 E1_H02W0701\narc: JA3 E1_H02W0701\narc: JA5 V02N0301\narc: JB1 E1_H02W0301\narc: JB3 H00R0100\narc: JB4 H02W0301\narc: JB5 N1_V02S0701\narc: JB7 V02N0501\narc: JC2 H00L0100\narc: JC3 H00L0100\narc: JC4 V00B0100\narc: JC6 V00B0100\narc: JCLK0 G_HPBX0000\narc: JD0 E1_H02W0201\narc: JD1 V02S0201\narc: JD2 S1_V02N0001\narc: JD4 W1_H02E0201\narc: JD6 W1_H02E0001\narc: N1_V01N0001 JF6\narc: N1_V01N0101 JQ3\narc: N1_V02N0001 JQ0\narc: N1_V02N0101 JQ1\narc: N1_V02N0201 JF0\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 JF6\narc: N1_V02N0501 JF5\narc: N1_V02N0601 JQ4\narc: N1_V02N0701 JF7\narc: N3_V06N0003 JF3\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 JQ5\narc: S1_V02S0501 JF5\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 N3_V06S0303\narc: V00B0100 V02N0301\narc: V01S0000 JF7\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 V06N0103\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0501 E1_H02W0401\nenum: CIB.JCE0MUX 1\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C14:CIB_EBR\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 N1_V02S0701\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02S0101\narc: H00R0000 N1_V02S0601\narc: H00R0100 W1_H02E0501\narc: H01W0100 JF4\narc: JA0 H00L0100\narc: JA1 H00R0000\narc: JA4 V00T0100\narc: JA5 V02S0101\narc: JA6 H00R0000\narc: JA7 V00T0100\narc: JB1 V02N0101\narc: JB3 H00R0100\narc: JB5 V02N0701\narc: JB7 H02E0301\narc: JC0 H00L0000\narc: JC1 H02E0601\narc: JC4 H02E0601\narc: JC5 V00B0100\narc: JC6 V00B0100\narc: JC7 N1_V02S0201\narc: JCLK0 G_HPBX0000\narc: JD0 W1_H02E0001\narc: JD2 W1_H02E0201\narc: JD4 V02N0601\narc: JD6 V02N0401\narc: N1_V01N0001 JF5\narc: N1_V02N0001 JF0\narc: N1_V02N0101 JF3\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 JF1\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 JF6\narc: N1_V02N0701 H01E0101\narc: N3_V06N0103 JF2\narc: N3_V06N0203 JF7\narc: N3_V06N0303 JF5\narc: S3_V06S0103 N1_V02S0101\narc: V00B0100 V02S0301\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 JF2\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0103 N3_V06S0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R25C15:CIB_EBR\narc: E1_H02E0401 V06S0203\narc: E3_H06E0003 JQ3\narc: E3_H06E0203 JQ7\narc: E3_H06E0303 JQ5\narc: H00L0000 H02W0201\narc: H00R0100 H02W0701\narc: JA0 H00L0000\narc: JA2 V02N0701\narc: JA6 V00T0100\narc: JB1 V00B0000\narc: JC1 H00R0100\narc: JC3 H02W0401\narc: JD0 W1_H02E0201\narc: N1_V02N0201 JF0\narc: N1_V02N0301 JF1\narc: N1_V02N0401 N1_V01S0000\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 JQ2\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ6\narc: S1_V02S0001 H02W0001\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 V01N0001\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 W1_H02E0401\narc: V00T0100 H02W0301\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V02N0701\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C16:CIB_EBR\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0103 JQ2\narc: H00R0100 S1_V02N0701\narc: JA0 H02W0501\narc: JA4 V02S0101\narc: JA6 W1_H02E0501\narc: JC1 H02W0401\narc: JC5 V00B0100\narc: JC7 H02E0401\narc: JCE1 H00R0100\narc: JCLK0 G_HPBX0000\narc: N1_V02N0101 H06E0103\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 JQ1\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: V00B0100 W1_H02E0701\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 V06S0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\n\n.tile CIB_R25C17:CIB_EBR\narc: E1_H02E0101 V02S0101\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0203 N3_V06S0203\narc: E3_H06E0303 JQ6\narc: N1_V01N0001 JQ7\narc: N1_V01N0101 JQ5\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 V01N0101\narc: N1_V02N0601 H02E0601\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0201 H02E0201\narc: S1_V02S0701 N1_V02S0701\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 N1_V02S0501\narc: W3_H06W0203 E3_H06W0203\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCLK1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JCE0MUX 1\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R25C18:CIB_EBR\narc: E1_H02E0001 V02S0001\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 V01N0001\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 JQ0\narc: E3_H06E0103 JQ2\narc: E3_H06E0203 JQ4\narc: JA0 H02E0701\narc: JA2 V00B0000\narc: JA6 S1_V02N0301\narc: JC1 W1_H02E0401\narc: JC3 S1_V02N0401\narc: N1_V01N0001 JQ1\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 JQ3\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 V02N0001\narc: W3_H06W0103 E3_H06W0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C19:CIB_EBR\narc: E1_H02E0001 V02N0001\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0203 JQ7\narc: H00L0100 H02W0301\narc: H00R0000 H02E0401\narc: JA0 H02E0701\narc: JA1 H00R0000\narc: JA2 V00T0000\narc: JA3 H00L0100\narc: JA4 V00T0100\narc: JA5 W1_H02E0501\narc: JCE1 W1_H02E0101\narc: JCLK0 G_HPBX0000\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0501 H02E0501\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 JQ6\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0401 H02W0401\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0303\narc: V00T0000 H02E0001\narc: V00T0100 H02W0101\nenum: CIB.JB5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC3MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JB7MUX 0\n\n.tile CIB_R25C1:CIB_LR_S\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0301 N3_V06S0003\n\n.tile CIB_R25C20:CIB_EBR\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0501 W1_H02E0401\narc: E3_H06E0003 JQ0\narc: E3_H06E0103 JQ2\narc: E3_H06E0203 JQ4\narc: H00R0000 V02S0401\narc: H00R0100 V02S0701\narc: JA0 H00R0000\narc: JA2 V00B0000\narc: JA6 V00T0100\narc: JC1 H02E0401\narc: JC3 H00R0100\narc: N1_V01N0001 JQ3\narc: N1_V01N0101 JQ6\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 H02E0201\narc: N3_V06N0103 JQ1\narc: N3_V06N0303 JQ5\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0501 V01N0101\narc: V00B0000 W1_H02E0601\narc: V00T0100 H02E0301\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 N3_V06S0203\narc: W3_H06W0103 V06S0103\narc: W3_H06W0303 E3_H06W0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C21:CIB_EBR\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 V01N0001\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 V01N0001\narc: E3_H06E0003 V01N0001\narc: H00L0100 H02E0101\narc: H00R0100 S1_V02N0501\narc: JA0 W1_H02E0501\narc: JA4 H02E0501\narc: JA6 V00T0100\narc: JC1 H00L0100\narc: JC5 N1_V02S0001\narc: JC7 V02S0001\narc: JCE1 H00R0100\narc: JCLK0 G_HPBX0000\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 H02W0601\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00T0100 H02E0301\narc: W1_H02W0101 N3_V06S0103\narc: N3_V06N0003 W3_H06E0003\narc: W3_H06W0203 N1_V01S0000\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\n\n.tile CIB_R25C22:CIB_EBR\narc: E1_H01E0001 JQ2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0301 V06S0003\narc: E1_H02E0701 V02N0701\narc: E3_H06E0003 JQ0\narc: E3_H06E0203 JQ4\narc: E3_H06E0303 JQ5\narc: H00L0000 S1_V02N0001\narc: H00R0000 N1_V02S0601\narc: JA0 V02N0701\narc: JA2 V00T0000\narc: JA6 H00R0000\narc: JC1 S1_V02N0401\narc: JC3 H00L0000\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 N1_V01S0100\narc: N3_V06N0003 JQ3\narc: N3_V06N0203 JQ7\narc: N3_V06N0303 JQ6\narc: S1_V02S0101 N1_V02S0001\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 JQ1\narc: S3_V06S0303 N1_V02S0601\narc: V00T0000 H02E0201\narc: W1_H02W0601 V06S0303\narc: W3_H06W0003 E1_H02W0001\narc: W3_H06W0303 E1_H02W0501\narc: E3_H06E0103 W3_H06E0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C23:CIB_EBR\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 JQ0\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 H01E0001\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 W1_H02E0001\narc: H00R0000 H02W0401\narc: H00R0100 N1_V02S0701\narc: JA0 H00R0000\narc: JA4 V00T0000\narc: JA6 V00T0100\narc: JC1 H00L0000\narc: JC5 V02N0001\narc: JC7 V00B0100\narc: JCE1 H00R0100\narc: JCLK0 G_HPBX0000\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 H02W0701\narc: S3_V06S0203 N1_V02S0401\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02E0001\narc: V00T0100 N1_V02S0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0301 S3_V06N0003\narc: E1_H01E0101 W3_H06E0203\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0203 E1_H02W0401\narc: E3_H06E0003 W3_H06E0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R25C24:CIB_EBR\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0303 H01E0101\narc: H00R0000 H02W0601\narc: H01W0100 JQ6\narc: JA0 W1_H02E0701\narc: JA1 W1_H02E0701\narc: JA2 H02E0701\narc: JA3 H02E0701\narc: JA6 N1_V02S0101\narc: JA7 N1_V02S0101\narc: JB3 V02S0101\narc: JB5 V00B0100\narc: JB7 N1_V02S0501\narc: JC0 V02S0601\narc: JC1 V02S0601\narc: JC2 H02E0401\narc: JC3 H02E0401\narc: JCLK0 G_HPBX0000\narc: JD2 H00R0000\narc: JD4 V00B0000\narc: JD6 H02E0001\narc: JLSR1 E1_H02W0301\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 JQ7\narc: N3_V06N0003 JQ3\narc: N3_V06N0103 JQ2\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ5\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 H02E0601\narc: V00B0100 V02S0301\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V06N0103\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 V02S0701\narc: E1_H01E0101 W3_H06E0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0103 E3_H06W0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C25:CIB_EBR\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 V06S0003\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 V06S0203\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 W1_H02E0701\narc: H00L0100 W1_H02E0101\narc: JA0 W1_H02E0501\narc: JA1 W1_H02E0501\narc: JA4 V00T0000\narc: JA5 V00T0000\narc: JA6 V02N0101\narc: JA7 V02N0101\narc: JB1 H02E0301\narc: JC0 H00L0100\narc: JC1 H00L0100\narc: JC4 V00B0100\narc: JC5 V00B0100\narc: JC6 H02E0601\narc: JC7 H02E0601\narc: JCLK0 G_HPBX0000\narc: JD0 H02E0001\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0601 S1_V02N0301\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 JQ1\narc: N3_V06N0203 E1_H01W0000\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N1_V02S0401\narc: S3_V06S0003 N3_V06S0003\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02E0201\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V06S0203\narc: E3_H06E0303 W3_H06E0203\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\n\n.tile CIB_R25C26:CIB_EBR\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 V01N0001\narc: E3_H06E0203 JQ4\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 E1_H02W0201\narc: H00R0100 N1_V02S0701\narc: H01W0000 JQ5\narc: JB5 H00L0000\narc: JB7 W1_H02E0101\narc: JD4 H00R0100\narc: JD6 H02W0001\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 JQ7\narc: N3_V06N0303 JQ6\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 V01N0101\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 JQ5\narc: W1_H02W0301 V06S0003\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: W3_H06W0303 E1_H02W0501\narc: E3_H06E0103 W3_H06E0103\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCLK1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JCE0MUX 1\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R25C27:CIB_EBR\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V01N0101\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 H01E0001\narc: H00L0000 V02N0201\narc: H00L0100 H02E0101\narc: H00R0000 N1_V02S0401\narc: H00R0100 S1_V02N0501\narc: JA0 V01N0101\narc: JA1 N1_V02S0501\narc: JA2 V02N0501\narc: JA3 V02S0701\narc: JA5 W1_H02E0501\narc: JB1 V00B0000\narc: JB3 V02N0101\narc: JB5 H00R0000\narc: JB7 H02E0301\narc: JC0 H02E0401\narc: JC1 H00L0000\narc: JC2 H00L0100\narc: JC3 H02W0401\narc: JC4 V00B0100\narc: JCLK0 G_HPBX0000\narc: JD0 H02E0201\narc: JD2 H02W0001\narc: JD4 H00R0100\narc: JD6 W1_H02E0201\narc: JLSR1 W1_H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 JQ4\narc: N1_V02N0001 JQ0\narc: N1_V02N0101 JQ1\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 JQ5\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 JQ3\narc: N3_V06N0103 JQ2\narc: N3_V06N0203 JQ7\narc: N3_V06N0303 JQ6\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 V01N0001\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02S0201\narc: V00B0100 W1_H02E0501\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 N1_V02S0301\narc: E1_H01E0101 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\n\n.tile CIB_R25C28:CIB_EBR\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0303 H01E0101\narc: H00L0000 V02N0001\narc: H00L0100 V02S0101\narc: H00R0100 E1_H02W0701\narc: JA0 W1_H02E0501\narc: JA1 H00L0000\narc: JA2 V00B0000\narc: JA3 W1_H02E0701\narc: JA4 V02N0101\narc: JA5 V02S0301\narc: JC0 V02N0401\narc: JC1 V02N0601\narc: JC2 H02E0601\narc: JC3 E1_H01W0000\narc: JC4 H02E0401\narc: JC5 E1_H02W0601\narc: JCE1 H00R0100\narc: JCLK0 G_HPBX0000\narc: JD0 V02S0001\narc: JD1 N1_V02S0201\narc: JD6 H00L0100\narc: JD7 N1_V02S0601\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 JQ1\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 JQ7\narc: N3_V06N0303 JQ6\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 H02W0601\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 V02N0501\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\nenum: CIB.JB5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB7MUX 0\n\n.tile CIB_R25C29:CIB_EBR\narc: E1_H01E0101 JQ7\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 JQ4\narc: E3_H06E0303 JQ6\narc: H00L0000 V02N0201\narc: H00L0100 H02E0101\narc: H00R0100 E1_H02W0501\narc: H01W0100 JQ2\narc: JA0 W1_H02E0701\narc: JA1 N1_V02S0701\narc: JA2 W1_H02E0501\narc: JA3 H00L0100\narc: JA5 V00T0100\narc: JB1 H02W0101\narc: JB3 S1_V02N0301\narc: JB5 W1_H02E0301\narc: JB7 H02W0301\narc: JC0 H02E0601\narc: JC1 H00L0000\narc: JC2 N1_V01N0001\narc: JC3 V02S0401\narc: JC4 V00T0100\narc: JCLK0 G_HPBX0000\narc: JD0 V02S0001\narc: JD2 V00B0100\narc: JD4 V00B0000\narc: JD6 H00R0100\narc: JLSR1 V00T0100\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 JQ1\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 JQ3\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 JQ5\narc: N3_V06N0003 JQ0\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02S0301\narc: V00T0100 N1_V02S0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: H01W0000 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\n\n.tile CIB_R25C2:CIB_EBR\narc: N1_V02N0001 H06W0003\narc: N1_V02N0301 H02E0301\narc: S1_V02S0001 H02E0001\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 N3_V06S0103\n\n.tile CIB_R25C30:CIB_EBR\narc: E1_H01E0001 JQ0\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0401 V06S0203\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0203 JQ7\narc: E3_H06E0303 H01E0101\narc: H00L0100 W1_H02E0301\narc: H00R0100 H02E0501\narc: JA0 H00L0100\narc: JA1 H02E0701\narc: JA4 V00T0000\narc: JA5 V00B0000\narc: JA6 E1_H02W0501\narc: JA7 V02N0101\narc: JB1 H00R0100\narc: JB3 V02S0301\narc: JB5 H02W0301\narc: JB7 H02E0101\narc: JC0 W1_H02E0401\narc: JC1 H02E0601\narc: JC4 V02N0201\narc: JC5 H02E0401\narc: JC6 N1_V02S0201\narc: JC7 S1_V02N0001\narc: JCE1 H02W0101\narc: JCLK0 G_HPBX0000\narc: JD0 V00T0100\narc: JD2 H02E0201\narc: JD4 V02S0601\narc: JD6 W1_H02E0001\narc: N1_V01N0001 JQ1\narc: N1_V01N0101 JQ5\narc: N1_V02N0001 JQ2\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 JQ3\narc: N1_V02N0401 JQ4\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 JQ5\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 JQ7\narc: N3_V06N0303 JQ6\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 N1_V02S0001\narc: V00T0000 S1_V02N0401\narc: V00T0100 H02E0301\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 V02S0501\narc: W1_H02W0701 V02N0701\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0701 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0103 V01N0101\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\n\n.tile CIB_R25C31:CIB_EBR\narc: E1_H02E0101 H01E0101\narc: E1_H02E0501 V01N0101\narc: E1_H02E0701 V06S0203\narc: E3_H06E0203 H01E0001\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H06W0203\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0101\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 V06S0303\narc: E1_H02E0201 W3_H06E0103\narc: W3_H06W0203 V06S0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\n\n.tile CIB_R25C32:CIB_EBR\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02S0601\narc: E3_H06E0203 W1_H02E0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 H06E0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N1_V02S0501\narc: V01S0000 S3_V06N0103\narc: W1_H02W0501 S1_V02N0501\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\n\n.tile CIB_R25C33:CIB_EBR\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 JQ1\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0103 JQ2\narc: E3_H06E0303 JQ6\narc: H00L0000 N1_V02S0001\narc: H00L0100 N1_V02S0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 V02S0501\narc: H01W0100 JQ7\narc: JA0 H00L0000\narc: JA1 H00L0100\narc: JA2 V00T0000\narc: JA3 V00B0000\narc: JA6 H02W0701\narc: JA7 H02W0501\narc: JB1 V02N0101\narc: JB3 W1_H02E0101\narc: JB5 V02S0701\narc: JB7 E1_H02W0101\narc: JC0 V02S0401\narc: JC1 H00R0100\narc: JC2 S1_V02N0401\narc: JC3 H02E0601\narc: JCLK0 G_HPBX0000\narc: JD0 V00B0100\narc: JD2 H00R0000\narc: JD4 N1_V02S0601\narc: JD6 H02E0001\narc: JLSR1 H02E0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 JQ0\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 JQ3\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ5\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V01S0000\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 V02N0001\narc: V00B0100 V02S0101\narc: V00T0000 V02N0601\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0501 S3_V06N0303\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0103 N3_V06S0103\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C34:CIB_EBR\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 N3_V06S0203\narc: H00L0000 H02W0201\narc: H00L0100 V02N0101\narc: H00R0000 H02E0401\narc: H00R0100 N1_V02S0501\narc: JA0 H00R0000\narc: JA4 S1_V02N0101\narc: JA5 V02N0301\narc: JA7 V00T0100\narc: JC0 H00L0100\narc: JC1 H00L0000\narc: JC4 V00B0100\narc: JC5 V00T0000\narc: JC6 W1_H02E0401\narc: JC7 N1_V02S0001\narc: JCE1 H00R0100\narc: JCLK0 G_HPBX0000\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H06E0203\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0701 V01N0101\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 H02E0501\narc: V00T0000 V02S0601\narc: V00T0100 V02N0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 V06N0103\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0701 V02S0701\narc: H01W0000 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: S1_V02S0601 W3_H06E0303\narc: W1_H02W0001 W3_H06E0003\narc: W3_H06W0203 E3_H06W0203\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R25C35:CIB_EBR\narc: E1_H01E0001 JF4\narc: E1_H01E0101 JF6\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 V02N0601\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0103 JF2\narc: E3_H06E0203 JQ4\narc: E3_H06E0303 JQ5\narc: H00L0000 W1_H02E0201\narc: H00L0100 V02N0301\narc: H00R0100 E1_H02W0501\narc: JA0 V02S0701\narc: JA1 H00L0000\narc: JA2 H02W0501\narc: JA3 H02W0701\narc: JA5 S1_V02N0101\narc: JB2 H02W0301\narc: JB4 N1_V02S0701\narc: JB5 V02S0501\narc: JB7 V00T0000\narc: JC2 H02W0601\narc: JC3 H00L0100\narc: JC4 V00B0100\narc: JC6 V00B0100\narc: JCLK0 G_HPBX0000\narc: JD2 V02N0201\narc: JD3 E1_H02W0001\narc: JD4 V00B0000\narc: JD5 H00R0100\narc: JD6 N1_V02S0401\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 JF3\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 JF7\narc: N3_V06N0003 JQ3\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 JF5\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H02E0701\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 N1_V02S0601\narc: V01S0000 N3_V06S0103\narc: V01S0100 JQ2\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 V02N0401\narc: H01W0000 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: S1_V02S0001 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0103\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JB3MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\n\n.tile CIB_R25C36:CIB_EBR\narc: E1_H01E0001 JF2\narc: E1_H01E0101 JF1\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 JF5\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0003 N3_V06S0003\narc: H00L0000 W1_H02E0001\narc: H00R0100 W1_H02E0501\narc: H01W0100 JF3\narc: JA4 V00T0000\narc: JA5 V02N0301\narc: JA6 H00L0000\narc: JA7 V02N0101\narc: JB1 N1_V02S0101\narc: JB3 H02E0101\narc: JB5 H02W0301\narc: JB7 H02E0301\narc: JC4 V00T0100\narc: JC5 H02E0401\narc: JC6 H02E0601\narc: JC7 S1_V02N0201\narc: JCE1 H00R0100\narc: JCLK0 G_HPBX0000\narc: JD0 W1_H02E0201\narc: JD2 H02E0001\narc: JD4 H02E0201\narc: JD6 S1_V02N0401\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 JF4\narc: N1_V02N0701 JF7\narc: N3_V06N0003 JF0\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 JF6\narc: S1_V02S0001 V01N0001\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N1_V02S0601\narc: V00T0000 V02S0601\narc: V00T0100 W1_H02E0301\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 N1_V02S0701\narc: S3_V06S0003 W3_H06E0003\narc: W3_H06W0203 V06S0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JA0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\n\n.tile CIB_R25C37:CIB_EBR\narc: E1_H01E0001 JQ6\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0203 JQ4\narc: E3_H06E0303 JQ5\narc: H00R0100 V02N0701\narc: H01W0000 JF0\narc: JB1 S1_V02N0101\narc: JB3 H00R0100\narc: JB5 H02E0301\narc: JB7 V00T0000\narc: JD0 H02E0201\narc: JD2 V00B0100\narc: JD4 V02S0601\narc: JD6 H02W0201\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 JF1\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 JF3\narc: N3_V06N0103 JF2\narc: N3_V06N0203 JQ7\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 H06W0003\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 N1_V02S0101\narc: V00B0100 H02E0701\narc: V00T0000 V02S0401\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 N1_V02S0701\narc: N1_V02N0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JCE0MUX 1\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCLK1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C38:CIB_EBR\narc: E1_H02E0201 V02S0201\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0103 JQ1\narc: E3_H06E0203 H01E0001\narc: H00L0000 V02S0001\narc: H00R0100 N1_V02S0701\narc: JA0 E1_H02W0501\narc: JA1 V02N0501\narc: JA2 V00T0000\narc: JA3 H02W0501\narc: JA6 H02W0701\narc: JA7 S1_V02N0101\narc: JB1 H00R0100\narc: JB3 N1_V02S0101\narc: JC0 H00L0000\narc: JC1 V02S0401\narc: JC2 H02W0601\narc: JC3 N1_V02S0601\narc: JCLK0 G_HPBX0000\narc: JD0 N1_V01S0000\narc: JD2 W1_H02E0001\narc: JLSR1 V00B0100\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 JQ2\narc: N1_V02N0101 JQ3\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 H06E0203\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02S0101\narc: V00T0000 H02E0001\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 V02N0301\narc: H01W0100 W3_H06E0303\narc: N1_V02N0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C39:CIB_EBR\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V01N0001\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 N3_V06S0003\narc: E3_H06E0203 JQ7\narc: E3_H06E0303 JQ6\narc: H00L0100 V02N0101\narc: H00R0100 W1_H02E0501\narc: JA0 W1_H02E0701\narc: JA1 V02S0501\narc: JA2 N1_V02S0701\narc: JA3 V00T0000\narc: JA4 N1_V02S0101\narc: JC0 N1_V01S0100\narc: JC1 V02N0601\narc: JC2 E1_H02W0601\narc: JC3 W1_H02E0601\narc: JC4 V00T0100\narc: JCE1 H00R0100\narc: JCLK0 G_HPBX0000\narc: JD6 V00B0000\narc: JD7 H00L0100\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H06W0203\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 E1_H01W0000\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H06W0003\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 N1_V02S0401\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 S1_V02N0201\narc: V00T0000 N1_V02S0601\narc: V00T0100 W1_H02E0101\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0501 V01N0101\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 V02S0701\narc: N1_V02N0501 W3_H06E0303\narc: N3_V06N0103 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\nenum: CIB.JB5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB7MUX 0\n\n.tile CIB_R25C3:CIB_EBR\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H06W0303\n\n.tile CIB_R25C40:CIB_EBR\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V01N0101\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02S0601\narc: E3_H06E0003 JQ3\narc: E3_H06E0103 JQ1\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 V02S0001\narc: H00L0100 H02W0101\narc: H00R0000 V02S0401\narc: H00R0100 H02W0501\narc: H01W0000 JQ4\narc: JA0 S1_V02N0501\narc: JA1 W1_H02E0501\narc: JA2 H00L0100\narc: JA3 E1_H02W0701\narc: JA6 H00R0000\narc: JA7 W1_H02E0701\narc: JB1 H02E0301\narc: JB3 V02S0101\narc: JB5 N1_V02S0701\narc: JC0 H00L0000\narc: JC1 V02S0601\narc: JC2 H02E0601\narc: JC3 W1_H02E0601\narc: JCLK0 G_HPBX0000\narc: JD0 W1_H02E0201\narc: JD2 H02E0001\narc: JD4 H00R0100\narc: JLSR1 V00B0000\narc: N1_V02N0001 JQ0\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 JQ2\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 E1_H02W0401\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 JQ5\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 N1_V01S0000\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 N1_V02S0001\narc: W1_H02W0001 V06S0003\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: W3_H06W0003 V06S0003\narc: W3_H06W0203 V06N0203\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C41:CIB_EBR\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 V01N0101\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 N3_V06S0303\narc: H00L0000 W1_H02E0201\narc: H00L0100 W1_H02E0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 H02W0501\narc: JA4 W1_H02E0501\narc: JA5 H02E0501\narc: JA6 H00R0000\narc: JA7 V00T0100\narc: JC0 H00L0000\narc: JC1 H00L0100\narc: JC4 V00B0100\narc: JC5 H02W0601\narc: JC6 V00T0000\narc: JC7 W1_H02E0401\narc: JCE1 H00R0100\narc: JCLK0 G_HPBX0000\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 H06E0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 V01N0101\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0701\narc: V00B0100 W1_H02E0701\narc: V00T0000 N1_V02S0601\narc: V00T0100 H02E0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 V02N0701\narc: N3_V06N0003 W3_H06E0003\narc: W3_H06W0103 V06N0103\narc: W3_H06W0303 E3_H06W0203\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\n\n.tile CIB_R25C42:CIB_EBR\narc: E1_H02E0001 V06S0003\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0003 JQ0\narc: E3_H06E0103 JQ2\narc: E3_H06E0303 JQ5\narc: H00L0000 H02W0001\narc: H00L0100 V02S0301\narc: H00R0000 W1_H02E0401\narc: H00R0100 N1_V02S0701\narc: H01W0100 JQ6\narc: JA0 N1_V02S0501\narc: JA1 H00L0100\narc: JA2 V00T0000\narc: JA3 V02N0701\narc: JA6 H00R0000\narc: JA7 N1_V02S0101\narc: JB1 H00R0100\narc: JB3 H00L0000\narc: JB5 V02S0701\narc: JB7 V00B0000\narc: JC0 V02N0401\narc: JC1 W1_H02E0601\narc: JC2 V02S0401\narc: JC3 N1_V02S0401\narc: JCLK0 G_HPBX0000\narc: JD0 H02E0001\narc: JD2 V02S0201\narc: JD4 N1_V02S0601\narc: JD6 E1_H02W0001\narc: JLSR1 V00B0100\narc: N1_V01N0001 JQ7\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 JQ3\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 V01N0101\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 JQ1\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 H06E0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0601\narc: V00B0100 E1_H02W0701\narc: V00T0000 H02E0201\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02N0701\narc: E1_H01E0001 W3_H06E0003\narc: W3_H06W0003 V06S0003\narc: W3_H06W0203 S3_V06N0203\narc: E3_H06E0203 W3_H06E0203\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C43:CIB_EBR\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0103 S3_V06N0103\narc: H00L0100 V02S0301\narc: H00R0000 H02E0401\narc: H00R0100 S1_V02N0501\narc: JA0 H00L0100\narc: JA4 V00B0000\narc: JA5 V00T0100\narc: JA7 H00R0000\narc: JC0 V02N0401\narc: JC1 H00R0100\narc: JC4 H02E0601\narc: JC5 V02S0001\narc: JC6 W1_H02E0601\narc: JC7 N1_V02S0201\narc: JCE1 W1_H02E0101\narc: JCLK0 G_HPBX0000\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H01E0001\narc: N3_V06N0003 H06W0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 W1_H02E0401\narc: V00T0100 H02E0301\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 V01N0101\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 V02N0701\narc: N1_V02N0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R25C44:CIB_EBR\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0003 JQ3\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 N3_V06S0303\narc: H00L0000 H02W0001\narc: H00L0100 H02W0101\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02W0701\narc: H01W0100 JQ4\narc: JA0 H00L0100\narc: JA1 H00L0100\narc: JA2 V00T0000\narc: JA3 V00T0000\narc: JA6 V00T0100\narc: JA7 V00T0100\narc: JB3 V02S0301\narc: JB5 H00L0000\narc: JB7 S1_V02N0701\narc: JC0 H02W0601\narc: JC1 H02W0601\narc: JC2 H00R0100\narc: JC3 H00R0100\narc: JCLK0 G_HPBX0000\narc: JD2 H00R0000\narc: JD4 S1_V02N0601\narc: JD6 V00B0000\narc: JLSR1 V00B0100\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H06E0203\narc: N1_V02N0701 JQ5\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 JQ2\narc: N3_V06N0203 JQ7\narc: N3_V06N0303 JQ6\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0401\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02E0201\narc: V00T0100 V02N0701\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0401 V02S0401\narc: W1_H02W0701 V02S0701\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0101 W3_H06E0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C45:CIB_EBR\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V02S0701\narc: E3_H06E0003 JQ0\narc: JA4 V00T0100\narc: JA5 V00T0100\narc: JA6 V02N0301\narc: JA7 V02N0301\narc: JB1 H02E0301\narc: JC4 V02S0001\narc: JC5 V02S0001\narc: JC6 V00B0100\narc: JC7 V00B0100\narc: JCLK0 G_HPBX0000\narc: JD0 H02E0001\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 JQ1\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 E1_H01W0000\narc: N3_V06N0103 H06E0103\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V01S0100\narc: V00B0100 H02E0501\narc: V00T0100 H02E0101\narc: V01S0000 N3_V06S0103\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 N1_V02S0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: N3_V06N0203 W3_H06E0203\narc: N3_V06N0303 W3_H06E0303\narc: S1_V02S0301 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\n\n.tile CIB_R25C46:CIB_EBR\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0203 V01N0001\narc: H00L0000 V02S0001\narc: JB5 H00L0000\narc: JB7 V02S0701\narc: JD4 H02W0001\narc: JD6 H02W0201\narc: N1_V01N0001 JQ4\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 JQ5\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 H06W0103\narc: N3_V06N0203 JQ7\narc: N3_V06N0303 JQ6\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0303\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V06N0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 V06S0203\narc: H01W0000 W3_H06E0103\narc: W3_H06W0003 S3_V06N0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCLK1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JCE0MUX 1\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R25C47:CIB_EBR\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0203 N3_V06S0203\narc: E3_H06E0303 V06N0303\narc: H00L0000 W1_H02E0201\narc: H00R0100 S1_V02N0501\narc: H01W0000 JQ3\narc: H01W0100 JQ0\narc: JA0 H00L0000\narc: JA1 H00L0000\narc: JA2 V00T0000\narc: JA3 V00T0000\narc: JA6 H02W0701\narc: JA7 H02W0701\narc: JB1 V02S0301\narc: JB3 H02E0101\narc: JC0 H00R0100\narc: JC1 H00R0100\narc: JC2 E1_H02W0401\narc: JC3 E1_H02W0401\narc: JCLK0 G_HPBX0000\narc: JD0 V02S0001\narc: JD2 V00B0100\narc: JLSR1 V00B0000\narc: N1_V01N0001 JQ1\narc: N1_V01N0101 JQ2\narc: N1_V02N0101 H06E0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H02W0401\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 H06E0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 H06E0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0701\narc: V00T0000 H02W0001\narc: V01S0000 S3_V06N0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 V06S0103\narc: W1_H02W0501 V02N0501\narc: W3_H06W0203 V01N0001\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C48:CIB_EBR\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0003 N1_V01S0000\narc: H00L0000 H02E0001\narc: H00L0100 V02S0301\narc: JA0 H02E0501\narc: JA1 V02N0701\narc: JA2 W1_H02E0501\narc: JA3 V00T0000\narc: JC0 H02E0401\narc: JC1 W1_H02E0401\narc: JC2 H00L0100\narc: JC3 H00L0000\narc: JCLK0 G_HPBX0000\narc: JD6 H02W0201\narc: JD7 V00B0000\narc: N1_V01N0001 JQ7\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 JQ6\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 E1_H01W0000\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 E1_H02W0401\narc: V00T0000 H02E0001\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0301 V01N0101\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 E1_H02W0701\narc: E1_H01E0001 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\nenum: CIB.JB5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB7MUX 0\n\n.tile CIB_R25C49:CIB_EBR\narc: E1_H01E0001 JQ2\narc: E1_H01E0101 JQ4\narc: E1_H02E0001 JQ0\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 V01N0001\narc: E3_H06E0203 V01N0001\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02N0101\narc: H00R0100 H02E0501\narc: H01W0000 JQ0\narc: H01W0100 JQ5\narc: JA0 E1_H02W0701\narc: JA1 E1_H02W0701\narc: JA2 V00B0000\narc: JA3 V00B0000\narc: JA6 H02W0701\narc: JA7 H02W0701\narc: JB1 H02E0101\narc: JB3 H00R0100\narc: JB5 H00L0000\narc: JC0 W1_H02E0601\narc: JC1 W1_H02E0601\narc: JC2 E1_H02W0401\narc: JC3 E1_H02W0401\narc: JCLK0 G_HPBX0000\narc: JD0 H02E0001\narc: JD2 V02N0201\narc: JD4 H00L0100\narc: JLSR1 H02E0301\narc: N1_V01N0001 JQ3\narc: N1_V01N0101 JQ1\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0401\narc: W1_H02W0201 V02S0201\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 V01N0001\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0103 JQ1\narc: E3_H06E0103 W3_H06E0003\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C4:CIB_EBR\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0601 V02N0601\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0701 N3_V06S0203\narc: W1_H02W0601 N3_V06S0303\n\n.tile CIB_R25C50:CIB_EBR\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0103 V01N0101\narc: JA4 V00T0100\narc: JA5 V00T0100\narc: JA6 V02N0301\narc: JA7 V02N0301\narc: JC4 H02E0401\narc: JC5 H02E0401\narc: JC6 V00B0100\narc: JC7 V00B0100\narc: JCLK0 G_HPBX0000\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 V01N0001\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 H01E0001\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0100 N1_V02S0301\narc: V00T0100 S1_V02N0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 V02S0401\narc: W1_H02W0701 V02N0701\narc: N1_V02N0301 W3_H06E0003\narc: W1_H02W0601 W3_H06E0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\n\n.tile CIB_R25C51:CIB_EBR\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0003 JQ3\narc: E3_H06E0103 JQ2\narc: E3_H06E0303 JQ6\narc: JA0 S1_V02N0701\narc: JA1 S1_V02N0701\narc: JA2 V00B0000\narc: JA3 V00B0000\narc: JA6 H02W0701\narc: JA7 H02W0701\narc: JB1 V00T0000\narc: JB3 N1_V02S0301\narc: JB5 N1_V02S0701\narc: JB7 V00B0100\narc: JC0 H02E0601\narc: JC1 H02E0601\narc: JC2 N1_V02S0401\narc: JC3 N1_V02S0401\narc: JCLK0 G_HPBX0000\narc: JD0 H02W0001\narc: JD2 V00T0100\narc: JD4 H02W0201\narc: JD6 V02N0601\narc: JLSR1 H02W0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 JQ0\narc: N1_V02N0401 JQ4\narc: N1_V02N0501 JQ5\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 JQ7\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 JQ1\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 V02S0201\narc: V00B0100 V02N0301\narc: V00T0000 N1_V02S0601\narc: V00T0100 H02E0101\narc: W1_H02W0401 N1_V02S0401\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0301 W3_H06E0003\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0203 W3_H06E0203\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C52:CIB_EBR\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V02N0701\narc: H00R0000 H02W0601\narc: JA0 W1_H02E0701\narc: JA4 V02N0301\narc: JA5 W1_H02E0701\narc: JA7 H00R0000\narc: JC1 H02E0601\narc: JC4 H02E0601\narc: JC5 V00T0100\narc: JC6 V00T0100\narc: JCLK0 G_HPBX0000\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: V00T0100 H02W0301\narc: W1_H02W0001 V02S0001\narc: W1_H02W0201 V02S0201\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V02S0501\narc: W1_H02W0701 V02N0701\narc: E3_H06E0003 W3_H06E0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R25C53:CIB_EBR\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 V02S0701\narc: E3_H06E0003 JQ3\narc: E3_H06E0103 JQ2\narc: E3_H06E0303 JQ6\narc: H00L0100 N1_V02S0101\narc: H00R0000 V02S0601\narc: H00R0100 H02E0501\narc: H01W0100 JQ4\narc: JA0 W1_H02E0701\narc: JA1 W1_H02E0701\narc: JA2 V00T0000\narc: JA3 V00T0000\narc: JA6 H02E0701\narc: JA7 H02E0701\narc: JB3 H00R0100\narc: JB5 V01S0000\narc: JB7 V00B0100\narc: JC0 H00L0100\narc: JC1 H00L0100\narc: JC2 H02W0401\narc: JC3 H02W0401\narc: JCLK0 G_HPBX0000\narc: JD2 H00R0000\narc: JD4 N1_V02S0401\narc: JD6 N1_V02S0601\narc: JLSR1 H02E0301\narc: N1_V01N0001 JQ5\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H02W0301\narc: N1_V02N0501 JQ7\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0701\narc: V00B0100 S1_V02N0101\narc: V00T0000 W1_H02E0201\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 V06N0203\narc: W1_H02W0601 E1_H02W0301\narc: N1_V02N0601 W3_H06E0303\narc: S1_V02S0001 W3_H06E0003\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\n\n.tile CIB_R25C54:CIB_EBR\narc: E1_H02E0101 JQ1\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 N3_V06S0303\narc: H01W0000 JQ0\narc: JA4 V00B0000\narc: JA5 V00B0000\narc: JA6 V00T0100\narc: JA7 V00T0100\narc: JB1 V02S0101\narc: JC4 V02S0001\narc: JC5 V02S0001\narc: JC6 N1_V02S0001\narc: JC7 N1_V02S0001\narc: JCLK0 G_HPBX0000\narc: JD0 V00B0100\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 V01N0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N1_V02S0001\narc: V00B0000 H02E0601\narc: V00B0100 H02E0701\narc: V00T0100 H02W0301\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 N1_V02S0401\narc: E3_H06E0003 W3_H06E0003\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\n\n.tile CIB_R25C55:CIB_EBR\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 V06S0203\narc: JB5 V00B0100\narc: JB7 V00T0000\narc: JD4 V02S0401\narc: JD6 V02S0601\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 JQ7\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 JQ5\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ6\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 H02W0601\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 N1_V02S0301\narc: V00T0000 W1_H02E0001\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0301 V02N0301\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JCE0MUX 1\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCLK1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C56:CIB_EBR\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 N1_V02S0501\narc: E3_H06E0103 V01N0101\narc: H00L0000 N1_V02S0201\narc: H00R0000 H02E0401\narc: H00R0100 W1_H02E0501\narc: H01W0000 JQ1\narc: JA0 H02W0701\narc: JA1 H02W0701\narc: JA2 V02S0701\narc: JA3 V02S0701\narc: JA6 E1_H02W0701\narc: JA7 E1_H02W0701\narc: JB1 H00R0100\narc: JB3 H02E0101\narc: JC0 H00L0000\narc: JC1 H00L0000\narc: JC2 W1_H02E0401\narc: JC3 W1_H02E0401\narc: JCLK0 G_HPBX0000\narc: JD0 W1_H02E0201\narc: JD2 H00R0000\narc: JLSR1 V00B0000\narc: N1_V01N0001 JQ2\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 JQ3\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0203 E1_H01W0000\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 N3_V06S0203\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 W1_H02E0601\narc: V01S0100 N3_V06S0303\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 V02N0601\narc: W1_H02W0201 W3_H06E0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C57:CIB_EBR\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 H02E0001\narc: H00L0100 V02S0301\narc: H00R0100 H02E0501\narc: JA0 H00L0100\narc: JA1 H02E0501\narc: JA2 V00T0000\narc: JA3 V00B0000\narc: JC0 H00L0100\narc: JC1 H00R0100\narc: JC2 H00L0000\narc: JC3 V02N0401\narc: JCLK0 G_HPBX0000\narc: JD6 V02S0601\narc: JD7 V02N0601\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 JQ7\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 H06W0203\narc: N3_V06N0303 JQ6\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 E1_H02W0401\narc: V00T0000 H02E0001\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 N3_V06S0003\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0701 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N3_V06N0003 W3_H06E0003\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0203 W3_H06E0203\nenum: CIB.JB5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB7MUX 0\n\n.tile CIB_R25C58:CIB_EBR\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0701 H01E0101\narc: H00L0000 V02S0201\narc: H00R0000 H02E0401\narc: H00R0100 N1_V02S0701\narc: H01W0000 JQ1\narc: H01W0100 JQ5\narc: JA0 H02W0501\narc: JA1 H02E0701\narc: JA2 V02S0701\narc: JA3 V02S0701\narc: JA6 V00T0100\narc: JA7 V00T0100\narc: JB1 H02E0301\narc: JB3 H02E0101\narc: JB5 H00R0000\narc: JC0 H00L0000\narc: JC1 H00L0000\narc: JC2 H00R0100\narc: JC3 H00R0100\narc: JCLK0 G_HPBX0000\narc: JD0 H02E0001\narc: JD2 H02E0201\narc: JD4 V00B0000\narc: JLSR1 V00B0100\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 JQ2\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 H02E0601\narc: V00B0100 E1_H02W0701\narc: V00T0100 V02N0701\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 V02N0701\narc: E1_H01E0001 W3_H06E0003\narc: W3_H06W0003 JQ3\narc: W3_H06W0203 JQ4\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C59:CIB_EBR\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0501 V02N0501\narc: JA4 H02E0501\narc: JA5 H02E0501\narc: JA6 V00T0100\narc: JA7 V00T0100\narc: JC4 V02S0001\narc: JC5 V02S0001\narc: JC6 N1_V02S0001\narc: JC7 N1_V02S0001\narc: JCLK0 G_HPBX0000\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 H01E0001\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 S3_V06N0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00T0100 E1_H02W0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 E1_H02W0401\narc: N1_V02N0501 W3_H06E0303\narc: N3_V06N0003 W3_H06E0003\narc: W3_H06W0103 E3_H06W0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\n\n.tile CIB_R25C5:CIB_EBR\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 H02E0601\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0101 H02W0101\narc: W3_H06W0003 E3_H06W0003\n\n.tile CIB_R25C60:CIB_EBR\narc: H00L0000 H02E0201\narc: H00L0100 V02S0101\narc: H00R0000 V02N0401\narc: H00R0100 V02N0701\narc: JA0 W1_H02E0701\narc: JA1 W1_H02E0701\narc: JA2 V00T0000\narc: JA3 V00T0000\narc: JA6 H02W0701\narc: JA7 H02W0701\narc: JB1 V02N0101\narc: JB3 H00R0100\narc: JB5 V02S0701\narc: JB7 V02N0501\narc: JC0 E1_H02W0401\narc: JC1 H00L0000\narc: JC2 N1_V02S0601\narc: JC3 N1_V02S0601\narc: JCLK0 G_HPBX0000\narc: JD0 V00B0100\narc: JD2 H00R0000\narc: JD4 V02S0401\narc: JD6 H00L0100\narc: JLSR1 V00B0000\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 JQ1\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ6\narc: V00B0000 V02N0001\narc: V00B0100 H02E0501\narc: V00T0000 V02S0601\narc: W1_H02W0701 V06S0203\narc: S3_V06S0003 W3_H06E0003\narc: W3_H06W0003 JQ3\narc: W3_H06W0103 JQ2\narc: W3_H06W0203 JQ7\narc: W3_H06W0303 JQ5\narc: E3_H06E0003 W3_H06E0003\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C61:CIB_EBR\narc: E1_H02E0201 V02N0201\narc: E1_H02E0701 V02N0701\narc: H00L0000 V02S0001\narc: JA0 N1_V02S0501\narc: JA4 V02N0101\narc: JA5 N1_V02S0301\narc: JA7 V02N0101\narc: JC1 H00L0000\narc: JC4 V02S0001\narc: JC5 V02N0001\narc: JC6 V02N0001\narc: JCLK0 G_HPBX0000\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 E3_H06W0103\narc: W1_H02W0101 V02N0101\narc: W1_H02W0701 V02N0701\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R25C62:CIB_EBR\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0601 N1_V02S0601\narc: H00R0000 H02W0401\narc: H00R0100 H02W0501\narc: JA0 H00R0000\narc: JA1 H00R0000\narc: JA2 H02W0701\narc: JA3 H02W0701\narc: JA6 H02E0701\narc: JA7 H02E0701\narc: JB3 S1_V02N0101\narc: JB5 V02S0701\narc: JB7 V00B0000\narc: JC0 S1_V02N0401\narc: JC1 S1_V02N0401\narc: JC2 H00R0100\narc: JC3 H00R0100\narc: JCLK0 G_HPBX0000\narc: JD2 V02S0001\narc: JD4 V02N0401\narc: JD6 V02N0601\narc: JLSR1 V00T0000\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ6\narc: S3_V06S0103 N1_V02S0201\narc: V00B0000 V02S0201\narc: V00T0000 V02S0601\narc: W1_H02W0401 S1_V02N0401\narc: W3_H06W0003 JQ3\narc: W3_H06W0103 JQ2\narc: W3_H06W0203 JQ7\narc: W3_H06W0303 JQ5\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C63:CIB_EBR\narc: E1_H02E0501 N1_V02S0501\narc: H00L0000 W1_H02E0201\narc: JA4 V02N0101\narc: JA5 V00B0000\narc: JA6 H00L0000\narc: JA7 H00L0000\narc: JB1 H02E0301\narc: JC4 V02S0001\narc: JC5 V02S0001\narc: JC6 H02W0601\narc: JC7 H02W0601\narc: JCLK0 G_HPBX0000\narc: JD0 H02E0201\narc: N3_V06N0303 H06W0303\narc: S3_V06S0003 H06E0003\narc: V00B0000 H02E0601\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0701 V02S0701\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0701 W3_H06E0203\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0003 JQ0\narc: W3_H06W0103 JQ1\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\n\n.tile CIB_R25C64:CIB_EBR\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 V06S0203\narc: H00R0100 V02S0501\narc: JB5 V02N0701\narc: JB7 V00B0000\narc: JD4 H00R0100\narc: JD6 V02N0601\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ6\narc: V00B0000 V02N0201\narc: W1_H02W0601 N1_V02S0601\narc: W3_H06W0203 JQ7\narc: W3_H06W0303 JQ5\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCLK1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JCE0MUX 1\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R25C65:CIB_EBR\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V01N0001\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0701 N1_V02S0701\narc: H00R0000 H02E0401\narc: H00R0100 W1_H02E0501\narc: JA0 W1_H02E0701\narc: JA1 W1_H02E0701\narc: JA2 V00T0000\narc: JA3 V00T0000\narc: JA6 V02N0301\narc: JA7 V02N0301\narc: JB1 H02E0101\narc: JB3 H00R0000\narc: JC0 S1_V02N0401\narc: JC1 S1_V02N0401\narc: JC2 H00R0100\narc: JC3 H00R0100\narc: JCLK0 G_HPBX0000\narc: JD0 V00B0100\narc: JD2 H02E0201\narc: JLSR1 H02E0501\narc: N3_V06N0003 JQ3\narc: N3_V06N0103 JQ1\narc: V00B0100 H02E0701\narc: V00T0000 V02S0401\narc: W3_H06W0003 JQ0\narc: W3_H06W0103 JQ2\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C66:CIB_EBR\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 V02N0701\narc: H00L0000 V02S0001\narc: H00R0100 V02N0701\narc: JA0 H00L0000\narc: JA1 V02N0701\narc: JA2 V00B0000\narc: JA3 H02W0701\narc: JC0 H00L0000\narc: JC1 H00R0100\narc: JC2 W1_H02E0601\narc: JC3 H02W0401\narc: JCLK0 G_HPBX0000\narc: JD6 V02S0401\narc: JD7 N1_V02S0601\narc: V00B0000 W1_H02E0601\narc: E1_H02E0001 W3_H06E0003\narc: S3_V06S0003 W3_H06E0003\narc: W3_H06W0203 JQ7\narc: W3_H06W0303 JQ6\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JB0MUX 0\n\n.tile CIB_R25C67:CIB_EBR\narc: H00L0000 V02N0001\narc: H00L0100 W1_H02E0101\narc: H00R0000 H02E0401\narc: H00R0100 W1_H02E0701\narc: JA0 H00L0000\narc: JA1 H00L0000\narc: JA2 W1_H02E0501\narc: JA3 W1_H02E0501\narc: JA6 S1_V02N0301\narc: JA7 S1_V02N0301\narc: JB1 H02E0301\narc: JB3 H00R0100\narc: JB5 H00R0000\narc: JC0 S1_V02N0601\narc: JC1 S1_V02N0601\narc: JC2 H00L0100\narc: JC3 H00L0100\narc: JCLK0 G_HPBX0000\narc: JD0 W1_H02E0001\narc: JD2 W1_H02E0201\narc: JD4 V02N0601\narc: JLSR1 V00B0100\narc: N3_V06N0003 JQ3\narc: N3_V06N0103 JQ2\narc: V00B0100 V02S0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 V02N0701\narc: W3_H06W0003 JQ0\narc: W3_H06W0103 JQ1\narc: W3_H06W0203 JQ4\narc: W3_H06W0303 JQ5\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R25C68:CIB_EBR\narc: JA0 V02N0501\narc: JA1 V02N0501\narc: JA4 V00T0000\narc: JA5 V00T0000\narc: JA6 W1_H02E0701\narc: JA7 W1_H02E0701\narc: JC0 N1_V02S0401\narc: JC1 N1_V02S0401\narc: JC4 V00B0100\narc: JC5 V00B0100\narc: JC6 V02S0001\narc: JC7 V02S0001\narc: JCLK0 G_HPBX0000\narc: V00B0100 W1_H02E0501\narc: V00T0000 W1_H02E0001\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\n\n.tile CIB_R25C69:CIB_EBR\narc: S1_V02S0301 N3_V06S0003\narc: S3_V06S0103 N3_V06S0003\n\n.tile CIB_R25C6:CIB_EBR\narc: E1_H01E0101 E3_H06W0203\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0501 S3_V06N0303\narc: N3_V06N0303 S1_V02N0501\narc: W1_H02W0101 V06S0103\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 V06N0303\narc: W3_H06W0303 V06N0303\narc: W3_H06W0203 E3_H06W0103\n\n.tile CIB_R25C70:CIB_EBR\narc: E1_H02E0301 V02S0301\n\n.tile CIB_R25C71:CIB_LR_S\narc: JA0 N1_V02S0701\narc: JA3 V02S0501\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 H02E0301\narc: JLSR1 H02E0301\narc: S3_V06S0203 N3_V06S0203\nenum: CIB.JB3MUX 0\nenum: CIB.JB0MUX 0\n\n.tile CIB_R25C7:CIB_EBR\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 H01E0101\narc: N3_V06N0003 H06W0003\narc: S1_V02S0001 V01N0001\narc: S1_V02S0201 N1_V01S0000\narc: W1_H02W0201 V01N0001\n\n.tile CIB_R25C8:CIB_EBR\narc: E1_H02E0401 V06S0203\narc: E3_H06E0103 V01N0101\narc: E3_H06E0203 N3_V06S0203\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0701 E1_H02W0701\n\n.tile CIB_R25C9:CIB_EBR\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 N1_V02S0501\narc: N1_V02N0101 H02W0101\narc: N1_V02N0601 E1_H01W0000\narc: N3_V06N0203 H06W0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 N1_V02S0201\n\n.tile CIB_R26C1:CIB_LR\narc: E1_H02E0001 E1_H01W0000\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0401 S1_V02N0401\n\n.tile CIB_R26C71:CIB_LR\narc: H00L0000 V02N0201\narc: JA0 H00L0000\narc: JA3 V00B0000\narc: JB3 W1_H02E0301\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 V00B0100\narc: JLSR1 V00B0100\narc: N3_V06N0203 JQ4\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02N0101\narc: W3_H06W0203 S3_V06N0203\nenum: CIB.JB0MUX 0\n\n.tile CIB_R27C1:CIB_LR\narc: E1_H02E0401 V02N0401\n\n.tile CIB_R27C71:CIB_LR\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 W1_H02E0201\narc: S1_V02S0101 H02E0101\narc: S3_V06S0203 N3_V06S0103\n\n.tile CIB_R28C1:CIB_LR\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0501 E1_H01W0100\narc: N1_V02N0401 E3_H06W0203\narc: N3_V06N0203 E3_H06W0203\n\n.tile CIB_R28C71:CIB_LR\narc: JA0 N1_V02S0701\narc: JA3 V00T0000\narc: JB0 W1_H02E0101\narc: JB3 W1_H02E0101\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 V00B0100\narc: JLSR1 V00B0100\narc: N3_V06N0203 JF4\narc: V00B0100 V02S0101\narc: V00T0000 H02E0201\narc: W3_H06W0203 JQ4\narc: W3_H06W0303 S3_V06N0303\n\n.tile CIB_R29C1:CIB_LR\narc: E1_H02E0001 E3_H06W0003\n\n.tile CIB_R29C71:CIB_LR\narc: S1_V02S0401 N3_V06S0203\narc: W3_H06W0203 S3_V06N0203\narc: W3_H06W0303 JQ5\n\n.tile CIB_R2C71:CIB_LR\narc: JA0 H02E0701\narc: JA3 H01E0001\narc: JB3 S1_V02N0301\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 V00B0000\narc: JLSR1 V00B0000\narc: V00B0000 V02N0201\narc: W3_H06W0203 JQ4\nenum: CIB.JB0MUX 0\n\n.tile CIB_R30C1:CIB_LR\narc: S3_V06S0003 N3_V06S0003\n\n.tile CIB_R30C71:CIB_LR\narc: S3_V06S0303 N3_V06S0203\n\n.tile CIB_R31C71:CIB_LR\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0701 N3_V06S0203\n\n.tile CIB_R32C1:CIB_LR\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0401 E3_H06W0203\narc: N3_V06N0103 E3_H06W0103\narc: S3_V06S0203 E1_H01W0000\n\n.tile CIB_R32C71:CIB_LR\narc: JA0 V02S0701\narc: JA3 V02S0501\narc: JB0 W1_H02E0101\narc: JB3 W1_H02E0101\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 H02E0301\narc: JLSR1 H02E0301\narc: N3_V06N0203 JQ4\narc: S3_V06S0203 N3_V06S0103\narc: W3_H06W0203 JF4\n\n.tile CIB_R33C1:CIB_LR\narc: E1_H02E0001 V06S0003\narc: S1_V02S0501 E1_H01W0100\n\n.tile CIB_R33C71:CIB_LR\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 N3_V06S0203\n\n.tile CIB_R34C1:CIB_LR\narc: E1_H02E0001 S1_V02N0001\narc: N1_V02N0001 S1_V02N0001\n\n.tile CIB_R34C71:CIB_LR\narc: JA3 H02E0501\narc: N3_V06N0303 JF5\nenum: CIB.JB3MUX 0\n\n.tile CIB_R35C1:CIB_LR\narc: JA3 N1_V02S0501\nenum: CIB.JB3MUX 0\n\n.tile CIB_R35C71:CIB_LR\narc: JA0 V02N0501\narc: JA3 N1_V02S0701\narc: JB0 W1_H02E0101\narc: JB3 W1_H02E0101\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 V00B0100\narc: JLSR1 V00B0100\narc: N3_V06N0203 JF4\narc: S1_V02S0501 N1_V02S0501\narc: V00B0100 V02N0101\narc: W3_H06W0203 JQ4\n\n.tile CIB_R36C1:CIB_LR\narc: N1_V02N0001 N3_V06S0003\n\n.tile CIB_R36C71:CIB_LR\narc: N1_V02N0101 H02E0101\narc: N1_V02N0501 N3_V06S0303\narc: S1_V02S0101 H02E0101\n\n.tile CIB_R37C11:CIB_EBR\narc: N1_V02N0101 N3_V06S0103\n\n.tile CIB_R37C12:CIB_EBR\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0701 V02S0701\n\n.tile CIB_R37C13:CIB_EBR\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0003 JQ0\narc: E3_H06E0103 JQ2\narc: E3_H06E0203 JQ4\narc: H00R0000 V02S0401\narc: JA0 H00R0000\narc: JA2 E1_H02W0501\narc: JA6 V02S0301\narc: JC1 N1_V01S0100\narc: JC3 S1_V02N0401\narc: N1_V01N0001 N3_V06S0003\narc: N3_V06N0003 JQ3\narc: N3_V06N0103 JQ1\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C14:CIB_EBR\narc: E1_H02E0401 W1_H02E0401\narc: H00R0000 H02E0601\narc: JA0 W1_H02E0701\narc: JA4 S1_V02N0301\narc: JA6 V00T0100\narc: JC1 W1_H02E0401\narc: JC5 H02E0401\narc: JC7 V02N0201\narc: JCE1 H00R0000\narc: JCLK0 G_HPBX0000\narc: V00T0100 N1_V02S0501\narc: V01S0000 N3_V06S0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R37C15:CIB_EBR\narc: E1_H02E0401 V06S0203\narc: E3_H06E0003 JQ3\narc: E3_H06E0103 JQ2\narc: E3_H06E0203 JQ4\narc: E3_H06E0303 JQ5\narc: H00L0000 H02W0201\narc: H00R0100 H02W0701\narc: JA0 H00L0000\narc: JA2 V02N0501\narc: JA6 V02S0301\narc: JC1 H02W0601\narc: JC3 H00R0100\narc: N3_V06N0303 JQ6\narc: W1_H02W0501 V02N0501\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C16:CIB_EBR\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0601 V06S0303\narc: H00R0100 S1_V02N0501\narc: JA0 H02W0701\narc: JA4 V02S0101\narc: JA6 S1_V02N0301\narc: JC1 H02W0601\narc: JC5 W1_H02E0401\narc: JC7 H02E0401\narc: JCE1 H00R0100\narc: JCLK0 G_HPBX0000\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 E1_H02W0601\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\n\n.tile CIB_R37C17:CIB_EBR\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0203 JQ4\narc: E3_H06E0303 JQ6\narc: N1_V01N0001 JQ5\narc: N1_V02N0301 N3_V06S0003\narc: N3_V06N0203 JQ7\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 N1_V01S0100\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCLK1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JCE0MUX 1\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R37C18:CIB_EBR\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 JQ0\narc: H00L0000 W1_H02E0201\narc: JA0 H00L0000\narc: JA2 V00B0000\narc: JA6 S1_V02N0301\narc: JC1 W1_H02E0601\narc: JC3 S1_V02N0601\narc: N1_V02N0201 N3_V06S0103\narc: V00B0000 V02N0201\narc: W1_H02W0601 S1_V02N0601\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C19:CIB_EBR\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0203 JQ7\narc: JA0 N1_V02S0701\narc: JA1 H02E0701\narc: JA2 V02S0701\narc: JA3 V00T0000\narc: JA4 V00B0000\narc: JA5 V00T0100\narc: JCE1 S1_V02N0201\narc: JCLK0 G_HPBX0000\narc: N1_V01N0101 JQ6\narc: V00B0000 W1_H02E0601\narc: V00T0000 H02W0201\narc: V00T0100 W1_H02E0101\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\nenum: CIB.JB5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC3MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JB7MUX 0\n\n.tile CIB_R37C20:CIB_EBR\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 JQ0\narc: E3_H06E0103 JQ1\narc: JA0 V02S0501\narc: JA2 V00B0000\narc: JA6 H02E0701\narc: JC1 H02E0601\narc: JC3 W1_H02E0601\narc: N1_V01N0001 JQ2\narc: V00B0000 V02N0201\narc: W1_H02W0201 N1_V02S0201\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C21:CIB_EBR\narc: E1_H02E0701 N1_V02S0701\narc: JA0 W1_H02E0501\narc: JA4 H02E0701\narc: JA6 N1_V02S0101\narc: JC1 N1_V02S0601\narc: JC5 V00T0100\narc: JC7 W1_H02E0401\narc: JCE1 V02S0201\narc: JCLK0 G_HPBX0000\narc: V00T0100 N1_V02S0701\narc: E1_H02E0301 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\n\n.tile CIB_R37C22:CIB_EBR\narc: E1_H02E0501 N3_V06S0303\narc: E3_H06E0003 JQ3\narc: E3_H06E0103 JQ2\narc: E3_H06E0203 JQ4\narc: H00L0000 S1_V02N0201\narc: H00R0000 V02S0401\narc: JA0 H02W0501\narc: JA2 V00B0000\narc: JA6 H00R0000\narc: JC1 S1_V02N0601\narc: JC3 H00L0000\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 JQ0\narc: N1_V02N0301 JQ1\narc: N1_V02N0701 H06E0203\narc: V00B0000 V02N0201\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C23:CIB_EBR\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0003 W1_H02E0301\narc: H00R0100 W1_H02E0701\narc: JA0 H02W0701\narc: JA4 N1_V02S0101\narc: JA6 H02E0501\narc: JC1 H00R0100\narc: JC5 H02W0401\narc: JC7 V00T0000\narc: JCE1 H02W0101\narc: JCLK0 G_HPBX0000\narc: V00T0000 N1_V02S0401\narc: W1_H02W0501 N1_V02S0501\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R37C24:CIB_EBR\narc: E1_H02E0101 V06S0103\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 V02S0701\narc: E3_H06E0203 JQ7\narc: E3_H06E0303 JQ6\narc: JA0 H02E0501\narc: JA2 V00B0000\narc: JA6 N1_V02S0101\narc: JC1 V02S0601\narc: JC3 H02E0601\narc: N1_V01N0101 JQ4\narc: N3_V06N0003 JQ3\narc: N3_V06N0103 JQ2\narc: N3_V06N0303 JQ5\narc: V00B0000 V02S0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0701 V02S0701\narc: E3_H06E0003 W3_H06E0003\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C25:CIB_EBR\narc: E3_H06E0003 JQ0\narc: E3_H06E0103 JQ1\narc: H01W0100 E3_H06W0303\narc: JA0 H02W0501\narc: JA4 H02E0701\narc: JA6 V00T0100\narc: JC1 W1_H02E0401\narc: JC5 H02E0401\narc: JC7 H02E0601\narc: JCE1 H02E0101\narc: JCLK0 G_HPBX0000\narc: N1_V02N0201 H06E0103\narc: N1_V02N0601 N1_V01S0000\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 JQ2\narc: V00T0100 H02W0101\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0301 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\n\n.tile CIB_R37C26:CIB_EBR\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 V01N0001\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0203 JQ7\narc: E3_H06E0303 JQ6\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H02E0301\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 JQ5\narc: N3_V06N0203 JQ4\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0501 N1_V02S0501\narc: E1_H01E0001 W3_H06E0003\narc: N3_V06N0103 W3_H06E0103\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCLK1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JCE0MUX 1\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R37C27:CIB_EBR\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 V06S0303\narc: E3_H06E0003 JQ0\narc: E3_H06E0103 JQ1\narc: E3_H06E0203 JQ4\narc: H00R0000 H02E0601\narc: JA0 H00R0000\narc: JA2 H02W0501\narc: JA6 V00T0100\narc: JC1 S1_V02N0601\narc: JC3 H02E0401\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 JQ3\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 N3_V06S0303\narc: N3_V06N0103 JQ2\narc: V00T0100 S1_V02N0501\narc: H01W0000 W3_H06E0103\narc: N1_V02N0701 W3_H06E0203\narc: N3_V06N0303 W3_H06E0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C28:CIB_EBR\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0303 JQ6\narc: H00L0000 H02E0201\narc: H00L0100 W1_H02E0101\narc: H00R0000 H02E0601\narc: JA0 H02E0501\narc: JA1 H00L0000\narc: JA2 V00T0000\narc: JA3 H00L0100\narc: JA4 W1_H02E0701\narc: JA5 W1_H02E0501\narc: JCE1 H00R0000\narc: JCLK0 G_HPBX0000\narc: N1_V01N0001 JQ7\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 V01N0001\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 H06E0303\narc: N3_V06N0103 H06E0103\narc: V00T0000 H02E0001\narc: W1_H02W0501 V01N0101\narc: N1_V02N0701 W3_H06E0203\nenum: CIB.JB5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC3MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JB7MUX 0\n\n.tile CIB_R37C29:CIB_EBR\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 N1_V01S0100\narc: E3_H06E0003 JQ0\narc: E3_H06E0103 JQ2\narc: E3_H06E0303 JQ6\narc: H00L0000 V02N0001\narc: JA0 H00L0000\narc: JA2 H02E0501\narc: JA6 H02E0701\narc: JC1 H02E0601\narc: JC3 S1_V02N0601\narc: N1_V01N0001 JQ4\narc: N1_V02N0501 H06E0303\narc: N3_V06N0003 JQ3\narc: N3_V06N0103 JQ1\narc: N3_V06N0303 JQ5\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C30:CIB_EBR\narc: H00R0000 H02W0601\narc: JA0 H02E0501\narc: JA4 V02N0101\narc: JA6 V00T0100\narc: JC1 H02E0401\narc: JC5 V00T0000\narc: JC7 V02S0201\narc: JCE1 H00R0000\narc: JCLK0 G_HPBX0000\narc: N1_V02N0101 H06W0103\narc: N3_V06N0103 H06E0103\narc: V00T0000 N1_V02S0601\narc: V00T0100 W1_H02E0301\narc: N3_V06N0203 W3_H06E0203\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\n\n.tile CIB_R37C31:CIB_EBR\narc: N3_V06N0303 H06E0303\narc: W1_H02W0601 E3_H06W0303\narc: N1_V02N0001 W3_H06E0003\narc: W3_H06W0303 E3_H06W0303\n\n.tile CIB_R37C32:CIB_EBR\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 S1_V02N0601\narc: N1_V02N0001 H06E0003\narc: N1_V02N0501 H06E0303\narc: N3_V06N0103 H06E0103\narc: N1_V02N0701 W3_H06E0203\n\n.tile CIB_R37C33:CIB_EBR\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 V01N0001\narc: E3_H06E0203 N1_V01S0000\narc: JA0 V02N0701\narc: JA2 V00T0000\narc: JA6 V02S0301\narc: JC1 N1_V02S0601\narc: JC3 H02E0601\narc: N1_V01N0101 JQ6\narc: N1_V02N0201 JQ2\narc: N1_V02N0301 JQ3\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 JQ7\narc: N3_V06N0003 JQ0\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ5\narc: V00T0000 V02S0601\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0401 W3_H06E0203\narc: W3_H06W0103 JQ1\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C34:CIB_EBR\narc: E1_H02E0401 N1_V02S0401\narc: H00L0100 H02E0301\narc: H01W0000 JQ0\narc: JA0 H02W0501\narc: JA4 V00T0000\narc: JA6 W1_H02E0501\narc: JC1 H00L0100\narc: JC5 H02E0401\narc: JC7 V00T0100\narc: JCE1 H02E0101\narc: JCLK0 G_HPBX0000\narc: V00T0000 W1_H02E0001\narc: V00T0100 N1_V02S0701\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R37C35:CIB_EBR\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 E1_H02W0001\narc: JA0 V02N0501\narc: JA2 V00T0000\narc: JA6 V00T0100\narc: JC1 H00L0000\narc: JC3 S1_V02N0401\narc: N1_V01N0101 JQ6\narc: N1_V02N0101 JQ3\narc: N1_V02N0401 JQ4\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0103 JQ2\narc: N3_V06N0203 JQ7\narc: N3_V06N0303 JQ5\narc: V00T0000 W1_H02E0201\narc: V00T0100 N1_V02S0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0501 N1_V01S0100\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C36:CIB_EBR\narc: H00R0000 H02E0601\narc: H00R0100 H02W0501\narc: JA0 H00R0000\narc: JA4 H02E0501\narc: JA6 N1_V02S0301\narc: JC1 W1_H02E0401\narc: JC5 N1_V02S0001\narc: JC7 V02S0001\narc: JCE1 H00R0100\narc: JCLK0 G_HPBX0000\narc: N1_V02N0201 JQ2\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 JQ1\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\n\n.tile CIB_R37C37:CIB_EBR\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0701 N3_V06S0203\narc: N1_V02N0401 JQ6\narc: N1_V02N0701 JQ7\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ5\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 E1_H01W0000\narc: W3_H06W0303 E1_H02W0501\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCLK1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JCE0MUX 1\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R37C38:CIB_EBR\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0103 JQ1\narc: H00L0000 H02E0001\narc: H00R0000 H02E0401\narc: H01W0000 JQ0\narc: H01W0100 JQ4\narc: JA0 V02S0701\narc: JA2 V00T0000\narc: JA6 H00R0000\narc: JC1 H00L0000\narc: JC3 N1_V02S0401\narc: N3_V06N0003 JQ3\narc: N3_V06N0103 JQ2\narc: V00T0000 V02S0601\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C39:CIB_EBR\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0303 JQ6\narc: H00L0000 N1_V02S0201\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02S0401\narc: JA0 H00L0000\narc: JA1 H00R0000\narc: JA2 V00B0000\narc: JA3 H00L0100\narc: JA4 W1_H02E0701\narc: JA5 H02E0501\narc: JCE1 H02W0101\narc: JCLK0 G_HPBX0000\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 JQ7\narc: N1_V02N0001 H02E0001\narc: N1_V02N0401 E1_H02W0401\narc: V00B0000 V02S0201\narc: W1_H02W0501 V02S0501\narc: E1_H01E0101 W3_H06E0203\narc: E3_H06E0203 W3_H06E0203\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC3MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JB0MUX 0\n\n.tile CIB_R37C3:CIB_EBR\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0501 N1_V01S0100\n\n.tile CIB_R37C40:CIB_EBR\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0003 JQ0\narc: E3_H06E0103 JQ1\narc: E3_H06E0303 JQ5\narc: JA0 H02W0701\narc: JA2 V00T0000\narc: JA6 W1_H02E0701\narc: JC1 N1_V02S0601\narc: JC3 W1_H02E0401\narc: N3_V06N0003 JQ3\narc: N3_V06N0103 JQ2\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ6\narc: V00T0000 W1_H02E0201\narc: W1_H02W0101 H01E0101\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C41:CIB_EBR\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 S1_V02N0601\narc: JA0 V02S0701\narc: JA4 W1_H02E0701\narc: JA6 N1_V02S0301\narc: JC1 W1_H02E0601\narc: JC5 V00T0100\narc: JC7 W1_H02E0401\narc: JCE1 W1_H02E0101\narc: JCLK0 G_HPBX0000\narc: N1_V02N0001 N1_V01S0000\narc: N3_V06N0103 E1_H01W0100\narc: V00T0100 H02W0101\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0701 V02N0701\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\n\n.tile CIB_R37C42:CIB_EBR\narc: E1_H02E0101 N1_V02S0101\narc: E3_H06E0203 JQ7\narc: E3_H06E0303 JQ6\narc: H00R0000 V02S0401\narc: H00R0100 N1_V02S0501\narc: H01W0100 JQ3\narc: JA0 H00R0000\narc: JA1 H00R0000\narc: JA2 V02N0701\narc: JA3 V02N0701\narc: JA6 S1_V02N0301\narc: JA7 S1_V02N0301\narc: JB1 V02S0301\narc: JB3 H02W0101\narc: JB5 V02N0501\narc: JB7 H02W0301\narc: JC0 W1_H02E0601\narc: JC1 W1_H02E0601\narc: JC2 H00R0100\narc: JC3 H00R0100\narc: JCLK0 G_HPBX0000\narc: JD0 N1_V02S0201\narc: JD2 V00B0100\narc: JD4 V00B0000\narc: JD6 S1_V02N0601\narc: JLSR1 H02W0501\narc: N1_V02N0001 JQ2\narc: N1_V02N0501 N3_V06S0303\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 JQ1\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ5\narc: V00B0000 V02S0201\narc: V00B0100 V02N0101\narc: W1_H02W0101 N1_V02S0101\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C43:CIB_EBR\narc: E1_H02E0201 N3_V06S0103\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 W1_H02E0001\narc: H00L0100 H02E0101\narc: JA0 H02W0701\narc: JA1 H00L0000\narc: JA4 V00T0100\narc: JA5 H02W0701\narc: JA6 H00L0000\narc: JA7 V00T0100\narc: JC0 W1_H02E0601\narc: JC1 H00L0100\narc: JC4 V00B0100\narc: JC5 V02S0001\narc: JC6 V02S0001\narc: JC7 W1_H02E0601\narc: JCLK0 G_HPBX0000\narc: V00B0100 N1_V02S0101\narc: V00T0100 W1_H02E0101\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 V06S0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R37C44:CIB_EBR\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0003 JQ3\narc: E3_H06E0103 JQ2\narc: E3_H06E0203 JQ7\narc: E3_H06E0303 JQ6\narc: H00L0000 H02W0201\narc: H00R0000 N1_V02S0401\narc: JA0 H02W0701\narc: JA1 H02W0701\narc: JA2 V02N0701\narc: JA3 V02N0701\narc: JA6 H00R0000\narc: JA7 H00R0000\narc: JB3 V02N0301\narc: JB5 S1_V02N0701\narc: JB7 V02N0501\narc: JC0 N1_V01N0001\narc: JC1 N1_V02S0601\narc: JC2 H00L0000\narc: JC3 H00L0000\narc: JCLK0 G_HPBX0000\narc: JD2 V02S0001\narc: JD4 H02E0201\narc: JD6 V00B0000\narc: JLSR1 V00B0100\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0701 JQ5\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ6\narc: V00B0000 V02S0201\narc: V00B0100 V02N0101\narc: W1_H02W0701 V02N0701\narc: N3_V06N0103 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C45:CIB_EBR\narc: E1_H02E0301 V02S0301\narc: E1_H02E0701 S1_V02N0701\narc: H00R0000 V02S0401\narc: JA4 V00B0000\narc: JA5 V00B0000\narc: JA6 N1_V02S0301\narc: JA7 N1_V02S0301\narc: JB1 V02N0101\narc: JC4 V02N0001\narc: JC5 V02N0001\narc: JC6 V02S0001\narc: JC7 V02S0001\narc: JCLK0 G_HPBX0000\narc: JD0 H00R0000\narc: N1_V02N0401 N3_V06S0203\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 JQ1\narc: N3_V06N0203 H06E0203\narc: V00B0000 H02E0601\narc: V01S0100 N3_V06S0303\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0701 S1_V02N0701\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\n\n.tile CIB_R37C46:CIB_EBR\narc: E1_H02E0301 V06S0003\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0303 JQ5\narc: H00L0000 V02N0001\narc: JB5 H00L0000\narc: JB7 H02E0301\narc: JD4 N1_V02S0401\narc: JD6 V00B0000\narc: N1_V02N0601 JQ6\narc: N1_V02N0701 JQ7\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 E1_H01W0100\narc: V00B0000 V02S0001\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JCE0MUX 1\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCLK1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C47:CIB_EBR\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 V06S0203\narc: E1_H02E0701 N1_V02S0701\narc: H00R0000 V02S0401\narc: H00R0100 V02N0701\narc: H01W0100 JQ3\narc: JA0 W1_H02E0701\narc: JA1 W1_H02E0701\narc: JA2 H02W0501\narc: JA3 H02W0501\narc: JA6 H02E0501\narc: JA7 H02E0501\narc: JB1 H00R0100\narc: JB3 H02E0301\narc: JC0 V02N0401\narc: JC1 V02N0401\narc: JC2 N1_V02S0601\narc: JC3 N1_V02S0601\narc: JCLK0 G_HPBX0000\narc: JD0 H00R0000\narc: JD2 V00T0100\narc: JLSR1 V00B0100\narc: N1_V02N0001 JQ0\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 JQ2\narc: N1_V02N0301 JQ1\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 E3_H06W0303\narc: V00B0100 N1_V02S0301\narc: V00T0100 V02N0501\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C48:CIB_EBR\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 N3_V06S0303\narc: H00L0000 V02N0001\narc: H00L0100 H02E0301\narc: H00R0000 N1_V02S0601\narc: JA0 H00L0000\narc: JA1 H00R0000\narc: JA2 W1_H02E0701\narc: JA3 H00L0100\narc: JC0 H00L0000\narc: JC1 N1_V02S0601\narc: JC2 E1_H02W0601\narc: JC3 H00L0100\narc: JCLK0 G_HPBX0000\narc: JD6 V02S0601\narc: JD7 H02W0001\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 JQ6\narc: N1_V02N0701 JQ7\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 E1_H01W0100\narc: W1_H02W0501 N3_V06S0303\narc: N1_V02N0501 W3_H06E0303\nenum: CIB.JB5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB7MUX 0\n\n.tile CIB_R37C49:CIB_EBR\narc: H00L0000 N1_V02S0201\narc: H01W0000 JQ3\narc: H01W0100 JQ2\narc: JA0 V02N0501\narc: JA1 V02N0501\narc: JA2 V00B0000\narc: JA3 V00B0000\narc: JA6 W1_H02E0701\narc: JA7 W1_H02E0701\narc: JB1 H02E0101\narc: JB3 S1_V02N0101\narc: JB5 V02S0701\narc: JC0 W1_H02E0401\narc: JC1 W1_H02E0401\narc: JC2 H00L0000\narc: JC3 H00L0000\narc: JCLK0 G_HPBX0000\narc: JD0 V02S0201\narc: JD2 V00B0100\narc: JD4 V02S0401\narc: JLSR1 V00T0000\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 JQ1\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ5\narc: V00B0000 H02E0601\narc: V00B0100 H02E0501\narc: V00T0000 H02E0201\narc: W1_H02W0001 N1_V01S0000\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0203 E3_H06W0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C4:CIB_EBR\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0601 N3_V06S0303\n\n.tile CIB_R37C50:CIB_EBR\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 N1_V02S0701\narc: JA4 V00T0000\narc: JA5 V00T0000\narc: JA6 N1_V01S0100\narc: JA7 N1_V01S0100\narc: JC4 V02S0001\narc: JC5 V02S0001\narc: JC6 V02N0001\narc: JC7 V02N0001\narc: JCLK0 G_HPBX0000\narc: N1_V02N0101 E3_H06W0103\narc: N3_V06N0103 H06W0103\narc: V00T0000 N1_V02S0601\narc: V01S0000 N3_V06S0103\narc: W1_H02W0601 S1_V02N0601\narc: N3_V06N0003 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\n\n.tile CIB_R37C51:CIB_EBR\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 V02N0701\narc: E3_H06E0103 JQ1\narc: E3_H06E0203 JQ7\narc: H00L0100 N1_V02S0101\narc: H00R0000 V02S0401\narc: H00R0100 N1_V02S0701\narc: JA0 V02S0701\narc: JA1 V02S0701\narc: JA2 V02N0701\narc: JA3 V02N0701\narc: JA6 H02E0701\narc: JA7 H02E0701\narc: JB1 H02W0301\narc: JB3 V02N0301\narc: JB5 V02S0501\narc: JB7 V00B0100\narc: JC0 H02E0601\narc: JC1 H02E0601\narc: JC2 H00L0100\narc: JC3 H00L0100\narc: JCLK0 G_HPBX0000\narc: JD0 S1_V02N0001\narc: JD2 H00R0000\narc: JD4 V00B0000\narc: JD6 H00R0100\narc: JLSR1 V00T0100\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 JQ3\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 JQ5\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 JQ2\narc: N3_V06N0203 JQ4\narc: N3_V06N0303 JQ6\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: V00T0100 H02E0101\narc: W1_H02W0201 E3_H06W0103\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C52:CIB_EBR\narc: E1_H02E0101 V06S0103\narc: H00R0000 N1_V02S0601\narc: JA0 H00R0000\narc: JA4 W1_H02E0501\narc: JA5 V00T0000\narc: JA7 W1_H02E0501\narc: JC1 H02E0601\narc: JC4 H02E0601\narc: JC5 W1_H02E0401\narc: JC6 W1_H02E0401\narc: JCLK0 G_HPBX0000\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0601 E3_H06W0303\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0203 E3_H06W0203\narc: V00T0000 N1_V02S0601\narc: W1_H02W0301 N3_V06S0003\narc: E1_H02E0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R37C53:CIB_EBR\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0501 N1_V01S0100\narc: H00L0100 V02S0301\narc: H00R0000 N1_V02S0601\narc: H00R0100 N1_V02S0501\narc: H01W0000 JQ4\narc: JA0 V02S0501\narc: JA1 V02S0501\narc: JA2 W1_H02E0701\narc: JA3 W1_H02E0701\narc: JA6 H00R0000\narc: JA7 H00R0000\narc: JB3 E1_H02W0301\narc: JB5 H02E0101\narc: JB7 N1_V01S0000\narc: JC0 V02N0401\narc: JC1 V02N0401\narc: JC2 N1_V02S0401\narc: JC3 N1_V02S0401\narc: JCLK0 G_HPBX0000\narc: JD2 S1_V02N0001\narc: JD4 H00L0100\narc: JD6 H00R0100\narc: JLSR1 V00T0000\narc: N1_V01N0101 N3_V06S0203\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0203 JQ7\narc: N3_V06N0303 JQ6\narc: V00T0000 V02S0401\narc: V01S0000 N3_V06S0103\narc: W3_H06W0003 JQ3\narc: W3_H06W0103 JQ2\narc: W3_H06W0203 JQ4\narc: W3_H06W0303 JQ5\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C54:CIB_EBR\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 V02S0301\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0103 N3_V06S0103\narc: H00R0100 V02S0701\narc: JA4 V00T0100\narc: JA5 V00T0100\narc: JA6 H02E0501\narc: JA7 H02E0501\narc: JB1 H00R0100\narc: JC4 V02S0201\narc: JC5 V02S0201\narc: JC6 V00T0000\narc: JC7 V00T0000\narc: JCLK0 G_HPBX0000\narc: JD0 V00B0100\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0301 H06W0003\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 H06E0203\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02E0001\narc: V00T0100 V02N0501\narc: V01S0000 N3_V06S0103\narc: W3_H06W0003 JQ0\narc: W3_H06W0103 JQ1\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\n\n.tile CIB_R37C55:CIB_EBR\narc: E1_H02E0201 V02N0201\narc: E1_H02E0501 N1_V02S0501\narc: H00L0100 H02E0301\narc: JB5 H02W0101\narc: JB7 V00B0000\narc: JD4 H00L0100\narc: JD6 H02W0001\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0201 N3_V06S0103\narc: N3_V06N0203 JQ7\narc: N3_V06N0303 JQ5\narc: V00B0000 V02S0001\narc: W1_H02W0301 V02S0301\narc: W3_H06W0203 JQ4\narc: W3_H06W0303 JQ6\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCLK1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JCE0MUX 1\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R37C56:CIB_EBR\narc: E1_H02E0101 V02N0101\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 N1_V02S0501\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02N0301\narc: JA0 H00L0100\narc: JA1 H00L0100\narc: JA2 H02W0501\narc: JA3 H02W0501\narc: JA6 H02E0501\narc: JA7 H02E0501\narc: JB1 V00B0000\narc: JB3 N1_V02S0301\narc: JC0 V02N0401\narc: JC1 V02N0401\narc: JC2 H00L0000\narc: JC3 H00L0000\narc: JCLK0 G_HPBX0000\narc: JD0 W1_H02E0001\narc: JD2 H02E0201\narc: JLSR1 V00B0100\narc: N1_V02N0201 N3_V06S0103\narc: N3_V06N0003 JQ0\narc: N3_V06N0103 JQ1\narc: V00B0000 W1_H02E0601\narc: V00B0100 V02S0101\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 N1_V02S0101\narc: W3_H06W0003 JQ3\narc: W3_H06W0103 JQ2\narc: W3_H06W0303 E3_H06W0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C57:CIB_EBR\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 V02S0701\narc: H00L0000 V02S0001\narc: H00R0000 H02E0401\narc: H00R0100 V02S0501\narc: JA0 H00R0000\narc: JA1 V02S0501\narc: JA2 V02N0701\narc: JA3 V00T0000\narc: JC0 H02E0401\narc: JC1 H00R0100\narc: JC2 E1_H02W0601\narc: JC3 H00L0000\narc: JCLK0 G_HPBX0000\narc: JD6 V00B0000\narc: JD7 V02S0601\narc: N3_V06N0303 JQ6\narc: V00B0000 N1_V02S0001\narc: V00T0000 H02W0001\narc: W1_H02W0501 N1_V01S0100\narc: E1_H01E0001 W3_H06E0003\narc: W3_H06W0203 JQ7\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JA5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JB0MUX 0\n\n.tile CIB_R37C58:CIB_EBR\narc: E1_H02E0401 N1_V02S0401\narc: H00R0000 H02E0401\narc: H00R0100 V02S0501\narc: JA0 W1_H02E0501\narc: JA1 W1_H02E0501\narc: JA2 H02E0701\narc: JA3 V02S0701\narc: JA6 S1_V02N0101\narc: JA7 S1_V02N0101\narc: JB1 H00R0100\narc: JB3 W1_H02E0101\narc: JB5 V02N0501\narc: JC0 H02E0601\narc: JC1 H02E0601\narc: JC2 H02W0401\narc: JC3 H02W0401\narc: JCLK0 G_HPBX0000\narc: JD0 H00R0000\narc: JD2 H02E0201\narc: JD4 V00B0000\narc: JLSR1 V00B0100\narc: N1_V02N0001 H01E0001\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0003 JQ3\narc: N3_V06N0103 JQ2\narc: S1_V02S0101 N3_V06S0103\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: W1_H02W0001 V02S0001\narc: E1_H02E0001 W3_H06E0003\narc: W3_H06W0003 JQ0\narc: W3_H06W0103 JQ1\narc: W3_H06W0203 JQ4\narc: W3_H06W0303 JQ5\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C59:CIB_EBR\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 N1_V02S0001\narc: H00R0000 N1_V02S0401\narc: JA0 H00R0000\narc: JA1 H00R0000\narc: JA4 V00T0000\narc: JA5 V00T0000\narc: JA6 V02S0301\narc: JA7 V02S0301\narc: JC0 H00L0000\narc: JC1 H00L0000\narc: JC4 H02E0401\narc: JC5 H02E0401\narc: JC6 V02S0001\narc: JC7 V02S0001\narc: JCLK0 G_HPBX0000\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0303 E3_H06W0303\narc: V00T0000 W1_H02E0001\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E1_H01W0000\narc: W3_H06W0003 E3_H06W0303\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\n\n.tile CIB_R37C60:CIB_EBR\narc: E1_H01E0101 JQ6\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0401 N1_V02S0401\narc: H00L0000 V02S0201\narc: H00L0100 V02N0101\narc: H00R0000 H02E0601\narc: H01W0100 JQ0\narc: JA0 H00R0000\narc: JA2 H00L0100\narc: JA6 H02W0701\narc: JC1 H00L0000\narc: JC3 H02E0401\narc: N1_V01N0001 JQ5\narc: N1_V01N0101 JQ2\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 JQ4\narc: N1_V02N0501 JQ7\narc: N1_V02N0601 H01E0001\narc: W1_H02W0101 JQ1\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 E3_H06W0303\narc: H01W0000 W3_H06E0103\narc: W3_H06W0003 JQ3\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C61:CIB_EBR\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 H02E0001\narc: H00R0000 V02S0401\narc: JA0 H00L0000\narc: JA4 N1_V02S0101\narc: JA6 V02S0301\narc: JC1 H02E0401\narc: JC5 N1_V02S0201\narc: JC7 N1_V02S0001\narc: JCE1 H00R0000\narc: JCLK0 G_HPBX0000\narc: N1_V01N0001 JQ0\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H01E0101\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0101 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R37C62:CIB_EBR\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 N1_V02S0701\narc: H00L0100 V02S0101\narc: H01W0000 JQ2\narc: H01W0100 JQ3\narc: JA0 N1_V02S0501\narc: JA2 V00B0000\narc: JA6 V00T0100\narc: JC1 H00L0100\narc: JC3 S1_V02N0601\narc: N1_V01N0001 JQ4\narc: N1_V01N0101 JQ7\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 JQ6\narc: N1_V02N0701 H02E0701\narc: V00B0000 V02N0201\narc: V00T0100 S1_V02N0701\narc: W3_H06W0303 JQ5\nenum: CIB.JB3MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\n\n.tile CIB_R37C63:CIB_EBR\narc: E1_H02E0101 N3_V06S0103\narc: H00L0000 H02E0001\narc: H01W0100 JQ2\narc: JA0 H00L0000\narc: JA4 V00T0000\narc: JA6 H02E0701\narc: JC1 H02E0401\narc: JC5 N1_V02S0201\narc: JC7 H02E0601\narc: JCE1 W1_H02E0101\narc: JCLK0 G_HPBX0000\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 H06W0103\narc: V00T0000 V02N0601\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 JQ0\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 JQ1\narc: E3_H06E0103 W3_H06E0003\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\n\n.tile CIB_R37C64:CIB_EBR\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 N1_V02S0701\narc: H01W0000 JQ7\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 JQ5\narc: W1_H02W0401 JQ6\narc: W3_H06W0203 JQ4\nenum: CIB.JLSR1MUX 0\nenum: CIB.JCLK1MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB5MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JCE0MUX 1\nenum: CIB.JB2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R37C65:CIB_EBR\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 S1_V02N0601\narc: H01W0100 JQ4\narc: JA0 N1_V02S0501\narc: JA2 V00B0000\narc: JA6 N1_V02S0101\narc: JC1 H02E0601\narc: JC3 S1_V02N0601\narc: N1_V01N0101 JQ2\narc: N1_V02N0201 JQ0\narc: V00B0000 V02N0201\narc: W1_H02W0401 E1_H02W0401\narc: W3_H06W0003 JQ3\narc: W3_H06W0103 JQ1\narc: W3_H06W0303 E3_H06W0203\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C66:CIB_EBR\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0701 V02N0701\narc: H00L0000 N1_V02S0201\narc: H00L0100 N1_V02S0101\narc: H00R0000 H02E0401\narc: JA0 H00L0000\narc: JA1 H00R0000\narc: JA2 S1_V02N0501\narc: JA3 H00L0100\narc: JA4 W1_H02E0701\narc: JA5 V02S0101\narc: JCE1 H02E0101\narc: JCLK0 G_HPBX0000\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 JQ7\narc: W3_H06W0303 JQ6\nenum: CIB.JB5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC3MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JD7MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JB7MUX 0\n\n.tile CIB_R37C67:CIB_EBR\narc: H01W0000 JQ4\narc: H01W0100 JQ2\narc: JA0 W1_H02E0501\narc: JA2 H02E0701\narc: JA6 S1_V02N0101\narc: JC1 S1_V02N0601\narc: JC3 W1_H02E0601\narc: N1_V02N0201 JQ0\narc: W1_H02W0401 JQ6\narc: W3_H06W0003 JQ3\narc: W3_H06W0103 JQ1\narc: W3_H06W0303 JQ5\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JCLK0MUX 0\nenum: CIB.JCE1MUX 1\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC7MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR0MUX 0\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB6MUX 0\n\n.tile CIB_R37C68:CIB_EBR\narc: H00L0000 V02S0201\narc: H00R0000 N1_V02S0601\narc: JA0 H00L0000\narc: JA4 V00T0100\narc: JA6 H00R0000\narc: JC1 N1_V02S0401\narc: JC5 V00T0000\narc: JC7 W1_H02E0401\narc: JCE1 H02W0101\narc: JCLK0 G_HPBX0000\narc: V00T0000 W1_H02E0201\narc: V00T0100 W1_H02E0101\nenum: CIB.JCE3MUX 1\nenum: CIB.JCE2MUX 1\nenum: CIB.JB6MUX 0\nenum: CIB.JD7MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JD5MUX 0\nenum: CIB.JB2MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JLSR0MUX 0\nenum: CIB.JA1MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD6MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JCE0MUX 1\nenum: CIB.JLSR1MUX 0\nenum: CIB.JD1MUX 0\nenum: CIB.JB0MUX 0\nenum: CIB.JD3MUX 0\n\n.tile CIB_R37C69:CIB_EBR\narc: E1_H02E0101 N3_V06S0103\narc: N1_V02N0101 N3_V06S0103\narc: W1_H02W0101 W3_H06E0103\n\n.tile CIB_R37C71:CIB_LR_S\narc: JA3 N1_V02S0501\narc: JB3 W1_H02E0101\narc: JCLK1 G_HPBX0000\narc: JLSR1 V00B0100\narc: V00B0100 V02S0101\narc: W3_H06W0203 JQ4\n\n.tile CIB_R37C8:CIB_EBR\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 N3_V06S0103\n\n.tile CIB_R38C1:CIB_LR\narc: S3_V06S0203 N3_V06S0203\n\n.tile CIB_R38C71:CIB_LR\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0701 N3_V06S0203\n\n.tile CIB_R3C1:CIB_LR\narc: E1_H02E0101 V02N0101\narc: E1_H02E0701 S1_V02N0701\n\n.tile CIB_R3C71:CIB_LR\narc: N1_V02N0201 H02E0201\narc: S1_V02S0201 H02E0201\n\n.tile CIB_R40C1:CIB_LR\narc: JA0 E1_H02W0701\nenum: CIB.JB0MUX 0\n\n.tile CIB_R40C71:CIB_LR\narc: JA0 H02E0501\narc: JA3 N1_V02S0701\narc: JC0 N1_V02S0401\narc: JCLK0 G_HPBX0100\narc: JCLK1 G_HPBX0000\narc: JLSR1 H02E0301\nenum: CIB.JB3MUX 0\nenum: CIB.JB0MUX 0\n\n.tile CIB_R41C1:CIB_LR\narc: JA3 H02W0701\nenum: CIB.JB3MUX 0\n\n.tile CIB_R41C71:CIB_LR\narc: JA3 V00T0000\narc: JCLK1 G_HPBX0000\narc: JLSR1 V00B0000\narc: V00B0000 V02N0201\narc: V00T0000 H02E0001\nenum: CIB.JB3MUX 0\n\n.tile CIB_R42C71:CIB_LR\narc: N1_V02N0201 H02E0201\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 W1_H02E0301\n\n.tile CIB_R43C1:CIB_LR\narc: JA0 V02N0701\nenum: CIB.JB0MUX 0\n\n.tile CIB_R43C71:CIB_LR\narc: JA0 H02E0701\narc: JA3 V00T0000\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 V00B0000\narc: JLSR1 V00B0000\narc: V00B0000 V02S0201\narc: V00T0000 W1_H02E0201\nenum: CIB.JB3MUX 0\nenum: CIB.JB0MUX 0\n\n.tile CIB_R44C1:CIB_LR\narc: JA0 H02W0501\narc: N1_V02N0701 N3_V06S0203\nenum: CIB.JB0MUX 0\n\n.tile CIB_R44C71:CIB_LR\narc: H00L0100 N1_V02S0301\narc: JA0 W1_H02E0501\narc: JA3 H00L0100\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 V00T0100\narc: JLSR1 V00T0100\narc: V00T0100 H02E0101\nenum: CIB.JB3MUX 0\nenum: CIB.JB0MUX 0\n\n.tile CIB_R49C2:CIB_PLL2\narc: JB1 H02W0101\narc: N3_V06N0103 JQ2\narc: PLLCSOUT_PLLREFCS CLK1_PLLREFCS\n\n.tile CIB_R49C3:CIB_PLL3\narc: W1_H02W0101 N1_V02S0101\nenum: CIB.JA3MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R49C42:VCIB_DCU0\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C43:VCIB_DCUA\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C44:VCIB_DCUB\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C45:VCIB_DCUC\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C46:VCIB_DCUD\nenum: CIB.JA1MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C47:VCIB_DCUF\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C48:VCIB_DCU3\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C49:VCIB_DCU2\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C50:VCIB_DCUG\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C51:VCIB_DCUH\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C52:VCIB_DCUI\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C53:VCIB_DCU1\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\n\n.tile CIB_R49C69:CIB_PLL3\nenum: CIB.JA3MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R49C6:CIB_EFB0\nenum: CIB.JB3MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C7:CIB_EFB1\nenum: CIB.JA3MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JC3MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\n\n.tile CIB_R4C1:CIB_LR\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0701 V02N0701\narc: N1_V02N0101 E3_H06W0103\n\n.tile CIB_R4C71:CIB_LR\narc: H00R0100 H02E0501\narc: JA3 H02E0701\narc: JB3 H00R0100\narc: JCLK1 G_HPBX0000\narc: JLSR1 V00B0000\narc: N1_V02N0301 H06E0003\narc: V00B0000 V02S0201\narc: S3_V06S0003 W3_H06E0003\narc: W3_H06W0203 JQ4\n\n.tile CIB_R5C1:CIB_LR\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 E1_H01W0100\narc: N1_V02N0701 S1_V02N0701\n\n.tile CIB_R5C71:CIB_LR\narc: H00L0000 V02N0001\narc: H00L0100 V02N0301\narc: H00R0100 W1_H02E0501\narc: JA0 H00L0000\narc: JA3 H00L0100\narc: JB3 H00R0100\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 V00B0100\narc: JLSR1 V00B0000\narc: S3_V06S0003 H06E0003\narc: V00B0000 H02E0601\narc: V00B0100 V02N0101\narc: W3_H06W0203 JQ4\nenum: CIB.JB0MUX 0\n\n.tile CIB_R6C1:CIB_LR\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0601 E3_H06W0303\n\n.tile CIB_R6C71:CIB_LR\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 H02E0101\narc: S3_V06S0103 H06E0103\narc: W1_H02W0601 S1_V02N0601\narc: N1_V02N0301 W3_H06E0003\n\n.tile CIB_R7C1:CIB_LR\narc: N1_V02N0701 E3_H06W0203\narc: S3_V06S0203 E3_H06W0203\n\n.tile CIB_R7C71:CIB_LR\narc: S3_V06S0003 H06E0003\narc: W3_H06W0203 S3_V06N0203\n\n.tile CIB_R8C1:CIB_LR\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 S1_V02N0601\n\n.tile CIB_R8C71:CIB_LR\narc: H00L0100 W1_H02E0101\narc: JA0 H00L0100\narc: JA3 H02E0701\narc: JB0 H02E0101\narc: JB3 H02E0101\narc: JCLK0 G_HPBX0000\narc: JCLK1 G_HPBX0000\narc: JLSR0 H02E0301\narc: JLSR1 H02E0301\narc: N1_V02N0001 H06E0003\narc: N1_V02N0601 JQ4\narc: S3_V06S0003 H06E0003\narc: W3_H06W0203 JF4\n\n.tile CIB_R9C1:CIB_LR\narc: E1_H02E0601 V02N0601\n\n.tile CIB_R9C71:CIB_LR\narc: S1_V02S0401 V01N0001\narc: S3_V06S0303 H06E0303\n\n.tile MIB_R0C38:PIOT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R0C42:PIOT0\nenum: PIOA.BASE_TYPE INPUT_LVCMOS33\nenum: PIOA.HYSTERESIS ON\n\n.tile MIB_R0C49:PIOT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R0C53:PIOT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R0C54:PIOT1\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R0C56:PIOT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\n\n.tile MIB_R0C60:PIOT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\n\n.tile MIB_R0C65:PIOT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\n\n.tile MIB_R0C66:PIOT1\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\n\n.tile MIB_R0C67:PIOT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\n\n.tile MIB_R0C68:PIOT1\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\n\n.tile MIB_R0C69:BANKREF1\nenum: BANK.VCCIO 3V3\n\n.tile MIB_R11C72:PICR0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R12C72:PICR1\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE UP\nenum: PIOD.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOD.HYSTERESIS ON\nenum: PIOD.SLEWRATE FAST\nenum: PIOD.PULLMODE NONE\nenum: PIOD.DRIVE 4\nenum: PIOC.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOC.HYSTERESIS ON\nenum: PIOC.SLEWRATE FAST\nenum: PIOC.PULLMODE NONE\nenum: PIOC.DRIVE 4\n\n.tile MIB_R13C21:DSP_SPINE_UL0\narc: G_VPTX0000 G_HPRX0000\n\n.tile MIB_R13C31:CMUX_UL_0\narc: G_DCS0CLK0 G_VPFN0000\narc: G_ULPCLK0 G_HPFE0300\narc: G_ULPCLK1 G_HPFE0600\n\n.tile MIB_R13C32:CMUX_UR_0\narc: G_DCS0CLK1 G_VPFN0000\narc: G_URPCLK0 G_HPFE0300\narc: G_URPCLK1 G_HPFE0600\n\n.tile MIB_R13C3:DSP_SPINE_UL1\narc: G_VPTX0000 G_HPRX0000\nunknown: F2B0\nunknown: F3B0\nunknown: F5B0\nunknown: F11B0\nunknown: F13B0\n\n.tile MIB_R13C41:DSP_SPINE_UR0\narc: G_VPTX0000 G_HPRX0000\n\n.tile MIB_R13C51:MIB_DSP0\narc: JMULTA0 JMUIA0\narc: JMULTA1 JMUIA1\narc: JMULTA10 JMUIA10\narc: JMULTA11 JMUIA11\narc: JMULTA12 JMUIA12\narc: JMULTA13 JMUIA13\narc: JMULTA14 JMUIA14\narc: JMULTA15 JMUIA15\narc: JMULTA2 JMUIA2\narc: JMULTA3 JMUIA3\narc: JMULTA4 JMUIA4\narc: JMULTA5 JMUIA5\narc: JMULTA6 JMUIA6\narc: JMULTA7 JMUIA7\narc: JMULTA8 JMUIA8\narc: JMULTA9 JMUIA9\n\n.tile MIB_R13C59:DSP_SPINE_UR1\narc: G_VPTX0000 G_HPRX0000\n\n.tile MIB_R13C72:MIB_CIB_LR_A\nword: IOLOGICD.DELAY.DEL_VALUE 0000000\nword: IOLOGICC.DELAY.DEL_VALUE 0000000\nenum: IOLOGICD.OUTREG.REGSET SET\nenum: IOLOGICD.OUTREG.OUTREGMODE FF\nenum: IOLOGICD.CEOMUX CEMUX\nenum: IOLOGICD.SRMODE ASYNC\nenum: IOLOGICD.FF.REGSET SET\nenum: IOLOGICD.FF.INREGMODE FF\nenum: IOLOGICD.CEMUX CE\nenum: IOLOGICD.CEIMUX CEMUX\nenum: IOLOGICD.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICD.MTDDRX.REGSET RESET\nenum: IOLOGICD.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICD.LSROMUX LSRMUX\nenum: IOLOGICD.LSRIMUX LSRMUX\nenum: IOLOGICD.CLKOMUX CLK\nenum: IOLOGICD.GSR ENABLED\nenum: IOLOGICD.LSRMUX LSR\nenum: IOLOGICD.CLKIMUX CLK\nenum: IOLOGICD.MODE IREG_OREG\nenum: IOLOGICD.DELAY.OUTDEL DISABLED\nenum: IOLOGICD.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICD.IDDRXN.MODE NONE\nenum: IOLOGICD.ODDRXN.MODE NONE\nenum: IOLOGICD.MIDDRX.MODE NONE\nenum: IOLOGICD.MODDRX.MODE NONE\nenum: IOLOGICD.MTDDRX.MODE NONE\nenum: IOLOGICD.IOLTOMUX NONE\nenum: IOLOGICC.OUTREG.REGSET SET\nenum: IOLOGICC.OUTREG.OUTREGMODE FF\nenum: IOLOGICC.CEOMUX CEMUX\nenum: IOLOGICC.SRMODE ASYNC\nenum: IOLOGICC.FF.REGSET SET\nenum: IOLOGICC.FF.INREGMODE FF\nenum: IOLOGICC.CEMUX CE\nenum: IOLOGICC.CEIMUX CEMUX\nenum: IOLOGICC.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICC.MTDDRX.REGSET RESET\nenum: IOLOGICC.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICC.LSROMUX LSRMUX\nenum: IOLOGICC.LSRIMUX LSRMUX\nenum: IOLOGICC.CLKOMUX CLK\nenum: IOLOGICC.GSR ENABLED\nenum: IOLOGICC.LSRMUX LSR\nenum: IOLOGICC.CLKIMUX CLK\nenum: IOLOGICC.MODE IREG_OREG\nenum: IOLOGICC.DELAY.OUTDEL DISABLED\nenum: IOLOGICC.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICC.IDDRXN.MODE NONE\nenum: IOLOGICC.ODDRXN.MODE NONE\nenum: IOLOGICC.MIDDRX.MODE NONE\nenum: IOLOGICC.MODDRX.MODE NONE\nenum: IOLOGICC.MTDDRX.MODE NONE\nenum: IOLOGICC.IOLTOMUX NONE\nenum: PIOD.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOD.DATAMUX_OREG IOLDO\nenum: PIOC.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOC.DATAMUX_OREG IOLDO\n\n.tile MIB_R14C72:PICR0\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.FF.REGSET SET\nenum: IOLOGICA.FF.INREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEIMUX CEMUX\nenum: IOLOGICA.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICA.MTDDRX.REGSET RESET\nenum: IOLOGICA.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICA.LSROMUX LSRMUX\nenum: IOLOGICA.LSRIMUX LSRMUX\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.IDDRXN.MODE NONE\nenum: IOLOGICA.ODDRXN.MODE NONE\nenum: IOLOGICA.MIDDRX.MODE NONE\nenum: IOLOGICA.MODDRX.MODE NONE\nenum: IOLOGICA.MTDDRX.MODE NONE\nenum: IOLOGICA.IOLTOMUX NONE\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\nenum: PIOA.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICB.MTDDRX.REGSET RESET\nenum: IOLOGICB.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICB.LSROMUX LSRMUX\nenum: IOLOGICB.LSRIMUX 0\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.IDDRXN.MODE NONE\nenum: IOLOGICB.ODDRXN.MODE NONE\nenum: IOLOGICB.MIDDRX.MODE NONE\nenum: IOLOGICB.MODDRX.MODE NONE\nenum: IOLOGICB.MTDDRX.MODE NONE\nenum: IOLOGICB.IOLTOMUX NONE\n\n.tile MIB_R15C72:PICR1\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\nenum: PIOA.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOA.HYSTERESIS ON\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\n\n.tile MIB_R17C72:PICR0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R18C72:PICR1_DQS0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE UP\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOD.SLEWRATE FAST\n\n.tile MIB_R19C72:PICR2_DQS1\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R1C38:PICT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R1C42:PICT0\nenum: PIOA.BASE_TYPE INPUT_LVCMOS33\n\n.tile MIB_R1C49:PICT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R1C53:PICT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R1C54:PICT1\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R1C56:PICT0\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.LSRIMUX 0\nenum: IOLOGICA.LSROMUX LSRMUX\n\n.tile MIB_R1C60:PICT0\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.LSRIMUX 0\nenum: IOLOGICA.LSROMUX LSRMUX\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\n\n.tile MIB_R1C65:PICT0\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.LSRIMUX 0\nenum: IOLOGICA.LSROMUX LSRMUX\n\n.tile MIB_R1C66:PICT1\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.LSRIMUX 0\nenum: IOLOGICB.LSROMUX LSRMUX\n\n.tile MIB_R1C67:PICT0\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.LSRIMUX 0\nenum: IOLOGICA.LSROMUX LSRMUX\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\n\n.tile MIB_R1C68:PICT1\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.LSRIMUX 0\nenum: IOLOGICB.LSROMUX LSRMUX\n\n.tile MIB_R1C72:BANKREF2A\nenum: BANK.VCCIO 3V3\n\n.tile MIB_R20C72:PICR0_DQS2\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICB.MTDDRX.REGSET RESET\nenum: IOLOGICB.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICB.LSROMUX LSRMUX\nenum: IOLOGICB.LSRIMUX 0\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.IDDRXN.MODE NONE\nenum: IOLOGICB.ODDRXN.MODE NONE\nenum: IOLOGICB.MIDDRX.MODE NONE\nenum: IOLOGICB.MODDRX.MODE NONE\nenum: IOLOGICB.MTDDRX.MODE NONE\nenum: IOLOGICB.IOLTOMUX NONE\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICA.MTDDRX.REGSET RESET\nenum: IOLOGICA.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICA.LSROMUX LSRMUX\nenum: IOLOGICA.LSRIMUX 0\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.IDDRXN.MODE NONE\nenum: IOLOGICA.ODDRXN.MODE NONE\nenum: IOLOGICA.MIDDRX.MODE NONE\nenum: IOLOGICA.MODDRX.MODE NONE\nenum: IOLOGICA.MTDDRX.MODE NONE\nenum: IOLOGICA.IOLTOMUX NONE\n\n.tile MIB_R21C72:PICR1_DQS3\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\n\n.tile MIB_R23C72:PICR0\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICB.MTDDRX.REGSET RESET\nenum: IOLOGICB.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICB.LSROMUX LSRMUX\nenum: IOLOGICB.LSRIMUX 0\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.IDDRXN.MODE NONE\nenum: IOLOGICB.ODDRXN.MODE NONE\nenum: IOLOGICB.MIDDRX.MODE NONE\nenum: IOLOGICB.MODDRX.MODE NONE\nenum: IOLOGICB.MTDDRX.MODE NONE\nenum: IOLOGICB.IOLTOMUX NONE\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICA.MTDDRX.REGSET RESET\nenum: IOLOGICA.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICA.LSROMUX LSRMUX\nenum: IOLOGICA.LSRIMUX 0\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.IDDRXN.MODE NONE\nenum: IOLOGICA.ODDRXN.MODE NONE\nenum: IOLOGICA.MIDDRX.MODE NONE\nenum: IOLOGICA.MODDRX.MODE NONE\nenum: IOLOGICA.MTDDRX.MODE NONE\nenum: IOLOGICA.IOLTOMUX NONE\n\n.tile MIB_R24C72:PICR1\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOD.SLEWRATE FAST\nenum: PIOD.PULLMODE NONE\nenum: PIOD.DRIVE 4\nenum: PIOC.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOC.SLEWRATE FAST\nenum: PIOC.PULLMODE NONE\nenum: PIOC.DRIVE 4\n\n.tile MIB_R25C3:LMID_0\narc: G_LDCC3CLKI G_JLLCPLL0CLKOP\narc: G_LDCC6CLKI G_JLLCPLL0CLKOS\n\n.tile MIB_R25C72:MIB_CIB_LR_A\nword: IOLOGICC.DELAY.DEL_VALUE 0000000\nword: IOLOGICD.DELAY.DEL_VALUE 0000000\nenum: IOLOGICC.SRMODE ASYNC\nenum: IOLOGICC.OUTREG.REGSET SET\nenum: IOLOGICC.OUTREG.OUTREGMODE FF\nenum: IOLOGICC.CEMUX CE\nenum: IOLOGICC.CEOMUX CEMUX\nenum: IOLOGICC.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICC.MTDDRX.REGSET RESET\nenum: IOLOGICC.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICC.LSROMUX LSRMUX\nenum: IOLOGICC.LSRIMUX 0\nenum: IOLOGICC.CLKOMUX CLK\nenum: IOLOGICC.GSR ENABLED\nenum: IOLOGICC.LSRMUX LSR\nenum: IOLOGICC.CLKIMUX CLK\nenum: IOLOGICC.MODE IREG_OREG\nenum: IOLOGICC.DELAY.OUTDEL DISABLED\nenum: IOLOGICC.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICC.IDDRXN.MODE NONE\nenum: IOLOGICC.ODDRXN.MODE NONE\nenum: IOLOGICC.MIDDRX.MODE NONE\nenum: IOLOGICC.MODDRX.MODE NONE\nenum: IOLOGICC.MTDDRX.MODE NONE\nenum: IOLOGICC.IOLTOMUX NONE\nenum: IOLOGICD.SRMODE ASYNC\nenum: IOLOGICD.OUTREG.REGSET SET\nenum: IOLOGICD.OUTREG.OUTREGMODE FF\nenum: IOLOGICD.CEMUX CE\nenum: IOLOGICD.CEOMUX CEMUX\nenum: IOLOGICD.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICD.MTDDRX.REGSET RESET\nenum: IOLOGICD.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICD.LSROMUX LSRMUX\nenum: IOLOGICD.LSRIMUX 0\nenum: IOLOGICD.CLKOMUX CLK\nenum: IOLOGICD.GSR ENABLED\nenum: IOLOGICD.LSRMUX LSR\nenum: IOLOGICD.CLKIMUX CLK\nenum: IOLOGICD.MODE IREG_OREG\nenum: IOLOGICD.DELAY.OUTDEL DISABLED\nenum: IOLOGICD.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICD.IDDRXN.MODE NONE\nenum: IOLOGICD.ODDRXN.MODE NONE\nenum: IOLOGICD.MIDDRX.MODE NONE\nenum: IOLOGICD.MODDRX.MODE NONE\nenum: IOLOGICD.MTDDRX.MODE NONE\nenum: IOLOGICD.IOLTOMUX NONE\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOD.DATAMUX_OREG IOLDO\nenum: PIOC.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOC.DATAMUX_OREG IOLDO\n\n.tile MIB_R26C72:PICR0\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICA.MTDDRX.REGSET RESET\nenum: IOLOGICA.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICA.LSROMUX LSRMUX\nenum: IOLOGICA.LSRIMUX 0\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.IDDRXN.MODE NONE\nenum: IOLOGICA.ODDRXN.MODE NONE\nenum: IOLOGICA.MIDDRX.MODE NONE\nenum: IOLOGICA.MODDRX.MODE NONE\nenum: IOLOGICA.MTDDRX.MODE NONE\nenum: IOLOGICA.IOLTOMUX NONE\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.FF.REGSET SET\nenum: IOLOGICB.FF.INREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEIMUX CEMUX\nenum: IOLOGICB.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICB.MTDDRX.REGSET RESET\nenum: IOLOGICB.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICB.LSROMUX LSRMUX\nenum: IOLOGICB.LSRIMUX LSRMUX\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.IDDRXN.MODE NONE\nenum: IOLOGICB.ODDRXN.MODE NONE\nenum: IOLOGICB.MIDDRX.MODE NONE\nenum: IOLOGICB.MODDRX.MODE NONE\nenum: IOLOGICB.MTDDRX.MODE NONE\nenum: IOLOGICB.IOLTOMUX NONE\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\nenum: PIOB.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\n\n.tile MIB_R27C72:PICR1\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\nenum: PIOD.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOD.HYSTERESIS ON\nenum: PIOD.SLEWRATE FAST\nenum: PIOD.PULLMODE NONE\nenum: PIOD.DRIVE 4\nenum: PIOC.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOC.HYSTERESIS ON\nenum: PIOC.SLEWRATE FAST\nenum: PIOC.PULLMODE NONE\nenum: PIOC.DRIVE 4\nenum: PIOB.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOB.HYSTERESIS ON\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\n\n.tile MIB_R28C72:PICR2\nword: IOLOGICD.DELAY.DEL_VALUE 0000000\nword: IOLOGICC.DELAY.DEL_VALUE 0000000\nenum: IOLOGICD.OUTREG.REGSET SET\nenum: IOLOGICD.OUTREG.OUTREGMODE FF\nenum: IOLOGICD.CEOMUX CEMUX\nenum: IOLOGICD.SRMODE ASYNC\nenum: IOLOGICD.FF.REGSET SET\nenum: IOLOGICD.FF.INREGMODE FF\nenum: IOLOGICD.CEMUX CE\nenum: IOLOGICD.CEIMUX CEMUX\nenum: IOLOGICD.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICD.MTDDRX.REGSET RESET\nenum: IOLOGICD.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICD.LSROMUX LSRMUX\nenum: IOLOGICD.LSRIMUX LSRMUX\nenum: IOLOGICD.CLKOMUX CLK\nenum: IOLOGICD.GSR ENABLED\nenum: IOLOGICD.LSRMUX LSR\nenum: IOLOGICD.CLKIMUX CLK\nenum: IOLOGICD.MODE IREG_OREG\nenum: IOLOGICD.DELAY.OUTDEL DISABLED\nenum: IOLOGICD.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICD.IDDRXN.MODE NONE\nenum: IOLOGICD.ODDRXN.MODE NONE\nenum: IOLOGICD.MIDDRX.MODE NONE\nenum: IOLOGICD.MODDRX.MODE NONE\nenum: IOLOGICD.MTDDRX.MODE NONE\nenum: IOLOGICD.IOLTOMUX NONE\nenum: IOLOGICC.OUTREG.REGSET SET\nenum: IOLOGICC.OUTREG.OUTREGMODE FF\nenum: IOLOGICC.CEOMUX CEMUX\nenum: IOLOGICC.SRMODE ASYNC\nenum: IOLOGICC.FF.REGSET SET\nenum: IOLOGICC.FF.INREGMODE FF\nenum: IOLOGICC.CEMUX CE\nenum: IOLOGICC.CEIMUX CEMUX\nenum: IOLOGICC.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICC.MTDDRX.REGSET RESET\nenum: IOLOGICC.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICC.LSROMUX LSRMUX\nenum: IOLOGICC.LSRIMUX LSRMUX\nenum: IOLOGICC.CLKOMUX CLK\nenum: IOLOGICC.GSR ENABLED\nenum: IOLOGICC.LSRMUX LSR\nenum: IOLOGICC.CLKIMUX CLK\nenum: IOLOGICC.MODE IREG_OREG\nenum: IOLOGICC.DELAY.OUTDEL DISABLED\nenum: IOLOGICC.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICC.IDDRXN.MODE NONE\nenum: IOLOGICC.ODDRXN.MODE NONE\nenum: IOLOGICC.MIDDRX.MODE NONE\nenum: IOLOGICC.MODDRX.MODE NONE\nenum: IOLOGICC.MTDDRX.MODE NONE\nenum: IOLOGICC.IOLTOMUX NONE\nenum: PIOD.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOD.DATAMUX_OREG IOLDO\nenum: PIOC.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOC.DATAMUX_OREG IOLDO\n\n.tile MIB_R29C72:PICR0\narc: JDIB JPADDIB_PIO\nenum: PIOB.BASE_TYPE INPUT_LVCMOS33\n\n.tile MIB_R2C72:PICR0\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICA.MTDDRX.REGSET RESET\nenum: IOLOGICA.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICA.LSROMUX LSRMUX\nenum: IOLOGICA.LSRIMUX 0\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.IDDRXN.MODE NONE\nenum: IOLOGICA.ODDRXN.MODE NONE\nenum: IOLOGICA.MIDDRX.MODE NONE\nenum: IOLOGICA.MODDRX.MODE NONE\nenum: IOLOGICA.MTDDRX.MODE NONE\nenum: IOLOGICA.IOLTOMUX NONE\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.FF.REGSET SET\nenum: IOLOGICB.FF.INREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEIMUX CEMUX\nenum: IOLOGICB.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICB.MTDDRX.REGSET RESET\nenum: IOLOGICB.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICB.LSROMUX LSRMUX\nenum: IOLOGICB.LSRIMUX LSRMUX\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.IDDRXN.MODE NONE\nenum: IOLOGICB.ODDRXN.MODE NONE\nenum: IOLOGICB.MIDDRX.MODE NONE\nenum: IOLOGICB.MODDRX.MODE NONE\nenum: IOLOGICB.MTDDRX.MODE NONE\nenum: IOLOGICB.IOLTOMUX NONE\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\nenum: PIOB.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\n\n.tile MIB_R30C72:PICR1_DQS0\nenum: PIOB.BASE_TYPE INPUT_LVCMOS33\nenum: PIOB.HYSTERESIS ON\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE UP\n\n.tile MIB_R32C72:PICR0_DQS2\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.FF.REGSET SET\nenum: IOLOGICA.FF.INREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEIMUX CEMUX\nenum: IOLOGICA.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICA.MTDDRX.REGSET RESET\nenum: IOLOGICA.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICA.LSROMUX LSRMUX\nenum: IOLOGICA.LSRIMUX LSRMUX\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.IDDRXN.MODE NONE\nenum: IOLOGICA.ODDRXN.MODE NONE\nenum: IOLOGICA.MIDDRX.MODE NONE\nenum: IOLOGICA.MODDRX.MODE NONE\nenum: IOLOGICA.MTDDRX.MODE NONE\nenum: IOLOGICA.IOLTOMUX NONE\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.FF.REGSET SET\nenum: IOLOGICB.FF.INREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEIMUX CEMUX\nenum: IOLOGICB.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICB.MTDDRX.REGSET RESET\nenum: IOLOGICB.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICB.LSROMUX LSRMUX\nenum: IOLOGICB.LSRIMUX LSRMUX\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.IDDRXN.MODE NONE\nenum: IOLOGICB.ODDRXN.MODE NONE\nenum: IOLOGICB.MIDDRX.MODE NONE\nenum: IOLOGICB.MODDRX.MODE NONE\nenum: IOLOGICB.MTDDRX.MODE NONE\nenum: IOLOGICB.IOLTOMUX NONE\nenum: PIOB.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\nenum: PIOA.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\n\n.tile MIB_R33C72:PICR1_DQS3\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOC.BASE_TYPE INPUT_LVCMOS33\nenum: PIOC.HYSTERESIS ON\nenum: PIOB.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOB.HYSTERESIS ON\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\nenum: PIOA.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOA.HYSTERESIS ON\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\n\n.tile MIB_R34C72:PICR2\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOC.BASE_TYPE INPUT_LVCMOS33\n\n.tile MIB_R35C0:PICL0\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R35C72:PICR0\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.FF.REGSET SET\nenum: IOLOGICB.FF.INREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEIMUX CEMUX\nenum: IOLOGICB.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICB.MTDDRX.REGSET RESET\nenum: IOLOGICB.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICB.LSROMUX LSRMUX\nenum: IOLOGICB.LSRIMUX LSRMUX\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.IDDRXN.MODE NONE\nenum: IOLOGICB.ODDRXN.MODE NONE\nenum: IOLOGICB.MIDDRX.MODE NONE\nenum: IOLOGICB.MODDRX.MODE NONE\nenum: IOLOGICB.MTDDRX.MODE NONE\nenum: IOLOGICB.IOLTOMUX NONE\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.FF.REGSET SET\nenum: IOLOGICA.FF.INREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEIMUX CEMUX\nenum: IOLOGICA.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICA.MTDDRX.REGSET RESET\nenum: IOLOGICA.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICA.LSROMUX LSRMUX\nenum: IOLOGICA.LSRIMUX LSRMUX\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.IDDRXN.MODE NONE\nenum: IOLOGICA.ODDRXN.MODE NONE\nenum: IOLOGICA.MIDDRX.MODE NONE\nenum: IOLOGICA.MODDRX.MODE NONE\nenum: IOLOGICA.MTDDRX.MODE NONE\nenum: IOLOGICA.IOLTOMUX NONE\nenum: PIOA.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\nenum: PIOB.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\n\n.tile MIB_R36C0:PICL1\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R36C72:PICR1\nenum: PIOA.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOA.HYSTERESIS ON\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\nenum: PIOB.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOB.HYSTERESIS ON\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\nenum: PIOD.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOD.HYSTERESIS ON\nenum: PIOD.SLEWRATE FAST\nenum: PIOD.PULLMODE NONE\nenum: PIOD.DRIVE 4\n\n.tile MIB_R37C21:EBR_SPINE_LL0\narc: G_VPTX0000 G_HPRX0000\n\n.tile MIB_R37C31:CMUX_LL_0\narc: G_DCS1CLK0 G_VPFN0000\narc: G_LLPCLK0 G_HPFE0300\narc: G_LLPCLK1 G_HPFE0600\n\n.tile MIB_R37C32:CMUX_LR_0\narc: G_DCS1CLK1 G_VPFN0000\narc: G_LRPCLK0 G_HPFE0300\narc: G_LRPCLK1 G_HPFE0600\n\n.tile MIB_R37C3:EBR_SPINE_LL3\narc: G_VPTX0000 G_HPRX0000\n\n.tile MIB_R37C41:EBR_SPINE_LR0\narc: G_VPTX0000 G_HPRX0000\n\n.tile MIB_R37C59:EBR_SPINE_LR1\narc: G_VPTX0000 G_HPRX0000\narc: G_VPTX0100 G_HPRX0100\n\n.tile MIB_R37C72:MIB_CIB_LR_A\nword: IOLOGICD.DELAY.DEL_VALUE 0000000\nenum: IOLOGICD.OUTREG.REGSET SET\nenum: IOLOGICD.OUTREG.OUTREGMODE FF\nenum: IOLOGICD.CEOMUX CEMUX\nenum: IOLOGICD.SRMODE ASYNC\nenum: IOLOGICD.FF.REGSET SET\nenum: IOLOGICD.FF.INREGMODE FF\nenum: IOLOGICD.CEMUX CE\nenum: IOLOGICD.CEIMUX CEMUX\nenum: IOLOGICD.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICD.MTDDRX.REGSET RESET\nenum: IOLOGICD.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICD.LSROMUX LSRMUX\nenum: IOLOGICD.LSRIMUX LSRMUX\nenum: IOLOGICD.CLKOMUX CLK\nenum: IOLOGICD.GSR ENABLED\nenum: IOLOGICD.LSRMUX LSR\nenum: IOLOGICD.CLKIMUX CLK\nenum: IOLOGICD.MODE IREG_OREG\nenum: IOLOGICD.DELAY.OUTDEL DISABLED\nenum: IOLOGICD.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICD.IDDRXN.MODE NONE\nenum: IOLOGICD.ODDRXN.MODE NONE\nenum: IOLOGICD.MIDDRX.MODE NONE\nenum: IOLOGICD.MODDRX.MODE NONE\nenum: IOLOGICD.MTDDRX.MODE NONE\nenum: IOLOGICD.IOLTOMUX NONE\nenum: PIOD.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOD.DATAMUX_OREG IOLDO\n\n.tile MIB_R39C0:PICL1\nenum: PIOC.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R39C72:PICR1\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOD.SLEWRATE FAST\nenum: PIOD.PULLMODE NONE\nenum: PIOD.DRIVE 4\nenum: PIOC.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOC.SLEWRATE FAST\nenum: PIOC.PULLMODE NONE\nenum: PIOC.DRIVE 4\n\n.tile MIB_R3C72:PICR1\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\nenum: PIOB.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOB.HYSTERESIS ON\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\nenum: PIOD.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOD.HYSTERESIS ON\nenum: PIOD.SLEWRATE FAST\nenum: PIOD.PULLMODE NONE\nenum: PIOD.DRIVE 4\n\n.tile MIB_R40C0:PICL2\nenum: PIOC.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R40C72:PICR2\nword: IOLOGICC.DELAY.DEL_VALUE 0000000\nword: IOLOGICD.DELAY.DEL_VALUE 0000000\nenum: IOLOGICC.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICC.MTDDRX.REGSET RESET\nenum: IOLOGICC.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICC.LSROMUX 0\nenum: IOLOGICC.LSRIMUX 0\nenum: IOLOGICC.CLKOMUX CLK\nenum: IOLOGICC.GSR DISABLED\nenum: IOLOGICC.LSRMUX LSR\nenum: IOLOGICC.CLKIMUX CLK\nenum: IOLOGICC.MODE IDDRX1_ODDRX1\nenum: IOLOGICC.DELAY.OUTDEL DISABLED\nenum: IOLOGICC.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICC.IDDRXN.MODE NONE\nenum: IOLOGICC.ODDRXN.MODE NONE\nenum: IOLOGICC.MIDDRX.MODE NONE\nenum: IOLOGICC.MODDRX.MODE NONE\nenum: IOLOGICC.MTDDRX.MODE NONE\nenum: IOLOGICC.IOLTOMUX NONE\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOD.DATAMUX_OREG IOLDO\nenum: PIOC.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOC.DATAMUX_ODDR IOLDO\nenum: IOLOGICD.SRMODE ASYNC\nenum: IOLOGICD.OUTREG.REGSET SET\nenum: IOLOGICD.OUTREG.OUTREGMODE FF\nenum: IOLOGICD.CEMUX CE\nenum: IOLOGICD.CEOMUX CEMUX\nenum: IOLOGICD.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICD.MTDDRX.REGSET RESET\nenum: IOLOGICD.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICD.LSROMUX LSRMUX\nenum: IOLOGICD.LSRIMUX 0\nenum: IOLOGICD.CLKOMUX CLK\nenum: IOLOGICD.GSR ENABLED\nenum: IOLOGICD.LSRMUX LSR\nenum: IOLOGICD.CLKIMUX CLK\nenum: IOLOGICD.MODE IREG_OREG\nenum: IOLOGICD.DELAY.OUTDEL DISABLED\nenum: IOLOGICD.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICD.IDDRXN.MODE NONE\nenum: IOLOGICD.ODDRXN.MODE NONE\nenum: IOLOGICD.MIDDRX.MODE NONE\nenum: IOLOGICD.MODDRX.MODE NONE\nenum: IOLOGICD.MTDDRX.MODE NONE\nenum: IOLOGICD.IOLTOMUX NONE\n\n.tile MIB_R41C0:PICL0\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R41C72:PICR0\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICB.MTDDRX.REGSET RESET\nenum: IOLOGICB.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICB.LSROMUX LSRMUX\nenum: IOLOGICB.LSRIMUX 0\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.IDDRXN.MODE NONE\nenum: IOLOGICB.ODDRXN.MODE NONE\nenum: IOLOGICB.MIDDRX.MODE NONE\nenum: IOLOGICB.MODDRX.MODE NONE\nenum: IOLOGICB.MTDDRX.MODE NONE\nenum: IOLOGICB.IOLTOMUX NONE\n\n.tile MIB_R42C0:PICL1_DQS0\nenum: PIOC.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R42C72:PICR1_DQS0\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOD.SLEWRATE FAST\nenum: PIOD.PULLMODE NONE\nenum: PIOD.DRIVE 4\nenum: PIOC.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOC.SLEWRATE FAST\nenum: PIOC.PULLMODE NONE\nenum: PIOC.DRIVE 4\n\n.tile MIB_R43C0:PICL2_DQS1\nenum: PIOC.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R43C72:PICR2_DQS1\nword: IOLOGICC.DELAY.DEL_VALUE 0000000\nword: IOLOGICD.DELAY.DEL_VALUE 0000000\nenum: IOLOGICC.SRMODE ASYNC\nenum: IOLOGICC.OUTREG.REGSET SET\nenum: IOLOGICC.OUTREG.OUTREGMODE FF\nenum: IOLOGICC.CEMUX CE\nenum: IOLOGICC.CEOMUX CEMUX\nenum: IOLOGICC.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICC.MTDDRX.REGSET RESET\nenum: IOLOGICC.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICC.LSROMUX LSRMUX\nenum: IOLOGICC.LSRIMUX 0\nenum: IOLOGICC.CLKOMUX CLK\nenum: IOLOGICC.GSR ENABLED\nenum: IOLOGICC.LSRMUX LSR\nenum: IOLOGICC.CLKIMUX CLK\nenum: IOLOGICC.MODE IREG_OREG\nenum: IOLOGICC.DELAY.OUTDEL DISABLED\nenum: IOLOGICC.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICC.IDDRXN.MODE NONE\nenum: IOLOGICC.ODDRXN.MODE NONE\nenum: IOLOGICC.MIDDRX.MODE NONE\nenum: IOLOGICC.MODDRX.MODE NONE\nenum: IOLOGICC.MTDDRX.MODE NONE\nenum: IOLOGICC.IOLTOMUX NONE\nenum: IOLOGICD.SRMODE ASYNC\nenum: IOLOGICD.OUTREG.REGSET SET\nenum: IOLOGICD.OUTREG.OUTREGMODE FF\nenum: IOLOGICD.CEMUX CE\nenum: IOLOGICD.CEOMUX CEMUX\nenum: IOLOGICD.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICD.MTDDRX.REGSET RESET\nenum: IOLOGICD.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICD.LSROMUX LSRMUX\nenum: IOLOGICD.LSRIMUX 0\nenum: IOLOGICD.CLKOMUX CLK\nenum: IOLOGICD.GSR ENABLED\nenum: IOLOGICD.LSRMUX LSR\nenum: IOLOGICD.CLKIMUX CLK\nenum: IOLOGICD.MODE IREG_OREG\nenum: IOLOGICD.DELAY.OUTDEL DISABLED\nenum: IOLOGICD.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICD.IDDRXN.MODE NONE\nenum: IOLOGICD.ODDRXN.MODE NONE\nenum: IOLOGICD.MIDDRX.MODE NONE\nenum: IOLOGICD.MODDRX.MODE NONE\nenum: IOLOGICD.MTDDRX.MODE NONE\nenum: IOLOGICD.IOLTOMUX NONE\nenum: PIOD.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOD.DATAMUX_OREG IOLDO\nenum: PIOC.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOC.DATAMUX_OREG IOLDO\n\n.tile MIB_R44C0:PICL0_DQS2\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R44C72:PICR0_DQS2\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICB.MTDDRX.REGSET RESET\nenum: IOLOGICB.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICB.LSROMUX LSRMUX\nenum: IOLOGICB.LSRIMUX 0\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.IDDRXN.MODE NONE\nenum: IOLOGICB.ODDRXN.MODE NONE\nenum: IOLOGICB.MIDDRX.MODE NONE\nenum: IOLOGICB.MODDRX.MODE NONE\nenum: IOLOGICB.MTDDRX.MODE NONE\nenum: IOLOGICB.IOLTOMUX NONE\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICA.MTDDRX.REGSET RESET\nenum: IOLOGICA.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICA.LSROMUX LSRMUX\nenum: IOLOGICA.LSRIMUX 0\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.IDDRXN.MODE NONE\nenum: IOLOGICA.ODDRXN.MODE NONE\nenum: IOLOGICA.MIDDRX.MODE NONE\nenum: IOLOGICA.MODDRX.MODE NONE\nenum: IOLOGICA.MTDDRX.MODE NONE\nenum: IOLOGICA.IOLTOMUX NONE\n\n.tile MIB_R45C0:PICL1_DQS3\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R45C72:PICR1_DQS3\nenum: PIOB.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\n\n.tile MIB_R48C0:PICL1\nenum: PIOC.BASE_TYPE INPUT_LVCMOS33\nenum: PIOC.HYSTERESIS ON\n\n.tile MIB_R49C0:MIB_CIB_LR\nenum: PIOC.BASE_TYPE INPUT_LVCMOS33\n\n.tile MIB_R4C72:PICR2\nword: IOLOGICD.DELAY.DEL_VALUE 0000000\nenum: IOLOGICD.OUTREG.REGSET SET\nenum: IOLOGICD.OUTREG.OUTREGMODE FF\nenum: IOLOGICD.CEOMUX CEMUX\nenum: IOLOGICD.SRMODE ASYNC\nenum: IOLOGICD.FF.REGSET SET\nenum: IOLOGICD.FF.INREGMODE FF\nenum: IOLOGICD.CEMUX CE\nenum: IOLOGICD.CEIMUX CEMUX\nenum: IOLOGICD.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICD.MTDDRX.REGSET RESET\nenum: IOLOGICD.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICD.LSROMUX LSRMUX\nenum: IOLOGICD.LSRIMUX LSRMUX\nenum: IOLOGICD.CLKOMUX CLK\nenum: IOLOGICD.GSR ENABLED\nenum: IOLOGICD.LSRMUX LSR\nenum: IOLOGICD.CLKIMUX CLK\nenum: IOLOGICD.MODE IREG_OREG\nenum: IOLOGICD.DELAY.OUTDEL DISABLED\nenum: IOLOGICD.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICD.IDDRXN.MODE NONE\nenum: IOLOGICD.ODDRXN.MODE NONE\nenum: IOLOGICD.MIDDRX.MODE NONE\nenum: IOLOGICD.MODDRX.MODE NONE\nenum: IOLOGICD.MTDDRX.MODE NONE\nenum: IOLOGICD.IOLTOMUX NONE\nenum: PIOD.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOD.DATAMUX_OREG IOLDO\n\n.tile MIB_R50C1:BANKREF6\nenum: BANK.VCCIO 3V3\n\n.tile MIB_R50C2:PLL0_LL\narc: N1_REFCLK1 N1_JREFCLK1_3\n\n.tile MIB_R50C4:EFB0_PICB0\nunknown: F54B1\nunknown: F56B1\nunknown: F82B1\nunknown: F94B1\n\n.tile MIB_R50C71:BANKREF3\nenum: BANK.VCCIO 3V3\n\n.tile MIB_R5C72:PICR0\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICA.MTDDRX.REGSET RESET\nenum: IOLOGICA.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICA.LSROMUX LSRMUX\nenum: IOLOGICA.LSRIMUX 0\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.IDDRXN.MODE NONE\nenum: IOLOGICA.ODDRXN.MODE NONE\nenum: IOLOGICA.MIDDRX.MODE NONE\nenum: IOLOGICA.MODDRX.MODE NONE\nenum: IOLOGICA.MTDDRX.MODE NONE\nenum: IOLOGICA.IOLTOMUX NONE\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.FF.REGSET SET\nenum: IOLOGICB.FF.INREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEIMUX CEMUX\nenum: IOLOGICB.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICB.MTDDRX.REGSET RESET\nenum: IOLOGICB.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICB.LSROMUX LSRMUX\nenum: IOLOGICB.LSRIMUX LSRMUX\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.IDDRXN.MODE NONE\nenum: IOLOGICB.ODDRXN.MODE NONE\nenum: IOLOGICB.MIDDRX.MODE NONE\nenum: IOLOGICB.MODDRX.MODE NONE\nenum: IOLOGICB.MTDDRX.MODE NONE\nenum: IOLOGICB.IOLTOMUX NONE\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\nenum: PIOB.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\n\n.tile MIB_R6C72:PICR1_DQS0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\nenum: PIOB.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOB.HYSTERESIS ON\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\n\n.tile MIB_R8C72:PICR0_DQS2\nword: IOLOGICB.DELAY.DEL_VALUE 0000000\nword: IOLOGICA.DELAY.DEL_VALUE 0000000\nenum: IOLOGICB.OUTREG.REGSET SET\nenum: IOLOGICB.OUTREG.OUTREGMODE FF\nenum: IOLOGICB.CEOMUX CEMUX\nenum: IOLOGICB.SRMODE ASYNC\nenum: IOLOGICB.FF.REGSET SET\nenum: IOLOGICB.FF.INREGMODE FF\nenum: IOLOGICB.CEMUX CE\nenum: IOLOGICB.CEIMUX CEMUX\nenum: IOLOGICB.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICB.MTDDRX.REGSET RESET\nenum: IOLOGICB.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICB.LSROMUX LSRMUX\nenum: IOLOGICB.LSRIMUX LSRMUX\nenum: IOLOGICB.CLKOMUX CLK\nenum: IOLOGICB.GSR ENABLED\nenum: IOLOGICB.LSRMUX LSR\nenum: IOLOGICB.CLKIMUX CLK\nenum: IOLOGICB.MODE IREG_OREG\nenum: IOLOGICB.DELAY.OUTDEL DISABLED\nenum: IOLOGICB.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICB.IDDRXN.MODE NONE\nenum: IOLOGICB.ODDRXN.MODE NONE\nenum: IOLOGICB.MIDDRX.MODE NONE\nenum: IOLOGICB.MODDRX.MODE NONE\nenum: IOLOGICB.MTDDRX.MODE NONE\nenum: IOLOGICB.IOLTOMUX NONE\nenum: PIOB.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOB.DATAMUX_OREG IOLDO\nenum: PIOA.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOA.DATAMUX_OREG IOLDO\nenum: IOLOGICA.OUTREG.REGSET SET\nenum: IOLOGICA.OUTREG.OUTREGMODE FF\nenum: IOLOGICA.CEOMUX CEMUX\nenum: IOLOGICA.SRMODE ASYNC\nenum: IOLOGICA.FF.REGSET SET\nenum: IOLOGICA.FF.INREGMODE FF\nenum: IOLOGICA.CEMUX CE\nenum: IOLOGICA.CEIMUX CEMUX\nenum: IOLOGICA.MIDDRX_MODDRX.WRCLKMUX NONE\nenum: IOLOGICA.MTDDRX.REGSET RESET\nenum: IOLOGICA.MTDDRX.DQSW_INVERT DISABLED\nenum: IOLOGICA.LSROMUX LSRMUX\nenum: IOLOGICA.LSRIMUX LSRMUX\nenum: IOLOGICA.CLKOMUX CLK\nenum: IOLOGICA.GSR ENABLED\nenum: IOLOGICA.LSRMUX LSR\nenum: IOLOGICA.CLKIMUX CLK\nenum: IOLOGICA.MODE IREG_OREG\nenum: IOLOGICA.DELAY.OUTDEL DISABLED\nenum: IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED\nenum: IOLOGICA.IDDRXN.MODE NONE\nenum: IOLOGICA.ODDRXN.MODE NONE\nenum: IOLOGICA.MIDDRX.MODE NONE\nenum: IOLOGICA.MODDRX.MODE NONE\nenum: IOLOGICA.MTDDRX.MODE NONE\nenum: IOLOGICA.IOLTOMUX NONE\n\n.tile MIB_R9C72:PICR1_DQS3\nenum: PIOB.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOB.HYSTERESIS ON\nenum: PIOB.SLEWRATE FAST\nenum: PIOB.PULLMODE NONE\nenum: PIOB.DRIVE 4\nenum: PIOA.BASE_TYPE BIDIR_LVCMOS33\nenum: PIOA.HYSTERESIS ON\nenum: PIOA.SLEWRATE FAST\nenum: PIOA.PULLMODE NONE\nenum: PIOA.DRIVE 4\n\n.tile R10C10:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 S1_V02N0501\narc: E3_H06E0303 N3_V06S0303\narc: H00R0100 H02W0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0301 V01N0101\narc: S1_V02S0601 W1_H02E0601\narc: V00B0000 E1_H02W0601\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02E0001\narc: V00T0100 V02S0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 E1_H01W0100\narc: E1_H01E0101 W3_H06E0203\narc: A3 H01E0001\narc: A6 N1_V01N0101\narc: A7 H00R0000\narc: B3 V01N0001\narc: B6 V00B0000\narc: B7 V00B0100\narc: C1 E1_H01W0000\narc: C3 H02W0401\narc: C4 E1_H02W0401\narc: C5 V00T0000\narc: C6 V02N0001\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D3 E1_H02W0201\narc: D4 V02S0401\narc: D5 V02S0601\narc: D6 H00R0100\narc: D7 V02N0601\narc: E3_H06E0203 F7\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q6\narc: H01W0100 F4\narc: LSR0 H02E0301\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F3\narc: N3_V06N0203 F4\narc: N3_V06N0303 F5\narc: S1_V02S0701 F5\narc: S3_V06S0303 F5\narc: W1_H02W0101 F1\narc: W3_H06W0203 F4\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 0111111111111111\nword: SLICED.K1.INIT 0000000000000001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R10C11:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 N1_V01S0000\narc: H00L0000 E1_H02W0001\narc: H00R0100 V02N0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H02E0401\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 H06W0003\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 H06W0303\narc: V00B0000 V02N0001\narc: V00B0100 V02N0101\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 V02N0701\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0303 E1_H02W0501\narc: C6 E1_H01E0101\narc: C7 S1_V02N0201\narc: CE0 H00L0000\narc: CE1 H00R0100\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D6 V00B0000\narc: D7 V01N0001\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: E1_H02E0001 Q2\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H01W0000 F7\narc: H01W0100 Q2\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00B0100\narc: M2 E1_H02W0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V02N0701 F7\narc: N3_V06N0203 Q4\narc: V01S0100 Q0\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0000000011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R10C12:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 H02E0001\narc: H00L0100 S1_V02N0101\narc: H00R0100 N1_V02S0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 E1_H01W0000\narc: V00B0000 V02N0001\narc: V00B0100 H02W0701\narc: V00T0000 V02N0601\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 H01E0001\narc: E1_H02E0601 W3_H06E0303\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: A3 H00L0100\narc: A4 V00T0000\narc: A5 S1_V02N0101\narc: B1 H00R0100\narc: B3 V02N0101\narc: B4 H00L0000\narc: B5 E1_H02W0101\narc: B7 V00B0000\narc: C1 V02N0401\narc: C2 N1_V01N0001\narc: C3 H02E0401\narc: C4 E1_H01E0101\narc: C5 H02E0401\narc: C7 V01N0101\narc: CLK0 G_HPBX0000\narc: D1 N1_V02S0201\narc: D2 S1_V02N0001\narc: D3 V00B0100\narc: D4 V02S0401\narc: D5 H02W0201\narc: D7 V02S0601\narc: E1_H01E0101 F5\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F3\narc: N1_V02N0301 Q1\narc: N1_V02N0501 Q7\narc: N3_V06N0003 F3\narc: S1_V02S0501 F5\narc: S3_V06S0103 F2\narc: S3_V06S0303 F5\narc: W1_H02W0501 F5\narc: W1_H02W0601 F4\narc: W3_H06W0003 F3\narc: W3_H06W0103 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111110000001100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110000001100\nword: SLICEC.K0.INIT 0001010100111111\nword: SLICEC.K1.INIT 0100000000000000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0100000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R10C13:PLC2\narc: E1_H02E0401 E1_H01W0000\narc: H00L0100 S1_V02N0101\narc: H00R0100 E1_H02W0501\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 H06E0303\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 H02E0601\narc: V00B0100 E1_H02W0501\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 E3_H06W0303\narc: A1 V01N0101\narc: A3 H00L0100\narc: A5 S1_V02N0101\narc: A6 N1_V01N0101\narc: A7 V00T0100\narc: B1 V02N0301\narc: B3 H02W0101\narc: B5 H02W0101\narc: B6 H02E0101\narc: B7 S1_V02N0701\narc: C1 E1_H01W0000\narc: C2 N1_V01N0001\narc: C3 H02W0401\narc: C4 E1_H01E0101\narc: C5 E1_H02W0401\narc: C6 V02N0001\narc: C7 V02N0201\narc: CLK0 G_HPBX0000\narc: D1 V02S0201\narc: D2 H02E0001\narc: D3 V00B0100\narc: D4 H02E0001\narc: D5 H00R0100\narc: D6 H02E0201\narc: D7 V00B0000\narc: E1_H01E0101 F5\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: H01W0100 F4\narc: LSR0 H02E0301\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F3\narc: N1_V01N0101 Q7\narc: N3_V06N0303 F5\narc: S3_V06S0003 F3\narc: S3_V06S0303 F5\narc: V00T0100 F1\narc: V01S0000 F4\narc: W1_H02W0001 F2\narc: W1_H02W0101 F3\narc: W1_H02W0501 F5\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0100000000000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0001000000000000\nword: SLICED.K0.INIT 0000000000000001\nword: SLICED.K1.INIT 0111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R10C14:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 E1_H01W0000\narc: H00L0000 V02N0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02W0601\narc: H00R0100 V02N0701\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 W1_H02E0401\narc: V00B0000 H02W0601\narc: V00B0100 V02S0101\narc: V00T0000 V02S0401\narc: V00T0100 V02N0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 E3_H06W0303\narc: A3 H00L0100\narc: A7 S1_V02N0301\narc: B3 H00R0000\narc: B5 H00L0000\narc: B7 V00B0000\narc: C0 H00R0100\narc: C1 H00L0100\narc: C2 H02E0401\narc: C3 V02S0401\narc: C5 V02S0201\narc: C6 E1_H01E0101\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 V02S0001\narc: D2 V00T0100\narc: D3 H02W0201\narc: D5 V02N0601\narc: D6 H00R0100\narc: D7 V02S0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: E3_H06E0303 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 F1\narc: LSR1 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F1\narc: N3_V06N0003 F3\narc: N3_V06N0203 F7\narc: S3_V06S0003 F3\narc: S3_V06S0103 F1\narc: S3_V06S0203 F7\narc: S3_V06S0303 F6\narc: V01S0000 F0\narc: V01S0100 F2\narc: W1_H02W0701 F7\narc: W3_H06W0003 F0\narc: W3_H06W0103 F2\narc: W3_H06W0203 F7\narc: W3_H06W0303 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100000011111111\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0001000000000000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0100000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R10C15:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 S1_V02N0601\narc: H00L0100 V02N0301\narc: H00R0000 V02N0601\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0601 H02W0601\narc: S3_V06S0103 N1_V02S0201\narc: V00B0000 V02N0001\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 E1_H02W0601\narc: E3_H06E0303 W3_H06E0203\narc: B1 H02E0301\narc: B3 H00R0000\narc: C1 N1_V01N0001\narc: C3 H02E0601\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D3 S1_V02N0001\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: H01W0000 Q6\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M4 V00B0000\narc: M6 N1_V01N0101\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q4\narc: N3_V06N0003 F3\narc: N3_V06N0103 F1\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100110011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R10C16:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: H00R0000 H02W0601\narc: H00R0100 S1_V02N0701\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S1_V02N0601\narc: S3_V06S0203 H06W0203\narc: V00T0000 S1_V02N0601\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 V06N0303\narc: E1_H01E0101 W3_H06E0203\narc: A1 H02W0501\narc: B1 V02N0101\narc: B2 H02E0301\narc: B3 V02N0101\narc: B5 H00R0000\narc: C1 H02E0401\narc: C2 H02E0401\narc: C3 V02N0601\narc: C4 V00B0100\narc: C5 H02W0401\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: D2 V00T0100\narc: D3 V02N0201\narc: D4 S1_V02N0401\narc: D5 H02E0201\narc: E1_H01E0001 F4\narc: E1_H02E0501 F5\narc: E3_H06E0003 F0\narc: E3_H06E0103 F2\narc: E3_H06E0203 F4\narc: E3_H06E0303 F5\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q6\narc: H01W0100 F4\narc: LSR1 V00T0000\narc: M0 H02E0601\narc: M6 W1_H02E0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F5\narc: N1_V01N0101 F0\narc: N3_V06N0303 F5\narc: S1_V02S0601 F4\narc: S1_V02S0701 F5\narc: S3_V06S0303 F5\narc: V00B0100 F5\narc: V00T0100 F3\narc: V01S0000 F3\narc: V01S0100 F4\narc: W1_H02W0501 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000001100000000\nword: SLICEB.K0.INIT 1100111111111111\nword: SLICEB.K1.INIT 0000000000110000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111110\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R10C17:PLC2\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 V02N0601\narc: H00R0000 H02W0601\narc: H00R0100 H02E0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H01E0101\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0201 H01E0001\narc: S1_V02S0501 V01N0101\narc: S3_V06S0003 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00B0100 V02N0101\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02S0501\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 N1_V01S0000\narc: A1 E1_H01E0001\narc: A4 N1_V01N0101\narc: B1 V00T0000\narc: B4 H00R0000\narc: B5 V02N0501\narc: C1 H00R0100\narc: C4 H02W0401\narc: C5 V02N0201\narc: CE1 W1_H02E0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D4 V00B0000\narc: D5 H02E0201\narc: E1_H01E0001 Q6\narc: E1_H02E0101 F1\narc: E1_H02E0201 Q2\narc: E1_H02E0701 Q5\narc: E3_H06E0203 F4\narc: E3_H06E0303 Q5\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M2 V00B0100\narc: M6 H02E0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q5\narc: V01S0100 Q5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0010000010101010\nword: SLICEC.K1.INIT 0000001100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R10C18:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0501 V02S0501\narc: E3_H06E0103 S3_V06N0103\narc: H00R0000 V02S0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0301 N1_V01S0100\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: V00T0100 N1_V02S0701\narc: W1_H02W0401 N1_V01S0000\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0303 E3_H06W0203\narc: A0 H02E0701\narc: B0 H00R0100\narc: B3 V02S0101\narc: B7 V00B0100\narc: C0 V02S0401\narc: C2 H00L0100\narc: C3 S1_V02N0401\narc: C6 V02N0201\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D2 V02N0001\narc: D3 V00T0100\narc: D6 V02N0601\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: E1_H01E0101 F6\narc: E1_H02E0601 Q4\narc: E1_H02E0701 F7\narc: E3_H06E0003 F3\narc: E3_H06E0203 F7\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H01W0000 F0\narc: H01W0100 Q4\narc: M0 H02E0601\narc: M4 H02W0401\narc: MUXCLK2 CLK0\narc: N1_V01N0101 F2\narc: N1_V02N0601 Q4\narc: S1_V02S0201 F2\narc: S1_V02S0301 F3\narc: S1_V02S0601 F6\narc: S3_V06S0103 F2\narc: S3_V06S0203 F7\narc: S3_V06S0303 F6\narc: V01S0000 F7\narc: V01S0100 F7\narc: W1_H02W0101 F3\narc: W1_H02W0601 Q4\narc: W3_H06W0003 F3\narc: W3_H06W0203 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0000001100000000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0000001100000000\nword: SLICEA.K0.INIT 0011001100110001\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R10C19:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 H01E0001\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 H01E0101\narc: H00L0000 W1_H02E0201\narc: H00R0000 V02N0601\narc: H00R0100 H02E0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 H01E0001\narc: S3_V06S0003 H01E0001\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 H06E0303\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02N0301\narc: V00T0000 H02E0001\narc: V00T0100 H02W0301\narc: V01S0100 S3_V06N0303\narc: W1_H02W0401 V02S0401\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A1 V01N0101\narc: A2 E1_H01E0001\narc: A3 E1_H02W0701\narc: A4 S1_V02N0101\narc: A5 V00T0100\narc: A6 F7\narc: A7 H02W0501\narc: B1 E1_H02W0301\narc: B2 H02W0101\narc: B3 V02S0301\narc: B4 H00R0000\narc: B5 H00L0000\narc: B6 W1_H02E0101\narc: B7 V00B0000\narc: C1 H02W0401\narc: C2 H02W0601\narc: C3 E1_H01W0000\narc: C4 V02N0201\narc: C5 V00T0000\narc: C6 E1_H01E0101\narc: C7 H01E0001\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D2 V00B0100\narc: D3 E1_H02W0001\narc: D4 E1_H02W0201\narc: D5 V02N0401\narc: D6 E1_H01W0100\narc: D7 H00R0100\narc: E1_H01E0001 Q3\narc: E1_H01E0101 F1\narc: E3_H06E0103 F2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 Q6\narc: LSR0 W1_H02E0501\narc: LSR1 W1_H02E0501\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000000000000001\nword: SLICEB.K1.INIT 0111111111111111\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0111111111111111\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R10C20:PLC2\narc: E1_H02E0601 W1_H02E0601\narc: H00R0000 S1_V02N0401\narc: H00R0100 W1_H02E0701\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 H06E0203\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 V02N0201\narc: V00B0100 H02W0501\narc: V00T0000 V02N0601\narc: V00T0100 V02N0701\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0701 E1_H02W0601\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\narc: A1 E1_H02W0501\narc: A5 V02N0101\narc: A6 V00T0100\narc: A7 H00L0000\narc: B1 E1_H02W0301\narc: B5 V02S0701\narc: B6 V02N0501\narc: B7 V00T0000\narc: C1 H00R0100\narc: C5 H02W0601\narc: C6 V01N0101\narc: C7 V02S0001\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D5 W1_H02E0201\narc: D6 V02N0401\narc: D7 H02E0001\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 F7\narc: H01W0100 F1\narc: LSR0 H02E0301\narc: M2 V00B0000\narc: M4 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: S1_V02S0401 F6\narc: S1_V02S0601 F4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R10C21:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 W1_H02E0101\narc: E3_H06E0203 W1_H02E0401\narc: H00R0000 E1_H02W0401\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0301 H06E0003\narc: S1_V02S0701 V01N0101\narc: S3_V06S0203 H06E0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 V02N0401\narc: V00T0100 V02S0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V02N0601\narc: S3_V06S0303 W3_H06E0303\narc: A5 V00T0000\narc: A7 H00L0000\narc: B5 N1_V01S0000\narc: B7 S1_V02N0501\narc: C5 W1_H02E0601\narc: C7 V00T0100\narc: CE0 W1_H02E0101\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D5 H02W0001\narc: D7 V00B0000\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q0\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: LSR0 W1_H02E0301\narc: LSR1 W1_H02E0301\narc: M0 V00B0100\narc: M2 E1_H02W0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: W1_H02W0701 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R10C22:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0103 S3_V06N0103\narc: H00R0000 H02E0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0601 H01E0001\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0303 H06E0303\narc: V00B0000 H02W0601\narc: V00B0100 S1_V02N0101\narc: V00T0000 E1_H02W0001\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 S1_V02N0601\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0201 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: N1_V02N0001 W3_H06E0003\narc: N3_V06N0003 W3_H06E0003\narc: S1_V02S0501 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A7 H00L0000\narc: B7 V01S0000\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CE1 H02W0101\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D7 H00R0100\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 H02W0601\narc: M2 H02W0601\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: S1_V02S0201 Q2\narc: V01S0000 Q4\narc: V01S0100 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R10C23:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 S1_V02N0201\narc: H00L0100 N1_V02S0101\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0201\narc: V00B0000 V02S0201\narc: W1_H02W0101 H01E0101\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E1_H02W0601\narc: H01W0100 W3_H06E0303\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: B3 H02E0101\narc: B6 V00B0100\narc: B7 V00B0100\narc: C3 H02E0601\narc: C6 H02E0601\narc: C7 V01N0101\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D2 Q2\narc: D3 V02S0201\narc: D6 V00B0000\narc: D7 S1_V02N0601\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: S1_V02S0001 Q2\narc: S1_V02S0101 F3\narc: S1_V02S0601 F6\narc: S3_V06S0203 Q7\narc: V00B0100 Q7\narc: V00T0100 F3\narc: V01S0100 Q7\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 1111110011001100\nword: SLICED.K0.INIT 1111001100110011\nword: SLICED.K1.INIT 1100111111001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R10C24:PLC2\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0203 N1_V01S0000\narc: H00R0100 H02W0701\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 H02W0601\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0501 S3_V06N0303\narc: V00B0000 H02W0401\narc: V00B0100 H02W0501\narc: W1_H02W0501 V02S0501\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0301 W3_H06E0003\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: B7 V01S0000\narc: C1 H00R0100\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: D6 E1_H01W0100\narc: D7 V00B0000\narc: E1_H01E0101 Q7\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F6\narc: LSR0 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: S3_V06S0203 Q7\narc: V00T0100 F1\narc: V01S0000 Q7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111110000\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 1100111111001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R10C25:PLC2\narc: E1_H02E0701 E1_H01W0100\narc: H00R0000 S1_V02N0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0401 V01N0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 W1_H02E0201\narc: V00T0100 S1_V02N0701\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0301 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A1 H02W0701\narc: B1 H00R0100\narc: B5 V02N0501\narc: C1 S1_V02N0401\narc: C4 Q4\narc: C5 V02S0001\narc: C6 H02E0601\narc: C7 V00T0000\narc: CE2 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D4 H02W0201\narc: D5 H02W0201\narc: D6 H02W0001\narc: D7 H02E0201\narc: E1_H01E0001 F1\narc: E1_H01E0101 F1\narc: E1_H02E0501 F7\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F1\narc: LSR0 V00T0100\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q4\narc: V01S0000 F6\narc: V01S0100 Q5\narc: W1_H02W0401 Q4\narc: W1_H02W0501 Q5\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1111111111000011\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001000100010000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R10C26:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 V02N0701\narc: H00L0100 V02N0301\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 V01N0001\narc: S1_V02S0201 W1_H02E0201\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02S0701\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 H01E0001\narc: W1_H02W0701 S1_V02N0701\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A1 S1_V02N0701\narc: A3 V02N0501\narc: B1 S1_V02N0101\narc: B3 H00L0000\narc: B5 V01S0000\narc: C1 V02N0601\narc: C3 H00L0100\narc: C4 V02N0001\narc: C5 V00T0000\narc: C7 E1_H02W0401\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D3 H01E0101\narc: D4 V01N0001\narc: D5 E1_H01W0100\narc: D7 V01N0001\narc: E1_H01E0001 F0\narc: E1_H01E0101 F7\narc: E1_H02E0001 F0\narc: E3_H06E0003 F0\narc: E3_H06E0103 F2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H01W0100 F4\narc: LSR1 H02W0301\narc: M0 V00B0000\narc: M2 V00T0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F0\narc: S3_V06S0303 Q5\narc: V01S0000 Q5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111110000\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1100111111001100\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 1111111111111110\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R10C27:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0701 N1_V02S0701\narc: H00L0100 V02N0101\narc: H00R0100 W1_H02E0701\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 W1_H02E0501\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 H02W0401\narc: V00T0000 H02E0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0301 H01E0101\narc: E3_H06E0303 W3_H06E0203\narc: A0 H02E0701\narc: A2 V02N0501\narc: B0 V00T0000\narc: B2 H00L0000\narc: B3 H00R0000\narc: B4 V02S0501\narc: B5 V01S0000\narc: B7 V00B0100\narc: C0 V02N0401\narc: C2 H02E0401\narc: C3 H00L0000\narc: C4 V02S0001\narc: C5 H02E0401\narc: C6 Q6\narc: C7 E1_H01E0101\narc: CE0 H02W0101\narc: CE1 H00L0100\narc: CE2 S1_V02N0601\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D2 V02N0201\narc: D3 V00T0100\narc: D4 V02N0601\narc: D5 V02S0601\narc: D6 V02N0401\narc: D7 V02N0401\narc: E1_H01E0001 Q7\narc: E1_H01E0101 Q6\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: H01W0100 Q6\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 F5\narc: N1_V02N0001 Q0\narc: N1_V02N0201 Q2\narc: N1_V02N0401 Q4\narc: N3_V06N0303 F5\narc: S1_V02S0701 F5\narc: S3_V06S0303 F5\narc: V00B0100 Q7\narc: V01S0000 Q3\narc: V01S0100 Q3\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 1111111111000011\nword: SLICEC.K0.INIT 1111110011001100\nword: SLICEC.K1.INIT 0000000000001100\nword: SLICEB.K0.INIT 0000010011000101\nword: SLICEB.K1.INIT 1111111100110000\nword: SLICEA.K0.INIT 1111111111111110\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R10C28:PLC2\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V02S0601\narc: H00L0000 H02E0201\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02S0601\narc: H00R0100 H02E0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 W1_H02E0001\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02S0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 H02E0201\narc: V00T0100 W1_H02E0101\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 V06S0303\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0601 W3_H06E0303\narc: S1_V02S0601 W3_H06E0303\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A0 N1_V02S0501\narc: A3 V00T0000\narc: B0 F1\narc: B2 H01W0100\narc: B3 H02W0101\narc: C0 H00L0100\narc: C1 E1_H02W0601\narc: C2 H00L0000\narc: C3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H02E0001\narc: D2 H00R0000\narc: D3 V00T0100\narc: E1_H01E0001 Q6\narc: E1_H02E0101 F3\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0100 Q4\narc: LSR0 V00B0000\narc: M4 V00B0100\narc: M6 E1_H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V02N0301 F1\narc: N3_V06N0103 F1\narc: S3_V06S0103 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111000001110111\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R10C29:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0601 V02S0601\narc: H00R0000 V02N0401\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 V01N0101\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 H02E0601\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 S1_V02N0101\narc: V00T0000 H02W0201\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 V06S0103\narc: W1_H02W0701 S1_V02N0701\narc: N1_V02N0301 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: CE1 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q6\narc: E3_H06E0003 Q0\narc: LSR0 H02E0501\narc: LSR1 H02W0301\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: V00B0000 Q4\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R10C2:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 E3_H06W0303\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0001 V01N0001\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 H06W0203\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\n\n.tile R10C30:PLC2\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 V02S0001\narc: H00L0100 V02S0101\narc: H00R0000 N1_V02S0601\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 W1_H02E0401\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 N1_V02S0201\narc: V00T0100 V02S0701\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 S1_V02N0401\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0101 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: A5 V00T0000\narc: A7 V02N0101\narc: B4 V01S0000\narc: B5 H00R0000\narc: B6 V02N0701\narc: B7 H02E0101\narc: C4 V00T0100\narc: C5 H02E0601\narc: C6 V00T0100\narc: C7 V02S0201\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CLK0 G_HPBX0000\narc: D4 V02N0601\narc: D5 H00L0100\narc: D6 H02W0001\narc: D7 V02N0401\narc: E3_H06E0203 F4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F5\narc: M0 V00B0000\narc: M2 H02W0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0101 F7\narc: S3_V06S0303 F6\narc: V00T0000 Q0\narc: V01S0000 Q0\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111110000001100\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 1111110000001100\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R10C31:PLC2\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0601 V02S0601\narc: H00R0000 H02W0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 H02W0401\narc: S3_V06S0103 E3_H06W0103\narc: V00B0100 V02N0301\narc: V00T0000 V02S0601\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 V06S0303\narc: E1_H02E0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: B0 V00B0000\narc: C0 N1_V01N0001\narc: C1 H00L0000\narc: CE1 V02S0201\narc: CE2 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 V02N0201\narc: F0 F5A_SLICE\narc: H00L0000 Q2\narc: M0 V00T0000\narc: M2 V00B0100\narc: M4 V00B0100\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: V00B0000 Q4\narc: V01S0000 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0011001100001111\nword: SLICEA.K1.INIT 1111111100001111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R10C32:PLC2\narc: E1_H02E0101 V06N0103\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 W1_H02E0101\narc: E3_H06E0303 W1_H02E0501\narc: H00L0100 N1_V02S0301\narc: H00R0000 N1_V02S0401\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 E1_H02W0701\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A1 E1_H01E0001\narc: B1 V00B0000\narc: C1 H02E0601\narc: C3 H00R0100\narc: CE2 H00R0000\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 N1_V02S0201\narc: D3 V00B0100\narc: E1_H01E0001 Q4\narc: E1_H02E0301 F3\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: M4 E1_H02W0401\narc: M6 E1_H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: V00B0000 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111111111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111010111110011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R10C33:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0303 V06N0303\narc: H00L0100 N1_V02S0301\narc: H00R0100 H02W0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0701 H02W0701\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02N0101\narc: V00T0000 V02N0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0501 E1_H02W0501\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: CE0 H02W0101\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: E1_H02E0201 Q0\narc: E1_H02E0401 Q6\narc: E1_H02E0601 Q4\narc: M0 V00T0100\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0401 Q6\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R10C34:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V06N0303\narc: H00L0000 V02N0201\narc: H00R0000 H02E0601\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 H06W0303\narc: V00B0000 V02S0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 H02E0001\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 E1_H02W0701\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0103\narc: A1 H01E0001\narc: A2 H01E0001\narc: B1 H02E0301\narc: B2 H02E0301\narc: B7 V00B0100\narc: C1 H00L0000\narc: C2 H00L0000\narc: C6 V00T0100\narc: C7 W1_H02E0401\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D2 H02W0201\narc: D6 W1_H02E0201\narc: D7 V01N0001\narc: E1_H01E0101 F6\narc: E1_H02E0401 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0000 Q4\narc: H01W0100 F1\narc: LSR0 H02W0301\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N3_V06N0103 F1\narc: V01S0000 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111000011111111\nword: SLICED.K1.INIT 0000110000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000010000100001\nword: SLICEB.K0.INIT 1000010000100001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R10C35:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0401 S1_V02N0401\narc: E3_H06E0203 V01N0001\narc: E3_H06E0303 V01N0101\narc: H00L0000 H02W0201\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0003 H06W0003\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 H02W0701\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02N0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0501 E1_H02W0501\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A7 W1_H02E0501\narc: B7 V02N0701\narc: C1 H02E0401\narc: C7 V00T0100\narc: CE1 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D7 H00R0100\narc: E1_H01E0101 F1\narc: E1_H02E0701 F7\narc: F1 F1_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q2\narc: LSR1 H02E0301\narc: M2 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F1\narc: N1_V01N0101 F1\narc: N1_V02N0301 F1\narc: S3_V06S0103 F1\narc: V01S0000 Q2\narc: V01S0100 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R10C36:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 V02S0001\narc: H00R0000 V02N0401\narc: H00R0100 H02E0701\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 H02W0401\narc: V00B0100 E1_H02W0501\narc: V00T0000 V02S0401\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 V02N0101\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02N0701\narc: E1_H02E0501 W3_H06E0303\narc: S3_V06S0203 W3_H06E0203\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: A4 V02N0101\narc: A5 N1_V01N0101\narc: A7 V02S0301\narc: B4 V00B0100\narc: B5 V02S0701\narc: B7 H02W0101\narc: C4 V01N0101\narc: C5 V02S0201\narc: C7 V00T0000\narc: CE2 S1_V02N0601\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 V00T0100\narc: D2 H02W0001\narc: D3 H02E0201\narc: D4 H02W0201\narc: D5 H00R0100\narc: D7 E1_H02W0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q6\narc: H01W0100 Q4\narc: M0 V00B0000\narc: M1 H00L0000\narc: M2 V00B0000\narc: M6 E1_H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F4\narc: V01S0100 Q6\narc: W1_H02W0401 Q6\narc: W3_H06W0203 F4\nword: SLICEC.K0.INIT 0000111000000100\nword: SLICEC.K1.INIT 0001000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R10C37:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0303 H01E0101\narc: H00L0000 V02N0001\narc: H00L0100 V02S0301\narc: H00R0000 W1_H02E0401\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 H02E0601\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0401 H01E0001\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 H01E0101\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 V02S0201\narc: V00B0100 V02N0301\narc: V00T0000 V02N0601\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0501 W3_H06E0303\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: A0 S1_V02N0501\narc: A1 S1_V02N0501\narc: A6 V00T0100\narc: A7 V00T0100\narc: B0 V00B0000\narc: B1 V00B0000\narc: B6 N1_V01S0000\narc: B7 N1_V01S0000\narc: C0 H00L0000\narc: C1 H00L0000\narc: C6 S1_V02N0001\narc: C7 S1_V02N0001\narc: D0 V00B0100\narc: D1 V00B0100\narc: D6 V01N0001\narc: D7 V01N0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 H02W0601\narc: M1 H00L0100\narc: M2 H02W0601\narc: M3 H00R0000\narc: M4 V00T0000\narc: M5 H00L0100\narc: M6 V00T0000\narc: W1_H02W0101 F3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000100001\nword: SLICEA.K1.INIT 0010000100000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000100001\nword: SLICED.K1.INIT 0010000100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R10C38:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0003 W1_H02E0001\narc: H00L0000 H02E0201\narc: H00R0000 H02W0401\narc: H00R0100 H02W0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0601 H06E0303\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02N0001\narc: V00T0000 H02E0201\narc: V00T0100 E1_H02W0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V01N0001\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 N1_V01S0100\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A6 V02S0301\narc: A7 H00R0000\narc: B0 V00B0000\narc: B1 H02W0101\narc: B3 H00R0100\narc: B5 V01S0000\narc: B6 V02N0501\narc: B7 H02E0101\narc: C0 H00L0000\narc: C1 V02S0401\narc: C3 V02S0601\narc: C5 V00T0100\narc: C6 V00T0000\narc: C7 H02E0601\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 H02E0001\narc: D3 H02E0001\narc: D5 H02E0001\narc: D6 H02E0001\narc: D7 H02E0001\narc: E1_H01E0001 F7\narc: E1_H01E0101 F6\narc: E1_H02E0701 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q5\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: N1_V01N0001 F3\narc: S1_V02S0001 F0\narc: S1_V02S0301 F1\narc: V01S0100 F1\narc: W3_H06W0003 Q3\narc: W3_H06W0103 Q1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000111111001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111111001100\nword: SLICEA.K0.INIT 0000111111001100\nword: SLICEA.K1.INIT 0000111111001100\nword: SLICED.K0.INIT 0000001100100010\nword: SLICED.K1.INIT 0000001100100010\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R10C39:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0501 V01N0101\narc: H00L0000 V02S0001\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 W1_H02E0501\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 V02S0001\narc: V00B0100 H02E0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 V06N0203\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: A0 H00L0000\narc: A2 V00B0000\narc: B0 V02S0301\narc: B2 V02S0301\narc: C0 N1_V01S0100\narc: C2 N1_V01S0100\narc: D0 H01E0101\narc: D2 H01E0101\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 H01E0001\narc: M1 E1_H02W0001\narc: M2 V00B0100\narc: M3 H02E0201\narc: M4 V00B0100\narc: M5 E1_H02W0001\narc: M6 V00B0100\nword: SLICEA.K0.INIT 0000000000010101\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000011101010\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R10C3:PLC2\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 H02E0201\narc: H00R0000 H02E0401\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H06W0103\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 H06W0103\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 H06W0203\narc: S3_V06S0003 H06W0003\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 H06W0303\narc: V00B0100 E1_H02W0501\narc: V00T0000 V02N0401\narc: CE0 H00L0000\narc: CE1 H00R0000\narc: CE2 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q6\narc: E1_H02E0601 Q6\narc: H01W0100 Q2\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 V00T0000\narc: M2 W1_H02E0601\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: V01S0000 Q0\narc: V01S0100 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R10C40:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 V02S0001\narc: H00L0100 V02S0101\narc: H00R0000 V02N0401\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S1_V02N0501\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 E1_H02W0201\narc: V00B0100 E1_H02W0701\narc: V00T0000 N1_V02S0601\narc: V00T0100 H02E0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0301 N3_V06S0003\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0103 E3_H06W0103\narc: CE2 H00L0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 V02N0001\narc: D2 E1_H02W0001\narc: D3 H02W0201\narc: E1_H02E0601 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 F1\narc: H01W0100 Q4\narc: M0 V00T0100\narc: M1 H00L0000\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0303 Q6\narc: W1_H02W0101 F1\narc: W1_H02W0401 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R10C41:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0701 V02N0701\narc: H00R0000 V02S0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0501 N1_V02S0401\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 E1_H02W0401\narc: V00B0100 S1_V02N0301\narc: V00T0000 N1_V02S0601\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 S1_V02N0401\narc: W3_H06W0303 E1_H02W0601\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q6\narc: H01W0000 Q2\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0000 Q4\narc: W1_H02W0201 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R10C42:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 V02S0401\narc: E1_H02E0701 W1_H02E0601\narc: H00L0000 S1_V02N0001\narc: H00L0100 V02N0301\narc: H00R0000 V02S0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 E1_H02W0201\narc: V00B0000 W1_H02E0401\narc: V00B0100 W1_H02E0701\narc: V00T0000 N1_V02S0601\narc: V00T0100 V02S0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0701 E1_H01W0100\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: S1_V02S0501 W3_H06E0303\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A0 H00L0100\narc: A5 H02E0701\narc: A6 S1_V02N0101\narc: A7 S1_V02N0301\narc: B0 H00R0100\narc: B2 H01W0100\narc: B3 V02N0301\narc: B5 H00R0000\narc: B6 V01S0000\narc: B7 S1_V02N0501\narc: C0 V02N0401\narc: C2 H00L0000\narc: C3 V02N0601\narc: C5 H02E0401\narc: C6 E1_H02W0601\narc: C7 N1_V02S0001\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D2 H02E0201\narc: D3 V00B0100\narc: D5 V00B0000\narc: D6 H01W0000\narc: D7 N1_V02S0401\narc: E3_H06E0003 Q0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: H01W0100 Q3\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: S1_V02S0401 F6\narc: S3_V06S0003 Q0\narc: V01S0000 F7\narc: W3_H06W0003 Q3\narc: W3_H06W0103 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000010101010\nword: SLICED.K0.INIT 0000000000001101\nword: SLICED.K1.INIT 0000000000001000\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 1100000011111111\nword: SLICEA.K0.INIT 1010000011101100\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R10C43:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V02N0301\narc: E3_H06E0103 V06N0103\narc: E3_H06E0203 H01E0001\narc: H00R0000 E1_H02W0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0003 E1_H01W0000\narc: V00B0000 N1_V02S0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02N0401\narc: V00T0100 H02E0101\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0401 V02N0401\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0601 W3_H06E0303\narc: N1_V02N0201 W3_H06E0103\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: A6 H00R0000\narc: A7 V02S0101\narc: B6 V00B0000\narc: B7 H02W0101\narc: C6 V00T0100\narc: C7 F6\narc: CE0 W1_H02E0101\narc: CE1 W1_H02E0101\narc: CE2 V02S0601\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D6 V02N0601\narc: D7 N1_V02S0401\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q2\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0203 Q4\narc: S3_V06S0203 F7\narc: S3_V06S0303 F6\narc: W1_H02W0601 F6\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000011001010\nword: SLICED.K1.INIT 1010101111101111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R10C44:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0601 H01E0001\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0203 W1_H02E0701\narc: E3_H06E0303 V01N0101\narc: H00L0000 W1_H02E0001\narc: H00R0100 V02N0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 H02E0201\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 W1_H02E0601\narc: V00B0100 E1_H02W0501\narc: V00T0100 W1_H02E0301\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0501 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0101 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: B3 H02W0301\narc: B5 V00B0100\narc: B7 H02E0101\narc: C0 H00R0100\narc: C1 H00L0100\narc: C3 H00L0000\narc: C5 E1_H02W0401\narc: C7 E1_H02W0401\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 F0\narc: D3 H02W0201\narc: D5 F0\narc: D7 F0\narc: E1_H02E0001 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: H01W0000 F7\narc: LSR0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: W3_H06W0003 F3\narc: W3_H06W0103 Q1\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111100\nword: SLICEA.K0.INIT 0000111100000000\nword: SLICEA.K1.INIT 0000111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R10C45:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 V02N0201\narc: H00L0100 V02N0301\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S1_V02N0301\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0601 H06W0303\narc: S3_V06S0003 H06E0003\narc: V00B0000 H02E0401\narc: V00B0100 H02E0501\narc: V00T0000 H02E0201\narc: V00T0100 H02W0101\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 E1_H01W0000\narc: E3_H06E0103 W3_H06E0103\narc: A0 V02S0501\narc: A1 H00L0000\narc: A3 H00L0100\narc: A4 N1_V01N0101\narc: A5 V02N0301\narc: B0 H02W0301\narc: B1 V02N0101\narc: B2 H01W0100\narc: B3 H00R0100\narc: B4 N1_V02S0701\narc: B5 V02S0701\narc: B6 E1_H02W0301\narc: B7 E1_H02W0101\narc: C0 V02N0401\narc: C1 N1_V01N0001\narc: C2 S1_V02N0401\narc: C3 V02S0601\narc: C4 V00T0000\narc: C5 V02S0201\narc: C6 V01N0101\narc: C7 W1_H02E0601\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 V00T0100\narc: D2 E1_H02W0201\narc: D3 V00B0100\narc: D4 W1_H02E0001\narc: D5 V02N0601\narc: D6 H01W0000\narc: D7 H01W0000\narc: E1_H02E0101 F1\narc: E3_H06E0303 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F4\narc: H01W0100 Q3\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M6 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F0\narc: N1_V01N0101 Q5\narc: S1_V02S0301 Q3\narc: S3_V06S0303 F6\narc: W3_H06W0003 Q3\narc: W3_H06W0103 F2\narc: W3_H06W0303 Q5\nword: SLICEC.K0.INIT 1010110000000000\nword: SLICEC.K1.INIT 1111100011111111\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 1111111111111000\nword: SLICEA.K0.INIT 1010110000000000\nword: SLICEA.K1.INIT 0000101100001111\nword: SLICED.K0.INIT 0000000000111111\nword: SLICED.K1.INIT 0000000011001111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R10C46:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 V02S0701\narc: H00L0000 V02N0001\narc: H00L0100 V02N0301\narc: H00R0100 E1_H02W0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 N1_V01S0000\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0501 H02W0501\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0203 N1_V02S0401\narc: V00B0100 H02E0501\narc: V00T0000 H02E0001\narc: V00T0100 H02E0101\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 V01N0101\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 E1_H02W0601\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0001 W3_H06E0003\narc: W3_H06W0003 V01N0001\narc: W3_H06W0103 E1_H01W0100\narc: A3 V02N0701\narc: B1 V02S0301\narc: B3 H00L0000\narc: C1 S1_V02N0401\narc: C3 H00L0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0001\narc: D3 V02N0201\narc: E3_H06E0103 F1\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q6\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0103 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0101011111011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R10C47:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 V02S0701\narc: E3_H06E0103 N3_V06S0103\narc: E3_H06E0203 N3_V06S0203\narc: H00L0000 N1_V02S0001\narc: H00L0100 N1_V02S0301\narc: H00R0000 W1_H02E0601\narc: H00R0100 V02N0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 S1_V02N0301\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 V01N0101\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 V02S0001\narc: V00T0000 N1_V02S0401\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 V01N0001\narc: E1_H02E0201 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: A0 H00R0000\narc: A3 H02E0501\narc: A5 V00B0000\narc: A6 H02E0701\narc: A7 H02E0501\narc: B0 H02E0301\narc: B2 H01W0100\narc: B3 E1_H02W0101\narc: B4 V01S0000\narc: B5 H02W0301\narc: B6 H02W0101\narc: B7 S1_V02N0501\narc: C0 H00L0000\narc: C2 S1_V02N0401\narc: C3 S1_V02N0601\narc: C4 S1_V02N0001\narc: C5 V00T0100\narc: C6 S1_V02N0201\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D2 V02N0201\narc: D3 E1_H02W0001\narc: D4 V02N0601\narc: D5 H00L0100\narc: D6 E1_H01W0100\narc: D7 H00R0100\narc: E1_H01E0001 Q0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q3\narc: LSR1 V00T0000\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: V00B0100 F7\narc: V01S0000 Q5\narc: V01S0100 F6\narc: W1_H02W0501 Q5\narc: W3_H06W0003 Q0\narc: W3_H06W0103 F2\narc: W3_H06W0203 F4\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 1000000010101010\nword: SLICED.K1.INIT 1000000010101010\nword: SLICEC.K0.INIT 1100111111000000\nword: SLICEC.K1.INIT 1111111111111000\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 0011101110111011\nword: SLICEA.K0.INIT 1111111111111000\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R10C48:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0701 V02S0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 V01N0101\narc: H00L0000 V02S0001\narc: H00L0100 E1_H02W0101\narc: H00R0000 V02N0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 H01E0001\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 E3_H06W0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 H06E0303\narc: V00B0100 H02E0501\narc: V00T0000 V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 V06S0303\narc: W1_H02W0701 V02N0701\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0103 E1_H02W0201\narc: W3_H06W0303 V06S0303\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A6 W1_H02E0701\narc: A7 V02N0101\narc: B1 H00R0100\narc: B2 H00L0000\narc: B4 V02S0501\narc: B6 H02E0101\narc: B7 H02E0301\narc: C1 H00L0100\narc: C2 H02W0401\narc: C3 V02S0601\narc: C4 S1_V02N0201\narc: C5 V00T0100\narc: C6 H02E0401\narc: C7 H02E0401\narc: D1 W1_H02E0001\narc: D2 H00R0000\narc: D3 V00B0100\narc: D4 S1_V02N0601\narc: D5 S1_V02N0401\narc: D6 H01W0000\narc: D7 S1_V02N0401\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F2\narc: M2 V00T0000\narc: M4 V00T0000\narc: N1_V01N0001 F7\narc: W1_H02W0601 F6\nword: SLICED.K0.INIT 1000000010101010\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000001111001111\nword: SLICEC.K1.INIT 1111000011111111\nword: SLICEB.K0.INIT 0000001111001111\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R10C49:PLC2\narc: E1_H02E0401 V06N0203\narc: E3_H06E0103 V06S0103\narc: E3_H06E0303 H01E0101\narc: H00L0000 V02N0001\narc: H00L0100 V02N0101\narc: H00R0100 V02S0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 H06W0003\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 H02W0701\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 N1_V02S0001\narc: V00T0100 V02S0701\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 S1_V02N0701\narc: E1_H01E0101 W3_H06E0203\narc: E3_H06E0203 W3_H06E0203\narc: A0 H02E0701\narc: A1 W1_H02E0701\narc: A3 H02E0701\narc: B0 H02E0101\narc: B1 H00R0100\narc: B2 H00L0000\narc: B3 H02E0101\narc: B6 V00B0000\narc: C0 N1_V01S0100\narc: C1 E1_H02W0401\narc: C2 H00L0100\narc: C3 V02S0401\narc: C6 E1_H02W0401\narc: C7 N1_V02S0001\narc: D0 H00R0000\narc: D1 V02S0001\narc: D2 H02W0001\narc: D3 V02S0201\narc: D6 S1_V02N0401\narc: D7 V01N0001\narc: E1_H01E0001 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 F6\narc: M6 V00T0100\narc: N1_V01N0101 F1\narc: S1_V02S0001 F0\narc: S1_V02S0201 F2\nword: SLICEB.K0.INIT 0000000000111111\nword: SLICEB.K1.INIT 1000000010101010\nword: SLICEA.K0.INIT 1000000010101010\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000110000111111\nword: SLICED.K1.INIT 1111000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R10C4:PLC2\narc: E1_H02E0301 H01E0101\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 S1_V02N0201\narc: H00L0100 V02S0301\narc: H00R0000 W1_H02E0601\narc: H00R0100 H02E0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 H02W0601\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0201\narc: V00B0100 H02W0701\narc: V00T0000 H02W0201\narc: V00T0100 H02E0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 E3_H06W0203\narc: W3_H06W0003 E1_H01W0000\narc: A4 V02N0301\narc: A5 W1_H02E0701\narc: A7 N1_V01N0101\narc: B4 V01S0000\narc: B5 H00L0000\narc: B7 V00T0000\narc: C4 E1_H01E0101\narc: C5 V00B0100\narc: C7 V02S0201\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 H00L0100\narc: D5 V00B0000\narc: D7 H00R0100\narc: E1_H01E0101 F7\narc: E3_H06E0203 F4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M0 H01E0001\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: N1_V01N0101 Q2\narc: S3_V06S0003 Q0\narc: V01S0000 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R10C50:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0501 E1_H01W0100\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0203 V06S0203\narc: H00R0000 H02E0401\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 V02N0001\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0401\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0501 V06S0303\narc: W1_H02W0701 N1_V02S0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: A5 V00B0000\narc: B4 V01S0000\narc: B5 H00R0000\narc: C4 E1_H02W0601\narc: C5 V00B0100\narc: CLK0 G_HPBX0000\narc: D4 H02W0001\narc: D5 V02N0601\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: LSR1 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: V01S0000 Q5\narc: W3_H06W0203 F4\narc: W3_H06W0303 Q5\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1111111111111000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R10C51:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0101 V06N0103\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 V02S0401\narc: E1_H02E0701 V02S0701\narc: E3_H06E0303 S3_V06N0303\narc: H00R0000 V02N0601\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 H06E0203\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 V01N0101\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02N0201\narc: V00B0100 V02S0301\narc: V00T0000 H02E0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 E3_H06W0303\narc: H01W0000 W3_H06E0103\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q2\narc: E1_H02E0201 Q2\narc: E1_H02E0601 Q6\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: H01W0100 Q2\narc: M0 V00B0000\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: S1_V02S0401 Q6\narc: V01S0000 Q2\narc: V01S0100 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R10C52:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 H01E0101\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 H01E0101\narc: H00L0000 H02W0201\narc: H00L0100 V02N0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0001 H02W0001\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 H01E0001\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 H02E0401\narc: V00T0000 V02S0401\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: S1_V02S0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 E1_H01E0001\narc: A1 H00L0000\narc: A2 V02N0501\narc: A3 V01N0101\narc: A5 W1_H02E0501\narc: A7 V02N0101\narc: B0 H02E0101\narc: B1 V00B0000\narc: B2 H02E0301\narc: B3 H02E0101\narc: B5 E1_H02W0101\narc: B7 H02E0301\narc: C0 H00L0100\narc: C1 V02S0401\narc: C2 S1_V02N0401\narc: C3 N1_V02S0601\narc: C5 H02E0401\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H00R0000\narc: D2 V00T0100\narc: D3 V00B0100\narc: D5 E1_H02W0201\narc: D7 H00R0100\narc: E1_H01E0001 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: V00B0100 F7\narc: V00T0100 F3\narc: V01S0100 F1\narc: W3_H06W0003 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000101000001100\nword: SLICEA.K0.INIT 1111111111010101\nword: SLICEA.K1.INIT 0000101000001100\nword: SLICEB.K0.INIT 1000000011111111\nword: SLICEB.K1.INIT 0000000000010101\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 0010101111010111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R10C53:PLC2\narc: E1_H02E0301 W1_H02E0201\narc: H00L0000 N1_V02S0201\narc: H00L0100 N1_V02S0101\narc: H00R0000 H02W0401\narc: H00R0100 H02E0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0001 H02E0001\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 H02E0401\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 W1_H02E0601\narc: V00B0100 N1_V02S0101\narc: V00T0000 W1_H02E0201\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 E1_H02W0601\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0101 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A0 H02W0701\narc: A1 N1_V02S0701\narc: A3 V00T0000\narc: A5 V00B0000\narc: A7 H02E0701\narc: B0 S1_V02N0101\narc: B1 V02N0101\narc: B3 H00R0100\narc: B5 H02E0301\narc: B7 N1_V02S0701\narc: C0 H00L0000\narc: C1 H00L0100\narc: C3 N1_V01N0001\narc: C5 H02E0601\narc: C7 V02N0201\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 H00R0000\narc: D3 S1_V02N0201\narc: D5 H02W0201\narc: D7 H02W0201\narc: E1_H01E0001 F2\narc: E1_H01E0101 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: M2 V00B0100\narc: M4 E1_H02W0401\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: V00T0100 F1\narc: V01S0100 F4\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 1111111111010101\nword: SLICEA.K1.INIT 0000110000001010\nword: SLICED.K0.INIT 1111111111111111\nword: SLICED.K1.INIT 0010101111010111\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 0100110110110111\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 0010101111010111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R10C54:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 V02S0701\narc: H00L0000 H02W0201\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02S0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0201 H06E0103\narc: S1_V02S0701 V01N0101\narc: S3_V06S0103 H06E0103\narc: V00B0000 S1_V02N0201\narc: V00B0100 S1_V02N0301\narc: V00T0000 W1_H02E0201\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 V02S0401\narc: W1_H02W0701 H01E0101\narc: H01W0000 W3_H06E0103\narc: S1_V02S0101 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0203 V06S0203\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A0 E1_H01E0001\narc: A1 S1_V02N0501\narc: A2 H01E0001\narc: A3 H02W0501\narc: A5 H02W0701\narc: A7 W1_H02E0701\narc: B0 V02N0101\narc: B1 V00T0000\narc: B2 V02N0101\narc: B3 H00R0100\narc: B4 E1_H02W0301\narc: B5 E1_H02W0101\narc: B7 S1_V02N0501\narc: C0 V02N0601\narc: C1 H00L0100\narc: C2 H00L0000\narc: C3 H00L0100\narc: C4 N1_V02S0201\narc: C5 V02N0201\narc: C7 E1_H02W0601\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H00R0000\narc: D2 V00T0100\narc: D3 H00R0000\narc: D4 V02S0601\narc: D5 H02W0001\narc: D7 V00B0000\narc: E1_H01E0001 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q0\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F5\narc: S3_V06S0203 F4\narc: V00T0100 F3\narc: V01S0000 Q2\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0000000000111111\nword: SLICEC.K1.INIT 1000000010101010\nword: SLICEA.K0.INIT 1111111111010101\nword: SLICEA.K1.INIT 0000110000001010\nword: SLICEB.K0.INIT 1111111111010101\nword: SLICEB.K1.INIT 0000110000001010\nword: SLICED.K0.INIT 1111111111111111\nword: SLICED.K1.INIT 0010101111010111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R10C55:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0401 V06N0203\narc: E1_H02E0701 V02S0701\narc: H00L0000 N1_V02S0001\narc: H00L0100 W1_H02E0301\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 S3_V06N0103\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02E0501\narc: V00T0000 H02E0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 V02S0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0701 V02S0701\narc: E1_H01E0101 W3_H06E0203\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A1 H00L0100\narc: A2 V02S0701\narc: A3 V02N0701\narc: A4 N1_V01N0101\narc: A5 N1_V02S0301\narc: A7 H02E0701\narc: B1 H00R0100\narc: B2 H02W0101\narc: B3 V02S0301\narc: B4 V02S0501\narc: B5 V00B0100\narc: B7 H02E0101\narc: C1 H00L0000\narc: C2 H02E0601\narc: C3 H02E0601\narc: C4 V00T0100\narc: C5 S1_V02N0201\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 E1_H02W0001\narc: D3 H02E0001\narc: D4 H01W0000\narc: D5 V02N0401\narc: D7 H02W0201\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: H01W0100 F7\narc: M0 V00B0000\narc: MUXCLK2 CLK0\narc: N1_V01N0101 F0\narc: V01S0000 F2\narc: W1_H02W0601 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000010101010\nword: SLICEB.K0.INIT 1000000010101010\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1111111111010101\nword: SLICEC.K1.INIT 0000110000001010\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0011100110011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R10C56:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 V02S0401\narc: H00L0000 H02W0201\narc: H00L0100 H02W0101\narc: H00R0000 W1_H02E0401\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0701 H02W0701\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02W0501\narc: V00T0000 H02W0201\narc: V00T0100 H02W0301\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0701 V02S0701\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A1 H00L0100\narc: A5 V02S0101\narc: A7 H02E0701\narc: B1 V02S0301\narc: B2 H02E0101\narc: B5 V02S0501\narc: B6 V02N0701\narc: B7 W1_H02E0101\narc: C1 H00R0100\narc: C2 H00L0000\narc: C3 V02S0601\narc: C5 V00T0000\narc: C6 V00T0100\narc: C7 E1_H01E0101\narc: D1 H00R0000\narc: D2 V02N0001\narc: D3 S1_V02N0001\narc: D5 V02N0601\narc: D6 H01W0000\narc: D7 V02N0601\narc: E1_H01E0101 F2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M0 V00B0100\narc: M2 V00B0000\narc: N1_V01N0001 F5\narc: V01S0000 F0\narc: W3_H06W0303 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000111111\nword: SLICED.K1.INIT 1000101000001010\nword: SLICEB.K0.INIT 0000110000111111\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0010110110110111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R10C57:PLC2\narc: E1_H02E0501 V02N0501\narc: H00L0000 H02E0201\narc: H00L0100 H02W0101\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02S0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S3_V06N0203\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0401 V01N0001\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02W0401\narc: V00B0100 E1_H02W0701\narc: V00T0000 V02S0601\narc: V00T0100 V02N0501\narc: W1_H02W0201 V06N0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 E1_H02W0401\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: S1_V02S0101 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: S3_V06S0003 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A5 N1_V02S0101\narc: A6 V00T0100\narc: A7 V02N0101\narc: B0 V00T0000\narc: B2 H00R0100\narc: B5 S1_V02N0701\narc: B6 V01S0000\narc: B7 V02N0701\narc: C0 H00L0100\narc: C1 V02S0601\narc: C2 H00L0000\narc: C3 H00R0100\narc: C5 H02W0601\narc: C6 H02E0401\narc: C7 E1_H02W0401\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 V00B0100\narc: D2 H00R0000\narc: D3 E1_H02W0201\narc: D5 N1_V02S0601\narc: D6 H01W0000\narc: D7 N1_V02S0401\narc: E1_H01E0001 F0\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M0 V00B0000\narc: M2 V00B0000\narc: M4 E1_H02W0401\narc: MUXCLK3 CLK0\narc: V01S0000 F4\narc: W1_H02W0001 F2\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1111111110110011\nword: SLICED.K1.INIT 0000101000001100\nword: SLICEA.K0.INIT 0000110000111111\nword: SLICEA.K1.INIT 1111000011111111\nword: SLICEB.K0.INIT 0000001111001111\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 0011100110011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R10C58:PLC2\narc: H00L0000 V02N0201\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 H02W0401\narc: S3_V06S0303 H01E0101\narc: V00B0000 V02N0201\narc: V00B0100 V02N0301\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: S3_V06S0103 W3_H06E0103\narc: W3_H06W0003 N1_V01S0000\narc: A4 S1_V02N0301\narc: A5 H02E0501\narc: A7 S1_V02N0301\narc: B4 H00L0000\narc: B5 V00B0100\narc: B7 V00B0000\narc: C4 S1_V02N0201\narc: C5 E1_H02W0601\narc: C7 H02W0401\narc: CLK0 G_HPBX0000\narc: D4 H00R0100\narc: D5 H01W0000\narc: D7 V02S0401\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0000 F7\narc: MUXCLK2 CLK0\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000110000001010\nword: SLICEC.K0.INIT 1000000011111111\nword: SLICEC.K1.INIT 0000000000010011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R10C59:PLC2\narc: N1_V02N0401 E1_H02W0401\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 V01N0001\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 N1_V01S0100\narc: H01W0100 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\n\n.tile R10C5:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 S1_V02N0601\narc: H00R0000 V02N0401\narc: H00R0100 E1_H02W0501\narc: H01W0000 E3_H06W0103\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 H06W0003\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0401 E1_H01W0000\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 H02W0401\narc: V00B0100 H02E0701\narc: V00T0000 S1_V02N0401\narc: V00T0100 V02N0701\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 E1_H02W0701\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A7 N1_V01N0101\narc: B7 H02E0301\narc: C7 V00B0100\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: E1_H02E0701 F7\narc: F7 F7_SLICE\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M0 V00T0000\narc: M2 W1_H02E0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q4\narc: S1_V02S0601 Q4\narc: S3_V06S0103 Q2\narc: W1_H02W0201 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R10C60:PLC2\narc: N1_V02N0601 H06E0303\narc: W1_H02W0101 V02N0101\narc: W1_H02W0601 S1_V02N0601\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\n\n.tile R10C61:PLC2\narc: N1_V02N0301 H01E0101\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0401 W3_H06E0203\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\n\n.tile R10C62:PLC2\narc: N1_V02N0301 V01N0101\narc: N1_V02N0501 H01E0101\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\n\n.tile R10C63:PLC2\narc: E1_H02E0201 S3_V06N0103\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0601 W3_H06E0303\n\n.tile R10C64:PLC2\narc: N1_V02N0201 H02E0201\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0303 N1_V02S0501\n\n.tile R10C67:PLC2\narc: S3_V06S0003 W3_H06E0003\n\n.tile R10C68:PLC2\narc: E3_H06E0103 W3_H06E0103\n\n.tile R10C6:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0401 E3_H06W0203\narc: H00L0100 V02N0101\narc: H00R0100 E1_H02W0501\narc: H01W0000 E3_H06W0103\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0401 E1_H02W0101\narc: W3_H06W0003 E1_H02W0001\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A5 V00T0000\narc: A6 H02E0701\narc: A7 S1_V02N0101\narc: B5 V01S0000\narc: B6 E1_H02W0301\narc: B7 H02E0301\narc: C5 E1_H02W0401\narc: C6 E1_H01E0101\narc: C7 W1_H02E0601\narc: CE0 H00L0100\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D5 V02N0601\narc: D6 H02W0201\narc: D7 V00B0000\narc: E1_H01E0001 F7\narc: E1_H01E0101 F5\narc: E1_H02E0201 Q2\narc: E3_H06E0303 F6\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 H02E0601\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: V00T0000 Q0\narc: V01S0000 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R10C70:PLC2\narc: N1_V02N0301 S1_V02N0301\n\n.tile R10C7:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0601 V06S0303\narc: H00L0000 H02E0001\narc: H00L0100 V02N0101\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0501 E3_H06W0303\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 V02S0301\narc: V00T0100 V02N0701\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 E3_H06W0203\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A1 E1_H01E0001\narc: B1 V01N0001\narc: C1 H00L0000\narc: CE1 H02E0101\narc: CE2 E1_H02W0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M2 H02W0601\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q4\narc: S3_V06S0303 Q6\narc: V00T0000 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R10C8:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 E3_H06W0303\narc: H00L0100 V02N0301\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H06W0203\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0201 V01N0001\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 E1_H02W0601\narc: V00B0100 E1_H02W0701\narc: V00T0000 W1_H02E0201\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 E3_H06W0203\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: C3 E1_H02W0401\narc: CE0 H00L0100\narc: CE2 H00L0100\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D3 H02E0201\narc: F3 F3_SLICE\narc: H01W0000 Q6\narc: H01W0100 F3\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M0 V00T0000\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q3\narc: N1_V02N0101 Q3\narc: N3_V06N0003 Q3\narc: S3_V06S0003 Q0\narc: S3_V06S0203 Q4\narc: W3_H06W0003 Q3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R10C9:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 V02N0301\narc: H00L0000 W1_H02E0001\narc: H00R0000 H02E0401\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 H06W0103\narc: S3_V06S0203 H06W0203\narc: V00B0100 H02E0501\narc: V00T0100 V02S0501\narc: W1_H02W0101 E1_H01W0100\narc: W3_H06W0003 E1_H02W0301\narc: W3_H06W0303 E3_H06W0303\narc: A7 H00L0000\narc: B7 V02S0701\narc: C7 V00T0100\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D7 W1_H02E0201\narc: E1_H01E0001 Q0\narc: E3_H06E0203 Q4\narc: F7 F7_SLICE\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 E1_H02W0601\narc: M2 V00T0000\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q4\narc: S3_V06S0103 Q2\narc: V00T0000 Q0\narc: V01S0000 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R11C10:PLC2\narc: E1_H02E0301 V02N0301\narc: H00R0000 V02S0601\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0601 H06W0303\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 H02E0601\narc: S3_V06S0103 H06W0103\narc: V00B0100 E1_H02W0701\narc: V00T0100 V02N0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V02N0401\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: C6 V00B0100\narc: C7 V02N0001\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D6 H02W0001\narc: D7 H02W0201\narc: E1_H01E0001 F7\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: H01W0100 F6\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 H02W0601\narc: M2 V00T0000\narc: M4 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q4\narc: S1_V02S0701 F7\narc: S3_V06S0203 F7\narc: S3_V06S0303 F6\narc: V00T0000 Q0\narc: V01S0000 Q2\narc: V01S0100 F7\narc: W1_H02W0501 F7\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R11C11:PLC2\narc: E1_H02E0101 S3_V06N0103\narc: H00L0000 H02W0001\narc: H00R0100 V02N0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0201 H02W0201\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02S0101\narc: V00T0000 H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V06S0203\narc: S3_V06S0103 W3_H06E0103\narc: W3_H06W0003 E1_H02W0301\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A2 E1_H01E0001\narc: A5 V00B0000\narc: B2 F3\narc: B5 H00L0000\narc: C2 H02W0601\narc: C3 N1_V01S0100\narc: C5 V00T0000\narc: CE0 H02W0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 V01S0100\narc: D3 V00B0100\narc: D5 V02N0601\narc: E1_H01E0001 Q0\narc: E1_H02E0201 F2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00T0100\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR3 LSR1\narc: V00B0000 Q6\narc: V01S0100 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0001001100000000\nword: SLICEB.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R11C12:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 V01N0101\narc: H00L0100 H02W0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 E1_H02W0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N3_V06S0303\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 S1_V02N0101\narc: V00T0000 H02W0001\narc: V00T0100 V02S0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 V02N0601\narc: N1_V02N0201 W3_H06E0103\narc: C4 V00T0100\narc: C5 V02S0201\narc: CE0 H00R0100\narc: CE1 E1_H02W0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 V02S0401\narc: D5 H00L0100\narc: E1_H01E0101 Q0\narc: E1_H02E0401 Q6\narc: E1_H02E0701 F5\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q0\narc: H01W0100 F4\narc: LSR0 W1_H02E0301\narc: LSR1 W1_H02E0301\narc: M0 V00B0100\narc: M2 H02W0601\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F5\narc: N1_V02N0601 Q6\narc: S3_V06S0203 F4\narc: V01S0000 F5\narc: W1_H02W0001 Q2\narc: W1_H02W0701 F5\narc: W3_H06W0203 F4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000000011110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R11C13:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0601 V06S0303\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 E1_H02W0201\narc: H00R0000 H02W0401\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 E1_H02W0501\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H02E0401\narc: S3_V06S0203 N1_V01S0000\narc: V00B0100 V02S0101\narc: V00T0000 S1_V02N0601\narc: V00T0100 H02E0101\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0601 V06N0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A3 V00B0000\narc: B3 H02E0301\narc: C3 H00L0000\narc: CE0 H02W0101\narc: CE2 H02W0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: F3 F3_SLICE\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00B0000\narc: M4 E1_H02W0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q4\narc: S3_V06S0003 Q0\narc: V00B0000 Q6\narc: V01S0100 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R11C14:PLC2\narc: H00L0000 H02W0001\narc: H00R0000 V02N0601\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H06W0103\narc: S1_V02S0301 E1_H01W0100\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 S1_V02N0201\narc: V00T0100 V02N0501\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0701 N1_V01S0100\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: B3 H01W0100\narc: C3 N1_V01N0001\narc: CE0 H00R0000\narc: CE1 H00L0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D2 V02N0201\narc: D3 V02N0001\narc: E1_H01E0001 Q0\narc: E1_H02E0001 Q2\narc: E1_H02E0401 Q6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0100 Q2\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 E1_H02W0601\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q6\narc: N3_V06N0003 F3\narc: V01S0000 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R11C15:PLC2\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0203 V01N0001\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0601 E1_H02W0601\narc: V00T0100 V02N0501\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N3_V06S0303\narc: N1_V02N0301 W3_H06E0003\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: CLK0 G_HPBX0000\narc: E3_H06E0003 Q0\narc: H01W0100 Q6\narc: LSR1 V00T0100\narc: M0 H01E0001\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R11C16:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V02S0701\narc: H00R0100 V02S0701\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0601 H02W0601\narc: S3_V06S0303 N1_V01S0100\narc: V00B0100 E1_H02W0501\narc: V00T0000 V02N0601\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0601 E1_H01W0000\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A3 V00B0000\narc: B3 H00L0000\narc: C3 H00R0100\narc: CE0 E1_H02W0101\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: D3 V02N0001\narc: E1_H02E0301 F3\narc: F3 F3_SLICE\narc: H00L0000 Q0\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00T0100\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: V00B0000 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R11C17:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V01N0001\narc: H00L0000 H02W0201\narc: H00R0000 N1_V02S0601\narc: H00R0100 H02E0701\narc: H01W0000 E3_H06W0103\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0201 V01N0001\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0103 H06W0103\narc: V00B0000 H02E0601\narc: V00B0100 S1_V02N0101\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 S3_V06N0303\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A3 V00T0000\narc: B3 V02N0301\narc: C3 H00R0100\narc: CE0 V02S0201\narc: CE2 H00L0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: E1_H02E0301 F3\narc: F3 F3_SLICE\narc: H01W0100 Q4\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 V00B0100\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: V00T0000 Q0\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R11C18:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 E3_H06W0303\narc: H00L0000 H02W0001\narc: H00R0000 H02W0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H06E0203\narc: S1_V02S0101 H02W0101\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 V02S0301\narc: V00T0100 W1_H02E0301\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0501 S1_V02N0501\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 E1_H01E0001\narc: A1 V01N0101\narc: A3 H02W0701\narc: A4 F5\narc: A5 W1_H02E0501\narc: A7 E1_H01W0000\narc: B0 H02E0301\narc: B1 E1_H02W0101\narc: B3 H00R0100\narc: B4 F3\narc: B5 H00L0000\narc: B7 E1_H02W0301\narc: C0 E1_H02W0601\narc: C1 N1_V01S0100\narc: C3 H02E0401\narc: C4 V00T0100\narc: C5 V00B0100\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H00R0000\narc: D3 V02N0001\narc: D4 V01N0001\narc: D5 S1_V02N0601\narc: D7 V02N0601\narc: E1_H01E0001 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q4\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: V01S0100 F7\narc: W1_H02W0001 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0111111111111111\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0111111111111111\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R11C19:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 V02N0201\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H02W0401\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 E3_H06W0103\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 E1_H02W0601\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0203\narc: A0 V02N0501\narc: B2 H01W0100\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 V01S0000\narc: CE1 V02N0201\narc: CE2 H00L0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q3\narc: H01W0100 Q2\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q6\narc: N1_V02N0601 Q4\narc: S1_V02S0001 Q2\narc: S1_V02S0301 Q3\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V01S0000 Q7\narc: V01S0100 Q5\narc: W1_H02W0701 Q7\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R11C20:PLC2\narc: E3_H06E0003 V06S0003\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 E1_H01W0000\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 N3_V06S0303\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E1_H02W0701\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H01W0100\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V01S0000\narc: B6 V00B0000\narc: B7 V00B0100\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 S1_V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: E1_H02E0101 Q3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q6\narc: H01W0100 Q2\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q4\narc: N1_V02N0501 Q7\narc: N1_V02N0601 Q4\narc: N1_V02N0701 Q5\narc: S1_V02S0201 Q0\narc: S1_V02S0301 Q1\narc: S1_V02S0701 Q5\narc: V00B0000 Q6\narc: V00B0100 Q7\narc: V00T0000 Q0\narc: V01S0000 Q5\narc: V01S0100 Q0\narc: W1_H02W0201 Q2\narc: W1_H02W0301 Q3\narc: W1_H02W0501 Q7\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R11C21:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0601 V06S0303\narc: E3_H06E0203 W1_H02E0401\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0301 H01E0101\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 E1_H01W0100\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 V06S0303\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0303 V06S0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 H02W0301\narc: B6 V00B0000\narc: B7 V00B0100\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q2\narc: LSR0 W1_H02E0301\narc: LSR1 W1_H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q3\narc: N1_V02N0401 Q4\narc: N1_V02N0601 Q6\narc: N1_V02N0701 Q7\narc: S1_V02S0601 Q4\narc: S1_V02S0701 Q5\narc: V00B0000 Q6\narc: V00B0100 Q7\narc: V00T0000 Q0\narc: V01S0000 Q2\narc: V01S0100 Q0\narc: W1_H02W0101 Q1\narc: W1_H02W0501 Q7\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R11C22:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 V02N0201\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0601 H02E0601\narc: S3_V06S0203 N3_V06S0203\narc: W1_H02W0301 H01E0101\narc: W1_H02W0501 E1_H01W0100\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H01W0100\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 V01S0000\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q0\narc: H01W0100 Q2\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q1\narc: N1_V01N0101 Q6\narc: S1_V02S0101 Q1\narc: S1_V02S0401 Q4\narc: S1_V02S0501 Q7\narc: S1_V02S0701 Q5\narc: S3_V06S0103 Q2\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V00T0000 Q0\narc: V01S0000 Q7\narc: V01S0100 Q5\narc: W1_H02W0001 Q0\narc: W1_H02W0101 Q3\narc: W1_H02W0401 Q6\narc: W1_H02W0701 Q7\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R11C23:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0101 V01N0101\narc: E1_H02E0701 V06S0203\narc: E3_H06E0103 W1_H02E0101\narc: H00L0000 V02N0001\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 N1_V01S0100\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02N0101\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0301 V02N0301\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A7 Q7\narc: B0 V00T0000\narc: B1 Q1\narc: B6 V01S0000\narc: B7 V01S0000\narc: C6 H02E0601\narc: C7 H02E0601\narc: CE0 H00L0000\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D6 V00B0000\narc: D7 V00B0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q1\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q7\narc: V00T0000 Q0\narc: V01S0000 Q6\narc: V01S0100 Q0\nword: SLICED.K0.INIT 1111001100110011\nword: SLICED.K1.INIT 1111100110011001\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R11C24:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0601 V02N0601\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 W1_H02E0001\narc: H00L0100 V02N0101\narc: H00R0000 V02N0401\narc: H00R0100 V02N0501\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 H02W0601\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 V02N0601\narc: V00T0100 H02W0101\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A0 V02N0701\narc: A2 V02N0501\narc: A5 V02N0101\narc: A6 V02N0101\narc: B0 H02W0101\narc: B2 H02W0101\narc: B4 H02W0101\narc: B5 H02W0101\narc: B6 H02W0101\narc: C0 V02N0601\narc: C1 H00L0100\narc: C2 V02N0601\narc: C3 H00R0100\narc: C4 V00B0100\narc: C5 V00T0000\narc: C6 V00B0100\narc: C7 V02N0201\narc: D0 H00R0000\narc: D1 V00T0100\narc: D2 H00R0000\narc: D3 V00B0100\narc: D4 V02N0401\narc: D5 V02N0401\narc: D6 V02N0401\narc: D7 V02N0401\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00B0000\narc: M1 H02E0001\narc: M2 V00B0000\narc: M3 H00L0000\narc: M4 V00B0000\narc: M5 H02E0001\narc: M6 V00B0000\narc: V01S0100 F3\nword: SLICEA.K0.INIT 1011101110110000\nword: SLICEA.K1.INIT 1111000011111111\nword: SLICEB.K0.INIT 1010111110001100\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICEC.K0.INIT 1111111111111100\nword: SLICEC.K1.INIT 1010101010101000\nword: SLICED.K0.INIT 1010100011111100\nword: SLICED.K1.INIT 1111000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R11C25:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 V06S0303\narc: H00R0000 E1_H02W0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0601 V01N0001\narc: S3_V06S0103 E3_H06W0103\narc: V00T0100 V02N0501\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0601 S1_V02N0601\narc: N1_V02N0701 W3_H06E0203\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: B2 W1_H02E0101\narc: B3 W1_H02E0101\narc: C2 V02N0401\narc: C3 H02E0601\narc: D2 V02N0001\narc: D3 V02N0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00R0100\narc: M2 V00T0100\narc: M3 H00R0000\narc: M4 V00T0100\narc: M5 H00R0100\narc: M6 V00T0100\narc: N1_V01N0001 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111001111110000\nword: SLICEB.K1.INIT 1111111100110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R11C26:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0401 V02N0401\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0103 W1_H02E0101\narc: H00L0000 E1_H02W0201\narc: H00R0000 H02W0601\narc: H00R0100 V02N0501\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 V01N0101\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02N0401\narc: V00T0100 N1_V02S0501\narc: E1_H02E0301 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A1 V02N0701\narc: A5 E1_H02W0701\narc: A6 H00L0000\narc: A7 E1_H02W0501\narc: B1 V02N0101\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V00B0100\narc: B7 E1_H02W0301\narc: C1 W1_H02E0601\narc: C4 H02E0601\narc: C5 E1_H02W0401\narc: C6 E1_H01E0101\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D4 V02N0601\narc: D5 H02W0001\narc: D6 H02W0201\narc: D7 H02E0201\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: E3_H06E0203 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q5\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 V00T0000\narc: M1 H00R0100\narc: M2 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F1\narc: N1_V02N0101 F1\narc: N1_V02N0301 F1\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 1111110000001100\nword: SLICEC.K1.INIT 1000111111111111\nword: SLICED.K0.INIT 1000111111111111\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0100010001000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R11C27:PLC2\narc: E1_H02E0501 V02S0501\narc: H00L0100 V02N0301\narc: H00R0000 H02E0401\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0501 S3_V06N0303\narc: V00B0000 V02N0001\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E1_H02W0601\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A7 H00R0000\narc: B2 V02S0101\narc: B5 V00B0100\narc: B6 V02S0701\narc: B7 V02N0701\narc: C0 N1_V02S0401\narc: C2 H00L0100\narc: C4 V00B0100\narc: C5 V01N0101\narc: C6 N1_V02S0001\narc: C7 V02N0201\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D2 S1_V02N0201\narc: D4 V02S0401\narc: D5 V02N0401\narc: D6 S1_V02N0601\narc: D7 V00B0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0000 F6\narc: LSR1 E1_H02W0501\narc: M0 H02W0601\narc: M1 H00R0100\narc: M2 H02W0601\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V02N0101 F1\narc: S1_V02S0601 F4\narc: S3_V06S0303 Q5\narc: V00B0100 Q5\narc: V01S0000 F1\narc: V01S0100 Q5\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1100111111001100\nword: SLICED.K0.INIT 0000000000110000\nword: SLICED.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0000000000001111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0011001100110000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R11C28:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 W1_H02E0301\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H06E0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02E0501\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E1_H01W0100\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A7 S1_V02N0301\narc: B7 V00B0000\narc: C1 V02S0601\narc: C3 V02N0401\narc: C7 E1_H02W0401\narc: D1 V00B0100\narc: D3 V02S0001\narc: D7 V02S0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 F3\narc: E1_H02E0101 F1\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: M6 H02W0401\narc: S1_V02S0101 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111111111110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R11C29:PLC2\narc: E1_H02E0401 S3_V06N0203\narc: H00L0000 V02N0001\narc: H00R0100 H02E0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0201 H01E0001\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 E3_H06W0003\narc: V00B0100 V02N0301\narc: V00T0000 V02S0401\narc: W1_H02W0001 V06S0003\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 H01E0101\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0103 E3_H06W0103\narc: CE0 H00R0100\narc: CE1 H02E0101\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q0\narc: H01W0000 Q2\narc: H01W0100 Q6\narc: M0 V00B0100\narc: M2 H02W0601\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: N3_V06N0003 Q0\narc: W1_H02W0601 Q6\narc: W3_H06W0003 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R11C2:PLC2\narc: E1_H02E0601 V02N0601\narc: H00R0000 H02W0601\narc: H00R0100 V02S0701\narc: N1_V02N0501 E1_H02W0501\narc: S3_V06S0103 E3_H06W0103\narc: V00B0100 H02E0501\narc: A1 E1_H01E0001\narc: B1 V00B0000\narc: C1 V02S0601\narc: CE1 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: E1_H01E0001 Q2\narc: E1_H02E0301 F1\narc: F1 F1_SLICE\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: M2 H02E0601\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: S1_V02S0201 Q2\narc: V00B0000 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R11C30:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 S3_V06N0203\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 N1_V01S0100\narc: S3_V06S0103 E3_H06W0103\narc: V00B0100 V02S0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 H01E0001\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: CE1 H02W0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: M2 V00B0100\narc: MUXCLK1 CLK0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R11C31:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 E1_H01W0000\narc: H00L0000 H02E0201\narc: H00R0000 V02S0401\narc: H00R0100 H02E0701\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0701 H02W0701\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 H06W0003\narc: S3_V06S0303 H06W0303\narc: V00B0100 V02N0301\narc: W1_H02W0101 H01E0101\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A2 H01E0001\narc: B0 V02S0301\narc: B2 V02N0301\narc: B3 V02N0101\narc: C0 N1_V01N0001\narc: C1 H02E0401\narc: C2 H00L0000\narc: C3 V02N0601\narc: CE2 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 H02E0201\narc: D2 H02W0201\narc: D3 V02N0201\narc: E1_H01E0001 F2\narc: E1_H02E0201 F0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0000 F3\narc: H01W0100 F3\narc: M0 V00B0100\narc: M4 H02W0401\narc: M6 H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111110100000000\nword: SLICEB.K1.INIT 0000000000110000\nword: SLICEA.K0.INIT 0011001100001111\nword: SLICEA.K1.INIT 1111111111110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R11C32:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0501 V02S0501\narc: H00L0000 H02W0201\narc: H00R0000 V02S0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0501 S3_V06N0303\narc: S1_V02S0101 E1_H02W0101\narc: V00B0100 E1_H02W0701\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0701 V06S0203\narc: W3_H06W0103 E1_H02W0101\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A0 E1_H01E0001\narc: A4 W1_H02E0501\narc: A6 H02W0701\narc: A7 H02E0501\narc: B0 V00T0000\narc: B2 H00R0100\narc: B4 S1_V02N0501\narc: B6 H02W0301\narc: B7 V01S0000\narc: C0 V02N0601\narc: C2 H00L0000\narc: C3 H02W0401\narc: C4 H01E0001\narc: C6 H02E0401\narc: C7 N1_V02S0001\narc: CE1 H00R0000\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D2 H02E0001\narc: D3 V02S0001\narc: D4 N1_V02S0601\narc: D6 H02W0201\narc: D7 H02E0201\narc: E1_H01E0001 Q7\narc: E1_H01E0101 F0\narc: E1_H02E0001 F0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 H02E0601\narc: M4 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: V00T0000 Q2\narc: V00T0100 F3\narc: V01S0000 F6\nword: SLICED.K0.INIT 1110101000000000\nword: SLICED.K1.INIT 1100111011111111\nword: SLICEB.K0.INIT 1100000011111111\nword: SLICEB.K1.INIT 0000111100000000\nword: SLICEC.K0.INIT 1100101011111111\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1000110010101010\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R11C33:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 V06N0303\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0103 V01N0101\narc: E3_H06E0203 S3_V06N0203\narc: H00L0100 V02S0301\narc: H00R0100 V02S0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 H01E0101\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 H02E0501\narc: V00T0000 V02S0401\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A7 E1_H02W0701\narc: B7 H02E0101\narc: C3 H00L0100\narc: C7 H02W0601\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 V02S0201\narc: D7 H00R0100\narc: E1_H01E0101 Q4\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 F6\narc: LSR0 V00T0100\narc: M4 V00B0100\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: V00T0100 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000010000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R11C34:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 H01E0101\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0303 H01E0101\narc: H00L0000 V02S0001\narc: H00R0100 H02W0501\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 E3_H06W0203\narc: V00T0000 W1_H02E0001\narc: V00T0100 H02E0301\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V01N0101\narc: W3_H06W0303 E1_H02W0601\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A0 E1_H02W0701\narc: A3 V02S0501\narc: A4 V02S0101\narc: B0 V00B0000\narc: B1 V00T0000\narc: B3 V01N0001\narc: B4 H02W0101\narc: B5 H00R0000\narc: B7 H01E0101\narc: C0 H00L0000\narc: C1 V02N0401\narc: C2 V02N0401\narc: C3 H02E0401\narc: C4 V02N0001\narc: C5 E1_H02W0601\narc: C7 V00T0100\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 V02S0001\narc: D2 S1_V02N0201\narc: D3 F2\narc: D4 H02W0001\narc: D5 F0\narc: D7 H00R0100\narc: E1_H02E0201 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H01W0000 F7\narc: H01W0100 Q4\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F2\narc: N1_V02N0001 F0\narc: S3_V06S0003 F3\narc: S3_V06S0103 F1\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V00B0000 F4\narc: W1_H02W0401 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011001111\nword: SLICEB.K0.INIT 0000111100000000\nword: SLICEB.K1.INIT 1111010000000000\nword: SLICEA.K0.INIT 0000000011010000\nword: SLICEA.K1.INIT 1111110000000000\nword: SLICEC.K0.INIT 0000000011100100\nword: SLICEC.K1.INIT 0000001100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R11C35:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 V01N0001\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0103 N1_V01S0100\narc: H00L0100 H02W0101\narc: H00R0000 V02S0401\narc: H00R0100 V02N0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H06W0203\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 N1_V02S0001\narc: V00T0000 W1_H02E0201\narc: V00T0100 H02W0101\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0701 V01N0101\narc: W3_H06W0103 E1_H02W0101\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: A0 H00L0100\narc: A4 V02N0301\narc: A6 V02N0301\narc: A7 V00T0100\narc: B0 H02E0101\narc: B1 H02E0101\narc: B4 W1_H02E0101\narc: B5 H02E0301\narc: B6 H02W0301\narc: B7 N1_V01S0000\narc: C0 H02E0401\narc: C1 V02S0401\narc: C4 E1_H01E0101\narc: C5 V02N0201\narc: C6 V00T0000\narc: C7 F6\narc: CE1 N1_V02S0201\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 S1_V02N0201\narc: D4 V02N0601\narc: D5 H02E0201\narc: D6 V02N0601\narc: D7 H00R0100\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F4\narc: LSR0 V00B0000\narc: M2 W1_H02E0601\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F5\narc: S1_V02S0701 F5\narc: S3_V06S0103 F1\narc: S3_V06S0303 F5\narc: W1_H02W0501 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0100000001010000\nword: SLICEA.K1.INIT 0000000011001111\nword: SLICEC.K0.INIT 1010000000100000\nword: SLICEC.K1.INIT 0000001100001111\nword: SLICED.K0.INIT 1000101000001010\nword: SLICED.K1.INIT 1101110110001101\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R11C36:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 H02E0201\narc: H00R0000 H02W0401\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0401 H01E0001\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0601\narc: V00T0000 E1_H02W0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 N1_V01S0100\narc: E1_H02E0101 W3_H06E0103\narc: N1_V02N0001 W3_H06E0003\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0203 V06S0203\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0003\narc: A0 H00L0100\narc: A1 V02S0701\narc: A3 V00B0000\narc: A4 H02E0701\narc: A5 V00T0100\narc: A6 V00T0100\narc: B0 V00T0000\narc: B1 H02W0301\narc: B3 H00L0000\narc: B4 E1_H02W0101\narc: B5 H00R0000\narc: B6 H02E0301\narc: C0 V02S0601\narc: C1 S1_V02N0401\narc: C3 H02E0401\narc: C4 V00B0100\narc: C5 V02N0201\narc: C6 V02S0001\narc: C7 H02E0601\narc: CE0 V02S0201\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H02W0001\narc: D3 E1_H02W0201\narc: D4 V02N0401\narc: D5 H00R0100\narc: D6 H00R0100\narc: D7 H02E0201\narc: E1_H01E0001 F6\narc: E1_H01E0101 F7\narc: E1_H02E0001 F0\narc: E3_H06E0003 F3\narc: E3_H06E0103 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: H00R0100 F7\narc: H01W0000 Q1\narc: H01W0100 Q6\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F7\narc: N1_V02N0101 Q1\narc: S3_V06S0103 Q1\narc: S3_V06S0203 F7\narc: V00B0100 F5\narc: V00T0100 Q1\narc: V01S0000 F4\narc: V01S0100 F3\narc: W1_H02W0101 Q1\narc: W1_H02W0401 F6\narc: W1_H02W0501 Q5\narc: W1_H02W0601 F6\narc: W1_H02W0701 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000111\nword: SLICED.K0.INIT 0000000011100100\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0110011111101111\nword: SLICEC.K1.INIT 0000000011100100\nword: SLICEA.K0.INIT 1110010000000000\nword: SLICEA.K1.INIT 1010100000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R11C37:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0103 H01E0101\narc: E3_H06E0303 H01E0101\narc: H00L0100 W1_H02E0101\narc: H00R0100 W1_H02E0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02E0601\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0501 V01N0101\narc: V00B0100 V02S0101\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 H01E0101\narc: E1_H02E0101 W3_H06E0103\narc: W3_H06W0203 E1_H02W0701\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: A6 V00T0100\narc: A7 V00T0100\narc: B0 H02W0301\narc: B1 V02N0101\narc: B3 N1_V02S0101\narc: B6 S1_V02N0501\narc: B7 S1_V02N0501\narc: C0 H00L0100\narc: C1 V02S0401\narc: C3 E1_H02W0401\narc: C6 V02N0201\narc: C7 V02N0201\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 V02S0001\narc: D3 V02S0001\narc: D6 H02E0201\narc: D7 H02E0201\narc: E1_H01E0001 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q1\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F1\narc: N1_V02N0001 F0\narc: N1_V02N0301 F1\narc: S3_V06S0003 Q3\narc: S3_V06S0103 Q1\narc: V01S0000 F0\narc: V01S0100 Q6\narc: W1_H02W0601 Q6\narc: W3_H06W0003 Q3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111111001100\nword: SLICEA.K0.INIT 0000111111001100\nword: SLICEA.K1.INIT 0000111111001100\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0111111111111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R11C38:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0203 W1_H02E0401\narc: H00L0000 N1_V02S0001\narc: H00R0000 V02S0601\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 H02W0701\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0203 H06W0203\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 H01E0001\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0201 W3_H06E0103\narc: W3_H06W0303 E1_H02W0501\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A1 S1_V02N0701\narc: A7 V00T0100\narc: B1 H02E0301\narc: B7 H02E0301\narc: C1 N1_V01S0100\narc: C7 V00B0100\narc: D1 V02S0001\narc: D7 V00B0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 E1_H02W0601\narc: M1 H00L0000\narc: M2 E1_H02W0601\narc: M3 H00R0000\narc: M4 E1_H02W0401\narc: M5 H00L0000\narc: M6 E1_H02W0401\narc: N1_V01N0001 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010111100100011\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010111100100011\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R11C39:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 S1_V02N0001\narc: H00R0000 S1_V02N0401\narc: H00R0100 H02E0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 E3_H06W0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0301 S3_V06N0003\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V06N0003\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0701 E3_H06W0203\narc: W3_H06W0303 E1_H02W0501\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: C0 H02E0601\narc: C1 E1_H01W0000\narc: C2 H02E0601\narc: C3 E1_H01W0000\narc: C4 H02E0601\narc: C5 E1_H02W0601\narc: C6 H02E0601\narc: C7 E1_H02W0401\narc: D0 H00R0000\narc: D1 V02S0201\narc: D2 H00R0000\narc: D3 V02S0201\narc: D4 S1_V02N0401\narc: D5 V00B0000\narc: D6 S1_V02N0401\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00L0000\narc: M2 V00B0100\narc: M3 H00R0100\narc: M4 V00B0100\narc: M5 W1_H02E0001\narc: M6 V00B0100\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000000000001111\nword: SLICEB.K0.INIT 0000111100000000\nword: SLICEB.K1.INIT 0000111100000000\nword: SLICEC.K0.INIT 0000000011110000\nword: SLICEC.K1.INIT 0000000011110000\nword: SLICED.K0.INIT 0000000000001111\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R11C3:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 S3_V06N0003\narc: H00L0100 V02S0101\narc: H00R0000 H02E0601\narc: H00R0100 V02S0701\narc: N1_V02N0401 E1_H02W0401\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0401 H06W0203\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 H06W0203\narc: V00B0100 E1_H02W0701\narc: W1_H02W0201 V02S0201\narc: W1_H02W0601 V02S0601\narc: A5 V00T0000\narc: B5 N1_V01S0000\narc: C5 V02S0201\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D5 V02S0401\narc: E1_H01E0001 Q6\narc: E3_H06E0103 Q2\narc: F5 F5_SLICE\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 V00B0100\narc: M2 V00T0000\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F5\narc: V00T0000 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R11C40:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 V01N0001\narc: H00R0000 W1_H02E0401\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 H06W0103\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 V02S0101\narc: V00T0000 H02E0201\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 E1_H02W0601\narc: E1_H02E0501 W3_H06E0303\narc: W3_H06W0003 E1_H02W0301\narc: W3_H06W0203 E1_H02W0701\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A5 H02E0701\narc: B5 H02W0301\narc: C5 H02E0401\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 V02N0001\narc: D2 H02W0201\narc: D3 E1_H02W0201\narc: D5 V02N0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 F5\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F1\narc: H01W0100 Q6\narc: M0 V00B0100\narc: M1 H02W0001\narc: M2 V00B0100\narc: M6 V00T0000\narc: MUXCLK3 CLK0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000010101010\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R11C41:PLC2\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0303 H01E0101\narc: H00R0000 H02E0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 W1_H02E0601\narc: V00B0100 S1_V02N0101\narc: V00T0000 S1_V02N0601\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 H01E0001\narc: N1_V02N0401 W3_H06E0203\narc: S1_V02S0101 W3_H06E0103\narc: S1_V02S0301 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q6\narc: E3_H06E0003 Q0\narc: E3_H06E0203 Q4\narc: H01W0000 Q4\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0000 Q2\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R11C42:PLC2\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V06N0203\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 H02E0201\narc: H00R0000 W1_H02E0601\narc: H00R0100 W1_H02E0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0401 E1_H02W0401\narc: V00B0000 H02W0601\narc: V00B0100 H02W0701\narc: V00T0000 H02W0201\narc: V00T0100 E1_H02W0101\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 E1_H02W0601\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0401 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0101 W3_H06E0103\narc: N3_V06N0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\narc: A1 H00L0000\narc: B1 E1_H02W0101\narc: B2 H01W0100\narc: B3 W1_H02E0101\narc: B5 E1_H02W0101\narc: B6 S1_V02N0701\narc: C1 H02E0601\narc: C2 N1_V01N0001\narc: C3 H02E0401\narc: C4 V00T0100\narc: C5 E1_H02W0601\narc: C6 V02S0201\narc: CLK0 G_HPBX0000\narc: D1 H02W0001\narc: D2 H00R0000\narc: D3 E1_H02W0201\narc: D4 V02N0401\narc: D5 W1_H02E0001\narc: D6 H01W0000\narc: D7 H00R0100\narc: E1_H01E0101 Q3\narc: E3_H06E0003 Q3\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q3\narc: LSR1 H02E0501\narc: M0 V00B0100\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0101 F3\narc: N1_V02N0301 Q3\narc: S1_V02S0201 F0\narc: S3_V06S0003 Q3\narc: S3_V06S0103 F2\narc: S3_V06S0203 F4\narc: V01S0000 F6\narc: W1_H02W0101 Q3\narc: W1_H02W0601 F6\nword: SLICEB.K0.INIT 0000000000111111\nword: SLICEB.K1.INIT 1100000000000000\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 1111111111110000\nword: SLICEC.K1.INIT 0000001111001111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010101111101111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R11C43:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 S3_V06N0003\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 V01N0101\narc: H00L0000 H02E0201\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02W0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 H01E0001\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 V01N0001\narc: N3_V06N0203 E1_H01W0000\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 H02E0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 H06W0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: V00T0000 S1_V02N0401\narc: V00T0100 H02W0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 E1_H02W0301\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: E1_H02E0601 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: S1_V02S0601 W3_H06E0303\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0103\narc: A0 H02E0701\narc: A1 V01N0101\narc: A2 H02E0701\narc: A3 V02S0501\narc: A5 V00T0100\narc: B0 F1\narc: B1 V02S0301\narc: B2 F3\narc: B3 W1_H02E0301\narc: B5 E1_H02W0301\narc: C0 H00L0100\narc: C1 H00L0000\narc: C2 H00L0100\narc: C3 H00L0000\narc: C5 S1_V02N0001\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 V02S0201\narc: D2 V02N0201\narc: D3 V02S0201\narc: D5 E1_H02W0201\narc: E1_H01E0001 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F1\narc: H01W0100 Q6\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q3\narc: N1_V02N0101 F1\narc: N3_V06N0103 Q1\narc: S1_V02S0001 F0\narc: V01S0000 F2\narc: W1_H02W0701 F5\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011011110111111\nword: SLICEA.K0.INIT 0111011100000111\nword: SLICEA.K1.INIT 0000000011001010\nword: SLICEB.K0.INIT 0111011100000111\nword: SLICEB.K1.INIT 0000000011001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R11C44:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 W1_H02E0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 W1_H02E0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 H02E0601\narc: V00T0000 W1_H02E0201\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0601 H01E0001\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E1_H02W0101\narc: E3_H06E0003 W3_H06E0303\narc: A0 H00L0100\narc: A1 W1_H02E0501\narc: A4 W1_H02E0701\narc: A5 S1_V02N0301\narc: A6 E1_H02W0701\narc: A7 N1_V01N0101\narc: B0 E1_H02W0301\narc: B1 V02N0101\narc: B4 E1_H02W0301\narc: B5 W1_H02E0301\narc: B6 V01S0000\narc: B7 W1_H02E0101\narc: C0 N1_V01N0001\narc: C1 H00L0000\narc: C4 V00B0100\narc: C5 V00T0000\narc: C6 V02N0001\narc: C7 H02E0601\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 H02E0201\narc: D4 V02N0601\narc: D5 V00B0000\narc: D6 H02W0201\narc: D7 S1_V02N0401\narc: E1_H02E0701 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q1\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q2\narc: S1_V02S0201 F0\narc: S1_V02S0301 F1\narc: S3_V06S0103 Q2\narc: S3_V06S0203 F4\narc: S3_V06S0303 F6\narc: V00B0100 F5\narc: V01S0000 F7\narc: V01S0100 Q2\narc: W1_H02W0301 F1\narc: W1_H02W0501 F5\narc: W1_H02W0701 Q7\narc: W3_H06W0203 F7\narc: W3_H06W0303 Q5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000111000000100\nword: SLICED.K1.INIT 0000111000000010\nword: SLICEC.K0.INIT 0101111100010011\nword: SLICEC.K1.INIT 0000000011001010\nword: SLICEA.K0.INIT 0101111100010011\nword: SLICEA.K1.INIT 0000000011001010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R11C45:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 H01E0101\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0103 W1_H02E0101\narc: H00L0000 H02W0001\narc: H00R0000 H02E0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H06E0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 E1_H01W0000\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0103 E1_H01W0100\narc: V00B0000 W1_H02E0601\narc: V00B0100 H02E0701\narc: V00T0100 W1_H02E0301\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0701 E3_H06W0203\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0501 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A1 E1_H01E0001\narc: A3 E1_H02W0501\narc: A4 S1_V02N0101\narc: A5 V02S0301\narc: A6 H00L0000\narc: A7 V02S0101\narc: B0 V01N0001\narc: B1 S1_V02N0301\narc: B3 H02W0101\narc: B4 H02W0301\narc: B5 V02N0501\narc: B6 H02E0101\narc: B7 E1_H02W0101\narc: C0 E1_H02W0601\narc: C1 V02S0601\narc: C3 N1_V01N0001\narc: C4 E1_H01E0101\narc: C5 H02E0401\narc: C6 V00T0100\narc: C7 V02S0001\narc: CE0 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 E1_H02W0001\narc: D3 V00B0100\narc: D4 H02E0201\narc: D5 V00B0000\narc: D6 H00R0100\narc: D7 V00B0000\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F5\narc: E3_H06E0003 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: H01W0100 F7\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 F5\narc: N1_V02N0701 Q7\narc: S3_V06S0203 F4\narc: S3_V06S0303 F6\narc: V01S0000 F3\narc: W3_H06W0103 F1\narc: W3_H06W0203 F7\narc: W3_H06W0303 Q5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0011011110111111\nword: SLICED.K0.INIT 0000111000000100\nword: SLICED.K1.INIT 0000000011011000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICEC.K0.INIT 0101111100010011\nword: SLICEC.K1.INIT 0000000010101100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R11C46:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0601 H01E0001\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 V02N0001\narc: H00R0000 E1_H02W0401\narc: H00R0100 W1_H02E0501\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 V01N0001\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 V01N0101\narc: V00B0000 E1_H02W0601\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02N0501\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0701 V01N0101\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0701 W3_H06E0203\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 S1_V02N0501\narc: A1 V02S0701\narc: A2 S1_V02N0501\narc: A3 V02S0501\narc: A6 H00L0000\narc: A7 V02N0301\narc: B0 E1_H02W0301\narc: B1 V00T0000\narc: B2 E1_H02W0301\narc: B3 H00R0000\narc: B6 V01S0000\narc: B7 V00B0000\narc: C0 N1_V01N0001\narc: C1 W1_H02E0401\narc: C2 H02W0401\narc: C3 W1_H02E0401\narc: C6 S1_V02N0201\narc: C7 W1_H02E0401\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H02E0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 H02E0001\narc: D2 V00T0100\narc: D3 H02E0001\narc: D6 V01N0001\narc: D7 H02E0001\narc: E1_H01E0001 F3\narc: E3_H06E0203 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q1\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 F7\narc: N1_V02N0301 F3\narc: N3_V06N0003 F3\narc: S1_V02S0101 F1\narc: S3_V06S0003 F0\narc: S3_V06S0103 F2\narc: S3_V06S0303 F6\narc: V01S0000 F7\narc: V01S0100 Q4\narc: W1_H02W0501 Q7\narc: W3_H06W0003 Q3\narc: W3_H06W0103 F1\narc: W3_H06W0203 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0101111100010011\nword: SLICEB.K1.INIT 0000000010101100\nword: SLICEA.K0.INIT 0101111100010011\nword: SLICEA.K1.INIT 0000000010101100\nword: SLICED.K0.INIT 0000111000000100\nword: SLICED.K1.INIT 0000000011001010\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R11C47:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0003 N3_V06S0003\narc: H00R0000 V02S0401\narc: H00R0100 V02N0701\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 H06W0303\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S3_V06S0203 H06W0203\narc: V00B0000 V02N0001\narc: V00B0100 V02N0101\narc: V00T0000 N1_V02S0401\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 V02S0501\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0601 W3_H06E0303\narc: W3_H06W0003 E1_H02W0301\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0103\narc: A6 H00R0000\narc: B6 S1_V02N0501\narc: C6 S1_V02N0001\narc: C7 S1_V02N0201\narc: CE0 E1_H02W0101\narc: CE1 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D6 N1_V02S0601\narc: D7 H00R0100\narc: E1_H01E0101 Q2\narc: F6 F5D_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q0\narc: M0 V00B0100\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q2\narc: S1_V02S0601 F6\narc: S3_V06S0003 Q0\narc: V01S0000 Q4\narc: V01S0100 Q2\narc: W1_H02W0201 Q2\narc: W1_H02W0601 Q4\narc: W3_H06W0103 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000011101110111\nword: SLICED.K1.INIT 0000000000001111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R11C48:PLC2\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0003 W1_H02E0301\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0201 V01N0001\narc: S1_V02S0501 H06W0303\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 S1_V02N0101\narc: V00T0000 S1_V02N0601\narc: V00T0100 H02E0301\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 H01E0101\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0001 W3_H06E0003\narc: N1_V02N0701 W3_H06E0203\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A7 H02E0501\narc: B7 H02E0101\narc: C7 V00T0100\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D7 W1_H02E0001\narc: E1_H02E0201 Q2\narc: E3_H06E0203 Q4\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M0 V00B0100\narc: M2 H02W0601\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q0\narc: W1_H02W0001 Q2\narc: W1_H02W0401 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000010101010\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R11C49:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V06N0203\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 H01E0001\narc: H00L0000 H02E0001\narc: H00L0100 V02N0301\narc: H00R0000 W1_H02E0601\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0101\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0701 E1_H02W0701\narc: V00B0000 E1_H02W0401\narc: V00T0000 H02E0001\narc: V00T0100 V02S0701\narc: W1_H02W0101 H01E0101\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 S3_V06N0303\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A1 H01E0001\narc: A3 W1_H02E0501\narc: A5 V00T0000\narc: A7 H00L0000\narc: B0 V02N0101\narc: B1 S1_V02N0301\narc: B2 H01W0100\narc: B3 H02W0101\narc: B4 V00B0100\narc: B5 S1_V02N0501\narc: B6 V01S0000\narc: B7 V00B0000\narc: C0 V02N0601\narc: C1 N1_V02S0601\narc: C2 E1_H02W0601\narc: C3 N1_V01S0100\narc: C4 V02N0001\narc: C5 H02E0601\narc: C6 H02W0601\narc: C7 V02S0001\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 H00R0000\narc: D2 V02N0001\narc: D3 V02S0201\narc: D4 H00L0100\narc: D5 W1_H02E0001\narc: D6 V02N0601\narc: D7 S1_V02N0601\narc: E1_H01E0001 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q5\narc: H01W0100 Q3\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: S3_V06S0303 F6\narc: V00B0100 Q5\narc: V01S0000 Q7\narc: V01S0100 Q1\narc: W1_H02W0301 Q3\narc: W3_H06W0003 F0\narc: W3_H06W0103 F2\narc: W3_H06W0203 F4\narc: W3_H06W0303 Q5\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0010101011111111\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111111111111000\nword: SLICEC.K0.INIT 1100111111000000\nword: SLICEC.K1.INIT 1111111111111000\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111111111111000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R11C4:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 V02N0701\narc: H00R0000 V02N0601\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 W1_H02E0301\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 H02W0401\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0601\narc: V00B0100 H02E0501\narc: V00T0000 H02W0001\narc: V00T0100 H02E0101\narc: W1_H02W0501 V02N0501\narc: A1 H02E0701\narc: A3 H01E0001\narc: A5 E1_H01W0000\narc: A6 N1_V01N0101\narc: A7 V02N0101\narc: B1 V00B0000\narc: B3 H02W0301\narc: B5 H00R0000\narc: B6 F1\narc: B7 V01S0000\narc: C1 V02S0601\narc: C3 V02S0401\narc: C5 V00T0100\narc: C6 V02N0001\narc: C7 H02W0601\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D3 N1_V02S0201\narc: D5 N1_V02S0601\narc: D6 H00R0100\narc: D7 H02E0001\narc: E3_H06E0303 Q6\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: LSR0 V00T0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 F3\narc: V01S0000 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0111111111111111\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R11C50:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0103 W1_H02E0201\narc: H00R0100 V02N0501\narc: H01W0000 E3_H06W0103\narc: H01W0100 E3_H06W0303\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 H06W0103\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 N1_V02S0101\narc: V00T0100 H02W0101\narc: W1_H02W0101 V06N0103\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 V01N0001\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0303 V01N0101\narc: E3_H06E0003 W3_H06E0303\narc: A1 N1_V02S0501\narc: A4 V02S0301\narc: A5 W1_H02E0501\narc: A6 W1_H02E0701\narc: A7 S1_V02N0301\narc: B1 V00B0000\narc: B4 V02N0501\narc: B5 V02N0501\narc: B6 V02N0501\narc: B7 V02N0501\narc: C1 N1_V02S0401\narc: C4 V00B0100\narc: C5 V00B0100\narc: C6 V00B0100\narc: C7 V00B0100\narc: D1 V02N0001\narc: D4 H00L0100\narc: D5 H00L0100\narc: D6 H00L0100\narc: D7 H00L0100\narc: E3_H06E0203 F4\narc: E3_H06E0303 F5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: M0 V00T0100\narc: M1 H00R0100\narc: M2 V00T0100\narc: S3_V06S0303 F6\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 1111101111110000\nword: SLICED.K1.INIT 1111101111110000\nword: SLICEC.K0.INIT 1111101111110000\nword: SLICEC.K1.INIT 1111101111110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0100000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R11C51:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V02N0201\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0303 W1_H02E0501\narc: H00L0100 H02W0301\narc: H00R0100 H02W0501\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N1_V01S0000\narc: V00B0000 V02S0201\narc: V00T0100 H02E0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 V02S0701\narc: E1_H02E0501 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0301 W3_H06E0003\narc: N3_V06N0003 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0303 E3_H06W0303\narc: B0 V02S0301\narc: B1 V00T0000\narc: B3 W1_H02E0101\narc: B4 V00B0100\narc: B5 V01S0000\narc: B7 N1_V02S0501\narc: C0 N1_V01N0001\narc: C1 N1_V02S0601\narc: C3 V02N0601\narc: C4 E1_H01E0101\narc: C5 N1_V02S0201\narc: C7 H02W0601\narc: CE0 H00R0100\narc: CE1 H00L0100\narc: CE2 H00R0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 V00T0100\narc: D3 W1_H02E0201\narc: D4 H02W0201\narc: D5 V00B0000\narc: D7 W1_H02E0201\narc: E1_H01E0101 F7\narc: E3_H06E0103 F1\narc: E3_H06E0203 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 F7\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F3\narc: N1_V01N0101 Q3\narc: S3_V06S0303 F5\narc: V00B0100 Q7\narc: V00T0000 Q0\narc: V01S0000 Q4\narc: W3_H06W0003 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111000011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R11C52:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0201 V06N0103\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 W1_H02E0001\narc: H00L0000 H02W0201\narc: H00R0000 H02E0601\narc: H00R0100 H02E0701\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0501 E1_H01W0100\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 H06W0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 V02S0001\narc: V00B0100 N1_V02S0101\narc: V00T0100 V02N0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 E3_H06W0303\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0001 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A1 H02E0501\narc: A2 H02W0501\narc: A5 E1_H02W0701\narc: A7 E1_H02W0501\narc: B1 E1_H02W0101\narc: B2 V02S0301\narc: B3 H00R0000\narc: B4 V02N0501\narc: B5 V01S0000\narc: B6 H02E0101\narc: B7 S1_V02N0501\narc: C1 S1_V02N0401\narc: C2 N1_V01N0001\narc: C3 H00L0000\narc: C4 H02W0601\narc: C5 N1_V02S0201\narc: C6 V01N0101\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: D2 S1_V02N0201\narc: D3 V00T0100\narc: D4 V00B0000\narc: D5 H00L0100\narc: D6 H02W0001\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0000 F4\narc: H01W0100 Q7\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F3\narc: N1_V01N0101 F2\narc: S3_V06S0003 F3\narc: S3_V06S0303 Q5\narc: V01S0100 Q5\narc: W3_H06W0203 Q7\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000010101010\nword: SLICEB.K0.INIT 1110011011100000\nword: SLICEB.K1.INIT 0011000000000000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111111111111000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1111111111111000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R11C53:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 V02N0401\narc: E1_H02E0701 H01E0101\narc: E3_H06E0203 H01E0001\narc: H00R0100 H02E0701\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0401 H02W0401\narc: S1_V02S0701 V01N0101\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 H06E0303\narc: V00B0000 H02E0401\narc: V00B0100 V02N0101\narc: V00T0000 N1_V02S0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 V02N0701\narc: H01W0000 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: A4 N1_V01S0100\narc: A5 V00B0000\narc: B4 V00B0100\narc: B5 H02E0301\narc: C2 S1_V02N0401\narc: C3 S1_V02N0401\narc: C4 H02W0601\narc: C5 V00T0000\narc: C6 V00T0100\narc: C7 E1_H02W0401\narc: CLK0 G_HPBX0000\narc: D2 H02E0001\narc: D3 V02S0001\narc: D4 V02S0601\narc: D5 S1_V02N0601\narc: D6 H00R0100\narc: D7 V02S0401\narc: E1_H01E0001 F3\narc: E1_H01E0101 F6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F5\narc: S1_V02S0501 F7\narc: V01S0000 F2\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 1111111111010101\nword: SLICEC.K1.INIT 0000110000001010\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000111111110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R11C54:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 V02N0701\narc: H00L0000 V02S0201\narc: H00L0100 V02S0101\narc: H00R0000 H02W0401\narc: H00R0100 V02N0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 H01E0101\narc: V00B0100 V02N0301\narc: V00T0000 H02W0201\narc: V00T0100 S1_V02N0701\narc: W1_H02W0301 V06N0003\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V06N0303\narc: W1_H02W0701 E1_H02W0701\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 N1_V01S0000\narc: A1 H00L0000\narc: A5 H02W0701\narc: A6 H02W0701\narc: B1 H00R0100\narc: B4 V02S0701\narc: B5 H02W0301\narc: B6 H02W0101\narc: C1 W1_H02E0601\narc: C2 H02W0401\narc: C3 H00L0100\narc: C4 H02E0401\narc: C5 N1_V02S0201\narc: C6 V00T0100\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: D2 W1_H02E0201\narc: D3 H00R0000\narc: D4 H02E0001\narc: D5 H02E0201\narc: D6 V02N0401\narc: E1_H02E0201 F0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q6\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00B0100\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q5\narc: S1_V02S0301 F3\narc: V01S0100 F2\narc: W3_H06W0203 F4\narc: W3_H06W0303 Q5\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1111111111111000\nword: SLICED.K0.INIT 1010000011101100\nword: SLICED.K1.INIT 1111111111111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0010101111010111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R11C55:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 V06N0303\narc: E3_H06E0103 H01E0101\narc: H00L0100 V02S0101\narc: H00R0000 H02E0601\narc: H00R0100 V02N0701\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0701 S3_V06N0203\narc: V00B0000 E1_H02W0401\narc: V00B0100 V02N0301\narc: V00T0000 H02E0201\narc: V00T0100 E1_H02W0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: E1_H01E0101 W3_H06E0203\narc: W1_H02W0501 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: A3 H00L0100\narc: A4 V00T0000\narc: A5 H02E0701\narc: A6 H00L0000\narc: A7 V00T0100\narc: B3 E1_H02W0101\narc: B4 H02W0101\narc: B5 H02W0301\narc: B6 V00B0000\narc: B7 H02E0301\narc: C0 S1_V02N0401\narc: C1 S1_V02N0401\narc: C3 H00R0100\narc: C4 S1_V02N0001\narc: C5 V00B0100\narc: C6 V02N0001\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V02S0001\narc: D3 H02E0001\narc: D4 H01W0000\narc: D5 S1_V02N0601\narc: D6 H02W0201\narc: D7 S1_V02N0601\narc: E1_H01E0001 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F2\narc: H01W0000 F5\narc: M2 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0001 F0\narc: V01S0100 F1\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 1111111111010101\nword: SLICED.K1.INIT 0000110000001010\nword: SLICEC.K0.INIT 1111111111010101\nword: SLICEC.K1.INIT 0000110000001010\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 0010110110110111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R11C56:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0701 V06N0203\narc: H00L0000 S1_V02N0201\narc: H00L0100 E1_H02W0101\narc: H00R0000 H02W0401\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 V01N0001\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02N0101\narc: V00T0000 H02W0201\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 V06N0303\narc: W1_H02W0701 H01E0101\narc: E1_H02E0101 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: A1 V02S0701\narc: A2 E1_H01E0001\narc: A3 V02S0701\narc: A6 H00R0000\narc: A7 N1_V02S0301\narc: B1 V00T0000\narc: B2 H00R0000\narc: B3 H00L0000\narc: B6 N1_V01S0000\narc: B7 V02N0501\narc: C1 V02N0401\narc: C2 S1_V02N0401\narc: C3 H00L0100\narc: C4 H02E0401\narc: C5 H02E0401\narc: C6 H02E0601\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D2 V01S0100\narc: D3 S1_V02N0001\narc: D4 H02E0201\narc: D5 H02E0001\narc: D6 H01W0000\narc: D7 V00B0000\narc: E1_H01E0001 F0\narc: E1_H01E0101 F4\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M0 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0501 F5\narc: V01S0100 F3\narc: W3_H06W0103 Q2\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1111111110110011\nword: SLICED.K1.INIT 0000110000001010\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 1111111111010101\nword: SLICEB.K1.INIT 0000110000001010\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0100101111010111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R11C57:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 V02S0201\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02N0701\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 E1_H02W0401\narc: S3_V06S0303 H01E0101\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0601\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 V02S0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 S3_V06N0303\narc: N1_V02N0401 W3_H06E0203\narc: S3_V06S0203 W3_H06E0203\narc: W1_H02W0001 W3_H06E0003\narc: W3_H06W0203 S3_V06N0203\narc: A1 S1_V02N0501\narc: A3 V00T0000\narc: A5 V00T0100\narc: A6 V00T0100\narc: A7 H00R0000\narc: B1 V02N0301\narc: B3 H00R0100\narc: B5 H02E0301\narc: B6 H02E0301\narc: B7 F1\narc: C1 E1_H02W0401\narc: C3 H00L0000\narc: C5 V00B0100\narc: C6 V01N0101\narc: C7 V02N0001\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D3 W1_H02E0001\narc: D5 N1_V02S0401\narc: D6 V02S0401\narc: D7 H01W0000\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: H01W0100 F2\narc: M2 V00B0100\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F7\narc: W3_H06W0303 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1110011011100000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000110000001010\nword: SLICED.K0.INIT 1000000011111111\nword: SLICED.K1.INIT 0000000000010011\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 0110001111010111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R11C58:PLC2\narc: H00L0000 V02S0001\narc: H00L0100 V02S0301\narc: H00R0000 H02E0401\narc: H00R0100 H02W0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0401 S3_V06N0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0101 H02W0101\narc: S1_V02S0401 H02W0401\narc: V00T0000 V02S0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 S3_V06N0003\narc: E1_H02E0101 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0103 W3_H06E0003\narc: A1 V02N0501\narc: A3 H00L0100\narc: A4 V02S0301\narc: A6 H00R0000\narc: B1 V02S0101\narc: B3 W1_H02E0101\narc: B4 W1_H02E0101\narc: B5 H00L0000\narc: B6 F3\narc: C1 H00R0100\narc: C3 H00R0100\narc: C4 V00T0000\narc: C5 V00T0100\narc: C6 V02N0001\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D3 S1_V02N0201\narc: D4 N1_V02S0401\narc: D5 V02N0601\narc: D6 V00B0000\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M6 V00B0100\narc: MUXCLK3 CLK0\narc: N1_V02N0301 F1\narc: V00B0000 F4\narc: V00B0100 F5\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1110011011100000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1110011011100000\nword: SLICEC.K0.INIT 0000110000001010\nword: SLICEC.K1.INIT 1100000000000000\nword: SLICED.K0.INIT 1111111111101100\nword: SLICED.K1.INIT 1111111111111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R11C59:PLC2\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0601\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S3_V06N0103\narc: H01W0000 W3_H06E0103\narc: W1_H02W0401 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0303 E3_H06W0203\n\n.tile R11C5:PLC2\narc: E1_H02E0401 E3_H06W0203\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 H02W0401\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0201 H02W0201\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0201\narc: V00B0100 E1_H02W0701\narc: V00T0000 V02S0601\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 E3_H06W0203\narc: CE0 E1_H02W0101\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: E3_H06E0103 Q2\narc: H01W0000 Q6\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00B0100\narc: M2 H02E0601\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q0\narc: S3_V06S0203 Q4\narc: V01S0000 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R11C60:PLC2\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0601 S3_V06N0303\narc: W1_H02W0001 S1_V02N0001\narc: W3_H06W0003 E1_H01W0000\n\n.tile R11C61:PLC2\narc: N1_V02N0401 S3_V06N0203\narc: H01W0000 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\n\n.tile R11C62:PLC2\narc: N1_V01N0101 S3_V06N0203\narc: S3_V06S0203 W3_H06E0203\n\n.tile R11C63:PLC2\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0401 W3_H06E0203\n\n.tile R11C64:PLC2\narc: N1_V02N0701 S3_V06N0203\narc: E3_H06E0103 W3_H06E0103\n\n.tile R11C65:PLC2\narc: N1_V02N0401 S3_V06N0203\narc: W3_H06W0203 E3_H06W0203\n\n.tile R11C67:PLC2\narc: E1_H02E0301 W3_H06E0003\n\n.tile R11C69:PLC2\narc: E1_H02E0601 W1_H02E0301\narc: S3_V06S0103 N3_V06S0003\n\n.tile R11C6:PLC2\narc: E3_H06E0103 S3_V06N0103\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 H06W0303\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 W1_H02E0701\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 E3_H06W0203\narc: W3_H06W0203 E3_H06W0203\narc: A3 V00B0000\narc: B3 E1_H01W0100\narc: C3 V02N0601\narc: CE0 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D3 E1_H02W0001\narc: F3 F3_SLICE\narc: H01W0000 F3\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00B0000\narc: M4 V00B0100\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: S1_V02S0201 Q0\narc: S3_V06S0003 Q0\narc: V00B0000 Q6\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R11C70:PLC2\narc: S3_V06S0103 W3_H06E0103\n\n.tile R11C7:PLC2\narc: E1_H02E0701 E1_H01W0100\narc: N1_V02N0101 H02W0101\narc: N1_V02N0701 H02W0701\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 H06W0103\narc: V00B0000 H02W0401\narc: V00B0100 H02W0501\narc: V00T0000 V02N0401\narc: V00T0100 V02S0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 S1_V02N0701\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: H01W0100 Q2\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00T0000\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q4\narc: W1_H02W0201 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R11C8:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 V06S0203\narc: E1_H02E0701 V01N0101\narc: E3_H06E0103 V01N0101\narc: H00R0000 V02N0601\narc: H00R0100 H02W0501\narc: N1_V02N0301 V01N0101\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 H02W0401\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 H01E0101\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0401\narc: V00T0100 V02N0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V01N0101\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 V06N0303\narc: W1_H02W0701 V06S0203\narc: W3_H06W0103 E3_H06W0103\narc: A1 E1_H01E0001\narc: B1 V00B0000\narc: C1 H00R0100\narc: CE1 S1_V02N0201\narc: CE2 S1_V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: E1_H01E0001 Q4\narc: F1 F1_SLICE\narc: H01W0100 Q2\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M2 V00B0100\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F1\narc: V00B0000 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R11C9:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0601 V06S0303\narc: H00L0100 V02N0301\narc: H00R0000 V02N0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S3_V06N0003\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 E3_H06W0003\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 E1_H02W0701\narc: V00T0000 H02W0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V06S0303\narc: S3_V06S0103 W3_H06E0103\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: A1 W1_H02E0701\narc: A3 V00B0000\narc: B1 H02E0301\narc: B3 H01W0100\narc: C1 H00R0100\narc: C2 H00L0100\narc: C3 H00L0000\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0001\narc: D2 V00B0100\narc: D3 H00R0000\narc: E1_H01E0001 F0\narc: E1_H02E0001 F2\narc: E3_H06E0103 F2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H00L0000 F2\narc: H01W0000 F2\narc: H01W0100 Q4\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00T0100\narc: M4 E1_H02W0401\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: V00B0000 Q6\narc: V00T0100 F3\narc: V01S0100 F2\narc: W3_H06W0103 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000111100000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R12C10:PLC2\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 S3_V06N0203\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S3_V06N0303\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 H06W0303\narc: V00B0000 S1_V02N0201\narc: V00B0100 S1_V02N0301\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02N0501\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0203 E1_H02W0701\narc: W3_H06W0103 E3_H06W0103\narc: A1 H00L0000\narc: A6 H02E0701\narc: A7 N1_V02S0301\narc: B1 H01W0100\narc: B6 V01S0000\narc: B7 V00T0000\narc: C1 H02E0601\narc: C6 E1_H01E0101\narc: C7 H02E0401\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D6 E1_H01W0100\narc: D7 H00R0100\narc: E1_H01E0101 F1\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0100 Q4\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M2 V00B0100\narc: M4 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: V01S0000 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R12C11:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0601 V02S0601\narc: H00R0100 H02E0701\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 H02E0701\narc: S1_V02S0301 H02E0301\narc: S3_V06S0103 H06W0103\narc: V00B0000 H02E0601\narc: V00B0100 V02N0101\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02S0701\narc: W3_H06W0303 E1_H01W0100\narc: A5 N1_V01N0101\narc: B5 V01S0000\narc: C5 V02S0201\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: F5 F5_SLICE\narc: H01W0100 F5\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00T0100\narc: M2 V00B0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q6\narc: S3_V06S0003 Q0\narc: V01S0000 Q2\narc: W3_H06W0003 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R12C12:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0701 V02S0701\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0601 W1_H02E0601\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 E1_H02W0601\narc: V00T0000 E1_H02W0001\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 S1_V02N0701\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: H01W0100 Q2\narc: LSR0 W1_H02E0301\narc: LSR1 W1_H02E0301\narc: M0 V00T0000\narc: M2 H02E0601\narc: M4 H02W0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q6\narc: S3_V06S0203 Q4\narc: V01S0100 Q2\narc: W1_H02W0201 Q0\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R12C13:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0101 H02W0101\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0301 S3_V06N0003\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 V02S0201\narc: V00B0100 H02E0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0401 V02S0401\narc: W3_H06W0003 E1_H02W0001\narc: W3_H06W0303 E3_H06W0303\narc: A4 H02W0701\narc: B4 S1_V02N0501\narc: C4 E1_H01E0101\narc: C5 V00B0100\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 S1_V02N0601\narc: E1_H01E0101 F5\narc: E1_H02E0601 F4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: LSR1 E1_H02W0501\narc: M6 H02W0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000011100000000\nword: SLICEC.K1.INIT 1111000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R12C14:PLC2\narc: H00L0000 V02S0001\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 E1_H01W0000\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 H02E0601\narc: V00B0100 H02W0701\narc: V00T0100 H02E0101\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 N1_V01S0100\narc: H01W0100 W3_H06E0303\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E3_H06W0003\narc: A0 H00L0100\narc: A1 H02E0701\narc: A2 E1_H01E0001\narc: A3 V02N0501\narc: A4 N1_V01N0101\narc: A5 H02E0501\narc: B0 V02S0101\narc: B1 H00R0100\narc: B2 V02S0301\narc: B3 S1_V02N0101\narc: B4 W1_H02E0101\narc: B5 H00R0000\narc: C0 V02N0401\narc: C1 S1_V02N0401\narc: C2 H00L0000\narc: C3 W1_H02E0401\narc: C4 H02E0401\narc: C5 V02N0001\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 V00T0100\narc: D2 V00B0100\narc: D3 E1_H02W0201\narc: D4 H02W0201\narc: D5 V00B0000\narc: E1_H01E0001 Q3\narc: E3_H06E0003 F0\narc: E3_H06E0103 F2\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0100 Q1\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q5\nword: SLICEA.K0.INIT 0000000000000001\nword: SLICEA.K1.INIT 0111111111111111\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 0111111111111111\nword: SLICEB.K0.INIT 0000000000000001\nword: SLICEB.K1.INIT 0111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R12C15:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E3_H06E0303 V06N0303\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0201 E3_H06W0103\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02S0101\narc: V00T0000 V02S0601\narc: V00T0100 S1_V02N0501\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0701 E1_H02W0701\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A7 V02N0301\narc: B7 V00T0000\narc: C6 V02N0001\narc: C7 V00B0100\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D6 H00R0100\narc: D7 V00B0000\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q6\narc: H00R0100 F7\narc: H01W0000 F6\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M2 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V02N0001 Q2\narc: N1_V02N0201 Q2\narc: N1_V02N0501 F7\narc: S3_V06S0303 F6\narc: W1_H02W0001 Q2\narc: W1_H02W0501 F7\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 1011111111111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R12C16:PLC2\narc: E1_H02E0501 S3_V06N0303\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 S3_V06N0003\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0501 S3_V06N0303\narc: E1_H02E0301 W3_H06E0003\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0003\n\n.tile R12C17:PLC2\narc: E1_H02E0401 V02N0401\narc: H00L0000 H02W0201\narc: H00R0100 V02S0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0301 N1_V01S0100\narc: S1_V02S0501 H02E0501\narc: S3_V06S0003 H06W0003\narc: V00B0000 H02W0601\narc: V00B0100 H02W0501\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 V06S0103\narc: W1_H02W0701 E3_H06W0203\narc: A1 E1_H02W0701\narc: B1 V00T0000\narc: C0 E1_H01W0000\narc: C1 H00R0100\narc: C4 V02S0201\narc: C5 V00T0100\narc: CE0 V02N0201\narc: CE1 H00L0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 V02N0001\narc: D4 V02N0601\narc: D5 V02S0401\narc: E1_H01E0101 F4\narc: E1_H02E0001 Q2\narc: E3_H06E0003 F0\narc: E3_H06E0103 Q1\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0000 F4\narc: H01W0000 F5\narc: H01W0100 F4\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M2 E1_H02W0601\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: N1_V02N0101 Q1\narc: N1_V02N0601 F4\narc: N3_V06N0003 F0\narc: S1_V02S0601 Q6\narc: S3_V06S0303 F5\narc: V00T0000 F0\narc: V00T0100 Q1\narc: V01S0000 Q1\narc: W3_H06W0003 F0\narc: W3_H06W0103 Q1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000000011110000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000100000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\n\n.tile R12C18:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 V06S0303\narc: E3_H06E0203 S3_V06N0203\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0501 H01E0101\narc: S3_V06S0003 H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 V02N0101\narc: V00T0100 V02N0501\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 S1_V02N0601\narc: A3 V00B0000\narc: B3 H00R0100\narc: C3 S1_V02N0401\narc: CE0 N1_V02S0201\narc: CE2 N1_V02S0601\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: E1_H01E0001 Q0\narc: F3 F3_SLICE\narc: LSR0 W1_H02E0301\narc: LSR1 W1_H02E0301\narc: M0 E1_H02W0601\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F3\narc: N1_V01N0101 Q6\narc: V00B0000 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R12C19:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 E1_H01W0100\narc: E3_H06E0103 V06S0103\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 V02S0001\narc: H00L0100 H02W0301\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H06E0203\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0601 H02E0601\narc: V00B0000 E1_H02W0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02S0501\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 V02N0701\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0303 E3_H06W0303\narc: A1 H01E0001\narc: A5 V00T0000\narc: A6 V02S0301\narc: A7 H00L0000\narc: B0 F1\narc: B1 V02S0101\narc: B5 V02N0501\narc: B6 N1_V01S0000\narc: B7 V00B0000\narc: C0 H00R0100\narc: C1 N1_V02S0601\narc: C5 S1_V02N0001\narc: C6 V02S0001\narc: C7 H02E0601\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 H02E0001\narc: D5 V02S0601\narc: D6 N1_V02S0401\narc: D7 V02S0401\narc: E1_H02E0601 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: M2 V00T0100\narc: MUXCLK1 CLK0\narc: S1_V02S0201 F0\narc: S1_V02S0501 F5\narc: S3_V06S0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 1100000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R12C20:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02S0001\narc: H00L0100 W1_H02E0301\narc: H00R0000 V02S0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 H06E0203\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 H02E0601\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0601 S1_V02N0601\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: A0 H02E0501\narc: A1 V02N0701\narc: A3 V02S0701\narc: A4 V02S0301\narc: A5 N1_V01S0100\narc: A7 V02S0101\narc: B0 F1\narc: B1 E1_H01W0100\narc: B3 E1_H02W0101\narc: B4 H02W0101\narc: B5 H00L0000\narc: B7 H02W0301\narc: C0 N1_V02S0601\narc: C1 N1_V02S0401\narc: C3 H00L0100\narc: C4 V02S0201\narc: C5 V00B0100\narc: C7 V00T0000\narc: D0 S1_V02N0201\narc: D1 E1_H02W0001\narc: D3 H00R0000\narc: D4 H02E0201\narc: D5 H00R0100\narc: D7 V00B0000\narc: E1_H01E0001 F0\narc: E1_H02E0201 F0\narc: E1_H02E0701 F5\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: H01W0100 F6\narc: M6 V00T0100\narc: N1_V02N0201 F0\narc: V01S0000 F0\narc: V01S0100 F4\narc: W1_H02W0201 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0111111100000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R12C21:PLC2\narc: E1_H02E0001 V02N0001\narc: H00L0000 H02E0001\narc: H00L0100 N1_V02S0301\narc: H00R0100 V02S0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 H01E0001\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H01E0001\narc: V00B0000 E1_H02W0601\narc: V00B0100 H02E0501\narc: V00T0000 S1_V02N0401\narc: V00T0100 H02E0101\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 H01E0001\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A0 N1_V02S0701\narc: A1 N1_V02S0701\narc: B0 H00R0100\narc: B1 V00T0000\narc: C0 V02S0601\narc: C1 H00L0100\narc: C3 H02E0401\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 V00B0100\narc: D3 V00T0100\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: H01W0000 F1\narc: H01W0100 F0\narc: M4 V00B0000\narc: M6 W1_H02E0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0003 F3\narc: S3_V06S0303 Q6\narc: W3_H06W0003 Q3\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011110000\nword: SLICEA.K0.INIT 1000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R12C22:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: H00L0000 H02W0201\narc: H00R0000 V02S0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 W1_H02E0201\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 W1_H02E0701\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0101 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: A0 V02S0701\narc: A1 H00L0000\narc: A4 V02S0301\narc: A5 V00B0000\narc: B0 H00R0100\narc: B1 V00T0000\narc: B4 V01S0000\narc: B5 H02W0101\narc: C0 V02S0401\narc: C1 V02N0401\narc: C4 V00B0100\narc: C5 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 H00R0000\narc: D4 N1_V02S0601\narc: D5 V02S0601\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F1\narc: LSR0 H02W0501\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V02N0601 Q4\narc: V01S0000 F5\narc: W1_H02W0001 F0\nword: SLICEA.K0.INIT 1000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0111111111111111\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R12C23:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0401 E1_H01W0000\narc: E3_H06E0303 N3_V06S0303\narc: H00L0000 E1_H02W0201\narc: H00R0000 V02N0601\narc: H00R0100 H02W0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0601 N1_V01S0000\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0401 N1_V02S0101\narc: V00B0000 V02N0001\narc: V00B0100 V02S0301\narc: V00T0000 W1_H02E0001\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 E3_H06W0303\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: W3_H06W0203 V06S0203\narc: E3_H06E0103 W3_H06E0003\narc: A3 H02W0701\narc: A5 Q5\narc: A6 V02N0101\narc: A7 H02W0701\narc: B2 H02W0301\narc: B3 H01W0100\narc: B5 V02N0701\narc: B6 V00B0000\narc: B7 V01S0000\narc: C2 S1_V02N0601\narc: C3 S1_V02N0401\narc: C5 V00T0000\narc: C6 V00T0100\narc: C7 V02N0001\narc: CE0 H00R0000\narc: CE1 V02S0201\narc: CE2 H00L0000\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D2 V01S0100\narc: D3 V02S0001\narc: D5 V02S0601\narc: D6 E1_H01W0100\narc: D7 H00R0100\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q2\narc: E1_H02E0001 Q2\narc: E1_H02E0601 Q6\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q5\narc: H01W0100 F7\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00B0100\narc: M2 N1_V01N0001\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q6\narc: S3_V06S0103 Q2\narc: S3_V06S0303 Q6\narc: V01S0000 Q6\narc: V01S0100 F7\narc: W1_H02W0001 Q2\narc: W1_H02W0201 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1010100011111111\nword: SLICED.K1.INIT 1011111110001110\nword: SLICEB.K0.INIT 0011000011111111\nword: SLICEB.K1.INIT 0011001111110111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111100110011001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R12C24:PLC2\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 H02E0001\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0401 E1_H02W0401\narc: V00B0000 V02N0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 H01E0101\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 H01E0101\narc: E1_H02E0701 W3_H06E0203\narc: W3_H06W0203 V06S0203\narc: W3_H06W0303 V06S0303\narc: W3_H06W0103 E3_H06W0003\narc: A1 H00L0000\narc: B1 V00B0000\narc: B5 W1_H02E0101\narc: B6 V01S0000\narc: B7 V01S0000\narc: C0 H00L0000\narc: C1 V02N0601\narc: C3 H02W0401\narc: C5 H02W0601\narc: C6 H02W0601\narc: C7 H02E0401\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 V00B0100\narc: D3 V00T0100\narc: D4 H01W0000\narc: D5 V02S0601\narc: D6 V02S0601\narc: D7 W1_H02E0001\narc: E1_H01E0001 F6\narc: E1_H01E0101 F3\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 Q7\narc: H01W0000 Q4\narc: H01W0100 F0\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 H02E0601\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: S1_V02S0501 F5\narc: S3_V06S0203 Q7\narc: V01S0000 Q7\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 1111110011001100\nword: SLICED.K0.INIT 1111001100110011\nword: SLICED.K1.INIT 1100110011111100\nword: SLICEA.K0.INIT 1111111111110000\nword: SLICEA.K1.INIT 1011101110110001\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R12C25:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 W1_H02E0601\narc: H00L0100 H02E0301\narc: H00R0000 W1_H02E0601\narc: H00R0100 H02E0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 H06E0203\narc: N3_V06N0203 H06E0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 S1_V02N0001\narc: V00T0000 H02E0201\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E1_H02W0601\narc: W3_H06W0203 E1_H02W0401\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0303 E3_H06W0303\narc: A1 H00R0000\narc: B1 V00B0000\narc: B7 V01S0000\narc: C1 H00L0100\narc: C6 V00T0100\narc: C7 V00T0000\narc: CE2 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 E1_H02W0001\narc: D2 S1_V02N0001\narc: D3 S1_V02N0201\narc: D5 V02S0601\narc: D6 E1_H02W0201\narc: D7 N1_V02S0401\narc: E1_H01E0001 Q5\narc: E1_H01E0101 F6\narc: E1_H02E0401 F6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: H01W0100 F6\narc: LSR0 V00B0100\narc: M0 H02E0601\narc: M1 H00R0100\narc: M2 H02E0601\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q5\narc: N1_V02N0601 F6\narc: S1_V02S0401 F6\narc: V00B0100 F7\narc: V01S0000 F6\narc: V01S0100 F1\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 1111110011110000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0010001000100011\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R12C26:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 E1_H01W0000\narc: H00L0100 V02N0301\narc: H00R0000 W1_H02E0401\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 H01E0101\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H02E0701\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 H01E0101\narc: V00B0000 H02E0601\narc: V00B0100 S1_V02N0301\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0401 H01E0001\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A1 H02E0501\narc: A3 W1_H02E0501\narc: A5 W1_H02E0501\narc: B1 V02N0101\narc: B3 H00R0000\narc: B5 H00R0000\narc: C0 V02N0601\narc: C1 H00L0100\narc: C2 V02N0601\narc: C3 V02N0401\narc: C5 H02E0401\narc: C6 V02N0001\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 S1_V02N0201\narc: D2 H02E0001\narc: D3 V00B0100\narc: D5 H01W0000\narc: D6 V00B0000\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 F2\narc: E1_H02E0501 F7\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 F0\narc: LSR1 E1_H02W0301\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0001 F2\narc: N1_V01N0101 F4\narc: N1_V02N0301 F3\narc: N3_V06N0103 Q1\narc: N3_V06N0203 F4\narc: S1_V02S0201 F0\narc: S3_V06S0003 F3\narc: V01S0000 F3\narc: V01S0100 F6\nword: SLICEA.K0.INIT 0000111100000000\nword: SLICEA.K1.INIT 1000100011111000\nword: SLICED.K0.INIT 0000111100000000\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 1100010010000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0100000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R12C27:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 W1_H02E0101\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 W1_H02E0001\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02W0601\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 H01E0101\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0601 E1_H02W0601\narc: V00B0000 V02N0001\narc: V00B0100 H02E0501\narc: V00T0000 N1_V02S0601\narc: V00T0100 W1_H02E0301\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0601 S3_V06N0303\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0103\narc: A1 W1_H02E0501\narc: A3 W1_H02E0501\narc: A6 H00L0000\narc: B1 V02N0301\narc: B3 V02N0301\narc: B5 H02E0301\narc: B6 S1_V02N0701\narc: C1 N1_V01N0001\narc: C2 H00L0100\narc: C3 N1_V01N0001\narc: C4 Q4\narc: C5 H02E0401\narc: C6 V00T0100\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 S1_V02N0001\narc: D3 H00R0000\narc: D4 H02W0001\narc: D5 H02W0001\narc: D6 V00B0000\narc: E1_H01E0001 F0\narc: E1_H01E0101 Q6\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q5\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: M0 V00B0100\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F2\narc: N1_V01N0101 Q5\narc: N1_V02N0401 Q4\narc: V01S0000 F3\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1111111111000011\nword: SLICEB.K0.INIT 0000111100000000\nword: SLICEB.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICED.K0.INIT 0111011100000111\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R12C28:PLC2\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 V06S0303\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 H02E0001\narc: H00L0100 V02S0101\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 H01E0101\narc: N1_V02N0601 H01E0001\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0401 V01N0001\narc: V00B0000 H02W0401\narc: V00B0100 V02N0101\narc: V00T0000 V02N0401\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0601 S1_V02N0601\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0303 E3_H06W0203\narc: CE0 H00L0000\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N1_V02N0001 Q2\narc: S3_V06S0103 Q2\narc: S3_V06S0303 Q6\narc: V01S0000 Q4\narc: V01S0100 Q6\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R12C29:PLC2\narc: H00L0000 H02W0001\narc: H00R0100 V02N0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0701 H06E0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02E0501\narc: V00T0100 H02W0101\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 E3_H06W0303\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0303 E3_H06W0203\narc: A5 V00T0000\narc: A7 N1_V01N0101\narc: B4 V01S0000\narc: B5 E1_H02W0101\narc: B6 H02E0301\narc: B7 V00B0100\narc: C4 H02E0601\narc: C5 V02N0201\narc: C6 E1_H01E0101\narc: C7 V00T0100\narc: CE0 H00L0000\narc: CE1 V02S0201\narc: CLK0 G_HPBX0000\narc: D4 H00R0100\narc: D5 V02N0601\narc: D6 N1_V02S0601\narc: D7 V02S0601\narc: E1_H01E0101 Q0\narc: E3_H06E0203 F4\narc: E3_H06E0303 F6\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M0 V00B0000\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q0\narc: V00T0000 Q2\narc: V01S0000 Q2\narc: V01S0100 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1111110000001100\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R12C2:PLC2\narc: H00R0000 H02E0401\narc: H01W0000 E3_H06W0103\narc: H01W0100 E3_H06W0303\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 N1_V02S0001\narc: V00T0000 V02N0601\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: M0 E1_H02W0601\narc: M2 V00B0000\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: S3_V06S0103 Q2\narc: S3_V06S0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R12C30:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 S1_V02N0401\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0401 H06E0203\narc: N1_V02N0701 S3_V06N0203\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V06S0103\narc: E1_H02E0501 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0203 W3_H06E0203\narc: A7 H02W0501\narc: B7 E1_H02W0301\narc: C7 V02N0201\narc: D7 S1_V02N0601\narc: F7 F7_SLICE\narc: N1_V02N0501 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000010101010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R12C31:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 S1_V02N0401\narc: H00L0000 H02W0001\narc: H00R0000 H02W0601\narc: H00R0100 H02E0701\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 E1_H02W0701\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0501 V02N0501\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0303 E3_H06W0303\narc: B7 V00B0100\narc: C3 H00L0000\narc: C7 H02E0401\narc: CE1 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: D7 V02S0601\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: M4 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0003 Q3\narc: S3_V06S0203 Q7\narc: W3_H06W0003 F3\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100111111000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R12C32:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0103 W1_H02E0101\narc: H00R0000 H02W0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 S1_V02N0701\narc: V00B0000 H02E0401\narc: V00B0100 V02N0301\narc: V00T0000 V02N0601\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 E1_H02W0301\narc: N1_V02N0401 W3_H06E0203\narc: W3_H06W0003 E1_H02W0301\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: A7 W1_H02E0501\narc: B7 W1_H02E0101\narc: C7 V02N0201\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D7 W1_H02E0201\narc: E1_H01E0101 F6\narc: E1_H02E0401 Q4\narc: E3_H06E0303 F6\narc: F6 F5D_SLICE\narc: H01W0100 F6\narc: M0 V00B0000\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: S3_V06S0003 Q0\narc: S3_V06S0103 Q2\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0011001100110001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R12C33:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0301 E1_H01W0100\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 V02N0301\narc: H00R0000 E1_H02W0601\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0101\narc: V00T0100 H02E0101\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0601 E1_H02W0601\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A1 H00L0000\narc: B1 V00B0000\narc: B5 V02S0701\narc: C1 H02E0601\narc: C5 H02W0601\narc: CE1 H00R0000\narc: CE2 W1_H02E0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D5 S1_V02N0401\narc: E1_H01E0001 Q6\narc: E1_H01E0101 F1\narc: E1_H02E0401 Q6\narc: E1_H02E0601 Q6\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: H00L0000 Q2\narc: H01W0000 Q6\narc: M2 V00T0100\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q6\narc: V01S0000 Q6\narc: W1_H02W0701 Q5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100110000001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000010000100001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R12C34:PLC2\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0103 S3_V06N0103\narc: H00L0100 V02S0101\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 E1_H01W0000\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 E1_H02W0601\narc: V00B0100 S1_V02N0101\narc: V00T0000 S1_V02N0401\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 V02S0601\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A0 H01E0001\narc: A1 E1_H01E0001\narc: A3 H01E0001\narc: A4 V02N0301\narc: A7 H00R0000\narc: B0 E1_H01W0100\narc: B1 V02S0101\narc: B2 V02N0101\narc: B3 E1_H01W0100\narc: B4 H01E0101\narc: B5 H02E0301\narc: B7 V00B0100\narc: C0 N1_V02S0401\narc: C1 H00L0000\narc: C2 N1_V01N0001\narc: C3 H00L0100\narc: C4 V00T0100\narc: C5 V02N0001\narc: C6 V00T0000\narc: C7 V02S0001\narc: CE1 H02E0101\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 V00B0100\narc: D2 V00B0100\narc: D3 H02W0201\narc: D4 H00R0100\narc: D5 V02S0401\narc: D6 H01W0000\narc: D7 V00B0000\narc: E1_H01E0001 Q6\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H00R0000 Q6\narc: H01W0000 F5\narc: H01W0100 F4\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F3\narc: N1_V01N0101 F5\narc: N1_V02N0101 F3\narc: S1_V02S0101 F1\narc: S3_V06S0103 F2\narc: S3_V06S0303 F5\narc: V01S0000 F7\narc: W1_H02W0301 F3\narc: W3_H06W0003 Q3\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0101010000000000\nword: SLICEB.K0.INIT 0011001100001111\nword: SLICEB.K1.INIT 0000000000001011\nword: SLICEA.K0.INIT 1011000000000000\nword: SLICEA.K1.INIT 0000000010111010\nword: SLICEC.K0.INIT 0001010101010101\nword: SLICEC.K1.INIT 1100111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R12C35:PLC2\narc: E1_H02E0201 V06N0103\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 V02S0701\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 W1_H02E0401\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 V02S0101\narc: H00R0100 V02N0501\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 V01N0001\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 W1_H02E0601\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0401\narc: V00T0100 S1_V02N0701\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 E1_H02W0601\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0101 W3_H06E0103\narc: S3_V06S0303 W3_H06E0303\narc: W3_H06W0203 E1_H02W0701\narc: W3_H06W0303 E1_H02W0501\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: A0 H02E0501\narc: A1 H00L0100\narc: A2 V02N0701\narc: B0 V02S0101\narc: B1 V00B0000\narc: B2 V02S0101\narc: B3 V02N0301\narc: C0 H00R0100\narc: C1 S1_V02N0601\narc: C2 H02E0401\narc: C3 V02S0601\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 F0\narc: D2 E1_H02W0201\narc: D3 N1_V02S0201\narc: E1_H01E0001 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q4\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q4\narc: N1_V02N0001 F2\narc: V01S0000 F1\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0101000111111011\nword: SLICEA.K1.INIT 1111101100000000\nword: SLICEB.K0.INIT 0000000011011111\nword: SLICEB.K1.INIT 1111001111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R12C36:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V02S0701\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 W1_H02E0701\narc: H00R0100 V02S0701\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02N0301\narc: V00T0100 V02N0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 H01E0001\narc: E3_H06E0303 W3_H06E0203\narc: A3 V00B0000\narc: B1 H02W0301\narc: B3 H00R0000\narc: C0 V02S0601\narc: C1 E1_H02W0601\narc: C3 V02S0401\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 F0\narc: D3 E1_H02W0001\narc: E1_H01E0001 F3\narc: E1_H01E0101 F0\narc: E1_H02E0001 F0\narc: E1_H02E0301 F1\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: H00R0000 Q6\narc: H01W0000 F0\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0003 F0\narc: S3_V06S0103 F1\narc: V00B0000 Q4\narc: V01S0100 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0110011000100000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 1100110011110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R12C37:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0501 H01E0101\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 S1_V02N0201\narc: H00L0100 S1_V02N0301\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0203 S3_V06N0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 S1_V02N0601\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0701 E1_H02W0601\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0401 W3_H06E0203\narc: N3_V06N0103 W3_H06E0103\narc: W3_H06W0003 V06S0003\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A0 V02S0501\narc: A1 H02W0701\narc: A7 N1_V01S0100\narc: B0 E1_H02W0101\narc: B1 V00B0000\narc: B7 V02N0701\narc: C0 H00L0100\narc: C1 H00L0000\narc: C7 V00B0100\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 H02W0201\narc: D7 H02E0201\narc: E1_H01E0101 Q2\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 F6\narc: H01W0100 F0\narc: M2 W1_H02E0601\narc: M4 W1_H02E0401\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: S1_V02S0601 F6\narc: S3_V06S0303 F6\narc: V00T0100 F1\narc: W1_H02W0601 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1001000000000000\nword: SLICEA.K1.INIT 1000101011001111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R12C38:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0203 V06N0203\narc: H00L0000 V02S0201\narc: H00R0100 H02E0501\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0301 H01E0101\narc: S3_V06S0003 E3_H06W0003\narc: V00B0100 H02W0701\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0701 H01E0101\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: A1 H00L0100\narc: A7 V00T0100\narc: B1 V00T0000\narc: B6 V00T0000\narc: B7 V00T0000\narc: C0 V02N0601\narc: C1 N1_V01N0001\narc: C6 Q6\narc: C7 E1_H01E0101\narc: CE1 V02S0201\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 W1_H02E0001\narc: D6 H00R0100\narc: D7 H00R0100\narc: E1_H01E0101 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: H01W0000 F7\narc: H01W0100 Q0\narc: LSR1 H02W0301\narc: M2 E1_H02W0601\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: S1_V02S0101 Q1\narc: V00T0000 Q0\narc: V00T0100 Q1\narc: V01S0000 Q0\narc: V01S0100 Q6\narc: W1_H02W0001 Q2\narc: W1_H02W0601 Q4\narc: W3_H06W0203 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 0110101010101010\nword: SLICED.K0.INIT 0011110011110000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R12C39:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 V06N0103\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 N1_V02S0501\narc: E3_H06E0103 W1_H02E0101\narc: H00L0000 S1_V02N0201\narc: H00R0000 S1_V02N0601\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0301 H06E0003\narc: S3_V06S0003 H06E0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 S1_V02N0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 V02S0301\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0001 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A0 H02W0701\narc: B2 H00L0000\narc: B3 H00R0000\narc: B4 S1_V02N0501\narc: B5 V02N0501\narc: B6 H02W0301\narc: B7 V00B0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 F6\narc: S1_V02S0201 F2\narc: S1_V02S0701 F5\narc: V01S0000 F7\narc: V01S0100 F4\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R12C3:PLC2\narc: H00R0000 V02S0401\narc: H00R0100 V02N0501\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 S1_V02N0601\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 E1_H02W0701\narc: A3 V00B0000\narc: B3 H00L0000\narc: C3 V02N0601\narc: CE0 H00R0100\narc: CE2 W1_H02E0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 V02N0001\narc: E1_H02E0301 F3\narc: E3_H06E0203 Q4\narc: F3 F3_SLICE\narc: H00L0000 Q0\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 V00B0100\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: S1_V02S0201 Q0\narc: S1_V02S0601 Q4\narc: V00B0000 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R12C40:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 W1_H02E0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0301 N3_V06S0003\narc: S3_V06S0103 H06W0103\narc: V00B0000 S1_V02N0001\narc: V00T0000 S1_V02N0401\narc: V00T0100 V02S0701\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 V02S0601\narc: N1_V02N0101 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0203 E3_H06W0103\narc: B0 V00B0000\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: LSR1 H02E0301\narc: M4 V00T0000\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: S1_V02S0001 F0\narc: S3_V06S0203 Q4\narc: S3_V06S0303 Q6\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R12C41:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 N1_V01S0000\narc: H00R0100 H02W0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H02W0501\narc: N3_V06N0103 H06W0103\narc: V00B0000 H02W0401\narc: V00B0100 V02N0301\narc: V00T0000 S1_V02N0401\narc: V00T0100 H02W0301\narc: W1_H02W0101 V02S0101\narc: W1_H02W0701 S1_V02N0701\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: A3 V02S0701\narc: A5 W1_H02E0501\narc: B3 V02S0301\narc: B4 V01S0000\narc: B5 V00B0100\narc: B6 V02N0701\narc: B7 H02E0101\narc: C3 H02W0601\narc: C4 V00T0100\narc: C5 W1_H02E0401\narc: C6 V00T0100\narc: C7 V02N0001\narc: CLK0 G_HPBX0000\narc: D3 S1_V02N0201\narc: D4 H00R0100\narc: D5 S1_V02N0601\narc: D6 E1_H01W0100\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: H01W0100 Q5\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: S3_V06S0303 F6\narc: V01S0000 Q5\narc: V01S0100 Q7\narc: W3_H06W0203 F4\narc: W3_H06W0303 Q5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000010101010\nword: SLICEC.K0.INIT 1100111111000000\nword: SLICEC.K1.INIT 0100110011111111\nword: SLICED.K0.INIT 1100111111000000\nword: SLICED.K1.INIT 1100000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R12C42:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0303 H01E0101\narc: H00L0100 E1_H02W0301\narc: H00R0000 V02S0401\narc: H00R0100 H02E0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 W1_H02E0501\narc: S3_V06S0003 N1_V02S0001\narc: V00B0100 V02N0301\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 E3_H06W0203\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0601 W3_H06E0303\narc: S1_V02S0001 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: A0 S1_V02N0501\narc: A3 S1_V02N0701\narc: B0 F3\narc: B3 H00R0100\narc: C0 H02E0601\narc: C3 W1_H02E0601\narc: CE0 H00R0000\narc: CE2 H00R0000\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D3 V02N0001\narc: E3_H06E0203 Q4\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: M0 E1_H02W0601\narc: M4 W1_H02E0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0303 Q6\narc: V01S0100 Q4\narc: W3_H06W0003 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000001001000001\nword: SLICEA.K0.INIT 0000000000001000\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R12C43:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 H01E0001\narc: H00L0100 V02S0101\narc: H00R0000 V02S0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0401 N1_V01S0000\narc: V00B0100 V02S0101\narc: V00T0100 V02S0501\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: E1_H02E0601 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E1_H02W0701\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A2 H02W0701\narc: A3 V02N0701\narc: A4 V02S0301\narc: A5 V00B0000\narc: B2 V02N0301\narc: B3 H02E0301\narc: B4 H02W0101\narc: B5 V00B0100\narc: C2 V02N0601\narc: C3 H00L0100\narc: C4 V02N0201\narc: C5 V00T0100\narc: CE0 H00R0100\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 H02W0201\narc: D3 H00R0000\narc: D4 V02S0401\narc: D5 V02S0601\narc: E1_H01E0001 F4\narc: E3_H06E0303 Q6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q3\narc: M0 H02E0601\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q0\narc: N1_V02N0301 F3\narc: N3_V06N0303 Q5\narc: S3_V06S0003 Q0\narc: S3_V06S0103 F2\narc: S3_V06S0303 F5\narc: V00B0000 Q6\narc: V01S0000 F3\narc: W1_H02W0301 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0101111100010011\nword: SLICEB.K1.INIT 0000000011001010\nword: SLICEC.K0.INIT 0111000011110000\nword: SLICEC.K1.INIT 0000000011100010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R12C44:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0103 N1_V01S0100\narc: H00L0000 H02W0001\narc: H00R0000 V02S0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 E1_H01W0000\narc: S1_V02S0401 H01E0001\narc: V00B0000 V02N0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02W0201\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 V02S0701\narc: E1_H02E0001 W3_H06E0003\narc: H01W0000 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: B0 V00B0000\narc: B1 V00T0000\narc: B6 V01S0000\narc: B7 V02S0501\narc: C0 N1_V01N0001\narc: C1 H02W0401\narc: C2 H00L0100\narc: C3 H00L0000\narc: C6 E1_H01E0101\narc: C7 V01N0101\narc: CE0 E1_H02W0101\narc: CE2 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 E1_H02W0001\narc: D2 H01E0101\narc: D3 H02E0001\narc: D6 H01W0000\narc: D7 W1_H02E0001\narc: E1_H01E0001 F3\narc: E1_H01E0101 F1\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H01W0100 F0\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q6\narc: N1_V02N0401 Q6\narc: S3_V06S0103 F2\narc: S3_V06S0203 F7\narc: S3_V06S0303 Q6\narc: V01S0000 Q1\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 0000000000001111\nword: SLICEB.K1.INIT 0000000000001111\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R12C45:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0003 H01E0001\narc: H00L0000 H02E0001\narc: H00L0100 H02E0301\narc: H00R0000 W1_H02E0601\narc: H00R0100 V02N0501\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0201 V01N0001\narc: S1_V02S0501 W1_H02E0501\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 H02W0701\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02S0501\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 E1_H01W0000\narc: E1_H02E0501 W3_H06E0303\narc: N3_V06N0103 W3_H06E0103\narc: W3_H06W0103 E1_H02W0201\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: A2 H00L0100\narc: A3 V02N0701\narc: A4 V02S0101\narc: A5 S1_V02N0301\narc: A6 E1_H02W0701\narc: A7 S1_V02N0101\narc: B2 H02W0301\narc: B3 V02S0301\narc: B4 E1_H02W0301\narc: B5 E1_H02W0101\narc: B6 H02E0101\narc: B7 W1_H02E0101\narc: C2 H02E0601\narc: C3 H00R0100\narc: C4 H02W0401\narc: C5 N1_V02S0201\narc: C6 E1_H01E0101\narc: C7 V02N0001\narc: CE0 H00L0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 V00T0100\narc: D4 E1_H01W0100\narc: D5 V02S0601\narc: D6 V02S0401\narc: D7 V02S0601\narc: E1_H01E0001 F5\narc: E1_H01E0101 F7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 Q7\narc: M0 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N1_V02N0101 Q3\narc: N3_V06N0303 Q5\narc: S1_V02S0601 F4\narc: S3_V06S0103 F2\narc: V01S0000 F6\narc: W1_H02W0701 F7\narc: W3_H06W0003 F3\narc: W3_H06W0303 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000010111111\nword: SLICED.K1.INIT 0000000011100010\nword: SLICEC.K0.INIT 0011011110111111\nword: SLICEC.K1.INIT 0000000010101100\nword: SLICEB.K0.INIT 0101111100010011\nword: SLICEB.K1.INIT 0000000011100010\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R12C46:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 S1_V02N0501\narc: H00L0000 V02N0201\narc: H00L0100 V02S0301\narc: H00R0000 V02N0401\narc: H00R0100 H02E0701\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H06E0203\narc: N3_V06N0003 S3_V06N0003\narc: V00B0000 V02N0001\narc: V00T0100 V02N0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 N1_V01S0100\narc: E1_H02E0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: A0 V02N0501\narc: A1 H00R0000\narc: A3 V00T0000\narc: A4 V00T0100\narc: A6 V00T0100\narc: A7 S1_V02N0301\narc: B0 E1_H02W0301\narc: B1 V00B0000\narc: B3 H00L0000\narc: B4 E1_H02W0301\narc: B5 V02S0701\narc: B6 E1_H02W0301\narc: B7 V02S0501\narc: C0 H02W0601\narc: C1 H00L0100\narc: C2 V02S0401\narc: C3 H02W0601\narc: C4 H01E0001\narc: C5 N1_V02S0001\narc: C6 E1_H01E0101\narc: C7 H02E0401\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 V02S0001\narc: D2 V02S0201\narc: D3 H01E0101\narc: D4 H01W0000\narc: D5 V02N0601\narc: D6 H01W0000\narc: D7 V02S0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: H01W0100 F1\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 F2\narc: N1_V02N0001 F2\narc: N1_V02N0501 F5\narc: N3_V06N0103 Q1\narc: S1_V02S0101 F3\narc: S1_V02S0501 F5\narc: S3_V06S0003 F0\narc: S3_V06S0203 F4\narc: S3_V06S0303 F6\narc: V00B0100 F5\narc: V00T0000 F2\narc: V01S0100 F2\narc: W1_H02W0701 F5\narc: W3_H06W0103 F1\nword: SLICEC.K0.INIT 0101111100010011\nword: SLICEC.K1.INIT 0000001111001111\nword: SLICEA.K0.INIT 0101111100010011\nword: SLICEA.K1.INIT 0000000011001010\nword: SLICEB.K0.INIT 0000111100000000\nword: SLICEB.K1.INIT 0011000100100000\nword: SLICED.K0.INIT 0101111100010011\nword: SLICED.K1.INIT 0000000011001010\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R12C47:PLC2\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0601 V02N0601\narc: H00L0000 H02E0001\narc: H00R0000 H02W0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 V01N0101\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02N0301\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 N1_V01S0100\narc: E1_H02E0501 W3_H06E0303\narc: S1_V02S0101 W3_H06E0103\narc: S1_V02S0601 W3_H06E0303\narc: W3_H06W0103 E1_H02W0201\narc: E3_H06E0303 W3_H06E0203\narc: A7 H02E0501\narc: B0 H01W0100\narc: B1 V00T0000\narc: B3 N1_V02S0301\narc: B6 S1_V02N0501\narc: B7 V00B0100\narc: C0 H00L0100\narc: C1 H02W0401\narc: C3 S1_V02N0601\narc: C6 W1_H02E0601\narc: C7 V00T0100\narc: CE0 H00L0000\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0201\narc: D1 N1_V02S0001\narc: D3 H00R0000\narc: D6 H00R0100\narc: D7 V02S0601\narc: E1_H01E0101 Q4\narc: E3_H06E0003 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H00R0100 F7\narc: H01W0100 Q3\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: S3_V06S0103 F1\narc: V00T0000 Q0\narc: V01S0100 F3\narc: W3_H06W0003 Q0\narc: W3_H06W0303 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1111001100000000\nword: SLICED.K1.INIT 0101011100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R12C48:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 E3_H06W0303\narc: E3_H06E0203 W1_H02E0401\narc: H00L0000 E1_H02W0001\narc: H00R0100 H02W0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H06E0203\narc: N3_V06N0103 H01E0101\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 H02W0601\narc: V00B0100 H02E0501\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 N1_V02S0401\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0501 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: S1_V02S0001 W3_H06E0003\narc: W1_H02W0501 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: B3 H02W0301\narc: B5 V02S0501\narc: B7 V00B0000\narc: C3 H00R0100\narc: C5 V02N0201\narc: C7 V02N0201\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: D5 S1_V02N0401\narc: D7 V02N0401\narc: E3_H06E0003 Q0\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: H01W0100 F7\narc: M0 H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q5\narc: S1_V02S0301 F3\narc: S1_V02S0501 F5\narc: V01S0000 Q3\narc: V01S0100 F3\narc: W3_H06W0203 F7\narc: W3_H06W0303 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100111111000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100111111000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R12C49:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 S3_V06N0203\narc: H00L0000 H02W0201\narc: H00L0100 E1_H02W0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0301 H02W0301\narc: S1_V02S0601 H06E0303\narc: S3_V06S0203 E1_H01W0000\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02E0201\narc: V00T0100 V02S0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 N1_V02S0601\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: N3_V06N0203 W3_H06E0203\narc: W3_H06W0303 N1_V01S0100\narc: E3_H06E0003 W3_H06E0303\narc: B0 V00T0000\narc: B1 N1_V02S0101\narc: B3 H02W0101\narc: B5 H00R0000\narc: B7 V02N0701\narc: C0 N1_V01N0001\narc: C1 H00L0100\narc: C3 H00L0000\narc: C5 H02E0601\narc: C7 V00T0100\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 V00B0100\narc: D3 V00B0100\narc: D5 H00R0100\narc: D7 H00R0100\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 Q3\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: S1_V02S0101 Q1\narc: S1_V02S0501 Q7\narc: S3_V06S0003 F3\narc: S3_V06S0103 F1\narc: S3_V06S0303 F5\narc: V01S0000 F7\narc: V01S0100 Q5\narc: W3_H06W0003 F0\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1100110011110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R12C4:PLC2\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0701 S3_V06N0203\narc: H00L0000 E1_H02W0001\narc: H00L0100 H02E0301\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02N0701\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0501 S3_V06N0303\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02N0101\narc: V00T0000 V02S0401\narc: V00T0100 S1_V02N0701\narc: V01S0100 S3_V06N0303\narc: W1_H02W0501 S3_V06N0303\narc: A0 H00R0000\narc: B0 F1\narc: C0 H00L0100\narc: C1 N1_V01N0001\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 V02N0001\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: LSR0 V00B0100\narc: M2 V00B0000\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N1_V02N0001 F0\narc: N1_V02N0201 Q2\narc: N1_V02N0601 Q4\narc: W1_H02W0601 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0001000000110000\nword: SLICEA.K1.INIT 1111000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R12C50:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0303 N3_V06S0303\narc: H00L0000 H02W0001\narc: H00R0000 H02W0601\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 E1_H01W0000\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02W0701\narc: V00T0000 N1_V02S0601\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 S3_V06N0203\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0201 W3_H06E0103\narc: N3_V06N0303 W3_H06E0303\narc: S1_V02S0001 W3_H06E0003\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: B0 V02S0101\narc: B1 V00B0000\narc: B3 H02E0101\narc: B5 H00L0000\narc: B7 V02N0501\narc: C0 H00L0100\narc: C1 V02N0401\narc: C3 H02E0401\narc: C5 V00B0100\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 H02E0001\narc: D3 H02E0001\narc: D5 H02E0001\narc: D7 H02E0001\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0000 Q3\narc: H01W0100 F7\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F3\narc: N1_V01N0101 F5\narc: S1_V02S0501 Q7\narc: S1_V02S0701 F5\narc: S3_V06S0103 Q1\narc: S3_V06S0203 F7\narc: S3_V06S0303 Q5\narc: V01S0100 F1\narc: W3_H06W0003 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1100110011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R12C51:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 H01E0001\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0303 V06S0303\narc: H00L0000 H02E0001\narc: H00L0100 E1_H02W0301\narc: H00R0000 N1_V02S0401\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 H06E0003\narc: S1_V02S0001 V01N0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 V01N0101\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 W1_H02E0601\narc: V00B0100 E1_H02W0701\narc: V00T0000 H02W0001\narc: V00T0100 V02S0701\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V06N0203\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 N1_V01S0100\narc: N1_V02N0501 W3_H06E0303\narc: B1 N1_V02S0101\narc: B3 V02S0301\narc: B4 V02N0701\narc: B5 H00R0000\narc: B6 V00T0000\narc: B7 V02S0501\narc: C1 V02N0601\narc: C3 H00L0100\narc: C4 V00T0100\narc: C5 V00B0100\narc: C6 E1_H01E0101\narc: C7 V02S0001\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0001\narc: D3 W1_H02E0001\narc: D4 V00B0000\narc: D5 W1_H02E0001\narc: D6 V02S0601\narc: D7 W1_H02E0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F3\narc: N1_V01N0101 F5\narc: S1_V02S0101 Q1\narc: S1_V02S0301 F1\narc: S1_V02S0701 Q7\narc: S3_V06S0003 Q3\narc: S3_V06S0303 F5\narc: V01S0000 Q5\narc: W3_H06W0203 F4\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R12C52:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0003 V06N0003\narc: H00L0000 W1_H02E0001\narc: H00L0100 S1_V02N0101\narc: H00R0100 H02E0501\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0303 H06W0303\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 H02E0401\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 H01E0101\narc: V00B0100 H02E0501\narc: V00T0000 V02N0601\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 V06N0103\narc: W1_H02W0601 V06N0303\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0201 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: B1 V00T0000\narc: B3 V02N0301\narc: B5 E1_H02W0101\narc: B7 V02S0501\narc: C1 S1_V02N0601\narc: C3 H00L0100\narc: C5 E1_H02W0601\narc: C7 V02S0001\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D3 V00B0100\narc: D5 H00R0100\narc: D7 H00R0100\narc: E1_H01E0001 F7\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q1\narc: H01W0100 Q3\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 F5\narc: S1_V02S0301 F1\narc: S1_V02S0501 Q7\narc: S3_V06S0203 F7\narc: S3_V06S0303 F5\narc: V01S0000 Q5\narc: W1_H02W0301 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R12C53:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0303 V01N0101\narc: H00L0100 H02E0301\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H01E0001\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0001 V01N0001\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 H01E0101\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 H01E0101\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02E0501\narc: V00T0000 H02W0201\narc: V00T0100 E1_H02W0101\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0701 N1_V01S0100\narc: H01W0100 W3_H06E0303\narc: W3_H06W0103 N3_V06S0103\narc: E3_H06E0003 W3_H06E0303\narc: A4 V00B0000\narc: A5 V00T0100\narc: B1 H02E0101\narc: B4 S1_V02N0501\narc: B5 S1_V02N0701\narc: B7 V00T0000\narc: C1 E1_H02W0401\narc: C2 V02N0401\narc: C3 V02N0401\narc: C4 W1_H02E0401\narc: C5 S1_V02N0001\narc: C7 V02N0001\narc: CE0 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D2 V00B0100\narc: D3 H02E0201\narc: D4 H00R0100\narc: D5 E1_H01W0100\narc: D7 H02E0001\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0000 Q7\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: S1_V02S0101 F3\narc: S3_V06S0103 Q1\narc: S3_V06S0203 F7\narc: V01S0100 F2\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1000000011111111\nword: SLICEC.K1.INIT 0000000000010011\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000111111110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R12C54:PLC2\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0601 V01N0001\narc: E1_H02E0701 V06N0203\narc: H00L0000 S1_V02N0001\narc: H00L0100 W1_H02E0301\narc: H00R0000 S1_V02N0601\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 V01N0101\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 H01E0101\narc: V00B0000 N1_V02S0201\narc: V00T0000 H02W0201\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 V06N0203\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: A2 E1_H01E0001\narc: A3 S1_V02N0701\narc: A5 S1_V02N0101\narc: A7 V02S0101\narc: B1 V02N0101\narc: B2 E1_H02W0101\narc: B3 H00R0000\narc: B5 S1_V02N0501\narc: B7 V00B0000\narc: C1 H00L0000\narc: C2 V02N0601\narc: C3 H02E0401\narc: C5 H02E0401\narc: C7 V00T0000\narc: CE0 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0001\narc: D2 V01S0100\narc: D3 V02N0001\narc: D5 V02S0601\narc: D7 S1_V02N0601\narc: E1_H01E0001 F6\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q1\narc: H01W0100 F5\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: V01S0100 F3\narc: W1_H02W0201 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000110000001010\nword: SLICEB.K0.INIT 1111111111010101\nword: SLICEB.K1.INIT 0000110000001010\nword: SLICED.K0.INIT 1111111111111111\nword: SLICED.K1.INIT 0100101111010111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R12C55:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02N0201\narc: H00L0100 N1_V02S0101\narc: H00R0000 W1_H02E0601\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 N1_V01S0100\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 H01E0101\narc: V00B0000 E1_H02W0601\narc: V00B0100 H02E0701\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 N1_V01S0000\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: W3_H06W0303 S3_V06N0303\narc: A1 H00L0100\narc: A4 V00T0000\narc: A5 S1_V02N0301\narc: B1 H02E0301\narc: B3 E1_H02W0101\narc: B4 H02W0101\narc: B5 H00L0000\narc: B7 V00B0000\narc: C1 E1_H02W0401\narc: C3 H02W0601\narc: C4 V00T0100\narc: C5 W1_H02E0401\narc: C7 N1_V02S0201\narc: CE1 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: D3 W1_H02E0201\narc: D4 H00R0100\narc: D5 V02N0601\narc: D7 W1_H02E0201\narc: E3_H06E0003 Q3\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0000 F7\narc: H01W0100 Q4\narc: M0 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0701 Q7\narc: S3_V06S0003 F3\narc: S3_V06S0203 F7\narc: V00T0000 F0\narc: W3_H06W0003 F3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1111111111010101\nword: SLICEC.K1.INIT 0000110000001010\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0010110110110111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R12C56:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 V02N0301\narc: H00R0000 H02E0601\narc: H00R0100 H02W0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 H02W0701\narc: N3_V06N0203 V01N0001\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 H06E0303\narc: V00B0100 H02W0701\narc: V00T0000 W1_H02E0201\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 E1_H02W0301\narc: H01W0000 W3_H06E0103\narc: S1_V02S0701 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A0 E1_H01E0001\narc: A1 H00L0100\narc: A5 V02N0301\narc: B0 H00R0100\narc: B1 H02E0301\narc: B5 V00B0100\narc: B7 H02W0301\narc: C0 S1_V02N0601\narc: C1 H02E0401\narc: C2 S1_V02N0401\narc: C3 S1_V02N0401\narc: C5 V00T0000\narc: C7 S1_V02N0201\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V02N0001\narc: D2 H02E0001\narc: D3 V02S0201\narc: D5 H02E0001\narc: D7 E1_H02W0001\narc: E1_H01E0001 F4\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0201 F2\narc: S1_V02S0301 F3\narc: S3_V06S0203 Q7\narc: V01S0100 F1\narc: W1_H02W0001 Q0\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1111111111010101\nword: SLICEA.K1.INIT 0000110000001010\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 0110001111010111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R12C57:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0501 S1_V02N0501\narc: H00L0000 H02W0201\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 H01E0101\narc: V00B0000 E1_H02W0401\narc: V00B0100 N1_V02S0101\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 S3_V06N0203\narc: H01W0000 W3_H06E0103\narc: W3_H06W0103 S3_V06N0103\narc: E3_H06E0303 W3_H06E0303\narc: A0 S1_V02N0501\narc: A1 H00L0100\narc: A2 S1_V02N0501\narc: A3 H02E0701\narc: A5 H02W0701\narc: A6 H02E0701\narc: B0 H02E0101\narc: B1 V02S0301\narc: B2 F3\narc: B3 V02N0301\narc: B5 S1_V02N0701\narc: B6 V02N0701\narc: B7 S1_V02N0701\narc: C0 S1_V02N0401\narc: C1 E1_H02W0401\narc: C2 H00R0100\narc: C3 H00L0000\narc: C5 V00B0100\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 V02N0001\narc: D2 S1_V02N0001\narc: D3 H00R0000\narc: D5 H02E0001\narc: D6 F2\narc: D7 V00B0000\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: E1_H02E0701 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F4\narc: M4 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F7\narc: S3_V06S0203 F7\narc: V00T0100 F1\narc: W1_H02W0601 Q6\narc: W3_H06W0003 Q0\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 1000000011111111\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEA.K0.INIT 1111111110110011\nword: SLICEA.K1.INIT 0000110000001010\nword: SLICEB.K0.INIT 0000000000010011\nword: SLICEB.K1.INIT 1110111001100000\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 0110001111010111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R12C58:PLC2\narc: H00L0100 V02S0101\narc: H00R0000 V02S0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 H01E0001\narc: S3_V06S0003 H06E0003\narc: V00T0000 S1_V02N0601\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 S1_V02N0701\narc: S1_V02S0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: A1 H00L0100\narc: A2 H02E0501\narc: A3 S1_V02N0701\narc: A4 V02S0101\narc: A6 H02E0501\narc: B1 H02W0101\narc: B2 W1_H02E0301\narc: B3 E1_H02W0301\narc: B4 H02W0101\narc: B5 H02E0101\narc: B6 F1\narc: C1 V02N0401\narc: C2 H02W0601\narc: C3 H02W0401\narc: C4 H02W0401\narc: C5 V00T0000\narc: C6 V02N0001\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 V00T0100\narc: D3 E1_H02W0001\narc: D4 E1_H02W0001\narc: D5 H00R0100\narc: D6 V00B0000\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q6\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: V00B0000 F4\narc: V00B0100 F5\narc: V00T0100 F3\narc: W3_H06W0103 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1110111001100000\nword: SLICEC.K0.INIT 0000110000001010\nword: SLICEC.K1.INIT 1100000000000000\nword: SLICEB.K0.INIT 1111111110110011\nword: SLICEB.K1.INIT 0000110000001010\nword: SLICED.K0.INIT 1111111111101100\nword: SLICED.K1.INIT 1111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R12C59:PLC2\narc: S3_V06S0103 N3_V06S0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V06N0103\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: H01W0000 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\n\n.tile R12C5:PLC2\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0401 E1_H01W0000\narc: H00L0000 H02W0001\narc: H00R0000 N1_V02S0401\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H02E0701\narc: S1_V02S0101 H06E0103\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N1_V02S0201\narc: V00B0000 V02S0201\narc: V00B0100 V02N0101\narc: W1_H02W0701 V02S0701\narc: A7 N1_V01N0101\narc: B7 V00T0000\narc: C7 V02N0001\narc: CE0 H00R0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: E1_H02E0601 Q4\narc: E1_H02E0701 F7\narc: E3_H06E0203 Q4\narc: F7 F7_SLICE\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M0 V00B0100\narc: M2 H02W0601\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q2\narc: V00T0000 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R12C60:PLC2\narc: N1_V02N0601 S1_V02N0301\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\n\n.tile R12C62:PLC2\narc: E3_H06E0303 W3_H06E0303\n\n.tile R12C63:PLC2\narc: E3_H06E0003 W3_H06E0303\n\n.tile R12C64:PLC2\narc: E3_H06E0003 W3_H06E0003\n\n.tile R12C66:PLC2\narc: E3_H06E0303 W3_H06E0203\n\n.tile R12C68:PLC2\narc: E3_H06E0303 W3_H06E0303\n\n.tile R12C69:PLC2\narc: S3_V06S0303 H06E0303\narc: S3_V06S0003 W3_H06E0003\n\n.tile R12C6:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 V02S0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0601 H06W0303\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0701 H06E0203\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 W1_H02E0401\narc: V00B0100 V02N0101\narc: V00T0000 H02E0201\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0601 S1_V02N0601\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q6\narc: H01W0000 Q6\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 H02E0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: S1_V02S0001 Q2\narc: S1_V02S0601 Q4\narc: S3_V06S0103 Q2\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R12C70:PLC2\narc: N1_V02N0301 W3_H06E0003\narc: S1_V02S0301 W3_H06E0003\n\n.tile R12C7:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 W1_H02E0701\narc: H00R0100 H02W0701\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H02W0501\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0103 H06W0103\narc: S3_V06S0303 H01E0101\narc: V00B0000 V02N0201\narc: V00B0100 V02S0301\narc: V00T0100 V02N0501\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 E1_H02W0601\narc: W3_H06W0003 E3_H06W0003\narc: A7 H00L0000\narc: B7 V00T0000\narc: C7 V02S0201\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D7 V02S0601\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0000 F7\narc: H01W0100 Q4\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 V00B0000\narc: M2 V00T0100\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: S3_V06S0203 Q4\narc: V00T0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R12C8:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 S1_V02N0401\narc: H00L0100 E1_H02W0101\narc: H00R0100 E1_H02W0501\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 E1_H02W0601\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 H06E0203\narc: V00B0000 H02E0601\narc: V00T0000 H02E0001\narc: V00T0100 S1_V02N0501\narc: S3_V06S0003 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A1 V02N0501\narc: A6 H02E0701\narc: A7 H00L0000\narc: B1 V00B0000\narc: B6 V00B0100\narc: B7 V00T0000\narc: C1 H00R0100\narc: C5 V02S0201\narc: C6 N1_V02S0201\narc: C7 V02S0001\narc: CE1 V02N0201\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0001\narc: D5 V02S0401\narc: D6 W1_H02E0201\narc: D7 H00L0100\narc: E1_H01E0101 F5\narc: E1_H02E0701 F5\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 F1\narc: LSR1 E1_H02W0301\narc: M2 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0101 F5\narc: S3_V06S0303 F5\narc: V00B0100 F7\narc: V01S0000 F5\narc: W1_H02W0501 F5\narc: W1_H02W0701 F5\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000001001000001\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R12C9:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 V06S0303\narc: H00L0000 N1_V02S0201\narc: H00R0100 H02W0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H02E0701\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N1_V01S0100\narc: V00B0100 V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0303 V06S0303\narc: W3_H06W0203 E3_H06W0203\narc: A5 V00T0000\narc: B5 H00R0000\narc: C5 N1_V02S0001\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D5 H00R0100\narc: E1_H02E0701 F5\narc: F5 F5_SLICE\narc: H00R0000 Q6\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00B0100\narc: M2 V00B0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: V00B0000 Q6\narc: V00T0000 Q0\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R14C10:PLC2\narc: E3_H06E0003 W1_H02E0001\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H02W0501\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 N1_V02S0601\narc: V00T0100 N1_V02S0501\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E1_H02W0301\narc: W3_H06W0103 E3_H06W0003\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 V02N0501\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: H01W0100 Q6\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q2\narc: S3_V06S0203 Q4\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V00T0000 Q0\narc: V01S0000 Q0\narc: V01S0100 Q7\narc: W1_H02W0001 Q2\narc: W1_H02W0101 Q3\narc: W1_H02W0301 Q1\narc: W1_H02W0701 Q5\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C11:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 N1_V02S0301\narc: E3_H06E0303 S3_V06N0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 E1_H02W0701\narc: V00T0100 V02N0501\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 E1_H02W0701\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E1_H01W0000\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H01W0100\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 V01S0000\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q6\narc: H01W0100 Q2\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q2\narc: N1_V02N0201 Q0\narc: N1_V02N0301 Q1\narc: N1_V02N0401 Q6\narc: S1_V02S0301 Q1\narc: S3_V06S0103 Q2\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V00T0000 Q0\narc: V01S0000 Q7\narc: V01S0100 Q6\narc: W1_H02W0001 Q0\narc: W1_H02W0301 Q3\narc: W1_H02W0501 Q7\narc: W1_H02W0601 Q4\narc: W1_H02W0701 Q5\narc: W3_H06W0003 Q3\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C12:PLC2\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: W3_H06W0303 E1_H02W0501\narc: W3_H06W0203 E3_H06W0203\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 H02E0101\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q5\narc: H01W0100 Q7\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q2\narc: N1_V02N0001 Q0\narc: N1_V02N0401 Q4\narc: S1_V02S0601 Q6\narc: S3_V06S0103 Q1\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V00T0000 Q0\narc: V01S0000 Q4\narc: V01S0100 Q0\narc: W1_H02W0101 Q1\narc: W1_H02W0201 Q2\narc: W1_H02W0301 Q3\narc: W1_H02W0401 Q4\narc: W1_H02W0501 Q7\narc: W1_H02W0701 Q5\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C13:PLC2\narc: E1_H02E0301 N1_V02S0301\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0303 H06W0303\narc: V00T0100 V02N0701\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E1_H01W0100\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H01W0100\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 V01S0000\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q1\narc: H01W0100 Q2\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q1\narc: N1_V02N0001 Q2\narc: N3_V06N0303 Q6\narc: S3_V06S0103 Q1\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V00T0000 Q0\narc: V01S0000 Q7\narc: V01S0100 Q2\narc: W1_H02W0001 Q0\narc: W1_H02W0101 Q3\narc: W1_H02W0201 Q2\narc: W1_H02W0401 Q6\narc: W1_H02W0501 Q5\narc: W1_H02W0601 Q4\narc: W1_H02W0701 Q7\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C14:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 N3_V06S0203\narc: N1_V02N0101 V01N0101\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 N3_V06S0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0303 E1_H01W0100\narc: W1_H02W0401 N3_V06S0203\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 V02S0501\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: H01W0100 Q1\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q7\narc: N1_V02N0001 Q2\narc: N3_V06N0003 Q0\narc: S3_V06S0203 Q4\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V00T0000 Q0\narc: V01S0000 Q3\narc: V01S0100 Q0\narc: W1_H02W0201 Q2\narc: W1_H02W0301 Q3\narc: W1_H02W0501 Q7\narc: W1_H02W0701 Q5\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C15:PLC2\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 S1_V02N0401\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0003 N3_V06S0303\narc: W3_H06W0103 E3_H06W0003\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 V02S0501\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q3\narc: H01W0100 Q4\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q7\narc: N1_V02N0401 Q6\narc: S1_V02S0101 Q3\narc: S1_V02S0701 Q7\narc: S3_V06S0103 Q1\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V00T0000 Q0\narc: V01S0000 Q2\narc: V01S0100 Q6\narc: W1_H02W0101 Q1\narc: W1_H02W0201 Q0\narc: W1_H02W0501 Q5\narc: W1_H02W0701 Q7\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q5\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R14C16:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 S1_V02N0601\narc: N1_V02N0201 S1_V02N0701\narc: S1_V02S0001 H06W0003\narc: S1_V02S0301 E1_H02W0301\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 N1_V02S0001\narc: W3_H06W0303 E3_H06W0303\narc: B0 V00T0000\narc: B1 Q1\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: LSR0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V00T0000 Q0\narc: W1_H02W0001 Q0\narc: W1_H02W0301 Q1\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C17:PLC2\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 V02N0501\narc: H00R0000 N1_V02S0601\narc: H00R0100 H02E0501\narc: S1_V02S0001 V01N0001\narc: S1_V02S0701 V01N0101\narc: V00T0100 N1_V02S0501\narc: W1_H02W0501 W3_H06E0303\narc: A5 V00B0000\narc: B5 H00R0000\narc: C5 H02E0601\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D5 V02N0601\narc: E1_H01E0001 F5\narc: F5 F5_SLICE\narc: LSR0 V00T0100\narc: M6 H02W0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00B0000 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R14C18:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 H01E0001\narc: E3_H06E0003 S3_V06N0003\narc: H00R0100 N1_V02S0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0401 N3_V06S0203\narc: S3_V06S0103 H06W0103\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: V00T0100 H02E0301\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 N1_V01S0000\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0003 E3_H06W0003\narc: A5 V00T0000\narc: B5 V00B0100\narc: C5 V02N0201\narc: CE0 H00R0100\narc: CE1 S1_V02N0201\narc: CLK0 G_HPBX0000\narc: D5 V02S0601\narc: E1_H01E0101 F5\narc: E1_H02E0201 Q2\narc: F5 F5_SLICE\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00T0100\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: V00T0000 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R14C19:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 H02W0201\narc: H00R0000 H02W0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H02W0101\narc: S1_V02S0401 H06W0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02E0501\narc: V00T0000 H02E0201\narc: W1_H02W0301 S1_V02N0301\narc: W3_H06W0003 E3_H06W0003\narc: A1 V01N0101\narc: A2 E1_H01E0001\narc: A3 S1_V02N0701\narc: A4 F5\narc: A5 V00T0000\narc: A6 E1_H01W0000\narc: A7 H00L0000\narc: B1 N1_V02S0101\narc: B2 E1_H01W0100\narc: B3 V02S0101\narc: B4 F1\narc: B5 V02S0701\narc: B6 H02E0301\narc: B7 S1_V02N0501\narc: C1 H02E0401\narc: C2 H00R0100\narc: C3 H02E0401\narc: C4 H02E0601\narc: C5 S1_V02N0001\narc: C6 H02E0401\narc: C7 F6\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H01E0101\narc: D3 V00B0100\narc: D4 N1_V02S0401\narc: D5 N1_V02S0601\narc: D6 H02W0001\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: LSR0 W1_H02E0501\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0111111111111111\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0001001101011111\nword: SLICED.K1.INIT 1000111111111111\nword: SLICEB.K0.INIT 0111111111111111\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R14C20:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0303 S3_V06N0303\narc: H00R0100 V02S0701\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: V00B0100 V02N0101\narc: V00T0000 H02E0001\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0401 N3_V06S0203\narc: W3_H06W0003 V06S0003\narc: W3_H06W0203 E3_H06W0103\narc: A3 V00B0000\narc: B3 V02S0301\narc: C3 H02E0601\narc: CE0 H00R0100\narc: CE2 H00R0100\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D3 H02W0201\narc: F3 F3_SLICE\narc: H01W0000 Q6\narc: H01W0100 F3\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00B0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: V00B0000 Q4\narc: W1_H02W0201 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R14C21:PLC2\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V01N0001\narc: H00L0000 V02N0201\narc: H00R0000 H02E0401\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 V01N0101\narc: S3_V06S0303 E3_H06W0303\narc: V00T0000 H02W0001\narc: V01S0100 N3_V06S0303\narc: W1_H02W0201 E1_H02W0701\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: A1 E1_H01E0001\narc: B1 H02W0101\narc: C1 H00L0000\narc: CE1 H00R0000\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 V01S0100\narc: E1_H01E0001 Q2\narc: F1 F1_SLICE\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M2 H02E0601\narc: M4 H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V02N0401 Q4\narc: W1_H02W0101 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R14C22:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 V01N0001\narc: H00L0000 V02S0001\narc: H00L0100 V02N0301\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 E1_H02W0201\narc: V00B0000 N1_V02S0001\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0401 N1_V01S0000\narc: W3_H06W0003 E3_H06W0303\narc: A3 E1_H01E0001\narc: B3 S1_V02N0301\narc: B5 H00R0000\narc: C1 H00L0000\narc: C3 H00L0100\narc: C4 V00B0100\narc: C5 V02S0201\narc: C6 V02S0001\narc: C7 H02E0601\narc: CE1 E1_H02W0101\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D1 V01S0100\narc: D3 V02N0201\narc: D4 E1_H02W0001\narc: D5 N1_V02S0601\narc: D6 H00R0100\narc: D7 V02N0601\narc: E1_H01E0001 Q3\narc: E3_H06E0103 F1\narc: E3_H06E0203 F4\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H00R0100 F7\narc: H01W0000 F7\narc: LSR0 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: N3_V06N0203 F4\narc: N3_V06N0303 Q5\narc: S1_V02S0501 F7\narc: S1_V02S0701 Q5\narc: S3_V06S0203 F4\narc: V00B0100 Q5\narc: V01S0000 Q3\narc: V01S0100 F7\narc: W3_H06W0203 F7\narc: W3_H06W0303 Q5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111100110011001\nword: SLICED.K0.INIT 0000111100000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0000000011110000\nword: SLICEC.K1.INIT 0011001111110011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R14C23:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0501 W1_H02E0501\narc: H00L0000 S1_V02N0201\narc: H00R0100 V02S0701\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 E1_H01W0000\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02N0301\narc: V00T0000 N1_V02S0401\narc: W1_H02W0101 V02N0101\narc: W1_H02W0701 N3_V06S0203\narc: A3 S1_V02N0501\narc: A5 V00B0000\narc: A6 V00T0100\narc: B0 H01W0100\narc: B1 Q1\narc: B3 V01N0001\narc: B5 S1_V02N0501\narc: B6 H02E0101\narc: B7 V02N0701\narc: C0 H02E0601\narc: C1 H02E0401\narc: C3 H00L0000\narc: C5 V01N0101\narc: C6 H02W0401\narc: C7 F6\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 N1_V02S0001\narc: D3 V00B0100\narc: D5 V02S0401\narc: D6 H00L0100\narc: D7 H00R0100\narc: E1_H01E0101 F0\narc: E1_H02E0601 F4\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H01W0100 Q1\narc: LSR0 V00T0000\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N3_V06N0103 Q1\narc: S1_V02S0401 F4\narc: V00T0100 Q1\narc: V01S0000 F7\nword: SLICED.K0.INIT 0000000010110011\nword: SLICED.K1.INIT 1111000000110000\nword: SLICEA.K0.INIT 1111001100110011\nword: SLICEA.K1.INIT 1100111111001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000001000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R14C24:PLC2\narc: E1_H02E0201 V02N0201\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02N0001\narc: H00L0100 V02N0101\narc: H00R0000 V02N0601\narc: H00R0100 V02S0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0501 E1_H01W0100\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 H02E0501\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0203 E3_H06W0203\narc: V00T0000 V02N0401\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 S1_V02N0401\narc: E1_H01E0001 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: A4 N1_V01N0101\narc: A7 Q7\narc: B0 V02S0301\narc: B2 H00R0100\narc: B4 S1_V02N0701\narc: B6 V00B0000\narc: B7 V00B0000\narc: C0 H00R0100\narc: C1 H02W0601\narc: C2 H02W0601\narc: C3 H02W0601\narc: C4 V00T0000\narc: C5 V00B0100\narc: C6 V02S0001\narc: C7 V02S0001\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 H02E0201\narc: D5 N1_V02S0401\narc: D6 H02W0201\narc: D7 H02W0201\narc: E1_H01E0101 F4\narc: E1_H02E0101 F1\narc: E1_H02E0501 Q5\narc: E1_H02E0601 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q5\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 E1_H02W0601\narc: M1 H00L0100\narc: M2 E1_H02W0601\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q5\narc: N1_V02N0301 F1\narc: V00B0000 Q6\narc: V00B0100 Q5\narc: V01S0000 Q6\narc: V01S0100 Q7\nword: SLICED.K0.INIT 1111001100110011\nword: SLICED.K1.INIT 1111100110011001\nword: SLICEC.K0.INIT 1010111110101100\nword: SLICEC.K1.INIT 1111111111110000\nword: SLICEA.K0.INIT 1100001100000000\nword: SLICEA.K1.INIT 1111111100001111\nword: SLICEB.K0.INIT 1100110000001111\nword: SLICEB.K1.INIT 1111111100001111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R14C25:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 H01E0001\narc: E3_H06E0203 S3_V06N0203\narc: H00L0100 V02S0101\narc: H00R0000 V02N0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 H02E0101\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H06E0203\narc: V00B0100 V02N0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 E1_H02W0601\narc: W3_H06W0003 E3_H06W0003\narc: B1 H00R0100\narc: C0 H00R0100\narc: C1 H00L0100\narc: C3 H02E0601\narc: C5 H02E0601\narc: C7 H02E0601\narc: D0 H01E0101\narc: D1 H01E0101\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 V02N0401\narc: D5 V02N0401\narc: D6 V02N0401\narc: D7 V02N0401\narc: E1_H01E0101 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F3\narc: M0 V00B0100\narc: M1 W1_H02E0001\narc: M2 V00B0100\narc: M3 H02E0201\narc: M4 V00B0100\narc: M5 W1_H02E0001\narc: M6 V00B0100\narc: N1_V02N0101 F3\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 0000000011110000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011110000\nword: SLICEA.K0.INIT 1111111111110000\nword: SLICEA.K1.INIT 1111111111000011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R14C26:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 S1_V02N0001\narc: H00L0100 H02E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H06E0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02W0501\narc: V00T0000 V02N0601\narc: V00T0100 N1_V02S0701\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 E1_H01W0000\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0103 V06S0103\narc: A3 H02E0501\narc: A4 V00B0000\narc: A5 V00T0000\narc: B3 H02E0101\narc: B4 V02S0501\narc: B5 H02W0301\narc: C2 H00L0100\narc: C3 H02E0601\narc: C4 V02N0201\narc: C5 V00T0100\narc: C6 E1_H01E0101\narc: C7 H02W0401\narc: CLK0 G_HPBX0000\narc: D2 H02W0201\narc: D3 H02W0201\narc: D4 H02E0201\narc: D5 V02S0401\narc: D6 N1_V02S0601\narc: D7 V02N0401\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: E1_H02E0601 Q4\narc: E1_H02E0701 F5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: H01W0100 F1\narc: LSR0 H02E0301\narc: M0 V00B0100\narc: M1 H00L0000\narc: M2 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 F5\narc: S1_V02S0501 F5\narc: S3_V06S0303 F5\narc: V01S0000 F7\narc: W1_H02W0101 F1\narc: W1_H02W0701 F5\nword: SLICEC.K0.INIT 1000100011111000\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 0000000000001111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 1111111110100110\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R14C27:PLC2\narc: H00L0000 V02N0001\narc: H00R0100 V02S0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0701 H02E0701\narc: S1_V02S0701 H02E0701\narc: S3_V06S0303 N1_V02S0601\narc: V00T0000 V02S0601\narc: V00T0100 S1_V02N0701\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 E1_H01W0100\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: A1 V02S0501\narc: A3 H02E0501\narc: A5 N1_V02S0101\narc: B1 H02E0101\narc: B3 H00R0100\narc: B5 V02N0701\narc: C1 V02N0401\narc: C3 S1_V02N0401\narc: C5 V00T0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D3 S1_V02N0001\narc: D5 V02S0401\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F3\narc: H01W0100 F0\narc: M0 V00B0100\narc: M6 H02W0401\narc: MUXCLK3 CLK0\narc: V00B0100 F5\narc: V01S0000 F0\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010111110101100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R14C28:PLC2\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0501 W1_H02E0501\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02N0301\narc: W1_H02W0401 N1_V02S0401\narc: H01W0000 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0303 E3_H06W0203\narc: C1 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: E1_H01E0001 Q1\narc: E1_H02E0001 Q2\narc: F1 F1_SLICE\narc: H00L0100 Q1\narc: H01W0100 Q1\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M2 W1_H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R14C29:PLC2\narc: H00R0000 H02W0401\narc: N1_V02N0001 H02E0001\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0201 H01E0001\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: M4 E1_H02W0401\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q4\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R14C2:PLC2\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0003 S3_V06N0003\narc: H00R0000 V02S0401\narc: H00R0100 N1_V02S0501\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: V00T0100 V02N0501\narc: CE1 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: E3_H06E0103 Q2\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M2 V00B0000\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R14C30:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0401 E3_H06W0203\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 S1_V02N0301\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E1_H01W0100\narc: W1_H02W0401 V01N0001\narc: E1_H02E0601 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0103\n\n.tile R14C31:PLC2\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 H02E0601\narc: N3_V06N0103 S3_V06N0103\narc: V00B0000 H02W0401\narc: W1_H02W0401 N1_V01S0000\narc: E1_H01E0101 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: CE1 V02N0201\narc: CLK0 G_HPBX0000\narc: H01W0100 Q2\narc: M2 V00B0000\narc: MUXCLK1 CLK0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R14C32:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0401 V01N0001\narc: E3_H06E0103 V06N0103\narc: H00L0000 W1_H02E0001\narc: H00R0000 V02N0401\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 H02W0301\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 E1_H02W0001\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 V02N0101\narc: W1_H02W0401 E1_H02W0401\narc: E3_H06E0303 W3_H06E0203\narc: C3 H00L0000\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 V02N0201\narc: E1_H01E0101 Q0\narc: E1_H02E0201 Q0\narc: F3 F3_SLICE\narc: LSR1 V00T0100\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: V00T0100 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111111100001111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R14C33:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V01N0001\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 S3_V06N0003\narc: H00L0100 V02N0301\narc: H00R0000 N1_V02S0601\narc: H00R0100 H02W0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 H01E0101\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0001\narc: V00B0100 H02W0701\narc: W1_H02W0301 V06N0003\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: C1 H02E0401\narc: C5 V02N0201\narc: CE0 H00L0100\narc: CE1 H00R0000\narc: CE2 H00L0100\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D5 H00R0100\narc: E1_H02E0001 Q2\narc: E3_H06E0303 Q6\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: M2 E1_H02W0601\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q5\narc: N1_V02N0101 Q1\narc: N3_V06N0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R14C34:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0701 V02N0701\narc: E3_H06E0203 V06S0203\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 W1_H02E0201\narc: H00L0100 N1_V02S0101\narc: H00R0100 V02N0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 N3_V06S0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0401 S3_V06N0203\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 V02S0101\narc: V00T0100 H02E0101\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0701 S3_V06N0203\narc: N1_V02N0701 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 S1_V02N0501\narc: A2 E1_H01E0001\narc: A4 H02E0701\narc: A7 H02E0701\narc: B0 H01W0100\narc: B2 V02S0301\narc: B3 V01N0001\narc: B4 S1_V02N0501\narc: B6 V01S0000\narc: B7 F3\narc: C0 N1_V01N0001\narc: C2 V02N0401\narc: C3 H00L0000\narc: C4 V01N0101\narc: C5 H02E0401\narc: C6 V02N0001\narc: C7 V01N0101\narc: D0 V00B0100\narc: D2 V00T0100\narc: D3 V02S0001\narc: D4 H00L0100\narc: D5 H00L0100\narc: D6 W1_H02E0001\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 F6\narc: E1_H02E0101 F3\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 F7\narc: M0 V00B0000\narc: N1_V01N0001 F5\narc: N1_V02N0101 F3\narc: S1_V02S0501 F5\narc: S1_V02S0701 F5\narc: S3_V06S0003 F0\narc: S3_V06S0303 F5\narc: V00B0000 F4\narc: V01S0000 F7\narc: W1_H02W0001 F2\nword: SLICEC.K0.INIT 0000001100000111\nword: SLICEC.K1.INIT 0000000000001111\nword: SLICEB.K0.INIT 0000010000001111\nword: SLICEB.K1.INIT 0000001100001111\nword: SLICED.K0.INIT 1100000011111111\nword: SLICED.K1.INIT 0100000000000000\nword: SLICEA.K0.INIT 1111101110111011\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C35:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 S1_V02N0401\narc: E3_H06E0303 H01E0101\narc: H00L0000 W1_H02E0201\narc: H00R0000 H02E0401\narc: H00R0100 V02N0701\narc: N1_V02N0101 H02E0101\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 H06W0203\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 V02N0101\narc: V00T0000 H02W0201\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 V01N0101\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 E3_H06W0203\narc: B7 V00T0000\narc: C3 N1_V02S0401\narc: C7 N1_V02S0001\narc: CE1 H00L0000\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: D7 H02E0201\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: M4 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q3\narc: N1_V01N0101 Q4\narc: V01S0000 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110011110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R14C36:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V06S0203\narc: E3_H06E0103 V06S0103\narc: E3_H06E0203 W1_H02E0401\narc: H00L0100 E1_H02W0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 N1_V02S0501\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 H06W0203\narc: N1_V02N0601 E1_H01W0000\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0701 H06W0203\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 H06E0303\narc: V00T0100 H02W0301\narc: V01S0100 S3_V06N0303\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0103 E3_H06W0003\narc: A3 E1_H01E0001\narc: B3 H00R0000\narc: B4 V01S0000\narc: B6 V00B0000\narc: C3 H00L0100\narc: C4 V00T0100\narc: C6 V02N0201\narc: CLK0 G_HPBX0000\narc: D3 E1_H02W0201\narc: D4 H02W0201\narc: D5 H00R0100\narc: D6 H02W0201\narc: D7 V02S0601\narc: E1_H01E0001 Q4\narc: E1_H01E0101 F2\narc: E1_H02E0201 F2\narc: E3_H06E0303 Q6\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: LSR0 H02E0301\narc: M2 N1_V01N0001\narc: M4 E1_H01E0101\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q2\narc: S1_V02S0601 Q6\narc: V00B0000 Q6\narc: V00T0000 F2\narc: V01S0000 Q4\narc: W1_H02W0201 Q2\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R14C37:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 H01E0001\narc: H00L0000 W1_H02E0001\narc: H00R0000 N1_V02S0601\narc: H00R0100 H02W0501\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 V01N0001\narc: N1_V02N0601 H06E0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 W1_H02E0401\narc: S3_V06S0103 H06W0103\narc: V00B0000 S1_V02N0201\narc: V00T0000 H02E0001\narc: V00T0100 H02E0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 S1_V02N0301\narc: A3 E1_H01E0001\narc: A4 H02W0701\narc: A5 V00T0100\narc: B3 S1_V02N0101\narc: B4 E1_H02W0101\narc: B5 E1_H02W0301\narc: C3 H00L0000\narc: C4 V00B0100\narc: C5 H02E0401\narc: CE0 H00R0000\narc: CE2 N1_V02S0601\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D3 E1_H02W0001\narc: D4 V02S0401\narc: D5 H00R0100\narc: E1_H01E0001 Q6\narc: E1_H02E0001 Q0\narc: E3_H06E0303 F5\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q5\narc: M0 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0001 Q0\narc: N1_V02N0301 F3\narc: S3_V06S0203 F4\narc: V00B0100 F5\narc: W1_H02W0501 F5\narc: W3_H06W0303 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000001001000001\nword: SLICEC.K0.INIT 1001110110111111\nword: SLICEC.K1.INIT 0000111000000100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R14C38:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0701 S3_V06N0203\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 H02W0201\narc: H00R0000 H02W0401\narc: H00R0100 V02N0501\narc: N1_V02N0201 S1_V02N0701\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 H02W0601\narc: S3_V06S0103 E3_H06W0103\narc: V00B0100 H02W0701\narc: V00T0000 H02E0001\narc: V00T0100 V02S0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 V06N0103\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 V06S0203\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0103 W3_H06E0103\narc: A0 E1_H01E0001\narc: A1 E1_H01E0001\narc: A6 N1_V01N0101\narc: A7 V02S0301\narc: B0 N1_V02S0301\narc: B1 V00T0000\narc: B6 V00B0000\narc: B7 V02S0701\narc: C0 H02W0401\narc: C1 H00L0000\narc: C6 E1_H01E0101\narc: C7 V02N0201\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 H00R0000\narc: D6 V01N0001\narc: D7 E1_H02W0001\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M2 W1_H02E0601\narc: M4 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q7\narc: N1_V02N0401 F6\narc: N3_V06N0203 Q7\narc: S1_V02S0101 F1\narc: S3_V06S0203 Q7\narc: V00B0000 Q4\narc: V01S0000 F7\narc: W3_H06W0203 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111010100110001\nword: SLICEA.K1.INIT 1010001011110011\nword: SLICED.K0.INIT 1001000000000000\nword: SLICED.K1.INIT 0100010001000111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R14C39:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 W1_H02E0701\narc: H00L0100 H02E0101\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 V01N0001\narc: S1_V02S0201 H06W0103\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H02E0701\narc: V00B0100 E1_H02W0701\narc: V00T0100 H02E0301\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 V02S0701\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0203 E3_H06W0103\narc: A3 V00T0000\narc: B0 V00T0000\narc: B3 H01W0100\narc: B4 H00R0000\narc: B6 V00B0000\narc: C0 H00L0100\narc: C3 N1_V01N0001\narc: C4 E1_H02W0601\narc: C6 V02N0201\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0201\narc: D1 N1_V02S0201\narc: D3 V00B0100\narc: D4 W1_H02E0201\narc: D5 H02E0001\narc: D6 W1_H02E0201\narc: D7 H00R0100\narc: E1_H01E0101 Q4\narc: E1_H02E0201 Q0\narc: E3_H06E0003 Q0\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 Q4\narc: H01W0000 F3\narc: H01W0100 Q4\narc: LSR1 E1_H02W0501\narc: M0 V00T0100\narc: M4 V00T0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q6\narc: N1_V02N0201 Q0\narc: N1_V02N0601 Q4\narc: S3_V06S0003 Q0\narc: S3_V06S0203 Q4\narc: S3_V06S0303 Q6\narc: V00B0000 Q6\narc: V00T0000 Q0\narc: V01S0000 Q6\narc: V01S0100 Q0\narc: W3_H06W0003 Q0\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R14C3:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 H01E0101\narc: E1_H02E0501 H01E0101\narc: H00R0000 H02E0601\narc: H00R0100 H02E0501\narc: H01W0100 E3_H06W0303\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 E3_H06W0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02S0101\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02N0501\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H02E0001 Q0\narc: E1_H02E0601 Q6\narc: E3_H06E0103 Q2\narc: E3_H06E0303 Q6\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00T0000\narc: M2 V00B0100\narc: M4 H02E0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V02N0601 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R14C40:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V06N0103\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0501 V01N0101\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0203 S3_V06N0203\narc: H00L0100 H02E0301\narc: H00R0100 V02N0501\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 E1_H02W0401\narc: N3_V06N0303 H06E0303\narc: S1_V02S0301 N1_V02S0301\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 V02S0001\narc: V00T0100 W1_H02E0301\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 E1_H01W0100\narc: E1_H02E0401 W3_H06E0203\narc: W3_H06W0303 V06S0303\narc: A6 V02S0101\narc: A7 H02E0701\narc: B1 V02S0301\narc: B2 H00L0000\narc: B4 H00R0000\narc: B6 H02E0101\narc: B7 V02N0701\narc: C1 H00L0100\narc: C2 H02W0401\narc: C4 V01N0101\narc: C6 E1_H01E0101\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: D2 S1_V02N0001\narc: D3 N1_V02S0001\narc: D4 S1_V02N0601\narc: D5 H02E0001\narc: D6 V00B0000\narc: D7 H00R0100\narc: E1_H01E0001 Q4\narc: E1_H01E0101 F7\narc: E1_H02E0001 Q2\narc: E1_H02E0601 F6\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M2 V00T0100\narc: M4 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V02N0001 Q2\narc: S1_V02S0001 Q2\narc: S1_V02S0101 F1\narc: S1_V02S0401 Q4\narc: S3_V06S0103 Q2\narc: S3_V06S0203 Q4\narc: W1_H02W0201 Q2\narc: W1_H02W0401 Q4\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111100\nword: SLICED.K0.INIT 0000000000000111\nword: SLICED.K1.INIT 1000000010101010\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R14C41:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 H02W0201\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 N3_V06S0303\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02E0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E1_H01W0100\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0303 E3_H06W0203\narc: A2 V02S0501\narc: A3 V00T0000\narc: A5 V00T0100\narc: B2 E1_H02W0101\narc: B3 H02E0101\narc: B4 V02N0501\narc: B5 V01S0000\narc: C2 H00L0100\narc: C3 V02N0601\narc: C4 V02S0201\narc: C5 V00B0100\narc: CE0 H00L0000\narc: CLK0 G_HPBX0000\narc: D2 E1_H02W0201\narc: D3 V02N0001\narc: D4 H02W0001\narc: D5 V00B0000\narc: E1_H01E0101 F4\narc: E1_H02E0501 F5\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0100 F3\narc: H01W0100 F4\narc: M0 W1_H02E0601\narc: MUXCLK0 CLK0\narc: V00B0000 F4\narc: V01S0000 F2\narc: V01S0100 Q0\narc: W1_H02W0201 Q0\narc: W3_H06W0203 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1001000000000000\nword: SLICEB.K1.INIT 1000001001000001\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1000000001000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R14C42:PLC2\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 V06S0003\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02S0201\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 H01E0101\narc: V00B0000 H02E0601\narc: V00B0100 W1_H02E0501\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02S0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S3_V06N0203\narc: E1_H02E0101 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: S3_V06S0303 W3_H06E0303\narc: W3_H06W0103 V06S0103\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A1 H02E0701\narc: A4 V00B0000\narc: A5 V00B0000\narc: B1 H02W0301\narc: B4 H02E0301\narc: B5 H02E0301\narc: B7 V02N0701\narc: C1 H00L0000\narc: C4 V00B0100\narc: C5 V00B0100\narc: C7 N1_V02S0001\narc: CE1 V02N0201\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D4 H02E0201\narc: D5 H02E0201\narc: D7 V02N0601\narc: E1_H01E0001 F4\narc: E1_H01E0101 F0\narc: E3_H06E0103 Q2\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: M0 V00T0100\narc: M2 V00T0000\narc: MUXCLK1 CLK0\narc: N1_V01N0101 F5\narc: N3_V06N0103 Q2\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111100\nword: SLICEC.K0.INIT 1010111100100011\nword: SLICEC.K1.INIT 1100010011110101\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000010000100001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R14C43:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 V01N0001\narc: H00L0000 W1_H02E0001\narc: H00R0100 V02S0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0601 H02W0601\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 S1_V02N0001\narc: V00T0100 V02N0501\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 S3_V06N0303\narc: H01W0100 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: A3 V00B0000\narc: A4 V02S0301\narc: A5 E1_H02W0501\narc: B3 H00L0000\narc: B4 E1_H02W0101\narc: B5 H02W0301\narc: C3 E1_H02W0401\narc: C4 H02E0401\narc: C5 H02W0401\narc: CE0 H02W0101\narc: CLK0 G_HPBX0000\narc: D2 W1_H02E0001\narc: D3 V02S0001\narc: D4 E1_H02W0001\narc: D5 H01W0000\narc: E1_H01E0001 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F4\narc: M0 V00T0100\narc: M1 H00R0100\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F1\narc: S1_V02S0101 F1\narc: S1_V02S0301 F1\narc: S1_V02S0501 F5\narc: S3_V06S0103 Q1\narc: V01S0000 Q1\nword: SLICEC.K0.INIT 1010101111101111\nword: SLICEC.K1.INIT 0111000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000100011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R14C44:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0103 V06S0103\narc: E3_H06E0203 W1_H02E0701\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 H02E0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02W0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0301 W1_H02E0301\narc: N3_V06N0003 E1_H01W0000\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02E0001\narc: V00T0100 V02N0501\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 S3_V06N0303\narc: E1_H02E0401 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: A3 V00T0000\narc: B3 V02S0101\narc: C3 H02E0601\narc: CE0 H00L0100\narc: CE2 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V02S0001\narc: D3 V02S0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 F1\narc: H01W0100 F1\narc: M0 V00T0100\narc: M1 H00L0000\narc: M2 V00T0100\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q1\narc: S1_V02S0101 Q1\narc: V00B0000 Q6\narc: V01S0000 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0010000011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R14C45:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 N3_V06S0003\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02N0201\narc: H00L0100 H02E0101\narc: H00R0000 H02E0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 S1_V02N0301\narc: S1_V02S0201 V01N0001\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 E1_H01W0100\narc: V00B0100 V02N0301\narc: V00T0000 V02S0401\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 V01N0001\narc: H01W0000 W3_H06E0103\narc: A0 V02S0501\narc: A1 S1_V02N0501\narc: B0 H02W0301\narc: B1 H02E0301\narc: B3 V02S0301\narc: C0 N1_V01N0001\narc: C1 H00L0100\narc: C2 E1_H02W0401\narc: C3 N1_V02S0601\narc: CE0 H00R0100\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 H00R0000\narc: D2 N1_V02S0201\narc: D3 V02S0001\narc: E1_H01E0001 F0\narc: E3_H06E0203 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: M2 V00B0100\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F1\narc: N3_V06N0103 Q1\narc: N3_V06N0203 Q4\narc: S3_V06S0103 F1\narc: V01S0000 F2\narc: W1_H02W0301 F1\narc: W3_H06W0103 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0011000100100000\nword: SLICEA.K1.INIT 0000000011001010\nword: SLICEB.K0.INIT 0000000011110000\nword: SLICEB.K1.INIT 0000001100110011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R14C46:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 V02N0601\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 W1_H02E0601\narc: H00L0100 W1_H02E0101\narc: H00R0000 W1_H02E0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 V01N0101\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 H01E0001\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02N0201\narc: V00T0000 H02W0001\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 V06N0003\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0501 N3_V06S0303\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0203 W3_H06E0203\narc: A0 H02W0701\narc: A1 S1_V02N0501\narc: A2 E1_H02W0701\narc: A3 V00B0000\narc: A5 V02S0301\narc: A7 V02S0101\narc: B0 V00T0000\narc: B1 H02W0301\narc: B2 V02N0301\narc: B3 H00R0100\narc: B5 V02S0501\narc: B7 V02S0701\narc: C0 S1_V02N0601\narc: C1 H00L0100\narc: C2 N1_V01N0001\narc: C3 H00L0100\narc: C5 V02S0201\narc: C7 E1_H01E0101\narc: D0 V01S0100\narc: D1 H00R0000\narc: D2 V00T0100\narc: D3 H00R0000\narc: D5 V02S0601\narc: D7 V02S0401\narc: E1_H01E0101 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: H01W0100 F2\narc: N1_V01N0001 F3\narc: N1_V01N0101 F5\narc: S1_V02S0501 F5\narc: S1_V02S0701 F5\narc: V01S0000 F7\narc: V01S0100 F1\narc: W3_H06W0003 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0011001000010000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0111111100000000\nword: SLICEA.K0.INIT 1011000011110000\nword: SLICEA.K1.INIT 0000000011001010\nword: SLICEB.K0.INIT 0101111100010011\nword: SLICEB.K1.INIT 0000000011001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R14C47:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 W1_H02E0201\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02N0401\narc: H00R0100 H02E0501\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 V01N0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 H06E0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0601\narc: V00T0000 H02E0201\narc: V00T0100 H02E0101\narc: W1_H02W0001 V06S0003\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0003 V06S0003\narc: A6 V02S0101\narc: A7 E1_H02W0501\narc: B4 W1_H02E0301\narc: B5 W1_H02E0101\narc: B6 V02S0701\narc: B7 V02N0701\narc: C2 H02W0401\narc: C3 H02E0401\narc: C4 V00B0100\narc: C5 S1_V02N0001\narc: C6 E1_H01E0101\narc: C7 V00T0100\narc: CE0 H00L0000\narc: CE1 V02N0201\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D2 H00R0000\narc: D3 H02W0001\narc: D4 N1_V02S0401\narc: D5 N1_V02S0601\narc: D6 V00B0000\narc: D7 H00R0100\narc: E1_H01E0001 F6\narc: E1_H01E0101 F7\narc: E3_H06E0003 Q0\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: H01W0100 Q0\narc: M0 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q3\narc: N1_V01N0101 Q3\narc: N1_V02N0001 Q2\narc: N1_V02N0301 Q3\narc: S1_V02S0001 F2\narc: S1_V02S0501 F5\narc: V00B0100 F5\narc: V01S0100 Q5\narc: W1_H02W0501 F7\narc: W3_H06W0203 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000001111\nword: SLICEB.K1.INIT 0000000000001111\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 0011001000010000\nword: SLICED.K1.INIT 0000000011001010\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R14C48:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 V02N0601\narc: E3_H06E0303 V01N0101\narc: H00L0000 E1_H02W0201\narc: H00L0100 H02E0301\narc: H00R0000 V02N0601\narc: H00R0100 S1_V02N0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H02W0701\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 V01N0001\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H06W0303\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 N1_V02S0001\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0701 N1_V01S0100\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0501 W3_H06E0303\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: B0 H01W0100\narc: B1 V00T0000\narc: B6 S1_V02N0501\narc: B7 E1_H02W0301\narc: C0 H02E0401\narc: C1 H00L0000\narc: C6 E1_H01E0101\narc: C7 H02W0401\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 H02E0001\narc: D6 V00B0000\narc: D7 H02E0201\narc: E1_H01E0101 F7\narc: E3_H06E0103 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q7\narc: M2 H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0003 Q0\narc: V00T0000 Q0\narc: W1_H02W0301 F1\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1100110011110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R14C49:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0203 H01E0001\narc: H00R0000 V02N0601\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 V01N0001\narc: S1_V02S0001 H01E0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0201\narc: V01S0100 S3_V06N0303\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V01N0101\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0001 W3_H06E0003\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0103 V06N0103\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: E3_H06E0003 Q0\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: N1_V01N0101 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C4:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0301 V02S0301\narc: H00L0100 H02E0101\narc: H00R0100 V02N0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 H02E0201\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0103\narc: V00T0000 H02E0001\narc: V00T0100 N1_V02S0501\narc: A1 H00R0000\narc: B1 V00T0000\narc: C1 H00L0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: F1 F1_SLICE\narc: H00R0000 Q6\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M2 H02W0601\narc: M4 E1_H01E0101\narc: M6 H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V02N0101 F1\narc: N1_V02N0401 Q4\narc: N3_V06N0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R14C50:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 S1_V02N0501\narc: E3_H06E0103 W1_H02E0201\narc: H00L0000 N1_V02S0001\narc: H00R0000 W1_H02E0601\narc: H00R0100 H02E0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02N0301\narc: V00T0000 S1_V02N0601\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 N3_V06S0303\narc: E1_H02E0201 W3_H06E0103\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 E1_H02W0501\narc: E3_H06E0003 W3_H06E0303\narc: B2 H00R0100\narc: B3 W1_H02E0301\narc: C2 H00L0100\narc: C3 V02S0401\narc: CE1 H00L0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 W1_H02E0001\narc: D3 V00B0100\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H00L0100 F3\narc: H01W0100 Q6\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: N1_V02N0601 Q6\narc: S1_V02S0101 F3\narc: V01S0100 Q3\narc: W3_H06W0103 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R14C51:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02N0601\narc: E3_H06E0003 V01N0001\narc: H00L0000 V02N0201\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02N0201\narc: V00T0000 H02W0201\narc: V00T0100 E1_H02W0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 N3_V06S0203\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0303 N1_V01S0100\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A0 H00L0000\narc: A2 V00B0000\narc: A4 H02W0701\narc: A7 E1_H02W0501\narc: B0 E1_H02W0301\narc: B2 E1_H01W0100\narc: B4 S1_V02N0501\narc: B5 H02W0101\narc: B7 V00T0000\narc: C0 E1_H02W0401\narc: C2 H02W0601\narc: C4 V00T0100\narc: C5 S1_V02N0201\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D2 H00R0000\narc: D4 V02N0401\narc: D5 N1_V02S0401\narc: D7 V02N0401\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H01W0000 Q0\narc: H01W0100 Q2\narc: M0 E1_H02W0601\narc: M2 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: V00B0100 F5\narc: V01S0100 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000110000001010\nword: SLICEC.K0.INIT 0000101000001100\nword: SLICEC.K1.INIT 1100000000000000\nword: SLICEA.K0.INIT 1111111111101100\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111111101100\nword: SLICEB.K1.INIT 1111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R14C52:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E3_H06E0003 V06S0003\narc: E3_H06E0203 W1_H02E0401\narc: H00R0000 S1_V02N0601\narc: H00R0100 H02E0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S1_V02N0301\narc: N3_V06N0103 H01E0101\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 S1_V02N0101\narc: V00T0000 E1_H02W0201\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 H01E0101\narc: E1_H02E0601 W3_H06E0303\narc: H01W0000 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A3 S1_V02N0501\narc: A5 V00T0000\narc: A6 S1_V02N0101\narc: B3 H00R0100\narc: B5 W1_H02E0101\narc: B6 V00B0000\narc: B7 V00B0100\narc: C3 S1_V02N0401\narc: C5 V01N0101\narc: C6 V01N0101\narc: C7 N1_V02S0201\narc: D3 H00R0000\narc: D5 S1_V02N0601\narc: D6 S1_V02N0601\narc: D7 N1_V02S0401\narc: E1_H01E0001 F7\narc: E1_H01E0101 F6\narc: E1_H02E0701 F5\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1110111001100000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1110111001100000\nword: SLICED.K0.INIT 1110111001100000\nword: SLICED.K1.INIT 1100000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R14C53:PLC2\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 V01N0101\narc: H00L0000 V02S0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 H02W0601\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00T0000 N1_V02S0401\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 H01E0101\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 N1_V02S0701\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0003 V01N0001\narc: E3_H06E0103 W3_H06E0003\narc: A0 E1_H02W0701\narc: A2 H00L0100\narc: A3 V02S0701\narc: A4 H02W0701\narc: A5 V00T0000\narc: A6 H00L0000\narc: A7 H00R0000\narc: B2 H00R0100\narc: B3 E1_H02W0101\narc: B4 V02N0701\narc: B5 S1_V02N0701\narc: B6 H02E0101\narc: B7 W1_H02E0301\narc: E1_H01E0101 F5\narc: E1_H02E0201 F2\narc: E3_H06E0003 F3\narc: E3_H06E0203 F4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: W1_H02W0401 F6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C54:PLC2\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0701 N1_V02S0701\narc: H00L0000 S1_V02N0001\narc: H00L0100 V02S0301\narc: H00R0000 N1_V02S0601\narc: H00R0100 V02N0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0103 H01E0101\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 V01N0001\narc: S1_V02S0401 H02W0401\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 H02W0601\narc: V00T0000 V02N0601\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V06S0203\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0101 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: N3_V06N0203 W3_H06E0203\narc: S1_V02S0001 W3_H06E0003\narc: S1_V02S0301 W3_H06E0003\narc: S1_V02S0701 W3_H06E0203\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\narc: A0 H00L0100\narc: A1 N1_V02S0501\narc: A2 S1_V02N0501\narc: A3 V01N0101\narc: A4 H02E0501\narc: A5 V00B0000\narc: A6 H02E0701\narc: A7 V02N0301\narc: B0 H00R0100\narc: B1 S1_V02N0301\narc: B2 S1_V02N0101\narc: B3 H00L0000\narc: B4 H02W0301\narc: B5 H00R0000\narc: B6 V00T0000\narc: B7 S1_V02N0701\narc: E1_H01E0001 F3\narc: E1_H02E0201 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: N1_V01N0001 F7\narc: N3_V06N0003 F0\narc: N3_V06N0303 F5\narc: S1_V02S0601 F4\narc: W1_H02W0301 F1\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C55:PLC2\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0303 H01E0101\narc: H00L0000 V02N0001\narc: H00L0100 V02S0101\narc: H00R0000 H02W0601\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0203 S1_V02N0401\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 H02W0501\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0401\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E1_H02W0701\narc: E1_H01E0001 W3_H06E0003\narc: N3_V06N0003 W3_H06E0003\narc: S1_V02S0701 W3_H06E0203\narc: W3_H06W0203 V01N0001\narc: A0 V02N0701\narc: A1 V01N0101\narc: A2 N1_V02S0501\narc: A3 H00L0100\narc: A4 V02N0101\narc: A5 S1_V02N0101\narc: A6 V02N0301\narc: A7 H00L0000\narc: B0 E1_H02W0101\narc: B1 V00B0000\narc: B2 S1_V02N0301\narc: B3 E1_H01W0100\narc: B4 H00R0000\narc: B5 W1_H02E0301\narc: B6 S1_V02N0501\narc: B7 H02E0101\narc: E1_H01E0101 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: N1_V01N0001 F3\narc: N1_V02N0001 F0\narc: N1_V02N0401 F4\narc: N1_V02N0501 F5\narc: N3_V06N0103 F2\narc: N3_V06N0303 F6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C56:PLC2\narc: E1_H02E0401 V01N0001\narc: E1_H02E0701 N1_V02S0701\narc: H00L0100 N1_V02S0301\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 V01N0001\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 H01E0101\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 N1_V02S0201\narc: V00T0000 S1_V02N0601\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 H01E0001\narc: E1_H01E0101 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: N1_V02N0001 W3_H06E0003\narc: N3_V06N0203 W3_H06E0203\narc: A0 V02S0501\narc: A1 H02W0501\narc: A2 H00L0100\narc: A3 V00B0000\narc: A4 E1_H02W0501\narc: A5 S1_V02N0101\narc: A6 E1_H02W0701\narc: A7 E1_H01W0000\narc: B0 S1_V02N0301\narc: B1 H02W0301\narc: B2 V02S0301\narc: B3 V02N0301\narc: B4 S1_V02N0701\narc: B5 S1_V02N0501\narc: B6 E1_H02W0101\narc: B7 V00T0000\narc: E1_H01E0001 F0\narc: E1_H02E0001 F2\narc: E1_H02E0601 F6\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: N1_V01N0001 F5\narc: N3_V06N0103 F1\narc: V01S0000 F4\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C57:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0601 W1_H02E0301\narc: H00L0100 E1_H02W0101\narc: H00R0100 H02E0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 V01N0001\narc: N3_V06N0303 H01E0101\narc: S1_V02S0001 H02W0001\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 E1_H02W0401\narc: V00T0100 V02N0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 V06N0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0501 V06S0303\narc: W1_H02W0701 V02N0701\narc: N1_V02N0601 W3_H06E0303\narc: A0 F5\narc: A1 E1_H01E0001\narc: B0 E1_H02W0301\narc: B1 H02W0301\narc: C4 V00T0100\narc: C5 V00T0100\narc: C6 V00T0100\narc: C7 H02E0401\narc: D4 V00B0000\narc: D5 E1_H02W0201\narc: D6 H00L0100\narc: D7 H00R0100\narc: E1_H01E0001 F4\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: N1_V01N0001 F0\narc: V01S0000 F1\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C58:PLC2\narc: E1_H02E0001 V02N0001\narc: H00L0000 V02N0201\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 S1_V02N0601\narc: S3_V06S0303 N1_V01S0100\narc: V00B0100 W1_H02E0701\narc: V00T0100 V02N0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 H01E0101\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: A3 V01N0101\narc: A5 S1_V02N0101\narc: A6 S1_V02N0101\narc: A7 V02N0101\narc: B3 H00R0100\narc: B5 V00B0100\narc: B6 V00B0100\narc: B7 V01S0000\narc: C3 H00L0000\narc: C5 V00T0100\narc: C6 N1_V02S0001\narc: C7 W1_H02E0601\narc: CLK0 G_HPBX0000\narc: D3 H02E0001\narc: D5 H02W0001\narc: D6 H01W0000\narc: D7 H00L0100\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H01W0000 F7\narc: H01W0100 Q6\narc: MUXCLK3 CLK0\narc: V01S0000 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1110111001100000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000110000001010\nword: SLICED.K0.INIT 1000000011111111\nword: SLICED.K1.INIT 0000000000010011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R14C59:PLC2\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 H06E0203\narc: S1_V02S0301 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V02N0401\narc: E1_H01E0101 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0101 W3_H06E0103\narc: W1_H02W0201 W3_H06E0103\n\n.tile R14C5:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 W1_H02E0601\narc: H00R0100 H02W0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 E1_H02W0201\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 E3_H06W0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0303 H06W0303\narc: V00B0100 W1_H02E0501\narc: V00T0100 H02W0301\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 H01E0001\narc: A7 H00R0000\narc: B7 W1_H02E0301\narc: C7 V02S0001\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D7 V02N0401\narc: E1_H01E0101 F7\narc: E3_H06E0103 Q2\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00B0000\narc: M2 V00B0100\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q2\narc: V00B0000 Q4\narc: V01S0100 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R14C60:PLC2\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0301 H01E0101\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: W1_H02W0101 S1_V02N0101\narc: S1_V02S0101 W3_H06E0103\n\n.tile R14C62:PLC2\narc: S1_V02S0001 N3_V06S0003\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\n\n.tile R14C64:PLC2\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V01S0100 N3_V06S0303\n\n.tile R14C69:PLC2\narc: E1_H02E0301 N1_V01S0100\n\n.tile R14C6:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 E3_H06W0103\narc: H00L0100 V02N0301\narc: H00R0100 E1_H02W0501\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 W1_H02E0001\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0701 E1_H02W0601\narc: A1 V02N0501\narc: A3 V00T0000\narc: A5 V02S0101\narc: A6 N1_V01N0101\narc: A7 F5\narc: B1 H00R0100\narc: B3 H02E0101\narc: B5 V00B0100\narc: B6 V02S0701\narc: B7 H01E0101\narc: C1 E1_H02W0601\narc: C3 H00L0100\narc: C5 V02S0001\narc: C6 E1_H01E0101\narc: C7 V02N0201\narc: CLK0 G_HPBX0000\narc: D1 V02S0201\narc: D3 H02E0201\narc: D5 V02S0601\narc: D6 V02N0601\narc: D7 V00B0000\narc: E1_H02E0301 F3\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 H02W0301\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q7\narc: N3_V06N0303 F6\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000010000100001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1001000000001001\nword: SLICED.K0.INIT 0000000000000001\nword: SLICED.K1.INIT 0111111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R14C70:PLC2\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 V02N0501\narc: S3_V06S0303 N3_V06S0303\n\n.tile R14C7:PLC2\narc: E1_H02E0301 E1_H01W0100\narc: H00L0000 V02N0001\narc: H00L0100 H02E0101\narc: H01W0100 E3_H06W0303\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 W1_H02E0401\narc: V00B0100 W1_H02E0701\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0701 E1_H02W0601\narc: W3_H06W0103 E1_H01W0100\narc: A0 H00L0100\narc: A1 H02W0701\narc: A2 V02S0501\narc: A5 V00T0100\narc: A6 V00T0100\narc: A7 H02W0701\narc: B0 E1_H02W0101\narc: B1 H02E0101\narc: B2 H02E0301\narc: B3 H01W0100\narc: B4 V02N0701\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 E1_H02W0301\narc: C0 H00L0000\narc: C1 V02N0601\narc: C2 F4\narc: C3 W1_H02E0601\narc: C4 S1_V02N0201\narc: C5 W1_H02E0401\narc: C6 E1_H01E0101\narc: C7 E1_H02W0401\narc: D0 E1_H02W0001\narc: D1 V02N0001\narc: D2 H02E0001\narc: D3 V02N0201\narc: D4 V02S0401\narc: D5 V02N0401\narc: D6 N1_V02S0401\narc: D7 E1_H02W0001\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: N1_V01N0001 F5\narc: N1_V01N0101 F0\narc: S1_V02S0401 F6\narc: V01S0000 F1\narc: V01S0100 F2\nword: SLICEA.K0.INIT 1010111100100011\nword: SLICEA.K1.INIT 1010111100100011\nword: SLICED.K0.INIT 1101000000000000\nword: SLICED.K1.INIT 1101000011011101\nword: SLICEC.K0.INIT 1100001100000000\nword: SLICEC.K1.INIT 1000110000100011\nword: SLICEB.K0.INIT 1000000000000000\nword: SLICEB.K1.INIT 1100001100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R14C8:PLC2\narc: N1_V02N0101 H06W0103\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: V00T0000 V02N0601\narc: V00T0100 V02N0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0701 E1_H02W0601\narc: E1_H02E0201 W3_H06E0103\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0303 E3_H06W0203\narc: A0 V02N0701\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 H02E0301\narc: B6 V00B0000\narc: B7 V00B0100\narc: CLK0 G_HPBX0000\narc: E1_H02E0001 Q2\narc: E3_H06E0303 Q6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q3\narc: H01W0100 Q5\narc: LSR0 V00T0100\narc: LSR1 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V02N0501 Q7\narc: S1_V02S0601 Q6\narc: V00B0000 Q6\narc: V00B0100 Q7\narc: V01S0000 Q7\narc: V01S0100 Q3\narc: W1_H02W0201 Q2\narc: W1_H02W0401 Q6\narc: W1_H02W0501 Q5\narc: W1_H02W0601 Q4\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R14C9:PLC2\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: V00T0100 V02N0501\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 E1_H02W0601\narc: E1_H02E0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: B0 V00T0000\narc: B1 Q1\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V01S0000\narc: B6 V00B0000\narc: B7 V00B0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: H01W0100 Q3\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q1\narc: N1_V02N0501 Q7\narc: N1_V02N0601 Q6\narc: S1_V02S0101 Q1\narc: S1_V02S0401 Q6\narc: S3_V06S0103 Q1\narc: S3_V06S0203 Q7\narc: S3_V06S0303 Q6\narc: V00B0000 Q6\narc: V00B0100 Q7\narc: V00T0000 Q0\narc: V01S0000 Q5\narc: V01S0100 Q4\narc: W1_H02W0201 Q2\narc: W1_H02W0501 Q5\narc: W3_H06W0003 Q0\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C10:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 H01E0101\narc: E1_H02E0501 V06N0303\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V06S0203\narc: E3_H06E0203 V06N0203\narc: H00L0000 V02S0201\narc: H00L0100 H02E0101\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0501 N1_V01S0100\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H02E0601\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 E1_H02W0601\narc: V00T0000 V02S0601\narc: V00T0100 V02N0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0501 V06N0303\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 V06N0203\narc: A0 H00L0000\narc: A1 H00L0100\narc: A2 V02N0501\narc: A3 H01E0001\narc: A4 V00T0000\narc: A5 V00T0100\narc: A6 V02N0301\narc: A7 V02N0101\narc: B0 H00R0100\narc: B1 V02S0101\narc: B2 N1_V02S0101\narc: B3 V02S0301\narc: B4 H00R0000\narc: B5 V02S0701\narc: B6 V00B0000\narc: B7 V02S0501\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C11:PLC2\narc: H00R0000 V02S0601\narc: N1_V02N0501 H02E0501\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0301 H02E0301\narc: S1_V02S0501 H06E0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 H06W0303\narc: V00B0000 V02S0001\narc: V00T0000 V02S0401\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 V02S0601\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A0 H02E0701\narc: A1 V02N0701\narc: A2 V01N0101\narc: A3 V02N0501\narc: A4 S1_V02N0101\narc: A5 W1_H02E0701\narc: A6 H02W0701\narc: A7 V02N0101\narc: B0 V00B0000\narc: B1 N1_V02S0301\narc: B2 E1_H02W0101\narc: B3 V02S0101\narc: B4 H00R0000\narc: B5 V02S0501\narc: B6 V00T0000\narc: B7 V02S0701\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C12:PLC2\narc: E1_H02E0701 V06S0203\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 V02S0201\narc: H00L0100 N1_V02S0301\narc: H00R0000 H02W0601\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 N1_V02S0001\narc: V00T0000 W1_H02E0001\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0003 E1_H02W0301\narc: W3_H06W0203 N1_V01S0000\narc: A0 H00L0100\narc: A1 V02N0701\narc: A2 V02N0501\narc: A3 S1_V02N0501\narc: A4 V02S0101\narc: A5 V00T0000\narc: A6 N1_V02S0101\narc: A7 S1_V02N0101\narc: B0 E1_H02W0301\narc: B1 H02W0301\narc: B2 H00L0000\narc: B3 V02S0301\narc: B4 H00R0000\narc: B5 V02S0701\narc: B6 V00B0000\narc: B7 V02S0501\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C13:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0601 V02N0601\narc: H00R0000 E1_H02W0401\narc: H01W0100 E3_H06W0303\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0201\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 V02S0301\narc: W1_H02W0601 V02S0601\narc: W3_H06W0203 N1_V01S0000\narc: A0 H02W0701\narc: A1 V02N0701\narc: A2 V01N0101\narc: A3 V02N0501\narc: A4 E1_H02W0701\narc: A5 S1_V02N0101\narc: A6 S1_V02N0301\narc: A7 H02W0501\narc: B0 V00B0000\narc: B1 V02S0101\narc: B2 H00R0000\narc: B3 V02N0101\narc: B4 H02W0101\narc: B5 V02S0501\narc: B6 E1_H02W0301\narc: B7 V02S0701\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C14:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0401 N1_V01S0000\narc: H00L0000 V02N0201\narc: H00R0000 H02E0601\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0301 E1_H02W0301\narc: N3_V06N0103 S3_V06N0103\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0001\narc: V00T0100 H02W0101\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0501 V01N0101\narc: W1_H02W0601 E1_H02W0601\narc: E1_H02E0601 W3_H06E0303\narc: S1_V02S0601 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 W1_H02E0701\narc: A1 H00R0000\narc: A5 E1_H02W0701\narc: B0 V00B0000\narc: B1 V02S0301\narc: B5 H00L0000\narc: C5 V02N0001\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D5 H02W0201\narc: F2 F2_SLICE\narc: F5 F5_SLICE\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F5\narc: V01S0000 Q6\narc: W3_H06W0103 F2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C15:PLC2\narc: E3_H06E0003 S3_V06N0003\narc: H00R0000 H02E0601\narc: H00R0100 V02N0501\narc: N1_V02N0301 E1_H01W0100\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02W0501\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02S0501\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0303 V06S0303\narc: W3_H06W0003 E3_H06W0303\narc: A3 E1_H01E0001\narc: A4 V02N0301\narc: B3 V01N0001\narc: B4 V00B0100\narc: B5 V01S0000\narc: C3 H00R0100\narc: C4 V00T0100\narc: C5 E1_H02W0601\narc: CE0 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 S1_V02N0201\narc: D4 S1_V02N0601\narc: D5 V00B0000\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q6\narc: E1_H02E0601 F4\narc: E3_H06E0303 F5\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F3\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00T0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N3_V06N0303 F5\narc: V01S0000 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 0000110000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R15C16:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0601 E1_H01W0000\narc: H00L0000 H02W0201\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 H02W0301\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0001\narc: V00B0100 H02W0501\narc: V00T0100 V02N0501\narc: W1_H02W0301 V06N0003\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 H01E0101\narc: E3_H06E0303 W3_H06E0203\narc: B1 E1_H01W0100\narc: B5 H00L0000\narc: B7 V00B0100\narc: C1 V02N0401\narc: C3 E1_H02W0401\narc: C5 E1_H02W0601\narc: C6 H02E0601\narc: C7 H02W0601\narc: CE0 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 E1_H02W0201\narc: D3 H00R0000\narc: D4 H02W0001\narc: D5 E1_H02W0201\narc: D6 V00B0000\narc: D7 H01W0000\narc: E1_H01E0001 F6\narc: E1_H01E0101 F7\narc: E1_H02E0101 F3\narc: E3_H06E0003 F0\narc: E3_H06E0203 F4\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H00R0100 F7\narc: H01W0000 F6\narc: H01W0100 Q0\narc: LSR0 E1_H02W0501\narc: M0 V00T0100\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR0\narc: N1_V02N0001 F0\narc: N1_V02N0601 Q4\narc: N3_V06N0003 Q0\narc: N3_V06N0203 Q4\narc: S3_V06S0003 F0\narc: V01S0000 F4\narc: V01S0100 F7\narc: W1_H02W0601 F4\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111111100001111\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 1111001100110000\nword: SLICEC.K0.INIT 1111111100000000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1100110011110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R15C17:PLC2\narc: E1_H02E0501 V02N0501\narc: H00L0000 H02W0201\narc: H00R0000 V02N0401\narc: H00R0100 V02N0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H01E0101\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 H02W0201\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 E1_H02W0601\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A1 V02S0701\narc: A2 H00L0100\narc: A3 H00L0100\narc: B1 Q1\narc: B2 V02N0101\narc: B3 V02N0101\narc: B5 H02E0301\narc: B6 V01S0000\narc: C0 H00L0100\narc: C1 H02E0601\narc: C2 H00L0000\narc: C3 H00L0000\narc: C5 V02S0001\narc: C6 V02N0001\narc: C7 V02N0201\narc: CE0 H02W0101\narc: CE2 H02W0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 Q0\narc: D1 H02W0201\narc: D2 E1_H02W0201\narc: D3 E1_H02W0201\narc: D5 H01W0000\narc: D6 H00R0100\narc: D7 H02E0201\narc: E1_H01E0001 F2\narc: E1_H01E0101 F6\narc: E1_H02E0701 Q7\narc: E3_H06E0103 F2\narc: E3_H06E0203 Q7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: H01W0000 Q0\narc: H01W0100 Q1\narc: LSR0 H02W0301\narc: LSR1 E1_H02W0301\narc: M2 N1_V01N0001\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q5\narc: N1_V02N0201 F2\narc: V01S0000 Q7\narc: V01S0100 Q0\narc: W1_H02W0201 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011110011110000\nword: SLICED.K0.INIT 0000000011000000\nword: SLICED.K1.INIT 1111111111110000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 0011001100110010\nword: SLICEB.K0.INIT 0000000011111110\nword: SLICEB.K1.INIT 0000000001111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R15C18:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0601 E3_H06W0303\narc: H00L0100 E1_H02W0301\narc: H01W0000 E3_H06W0103\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0701 H02E0701\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02S0001\narc: V00B0100 H02W0701\narc: V00T0000 V02S0401\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 E1_H02W0601\narc: E1_H02E0501 W3_H06E0303\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: H01W0100 Q2\narc: M0 V00T0000\narc: M2 V00B0100\narc: M4 E1_H02W0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0303 Q6\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R15C19:PLC2\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 S1_V02N0501\narc: H00R0000 N1_V02S0601\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 E3_H06W0303\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E1_H01W0100\narc: V00B0100 N1_V02S0301\narc: V00T0000 H02E0201\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\narc: A5 V00B0000\narc: B5 V01S0000\narc: C4 Q4\narc: C5 H02E0601\narc: C6 E1_H01E0101\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D4 V02N0401\narc: D5 H02W0201\narc: D6 V02N0401\narc: D7 H01W0000\narc: E1_H01E0101 Q4\narc: E3_H06E0203 F7\narc: E3_H06E0303 F5\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: H01W0100 F4\narc: LSR0 H02E0501\narc: LSR1 W1_H02E0501\narc: M0 V00T0000\narc: M2 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q0\narc: N1_V02N0601 F6\narc: N3_V06N0203 F7\narc: V00B0000 Q4\narc: V01S0000 Q6\narc: V01S0100 Q2\narc: W1_H02W0401 Q4\narc: W1_H02W0601 Q6\narc: W3_H06W0203 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111000000001111\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000111100000000\nword: SLICEC.K1.INIT 0000000000001101\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R15C20:PLC2\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: H00R0000 V02S0601\narc: N1_V02N0101 N1_V01S0100\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 V01N0101\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02S0101\narc: V00T0100 S1_V02N0501\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 E3_H06W0203\narc: C1 E1_H02W0601\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: F1 F1_SLICE\narc: H01W0000 F1\narc: H01W0100 Q1\narc: M2 V00B0000\narc: M4 E1_H02W0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R15C21:PLC2\narc: E1_H02E0301 V02S0301\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V01N0101\narc: E3_H06E0303 W1_H02E0501\narc: N1_V02N0201 H06W0103\narc: N1_V02N0501 S3_V06N0303\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 V02N0001\narc: V00B0100 H02W0701\narc: V00T0100 N1_V02S0701\narc: W1_H02W0201 E1_H02W0201\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0001 W3_H06E0003\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0303 E3_H06W0203\narc: A0 V02S0501\narc: A1 V02S0501\narc: A3 V02N0501\narc: A5 E1_H02W0701\narc: A7 H00L0000\narc: B0 V00T0000\narc: B1 V00T0000\narc: B3 V01N0001\narc: B5 V02N0701\narc: B6 S1_V02N0501\narc: B7 V01S0000\narc: C0 S1_V02N0401\narc: C1 S1_V02N0401\narc: C2 H02E0601\narc: C3 H02E0401\narc: C5 V02S0201\narc: C6 E1_H01E0101\narc: C7 V02N0201\narc: CE0 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 V01S0100\narc: D3 V01S0100\narc: D5 W1_H02E0201\narc: D6 H02W0201\narc: D7 V00B0000\narc: E1_H01E0101 F1\narc: E1_H02E0101 F3\narc: E1_H02E0201 Q0\narc: E1_H02E0501 F7\narc: E3_H06E0103 F2\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00R0000 F4\narc: H01W0000 Q0\narc: H01W0100 Q0\narc: LSR0 W1_H02E0301\narc: LSR1 W1_H02E0301\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F2\narc: N1_V01N0101 Q6\narc: S1_V02S0201 Q0\narc: S1_V02S0401 F4\narc: S1_V02S0601 Q6\narc: S3_V06S0203 F7\narc: V00T0000 Q0\narc: V01S0000 Q6\narc: V01S0100 F1\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 1010001011110011\nword: SLICED.K0.INIT 1100110011111100\nword: SLICED.K1.INIT 0100000000000000\nword: SLICEA.K0.INIT 0000000011001001\nword: SLICEA.K1.INIT 1100100100000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1010111000001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R15C22:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 H02E0201\narc: H00L0100 H02W0101\narc: H00R0000 H02W0401\narc: H00R0100 H02E0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 H01E0001\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 H06W0103\narc: V00B0000 H02E0601\narc: V00B0100 H02E0501\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02S0501\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E3_H06W0303\narc: N3_V06N0003 W3_H06E0003\narc: N3_V06N0203 W3_H06E0203\narc: S3_V06S0003 W3_H06E0003\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A2 W1_H02E0501\narc: A3 V00T0000\narc: A5 N1_V01N0101\narc: A7 H00L0000\narc: B1 E1_H01W0100\narc: B2 H02E0301\narc: B3 H01W0100\narc: B5 H02E0101\narc: B7 H02E0301\narc: C1 H00L0100\narc: C2 H00R0100\narc: C3 V02N0401\narc: C4 V00B0100\narc: C5 V00T0100\narc: C7 V02N0201\narc: D1 V02S0001\narc: D2 V02N0001\narc: D3 H00R0000\narc: D4 H01W0000\narc: D5 V00B0000\narc: D7 E1_H02W0201\narc: E1_H01E0001 F6\narc: E1_H01E0101 F6\narc: E1_H02E0301 F1\narc: E1_H02E0401 F4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: H01W0100 F2\narc: M6 H02W0401\narc: N1_V01N0101 F3\narc: V01S0100 F4\narc: W1_H02W0701 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111111100\nword: SLICEB.K0.INIT 0000000001000000\nword: SLICEB.K1.INIT 0010001100000011\nword: SLICEC.K0.INIT 0000000000001111\nword: SLICEC.K1.INIT 1000100000001000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000010000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R15C23:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0103 V06S0103\narc: H00L0100 V02N0101\narc: H00R0000 H02W0401\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 V01N0101\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0501 E1_H01W0100\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0303 N3_V06S0303\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0701 S1_V02N0701\narc: N3_V06N0203 W3_H06E0203\narc: S1_V02S0201 W3_H06E0103\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A0 H00L0100\narc: A1 V02N0501\narc: A2 V00B0000\narc: A4 V02N0101\narc: A5 V00B0000\narc: A6 F7\narc: B0 F3\narc: B1 V00T0000\narc: B2 H00L0000\narc: B3 V02N0301\narc: B4 F3\narc: B5 V01S0000\narc: B6 F3\narc: B7 V00B0000\narc: C0 H00R0100\narc: C1 N1_V01N0001\narc: C2 H02E0601\narc: C3 N1_V01N0001\narc: C4 V00B0100\narc: C5 H02E0601\narc: C6 S1_V02N0001\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 S1_V02N0201\narc: D2 V00T0100\narc: D3 V02N0201\narc: D4 V02N0601\narc: D5 V02N0401\narc: D6 H02E0201\narc: D7 H01W0000\narc: E1_H01E0001 F5\narc: E1_H01E0101 F1\narc: E1_H02E0301 F1\narc: E1_H02E0501 F7\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00R0100 F5\narc: H01W0000 Q2\narc: H01W0100 F7\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q4\narc: N1_V02N0701 F7\narc: S1_V02S0701 F5\narc: V00B0000 Q4\narc: V00B0100 F5\narc: V00T0000 Q0\narc: V01S0000 Q0\narc: V01S0100 Q2\narc: W1_H02W0101 F3\narc: W3_H06W0103 F1\narc: W3_H06W0303 F6\nword: SLICED.K0.INIT 0001000000000000\nword: SLICED.K1.INIT 0000001100000000\nword: SLICEB.K0.INIT 0000000011100001\nword: SLICEB.K1.INIT 0000001100110000\nword: SLICEA.K0.INIT 1111110011011100\nword: SLICEA.K1.INIT 0100000000000000\nword: SLICEC.K0.INIT 1101110011111100\nword: SLICEC.K1.INIT 1110000100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R15C24:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 W1_H02E0401\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 V06S0203\narc: E3_H06E0303 N3_V06S0303\narc: H00R0000 S1_V02N0601\narc: H00R0100 V02S0501\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 H02W0601\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 H01E0001\narc: S3_V06S0303 H01E0101\narc: V00B0000 V02S0001\narc: V00B0100 H02E0701\narc: V00T0000 H02W0001\narc: W1_H02W0201 V02N0201\narc: W3_H06W0103 N3_V06S0103\narc: W3_H06W0303 E3_H06W0203\narc: A1 H00R0000\narc: A5 V00T0000\narc: A6 F7\narc: B1 H02E0101\narc: B2 V02N0101\narc: B3 Q3\narc: B5 S1_V02N0701\narc: B6 S1_V02N0501\narc: C1 E1_H02W0601\narc: C2 H00R0100\narc: C3 N1_V01S0100\narc: C5 V01N0101\narc: C6 F4\narc: C7 H02E0601\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D2 E1_H02W0201\narc: D3 N1_V01S0000\narc: D5 V02N0601\narc: D6 E1_H02W0201\narc: D7 H02E0201\narc: E1_H01E0001 Q3\narc: E1_H01E0101 F7\narc: E1_H02E0001 F0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR0 V00B0000\narc: M0 V00B0100\narc: M4 H02E0401\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V02N0001 F2\narc: V01S0100 Q3\narc: W1_H02W0401 F6\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 1110000011000000\nword: SLICED.K1.INIT 0000000000001111\nword: SLICEB.K0.INIT 1111001100110011\nword: SLICEB.K1.INIT 1100111111001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1110110011001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1011101100001011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R15C25:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0003 H01E0001\narc: H00L0100 V02S0101\narc: H00R0000 V02S0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0101 V01N0101\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 W1_H02E0601\narc: V00B0100 V02S0301\narc: V00T0000 W1_H02E0201\narc: V00T0100 W1_H02E0301\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 V06N0303\narc: W1_H02W0701 E3_H06W0203\narc: H01W0100 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: B0 V00B0000\narc: B1 V00B0000\narc: B5 H01E0101\narc: C0 H00R0100\narc: C1 H00L0100\narc: C4 V00T0100\narc: C5 F4\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 H02W0001\narc: D4 V02S0601\narc: D5 E1_H01W0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q6\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F4\narc: LSR1 H02E0301\narc: M0 V00T0000\narc: M1 H00R0000\narc: M2 V00T0000\narc: M6 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F1\narc: N1_V02N0301 F1\narc: N3_V06N0103 F1\narc: N3_V06N0303 F5\narc: S1_V02S0301 F1\narc: V01S0000 F1\narc: V01S0100 Q6\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000001111\nword: SLICEC.K1.INIT 1111001100000000\nword: SLICEA.K0.INIT 1111111100110000\nword: SLICEA.K1.INIT 1111111100110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R15C26:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 H01E0001\narc: E1_H02E0601 V01N0001\narc: H00L0100 W1_H02E0101\narc: H00R0000 V02N0401\narc: H00R0100 H02E0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 H02E0601\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H02E0701\narc: V00B0100 W1_H02E0501\narc: V00T0100 V02S0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 E1_H01W0000\narc: A1 E1_H02W0501\narc: B1 H00R0100\narc: B3 H02E0301\narc: B5 V02N0701\narc: B7 V02N0701\narc: C1 H00L0100\narc: C2 E1_H02W0601\narc: C3 V02N0601\narc: C5 H02W0601\narc: C7 N1_V02S0001\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 N1_V01S0000\narc: D3 V00B0100\narc: D5 H02E0001\narc: D7 V02S0601\narc: E1_H01E0001 F1\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F2\narc: M2 H02E0601\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W3_H06W0203 Q7\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111001111000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111001111000000\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 1111001111000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010111110101100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R15C27:PLC2\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 W1_H02E0201\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 H06E0203\narc: S1_V02S0601 H02E0601\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 W1_H02E0401\narc: V00B0100 E1_H02W0701\narc: V00T0000 S1_V02N0401\narc: V00T0100 W1_H02E0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0601 E1_H02W0301\narc: H01W0000 W3_H06E0103\narc: W3_H06W0103 N3_V06S0103\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0203 E3_H06W0203\narc: A2 V00T0000\narc: A4 H02W0501\narc: A6 V00T0100\narc: B2 H02E0301\narc: B4 S1_V02N0701\narc: B6 V02S0701\narc: C2 V02N0601\narc: C4 V02N0201\narc: C5 S1_V02N0001\narc: C6 H02E0401\narc: D2 H02E0001\narc: D4 V01N0001\narc: D5 H02E0201\narc: D6 V00B0000\narc: E1_H01E0101 F4\narc: E1_H02E0401 F4\narc: E1_H02E0501 F5\narc: E1_H02E0601 F6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M0 E1_H02W0601\narc: M1 E1_H02W0001\narc: M2 E1_H02W0601\narc: M6 V00B0100\narc: N1_V02N0101 F1\narc: N3_V06N0103 F1\narc: W1_H02W0701 F5\nword: SLICEC.K0.INIT 1010111110101100\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 1000100011111000\nword: SLICED.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0000000000110111\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C28:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 N3_V06S0103\narc: H00L0100 H02E0301\narc: H00R0100 H02E0501\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 H06E0103\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 V01N0001\narc: S3_V06S0103 H06W0103\narc: S3_V06S0303 H06W0303\narc: V00T0000 H02E0201\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 E1_H01W0000\narc: S1_V02S0101 W3_H06E0103\narc: S3_V06S0003 W3_H06E0003\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0303 E3_H06W0203\narc: B1 S1_V02N0301\narc: C0 V02N0601\narc: C1 V02N0601\narc: C3 H02E0401\narc: C5 H02E0401\narc: C7 H02E0401\narc: D0 H01E0101\narc: D1 H01E0101\narc: D2 V02N0201\narc: D3 V02N0201\narc: D4 V02N0401\narc: D5 V02N0401\narc: D6 V02N0401\narc: D7 V02N0401\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H00L0100\narc: M2 V00T0000\narc: M3 H00R0100\narc: M4 V00T0000\narc: M5 H00L0100\narc: M6 V00T0000\narc: W1_H02W0101 F3\narc: W3_H06W0003 F3\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 0000000011110000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011110000\nword: SLICEA.K0.INIT 1111111111110000\nword: SLICEA.K1.INIT 1111111111000011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R15C29:PLC2\narc: E1_H02E0701 E3_H06W0203\narc: N1_V02N0701 E1_H01W0100\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 W1_H02E0601\narc: W1_H02W0001 V02N0001\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 V02N0701\narc: H01W0000 W3_H06E0103\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0203 N3_V06S0203\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: CE1 V02S0201\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: F3 F3_SLICE\narc: H01W0100 Q3\narc: LSR1 V00B0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00T0100 Q3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R15C2:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0501 V06S0303\narc: E3_H06E0103 V06S0103\narc: H00R0000 E1_H02W0401\narc: H00R0100 H02W0501\narc: N1_V02N0501 E1_H02W0501\narc: V00B0000 V02N0001\narc: V00B0100 H02E0701\narc: V00T0000 V02N0601\narc: A5 N1_V01N0101\narc: B5 H00R0000\narc: C5 V00T0000\narc: CE0 H00R0100\narc: CE1 V02N0201\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D5 V01N0001\narc: E3_H06E0303 Q6\narc: F5 F5_SLICE\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 H02E0601\narc: M2 V00B0100\narc: M6 N1_V01N0101\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q2\narc: S1_V02S0501 F5\narc: S3_V06S0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R15C30:PLC2\narc: E1_H02E0301 S3_V06N0003\narc: N1_V01N0001 N3_V06S0003\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 N3_V06S0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E1_H01W0100\narc: V00T0000 W1_H02E0001\narc: V00T0100 S1_V02N0701\narc: V01S0000 S3_V06N0103\narc: H01W0100 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\narc: B7 V00B0100\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D7 V02N0601\narc: F7 F7_SLICE\narc: LSR1 V00T0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: V00B0100 Q7\narc: W3_H06W0203 Q7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R15C31:PLC2\narc: E1_H02E0701 V06S0203\narc: H00R0000 E1_H02W0401\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0501 S3_V06N0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0401 E3_H06W0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 H06E0203\narc: V00B0100 W1_H02E0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0301 V06S0003\narc: W3_H06W0203 V06S0203\narc: W3_H06W0303 E3_H06W0203\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: H01W0100 Q2\narc: LSR0 H02E0301\narc: M2 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: W3_H06W0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R15C32:PLC2\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 V02N0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02N0001\narc: H00R0000 V02N0401\narc: H00R0100 H02W0501\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H02W0401\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0201 E1_H01W0000\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 H02W0501\narc: C3 H00L0000\narc: C7 V02N0001\narc: CE1 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: D7 H00R0100\narc: E1_H01E0001 Q3\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R15C33:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0301 V02N0301\narc: H00L0000 V02N0201\narc: H00R0000 H02W0401\narc: H00R0100 H02W0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 S3_V06N0003\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0201 V01N0001\narc: S1_V02S0401 H02E0401\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02W0701\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02N0501\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 E1_H02W0501\narc: E1_H02E0501 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A5 W1_H02E0701\narc: A6 N1_V01N0101\narc: A7 V02S0301\narc: B2 H00R0000\narc: B3 H01W0100\narc: B5 S1_V02N0501\narc: B6 V02S0501\narc: B7 H02W0101\narc: C0 E1_H01W0000\narc: C1 N1_V02S0401\narc: C2 H00R0100\narc: C3 H00L0000\narc: C5 V00T0000\narc: C6 H02E0601\narc: C7 V00B0100\narc: CE1 V02S0201\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 F0\narc: D2 V00T0100\narc: D3 V02S0001\narc: D5 V02N0601\narc: D6 V00B0000\narc: D7 S1_V02N0401\narc: E1_H01E0001 F1\narc: E1_H01E0101 F3\narc: E3_H06E0203 F7\narc: E3_H06E0303 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q2\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q6\narc: N1_V02N0001 Q2\narc: N1_V02N0501 Q5\narc: N1_V02N0601 Q6\narc: N3_V06N0203 F7\narc: S1_V02S0001 F0\narc: S1_V02S0501 F7\narc: S3_V06S0103 F1\narc: S3_V06S0203 F7\narc: V01S0100 F3\narc: W1_H02W0001 F0\narc: W3_H06W0203 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000001000000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0000000011000000\nword: SLICEB.K1.INIT 0000001100110011\nword: SLICED.K0.INIT 0110101010101010\nword: SLICED.K1.INIT 0000001000100010\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R15C34:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0203 S3_V06N0203\narc: H00L0100 E1_H02W0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 H06W0203\narc: V00B0000 V02N0201\narc: V00B0100 W1_H02E0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 V02S0101\narc: W1_H02W0401 V02S0401\narc: W1_H02W0701 V02S0701\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: B2 H02W0101\narc: B7 E1_H02W0101\narc: C1 N1_V01N0001\narc: C2 H02W0601\narc: C3 H00L0000\narc: C6 E1_H01E0101\narc: C7 F6\narc: CE1 H00L0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 N1_V02S0001\narc: D2 V00B0100\narc: D3 H00R0000\narc: D6 N1_V02S0401\narc: D7 H02E0001\narc: E1_H01E0001 F6\narc: E1_H01E0101 F1\narc: E1_H02E0501 F7\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 F1\narc: M4 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 F3\narc: S1_V02S0101 F1\narc: S3_V06S0303 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 0000000000001100\nword: SLICEB.K0.INIT 0011000000000000\nword: SLICEB.K1.INIT 1111000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R15C35:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 H01E0101\narc: H00L0000 V02N0001\narc: H00L0100 H02E0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 S1_V02N0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0201 H01E0001\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 V02N0101\narc: V00T0000 H02W0201\narc: V00T0100 V02N0701\narc: V01S0000 S3_V06N0103\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 N3_V06S0203\narc: W1_H02W0001 W3_H06E0003\narc: W3_H06W0203 E1_H02W0401\narc: A2 S1_V02N0701\narc: A4 V00B0000\narc: A6 V00T0100\narc: A7 E1_H01W0000\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H02E0101\narc: B3 H00R0100\narc: B4 V02S0701\narc: B5 N1_V02S0701\narc: B6 V00T0000\narc: B7 V02N0501\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0000\narc: C3 H00L0100\narc: C4 H02E0601\narc: C5 N1_V02S0001\narc: C6 E1_H01E0101\narc: C7 H02W0601\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02N0001\narc: D2 V02N0201\narc: D3 V02N0201\narc: D4 V02S0601\narc: D5 H02E0001\narc: D6 H02W0001\narc: D7 N1_V02S0601\narc: E1_H01E0001 F7\narc: E1_H01E0101 F1\narc: E1_H02E0701 F5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: H01W0100 F5\narc: LSR1 H02E0301\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N3_V06N0303 F5\narc: S1_V02S0401 Q4\narc: V00B0000 Q4\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 1111111100101010\nword: SLICEC.K1.INIT 1100000011111111\nword: SLICED.K0.INIT 0000110001011101\nword: SLICED.K1.INIT 0000011101110111\nword: SLICEA.K0.INIT 1100111111001100\nword: SLICEA.K1.INIT 0011001100111111\nword: SLICEB.K0.INIT 1110101011000000\nword: SLICEB.K1.INIT 1111111111110011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R15C36:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V02N0101\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V06N0303\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0003 V06S0003\narc: E3_H06E0103 V06S0103\narc: E3_H06E0203 W1_H02E0701\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 S1_V02N0001\narc: H00L0100 V02N0301\narc: H00R0000 V02N0401\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0001 V01N0001\narc: S1_V02S0501 W1_H02E0501\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 S1_V02N0201\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0201 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: A1 H00L0000\narc: B1 S1_V02N0101\narc: B7 V00B0000\narc: C1 S1_V02N0401\narc: C5 S1_V02N0001\narc: C7 V01N0101\narc: CE1 H02W0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D5 H00R0100\narc: D7 H00L0100\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q2\narc: M2 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0701 F5\narc: V00B0100 Q7\narc: V01S0000 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R15C37:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 V06S0303\narc: E1_H02E0701 V02N0701\narc: E3_H06E0103 S3_V06N0103\narc: H00L0100 W1_H02E0301\narc: H00R0100 H02E0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 S1_V02N0001\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0303 H06E0303\narc: V00B0100 W1_H02E0501\narc: V00T0000 E1_H02W0201\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0401 E3_H06W0203\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0303 V06S0303\narc: W3_H06W0203 E3_H06W0103\narc: A1 H00L0100\narc: A4 H02W0501\narc: A5 E1_H02W0501\narc: B1 H00R0100\narc: B4 E1_H02W0301\narc: B5 V00B0100\narc: C1 V02N0401\narc: C3 H02W0401\narc: C4 S1_V02N0201\narc: C5 E1_H01E0101\narc: CE1 E1_H02W0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0001\narc: D3 V00T0100\narc: D4 H02W0201\narc: D5 V02S0401\narc: E1_H01E0001 F5\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q3\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0203 F4\narc: V01S0000 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011110000\nword: SLICEC.K0.INIT 0011111100010101\nword: SLICEC.K1.INIT 0111000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R15C38:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 V01N0101\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0303 W1_H02E0601\narc: H00L0100 V02S0101\narc: H00R0000 N1_V02S0601\narc: H00R0100 H02E0501\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H06W0003\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0101 H06E0103\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 N1_V02S0401\narc: S3_V06S0103 N3_V06S0003\narc: V00T0000 V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 S1_V02N0501\narc: N1_V02N0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0103 E3_H06W0103\narc: A1 E1_H01E0001\narc: A5 V02N0301\narc: B0 V00T0000\narc: B1 V02S0301\narc: B4 V00B0100\narc: B5 H02E0301\narc: C0 E1_H02W0401\narc: C1 V02S0601\narc: C4 E1_H01E0101\narc: C5 V02N0201\narc: CE1 H00R0100\narc: CE2 H02W0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 H00R0000\narc: D4 H00L0100\narc: D5 V02N0401\narc: E1_H01E0001 F0\narc: E1_H01E0101 Q2\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q5\narc: M2 V00T0100\narc: M6 W1_H02E0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F4\narc: N3_V06N0303 Q5\narc: S3_V06S0003 F0\narc: S3_V06S0303 F5\narc: V00B0100 Q5\narc: V01S0000 Q5\narc: V01S0100 Q6\narc: W3_H06W0003 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1000001011000011\nword: SLICEC.K0.INIT 1100001100000000\nword: SLICEC.K1.INIT 1101110011111100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R15C39:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 H01E0001\narc: H00R0000 H02E0401\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0501 V01N0101\narc: V00B0100 V02N0301\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02N0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A1 W1_H02E0701\narc: A3 H02E0501\narc: A5 W1_H02E0701\narc: A6 V00T0100\narc: B1 S1_V02N0101\narc: B2 H01W0100\narc: B3 V02N0101\narc: B5 H00R0000\narc: B6 V02S0701\narc: C1 S1_V02N0601\narc: C2 V02S0601\narc: C3 V02S0401\narc: C5 V02N0001\narc: C6 V00T0000\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D2 S1_V02N0001\narc: D3 V02S0201\narc: D5 V02N0601\narc: D6 H00R0100\narc: E1_H01E0001 F6\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00R0100 F5\narc: H01W0100 Q3\narc: LSR1 H02E0301\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F1\narc: N3_V06N0003 Q3\narc: S1_V02S0001 F2\narc: W3_H06W0003 Q3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1010111110001111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001000000000000\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 0010101011111111\nword: SLICED.K0.INIT 0101111101001100\nword: SLICED.K1.INIT 1111111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R15C3:PLC2\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V02S0701\narc: H00R0000 V02N0601\narc: H00R0100 H02E0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0501 H02W0501\narc: S1_V02S0201 V01N0001\narc: S1_V02S0701 V01N0101\narc: V00B0000 V02N0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02S0601\narc: V00T0100 N1_V02S0701\narc: W1_H02W0501 E3_H06W0303\narc: A7 V02N0101\narc: B7 V02S0701\narc: C7 V00T0000\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D7 H01W0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q0\narc: E1_H02E0501 F7\narc: E3_H06E0003 Q0\narc: E3_H06E0203 Q4\narc: F7 F7_SLICE\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 H02W0601\narc: M2 V00T0100\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000110010101111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R15C40:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0103 S3_V06N0103\narc: H00R0000 H02E0401\narc: H00R0100 H02E0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0501 N1_V01S0100\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H06W0303\narc: S3_V06S0103 H06W0103\narc: V00B0100 V02N0101\narc: V00T0000 V02S0401\narc: W1_H02W0401 V06S0203\narc: N1_V02N0701 W3_H06E0203\narc: S3_V06S0303 W3_H06E0303\narc: W3_H06W0203 V06S0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: A0 H00R0000\narc: A1 H00R0000\narc: A6 H00R0000\narc: A7 H00R0000\narc: B0 V02N0101\narc: B1 V02N0101\narc: B6 V00B0100\narc: B7 V00B0100\narc: C0 H02W0401\narc: C1 H02W0401\narc: C6 H02W0401\narc: C7 H02W0401\narc: D0 H02E0201\narc: D1 H02E0201\narc: D6 H02E0201\narc: D7 H02E0201\narc: E1_H02E0101 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 W1_H02E0001\narc: M2 V00T0000\narc: M3 H00R0100\narc: M4 V00T0000\narc: M5 W1_H02E0001\narc: M6 V00T0000\nword: SLICEA.K0.INIT 0000001000000001\nword: SLICEA.K1.INIT 0010000000010000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000001000000001\nword: SLICED.K1.INIT 0010000000010000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R15C41:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0103 N1_V01S0100\narc: H00L0000 V02N0001\narc: H00L0100 S1_V02N0101\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 V01N0001\narc: S1_V02S0501 H02W0501\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0303 H06E0303\narc: V00B0000 S1_V02N0001\narc: V00T0000 H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0601 V06N0303\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0201 W3_H06E0103\narc: N3_V06N0003 W3_H06E0003\narc: S1_V02S0101 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: A1 W1_H02E0701\narc: A2 W1_H02E0701\narc: A5 V00T0000\narc: B1 H02E0301\narc: B2 H02E0301\narc: B5 V02N0701\narc: B7 H02W0101\narc: C1 H00R0100\narc: C2 H00R0100\narc: C5 H02E0401\narc: C7 H02W0401\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 V00T0100\narc: D5 V02N0401\narc: D7 H02E0001\narc: E1_H01E0101 F1\narc: E3_H06E0203 Q7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: M0 V00B0000\narc: M1 H00L0000\narc: M2 V00B0000\narc: MUXCLK3 CLK0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000101000001000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000001000000001\nword: SLICEB.K0.INIT 0000001000000001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R15C42:PLC2\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 H01E0101\narc: E1_H02E0701 S3_V06N0203\narc: H00L0000 H02W0001\narc: H00L0100 V02S0101\narc: H00R0100 W1_H02E0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0203 S1_V02N0401\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 W1_H02E0701\narc: V00T0000 H02W0001\narc: V00T0100 V02N0501\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0501 V01N0101\narc: E1_H02E0301 W3_H06E0003\narc: S3_V06S0103 W3_H06E0103\narc: S3_V06S0303 W3_H06E0303\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A1 E1_H02W0501\narc: A2 E1_H02W0501\narc: A5 H02W0501\narc: B1 V00T0000\narc: B2 H00L0000\narc: B4 H02E0301\narc: B5 H02W0101\narc: B7 H02W0301\narc: C1 N1_V01N0001\narc: C2 N1_V01N0001\narc: C4 V02S0001\narc: C5 H02W0401\narc: C7 H02W0601\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 V00T0100\narc: D4 V02N0401\narc: D5 V00B0000\narc: D7 H00R0100\narc: E1_H01E0001 F1\narc: E3_H06E0203 F4\narc: E3_H06E0303 F5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: M0 H02E0601\narc: M1 H00L0100\narc: M2 H02E0601\narc: MUXCLK3 CLK0\narc: S3_V06S0203 Q7\narc: V00B0000 F4\narc: V01S0100 Q7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110000110000\nword: SLICEC.K0.INIT 0000110000111111\nword: SLICEC.K1.INIT 0000000100000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010001001010001\nword: SLICEB.K0.INIT 1010001001010001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R15C43:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0003 V06S0003\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 V06S0303\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02N0101\narc: H00R0100 H02W0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 W1_H02E0501\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 H02W0001\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 H06E0203\narc: V00B0000 V02N0001\narc: V00T0000 W1_H02E0201\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 E1_H01W0100\narc: N1_V02N0101 W3_H06E0103\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A3 V00B0000\narc: B3 H00R0100\narc: B4 E1_H02W0101\narc: B6 E1_H02W0101\narc: C3 V02S0401\narc: C4 H02W0601\narc: C6 V01N0101\narc: CE0 H02W0101\narc: CLK0 G_HPBX0000\narc: D2 H02W0201\narc: D3 H02W0201\narc: D4 V02S0601\narc: D5 H00L0100\narc: D6 N1_V02S0601\narc: D7 V01N0001\narc: E1_H01E0001 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F1\narc: H01W0100 F1\narc: M0 V00T0000\narc: M1 H00L0000\narc: M2 V00T0000\narc: M4 W1_H02E0401\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: S1_V02S0301 Q1\narc: S3_V06S0303 F6\narc: V01S0000 Q1\narc: W1_H02W0601 F4\nword: SLICEC.K0.INIT 1100111100000011\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1100111100000011\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0010111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R15C44:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 S3_V06N0003\narc: H00L0100 S1_V02N0101\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 E1_H01W0000\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0201 H01E0001\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0001\narc: V00B0100 H02E0501\narc: V00T0000 S1_V02N0601\narc: V00T0100 E1_H02W0301\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0201 W3_H06E0103\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0103 N3_V06S0103\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0203 E3_H06W0103\narc: A3 V00B0000\narc: B3 V02S0301\narc: B6 V02N0701\narc: C3 H00R0100\narc: C6 V00T0000\narc: CE0 V02N0201\narc: CE2 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D2 V02S0001\narc: D3 E1_H02W0201\narc: D6 V02N0601\narc: D7 N1_V02S0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q4\narc: M0 V00B0100\narc: M1 H00L0100\narc: M2 V00B0100\narc: M4 E1_H02W0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: S1_V02S0101 Q1\narc: S3_V06S0203 Q4\narc: V01S0000 Q1\narc: W1_H02W0301 F1\narc: W1_H02W0601 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0011001100001111\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000100011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R15C45:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 H01E0101\narc: E3_H06E0103 H01E0101\narc: H00L0000 H02E0201\narc: H00R0000 H02E0401\narc: H00R0100 S1_V02N0701\narc: H01W0100 E3_H06W0303\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H01E0001\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 S3_V06N0203\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02E0501\narc: V00T0100 H02E0101\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 S3_V06N0203\narc: W1_H02W0001 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A1 E1_H02W0701\narc: B1 E1_H02W0101\narc: C1 W1_H02E0401\narc: CE0 V02S0201\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q1\narc: M0 V00B0100\narc: M1 H00L0000\narc: M2 V00B0100\narc: M4 V00B0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1011000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R15C46:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 V06S0203\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 V01N0001\narc: H00L0000 H02E0201\narc: H00L0100 H02W0301\narc: H00R0100 E1_H02W0701\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 H06E0303\narc: N3_V06N0003 H06W0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 H06E0103\narc: S1_V02S0501 V01N0101\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 N1_V02S0001\narc: V00B0100 E1_H02W0501\narc: V00T0000 W1_H02E0001\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 V02S0701\narc: E1_H02E0101 W3_H06E0103\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A6 H02E0701\narc: B1 V00B0000\narc: B6 V00B0100\narc: B7 H02E0301\narc: C1 W1_H02E0601\narc: C6 V00T0100\narc: C7 V00T0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D6 H00L0100\narc: D7 H00L0100\narc: E1_H01E0001 F6\narc: E1_H01E0101 F1\narc: E3_H06E0203 Q4\narc: F1 F1_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q2\narc: M2 H02E0601\narc: M4 V00T0000\narc: M6 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q6\narc: N1_V02N0001 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111110000000000\nword: SLICED.K0.INIT 1111111011110000\nword: SLICED.K1.INIT 1111110011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R15C47:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 W1_H02E0201\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02W0601\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H02W0401\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0401 H02E0401\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0303 N1_V02S0601\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02W0001\narc: V00T0100 S1_V02N0701\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 H01E0101\narc: S1_V02S0601 W3_H06E0303\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: A1 V01N0101\narc: A2 N1_V02S0501\narc: A3 V00T0000\narc: B1 H02W0101\narc: B2 H02W0101\narc: B3 H01W0100\narc: B7 V01S0000\narc: C1 F4\narc: C2 F4\narc: C3 N1_V01N0001\narc: C4 V00T0100\narc: C5 F4\narc: C6 W1_H02E0401\narc: C7 V00B0100\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D2 H00R0000\narc: D3 H02E0201\narc: D4 H00L0100\narc: D5 E1_H01W0100\narc: D6 H00R0100\narc: D7 E1_H01W0100\narc: E1_H01E0001 F4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 F7\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F2\narc: N1_V01N0101 Q5\narc: N1_V02N0501 Q5\narc: N1_V02N0601 Q4\narc: N3_V06N0203 Q7\narc: V01S0000 F6\narc: V01S0100 Q7\narc: W1_H02W0101 F3\narc: W3_H06W0303 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001110\nword: SLICED.K0.INIT 1111111111110000\nword: SLICED.K1.INIT 0000000011001111\nword: SLICEC.K0.INIT 0000000000001111\nword: SLICEC.K1.INIT 0000000000001111\nword: SLICEB.K0.INIT 0000000000001110\nword: SLICEB.K1.INIT 0000000000001011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R15C48:PLC2\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 E1_H02W0001\narc: H00R0100 S1_V02N0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 E1_H01W0000\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02W0401\narc: V00B0100 W1_H02E0701\narc: V00T0000 V02S0601\narc: V01S0000 S3_V06N0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V06S0003\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0301 W3_H06E0003\narc: H01W0100 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0401 W3_H06E0203\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0103 N3_V06S0103\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A2 S1_V02N0501\narc: B2 F3\narc: B3 H00L0000\narc: C2 H02E0401\narc: C3 V02N0601\narc: CE0 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 W1_H02E0001\narc: D3 S1_V02N0001\narc: E1_H01E0001 Q6\narc: E1_H01E0101 F3\narc: E1_H02E0401 Q4\narc: E3_H06E0003 Q0\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0000 Q6\narc: M0 V00B0000\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: N1_V02N0301 F3\narc: N1_V02N0401 Q4\narc: W1_H02W0201 F2\narc: W1_H02W0301 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0101111100010011\nword: SLICEB.K1.INIT 0000000000001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R15C49:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0601 V06S0303\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0203 H01E0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02W0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0301 H02W0301\narc: N1_V02N0601 S1_V02N0301\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 H01E0101\narc: V00B0000 S1_V02N0001\narc: V00B0100 S1_V02N0101\narc: V00T0100 S1_V02N0501\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 S3_V06N0203\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0701 W3_H06E0203\narc: W3_H06W0303 V06S0303\narc: E3_H06E0003 W3_H06E0003\narc: B2 H00R0100\narc: B3 H01W0100\narc: C2 N1_V02S0401\narc: C3 H02W0401\narc: CE0 H00L0100\narc: CE1 H00R0000\narc: CE2 H02W0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D2 V02N0001\narc: D3 H02W0201\narc: E1_H01E0001 F3\narc: E1_H02E0001 Q0\narc: E3_H06E0303 Q6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q2\narc: M0 V00B0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q6\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R15C4:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V02N0601\narc: E3_H06E0303 H01E0101\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02E0501\narc: N1_V02N0501 W1_H02E0501\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: V00T0000 V02S0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 V06N0303\narc: W1_H02W0601 H01E0001\narc: A4 H02E0701\narc: B4 V02S0701\narc: B5 V00B0100\narc: C4 H02W0601\narc: C5 E1_H02W0401\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 H01W0000\narc: D5 H00R0100\narc: E1_H01E0001 F4\narc: E1_H01E0101 Q0\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F5\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00T0000\narc: M2 V00B0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q6\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1101000000000000\nword: SLICEC.K1.INIT 1100001100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R15C50:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0003 H01E0001\narc: E3_H06E0203 W1_H02E0401\narc: H00R0100 W1_H02E0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0201\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0201 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0103 E1_H02W0101\narc: E3_H06E0103 W3_H06E0003\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: H01W0000 Q2\narc: LSR1 V00B0000\narc: M2 H02W0601\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: W1_H02W0001 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R15C51:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V06N0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V02N0701\narc: H00L0000 W1_H02E0201\narc: H00R0000 E1_H02W0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 V01N0001\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02N0101\narc: V00T0100 V02S0501\narc: W1_H02W0601 V02N0601\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: S1_V02S0101 W3_H06E0103\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: B2 V02S0301\narc: B3 H01W0100\narc: B5 H00L0000\narc: C2 N1_V02S0401\narc: C3 H02W0601\narc: C5 V00T0100\narc: CE0 H00R0100\narc: CE1 E1_H02W0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D2 V02N0001\narc: D3 H00R0000\narc: D5 S1_V02N0401\narc: E1_H01E0101 Q6\narc: E3_H06E0103 Q2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q2\narc: M0 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 F5\narc: N3_V06N0103 Q2\narc: V01S0100 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R15C52:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 H02W0201\narc: H00L0100 E1_H02W0301\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02E0601\narc: V00T0000 H02E0001\narc: V00T0100 E1_H02W0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 S3_V06N0203\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0701 W3_H06E0203\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A1 H00L0100\narc: A2 H00L0100\narc: A5 V00T0100\narc: A6 E1_H01W0000\narc: B0 H01W0100\narc: B1 S1_V02N0101\narc: B2 E1_H02W0101\narc: B4 V00B0100\narc: B5 V02N0701\narc: B6 V00T0000\narc: B7 H02E0301\narc: C0 V02S0601\narc: C1 H00L0000\narc: C2 S1_V02N0401\narc: C4 W1_H02E0601\narc: C5 V02N0201\narc: C6 V02N0001\narc: C7 E1_H02W0401\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 H00R0000\narc: D2 W1_H02E0201\narc: D4 H00R0100\narc: D5 V00B0000\narc: D6 V02N0601\narc: D7 H02W0001\narc: E1_H01E0101 F6\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q1\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M2 H02W0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 F7\narc: N1_V02N0701 F7\narc: V00B0100 Q5\narc: V01S0000 F7\narc: W3_H06W0003 F0\narc: W3_H06W0203 F4\narc: W3_H06W0303 Q5\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111111111111000\nword: SLICEC.K0.INIT 1100111111000000\nword: SLICEC.K1.INIT 0011101110111011\nword: SLICED.K0.INIT 1110111001100000\nword: SLICED.K1.INIT 0000000011000000\nword: SLICEB.K0.INIT 1010000011101100\nword: SLICEB.K1.INIT 1111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R15C53:PLC2\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 S3_V06N0303\narc: E3_H06E0203 H01E0001\narc: H00L0000 W1_H02E0001\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 W1_H02E0501\narc: V00T0000 W1_H02E0001\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V06N0003\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V01N0101\narc: W1_H02W0601 V02S0601\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0201 W3_H06E0103\narc: S1_V02S0101 W3_H06E0103\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: A0 H00R0000\narc: A4 V00B0000\narc: A5 W1_H02E0701\narc: B0 V00T0000\narc: B4 H00L0000\narc: B5 H01E0101\narc: C0 H02W0401\narc: C1 E1_H02W0401\narc: C2 E1_H02W0401\narc: C3 E1_H02W0401\narc: C4 V02N0201\narc: C5 V02S0001\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 V02N0001\narc: D2 V00B0100\narc: D3 W1_H02E0001\narc: D4 H00R0100\narc: D5 F0\narc: E1_H01E0001 F1\narc: E1_H01E0101 F2\narc: E1_H02E0601 Q6\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0000 Q6\narc: H00R0100 F5\narc: H01W0000 Q6\narc: M6 W1_H02E0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 F3\narc: V00B0000 Q6\narc: V01S0100 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1000000011111111\nword: SLICEC.K1.INIT 0000000000010011\nword: SLICEA.K0.INIT 0000110000001010\nword: SLICEA.K1.INIT 0000000000001111\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000111111110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R15C54:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0701 V02S0701\narc: E3_H06E0103 N1_V01S0100\narc: H00L0000 V02S0201\narc: H00L0100 E1_H02W0101\narc: H00R0000 W1_H02E0601\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 H01E0001\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0201 H06W0103\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 V02S0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 V06S0203\narc: E1_H02E0001 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\narc: A1 H02W0701\narc: A3 V00B0000\narc: B0 H01W0100\narc: B1 H02W0301\narc: B2 H00L0000\narc: B3 H00R0100\narc: C0 H02E0401\narc: C1 V02N0401\narc: C2 H02W0601\narc: C3 H00L0100\narc: C4 H02W0401\narc: C5 H02W0401\narc: C6 H02W0401\narc: C7 H02W0401\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V02N0201\narc: D2 H00R0000\narc: D3 H02W0001\narc: D4 W1_H02E0201\narc: D5 H02E0201\narc: D6 E1_H01W0100\narc: D7 V02N0601\narc: E1_H01E0001 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q3\narc: H01W0100 Q1\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 Q3\narc: N1_V01N0101 F6\narc: V01S0000 Q1\narc: V01S0100 F7\narc: W1_H02W0001 F0\narc: W1_H02W0501 F5\narc: W3_H06W0003 Q3\narc: W3_H06W0103 F2\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111111111111000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1111111111111000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R15C55:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 E1_H01W0100\narc: H00R0000 V02N0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H01E0001\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0401 H06E0203\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V06N0003\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V02S0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0601 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: B5 H00R0000\narc: C0 E1_H01W0000\narc: C1 E1_H01W0000\narc: C2 E1_H01W0000\narc: C3 E1_H01W0000\narc: C5 S1_V02N0201\narc: C6 H02W0401\narc: C7 H02W0401\narc: D0 E1_H02W0001\narc: D1 H02W0001\narc: D2 H02E0001\narc: D3 V00B0100\narc: D5 H00R0100\narc: D6 V00B0000\narc: D7 H02E0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V01N0001 F5\narc: N1_V01N0101 F6\narc: N1_V02N0001 F2\narc: N1_V02N0101 F1\narc: N1_V02N0301 F3\narc: N1_V02N0701 F7\narc: S1_V02S0501 F5\narc: V01S0100 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011110000000000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000111111110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R15C56:PLC2\narc: E1_H02E0601 N1_V01S0000\narc: H00R0100 H02E0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 H06E0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 H02W0401\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0701 W3_H06E0203\narc: S1_V02S0001 W3_H06E0003\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0203 E1_H02W0401\narc: A0 E1_H01E0001\narc: A1 V01N0101\narc: A3 V01N0101\narc: B0 H02W0101\narc: B1 W1_H02E0301\narc: B3 S1_V02N0301\narc: C0 H02E0401\narc: C1 E1_H02W0601\narc: C3 H02E0601\narc: C4 E1_H01E0101\narc: C5 E1_H01E0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 E1_H02W0001\narc: D3 H02E0201\narc: D4 H00R0100\narc: D5 V00B0000\narc: E1_H01E0001 F2\narc: E1_H01E0101 Q6\narc: E1_H02E0501 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q6\narc: H01W0100 Q6\narc: M2 E1_H02W0601\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q0\narc: V00T0100 F1\narc: V01S0100 F4\narc: W1_H02W0401 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111111010101\nword: SLICEA.K1.INIT 0000110000001010\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 0110110100110111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R15C57:PLC2\narc: H00L0000 V02N0201\narc: H00L0100 H02W0301\narc: H00R0000 V02N0601\narc: H00R0100 V02N0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0701 H01E0101\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02E0701\narc: V00T0000 S1_V02N0401\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0701 S1_V02N0701\narc: S1_V02S0101 W3_H06E0103\narc: S1_V02S0501 W3_H06E0303\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0303 E1_H01W0100\narc: A2 W1_H02E0501\narc: A3 W1_H02E0501\narc: A6 H02W0501\narc: B0 F1\narc: B1 H00R0100\narc: B2 H00R0000\narc: B3 H00R0000\narc: B6 V00B0100\narc: B7 W1_H02E0301\narc: C0 N1_V01S0100\narc: C1 H00L0000\narc: C2 H00L0100\narc: C3 H00L0100\narc: C6 H02W0601\narc: C7 V02N0201\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 E1_H02W0201\narc: D2 N1_V01S0000\narc: D3 N1_V01S0000\narc: D6 H01W0000\narc: D7 F2\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: E1_H02E0101 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M2 V00T0000\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F7\narc: N1_V02N0101 F1\narc: N3_V06N0203 F7\narc: S1_V02S0701 F7\narc: V01S0000 F1\narc: V01S0100 F6\narc: W1_H02W0101 F1\narc: W3_H06W0003 Q0\narc: W3_H06W0103 F1\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1100000011111111\nword: SLICEA.K1.INIT 0000001100000000\nword: SLICED.K0.INIT 0000110000001010\nword: SLICED.K1.INIT 0000001100110000\nword: SLICEB.K0.INIT 0111000001111111\nword: SLICEB.K1.INIT 0000100011111000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R15C58:PLC2\narc: E1_H02E0201 S3_V06N0103\narc: H00L0000 E1_H02W0001\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 W1_H02E0501\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0203 N1_V02S0401\narc: V00B0000 V02N0201\narc: V00B0100 V02N0301\narc: V00T0000 V02N0401\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 N1_V02S0701\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0401 W3_H06E0203\narc: S1_V02S0701 W3_H06E0203\narc: S3_V06S0303 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: H01W0100 Q2\narc: M0 V00B0000\narc: M2 V00B0100\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q0\narc: V01S0000 Q2\narc: V01S0100 Q0\narc: W1_H02W0401 Q4\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R15C59:PLC2\narc: N1_V02N0201 H02E0201\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0601 N1_V02S0301\narc: H01W0000 W3_H06E0103\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: N3_V06N0103 W3_H06E0103\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\n\n.tile R15C5:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 V02S0301\narc: N1_V02N0401 H02E0401\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 V01N0101\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02N0201\narc: V00T0000 V02N0401\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 H01E0101\narc: A1 N1_V02S0501\narc: A2 E1_H02W0501\narc: A3 E1_H02W0501\narc: A4 F7\narc: A5 H02E0501\narc: A6 H02W0501\narc: A7 V02N0101\narc: B1 S1_V02N0101\narc: B2 S1_V02N0101\narc: B3 V02S0101\narc: B4 V00B0100\narc: B5 H00L0000\narc: B6 E1_H02W0301\narc: B7 E1_H02W0301\narc: C1 V02S0601\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 H02E0601\narc: C5 S1_V02N0001\narc: C6 W1_H02E0601\narc: C7 V00T0000\narc: D1 V02S0201\narc: D2 V02S0201\narc: D3 V02S0001\narc: D4 V00B0000\narc: D5 F0\narc: D6 V02N0401\narc: D7 E1_H02W0201\narc: E1_H02E0401 F4\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F2\narc: M0 V00T0100\narc: V00B0100 F5\narc: V00T0100 F3\narc: W1_H02W0601 F6\nword: SLICEB.K0.INIT 1111010100110001\nword: SLICEB.K1.INIT 1010111100100011\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 1000010000000000\nword: SLICED.K0.INIT 1111010100110001\nword: SLICED.K1.INIT 1000101001000101\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000110010101111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R15C60:PLC2\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0501 S1_V02N0501\n\n.tile R15C61:PLC2\narc: S3_V06S0303 H06E0303\n\n.tile R15C62:PLC2\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\n\n.tile R15C64:PLC2\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: S1_V02S0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\n\n.tile R15C67:PLC2\narc: S3_V06S0003 H06E0003\n\n.tile R15C69:PLC2\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\n\n.tile R15C6:PLC2\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 V02S0201\narc: H00R0000 V02S0601\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H02E0601\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 N1_V01S0100\narc: V00B0000 E1_H02W0401\narc: V00T0000 V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 E1_H02W0601\narc: A0 E1_H02W0501\narc: A2 H02W0701\narc: A3 V01N0101\narc: A4 S1_V02N0301\narc: A5 H02E0501\narc: A6 V02S0101\narc: A7 V00T0100\narc: B2 H00L0000\narc: B3 E1_H02W0101\narc: B4 H00R0000\narc: B5 V02S0501\narc: B6 V00T0000\narc: B7 V00B0000\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C70:PLC2\narc: S3_V06S0003 N3_V06S0003\narc: N1_V02N0501 W3_H06E0303\n\n.tile R15C7:PLC2\narc: E1_H02E0501 V02N0501\narc: H00L0000 V02S0201\narc: H00R0000 S1_V02N0401\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 H02E0201\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 E1_H02W0401\narc: V00T0000 V02N0401\narc: V00T0100 N1_V02S0701\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V06S0203\narc: A0 H02E0701\narc: A1 H00R0000\narc: A2 V02N0701\narc: A3 V00T0000\narc: A4 V00T0100\narc: A5 H02E0501\narc: A6 W1_H02E0701\narc: A7 V02N0101\narc: B0 H02E0301\narc: B1 N1_V02S0301\narc: B2 H00L0000\narc: B3 V02S0301\narc: B4 E1_H02W0101\narc: B5 V02S0501\narc: B6 V00B0000\narc: B7 S1_V02N0701\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C8:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0701 V06S0203\narc: E3_H06E0303 V06S0303\narc: H00L0000 H02W0201\narc: H00L0100 V02N0301\narc: H00R0000 S1_V02N0601\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02N0201\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02W0301\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V06S0303\narc: E1_H02E0501 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: A0 V02N0701\narc: A1 H00R0000\narc: A2 H02W0701\narc: A3 H00L0100\narc: A4 V02N0101\narc: A5 V00B0000\narc: A6 V00T0100\narc: A7 S1_V02N0101\narc: B0 V00T0000\narc: B1 V02S0301\narc: B2 N1_V02S0301\narc: B3 V02S0101\narc: B4 H00L0000\narc: B5 V02S0701\narc: B6 N1_V02S0701\narc: B7 E1_H02W0101\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R15C9:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 V01N0101\narc: H00L0000 V02N0201\narc: H00R0000 V02S0601\narc: N1_V02N0501 H02W0501\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H02W0001\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02S0001\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02E0201\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 S1_V02N0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0301 W3_H06E0003\narc: W3_H06W0103 N1_V01S0100\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0303 E3_H06W0303\narc: A0 H00L0000\narc: A1 V02N0501\narc: A2 N1_V02S0701\narc: A3 H02E0501\narc: A4 S1_V02N0101\narc: A5 V00T0000\narc: A6 W1_H02E0501\narc: A7 H02E0701\narc: B0 V00B0000\narc: B1 N1_V02S0301\narc: B2 E1_H02W0101\narc: B3 V02S0301\narc: B4 H00R0000\narc: B5 V02S0701\narc: B6 V00B0100\narc: B7 V02S0501\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R16C10:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 N3_V06S0303\narc: H00L0000 H02E0001\narc: H00R0000 S1_V02N0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02S0301\narc: V00T0100 H02E0301\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 N1_V02S0701\narc: E3_H06E0203 W3_H06E0203\narc: A3 V00B0000\narc: A5 H02E0701\narc: B3 H00R0100\narc: B5 H00L0000\narc: C3 E1_H02W0601\narc: C5 H02E0601\narc: CE0 H00R0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D3 W1_H02E0001\narc: D5 V02N0401\narc: E1_H02E0101 F3\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: H01W0100 Q6\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M0 V00T0100\narc: M4 H02W0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: N1_V02N0401 F4\narc: S1_V02S0201 Q0\narc: W1_H02W0601 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1001000000001001\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R16C11:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0301 S1_V02N0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 V02S0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N1_V02S0301\narc: V00B0000 W1_H02E0401\narc: V00B0100 N1_V02S0101\narc: V00T0100 H02E0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N1_V02S0501\narc: A2 V02N0501\narc: A3 V00T0000\narc: A5 H02E0501\narc: A6 N1_V02S0301\narc: A7 E1_H02W0501\narc: B2 V02S0301\narc: B3 H00R0000\narc: B5 N1_V02S0501\narc: B6 S1_V02N0701\narc: B7 V00B0100\narc: C2 N1_V01N0001\narc: C3 H02W0401\narc: C5 V02S0001\narc: C6 E1_H01E0101\narc: C7 V02N0201\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 E1_H02W0201\narc: D3 N1_V02S0201\narc: D5 H02W0001\narc: D6 V00B0000\narc: D7 E1_H02W0001\narc: E1_H01E0101 F7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: LSR1 H02W0301\narc: M0 E1_H02W0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0001 F3\narc: N1_V01N0101 Q0\narc: V00T0000 Q0\narc: W3_H06W0103 F2\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1001000000000000\nword: SLICED.K1.INIT 1001000000000000\nword: SLICEB.K0.INIT 1001000000000000\nword: SLICEB.K1.INIT 1000001001000001\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1001000000001001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R16C12:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 N3_V06S0303\narc: H00L0000 N1_V02S0201\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02N0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 W1_H02E0601\narc: V00B0100 V02S0101\narc: V00T0100 H02W0301\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V02N0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 N1_V02S0601\narc: W3_H06W0103 N3_V06S0103\narc: W3_H06W0303 N3_V06S0303\narc: A0 E1_H02W0501\narc: A1 H00L0100\narc: A7 N1_V01N0101\narc: B0 N1_V02S0301\narc: B1 H00R0100\narc: B7 H02E0301\narc: C0 H00L0000\narc: C1 V02N0401\narc: C7 E1_H02W0401\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 W1_H02E0001\narc: D7 V00B0000\narc: E1_H01E0001 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F7 F7_SLICE\narc: LSR0 W1_H02E0301\narc: LSR1 W1_H02E0301\narc: M2 V00T0100\narc: M4 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q4\narc: N3_V06N0203 F7\narc: S1_V02S0201 Q2\narc: V01S0000 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 1000010010100101\nword: SLICEA.K1.INIT 1100010000110001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R16C13:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 N1_V01S0000\narc: H00L0100 H02E0101\narc: H00R0100 S1_V02N0701\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02E0501\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 E1_H02W0301\narc: W3_H06W0303 N3_V06S0303\narc: W3_H06W0203 E3_H06W0203\narc: A5 V00T0000\narc: A7 H00L0000\narc: B5 V00B0100\narc: B7 V02N0701\narc: C5 H02E0601\narc: C7 V02S0001\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D5 V02N0401\narc: D7 H00L0100\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: LSR0 V00B0000\narc: M0 H02W0601\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q0\narc: N3_V06N0303 F5\narc: V00T0000 Q2\narc: W1_H02W0701 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000010000100001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R16C14:PLC2\narc: E1_H02E0101 V02N0101\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02S0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 V01N0101\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 V02N0001\narc: V00B0100 S1_V02N0101\narc: V00T0100 S1_V02N0501\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V01N0001\narc: W3_H06W0103 N3_V06S0103\narc: E3_H06E0203 W3_H06E0203\narc: A3 V00T0000\narc: A7 E1_H02W0501\narc: B3 H00R0100\narc: B7 S1_V02N0701\narc: C3 H00L0100\narc: C7 H02E0601\narc: CE0 H00R0000\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: D3 E1_H02W0001\narc: D7 V02N0401\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: H01W0100 Q4\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00B0100\narc: M4 E1_H02W0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q0\narc: N1_V02N0401 F6\narc: V00T0000 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1001000000001001\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R16C15:PLC2\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 W1_H02E0501\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 H02W0601\narc: V00B0100 H02W0701\narc: V00T0000 N1_V02S0401\narc: V00T0100 N1_V02S0701\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 W3_H06E0303\narc: CE0 W1_H02E0101\narc: CE1 H02E0101\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q4\narc: H01W0000 Q2\narc: H01W0100 Q6\narc: LSR1 V00B0000\narc: M0 V00T0000\narc: M2 V00B0100\narc: M4 V00T0100\narc: M6 N1_V01N0101\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R16C16:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V02N0201\narc: E1_H02E0501 S1_V02N0501\narc: E3_H06E0303 N3_V06S0303\narc: H00L0100 V02S0301\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 H02E0601\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02N0401\narc: V00T0100 V02S0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V06S0203\narc: N1_V02N0701 W3_H06E0203\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: H01W0000 Q6\narc: H01W0100 Q0\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q4\narc: W3_H06W0103 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R16C17:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 E1_H01W0000\narc: H00R0100 H02W0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 H02W0701\narc: S1_V02S0201 N1_V02S0701\narc: V00B0000 V02S0001\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02W0201\narc: W1_H02W0001 N3_V06S0003\narc: A4 V00T0100\narc: B1 V00B0000\narc: B4 H00L0000\narc: B7 S1_V02N0701\narc: C1 H00L0100\narc: C3 N1_V01N0001\narc: C4 V00B0100\narc: C7 F4\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 Q0\narc: D1 H02E0001\narc: D3 H02E0001\narc: D4 V02N0601\narc: D7 H00R0100\narc: E1_H01E0101 Q3\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00L0100 Q1\narc: H01W0000 Q0\narc: H01W0100 F7\narc: LSR0 E1_H02W0301\narc: LSR1 V00T0000\narc: M4 E1_H01E0101\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q3\narc: N3_V06N0203 F4\narc: V00T0100 Q1\narc: V01S0000 Q1\narc: V01S0100 Q7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000011\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0011110011110000\nword: SLICEC.K0.INIT 0001000000010001\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R16C18:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 W1_H02E0201\narc: H00R0100 H02W0701\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 N3_V06S0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0501 E3_H06W0303\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02W0701\narc: V00T0000 V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 E3_H06W0203\narc: A1 E1_H01E0001\narc: A5 V00T0100\narc: B1 H02E0301\narc: B5 S1_V02N0501\narc: C1 V02S0401\narc: C5 V00T0000\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D5 H00R0100\narc: E1_H01E0001 Q1\narc: E3_H06E0103 Q1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: H00R0000 F4\narc: H01W0000 Q1\narc: LSR1 V00B0000\narc: M0 V00T0100\narc: M1 H00L0000\narc: M2 V00T0100\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N3_V06N0103 Q1\narc: S1_V02S0301 Q1\narc: S3_V06S0103 Q1\narc: W1_H02W0101 Q1\narc: W3_H06W0103 Q1\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0101010101010001\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 0101010101011101\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R16C19:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 S1_V02N0301\narc: H00R0000 N1_V02S0401\narc: H00R0100 V02N0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H06W0003\narc: S1_V02S0201 H02W0201\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 H06W0003\narc: W1_H02W0301 V02N0301\narc: W1_H02W0701 H01E0101\narc: B3 V02N0101\narc: C3 H00R0100\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: E1_H01E0001 F7\narc: E3_H06E0003 F3\narc: E3_H06E0203 Q7\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: LSR0 H02W0301\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N3_V06N0203 F7\narc: S3_V06S0203 F7\narc: W1_H02W0501 Q7\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0011000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R16C20:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 H01E0001\narc: E3_H06E0103 W1_H02E0101\narc: H00R0000 V02N0401\narc: N1_V01N0001 N3_V06S0003\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 E3_H06W0003\narc: V00T0100 V02N0701\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 S1_V02N0301\narc: E3_H06E0203 W3_H06E0203\narc: A0 E1_H01E0001\narc: A1 E1_H01E0001\narc: A2 E1_H01E0001\narc: A6 V02N0101\narc: A7 V02N0101\narc: B0 H01W0100\narc: B1 H01W0100\narc: B2 H00L0000\narc: B3 H00R0100\narc: B6 H02W0301\narc: B7 H02W0301\narc: C0 V02N0401\narc: C1 V02N0401\narc: C2 V02N0401\narc: C3 H00L0000\narc: C6 V02N0001\narc: C7 V02N0001\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 V00T0100\narc: D3 H00R0000\narc: D5 H00R0100\narc: D6 H02E0201\narc: D7 H02E0201\narc: E1_H01E0001 Q5\narc: E1_H01E0101 F6\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q2\narc: H00R0100 Q5\narc: H01W0000 Q5\narc: H01W0100 Q0\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q0\narc: S1_V02S0001 Q0\narc: S1_V02S0301 F3\narc: S1_V02S0601 F6\narc: V00T0000 Q2\nword: SLICEB.K0.INIT 0110110011001001\nword: SLICEB.K1.INIT 0000000000000011\nword: SLICEA.K0.INIT 1100110011001001\nword: SLICEA.K1.INIT 0110110011001100\nword: SLICED.K0.INIT 1100010001000100\nword: SLICED.K1.INIT 0011101110111011\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R16C21:PLC2\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 V02S0201\narc: H00L0100 V02N0301\narc: H00R0000 V02S0401\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 H02W0701\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 H02E0301\narc: S3_V06S0003 N3_V06S0303\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02E0501\narc: V00T0000 V02S0601\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 H01E0101\narc: W1_H02W0301 V02N0301\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A0 E1_H01E0001\narc: A5 V02N0101\narc: A6 F7\narc: B0 S1_V02N0101\narc: B1 H01W0100\narc: B5 E1_H02W0101\narc: B6 F1\narc: B7 V01S0000\narc: C0 N1_V01S0100\narc: C1 H00L0000\narc: C4 Q4\narc: C5 V02N0201\narc: C6 V00B0100\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CE1 H02W0101\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 N1_V01S0000\narc: D4 W1_H02E0001\narc: D5 H02W0201\narc: D6 H00L0100\narc: D7 H02E0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q2\narc: E1_H02E0201 Q0\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0000 Q4\narc: H01W0100 Q0\narc: LSR0 W1_H02E0301\narc: LSR1 W1_H02E0301\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q0\narc: N1_V02N0201 Q0\narc: S1_V02S0501 F5\narc: S1_V02S0601 Q4\narc: S1_V02S0701 F7\narc: S3_V06S0203 Q4\narc: V01S0000 Q0\narc: V01S0100 F1\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0001000000000000\nword: SLICED.K1.INIT 0000001100000000\nword: SLICEA.K0.INIT 1111101010111010\nword: SLICEA.K1.INIT 0000001100001100\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 1100010001000100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R16C22:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 W1_H02E0601\narc: H00L0100 V02S0101\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H01E0001\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0701 V01N0101\narc: S3_V06S0203 H01E0001\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 V02N0601\narc: V00T0100 V02N0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0701 N1_V01S0100\narc: A4 V00B0000\narc: A5 V00B0000\narc: A6 H00L0000\narc: A7 V02N0101\narc: B4 H02W0301\narc: B5 H02W0301\narc: B6 H01E0101\narc: B7 V00T0000\narc: C0 N1_V01N0001\narc: C1 H00R0100\narc: C4 H02W0601\narc: C5 H02W0601\narc: C6 V00B0100\narc: C7 E1_H02W0601\narc: CE1 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 S1_V02N0001\narc: D4 H00L0100\narc: D5 H00L0100\narc: D6 V02N0601\narc: D7 S1_V02N0601\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: LSR1 H02E0301\narc: M2 H02E0601\narc: M4 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F1\narc: N3_V06N0103 F1\narc: S1_V02S0401 F6\narc: S1_V02S0601 F4\narc: S3_V06S0003 F0\narc: W3_H06W0003 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1000001001000001\nword: SLICED.K1.INIT 1100101000000000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEC.K0.INIT 1100010001000100\nword: SLICEC.K1.INIT 0011101110111011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R16C23:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 E1_H02W0101\narc: H00R0000 N1_V02S0401\narc: H00R0100 V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0301 H06W0003\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 H06W0303\narc: S3_V06S0203 H06E0203\narc: V00B0000 S1_V02N0201\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V01N0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 V02N0601\narc: E1_H02E0401 W3_H06E0203\narc: W3_H06W0103 E1_H02W0201\narc: A3 H00L0100\narc: B3 H02E0101\narc: C3 E1_H01W0000\narc: D3 V00T0100\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M3 H00R0100\narc: M4 V00B0000\narc: M5 H00R0000\narc: M6 V00B0000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R16C24:PLC2\narc: E1_H02E0201 V01N0001\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 W1_H02E0601\narc: H00L0000 H02E0201\narc: H00L0100 V02S0101\narc: H00R0100 H02E0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0701 H06E0203\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H02E0401\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 H02W0401\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02S0401\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0601 E1_H02W0301\narc: E1_H02E0101 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: A1 H00L0100\narc: A5 V02S0101\narc: A6 V00T0100\narc: A7 H02W0701\narc: B1 H01W0100\narc: B5 H00R0000\narc: B6 V00B0000\narc: B7 V02S0501\narc: C1 H00L0000\narc: C4 V02N0001\narc: C5 V02N0201\narc: C6 H02W0601\narc: C7 N1_V02S0201\narc: CE1 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0201\narc: D4 V02S0601\narc: D5 H00R0100\narc: D6 V02N0401\narc: D7 E1_H02W0001\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q2\narc: E1_H02E0001 F0\narc: E3_H06E0203 F7\narc: E3_H06E0303 F5\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H01W0000 F4\narc: H01W0100 F4\narc: LSR0 E1_H02W0501\narc: M0 V00T0000\narc: M2 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 F5\narc: N3_V06N0203 F7\narc: N3_V06N0303 F5\narc: S1_V02S0001 Q2\narc: V01S0000 F7\narc: V01S0100 F0\narc: W3_H06W0203 F7\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 0000000000010000\nword: SLICED.K1.INIT 0000010000001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111111111111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R16C25:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 H01E0101\narc: H00R0000 S1_V02N0601\narc: H00R0100 V02N0501\narc: N1_V02N0301 S1_V02N0301\narc: S1_V02S0001 N1_V01S0000\narc: V00B0000 H02W0401\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 H01E0001\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 N1_V02S0701\narc: E1_H01E0001 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: A0 H02W0701\narc: B0 V00T0000\narc: B2 V02S0101\narc: B3 Q3\narc: B4 V01S0000\narc: B5 V01S0000\narc: B7 V00B0100\narc: C0 H02E0601\narc: C2 H00R0100\narc: C3 N1_V01N0001\narc: C4 V00T0100\narc: C5 V01N0101\narc: C7 V00T0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D2 N1_V01S0000\narc: D3 S1_V02N0201\narc: D4 V02S0401\narc: D5 V01N0001\narc: D6 V02S0601\narc: D7 V02S0401\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: H01W0000 Q3\narc: H01W0100 F7\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M0 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q3\narc: N1_V02N0201 F0\narc: S1_V02S0201 F2\narc: S1_V02S0401 Q6\narc: S1_V02S0601 F4\narc: V01S0000 Q5\narc: W1_H02W0501 Q5\nword: SLICEB.K0.INIT 1111001100110011\nword: SLICEB.K1.INIT 1100110011111100\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 1111110011001100\nword: SLICEC.K0.INIT 1111001100110011\nword: SLICEC.K1.INIT 1100111111001100\nword: SLICEA.K0.INIT 1000110010101111\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R16C26:PLC2\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V06S0203\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H06W0203\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: V00T0100 H02W0301\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 V02N0701\narc: N1_V02N0301 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0203 V06S0203\narc: E3_H06E0103 W3_H06E0003\narc: A0 H02E0701\narc: A3 V00B0000\narc: A4 H02E0501\narc: A5 H02E0501\narc: A7 E1_H01W0000\narc: B0 F1\narc: B1 V00B0000\narc: B2 F1\narc: B3 H01W0100\narc: B4 H00L0000\narc: B5 H00L0000\narc: B7 H02E0101\narc: C0 V02S0601\narc: C1 V02N0601\narc: C2 N1_V01N0001\narc: C3 H00L0000\narc: C4 Q4\narc: C5 E1_H01E0101\narc: C7 V02N0001\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0201\narc: D1 H02E0001\narc: D2 H02E0201\narc: D3 E1_H02W0001\narc: D4 V02N0401\narc: D5 V02N0401\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 Q4\narc: E1_H02E0001 Q2\narc: E1_H02E0301 F3\narc: E1_H02E0401 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q2\narc: H00R0000 F6\narc: H01W0000 Q2\narc: H01W0100 Q0\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F5\narc: S1_V02S0001 Q2\narc: S1_V02S0301 F1\narc: S1_V02S0401 Q4\narc: V00B0000 Q4\narc: V01S0000 Q0\narc: W1_H02W0101 F3\narc: W1_H02W0301 F3\narc: W3_H06W0003 F3\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0011001111110011\nword: SLICEB.K1.INIT 0100000000000000\nword: SLICEA.K0.INIT 1111001101110011\nword: SLICEA.K1.INIT 1111110011001111\nword: SLICEC.K0.INIT 0000000011100001\nword: SLICEC.K1.INIT 1110000100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111001100100010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R16C27:PLC2\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 H02E0001\narc: H00L0100 H02E0301\narc: H00R0000 V02S0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H02E0601\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0501 H02E0501\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 H02E0401\narc: V00T0000 H02E0001\narc: V00T0100 V02N0501\narc: W1_H02W0401 S1_V02N0401\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: A1 W1_H02E0501\narc: A5 V02N0301\narc: B1 V00B0000\narc: B3 E1_H02W0301\narc: B5 V02N0501\narc: B6 V00T0000\narc: B7 V00T0000\narc: C1 H00L0000\narc: C2 H00L0100\narc: C3 V02S0601\narc: C5 V02S0201\narc: C6 V02N0201\narc: C7 V02N0201\narc: D1 H00R0000\narc: D2 F0\narc: D3 V00B0100\narc: D5 V02N0601\narc: D6 H02W0001\narc: D7 H00R0100\narc: E1_H01E0001 F2\narc: E1_H01E0101 F0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F2\narc: M0 V00T0100\narc: M6 H02E0401\narc: N1_V01N0001 F0\narc: V00B0100 F5\narc: V01S0000 F6\narc: W1_H02W0301 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1110101000000000\nword: SLICEB.K0.INIT 0000000000001111\nword: SLICEB.K1.INIT 1100111100000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001000000000000\nword: SLICED.K0.INIT 1111111100111111\nword: SLICED.K1.INIT 1111111111111100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R16C28:PLC2\narc: E1_H02E0601 S3_V06N0303\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 V02S0101\narc: H00R0000 V02N0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 H02E0601\narc: N3_V06N0003 S1_V02N0001\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: V00T0100 V02S0501\narc: W1_H02W0001 V02S0001\narc: W1_H02W0501 S1_V02N0501\narc: A1 H02E0701\narc: A5 Q5\narc: A7 V02N0301\narc: B0 V00T0000\narc: B1 V00T0000\narc: B5 H00R0000\narc: B7 H01E0101\narc: C0 H00L0100\narc: C1 H00L0100\narc: C5 V00B0100\narc: C7 V00T0100\narc: CE0 V02N0201\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 V02S0201\narc: D5 V00B0000\narc: D7 H00R0100\narc: E1_H01E0001 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q1\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q5\narc: V00T0000 Q0\narc: V01S0000 Q0\narc: V01S0100 Q1\nword: SLICEA.K0.INIT 1111001100110011\nword: SLICEA.K1.INIT 1111100110011001\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1110110011001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111100110011001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R16C29:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 S1_V02N0301\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0201 H06E0103\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 E3_H06W0303\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: N1_V02N0001 W3_H06E0003\narc: W3_H06W0203 E1_H01W0000\n\n.tile R16C2:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 E3_H06W0203\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0303 S3_V06N0303\n\n.tile R16C30:PLC2\narc: E1_H02E0201 V01N0001\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 W1_H02E0601\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: H01W0000 W3_H06E0103\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0201 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\n\n.tile R16C31:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V02N0601\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0303 S3_V06N0303\narc: H00R0100 H02E0701\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 H06W0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02N0201\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q0\narc: E1_H02E0201 Q0\narc: M0 V00B0000\narc: MUXCLK0 CLK0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R16C32:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 H01E0101\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 V02N0201\narc: V00B0100 S1_V02N0301\narc: V00T0000 S1_V02N0601\narc: W1_H02W0601 N3_V06S0303\narc: E3_H06E0203 W3_H06E0103\narc: A3 V00B0000\narc: A5 V00T0000\narc: A7 S1_V02N0301\narc: B2 E1_H01W0100\narc: B3 V01N0001\narc: B5 V00B0100\narc: B7 S1_V02N0501\narc: C2 S1_V02N0601\narc: C3 H02W0601\narc: C5 V02N0001\narc: C7 H02E0601\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 E1_H02W0201\narc: D5 H02E0001\narc: D7 H02E0001\narc: E1_H01E0001 Q0\narc: E1_H02E0001 Q0\narc: E1_H02E0501 F7\narc: E3_H06E0003 Q0\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: M0 W1_H02E0601\narc: M4 E1_H02W0401\narc: MUXCLK0 CLK0\narc: S1_V02S0201 Q0\narc: S1_V02S0401 F4\narc: V00T0100 F3\narc: V01S0100 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000001\nword: SLICEB.K0.INIT 0000000000110000\nword: SLICEB.K1.INIT 0010101000111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000010000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R16C33:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 H01E0001\narc: E1_H02E0601 V02N0601\narc: E3_H06E0303 W1_H02E0501\narc: H00R0100 H02W0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0303 N1_V02S0601\narc: V00B0100 H02W0701\narc: V00T0100 H02E0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E1_H01W0000\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: A7 V02N0301\narc: B5 V01S0000\narc: B7 V02N0701\narc: C5 H02E0401\narc: C7 V00B0100\narc: CE0 H00R0100\narc: CE1 N1_V02S0201\narc: CLK0 G_HPBX0000\narc: D5 H02E0201\narc: D7 S1_V02N0401\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q0\narc: E1_H02E0501 F5\narc: E3_H06E0003 Q0\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: M0 V00T0100\narc: M2 H02W0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F7\narc: N1_V02N0201 Q2\narc: S1_V02S0501 F5\narc: V01S0000 Q0\narc: V01S0100 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010101000101010\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R16C34:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0701 H01E0101\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 H01E0101\narc: H00L0100 V02N0301\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0601 H06E0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 H01E0101\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00B0100 H02W0701\narc: V00T0000 V02S0401\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0601 W3_H06E0303\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: A1 W1_H02E0701\narc: A3 V02N0701\narc: A5 H02W0701\narc: A6 V02N0101\narc: B1 E1_H02W0301\narc: B3 H00L0000\narc: B4 H01E0101\narc: B5 H02W0301\narc: B6 V02N0701\narc: C0 H02W0401\narc: C1 H00L0100\narc: C3 H00R0100\narc: C4 H02E0401\narc: C5 V01N0101\narc: C6 V00B0100\narc: C7 V00T0000\narc: CE2 S1_V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 N1_V01S0000\narc: D3 V02N0001\narc: D4 V02N0401\narc: D5 E1_H02W0201\narc: D6 V00B0000\narc: D7 V02N0601\narc: E1_H01E0101 F1\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H01W0000 F2\narc: H01W0100 F0\narc: M2 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 F7\narc: N1_V02N0501 F7\narc: S1_V02S0401 F6\narc: S3_V06S0203 Q4\narc: V00T0100 F1\narc: V01S0000 F1\narc: W1_H02W0601 Q6\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 1100111111111111\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 0000111100000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 0000001000000011\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R16C35:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V01N0101\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V02N0701\narc: E3_H06E0103 N3_V06S0103\narc: E3_H06E0203 V01N0001\narc: H00L0100 H02W0301\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 H06W0003\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 N1_V02S0601\narc: V00B0100 H02W0701\narc: V00T0000 H02E0001\narc: V00T0100 S1_V02N0701\narc: W1_H02W0401 V01N0001\narc: W1_H02W0701 V01N0101\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\narc: A0 E1_H01E0001\narc: A1 H00L0100\narc: A2 V01N0101\narc: A3 V01N0101\narc: A4 N1_V01N0101\narc: A6 W1_H02E0501\narc: A7 N1_V01N0101\narc: B0 H00R0100\narc: B1 W1_H02E0301\narc: B2 E1_H02W0301\narc: B3 H02E0101\narc: B4 N1_V01S0000\narc: B5 V01S0000\narc: B6 H02E0301\narc: B7 W1_H02E0101\narc: C0 W1_H02E0601\narc: C1 N1_V01S0100\narc: C2 S1_V02N0401\narc: C3 W1_H02E0401\narc: C4 V00T0000\narc: C5 F4\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: D0 H01E0101\narc: D1 W1_H02E0001\narc: D2 V01S0100\narc: D3 V00T0100\narc: D4 H02W0201\narc: D5 E1_H01W0100\narc: D6 V02S0601\narc: D7 H02E0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F7\narc: N1_V01N0001 F5\narc: N1_V01N0101 F1\narc: V01S0000 F2\narc: V01S0100 F3\narc: W1_H02W0301 F1\narc: W1_H02W0601 F6\nword: SLICEB.K0.INIT 1100100011111010\nword: SLICEB.K1.INIT 0001000000000001\nword: SLICEC.K0.INIT 0010000000000000\nword: SLICEC.K1.INIT 0000000011001111\nword: SLICEA.K0.INIT 1100110010000000\nword: SLICEA.K1.INIT 0000010000000000\nword: SLICED.K0.INIT 0000011100000000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R16C36:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V01N0101\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 N3_V06S0203\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 V01N0001\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0601\narc: V00B0100 H02E0501\narc: V00T0000 V02N0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 V01N0101\narc: W1_H02W0701 V02S0701\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: A1 W1_H02E0701\narc: A5 V00T0000\narc: A7 H02E0701\narc: B1 E1_H02W0301\narc: B4 H02E0301\narc: B5 S1_V02N0701\narc: B7 V00B0000\narc: C0 H00R0100\narc: C1 H00L0000\narc: C3 H02E0601\narc: C4 E1_H01E0101\narc: C5 E1_H01E0101\narc: C6 V00T0100\narc: C7 E1_H02W0401\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 N1_V01S0000\narc: D3 H02E0001\narc: D4 E1_H01W0100\narc: D5 H02W0001\narc: D6 E1_H02W0001\narc: D7 H00L0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 F0\narc: E1_H02E0401 Q4\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H00L0100 F1\narc: H01W0000 F6\narc: H01W0100 F5\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 F6\narc: S1_V02S0401 F6\narc: V00B0000 F6\narc: V01S0000 F3\narc: W1_H02W0401 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0000000000001111\nword: SLICED.K1.INIT 1111011100000000\nword: SLICEC.K0.INIT 1111110011111111\nword: SLICEC.K1.INIT 0100000000000000\nword: SLICEA.K0.INIT 0000000011110000\nword: SLICEA.K1.INIT 0000010000001111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\n\n.tile R16C37:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V02N0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 V02N0301\narc: H00R0000 W1_H02E0401\narc: H00R0100 H02E0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0701 H02E0701\narc: N3_V06N0203 E1_H01W0000\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02E0701\narc: V00T0100 H02E0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 S1_V02N0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0203 E3_H06W0203\narc: A5 H02E0701\narc: A6 H00R0000\narc: A7 N1_V01N0101\narc: B4 V00B0100\narc: B5 H02E0301\narc: B6 E1_H02W0301\narc: B7 V00B0000\narc: C3 H00R0100\narc: C4 H02E0601\narc: C5 V02S0201\narc: C6 F4\narc: C7 H02W0601\narc: CE0 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D4 H02W0201\narc: D5 H01W0000\narc: D6 H02E0001\narc: D7 H00L0100\narc: E1_H01E0101 F3\narc: E3_H06E0203 F7\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F5\narc: M0 W1_H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q6\narc: V01S0100 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011110000\nword: SLICED.K0.INIT 0100000011111111\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000001100\nword: SLICEC.K1.INIT 0000000000011011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R16C38:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 V01N0101\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 V02N0101\narc: H00R0000 H02W0401\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H06W0303\narc: N3_V06N0203 V01N0001\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 H01E0101\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02E0601\narc: V00B0100 H02W0501\narc: V00T0000 W1_H02E0201\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 E1_H01W0100\narc: E1_H02E0001 W3_H06E0003\narc: N1_V02N0701 W3_H06E0203\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: B0 S1_V02N0301\narc: B2 S1_V02N0301\narc: C0 H00L0100\narc: C2 V02N0601\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 H00R0000\narc: D2 S1_V02N0001\narc: D3 V00B0100\narc: E1_H01E0101 F0\narc: E1_H02E0201 F2\narc: E1_H02E0401 Q4\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q2\narc: M0 V00T0000\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: N3_V06N0003 Q0\narc: N3_V06N0103 Q2\narc: S1_V02S0601 Q4\narc: V01S0100 Q6\narc: W3_H06W0003 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000001111001111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000000111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R16C39:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0303 H01E0101\narc: H00L0000 V02N0201\narc: H00L0100 W1_H02E0301\narc: H00R0000 V02N0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 H02W0701\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 W1_H02E0401\narc: V00B0100 E1_H02W0701\narc: V00T0100 H02W0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 V02S0101\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0301 W3_H06E0003\narc: S3_V06S0003 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: W1_H02W0501 W3_H06E0303\narc: A0 V02S0501\narc: A2 V00B0000\narc: A4 H02W0501\narc: B0 F1\narc: B2 F3\narc: B4 S1_V02N0501\narc: B5 W1_H02E0301\narc: C0 H00L0100\narc: C1 W1_H02E0401\narc: C2 H00L0100\narc: C3 H00L0000\narc: C4 N1_V02S0001\narc: C5 V00T0100\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 H00R0000\narc: D2 S1_V02N0001\narc: D3 V00B0100\narc: D4 H01W0000\narc: D5 H02W0201\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F5\narc: H01W0100 F1\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F3\narc: S3_V06S0103 Q2\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0100010001000000\nword: SLICEC.K1.INIT 0000000000110000\nword: SLICEB.K0.INIT 1000000000000000\nword: SLICEB.K1.INIT 0000000000001111\nword: SLICEA.K0.INIT 0000000010000000\nword: SLICEA.K1.INIT 1111000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R16C3:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 V06S0103\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V02S0701\narc: H00L0000 H02E0201\narc: H00R0000 S1_V02N0601\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0601 H02E0601\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 H02W0601\narc: V00B0000 H02W0401\narc: V00B0100 H02W0701\narc: V00T0000 S1_V02N0401\narc: V01S0100 N3_V06S0303\narc: CE0 H00L0000\narc: CE1 H00R0000\narc: CE2 S1_V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q0\narc: E1_H02E0401 Q4\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: H01W0100 Q6\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 V00B0000\narc: M2 W1_H02E0601\narc: M4 E1_H01E0101\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R16C40:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0701 V01N0101\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0203 H01E0001\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02S0201\narc: H00R0000 H02W0401\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 E1_H01W0000\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 V02N0001\narc: V00B0100 N1_V02S0301\narc: V00T0100 H02W0301\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0701 V01N0101\narc: W1_H02W0301 W3_H06E0003\narc: W1_H02W0501 W3_H06E0303\narc: A1 H00L0000\narc: A5 V02S0101\narc: B0 V02N0101\narc: B1 E1_H02W0101\narc: B3 S1_V02N0301\narc: B4 V02S0501\narc: B5 H00R0000\narc: B6 V02N0501\narc: C0 V02N0601\narc: C1 S1_V02N0401\narc: C3 H00R0100\narc: C4 V02S0001\narc: C5 V00B0100\narc: C6 S1_V02N0001\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 F0\narc: D3 V00T0100\narc: D4 V02S0601\narc: D5 H02W0201\narc: D6 H02W0001\narc: D7 H02E0201\narc: E1_H01E0001 F0\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F4\narc: LSR1 H02W0501\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q5\narc: N1_V02N0101 F1\narc: N1_V02N0701 Q5\narc: S1_V02S0401 F6\narc: V01S0000 F0\narc: V01S0100 F3\narc: W3_H06W0303 Q5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111100110011\nword: SLICEA.K0.INIT 0000110000111111\nword: SLICEA.K1.INIT 0101000001010001\nword: SLICEC.K0.INIT 1100111111000000\nword: SLICEC.K1.INIT 1111111111111000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R16C41:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: H00R0000 E1_H02W0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 H06E0003\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02W0701\narc: V00T0100 W1_H02E0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V06N0203\narc: W1_H02W0501 N1_V02S0501\narc: H01W0000 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: B1 V00B0000\narc: B3 H00R0000\narc: B4 V02S0501\narc: B7 V02N0501\narc: C0 H00L0100\narc: C1 W1_H02E0401\narc: C2 N1_V01N0001\narc: C3 H00R0100\narc: C4 H02W0401\narc: C7 H02W0601\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 V00B0100\narc: D2 H02W0201\narc: D3 H02E0201\narc: D4 E1_H01W0100\narc: D5 V01N0001\narc: D7 H02E0201\narc: E1_H01E0001 F0\narc: E3_H06E0103 F2\narc: E3_H06E0203 Q7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: H01W0100 F4\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q3\narc: S3_V06S0103 Q1\narc: V01S0100 Q7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110000110000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 1111110000110000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1111110000110000\nword: SLICEC.K0.INIT 1111110000001100\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R16C42:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 V02N0701\narc: E3_H06E0103 N3_V06S0103\narc: H00L0000 V02N0201\narc: H00L0100 V02S0101\narc: H00R0100 H02W0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02W0601\narc: V00B0100 S1_V02N0301\narc: V00T0000 E1_H02W0201\narc: V00T0100 E1_H02W0301\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 V02S0401\narc: W1_H02W0701 V02S0701\narc: S1_V02S0301 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 N3_V06S0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0303 E3_H06W0203\narc: A6 H02E0701\narc: B0 S1_V02N0101\narc: B2 E1_H01W0100\narc: B4 H00L0000\narc: B6 H02E0101\narc: C0 N1_V02S0601\narc: C2 V02S0401\narc: C4 V00T0100\narc: C6 V02N0001\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 H00R0000\narc: D2 V02S0001\narc: D3 S1_V02N0001\narc: D4 H00L0100\narc: D5 V00B0000\narc: D6 H00R0100\narc: E1_H01E0101 F2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 Q6\narc: H01W0000 F6\narc: H01W0100 F6\narc: M0 H02E0601\narc: M2 V00T0000\narc: M4 H02E0401\narc: M6 V00B0100\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F0\narc: S1_V02S0401 F6\narc: V01S0000 Q6\narc: V01S0100 F6\narc: W1_H02W0601 F4\nword: SLICEC.K0.INIT 1100111100000011\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111110000001100\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111000011111110\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R16C43:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 V01N0101\narc: H00L0000 V02N0001\narc: H00L0100 V02S0301\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0701 H02E0701\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0601\narc: V00B0100 V02N0301\narc: V00T0000 H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 H01E0101\narc: N1_V02N0501 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: S3_V06S0203 W3_H06E0203\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: B0 E1_H02W0101\narc: B2 E1_H01W0100\narc: B4 H00L0000\narc: B6 H02E0301\narc: C0 V02N0601\narc: C2 H02E0401\narc: C4 S1_V02N0201\narc: C6 V02N0201\narc: D0 H02W0001\narc: D1 N1_V01S0000\narc: D2 N1_V02S0001\narc: D3 N1_V02S0201\narc: D4 V00B0000\narc: D5 V02S0601\narc: D6 V00B0000\narc: D7 H00L0100\narc: E1_H01E0101 F6\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F0\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 V00B0100\narc: N1_V01N0101 F4\narc: W3_H06W0103 F2\nword: SLICED.K0.INIT 0011001100001111\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0011001100001111\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111110000001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R16C44:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 E1_H01W0100\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 W1_H02E0201\narc: H00L0100 N1_V02S0101\narc: H00R0000 H02W0601\narc: H00R0100 V02S0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H02E0701\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H01E0001\narc: V00B0000 E1_H02W0601\narc: V00B0100 H02E0501\narc: V00T0000 H02E0001\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 S3_V06N0203\narc: S1_V02S0301 W3_H06E0003\narc: W3_H06W0003 S3_V06N0003\narc: E3_H06E0203 W3_H06E0203\narc: A0 H02W0701\narc: A1 H02W0701\narc: A2 H02W0701\narc: A3 H02W0701\narc: A4 V02N0301\narc: A5 V00T0000\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 H00L0000\narc: B5 H02E0101\narc: B6 V02S0501\narc: C0 S1_V02N0401\narc: C1 S1_V02N0401\narc: C2 S1_V02N0401\narc: C3 S1_V02N0401\narc: C4 H02W0401\narc: C5 V02S0201\narc: C6 V01N0101\narc: CLK1 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 V02N0401\narc: D5 N1_V02S0401\narc: D6 V00B0000\narc: D7 H00L0100\narc: E1_H01E0101 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F6\narc: LSR1 W1_H02E0501\narc: M6 V00B0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0101 Q1\narc: S1_V02S0201 Q2\narc: V01S0000 Q3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R16C45:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: H00L0000 V02N0201\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02W0601\narc: H00R0100 H02W0501\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 H06E0103\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 S3_V06N0303\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0601\narc: V00T0100 V02N0501\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0401 V06N0203\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 S3_V06N0203\narc: E1_H02E0501 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: B0 V02N0101\narc: B2 V02N0301\narc: B4 H00L0000\narc: B6 H02W0101\narc: C0 E1_H01W0000\narc: C2 H00L0100\narc: C4 S1_V02N0001\narc: C6 V02N0001\narc: D0 E1_H02W0201\narc: D1 V00B0100\narc: D2 H00R0000\narc: D3 H02W0001\narc: D4 H00R0100\narc: D5 V00B0000\narc: D6 H00R0100\narc: D7 E1_H01W0100\narc: E1_H01E0101 F2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 V00T0000\narc: M6 V00T0000\narc: S3_V06S0003 F0\narc: V01S0000 F6\narc: V01S0100 F4\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1100111100000011\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R16C46:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 H01E0101\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0103 V06N0103\narc: E3_H06E0203 V06S0203\narc: E3_H06E0303 V06S0303\narc: H00L0000 S1_V02N0201\narc: H00R0000 E1_H02W0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02W0601\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02S0201\narc: V00B0100 V02N0301\narc: V00T0000 W1_H02E0001\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 S3_V06N0303\narc: N1_V02N0401 W3_H06E0203\narc: S1_V02S0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: A3 E1_H02W0701\narc: B3 H00L0000\narc: B6 S1_V02N0501\narc: C3 H00R0100\narc: C6 S1_V02N0001\narc: CE0 W1_H02E0101\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 S1_V02N0201\narc: D3 V02N0201\narc: D6 V02N0601\narc: D7 H00L0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 Q1\narc: H01W0000 F6\narc: H01W0100 Q1\narc: M0 V00B0000\narc: M1 H02W0001\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 F1\narc: V01S0000 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0011001100001111\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000100011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R16C47:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 S3_V06N0303\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 H01E0101\narc: H00L0000 V02N0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02W0601\narc: H00R0100 H02W0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 E1_H01W0000\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 N1_V02S0501\narc: S3_V06S0203 H06E0203\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0601\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 H01E0001\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V02S0601\narc: S1_V02S0701 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: B0 N1_V02S0301\narc: B1 H01W0100\narc: B2 H00L0000\narc: B4 H02E0301\narc: B7 S1_V02N0701\narc: C0 E1_H02W0401\narc: C1 H00R0100\narc: C2 V02N0401\narc: C4 S1_V02N0001\narc: C7 H02E0601\narc: CE0 H00R0000\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 H02W0001\narc: D2 S1_V02N0001\narc: D3 V00B0100\narc: D4 S1_V02N0401\narc: D5 H00L0100\narc: D7 H02E0001\narc: E1_H01E0001 Q7\narc: E1_H01E0101 Q7\narc: E1_H02E0601 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: H01W0100 Q0\narc: M2 V00T0000\narc: M4 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0201 Q0\narc: N3_V06N0003 Q0\narc: S3_V06S0103 F1\narc: V01S0000 Q7\narc: V01S0100 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110000110000\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 1100111100000011\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R16C48:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0501 S1_V02N0501\narc: H00R0000 S1_V02N0601\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02S0201\narc: V00B0100 H02W0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 E1_H01W0100\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0001 W3_H06E0003\narc: S1_V02S0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0203 E3_H06W0203\narc: B0 V02S0301\narc: B1 V00T0000\narc: B3 E1_H02W0101\narc: B6 H01E0101\narc: C0 H02W0601\narc: C1 N1_V02S0401\narc: C2 H00L0100\narc: C3 H02E0601\narc: C6 S1_V02N0001\narc: C7 H01E0001\narc: CE0 H00R0000\narc: CE1 W1_H02E0101\narc: CE2 V02N0601\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 N1_V02S0001\narc: D1 V02S0001\narc: D2 S1_V02N0201\narc: D3 H02E0001\narc: D6 V00B0000\narc: D7 S1_V02N0401\narc: E1_H02E0601 Q4\narc: E3_H06E0103 F2\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: H01W0000 Q6\narc: H01W0100 Q4\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0003 Q0\narc: S1_V02S0301 Q3\narc: S3_V06S0003 Q0\narc: V00T0000 Q0\narc: V01S0100 F1\narc: W3_H06W0003 Q3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1111110000110000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0000111111110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R16C49:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 H01E0001\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 H01E0101\narc: H00L0000 N1_V02S0001\narc: H00L0100 N1_V02S0301\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H06W0303\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 E1_H01W0000\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 H06E0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02W0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 V02N0701\narc: E1_H01E0101 W3_H06E0203\narc: A7 H00L0000\narc: B6 V01S0000\narc: B7 E1_H02W0101\narc: C3 S1_V02N0401\narc: C6 V02S0201\narc: C7 H02W0601\narc: CLK0 G_HPBX0000\narc: D3 V02N0201\narc: D6 H00L0100\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F3\narc: LSR1 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q7\narc: V01S0000 Q7\narc: W1_H02W0301 F3\narc: W3_H06W0003 F3\narc: W3_H06W0203 Q7\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 1100111111000000\nword: SLICED.K1.INIT 1111111111111000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R16C4:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 V02S0601\narc: H00L0000 S1_V02N0201\narc: H00L0100 V02N0301\narc: H00R0000 V02S0601\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0701 H02W0701\narc: S3_V06S0203 H06W0203\narc: V00B0000 V02S0201\narc: V00B0100 E1_H02W0501\narc: V00T0000 S1_V02N0601\narc: V00T0100 S1_V02N0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 S1_V02N0701\narc: A1 V02S0501\narc: A4 W1_H02E0501\narc: A5 N1_V01N0101\narc: A7 H02E0701\narc: B1 N1_V02S0101\narc: B4 V01S0000\narc: B5 H00L0000\narc: B7 V00T0000\narc: C1 H00L0100\narc: C4 E1_H01E0101\narc: C5 H02W0601\narc: C7 V00B0100\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D4 H01W0000\narc: D5 V00B0000\narc: D7 H00R0100\narc: E1_H01E0101 F1\narc: E3_H06E0203 F4\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: LSR1 V00T0100\narc: M2 H02E0601\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0101 Q2\narc: V01S0000 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R16C50:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 S3_V06N0303\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 W1_H02E0001\narc: H00L0100 V02N0101\narc: H00R0100 W1_H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 E1_H01W0000\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 H01E0001\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02N0301\narc: V00T0000 H02E0001\narc: V00T0100 W1_H02E0101\narc: W1_H02W0101 H01E0101\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 N3_V06S0203\narc: N3_V06N0303 W3_H06E0303\narc: W1_H02W0201 W3_H06E0103\narc: B0 S1_V02N0101\narc: B1 H01W0100\narc: B4 S1_V02N0501\narc: B5 H00R0000\narc: C0 H00L0000\narc: C1 N1_V02S0401\narc: C4 H02E0401\narc: C5 V00B0100\narc: CE0 H00R0100\narc: CE1 H00L0100\narc: CE2 H00R0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 V02S0201\narc: D4 V00B0000\narc: D5 W1_H02E0201\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q6\narc: E1_H02E0701 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: H01W0100 Q0\narc: M2 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0001 Q0\narc: S3_V06S0103 F1\narc: V01S0100 Q0\narc: W3_H06W0203 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100111111000000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111000011001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R16C51:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 H01E0101\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V02N0701\narc: E3_H06E0003 V01N0001\narc: H00L0000 H02E0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 W1_H02E0601\narc: H00R0100 H02W0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0001\narc: V00B0100 V02S0101\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 E1_H02W0501\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0103\narc: A5 V02S0101\narc: B0 W1_H02E0301\narc: B2 S1_V02N0101\narc: B3 H01W0100\narc: B5 W1_H02E0301\narc: B6 V00T0000\narc: B7 V01S0000\narc: C0 H02E0601\narc: C2 H00L0000\narc: C3 H00R0100\narc: C5 H02E0601\narc: C6 W1_H02E0401\narc: C7 V00T0100\narc: CE0 H02E0101\narc: CE1 H00L0100\narc: CE2 H02E0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 S1_V02N0201\narc: D2 H00R0000\narc: D3 H02E0201\narc: D5 V00B0000\narc: D6 N1_V02S0601\narc: D7 H02E0201\narc: E1_H01E0001 F3\narc: E3_H06E0103 Q2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q2\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q5\narc: N3_V06N0303 Q6\narc: S1_V02S0501 F7\narc: V01S0000 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100110111001000\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1100111111000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R16C52:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0303 W1_H02E0601\narc: H00L0100 E1_H02W0301\narc: H00R0000 V02S0601\narc: H00R0100 W1_H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 V01N0101\narc: N3_V06N0203 H06E0203\narc: N3_V06N0303 H06W0303\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0001\narc: V00T0000 H02W0201\narc: V00T0100 E1_H02W0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0701 V02S0701\narc: E1_H01E0001 W3_H06E0003\narc: S3_V06S0203 W3_H06E0203\narc: W3_H06W0003 S3_V06N0003\narc: A5 V00T0000\narc: B0 V00T0000\narc: B2 H02W0301\narc: B5 S1_V02N0501\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 W1_H02E0601\narc: C5 W1_H02E0601\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 H02E0001\narc: D2 S1_V02N0001\narc: D3 H00R0000\narc: D5 V00B0000\narc: E1_H01E0101 Q6\narc: E3_H06E0103 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q5\narc: H01W0100 Q0\narc: M2 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 F1\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111111000000100\nword: SLICEA.K0.INIT 1111001111000000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 1111110000001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R16C53:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 S3_V06N0003\narc: H00L0100 S1_V02N0101\narc: H00R0100 V02N0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 E1_H01W0000\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 V01N0001\narc: S1_V02S0001 H02W0001\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02S0201\narc: V00T0100 E1_H02W0301\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0701 S1_V02N0701\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A7 V02N0301\narc: B7 V00B0000\narc: C7 H02W0601\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D7 V02N0601\narc: E1_H01E0101 Q2\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q0\narc: M0 H02E0601\narc: M2 V00B0100\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q2\narc: V00B0100 Q7\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111000000010\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R16C54:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 V01N0101\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 V02S0201\narc: H00R0100 V02N0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 W1_H02E0201\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 H06E0303\narc: V00B0000 V02N0001\narc: V00B0100 H02W0501\narc: V00T0000 N1_V02S0601\narc: V00T0100 H02E0101\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 N3_V06S0203\narc: S1_V02S0301 W3_H06E0003\narc: S1_V02S0701 W3_H06E0203\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0001 W3_H06E0003\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 N1_V01S0000\narc: W3_H06W0303 E1_H01W0100\narc: A0 H00L0000\narc: A4 H02W0501\narc: A7 H02W0501\narc: B0 V00T0000\narc: B4 H02E0301\narc: B5 V00B0100\narc: B7 H02E0101\narc: C0 N1_V01N0001\narc: C4 V00T0100\narc: C5 V00T0100\narc: C7 H02W0401\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D4 V02N0401\narc: D5 S1_V02N0401\narc: D7 W1_H02E0001\narc: E1_H01E0001 F5\narc: E1_H01E0101 Q2\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H01W0000 Q2\narc: M0 H02W0601\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F7\narc: W3_H06W0003 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1110111001100000\nword: SLICEC.K0.INIT 0011000000100010\nword: SLICEC.K1.INIT 1100000000000000\nword: SLICEA.K0.INIT 1111111111111000\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R16C55:PLC2\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0303 V01N0101\narc: H00R0000 V02N0401\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 V01N0101\narc: N3_V06N0303 H01E0101\narc: S1_V02S0001 H02E0001\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 S1_V02N0101\narc: V00T0100 V02N0501\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 V06N0303\narc: W1_H02W0601 H01E0001\narc: E3_H06E0003 W3_H06E0303\narc: CE0 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q6\narc: H01W0100 Q4\narc: M0 W1_H02E0601\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: W1_H02W0001 Q0\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R16C56:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0003 V01N0001\narc: H00L0000 N1_V02S0201\narc: H00R0000 H02W0601\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0601 N1_V01S0000\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 H02W0401\narc: V00B0100 H02E0701\narc: V00T0000 H02W0001\narc: V00T0100 S1_V02N0701\narc: W1_H02W0301 S3_V06N0003\narc: E1_H02E0001 W3_H06E0003\narc: H01W0100 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: A2 V00T0000\narc: A5 W1_H02E0501\narc: A6 W1_H02E0501\narc: B2 H00L0000\narc: B5 H02E0301\narc: B6 H02E0301\narc: B7 W1_H02E0301\narc: C2 H00R0100\narc: C5 H02E0401\narc: C6 V02S0201\narc: C7 V00B0100\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V01S0100\narc: D5 E1_H02W0001\narc: D6 V02S0401\narc: D7 V00B0000\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: M0 V00T0100\narc: M2 N1_V01N0001\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q0\narc: N1_V02N0001 Q2\narc: V01S0100 F6\narc: W1_H02W0001 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1110111001100000\nword: SLICED.K0.INIT 0000110000001010\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEB.K0.INIT 1111111111111000\nword: SLICEB.K1.INIT 1111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R16C57:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0601 N1_V01S0000\narc: H00L0000 E1_H02W0201\narc: H00R0000 V02N0601\narc: H00R0100 V02S0701\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 V01N0001\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0401\narc: V00B0100 H02W0701\narc: V00T0000 S1_V02N0401\narc: V00T0100 H02W0301\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: W3_H06W0203 N1_V01S0000\narc: E3_H06E0103 W3_H06E0103\narc: A4 E1_H02W0701\narc: A5 E1_H02W0701\narc: A7 H00L0000\narc: B4 V00B0100\narc: B5 V00B0100\narc: B6 E1_H02W0101\narc: B7 H02E0101\narc: C4 E1_H02W0401\narc: C5 E1_H02W0401\narc: C6 V02S0201\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CE1 H02W0101\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 V00B0000\narc: D6 H00R0100\narc: D7 H00R0100\narc: E1_H01E0001 F4\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: M0 H02W0601\narc: M2 V00T0100\narc: M4 H02E0401\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 Q2\narc: N1_V02N0001 Q2\narc: V00B0000 F6\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000110000000000\nword: SLICED.K1.INIT 1010001010110011\nword: SLICEC.K0.INIT 0101010101010111\nword: SLICEC.K1.INIT 0000000000001011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R16C58:PLC2\narc: H00R0000 H02E0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 N1_V01S0000\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02N0001\narc: V00T0000 V02S0401\narc: V00T0100 V02N0501\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02S0701\narc: N1_V02N0201 W3_H06E0103\narc: A0 H00R0000\narc: A4 W1_H02E0501\narc: A7 W1_H02E0501\narc: B0 H01W0100\narc: B4 V02N0501\narc: B5 W1_H02E0301\narc: B7 V02N0501\narc: C0 V02S0601\narc: C4 V02S0201\narc: C5 V00T0100\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D4 H00R0100\narc: D5 V02N0401\narc: D7 V00B0000\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: V00B0100 F5\narc: V01S0100 F4\narc: W3_H06W0003 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1110111001100000\nword: SLICEC.K0.INIT 0000110000001010\nword: SLICEC.K1.INIT 1100000000000000\nword: SLICEA.K0.INIT 1111111111101100\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R16C59:PLC2\narc: N1_V02N0301 H06E0003\narc: V00B0000 S1_V02N0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02S0601\narc: V00T0100 H02W0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0103 V06S0103\narc: A4 V00T0100\narc: A6 V00T0100\narc: B4 W1_H02E0101\narc: B6 W1_H02E0101\narc: C4 V02N0201\narc: C6 V02N0001\narc: CLK0 G_HPBX0000\narc: D4 S1_V02N0401\narc: D6 S1_V02N0601\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: LSR0 V00B0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 1010000011101100\nword: SLICEC.K1.INIT 1111111111111111\nword: SLICED.K0.INIT 1010000011101100\nword: SLICED.K1.INIT 1111111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R16C5:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 V02N0701\narc: H00R0000 H02E0601\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 E1_H02W0401\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 H06W0103\narc: S1_V02S0401 H06W0203\narc: S1_V02S0701 E1_H02W0701\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0601\narc: V00T0100 N1_V02S0501\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 N1_V02S0701\narc: A5 H02E0501\narc: B5 N1_V02S0701\narc: C5 V02N0201\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D5 V02S0601\narc: E1_H01E0001 F5\narc: E1_H01E0101 Q0\narc: E1_H02E0001 Q2\narc: E3_H06E0003 Q0\narc: F5 F5_SLICE\narc: LSR0 V00B0000\narc: M0 V00B0100\narc: M2 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1001000000001001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R16C60:PLC2\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 N1_V02S0101\narc: N1_V02N0101 W3_H06E0103\n\n.tile R16C61:PLC2\narc: E3_H06E0003 W3_H06E0003\n\n.tile R16C62:PLC2\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\n\n.tile R16C63:PLC2\narc: N3_V06N0103 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\n\n.tile R16C64:PLC2\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\n\n.tile R16C66:PLC2\narc: S3_V06S0103 H06E0103\n\n.tile R16C67:PLC2\narc: S3_V06S0103 N3_V06S0003\narc: E3_H06E0003 W3_H06E0003\n\n.tile R16C6:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0501 H01E0101\narc: E1_H02E0701 V02S0701\narc: H00L0100 H02E0101\narc: H00R0000 V02S0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H06E0303\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 N3_V06S0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 E1_H02W0501\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 E1_H02W0301\narc: W3_H06W0303 E1_H01W0100\narc: W3_H06W0003 E3_H06W0303\narc: A1 H00L0100\narc: A4 H02E0501\narc: A5 V00T0000\narc: A6 H00L0000\narc: A7 V02N0101\narc: B1 S1_V02N0301\narc: B4 V01S0000\narc: B5 N1_V02S0701\narc: B6 V02N0701\narc: B7 V00T0000\narc: C1 H00R0100\narc: C4 F6\narc: C5 N1_V02S0201\narc: C6 H02W0601\narc: C7 V00T0100\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D4 H02W0001\narc: D5 S1_V02N0601\narc: D6 V00B0000\narc: D7 V00B0000\narc: E1_H01E0101 F4\narc: E1_H02E0001 F0\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 F7\narc: LSR0 H02E0301\narc: M0 H01E0001\narc: M2 E1_H02W0601\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q2\narc: V01S0000 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1000000001000000\nword: SLICEC.K1.INIT 1011000000001011\nword: SLICED.K0.INIT 1000010010100101\nword: SLICED.K1.INIT 1111001101010001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010001001010001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R16C70:PLC2\narc: S3_V06S0003 H06E0003\n\n.tile R16C7:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 H01E0101\narc: H00L0000 H02W0001\narc: H00R0000 V02N0601\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0203 E3_H06W0203\narc: S3_V06S0103 N3_V06S0003\narc: V00B0100 W1_H02E0701\narc: V00T0000 N1_V02S0401\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0303 E1_H02W0501\narc: W3_H06W0203 E3_H06W0203\narc: A1 H02W0701\narc: A3 E1_H02W0701\narc: A4 N1_V01N0101\narc: A5 H02E0701\narc: A6 V02S0101\narc: A7 V00T0100\narc: B1 V02N0101\narc: B3 H00R0000\narc: B4 E1_H02W0301\narc: B5 V02N0501\narc: B6 V00B0000\narc: B7 H02W0101\narc: C1 E1_H02W0601\narc: C3 H00L0000\narc: C4 V02N0201\narc: C5 V00T0000\narc: C6 W1_H02E0601\narc: C7 V02S0001\narc: D1 S1_V02N0201\narc: D3 V00B0100\narc: D4 H01W0000\narc: D5 H02E0001\narc: D6 H00R0100\narc: D7 V02S0401\narc: E1_H02E0601 F6\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0000 F5\narc: N1_V01N0101 F3\narc: V00B0000 F4\narc: V00T0100 F1\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000001001000001\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000010000100001\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R16C8:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V02S0701\narc: H00L0000 H02W0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 N1_V02S0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0601\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02W0101\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 S1_V02N0701\narc: W3_H06W0103 N3_V06S0103\narc: W3_H06W0303 N3_V06S0303\narc: W3_H06W0203 E3_H06W0103\narc: A1 V02N0701\narc: A2 N1_V02S0701\narc: A3 W1_H02E0501\narc: A4 H02E0501\narc: A5 N1_V01N0101\narc: A7 H00R0000\narc: B1 V02S0101\narc: B2 H02E0301\narc: B3 H00R0100\narc: B4 V01S0000\narc: B5 V00B0100\narc: B7 H02E0101\narc: C1 V02N0401\narc: C2 H00L0000\narc: C3 H00L0100\narc: C4 V02S0201\narc: C5 V01N0101\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D2 V00T0100\narc: D3 W1_H02E0201\narc: D4 V00B0000\narc: D5 H02W0201\narc: D7 H02E0201\narc: E1_H01E0101 F2\narc: E3_H06E0203 Q4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: MUXCLK2 CLK0\narc: N1_V01N0101 F3\narc: S3_V06S0203 Q4\narc: V00B0100 F7\narc: V01S0000 F5\narc: W1_H02W0301 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000001001000001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1001000000001001\nword: SLICEB.K0.INIT 1101000000001101\nword: SLICEB.K1.INIT 1000010010100101\nword: SLICEC.K0.INIT 1000111100001111\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R16C9:PLC2\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: H00R0100 H02E0501\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00B0100 H02E0701\narc: V00T0000 H02E0201\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V02N0701\narc: E3_H06E0303 W3_H06E0203\narc: A5 V00B0000\narc: B4 N1_V02S0701\narc: B5 V02S0701\narc: C4 V00T0000\narc: C5 V02S0001\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D4 H01W0000\narc: D5 H02W0201\narc: E1_H01E0101 Q0\narc: E1_H02E0001 Q2\narc: E1_H02E0401 F4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F5\narc: LSR1 H02W0301\narc: M0 H02E0601\narc: M2 V00B0100\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q0\narc: W1_H02W0401 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100111100000000\nword: SLICEC.K1.INIT 1001100100001001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R17C10:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 H02E0201\narc: H00R0100 V02N0501\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02S0201\narc: V00B0100 V02N0101\narc: V00T0000 V02S0601\narc: V00T0100 N1_V02S0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 E1_H02W0601\narc: N1_V02N0001 W3_H06E0003\narc: W3_H06W0103 V06S0103\narc: W3_H06W0203 N3_V06S0203\narc: E3_H06E0103 W3_H06E0103\narc: A1 H00R0000\narc: A7 H00L0000\narc: B1 V00B0000\narc: B7 V00B0100\narc: C1 N1_V02S0601\narc: C7 H02W0401\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D7 H02E0001\narc: E1_H01E0001 F1\narc: E3_H06E0203 F7\narc: F1 F1_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M2 H02E0601\narc: M4 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q2\narc: W1_H02W0001 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R17C11:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V02S0601\narc: E3_H06E0203 S3_V06N0203\narc: H00R0000 W1_H02E0401\narc: H00R0100 V02N0501\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 H06W0303\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0401\narc: V00B0100 H02E0501\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02W0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 V02S0401\narc: W3_H06W0003 E3_H06W0003\narc: A5 H02E0701\narc: A7 H00L0000\narc: B5 H00R0000\narc: B7 H02E0101\narc: C5 H02E0601\narc: C7 V00B0100\narc: CE0 E1_H02W0101\narc: CE1 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D5 H00R0100\narc: D7 V00B0000\narc: E3_H06E0303 F6\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q2\narc: H01W0100 Q0\narc: LSR1 H02E0301\narc: M0 V00T0000\narc: M2 V00T0100\narc: M6 N1_V01N0101\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: N1_V01N0101 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R17C12:PLC2\narc: E1_H02E0401 V06S0203\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 S3_V06N0003\narc: H00L0000 V02S0001\narc: H00L0100 V02S0101\narc: H00R0100 V02N0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 V02S0201\narc: V00B0100 V02N0301\narc: V00T0000 V02S0401\narc: V00T0100 E1_H02W0301\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 N3_V06S0203\narc: W3_H06W0203 E3_H06W0203\narc: A7 H02E0501\narc: B7 V00B0000\narc: C7 V02N0201\narc: CE0 H00L0100\narc: CE1 H00R0100\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D7 V02S0601\narc: E1_H02E0001 Q0\narc: E1_H02E0501 F7\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 V00T0000\narc: M2 H02E0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N3_V06N0203 Q4\narc: W1_H02W0001 Q0\narc: W1_H02W0601 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R17C13:PLC2\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 V01N0001\narc: H00L0000 H02E0001\narc: H00L0100 V02S0301\narc: H00R0000 H02W0601\narc: H00R0100 H02E0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 H06E0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H02W0701\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 V01N0001\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0701\narc: V00T0000 H02W0001\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0601 V06S0303\narc: W3_H06W0003 E1_H01W0000\narc: A1 V02N0501\narc: A3 E1_H02W0501\narc: A7 H00L0000\narc: B1 E1_H01W0100\narc: B3 W1_H02E0301\narc: B7 V00T0000\narc: C1 S1_V02N0401\narc: C3 H00L0100\narc: C7 H02W0401\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V02S0201\narc: D3 V00B0100\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: LSR1 H02W0501\narc: M4 V00B0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V02N0501 F7\narc: N3_V06N0103 F1\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R17C14:PLC2\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 V02N0201\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0401 N1_V01S0000\narc: N3_V06N0103 H06W0103\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0601\narc: V00B0100 H02E0501\narc: V00T0000 V02N0401\narc: V00T0100 V02S0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 V06S0203\narc: W3_H06W0303 V06S0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: H01W0000 Q0\narc: H01W0100 Q2\narc: LSR0 V00T0000\narc: LSR1 V00B0000\narc: M0 V00T0100\narc: M2 V00T0100\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q2\narc: N3_V06N0303 Q6\narc: V01S0100 Q4\narc: W1_H02W0001 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R17C15:PLC2\narc: E1_H02E0601 S3_V06N0303\narc: H00L0100 E1_H02W0301\narc: H00R0000 H02W0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 H01E0101\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0103 S1_V02N0101\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0401 N1_V02S0401\narc: S3_V06S0203 N1_V02S0701\narc: V00B0100 S1_V02N0101\narc: W1_H02W0501 V02N0501\narc: W3_H06W0103 V06S0103\narc: A4 H02E0701\narc: A5 H02E0501\narc: B0 H00R0100\narc: B1 V02N0301\narc: B4 H02W0101\narc: B5 H00R0000\narc: C0 H00L0100\narc: C1 S1_V02N0401\narc: C4 S1_V02N0001\narc: C5 E1_H02W0601\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00B0100\narc: D4 V02N0401\narc: D5 V02N0601\narc: E1_H01E0001 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q5\narc: LSR1 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N3_V06N0003 F0\narc: N3_V06N0203 F4\narc: V00T0000 F0\narc: V00T0100 F1\narc: W3_H06W0003 F0\nword: SLICEA.K0.INIT 1100111111111111\nword: SLICEA.K1.INIT 0000000000000011\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 0111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R17C16:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 V02N0701\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 V02N0301\narc: H00R0000 V02S0401\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0301 V01N0101\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 N1_V02S0101\narc: V00T0100 V02S0701\narc: W1_H02W0101 V06S0103\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0303 E1_H01W0100\narc: B1 V02S0101\narc: C1 E1_H02W0401\narc: CE0 H00R0000\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: F1 F1_SLICE\narc: M2 V00B0100\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q1\narc: S1_V02S0201 Q2\narc: V01S0000 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111001111000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R17C17:PLC2\narc: E1_H02E0601 V02N0601\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 V02S0201\narc: H00L0100 N1_V02S0101\narc: N1_V02N0601 H02E0601\narc: S1_V02S0101 H02W0101\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02N0101\narc: W1_H02W0401 E1_H02W0101\narc: E1_H02E0401 W3_H06E0203\narc: W1_H02W0601 W3_H06E0303\narc: B0 H00R0100\narc: B1 V01N0001\narc: B3 S1_V02N0301\narc: B4 V01S0000\narc: B5 H02W0301\narc: C0 N1_V01N0001\narc: C1 S1_V02N0601\narc: C3 H00L0000\narc: C4 V00T0100\narc: C5 V00B0100\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 V00B0100\narc: D2 N1_V01S0000\narc: D3 N1_V02S0201\narc: D4 H02E0001\narc: D5 V00B0000\narc: E1_H01E0001 F1\narc: E3_H06E0103 F2\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0100 Q5\narc: H01W0100 F2\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M2 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0001 Q1\narc: N1_V02N0201 Q2\narc: N1_V02N0401 F4\narc: N3_V06N0103 Q1\narc: N3_V06N0203 F4\narc: N3_V06N0303 Q5\narc: S3_V06S0103 F1\narc: S3_V06S0303 F5\narc: V00T0100 Q1\narc: V01S0000 Q5\narc: V01S0100 F2\narc: W1_H02W0301 Q1\narc: W1_H02W0501 Q5\narc: W3_H06W0003 F0\narc: W3_H06W0103 Q2\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 1111110011111111\nword: SLICEC.K1.INIT 1100111111000000\nword: SLICEA.K0.INIT 0011111111111111\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R17C18:PLC2\narc: E1_H02E0201 H01E0001\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 V01N0101\narc: E1_H02E0701 W1_H02E0701\narc: H00L0000 V02S0001\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0401 N3_V06S0203\narc: S3_V06S0203 N3_V06S0103\narc: V00B0100 H02W0501\narc: V00T0100 E1_H02W0301\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E1_H02W0601\narc: E1_H02E0301 W3_H06E0003\narc: C6 H02E0601\narc: C7 E1_H02W0401\narc: CE0 H00R0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D6 E1_H02W0201\narc: D7 V00B0000\narc: E1_H01E0101 Q2\narc: E1_H02E0601 Q4\narc: E3_H06E0303 Q6\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: LSR0 W1_H02E0501\narc: LSR1 W1_H02E0501\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V02N0201 Q0\narc: V00B0000 Q6\narc: W3_H06W0203 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 1111111111110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R17C19:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 V02N0301\narc: E1_H02E0601 V02S0601\narc: H00L0000 V02S0201\narc: H00L0100 V02N0101\narc: H00R0000 H02E0401\narc: H00R0100 H02W0701\narc: H01W0000 E3_H06W0103\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 H06W0303\narc: V00B0000 V02S0201\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0601\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V01N0101\narc: W1_H02W0701 E3_H06W0203\narc: A0 V02N0701\narc: A1 V02N0701\narc: A2 V02N0701\narc: A3 V02N0701\narc: A4 H02E0701\narc: A5 H02E0501\narc: A6 S1_V02N0101\narc: A7 V00T0100\narc: B0 V00B0000\narc: B1 V00B0000\narc: B2 H00L0000\narc: B3 H00L0000\narc: B4 E1_H02W0301\narc: B5 V02N0501\narc: B6 H01E0101\narc: B7 V00B0100\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 E1_H02W0401\narc: C5 V02S0001\narc: C6 H02E0601\narc: C7 E1_H02W0601\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CLK1 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02N0001\narc: D2 V02N0001\narc: D3 V02N0001\narc: D4 E1_H02W0001\narc: D5 H00R0100\narc: D6 S1_V02N0401\narc: D7 V02N0401\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00T0000\narc: LSR1 H02W0501\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: S1_V02S0701 F7\narc: V00T0100 Q3\narc: V01S0100 Q1\nword: SLICED.K0.INIT 1001000000001001\nword: SLICED.K1.INIT 1100101000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R17C20:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0601 H01E0001\narc: H00L0000 V02N0001\narc: H00L0100 V02S0301\narc: H00R0000 E1_H02W0401\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0501 N3_V06S0303\narc: S1_V02S0201 H02E0201\narc: S1_V02S0401 N3_V06S0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 H06E0103\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 V01N0101\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A1 V02S0701\narc: A5 N1_V01N0101\narc: A7 V00T0100\narc: B1 H02W0101\narc: B3 N1_V02S0101\narc: B5 H02W0101\narc: B6 V00B0000\narc: B7 V00T0000\narc: C0 H00L0000\narc: C1 N1_V01N0001\narc: C3 H00L0100\narc: C4 V02S0001\narc: C5 V00T0000\narc: C6 H02E0601\narc: C7 S1_V02N0001\narc: CE2 H00R0000\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 E1_H02W0201\narc: D3 H02W0201\narc: D4 H00L0100\narc: D5 E1_H01W0100\narc: D6 H00R0100\narc: D7 H01W0000\narc: E1_H01E0101 F4\narc: E1_H02E0401 Q4\narc: E1_H02E0701 F5\narc: E3_H06E0303 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0000 F3\narc: H01W0100 Q4\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F0\narc: N1_V01N0101 Q4\narc: N1_V02N0401 Q6\narc: N1_V02N0601 Q4\narc: N1_V02N0701 F7\narc: S1_V02S0301 F1\narc: S1_V02S0501 F5\narc: S1_V02S0701 F5\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V00B0000 Q6\narc: V00T0000 F0\narc: V01S0000 F1\narc: V01S0100 F7\narc: W1_H02W0501 F5\narc: W1_H02W0601 Q4\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000111111\nword: SLICEA.K0.INIT 0000000000001111\nword: SLICEA.K1.INIT 0001000000000000\nword: SLICED.K0.INIT 0011110011000011\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 1111000011111111\nword: SLICEC.K1.INIT 0001000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R17C21:PLC2\narc: E1_H02E0501 V06N0303\narc: E1_H02E0601 V02N0601\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 E1_H02W0001\narc: H00L0100 V02N0301\narc: H00R0000 H02E0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 N1_V01S0100\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 V01N0001\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02N0001\narc: V00T0000 H02W0001\narc: V00T0100 H02W0301\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 E1_H02W0701\narc: W3_H06W0003 E3_H06W0303\narc: A1 H02W0501\narc: A3 V00T0000\narc: A4 E1_H01W0000\narc: A7 H00R0000\narc: B1 V02S0101\narc: B3 H00R0100\narc: B4 H02W0101\narc: B7 H01E0101\narc: C0 H00L0100\narc: C1 N1_V01N0001\narc: C3 H00L0000\narc: C4 H02W0601\narc: C7 E1_H01E0101\narc: D0 H02E0001\narc: D1 V01S0100\narc: D3 V02N0001\narc: D4 E1_H01W0100\narc: D7 H02E0201\narc: E1_H01E0001 F1\narc: E1_H01E0101 F0\narc: E1_H02E0401 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F2\narc: M2 H02E0601\narc: M4 V00B0000\narc: M6 V00T0100\narc: N1_V01N0001 F0\narc: V01S0000 F6\narc: V01S0100 F4\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000000100000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000100000000\nword: SLICEC.K0.INIT 1111111011111111\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000010000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R17C22:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0103 W1_H02E0101\narc: H00L0100 V02N0301\narc: H00R0000 V02S0601\narc: N1_V02N0101 H06E0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 H02E0601\narc: S1_V02S0501 V01N0101\narc: S3_V06S0003 N1_V02S0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 E1_H01W0100\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: A0 V02S0701\narc: A1 H00L0000\narc: A4 V00T0100\narc: A6 V00T0100\narc: A7 V00T0100\narc: B0 V00B0000\narc: B1 E1_H01W0100\narc: B2 V02S0101\narc: B4 V01S0000\narc: B6 V00B0000\narc: B7 V00B0000\narc: C0 N1_V01N0001\narc: C1 H02W0601\narc: C2 H00L0100\narc: C4 V00T0000\narc: C5 V02N0201\narc: C6 Q6\narc: C7 V02S0001\narc: CE0 V02S0201\narc: CE1 H00R0000\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 E1_H02W0201\narc: D2 V00B0100\narc: D3 V00T0100\narc: D4 H00R0100\narc: D5 V02N0401\narc: D6 H00R0100\narc: D7 H00R0100\narc: E1_H01E0001 F0\narc: E1_H01E0101 F0\narc: E1_H02E0001 Q0\narc: E3_H06E0003 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q0\narc: H00R0100 F5\narc: H01W0000 Q3\narc: H01W0100 Q6\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q3\narc: N1_V02N0001 Q0\narc: N1_V02N0201 F0\narc: N1_V02N0501 F5\narc: S3_V06S0303 F5\narc: V00B0000 Q4\narc: V00B0100 F5\narc: V00T0000 Q2\narc: V00T0100 Q3\narc: V01S0000 Q4\narc: V01S0100 Q2\narc: W1_H02W0001 Q0\narc: W1_H02W0301 F1\narc: W1_H02W0601 Q4\narc: W3_H06W0003 F0\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0011110011000011\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0110110011001001\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 1111111111111110\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICED.K0.INIT 1111000011100001\nword: SLICED.K1.INIT 0111100011110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R17C23:PLC2\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0701 N1_V02S0701\narc: H00L0000 E1_H02W0001\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 H01E0101\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0003 H06W0003\narc: S3_V06S0303 E3_H06W0303\narc: V00T0000 V02N0401\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 S1_V02N0701\narc: N1_V02N0401 W3_H06E0203\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A0 H00L0100\narc: A3 H00L0100\narc: A4 V00T0100\narc: A6 V00T0100\narc: A7 V00T0100\narc: B0 H00R0100\narc: B2 H01W0100\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 V01S0000\narc: B6 V00B0000\narc: B7 V00B0000\narc: C0 N1_V01N0001\narc: C2 V02S0601\narc: C3 H02E0601\narc: C4 Q4\narc: C5 V00B0100\narc: C6 Q6\narc: C7 E1_H01E0101\narc: CE0 E1_H02W0101\narc: CE1 H00L0000\narc: CE2 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V00T0100\narc: D2 E1_H02W0201\narc: D3 V01S0100\narc: D4 H02E0201\narc: D5 H02E0201\narc: D6 H02E0201\narc: D7 H02E0201\narc: E1_H01E0001 F3\narc: E1_H01E0101 Q6\narc: E1_H02E0101 Q3\narc: E1_H02E0201 F2\narc: E1_H02E0301 F3\narc: E3_H06E0003 Q3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 Q1\narc: H00R0000 Q6\narc: H00R0100 Q5\narc: H01W0000 Q6\narc: H01W0100 Q3\narc: LSR0 V00T0000\narc: LSR1 H02E0501\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 F3\narc: V00B0000 Q4\narc: V00B0100 Q5\narc: V00T0100 Q1\narc: V01S0000 Q1\narc: V01S0100 Q4\narc: W1_H02W0001 F0\narc: W1_H02W0101 Q3\narc: W1_H02W0201 F2\nword: SLICEC.K0.INIT 0111100011100001\nword: SLICEC.K1.INIT 0011110011000011\nword: SLICEB.K0.INIT 1100000000000000\nword: SLICEB.K1.INIT 1111111111111110\nword: SLICEA.K0.INIT 0000000100000000\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1111000011100001\nword: SLICED.K1.INIT 0111100011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R17C24:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0201 V01N0001\narc: E1_H02E0601 H01E0001\narc: E3_H06E0203 V01N0001\narc: H00L0000 H02E0201\narc: H00L0100 V02S0101\narc: H00R0000 S1_V02N0601\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H02E0701\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 V01N0001\narc: S1_V02S0601 N1_V01S0000\narc: V00B0000 V02S0001\narc: V00T0000 S1_V02N0601\narc: V00T0100 V02N0501\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V02N0301\narc: E3_H06E0003 W3_H06E0303\narc: A0 W1_H02E0701\narc: A1 W1_H02E0701\narc: A4 V00T0000\narc: A7 H00R0000\narc: B0 H02E0301\narc: B1 H02E0301\narc: B4 S1_V02N0501\narc: B5 V01S0000\narc: B7 S1_V02N0501\narc: C0 H00L0000\narc: C1 H00L0000\narc: C4 V00B0100\narc: C5 V02N0201\narc: C7 V00B0100\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 V02S0201\narc: D4 V02N0401\narc: D5 E1_H01W0100\narc: D7 V02N0401\narc: E1_H01E0001 F6\narc: E1_H01E0101 F0\narc: E1_H02E0401 F6\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: LSR1 H02W0301\narc: M0 E1_H02W0601\narc: M2 V00T0100\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F4\narc: V00B0100 F5\narc: V01S0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 1100001100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 1100010001000100\nword: SLICEA.K1.INIT 0011101110111011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R17C25:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0401 V02N0401\narc: E3_H06E0203 H01E0001\narc: E3_H06E0303 V06N0303\narc: H00L0000 S1_V02N0001\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H06E0303\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0001\narc: V00B0100 H02W0501\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0701\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 E1_H01W0100\narc: H01W0100 W3_H06E0303\narc: N1_V02N0301 W3_H06E0003\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0203 E3_H06W0103\narc: A1 E1_H01E0001\narc: A7 Q7\narc: B1 V00T0000\narc: B2 W1_H02E0101\narc: B6 V02N0501\narc: B7 V02N0501\narc: C1 H00L0000\narc: C2 H00L0100\narc: C3 H02E0401\narc: C6 S1_V02N0001\narc: C7 S1_V02N0001\narc: CE0 V02S0201\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D2 V00B0100\narc: D3 V00T0100\narc: D6 V00B0000\narc: D7 V00B0000\narc: E1_H01E0001 Q1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q7\narc: N1_V02N0101 F3\narc: N3_V06N0003 F3\narc: V01S0000 Q1\narc: V01S0100 Q6\narc: W1_H02W0001 F2\narc: W3_H06W0103 F2\nword: SLICED.K0.INIT 1111001100110011\nword: SLICED.K1.INIT 1111100110011001\nword: SLICEB.K0.INIT 1111001100110011\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111100110011001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R17C26:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 N1_V01S0100\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 H06E0303\narc: V00B0000 W1_H02E0601\narc: V00B0100 V02S0301\narc: W1_H02W0201 V02N0201\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A4 F5\narc: B2 V02S0101\narc: B3 H00L0000\narc: B4 H02E0101\narc: B5 N1_V01S0000\narc: B7 V02S0701\narc: C2 H02E0401\narc: C3 V02N0401\narc: C4 V00B0100\narc: C5 V02S0001\narc: C7 V00B0100\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 H00R0000\narc: D3 W1_H02E0201\narc: D4 V00B0000\narc: D5 V02S0401\narc: D7 E1_H02W0001\narc: E1_H02E0701 F5\narc: E3_H06E0003 F3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 F3\narc: H01W0100 F4\narc: MUXCLK1 CLK0\narc: N1_V01N0101 F5\narc: N1_V02N0501 F7\narc: S3_V06S0003 F3\narc: W3_H06W0003 F3\nword: SLICEB.K0.INIT 1111001111000000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 0100000000000000\nword: SLICEC.K1.INIT 0000001100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111001111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R17C27:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 W1_H02E0001\narc: H00L0100 V02N0101\narc: H00R0100 V02N0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 H02E0701\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N1_V02S0001\narc: V00B0000 V02N0001\narc: V00B0100 H02E0501\narc: V00T0000 E1_H02W0201\narc: V01S0000 S3_V06N0103\narc: W1_H02W0301 V02N0301\narc: H01W0100 W3_H06E0303\narc: S1_V02S0401 W3_H06E0203\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0303 E3_H06W0303\narc: A4 F5\narc: A7 H02W0501\narc: B1 H02W0301\narc: B4 H00L0000\narc: B5 S1_V02N0501\narc: B7 V00B0000\narc: C1 H00R0100\narc: C4 V01N0101\narc: C5 V02N0001\narc: C7 S1_V02N0001\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 H02W0001\narc: D4 H02E0001\narc: D5 V02N0601\narc: D7 V01N0001\narc: E1_H01E0001 F6\narc: E1_H01E0101 F5\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q2\narc: LSR1 V00T0100\narc: M2 V00T0000\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F6\narc: N1_V01N0101 Q2\narc: N1_V02N0401 F6\narc: N3_V06N0303 F5\narc: V00T0100 F1\narc: V01S0100 Q2\narc: W1_H02W0201 Q2\narc: W3_H06W0203 F4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111111100\nword: SLICEC.K0.INIT 0000010000000000\nword: SLICEC.K1.INIT 0000001100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000001000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R17C28:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 V01N0001\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0303 V01N0101\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02E0601\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H01E0001\narc: N1_V02N0701 H06E0203\narc: S1_V02S0101 H01E0101\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 V02N0001\narc: V00B0100 S1_V02N0301\narc: W1_H02W0001 V02N0001\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 V06S0303\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: B2 H00R0000\narc: B3 Q3\narc: B4 V02N0701\narc: B5 V02N0701\narc: B7 V00B0000\narc: C2 H00L0100\narc: C3 N1_V01S0100\narc: C4 V00B0100\narc: C5 E1_H01E0101\narc: C7 V00B0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 N1_V02S0201\narc: D3 N1_V01S0000\narc: D4 N1_V02S0401\narc: D5 N1_V02S0601\narc: D6 V02S0401\narc: D7 N1_V02S0401\narc: E1_H01E0101 Q6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 Q5\narc: H01W0000 Q3\narc: H01W0100 F7\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N1_V02N0201 F2\narc: N1_V02N0601 Q6\narc: V01S0000 F4\narc: V01S0100 Q5\narc: W1_H02W0501 Q5\narc: W1_H02W0701 Q5\nword: SLICEC.K0.INIT 1111001100110011\nword: SLICEC.K1.INIT 1100110011111100\nword: SLICEB.K0.INIT 1111001100110011\nword: SLICEB.K1.INIT 1100111111001100\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 1111110011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R17C29:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E3_H06E0003 S3_V06N0003\narc: N3_V06N0003 S3_V06N0303\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 H02W0601\narc: V00T0100 V02S0701\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 E3_H06W0003\narc: H01W0100 W3_H06E0303\narc: N1_V02N0301 W3_H06E0003\narc: S3_V06S0303 W3_H06E0303\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0303 E3_H06W0303\narc: B1 H00R0100\narc: C1 H00L0100\narc: C7 V00B0100\narc: CE0 H02E0101\narc: CE2 H02W0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 Q0\narc: D1 V01S0100\narc: D7 H01W0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: H00R0100 Q7\narc: H01W0000 Q0\narc: LSR1 V00B0000\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N3_V06N0203 Q4\narc: S1_V02S0301 Q1\narc: S1_V02S0401 Q4\narc: S3_V06S0203 Q7\narc: V00B0100 Q7\narc: V01S0100 Q0\narc: W1_H02W0501 Q7\narc: W3_H06W0103 Q1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0011110011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R17C2:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 E1_H01W0100\narc: S1_V02S0201 V01N0001\narc: S3_V06S0103 N3_V06S0103\n\n.tile R17C30:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0701 S3_V06N0203\narc: E3_H06E0203 V01N0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 V02N0001\narc: V00B0100 N1_V02S0301\narc: V00T0100 H02W0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0601 S1_V02N0601\narc: S1_V02S0001 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: A4 S1_V02N0301\narc: A5 H02W0501\narc: A6 E1_H02W0501\narc: A7 H00L0000\narc: B4 V00B0100\narc: B5 H02E0301\narc: B6 V00B0000\narc: B7 V00T0000\narc: C4 E1_H01E0101\narc: C5 W1_H02E0401\narc: C6 V00T0100\narc: C7 V02N0201\narc: CE0 H00R0000\narc: CE1 H02E0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D4 H00L0100\narc: D5 V02N0601\narc: D6 H01W0000\narc: D7 V01N0001\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F5\narc: E3_H06E0003 Q0\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0000 F7\narc: M0 W1_H02E0601\narc: M2 H02W0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0203 F4\narc: S1_V02S0401 Q6\narc: S3_V06S0303 Q6\narc: V00T0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111010100110001\nword: SLICEC.K1.INIT 0111000000000000\nword: SLICED.K0.INIT 1010000010100011\nword: SLICED.K1.INIT 0101111100110011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R17C31:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V02S0601\narc: H00L0000 N1_V02S0001\narc: H00L0100 V02N0301\narc: H00R0000 V02N0601\narc: H00R0100 V02S0501\narc: N1_V02N0201 H02E0201\narc: N1_V02N0601 H06E0303\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N3_V06S0003\narc: S3_V06S0203 N1_V02S0401\narc: V00B0000 E1_H02W0601\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 H01E0001\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A3 H00L0100\narc: B3 H02W0101\narc: C3 H00L0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 E1_H02W0601\narc: M1 H00R0100\narc: M2 E1_H02W0601\narc: M3 W1_H02E0201\narc: M4 V00B0000\narc: M5 H00R0100\narc: M6 V00B0000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111111101000101\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R17C32:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 V02N0601\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 H02E0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 S1_V02N0601\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 S1_V02N0201\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H01E0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 H06W0203\narc: V00B0100 E1_H02W0501\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 S1_V02N0701\narc: S3_V06S0003 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: A0 H02E0501\narc: A3 V02N0501\narc: A5 V00T0100\narc: A6 V02N0101\narc: B0 E1_H02W0301\narc: B3 H00R0100\narc: B5 H00L0000\narc: B6 W1_H02E0101\narc: B7 V02N0701\narc: C0 H02W0401\narc: C1 E1_H02W0601\narc: C3 V02S0401\narc: C4 V00T0100\narc: C5 S1_V02N0001\narc: C6 V00T0000\narc: C7 S1_V02N0201\narc: CLK0 G_HPBX0000\narc: D0 N1_V02S0201\narc: D1 V00B0100\narc: D3 H00R0000\narc: D4 H02E0201\narc: D5 H01W0000\narc: D6 H00L0100\narc: D7 V02S0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0000 F6\narc: H01W0100 Q0\narc: LSR1 H02W0301\narc: M2 H02E0601\narc: M4 E1_H01E0101\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0001 F6\narc: N1_V01N0101 F2\narc: V01S0000 F4\narc: W3_H06W0003 Q0\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000001\nword: SLICED.K1.INIT 0000000000000011\nword: SLICEA.K0.INIT 1001101010101010\nword: SLICEA.K1.INIT 0000000011110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111111110000000\nword: SLICEC.K0.INIT 1111111111110000\nword: SLICEC.K1.INIT 0010000000100010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R17C33:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 N1_V02S0501\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 N1_V02S0201\narc: H00R0000 N1_V02S0401\narc: H00R0100 H02W0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0701 H06W0203\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0601\narc: V00B0100 V02N0101\narc: V00T0000 V02S0401\narc: V00T0100 V02N0701\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 N1_V01S0100\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0303 E3_H06W0203\narc: A2 V00T0000\narc: A4 V02N0301\narc: A6 V02N0301\narc: B2 V02N0101\narc: B4 V01S0000\narc: B6 V02N0701\narc: C2 E1_H01W0000\narc: C4 H02W0601\narc: C6 H02W0601\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D2 H00R0000\narc: D4 H00R0100\narc: D5 V00B0000\narc: D6 H00R0100\narc: E1_H02E0401 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 F1\narc: H01W0100 F1\narc: LSR1 E1_H02W0301\narc: M0 E1_H02W0601\narc: M1 H00L0000\narc: M2 E1_H02W0601\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: S1_V02S0401 Q4\narc: S1_V02S0601 Q6\narc: V01S0000 Q4\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0110001000100010\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 0001110100001101\nword: SLICED.K1.INIT 1111111111111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111111110110011\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R17C34:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0203 V06N0203\narc: H00R0000 N1_V02S0601\narc: H00R0100 V02S0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 V02S0001\narc: V00B0100 H02E0501\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02N0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V06N0203\narc: H01W0000 W3_H06E0103\narc: W3_H06W0003 N3_V06S0003\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: A5 E1_H02W0501\narc: B0 H02E0301\narc: B1 V02N0301\narc: B5 V02S0701\narc: B7 N1_V02S0701\narc: C0 H02E0401\narc: C1 H00L0000\narc: C5 V00T0000\narc: C6 E1_H01E0101\narc: C7 V02N0201\narc: CE0 H00R0000\narc: CE1 S1_V02N0201\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 V00B0100\narc: D5 V00B0000\narc: D6 V02N0401\narc: D7 H00R0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H01W0100 Q2\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V02N0201 Q0\narc: N1_V02N0501 F7\narc: N3_V06N0003 F0\narc: S1_V02S0501 F5\narc: S3_V06S0003 F0\narc: S3_V06S0303 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000010000\nword: SLICED.K0.INIT 0000111100000000\nword: SLICED.K1.INIT 0000001100110011\nword: SLICEA.K0.INIT 0000000000110000\nword: SLICEA.K1.INIT 0000000011111100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R17C35:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 V01N0001\narc: E3_H06E0303 N3_V06S0303\narc: H00R0100 H02E0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 N1_V02S0401\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N3_V06S0203\narc: V00B0100 S1_V02N0101\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 H01E0001\narc: E1_H02E0001 W3_H06E0003\narc: S1_V02S0201 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: B0 E1_H01W0100\narc: B1 V00B0000\narc: C0 H00L0100\narc: C1 N1_V01N0001\narc: C2 H00R0100\narc: C3 H00L0000\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 V02N0001\narc: D2 H00R0000\narc: D3 V02S0201\narc: E1_H01E0001 F2\narc: E1_H01E0101 Q6\narc: E1_H02E0401 Q4\narc: E3_H06E0103 Q1\narc: E3_H06E0203 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H00L0000 F2\narc: H00L0100 F1\narc: H00R0000 Q4\narc: H01W0000 Q3\narc: H01W0100 Q6\narc: M4 H02E0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q4\narc: N1_V02N0401 Q6\narc: N3_V06N0003 F0\narc: S1_V02S0601 Q4\narc: S3_V06S0303 Q6\narc: V00B0000 Q6\narc: V01S0000 F1\narc: V01S0100 Q6\narc: W1_H02W0201 F2\narc: W3_H06W0103 F2\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0000000011110000\nword: SLICEA.K0.INIT 1100000000000000\nword: SLICEA.K1.INIT 0000000000110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R17C36:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 V06N0203\narc: E1_H02E0501 V02N0501\narc: E3_H06E0303 H01E0101\narc: H00R0000 V02S0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 N1_V01S0000\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H02E0401\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02E0401\narc: V00B0100 H02E0501\narc: V00T0000 H02E0001\narc: V00T0100 W1_H02E0301\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0501 H01E0101\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0701 W3_H06E0203\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0103 V01N0101\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\narc: A6 H02W0501\narc: A7 V02S0101\narc: B5 H00L0000\narc: B6 V00B0100\narc: B7 W1_H02E0101\narc: C5 V00T0100\narc: C6 H02E0601\narc: C7 S1_V02N0001\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: D6 H00R0100\narc: D7 H02E0201\narc: E1_H01E0001 Q0\narc: E1_H02E0601 F6\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: E3_H06E0203 F7\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0000 F7\narc: H01W0100 Q0\narc: M0 V00T0000\narc: M2 W1_H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q7\narc: N1_V01N0101 Q0\narc: N1_V02N0001 Q0\narc: N1_V02N0701 F7\narc: N3_V06N0203 F7\narc: S1_V02S0001 Q2\narc: S1_V02S0201 Q0\narc: S1_V02S0701 F5\narc: S3_V06S0203 F7\narc: V01S0100 Q2\narc: W1_H02W0001 Q0\narc: W1_H02W0701 F7\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000110000000000\nword: SLICED.K0.INIT 0100010101000100\nword: SLICED.K1.INIT 0111000000110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R17C37:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0401 V06N0203\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 W1_H02E0701\narc: H00L0000 H02E0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 N1_V02S0601\narc: H00R0100 H02E0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 E1_H02W0601\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02S0601\narc: V01S0000 N3_V06S0103\narc: W1_H02W0501 E1_H02W0401\narc: E1_H01E0001 W3_H06E0003\narc: W3_H06W0103 N3_V06S0103\narc: A1 H00R0000\narc: A3 H02E0501\narc: A5 H02E0501\narc: A6 E1_H02W0701\narc: B1 W1_H02E0301\narc: B3 H02E0301\narc: B5 H00L0000\narc: B6 V00B0100\narc: B7 V00T0000\narc: C1 H00L0100\narc: C3 W1_H02E0401\narc: C5 V02S0001\narc: C6 E1_H01E0101\narc: C7 H02E0401\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D1 H01E0101\narc: D3 H02E0001\narc: D5 V00B0000\narc: D6 H01W0000\narc: D7 H00R0100\narc: E1_H01E0101 F7\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: S1_V02S0301 F3\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000001010100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111100011111010\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000001100000001\nword: SLICED.K0.INIT 1011000010111011\nword: SLICED.K1.INIT 1100000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R17C38:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V01N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 V01N0001\narc: E3_H06E0303 W1_H02E0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H01E0001\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0701 H06E0203\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02S0201\narc: V00B0100 H02W0501\narc: V00T0100 V02N0501\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0701 E1_H01W0100\narc: N3_V06N0103 W3_H06E0103\narc: S3_V06S0003 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0103 W3_H06E0003\narc: A5 H02E0501\narc: B3 H00L0000\narc: B5 V00B0100\narc: C3 S1_V02N0601\narc: C5 S1_V02N0201\narc: CE0 H00R0100\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D5 H02E0201\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H00L0000 Q0\narc: M0 V00B0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q6\narc: N3_V06N0003 F3\narc: S1_V02S0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000010101010\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0011001100001111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R17C39:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0601 S3_V06N0303\narc: E3_H06E0303 W1_H02E0501\narc: H00L0100 H02E0101\narc: H00R0000 S1_V02N0401\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 H06W0003\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 E1_H01W0100\narc: V00T0000 V02N0401\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E1_H02W0601\narc: E1_H01E0001 W3_H06E0003\narc: H01W0100 W3_H06E0303\narc: N1_V02N0501 W3_H06E0303\narc: N3_V06N0203 W3_H06E0203\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0203 V06S0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: A1 V02S0701\narc: A3 H00L0100\narc: A4 V00T0000\narc: A7 H00R0000\narc: B1 V02N0301\narc: B3 E1_H02W0301\narc: B4 H02E0301\narc: B5 H02E0101\narc: B7 V00T0000\narc: C0 N1_V01S0100\narc: C1 W1_H02E0601\narc: C3 H00L0000\narc: C4 V01N0101\narc: C5 H02E0401\narc: C7 S1_V02N0201\narc: D0 H02W0201\narc: D1 S1_V02N0001\narc: D3 V00B0100\narc: D4 H00R0100\narc: D5 F0\narc: D7 H02E0201\narc: E1_H01E0101 F2\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H00R0100 F5\narc: M2 V00T0100\narc: S1_V02S0201 F2\narc: V00B0100 F7\narc: V00T0100 F1\narc: V01S0000 F4\narc: W1_H02W0001 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000001001000001\nword: SLICEC.K0.INIT 1001000000000000\nword: SLICEC.K1.INIT 1100001100000000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 1000010000100001\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1001000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R17C3:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V01N0001\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02S0301\narc: H00R0000 V02S0601\narc: H00R0100 V02S0501\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0601 H01E0001\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0303 H06W0303\narc: V00B0000 H02W0401\narc: V00B0100 H02W0701\narc: V00T0000 H02E0201\narc: A1 H00L0000\narc: A3 V01N0101\narc: A6 V00T0100\narc: A7 H02E0701\narc: B1 V01N0001\narc: B3 W1_H02E0301\narc: B6 F3\narc: B7 V00B0000\narc: C1 H00R0100\narc: C3 H00L0100\narc: C6 V00B0100\narc: C7 V02S0001\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 V02S0201\narc: D3 H00R0000\narc: D6 H01W0000\narc: D7 V02S0401\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q4\narc: LSR1 H02E0501\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: V00T0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R17C40:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 S3_V06N0203\narc: H00R0000 E1_H02W0401\narc: H00R0100 H02W0701\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0301 H01E0101\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H02W0701\narc: V00B0000 V02N0201\narc: V00B0100 W1_H02E0701\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02S0701\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0701 N3_V06S0203\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: B0 V00B0000\narc: B2 H02E0101\narc: B3 V02S0301\narc: B4 H02W0101\narc: C0 H00L0100\narc: C2 W1_H02E0601\narc: C3 N1_V01S0100\narc: C4 H02W0401\narc: CE1 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 F2\narc: D2 H02W0001\narc: D3 H02E0001\narc: D4 H00R0100\narc: D5 F2\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q2\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: H00L0100 F3\narc: H01W0100 Q6\narc: LSR1 E1_H02W0301\narc: M0 V00T0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q6\narc: S3_V06S0003 F0\narc: S3_V06S0203 F4\narc: V01S0000 Q6\narc: V01S0100 Q6\narc: W3_H06W0103 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100000011001111\nword: SLICEB.K1.INIT 1100110000001111\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 0000001111001111\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R17C41:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V02N0501\narc: E3_H06E0003 H01E0001\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 V02S0001\narc: H00L0100 V02N0101\narc: H00R0000 W1_H02E0601\narc: H00R0100 H02W0701\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 W1_H02E0601\narc: V00B0100 H02E0701\narc: V00T0000 E1_H02W0001\narc: V00T0100 W1_H02E0301\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 V06N0103\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 V01N0101\narc: E1_H02E0601 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: S3_V06S0103 W3_H06E0103\narc: S3_V06S0203 W3_H06E0203\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0003 N3_V06S0003\narc: W3_H06W0203 E3_H06W0103\narc: A3 H00L0100\narc: A7 V02N0101\narc: B0 V01N0001\narc: B3 H00R0000\narc: B4 H02W0101\narc: B5 H02E0301\narc: B7 V00B0000\narc: C0 V02N0601\narc: C2 H00L0100\narc: C3 H00L0000\narc: C4 H02E0601\narc: C5 E1_H01E0101\narc: C6 V00T0100\narc: C7 V02S0001\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 H02W0001\narc: D2 E1_H02W0201\narc: D3 E1_H02W0201\narc: D4 H01W0000\narc: D5 V02S0601\narc: D6 S1_V02N0401\narc: D7 S1_V02N0401\narc: E1_H01E0101 F0\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: LSR0 H02W0301\narc: M0 V00T0000\narc: M2 V00B0100\narc: M6 H02E0401\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0001 F4\narc: N1_V01N0101 F5\narc: V01S0100 Q4\narc: W1_H02W0001 F2\narc: W1_H02W0601 Q4\nword: SLICEC.K0.INIT 1100000011001111\nword: SLICEC.K1.INIT 0000001111001111\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 1010100000000000\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 1010100000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R17C42:PLC2\narc: E1_H02E0401 V02N0401\narc: E1_H02E0701 V02N0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 H02E0201\narc: H00L0100 V02S0101\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02E0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 H02W0601\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02W0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 S3_V06N0003\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0701 W3_H06E0203\narc: N3_V06N0203 W3_H06E0203\narc: S3_V06S0003 W3_H06E0003\narc: S3_V06S0103 W3_H06E0103\narc: S3_V06S0203 W3_H06E0203\narc: W1_H02W0401 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0003 N3_V06S0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: B0 H02E0301\narc: B2 E1_H02W0101\narc: B4 H02W0301\narc: B6 V02S0501\narc: C0 H00L0000\narc: C2 E1_H02W0401\narc: C4 E1_H02W0601\narc: C6 V02S0201\narc: CE0 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 V02N0201\narc: D2 V02S0001\narc: D3 V00T0100\narc: D4 S1_V02N0401\narc: D5 H00R0100\narc: D6 E1_H02W0001\narc: D7 H01W0000\narc: E1_H01E0001 F0\narc: E1_H01E0101 F0\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q0\narc: H01W0100 F6\narc: M0 V00B0100\narc: M2 H02W0601\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: N1_V01N0101 Q0\narc: S1_V02S0401 F4\narc: V01S0000 F2\narc: V01S0100 F0\narc: W1_H02W0201 F0\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 0011001100001111\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000111100110011\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000110011111100\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R17C43:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 V02S0701\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 W1_H02E0001\narc: H00L0100 E1_H02W0101\narc: H00R0000 V02N0401\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 H02W0201\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 S3_V06N0303\narc: W3_H06W0003 S3_V06N0003\narc: A0 V02N0501\narc: A1 H00R0000\narc: A2 V02N0501\narc: A3 V02N0501\narc: A4 W1_H02E0501\narc: A5 V00B0000\narc: B0 V02N0301\narc: B1 V02N0301\narc: B2 V02N0301\narc: B3 V02N0301\narc: B4 H00L0000\narc: B5 V00B0100\narc: B6 V02N0701\narc: C0 E1_H02W0601\narc: C1 E1_H02W0601\narc: C2 E1_H02W0601\narc: C3 E1_H02W0601\narc: C4 V00T0100\narc: C5 N1_V02S0001\narc: C6 W1_H02E0401\narc: CLK1 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02N0001\narc: D2 V02N0001\narc: D3 V02N0001\narc: D4 H00L0100\narc: D5 V02S0601\narc: D6 V02S0601\narc: D7 N1_V02S0401\narc: E1_H01E0101 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q0\narc: LSR1 H02W0501\narc: M6 V00T0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0101 Q1\narc: N1_V02N0001 Q2\narc: W1_H02W0301 Q3\nword: SLICED.K0.INIT 1111110000001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R17C44:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 W1_H02E0401\narc: H00L0000 H02E0001\narc: H00L0100 H02E0101\narc: H00R0000 S1_V02N0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 H01E0101\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02E0601\narc: V00B0100 W1_H02E0701\narc: V00T0100 H02W0301\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 V01N0001\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0401 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: N1_V02N0001 W3_H06E0003\narc: S1_V02S0101 W3_H06E0103\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0003 N3_V06S0003\narc: W3_H06W0303 S3_V06N0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A0 H02E0701\narc: A1 H02E0701\narc: A2 H02E0701\narc: A3 H02E0701\narc: A4 V00T0100\narc: A5 H02E0501\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 H00L0000\narc: B5 S1_V02N0701\narc: B6 V00T0000\narc: C0 H02W0401\narc: C1 H02W0401\narc: C2 H02W0401\narc: C3 H02W0401\narc: C4 H02E0401\narc: C5 N1_V02S0201\narc: C6 V02S0201\narc: CLK1 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 S1_V02N0401\narc: D5 H00L0100\narc: D6 V02S0601\narc: D7 H02E0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q0\narc: LSR1 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0101 Q1\narc: V00T0000 Q2\narc: V01S0100 F6\narc: W1_H02W0101 Q3\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R17C45:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 V02S0101\narc: H00R0000 N1_V02S0401\narc: H00R0100 H02W0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 V01N0001\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 H02W0601\narc: V00B0100 E1_H02W0701\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0601 S1_V02N0601\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0101 W3_H06E0103\narc: S3_V06S0103 W3_H06E0103\narc: W3_H06W0103 N1_V01S0100\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: A0 V02N0501\narc: A1 V02N0501\narc: A2 V02N0501\narc: A3 V02N0501\narc: A4 S1_V02N0301\narc: A5 H02W0701\narc: B0 V00T0000\narc: B1 V00T0000\narc: B2 H00R0000\narc: B3 H00R0000\narc: B4 E1_H02W0301\narc: B5 E1_H02W0101\narc: B6 V01S0000\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 N1_V02S0201\narc: C5 N1_V02S0001\narc: C6 V01N0101\narc: CLK1 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 V00T0100\narc: D3 V00T0100\narc: D4 E1_H02W0201\narc: D5 H02W0201\narc: D6 H00R0100\narc: D7 V00B0000\narc: E1_H01E0101 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F6\narc: LSR1 H02E0501\narc: M6 V00B0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V02N0201 Q0\narc: N1_V02N0301 Q1\narc: V01S0000 Q3\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R17C46:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 V01N0001\narc: E3_H06E0003 H01E0001\narc: E3_H06E0203 V06N0203\narc: E3_H06E0303 V06N0303\narc: H00L0100 E1_H02W0301\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H02W0601\narc: N3_V06N0003 H06W0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 H02E0401\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0501\narc: V00T0000 H02E0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 E1_H01W0100\narc: E1_H01E0101 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0501 W3_H06E0303\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A0 S1_V02N0701\narc: A1 S1_V02N0701\narc: A2 S1_V02N0701\narc: A3 S1_V02N0701\narc: A4 S1_V02N0301\narc: A5 E1_H02W0501\narc: B0 W1_H02E0301\narc: B1 W1_H02E0301\narc: B2 W1_H02E0301\narc: B3 W1_H02E0301\narc: B4 V00B0100\narc: B5 H02W0101\narc: B6 V01S0000\narc: C0 V02N0601\narc: C1 V02N0601\narc: C2 V02N0601\narc: C3 V02N0601\narc: C4 V00T0100\narc: C5 V00T0000\narc: C6 V01N0101\narc: CLK1 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 S1_V02N0001\narc: D2 S1_V02N0001\narc: D3 S1_V02N0201\narc: D4 H02W0201\narc: D5 H00R0100\narc: D6 V02N0401\narc: D7 H00L0100\narc: E1_H01E0001 F6\narc: E1_H02E0101 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q0\narc: LSR1 H02E0301\narc: M6 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: V01S0000 Q3\narc: V01S0100 Q2\nword: SLICED.K0.INIT 0011001100001111\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R17C47:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0701 V02S0701\narc: H00L0100 V02S0301\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0401\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 H06E0003\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00T0000 H02E0001\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 E1_H02W0601\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0103 N1_V01S0100\narc: W3_H06W0203 E1_H01W0000\narc: A3 H00L0100\narc: B3 H02W0101\narc: B4 H02E0101\narc: B6 W1_H02E0101\narc: C3 N1_V02S0401\narc: C4 H02E0601\narc: C6 H01E0001\narc: CE0 V02S0201\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 H02E0201\narc: D4 S1_V02N0601\narc: D5 H01W0000\narc: D6 E1_H01W0100\narc: D7 V02N0601\narc: E1_H01E0101 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q1\narc: H01W0100 F1\narc: M0 V00B0000\narc: M1 H02W0001\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: N1_V02N0401 F4\narc: S3_V06S0303 F6\narc: V01S0000 F1\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0011001100001111\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1100111100000011\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000110010001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R17C48:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02N0601\narc: H00L0000 V02N0001\narc: H00L0100 E1_H02W0301\narc: H00R0100 V02S0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 S1_V02N0501\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 V01N0101\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 S1_V02N0201\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02W0301\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 N3_V06S0303\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0601 W3_H06E0303\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0001 W3_H06E0003\narc: S1_V02S0401 W3_H06E0203\narc: S1_V02S0601 W3_H06E0303\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A3 V02S0501\narc: A7 H00L0000\narc: B3 H02W0301\narc: B4 N1_V02S0701\narc: B5 H00R0000\narc: B7 H02E0101\narc: C3 H00R0100\narc: C4 V02S0001\narc: C5 V00T0000\narc: C7 E1_H02W0401\narc: CE0 V02S0201\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 H02E0201\narc: D4 V02S0601\narc: D5 N1_V02S0601\narc: D7 H00L0100\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0000 F1\narc: H01W0100 F1\narc: M0 V00B0000\narc: M1 H02W0001\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N3_V06N0203 Q4\narc: S1_V02S0501 F7\narc: V01S0100 F1\narc: W1_H02W0301 Q1\narc: W1_H02W0701 F5\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000001\nword: SLICEC.K0.INIT 1100111111000000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000100011001100\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R17C49:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 H01E0001\narc: E1_H02E0601 V02S0601\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 N1_V02S0001\narc: H00R0000 H02E0601\narc: H00R0100 H02W0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 S3_V06N0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 V01N0001\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 H02W0701\narc: V00T0100 V02S0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 V02N0301\narc: N1_V02N0701 W3_H06E0203\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 N3_V06S0303\narc: A1 E1_H01E0001\narc: A5 H02W0701\narc: B1 H00R0100\narc: B2 V02S0101\narc: B3 H01W0100\narc: B5 S1_V02N0501\narc: B6 S1_V02N0701\narc: C0 N1_V02S0601\narc: C1 E1_H02W0401\narc: C2 V02S0601\narc: C3 H00L0000\narc: C5 H02W0401\narc: C6 V00T0100\narc: CE1 H00R0000\narc: CE2 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 V02S0001\narc: D2 S1_V02N0201\narc: D3 H02W0201\narc: D5 S1_V02N0601\narc: D6 E1_H02W0201\narc: D7 V02N0601\narc: E1_H01E0001 F0\narc: E1_H01E0101 F0\narc: E1_H02E0001 F0\narc: E1_H02E0401 Q6\narc: E3_H06E0003 F0\narc: E3_H06E0303 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F1\narc: H01W0100 Q2\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0201 F0\narc: N3_V06N0103 Q2\narc: S1_V02S0201 F0\narc: V01S0000 F3\narc: W3_H06W0003 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100110011011000\nword: SLICEA.K0.INIT 0000000000001111\nword: SLICEA.K1.INIT 1101000010000000\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1111110000001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R17C4:PLC2\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V02S0701\narc: H00L0000 V02S0001\narc: H00R0100 V02N0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 E3_H06W0203\narc: S1_V02S0101 V01N0101\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: V00B0100 V02S0101\narc: V00T0100 V02N0701\narc: V01S0100 N3_V06S0303\narc: W3_H06W0003 N3_V06S0003\narc: A5 E1_H01W0000\narc: B5 V02S0501\narc: C5 N1_V02S0201\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D5 H02E0201\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: F5 F5_SLICE\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 H02E0601\narc: M2 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q2\narc: V00B0000 Q6\narc: W1_H02W0401 Q6\narc: W1_H02W0701 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R17C50:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 W1_H02E0601\narc: H00L0100 V02S0301\narc: H00R0000 W1_H02E0601\narc: H00R0100 V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 V01N0001\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 H06W0103\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02W0701\narc: V00T0000 V02N0401\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V06N0303\narc: W1_H02W0701 V02N0701\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: B0 H02E0101\narc: B1 H01W0100\narc: B2 V02S0101\narc: B3 H00L0000\narc: B4 V02N0701\narc: B6 N1_V02S0701\narc: B7 V01S0000\narc: C0 H00L0100\narc: C1 V02S0601\narc: C2 H00L0100\narc: C3 H00R0100\narc: C4 V02N0001\narc: C5 V00T0000\narc: C6 V02S0001\narc: C7 E1_H02W0401\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H02W0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 N1_V02S0201\narc: D2 V00B0100\narc: D3 N1_V02S0201\narc: D4 V02N0401\narc: D5 H02W0001\narc: D6 V02S0401\narc: D7 V00B0000\narc: E3_H06E0003 F3\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 Q2\narc: H01W0100 Q0\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V02N0401 Q6\narc: N3_V06N0003 Q0\narc: N3_V06N0103 Q2\narc: S1_V02S0501 F5\narc: V01S0000 Q6\narc: V01S0100 F7\narc: W3_H06W0003 Q0\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1100111111000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 0000111111110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R17C51:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0003 N1_V01S0000\narc: H00L0100 H02W0301\narc: H00R0000 H02E0601\narc: H00R0100 H02W0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 H06E0203\narc: V00B0100 V02S0101\narc: V00T0100 V02S0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0701 V02N0701\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0003 S3_V06N0003\narc: E3_H06E0103 W3_H06E0003\narc: B0 H00R0100\narc: B1 V00T0000\narc: B2 V02S0301\narc: B3 H00L0000\narc: B4 E1_H02W0301\narc: B5 V01S0000\narc: B6 N1_V02S0701\narc: B7 V00B0000\narc: C0 W1_H02E0601\narc: C1 H00L0100\narc: C2 W1_H02E0601\narc: C3 V02N0401\narc: C4 V02S0001\narc: C5 V00B0100\narc: C6 V02S0001\narc: C7 V02S0201\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 H02W0201\narc: D2 H02E0201\narc: D3 H02W0201\narc: D4 E1_H02W0001\narc: D5 H02W0201\narc: D6 V02N0601\narc: D7 H02W0201\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q2\narc: E1_H02E0201 Q0\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: S1_V02S0701 F7\narc: S3_V06S0303 F5\narc: V00B0000 Q6\narc: V00T0000 Q0\narc: V01S0000 Q4\narc: V01S0100 F3\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1100111111000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 1100111111000000\nword: SLICEC.K1.INIT 1111000011001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R17C52:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 N3_V06S0003\narc: E3_H06E0303 H01E0101\narc: H00L0000 V02S0001\narc: H00L0100 V02N0101\narc: H00R0000 W1_H02E0601\narc: H00R0100 S1_V02N0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 H06W0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 H01E0101\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N1_V02S0101\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 H01E0001\narc: V00B0000 V02S0201\narc: V00T0100 V02N0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V06S0203\narc: W1_H02W0701 V02S0701\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0601 W3_H06E0303\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0303 N3_V06S0303\narc: B2 H00L0000\narc: B3 H01W0100\narc: B4 N1_V02S0501\narc: B5 V02S0501\narc: C0 E1_H02W0601\narc: C1 H00L0100\narc: C2 H02E0601\narc: C3 V02N0601\narc: C4 H02E0401\narc: C5 N1_V02S0001\narc: C6 E1_H01E0101\narc: C7 V02N0001\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 H02E0001\narc: D2 V00T0100\narc: D3 V02S0201\narc: D4 H00R0100\narc: D5 V00B0000\narc: D6 H02E0001\narc: D7 H02E0001\narc: E1_H02E0001 F0\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q2\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: S1_V02S0501 F5\narc: S1_V02S0601 F6\narc: S1_V02S0701 F7\narc: V01S0100 F3\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 1100111111000000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R17C53:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0103 W1_H02E0201\narc: H00L0000 V02N0201\narc: H00L0100 H02E0301\narc: H00R0100 H02W0701\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 H02E0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 H02E0401\narc: V00T0000 V02N0401\narc: V00T0100 H02W0301\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0301 V02N0301\narc: W1_H02W0701 H01E0101\narc: W3_H06W0103 E1_H01W0100\narc: A1 V02S0701\narc: B1 W1_H02E0101\narc: B2 E1_H02W0301\narc: B4 H00L0000\narc: B5 H00R0000\narc: B6 V00T0000\narc: C1 H02W0401\narc: C2 V02N0401\narc: C3 H00L0100\narc: C4 V02S0001\narc: C5 N1_V02S0001\narc: C6 E1_H02W0401\narc: C7 E1_H02W0401\narc: CE1 H02W0101\narc: CE2 H02E0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: D2 S1_V02N0001\narc: D3 V00T0100\narc: D4 V02N0601\narc: D5 E1_H02W0201\narc: D6 V00B0000\narc: D7 H00R0100\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q2\narc: E3_H06E0203 Q4\narc: E3_H06E0303 F5\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0100 F1\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 F7\narc: N3_V06N0203 Q4\narc: V01S0000 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1011000010000000\nword: SLICED.K0.INIT 1111001111000000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 1100111111000000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 1111110000001100\nword: SLICEB.K1.INIT 0000111111110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R17C54:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0203 W1_H02E0401\narc: H00R0000 H02E0401\narc: H00R0100 V02N0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 W1_H02E0501\narc: V00T0000 S1_V02N0601\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02N0701\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: N1_V02N0301 W3_H06E0003\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: A3 H02E0701\narc: B3 H00R0000\narc: B4 E1_H02W0301\narc: C3 H02E0601\narc: C4 H02E0401\narc: C5 V02N0001\narc: CE0 H02W0101\narc: CE1 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: D4 E1_H02W0001\narc: D5 H00R0100\narc: E1_H01E0001 Q4\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: M0 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: S1_V02S0501 F5\narc: V00T0100 Q3\narc: V01S0100 Q6\narc: W1_H02W0201 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010101110101000\nword: SLICEC.K0.INIT 1111110000001100\nword: SLICEC.K1.INIT 0000111111110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R17C55:PLC2\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 N1_V02S0501\narc: H00L0100 S1_V02N0101\narc: H00R0100 H02E0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H02E0401\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 V01N0101\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H02E0701\narc: S3_V06S0103 H01E0101\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02S0001\narc: V00B0100 W1_H02E0501\narc: V00T0000 W1_H02E0001\narc: V00T0100 H02E0101\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 V02N0501\narc: N1_V02N0501 W3_H06E0303\narc: S3_V06S0003 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0003 E1_H01W0000\narc: CE0 H00L0100\narc: CE1 H00R0100\narc: CE2 H00L0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: H01W0000 Q0\narc: H01W0100 Q2\narc: M0 V00B0000\narc: M2 V00T0100\narc: M4 V00B0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: N1_V02N0601 Q6\narc: V01S0000 Q2\narc: V01S0100 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R17C56:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: H00R0000 W1_H02E0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0501 S3_V06N0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 W1_H02E0501\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 V02N0201\narc: V00T0000 S1_V02N0601\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 N1_V02S0401\narc: S3_V06S0103 W3_H06E0103\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q0\narc: E3_H06E0103 Q2\narc: H01W0000 Q0\narc: H01W0100 Q4\narc: M0 V00T0000\narc: M2 V00B0000\narc: M4 E1_H02W0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q2\narc: N1_V02N0401 Q4\narc: N1_V02N0601 Q6\narc: V01S0000 Q6\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R17C57:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 H01E0001\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 N1_V02S0501\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02E0401\narc: H00R0100 S1_V02N0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 H01E0101\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0201\narc: V00T0000 E1_H02W0001\narc: V00T0100 H02E0301\narc: V01S0100 S3_V06N0303\narc: W1_H02W0301 V01N0101\narc: N1_V02N0101 W3_H06E0103\narc: N3_V06N0203 W3_H06E0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: CE0 H00L0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: N1_V02N0001 Q0\narc: V01S0000 Q4\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R17C58:PLC2\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H02E0501\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S1_V02N0601\narc: V00B0000 E1_H02W0401\narc: V00B0100 V02N0101\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0401 S1_V02N0401\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: N1_V02N0701 W3_H06E0203\narc: S3_V06S0203 W3_H06E0203\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: M2 V00B0000\narc: M4 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R17C59:PLC2\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 H06E0103\narc: N3_V06N0303 S1_V02N0501\narc: S3_V06S0003 H06E0003\narc: W1_H02W0001 V02N0001\narc: N3_V06N0203 W3_H06E0203\narc: S3_V06S0203 W3_H06E0203\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\n\n.tile R17C5:PLC2\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 W1_H02E0401\narc: H00L0000 V02N0001\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N3_V06S0303\narc: V00B0000 H02W0401\narc: V00B0100 H02E0701\narc: V00T0000 E1_H02W0201\narc: V00T0100 E1_H02W0301\narc: A7 N1_V01N0101\narc: B7 V01S0000\narc: C7 V02S0001\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: E1_H01E0001 F7\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q2\narc: N1_V02N0601 Q4\narc: V01S0000 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R17C60:PLC2\narc: N3_V06N0303 S1_V02N0501\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0501 W3_H06E0303\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0203 S3_V06N0203\n\n.tile R17C61:PLC2\narc: N3_V06N0203 H06E0203\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 S1_V02N0201\n\n.tile R17C62:PLC2\narc: N3_V06N0203 H06E0203\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0003 W3_H06E0003\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\n\n.tile R17C63:PLC2\narc: N3_V06N0303 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\n\n.tile R17C64:PLC2\narc: S3_V06S0303 N1_V02S0501\narc: N3_V06N0203 W3_H06E0203\narc: S3_V06S0203 W3_H06E0203\n\n.tile R17C65:PLC2\narc: S3_V06S0103 H06E0103\narc: S3_V06S0303 H06E0303\narc: N3_V06N0203 W3_H06E0203\narc: S3_V06S0203 W3_H06E0203\n\n.tile R17C66:PLC2\narc: S1_V02S0401 H06E0203\narc: S3_V06S0003 H06E0003\narc: S3_V06S0303 H06E0303\n\n.tile R17C69:PLC2\narc: E1_H02E0701 S1_V02N0701\narc: S3_V06S0203 N3_V06S0103\n\n.tile R17C6:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 N3_V06S0203\narc: H00L0000 H02W0001\narc: H00L0100 V02S0301\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0601 H01E0001\narc: V00B0000 H02W0601\narc: V00B0100 H02W0501\narc: V00T0000 V02N0401\narc: V00T0100 V02S0501\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0401 V06S0203\narc: W3_H06W0303 E3_H06W0203\narc: A1 H00L0000\narc: A5 S1_V02N0101\narc: B1 V01N0001\narc: B5 H02E0301\narc: B7 E1_H02W0301\narc: C1 H00L0100\narc: C5 V01N0101\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D5 V00B0000\narc: D7 V02S0401\narc: E1_H01E0001 F7\narc: F0 F5A_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: LSR1 V00T0000\narc: M0 V00T0100\narc: M2 W1_H02E0601\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0101 F5\narc: N1_V02N0201 F0\narc: N3_V06N0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100001100000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R17C70:PLC2\narc: E1_H02E0501 V06S0303\narc: S3_V06S0203 N3_V06S0103\n\n.tile R17C7:PLC2\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0501 V01N0101\narc: H00R0000 V02N0601\narc: H00R0100 V02N0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0201 H06W0103\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02N0001\narc: V00B0100 H02W0701\narc: V00T0000 V02N0401\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 N1_V02S0601\narc: W3_H06W0003 E1_H01W0000\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: H01W0100 Q0\narc: LSR0 E1_H02W0501\narc: LSR1 V00B0000\narc: M0 H02W0601\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q4\narc: V01S0100 Q6\narc: W1_H02W0001 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R17C8:PLC2\narc: E1_H02E0601 V02S0601\narc: H00L0100 H02W0101\narc: H00R0000 H02W0401\narc: H00R0100 V02N0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 V01N0101\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 V02S0701\narc: W3_H06W0003 V06S0003\narc: A1 H00R0000\narc: A7 H02E0501\narc: B1 V01N0001\narc: B7 W1_H02E0301\narc: C1 H00L0100\narc: C7 W1_H02E0601\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D7 H02W0201\narc: E1_H01E0101 Q2\narc: F1 F1_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: H01W0100 F1\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: M2 E1_H02W0601\narc: M4 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000101001000101\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000010000100001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R17C9:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V01N0101\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0303 V01N0101\narc: H00L0100 V02N0101\narc: H00R0100 V02N0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 E3_H06W0003\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02S0101\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V06S0203\narc: W3_H06W0203 V06S0203\narc: CE0 H00L0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q0\narc: E1_H02E0201 Q2\narc: E1_H02E0401 Q6\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00B0000\narc: M2 H02E0601\narc: M4 E1_H01E0101\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: W1_H02W0401 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R18C10:PLC2\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0701 H01E0101\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 H02W0001\narc: H00R0000 V02S0401\narc: H00R0100 W1_H02E0501\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H06W0003\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 V01N0101\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 V02S0601\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0301 W3_H06E0003\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0103 N3_V06S0103\narc: W3_H06W0203 E1_H01W0000\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E3_H06E0003 Q0\narc: H01W0000 Q6\narc: LSR1 V00B0100\narc: M0 H02E0601\narc: M2 H02W0601\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V02N0001 Q2\narc: N1_V02N0401 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R18C11:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0701 S1_V02N0701\narc: H00R0000 V02S0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0701 H02E0701\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 H02W0701\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0101\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0601 E1_H01W0000\narc: E3_H06E0303 W3_H06E0203\narc: CE0 H00R0100\narc: CE1 E1_H02W0101\narc: CE2 H00R0000\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: H01W0000 Q4\narc: H01W0100 Q0\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00B0100\narc: M2 E1_H02W0601\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q4\narc: N1_V02N0001 Q2\narc: N1_V02N0601 Q6\narc: V00T0000 Q0\narc: W3_H06W0103 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R18C12:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 E3_H06W0303\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 N1_V02S0001\narc: H00R0000 V02S0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 H02W0501\narc: V00T0000 H02W0001\narc: V00T0100 V02S0701\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 V06S0203\narc: A7 H00R0000\narc: B7 V01S0000\narc: C7 E1_H02W0601\narc: CE0 H00R0100\narc: CE1 E1_H02W0101\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D7 H02E0001\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q4\narc: F6 F5D_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q2\narc: LSR0 W1_H02E0301\narc: LSR1 W1_H02E0301\narc: M0 V00T0000\narc: M2 V00T0100\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q0\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000001010100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R18C13:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 V01N0001\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 S3_V06N0303\narc: H00L0000 H02W0001\narc: H00R0000 V02S0401\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 H01E0001\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 H06W0003\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00B0100 V02N0301\narc: V00T0000 V02S0601\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0601 E1_H01W0000\narc: H01W0000 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: A4 V02N0101\narc: A7 N1_V01N0101\narc: B4 V00B0100\narc: B5 H02E0101\narc: B7 H01E0101\narc: C4 H02E0401\narc: C5 E1_H02W0601\narc: C7 N1_V02S0001\narc: CE1 H00R0000\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D4 N1_V02S0401\narc: D5 V02N0601\narc: D7 N1_V02S0601\narc: E1_H02E0701 Q5\narc: E3_H06E0203 F4\narc: E3_H06E0303 Q5\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q5\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M2 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q2\narc: N3_V06N0203 F7\narc: N3_V06N0303 Q5\narc: S1_V02S0401 F4\narc: V01S0000 F4\narc: W1_H02W0001 Q2\narc: W1_H02W0501 Q5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 0000110000111100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R18C14:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 V02S0201\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0103 S1_V02N0201\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E1_H01W0100\narc: V00T0000 H02E0001\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V02S0101\narc: W1_H02W0601 E3_H06W0303\narc: H01W0100 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: W1_H02W0501 W3_H06E0303\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: H01W0000 Q6\narc: LSR0 H02E0501\narc: M6 V00T0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R18C15:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V02S0001\narc: E1_H02E0401 N3_V06S0203\narc: E3_H06E0303 V06N0303\narc: H00L0000 N1_V02S0201\narc: H00R0100 W1_H02E0701\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0003 S1_V02N0001\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0103 H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02W0601\narc: V00B0100 H02E0501\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V06S0203\narc: A0 H02E0701\narc: A1 V02N0501\narc: B0 H00R0100\narc: B1 H02E0101\narc: C0 H00L0000\narc: C1 H02E0401\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 V01S0100\narc: E1_H02E0201 Q0\narc: E3_H06E0003 Q0\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: H01W0000 F1\narc: H01W0100 Q0\narc: LSR1 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: S3_V06S0003 Q0\narc: V01S0000 Q0\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000010101110\nword: SLICEA.K1.INIT 1010110000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R18C16:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V01N0101\narc: E3_H06E0103 S3_V06N0103\narc: H00L0100 H02W0301\narc: H00R0100 E1_H02W0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H02W0301\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 N1_V02S0001\narc: V00B0100 V02N0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 S3_V06N0303\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0501 W3_H06E0303\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0501 W3_H06E0303\narc: W3_H06W0003 E1_H02W0001\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: B5 V00B0100\narc: C5 H02E0401\narc: CE2 H00R0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D5 H02E0001\narc: F5 F5_SLICE\narc: H01W0100 Q5\narc: M6 E1_H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111001111000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R18C17:PLC2\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 H01E0101\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 E1_H02W0201\narc: H00R0000 H02E0601\narc: H00R0100 H02W0701\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0101 H02E0101\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 V02N0201\narc: V00B0100 V02S0101\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02S0701\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0701 E1_H01W0100\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: A7 N1_V01N0101\narc: B3 V02N0101\narc: B5 H02W0301\narc: B6 V00B0000\narc: B7 S1_V02N0701\narc: C3 H00L0000\narc: C5 E1_H02W0601\narc: C6 H02W0601\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D5 E1_H02W0001\narc: D6 H02E0001\narc: D7 E1_H01W0100\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q3\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q6\narc: V01S0000 F7\narc: V01S0100 Q5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111001111000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111001111000000\nword: SLICED.K0.INIT 1111001111000000\nword: SLICED.K1.INIT 1010000011000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R18C18:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0003 H01E0001\narc: H00L0100 H02E0301\narc: H01W0100 E3_H06W0303\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 V02N0201\narc: V00T0100 H02E0301\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 E3_H06W0203\narc: W3_H06W0203 N3_V06S0203\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A1 V02N0501\narc: A3 E1_H01E0001\narc: A5 V00B0000\narc: B1 S1_V02N0301\narc: B3 Q3\narc: B5 F1\narc: C1 V02N0401\narc: C2 H00L0100\narc: C3 H02W0401\narc: C5 V01N0101\narc: C6 V00T0100\narc: C7 V00B0100\narc: CE1 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: D2 V02N0001\narc: D3 E1_H02W0201\narc: D5 E1_H02W0001\narc: D6 H01W0000\narc: D7 E1_H02W0201\narc: E1_H01E0001 Q7\narc: E1_H01E0101 F2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: LSR0 W1_H02E0501\narc: LSR1 W1_H02E0501\narc: M4 H02E0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 F6\narc: N3_V06N0203 Q4\narc: V00B0100 Q7\narc: V01S0000 Q3\narc: V01S0100 F6\narc: W1_H02W0201 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100000010100000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0110110000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111111111101111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R18C19:PLC2\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 H01E0001\narc: H00L0100 E1_H02W0101\narc: H00R0000 W1_H02E0601\narc: H00R0100 V02N0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 H06E0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 H06E0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0401\narc: V00B0100 E1_H02W0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 V01N0101\narc: W1_H02W0601 V06S0303\narc: N3_V06N0203 W3_H06E0203\narc: W3_H06W0303 E1_H02W0601\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: A0 W1_H02E0701\narc: A1 W1_H02E0701\narc: A2 V00B0000\narc: A3 V00B0000\narc: A4 V00B0000\narc: A5 V02S0301\narc: A7 V00T0100\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 E1_H02W0301\narc: B5 H00R0000\narc: B7 V00T0000\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V00B0100\narc: C5 H02W0401\narc: C7 E1_H01E0101\narc: CE0 V02S0201\narc: CE1 V02S0201\narc: CLK1 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 E1_H02W0001\narc: D2 E1_H02W0001\narc: D3 E1_H02W0001\narc: D4 V02N0601\narc: D5 V02S0401\narc: D7 H01W0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 F0\narc: E1_H02E0001 Q2\narc: E1_H02E0101 Q3\narc: E3_H06E0103 F2\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: LSR0 H02E0501\narc: LSR1 H02W0501\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q0\narc: S1_V02S0301 Q1\narc: V00T0000 Q0\narc: V00T0100 Q3\narc: V01S0000 Q1\narc: V01S0100 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000001001000001\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R18C20:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0003 V01N0001\narc: E3_H06E0303 S3_V06N0303\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H06E0203\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 V01N0101\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 E1_H02W0401\narc: V00B0100 E1_H02W0701\narc: V00T0100 V02S0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V02S0501\narc: W3_H06W0003 N3_V06S0003\narc: W3_H06W0203 E3_H06W0103\narc: A2 V00B0000\narc: A3 V00B0000\narc: A7 H00L0000\narc: B0 H01W0100\narc: B2 V02S0301\narc: B3 V02S0301\narc: B5 V02N0701\narc: B7 N1_V01S0000\narc: C0 H02E0401\narc: C1 N1_V01S0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 E1_H02W0401\narc: C5 H02E0401\narc: C7 E1_H01E0101\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 V00T0100\narc: D2 V00B0100\narc: D3 V00B0100\narc: D4 H01W0000\narc: D5 F2\narc: D7 H00R0100\narc: E1_H01E0101 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 F0\narc: H00L0100 F1\narc: H01W0000 Q5\narc: H01W0100 Q5\narc: LSR0 W1_H02E0501\narc: M6 E1_H02W0401\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 F4\narc: N3_V06N0303 F6\narc: S1_V02S0601 F4\narc: V01S0000 F3\narc: V01S0100 Q5\narc: W1_H02W0101 F3\narc: W1_H02W0201 F2\narc: W1_H02W0601 F4\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 1100000000000000\nword: SLICEA.K1.INIT 0000000000001111\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0011110000000000\nword: SLICEB.K0.INIT 1010101010001010\nword: SLICEB.K1.INIT 1111111111011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010101010001010\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R18C21:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0303 V06N0303\narc: H00L0100 N1_V02S0301\narc: H00R0000 N1_V02S0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 V01N0001\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 S1_V02N0001\narc: V00T0000 E1_H02W0201\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 N3_V06S0303\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0301 W3_H06E0003\narc: N1_V02N0501 W3_H06E0303\narc: S1_V02S0101 W3_H06E0103\narc: W3_H06W0003 N3_V06S0003\narc: W3_H06W0303 E3_H06W0303\narc: B3 Q3\narc: B7 V00B0100\narc: C3 H00L0000\narc: C7 V02N0201\narc: CE1 H00R0100\narc: CE2 H00L0100\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D2 Q2\narc: D3 H00R0000\narc: D6 V02N0401\narc: D7 V02N0601\narc: E1_H01E0101 Q4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 Q2\narc: H01W0100 Q7\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M4 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q7\narc: S1_V02S0001 Q2\narc: S1_V02S0301 Q3\narc: S1_V02S0501 Q7\narc: S1_V02S0601 Q6\narc: S3_V06S0003 Q3\narc: V00B0100 Q7\narc: V01S0000 Q6\narc: V01S0100 Q3\narc: W1_H02W0001 Q2\narc: W1_H02W0101 Q3\narc: W1_H02W0701 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0011110011001100\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0011110011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R18C22:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 N1_V02S0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0601 S1_V02N0301\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 H06E0203\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02W0601\narc: V00B0100 V02N0301\narc: V00T0000 H02W0201\narc: V00T0100 H02W0301\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 H01E0001\narc: W1_H02W0701 E1_H01W0100\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0501 W3_H06E0303\narc: N3_V06N0003 W3_H06E0003\narc: S1_V02S0501 W3_H06E0303\narc: S1_V02S0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A5 E1_H01W0000\narc: A6 H00L0000\narc: A7 H00R0000\narc: B3 H00R0100\narc: B4 V02S0501\narc: B5 W1_H02E0301\narc: B6 H01E0101\narc: B7 H02E0301\narc: C3 S1_V02N0401\narc: C4 E1_H01E0101\narc: C5 V02N0001\narc: C6 V00B0100\narc: C7 V00T0100\narc: CE0 H00L0100\narc: CLK0 G_HPBX0000\narc: D3 H02W0201\narc: D4 N1_V02S0401\narc: D5 H02W0001\narc: D6 H02E0001\narc: D7 V00B0000\narc: E1_H01E0101 F5\narc: E1_H02E0401 F4\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: LSR1 V00T0000\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0101 F6\narc: V01S0000 F3\narc: W1_H02W0501 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111111111111100\nword: SLICED.K0.INIT 1000010000100001\nword: SLICED.K1.INIT 1010110000000000\nword: SLICEC.K0.INIT 1100000000000000\nword: SLICEC.K1.INIT 1001000000001001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R18C23:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0003 S3_V06N0003\narc: H00L0100 H02W0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 H02W0501\narc: N1_V02N0401 H01E0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02N0201\narc: V00B0100 H02W0501\narc: V00T0000 V02S0401\narc: V00T0100 H02W0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0601 S1_V02N0601\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: N1_V02N0701 W3_H06E0203\narc: W3_H06W0303 V06S0303\narc: E3_H06E0103 W3_H06E0103\narc: A0 H00L0000\narc: A1 H00L0000\narc: A4 W1_H02E0501\narc: A7 H00L0000\narc: B0 H00R0100\narc: B1 H00R0100\narc: B4 N1_V02S0501\narc: B5 V01S0000\narc: B7 H02W0101\narc: C0 E1_H01W0000\narc: C1 E1_H01W0000\narc: C4 V02N0001\narc: C5 E1_H02W0601\narc: C7 V00B0100\narc: CE0 H00R0000\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0201\narc: D1 W1_H02E0201\narc: D4 V00B0000\narc: D5 S1_V02N0401\narc: D7 E1_H01W0100\narc: E1_H01E0001 F6\narc: E1_H02E0001 Q0\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q0\narc: H01W0000 Q2\narc: H01W0100 F6\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00T0100\narc: M2 H02E0601\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N3_V06N0303 F5\narc: V01S0000 Q4\narc: W1_H02W0401 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1010100010101010\nword: SLICEC.K1.INIT 1100111111000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111101\nword: SLICEA.K0.INIT 1010100010101001\nword: SLICEA.K1.INIT 0110101010101010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R18C24:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0401 H01E0001\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0103 S3_V06N0103\narc: H00L0100 W1_H02E0101\narc: H00R0000 E1_H02W0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H02E0501\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02S0201\narc: V00T0000 H02E0201\narc: W1_H02W0301 N1_V02S0301\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: A0 E1_H01E0001\narc: A4 V00B0000\narc: A6 N1_V01N0101\narc: B0 V02N0101\narc: B4 H02E0101\narc: B5 V00B0100\narc: B6 V02N0701\narc: B7 V01S0000\narc: C0 H02E0601\narc: C1 H00L0000\narc: C4 V00T0000\narc: C5 H02E0401\narc: C6 Q6\narc: C7 V00T0100\narc: CE0 H00R0100\narc: CE1 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 H00R0000\narc: D3 V01S0100\narc: D4 V02S0601\narc: D5 N1_V02S0401\narc: D6 H00L0100\narc: D7 H00L0100\narc: E1_H01E0001 Q7\narc: E1_H01E0101 F1\narc: E1_H02E0001 Q0\narc: E1_H02E0201 F0\narc: E1_H02E0301 F1\narc: E1_H02E0501 Q5\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0000 Q6\narc: H01W0100 Q6\narc: LSR0 W1_H02E0301\narc: LSR1 W1_H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q7\narc: N1_V02N0001 F0\narc: N1_V02N0701 Q5\narc: N3_V06N0203 F4\narc: N3_V06N0303 Q5\narc: V00B0100 Q5\narc: V00T0100 Q3\narc: V01S0000 Q7\narc: V01S0100 Q3\narc: W1_H02W0001 Q0\narc: W1_H02W0101 Q3\narc: W1_H02W0201 F0\narc: W1_H02W0501 Q7\narc: W3_H06W0203 F4\narc: W3_H06W0303 Q5\nword: SLICEA.K0.INIT 1111111111111110\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0011001100111011\nword: SLICEC.K1.INIT 1111110011000000\nword: SLICED.K0.INIT 0111100011100001\nword: SLICED.K1.INIT 0011110011000011\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R18C25:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 H01E0101\narc: H00L0000 H02E0001\narc: H00L0100 H02E0301\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H02E0601\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 H06E0303\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0201\narc: V00B0100 H02E0701\narc: V00T0000 H02E0201\narc: V00T0100 E1_H02W0301\narc: W1_H02W0601 V06S0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0103\narc: A4 E1_H02W0701\narc: A5 V00B0000\narc: A6 H00L0000\narc: A7 H00L0000\narc: B4 V01S0000\narc: B5 V02S0501\narc: B6 V00T0000\narc: B7 V00T0000\narc: C4 S1_V02N0001\narc: C5 H02W0601\narc: C6 V00B0100\narc: C7 V00B0100\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CLK0 G_HPBX0000\narc: D4 V02N0601\narc: D5 H00L0100\narc: D6 V02S0601\narc: D7 V02S0601\narc: E1_H01E0101 F6\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 E1_H02W0601\narc: M2 V00T0100\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: N1_V01N0101 F4\narc: N3_V06N0303 F5\narc: V01S0000 F5\narc: V01S0100 Q2\narc: W1_H02W0001 Q0\narc: W1_H02W0401 F6\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000010100010\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 1100010001000100\nword: SLICED.K1.INIT 0011101110111011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R18C26:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0501 V01N0101\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 H02W0001\narc: H00L0100 V02N0301\narc: H00R0000 V02S0601\narc: H00R0100 H02E0701\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 V01N0001\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 E1_H02W0301\narc: V00B0000 V02S0001\narc: V00B0100 H02E0501\narc: V00T0000 V02N0601\narc: V00T0100 V02N0501\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 E1_H02W0101\narc: E1_H01E0001 W3_H06E0003\narc: H01W0100 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: A1 H02W0501\narc: A2 H00L0100\narc: A5 V00B0000\narc: B1 V02S0101\narc: B2 H00L0000\narc: B3 V02N0101\narc: B5 V02S0701\narc: C0 N1_V01N0001\narc: C1 V02S0401\narc: C2 H02W0401\narc: C3 E1_H02W0401\narc: C5 V00B0100\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 H00R0000\narc: D2 V00T0100\narc: D3 H02E0001\narc: D5 H00R0100\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: LSR0 E1_H02W0301\narc: M4 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F1\narc: N1_V02N0601 F4\narc: N3_V06N0203 F4\narc: S3_V06S0003 F3\narc: V01S0100 Q2\narc: W3_H06W0003 F0\narc: W3_H06W0103 F1\nword: SLICEB.K0.INIT 1000000011001100\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1111000011111111\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R18C27:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 V01N0001\narc: H00R0000 V02S0401\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H06E0203\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 E1_H01W0100\narc: N3_V06N0303 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0303 E3_H06W0203\narc: A0 N1_V02S0701\narc: A1 E1_H01E0001\narc: A2 V02S0701\narc: A3 V00B0000\narc: A4 V00B0000\narc: A6 N1_V01S0100\narc: A7 H02E0701\narc: B0 V02S0101\narc: B1 V00T0000\narc: B2 V02S0301\narc: B3 H00L0000\narc: B4 H00L0000\narc: B5 V01S0000\narc: B6 V00B0100\narc: B7 V00B0000\narc: C0 H00L0100\narc: C1 N1_V01N0001\narc: C2 H00R0100\narc: C3 V02N0601\narc: C4 Q4\narc: C5 V02S0201\narc: C6 E1_H01E0101\narc: C7 V00T0000\narc: CE0 W1_H02E0101\narc: CE2 W1_H02E0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V02S0001\narc: D2 V00T0100\narc: D3 E1_H02W0201\narc: D4 V02N0401\narc: D5 H01W0000\narc: D6 V02S0401\narc: D7 V02S0601\narc: E1_H01E0001 Q4\narc: E1_H01E0101 F3\narc: E1_H02E0201 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00L0100 F3\narc: H00R0100 F7\narc: H01W0000 Q0\narc: H01W0100 Q4\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V01N0101 F5\narc: N1_V02N0001 Q0\narc: N1_V02N0101 F1\narc: N1_V02N0601 Q4\narc: N1_V02N0701 F5\narc: V00B0000 Q6\narc: V00B0100 F5\narc: V00T0000 Q0\narc: V01S0000 Q4\narc: V01S0100 Q6\narc: W3_H06W0103 F1\nword: SLICEB.K0.INIT 0000101100000011\nword: SLICEB.K1.INIT 1110000100000000\nword: SLICED.K0.INIT 1101110011111100\nword: SLICED.K1.INIT 0000000001000000\nword: SLICEC.K0.INIT 0000000011100001\nword: SLICEC.K1.INIT 0000001100110000\nword: SLICEA.K0.INIT 1111110011011100\nword: SLICEA.K1.INIT 0100000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R18C28:PLC2\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0401 V01N0001\narc: E3_H06E0003 S3_V06N0003\narc: H00L0100 W1_H02E0101\narc: H00R0000 N1_V02S0601\narc: H00R0100 W1_H02E0501\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 V02N0201\narc: V00B0100 H02E0501\narc: V00T0000 H02E0201\narc: V00T0100 V02N0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 E1_H02W0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0001 W3_H06E0003\narc: H01W0000 W3_H06E0103\narc: N1_V02N0001 W3_H06E0003\narc: S1_V02S0601 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0303 E3_H06W0203\narc: A3 H00L0100\narc: A5 S1_V02N0301\narc: A7 S1_V02N0301\narc: B3 V02S0101\narc: B5 H02W0301\narc: B7 H02W0301\narc: C3 H00R0100\narc: C5 V02N0001\narc: C7 V00T0100\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 H01E0101\narc: D5 V00B0000\narc: D7 H02E0001\narc: E1_H01E0101 Q0\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F2\narc: M0 V00B0100\narc: M2 V00T0000\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q0\narc: N3_V06N0203 F7\narc: S3_V06S0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010001011110011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R18C29:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 H01E0101\narc: E3_H06E0103 S3_V06N0103\narc: H00R0000 V02N0601\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 H01E0001\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: V00T0100 V02N0501\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 S3_V06N0003\narc: S1_V02S0001 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H02E0201 Q0\narc: E3_H06E0003 Q0\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: H01W0000 Q0\narc: M0 H02W0601\narc: M2 W1_H02E0601\narc: M4 H02E0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0001 Q2\narc: S3_V06S0203 Q4\narc: S3_V06S0303 Q6\narc: V01S0000 Q2\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R18C2:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0003 V06S0003\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0501 E1_H02W0501\narc: S3_V06S0003 H06W0003\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02N0201\narc: CE0 V02S0201\narc: CLK0 G_HPBX0000\narc: LSR1 E1_H02W0501\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: V01S0000 Q0\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R18C30:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0701 V02S0701\narc: H00L0000 N1_V02S0201\narc: H00R0100 V02S0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0601 H06W0303\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0303 E3_H06W0303\narc: V00T0100 H02W0301\narc: W1_H02W0201 V06S0103\narc: W1_H02W0601 V02S0601\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0601 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: B0 E1_H02W0101\narc: B1 V00T0000\narc: B2 E1_H02W0301\narc: B3 V02S0101\narc: C0 H00L0000\narc: C1 E1_H02W0601\narc: C2 S1_V02N0401\narc: C3 E1_H02W0601\narc: C6 V00B0100\narc: C7 V02S0001\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 V02N0201\narc: D2 N1_V02S0201\narc: D3 W1_H02E0201\narc: D6 H02E0001\narc: D7 W1_H02E0001\narc: E1_H01E0001 F6\narc: E1_H02E0501 F7\narc: E3_H06E0003 F3\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: H01W0100 F7\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: N1_V02N0501 F7\narc: N3_V06N0203 F7\narc: S3_V06S0003 F3\narc: S3_V06S0103 F1\narc: S3_V06S0203 F7\narc: V00B0100 F7\narc: V00T0000 Q0\narc: V01S0000 Q4\narc: V01S0100 F7\narc: W1_H02W0501 F7\narc: W3_H06W0003 F3\narc: W3_H06W0103 F1\narc: W3_H06W0203 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 0000000000001111\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1100111111000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100111111000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R18C31:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 H01E0001\narc: E1_H02E0701 V02N0701\narc: H00L0100 E1_H02W0301\narc: H00R0100 H02E0701\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H06W0003\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 H06W0303\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0201 H02E0201\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 E1_H01W0100\narc: V00T0000 V02N0401\narc: W1_H02W0101 H01E0101\narc: W1_H02W0301 N1_V01S0100\narc: N3_V06N0003 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: CE0 H00R0100\narc: CE2 H00L0100\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: LSR1 V00T0000\narc: M0 V00B0000\narc: M4 E1_H01E0101\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: S1_V02S0001 Q0\narc: V00B0000 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R18C32:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 S1_V02N0201\narc: H00L0100 E1_H02W0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 S1_V02N0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H06E0203\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 E1_H02W0401\narc: S3_V06S0003 H06E0003\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 H06E0303\narc: V00B0000 W1_H02E0601\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02E0201\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0601 W3_H06E0303\narc: A1 N1_V02S0501\narc: A5 Q5\narc: A7 H00R0000\narc: B1 V02S0301\narc: B5 H00L0000\narc: B6 N1_V01S0000\narc: B7 V02S0701\narc: C1 H00L0100\narc: C5 V00T0100\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D5 W1_H02E0001\narc: D6 V00B0000\narc: D7 V02S0401\narc: E1_H01E0001 F6\narc: E1_H01E0101 F7\narc: E3_H06E0303 F5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00T0000\narc: M0 H02W0601\narc: M1 H00R0100\narc: M2 H02W0601\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: S1_V02S0701 Q5\narc: S3_V06S0103 F1\narc: V00T0100 F1\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000110000000000\nword: SLICED.K0.INIT 1100111100000000\nword: SLICED.K1.INIT 0100000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R18C33:PLC2\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 V02S0601\narc: H00L0000 V02N0001\narc: H00L0100 V02N0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02W0701\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 H02W0601\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 H06W0103\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 H02E0401\narc: V00B0100 V02S0301\narc: V00T0000 V02S0401\narc: V00T0100 H02W0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V06N0003\narc: W1_H02W0601 N1_V02S0601\narc: W3_H06W0303 E1_H02W0501\narc: A1 H02W0701\narc: A2 H02W0701\narc: A5 W1_H02E0701\narc: A6 V02S0101\narc: B0 H00R0100\narc: B1 V02N0301\narc: B2 V02N0301\narc: B5 V01S0000\narc: B6 V02N0501\narc: C0 H00L0100\narc: C1 H00L0000\narc: C2 H00L0000\narc: C4 H02E0601\narc: C5 V02N0201\narc: C6 E1_H01E0101\narc: C7 V00T0000\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 W1_H02E0001\narc: D2 W1_H02E0001\narc: D4 V02S0601\narc: D5 V00B0000\narc: D6 S1_V02N0401\narc: D7 H02W0201\narc: E1_H01E0001 F4\narc: E1_H01E0101 F7\narc: E1_H02E0701 F5\narc: E3_H06E0203 F7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: H01W0100 Q7\narc: LSR1 V00B0100\narc: M0 V00T0100\narc: M1 H00R0000\narc: M2 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q7\narc: N1_V01N0101 F4\narc: N1_V02N0701 Q7\narc: S1_V02S0701 F7\narc: S3_V06S0303 F6\narc: V01S0000 F4\narc: V01S0100 F1\narc: W1_H02W0701 F7\narc: W3_H06W0203 F7\nword: SLICEC.K0.INIT 0000111100000000\nword: SLICEC.K1.INIT 0000101100000000\nword: SLICED.K0.INIT 1010110000000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 1111111111110011\nword: SLICEA.K1.INIT 1111111111101111\nword: SLICEB.K0.INIT 1111111111111110\nword: SLICEB.K1.INIT 1111111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R18C34:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 V02N0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 W1_H02E0201\narc: H00L0100 V02S0301\narc: H00R0100 W1_H02E0501\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H01E0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H01E0101\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 V02S0201\narc: V00T0100 V02S0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 V02S0501\narc: W1_H02W0701 E1_H02W0601\narc: E1_H02E0201 W3_H06E0103\narc: W3_H06W0303 V06S0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: A6 V02N0101\narc: B3 H00L0000\narc: B5 H00R0000\narc: B6 V00B0100\narc: B7 W1_H02E0301\narc: C0 H00L0100\narc: C1 H00R0100\narc: C3 S1_V02N0601\narc: C4 V01N0101\narc: C5 V02N0001\narc: C6 S1_V02N0201\narc: C7 H02E0601\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 V00T0100\narc: D3 W1_H02E0001\narc: D4 H02W0001\narc: D5 V00B0000\narc: D6 N1_V02S0401\narc: D7 H02E0201\narc: E1_H01E0101 F1\narc: E1_H02E0101 F3\narc: E1_H02E0601 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H01W0000 F7\narc: H01W0100 F7\narc: LSR1 H02W0301\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0101 F5\narc: V00B0100 F7\narc: V01S0100 Q0\narc: W1_H02W0601 F4\narc: W3_H06W0003 Q0\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0011111111111111\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 1111111100001111\nword: SLICED.K0.INIT 0000110100001111\nword: SLICED.K1.INIT 0000000000000011\nword: SLICEC.K0.INIT 0000000000001111\nword: SLICEC.K1.INIT 0000001100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R18C35:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0303 N3_V06S0303\narc: H00R0000 W1_H02E0401\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 H06E0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02W0401\narc: V00B0100 N1_V02S0301\narc: V00T0100 H02W0101\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 N3_V06S0203\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0401 W3_H06E0203\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 N3_V06S0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: A1 H02E0701\narc: A5 H02W0701\narc: B1 H02W0301\narc: B3 V02S0301\narc: B5 H02W0301\narc: C1 V02N0401\narc: C3 V02S0401\narc: C5 V00T0100\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D3 H02E0001\narc: D5 V00B0000\narc: E1_H01E0101 Q6\narc: E1_H02E0401 Q6\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F3\narc: H01W0100 Q6\narc: M6 V00B0100\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V02N0101 F1\narc: W1_H02W0501 F5\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111111111001111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R18C36:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 V02S0701\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 V02S0201\narc: H00L0100 S1_V02N0101\narc: H00R0100 H02E0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 V01N0001\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H06E0203\narc: V00B0000 V02S0001\narc: V00T0100 V02N0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 V06N0203\narc: W1_H02W0701 S3_V06N0203\narc: H01W0000 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: S3_V06S0003 W3_H06E0003\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0103 N1_V01S0100\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A1 W1_H02E0501\narc: A3 V00B0000\narc: B1 V02S0301\narc: B3 H02E0301\narc: B4 H00L0000\narc: C1 E1_H02W0601\narc: C3 V02S0401\narc: C4 H02E0601\narc: C5 H01E0001\narc: CE2 H00L0100\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: D3 V00B0100\narc: D4 V02S0601\narc: D5 H00R0100\narc: E1_H01E0001 Q6\narc: E1_H01E0101 F2\narc: E1_H02E0001 F2\narc: E1_H02E0601 Q6\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: M0 W1_H02E0601\narc: M2 H02W0601\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q6\narc: N3_V06N0203 Q4\narc: S3_V06S0303 Q6\narc: V00B0100 F5\narc: V01S0000 Q4\narc: W1_H02W0001 F0\narc: W1_H02W0601 Q6\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000110011001100\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 1110101011101000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R18C37:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 W1_H02E0401\narc: H00L0000 H02E0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 V02N0401\narc: H00R0100 W1_H02E0701\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02S0301\narc: W1_H02W0601 V02S0601\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0203\narc: A1 H01E0001\narc: A2 H00L0100\narc: A3 V00T0000\narc: A4 E1_H01W0000\narc: A5 W1_H02E0701\narc: A6 H00R0000\narc: A7 H00L0000\narc: B1 H02E0101\narc: B2 H00R0100\narc: B3 V02S0101\narc: B4 H01E0101\narc: B5 N1_V02S0501\narc: B6 S1_V02N0701\narc: B7 H02W0301\narc: C1 S1_V02N0401\narc: C2 H02E0401\narc: C3 V02N0601\narc: C4 E1_H02W0401\narc: C5 V00B0100\narc: C6 E1_H01E0101\narc: C7 F6\narc: CE1 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D2 E1_H02W0201\narc: D3 V02N0001\narc: D4 H01W0000\narc: D5 N1_V02S0401\narc: D6 V01N0001\narc: D7 H01W0000\narc: E1_H01E0001 F4\narc: E1_H01E0101 F1\narc: E1_H02E0401 F6\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: H01W0100 Q2\narc: LSR0 H02W0501\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 Q2\narc: N1_V02N0201 Q2\narc: V00T0000 Q2\narc: V01S0000 F7\narc: V01S0100 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000010000100001\nword: SLICED.K0.INIT 1001000000000000\nword: SLICED.K1.INIT 1010111100100011\nword: SLICEC.K0.INIT 1101110100001101\nword: SLICEC.K1.INIT 0000000011100000\nword: SLICEB.K0.INIT 0100110011111111\nword: SLICEB.K1.INIT 0000000000100000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R18C38:PLC2\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0003 V06S0003\narc: H00L0000 H02W0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 N1_V02S0601\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H06E0203\narc: V00B0000 H02E0401\narc: V00B0100 H02E0501\narc: V00T0000 N1_V02S0601\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 N1_V02S0601\narc: N1_V02N0401 W3_H06E0203\narc: W3_H06W0303 E3_H06W0203\narc: A0 H00L0000\narc: A1 H00R0000\narc: A2 V01N0101\narc: A3 N1_V02S0701\narc: A4 E1_H01W0000\narc: A5 V00T0000\narc: A7 W1_H02E0501\narc: B0 H01W0100\narc: B1 V02S0301\narc: B2 E1_H01W0100\narc: B3 E1_H01W0100\narc: B4 W1_H02E0301\narc: B5 V02S0501\narc: B6 V01S0000\narc: B7 H02E0101\narc: C0 H00R0100\narc: C1 H00L0100\narc: C2 H02W0601\narc: C3 W1_H02E0601\narc: C4 E1_H01E0101\narc: C5 S1_V02N0001\narc: C6 N1_V02S0001\narc: C7 H02E0601\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 F0\narc: D2 S1_V02N0201\narc: D3 V00B0100\narc: D4 V01N0001\narc: D5 H01W0000\narc: D6 V02S0401\narc: D7 V00B0000\narc: E1_H01E0001 F0\narc: E1_H01E0101 F3\narc: E1_H02E0101 F1\narc: E1_H02E0701 F5\narc: E3_H06E0103 F1\narc: E3_H06E0203 F7\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F2\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F7\narc: S1_V02S0501 F7\narc: S1_V02S0701 F5\narc: S3_V06S0303 F5\narc: V01S0000 F7\narc: V01S0100 F1\nword: SLICEA.K0.INIT 1000010000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 1001000000000000\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 1111110000110000\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 1001000000001001\nword: SLICEB.K1.INIT 1000010000100001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R18C39:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V06N0203\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V01N0101\narc: E3_H06E0203 N1_V01S0000\narc: H00R0000 N1_V02S0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 E1_H02W0701\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 W1_H02E0701\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02N0501\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 S3_V06N0303\narc: E1_H01E0101 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\narc: A3 V01N0101\narc: B3 V02S0101\narc: C3 H00R0100\narc: CE0 H00R0000\narc: CE2 N1_V02S0601\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D3 H02W0201\narc: F3 F3_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q4\narc: M0 V00B0100\narc: M4 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 F3\narc: S1_V02S0601 Q4\narc: V01S0100 Q6\narc: W1_H02W0001 Q0\narc: W1_H02W0601 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100111101000101\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R18C3:PLC2\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0601 V01N0001\narc: E1_H02E0701 V02S0701\narc: E3_H06E0203 N3_V06S0203\narc: H00R0000 V02S0401\narc: H00R0100 V02S0701\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0201\narc: CE0 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 V00B0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q6\narc: N1_V02N0401 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R18C40:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 S1_V02N0001\narc: H00L0100 V02N0101\narc: H00R0100 V02N0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 H02E0201\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 H01E0101\narc: V00B0000 S1_V02N0001\narc: V00B0100 E1_H02W0701\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02W0301\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 H01E0101\narc: W1_H02W0701 S3_V06N0203\narc: E1_H02E0201 W3_H06E0103\narc: N3_V06N0003 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: A0 H00L0000\narc: A1 H00L0000\narc: A2 V00B0000\narc: A3 V00B0000\narc: A4 H02E0701\narc: A5 N1_V02S0101\narc: A6 H02W0501\narc: B0 S1_V02N0101\narc: B1 S1_V02N0101\narc: B2 S1_V02N0101\narc: B3 S1_V02N0101\narc: B4 N1_V01S0000\narc: B5 E1_H02W0301\narc: B6 H01E0101\narc: B7 S1_V02N0701\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 H02E0601\narc: C5 V00T0000\narc: C6 H02E0401\narc: C7 F6\narc: CLK1 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 V00T0100\narc: D3 V00T0100\narc: D4 H00L0100\narc: D5 V02N0601\narc: D6 S1_V02N0401\narc: D7 V02S0401\narc: E1_H01E0001 Q1\narc: E1_H02E0601 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR1 V00B0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0101 Q2\narc: N1_V02N0301 Q3\narc: N1_V02N0401 F6\narc: S3_V06S0203 F7\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 1011100000000000\nword: SLICED.K1.INIT 1111000011110011\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R18C41:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0103 V06S0103\narc: H00L0000 S1_V02N0201\narc: H00L0100 N1_V02S0301\narc: H00R0100 H02W0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 H02E0201\narc: S1_V02S0401 H02E0401\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 H06E0203\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02E0501\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02S0501\narc: V01S0000 S3_V06N0103\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 H01E0101\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0003 V01N0001\narc: W3_H06W0303 N3_V06S0303\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: A0 H00L0000\narc: A1 H00L0000\narc: A2 V00B0000\narc: A3 V00B0000\narc: A4 W1_H02E0701\narc: A5 N1_V02S0101\narc: B0 H02E0101\narc: B1 H02E0101\narc: B2 H02E0101\narc: B3 H02E0101\narc: B4 N1_V02S0701\narc: B5 H02W0301\narc: B6 V02S0701\narc: C0 E1_H02W0401\narc: C1 E1_H02W0401\narc: C2 E1_H02W0401\narc: C3 E1_H02W0401\narc: C4 V02N0201\narc: C5 E1_H02W0601\narc: C6 V00T0000\narc: CE3 W1_H02E0101\narc: CLK1 G_HPBX0000\narc: D0 H01E0101\narc: D1 H01E0101\narc: D2 H01E0101\narc: D3 H01E0101\narc: D4 H02E0001\narc: D5 V02N0601\narc: D6 H00L0100\narc: D7 H00R0100\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q3\narc: LSR1 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXCLK3 CLK1\narc: N1_V01N0001 Q1\narc: S3_V06S0303 Q6\narc: V01S0100 Q0\narc: W1_H02W0001 Q2\nword: SLICED.K0.INIT 1100000011110011\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R18C42:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V01N0001\narc: E3_H06E0203 V06S0203\narc: H00R0100 V02S0701\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H02W0301\narc: N1_V02N0501 S3_V06N0303\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N1_V02S0401\narc: V00B0000 V02S0001\narc: V00B0100 W1_H02E0701\narc: V00T0000 V02S0401\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 S1_V02N0501\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0701 W3_H06E0203\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A2 V02N0701\narc: B0 H02E0301\narc: B2 H00R0100\narc: B3 V02S0301\narc: B4 W1_H02E0301\narc: B6 N1_V01S0000\narc: C0 H02E0601\narc: C2 N1_V02S0601\narc: C3 N1_V01N0001\narc: C4 V00T0000\narc: C6 E1_H02W0401\narc: CE1 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 V01S0100\narc: D2 S1_V02N0201\narc: D3 F2\narc: D4 H02W0201\narc: D5 V02N0601\narc: D6 H02W0201\narc: D7 V02N0601\narc: E1_H01E0001 F2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0000\narc: M4 V00B0100\narc: M6 W1_H02E0401\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F0\narc: S1_V02S0001 F2\narc: S1_V02S0201 F2\narc: S1_V02S0401 F6\narc: V01S0000 F3\narc: V01S0100 Q2\narc: W1_H02W0201 F2\narc: W1_H02W0601 F4\nword: SLICEB.K0.INIT 1111111100101010\nword: SLICEB.K1.INIT 0011000011111100\nword: SLICEA.K0.INIT 0011001100001111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 1100111100000011\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111001100000011\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R18C43:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 N3_V06S0303\narc: H00L0100 V02N0301\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02W0701\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 H01E0101\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 E1_H02W0701\narc: V00T0100 N1_V02S0501\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 V01N0101\narc: E1_H02E0701 W3_H06E0203\narc: S3_V06S0203 W3_H06E0203\narc: W3_H06W0303 N3_V06S0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: A0 E1_H02W0501\narc: A1 E1_H02W0501\narc: A2 E1_H02W0501\narc: A3 E1_H02W0501\narc: A4 W1_H02E0701\narc: A5 H02E0501\narc: A7 N1_V01N0101\narc: B0 E1_H02W0101\narc: B1 E1_H02W0101\narc: B2 E1_H02W0101\narc: B3 E1_H02W0101\narc: B4 V02S0501\narc: B5 H02E0101\narc: B6 E1_H02W0301\narc: B7 W1_H02E0101\narc: C0 E1_H02W0401\narc: C1 E1_H02W0401\narc: C2 E1_H02W0401\narc: C3 E1_H02W0401\narc: C4 V00B0100\narc: C5 H01E0001\narc: C6 V02N0001\narc: C7 H02E0401\narc: CE3 H00R0100\narc: CLK1 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 V00T0100\narc: D3 V00T0100\narc: D4 E1_H02W0201\narc: D5 V02N0601\narc: D6 W1_H02E0001\narc: D7 H00L0100\narc: E1_H01E0101 Q3\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q1\narc: LSR1 W1_H02E0501\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXCLK3 CLK1\narc: N1_V01N0101 Q6\narc: S1_V02S0001 Q0\narc: S1_V02S0601 Q6\narc: V01S0000 Q2\nword: SLICED.K0.INIT 1111110000110000\nword: SLICED.K1.INIT 0000000000000001\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R18C44:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 V01N0101\narc: E1_H02E0701 V06S0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 H02E0301\narc: H00R0100 V02N0501\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 V01N0001\narc: N3_V06N0003 H06W0003\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 W1_H02E0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 N1_V01S0100\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0101 W3_H06E0103\narc: H01W0000 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: N1_V02N0201 W3_H06E0103\narc: S1_V02S0701 W3_H06E0203\narc: W3_H06W0003 V01N0001\narc: W3_H06W0203 V06S0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A0 E1_H02W0701\narc: A1 E1_H02W0701\narc: A2 E1_H02W0701\narc: A3 E1_H02W0701\narc: A4 V02S0301\narc: A5 S1_V02N0301\narc: B0 E1_H02W0301\narc: B1 E1_H02W0301\narc: B2 E1_H02W0301\narc: B3 E1_H02W0301\narc: B4 E1_H02W0101\narc: B5 V02N0701\narc: B6 V02S0701\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 E1_H02W0401\narc: C5 V02S0201\narc: C6 V02N0201\narc: CLK1 G_HPBX0000\narc: D0 H02W0001\narc: D1 H02W0001\narc: D2 H02W0001\narc: D3 H02W0001\narc: D4 V02N0401\narc: D5 V00B0000\narc: D6 V02S0401\narc: D7 H00L0100\narc: E1_H01E0001 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: LSR1 V00B0100\narc: M6 H02E0401\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0001 Q3\narc: S1_V02S0401 F6\narc: V01S0100 Q1\narc: W1_H02W0201 Q2\nword: SLICED.K0.INIT 1111110000001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R18C45:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0303 H01E0101\narc: H00L0100 V02S0101\narc: H00R0000 N1_V02S0601\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 H01E0101\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02S0301\narc: V00T0000 H02W0201\narc: V00T0100 V02N0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 V02N0701\narc: S3_V06S0203 W3_H06E0203\narc: A0 S1_V02N0501\narc: A1 S1_V02N0501\narc: A2 S1_V02N0501\narc: A3 S1_V02N0501\narc: A4 V02N0301\narc: A5 E1_H02W0501\narc: B0 S1_V02N0101\narc: B1 S1_V02N0101\narc: B2 S1_V02N0101\narc: B3 S1_V02N0101\narc: B4 V02S0701\narc: B5 V02S0501\narc: B6 V00T0000\narc: C0 V02S0401\narc: C1 V02S0401\narc: C2 V02S0401\narc: C3 V02S0401\narc: C4 V00T0100\narc: C5 V02S0001\narc: C6 V02S0201\narc: CLK1 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 E1_H02W0201\narc: D5 V00B0000\narc: D6 H02E0001\narc: D7 H00L0100\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: LSR1 W1_H02E0501\narc: M6 V00B0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q3\narc: N1_V02N0001 Q0\narc: N1_V02N0301 Q1\narc: W3_H06W0303 F6\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R18C46:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0203 W1_H02E0701\narc: E3_H06E0303 W1_H02E0501\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 V01N0101\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N1_V02S0101\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02S0201\narc: V00B0100 H02E0701\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02N0501\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 V02N0701\narc: E1_H01E0001 W3_H06E0003\narc: H01W0100 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\narc: A0 V02N0701\narc: A1 V02N0701\narc: A2 V02N0701\narc: A3 V02N0701\narc: A4 V02N0301\narc: A5 H02W0501\narc: B0 S1_V02N0101\narc: B1 S1_V02N0101\narc: B2 S1_V02N0301\narc: B3 S1_V02N0301\narc: B4 V02S0501\narc: B5 E1_H02W0301\narc: B7 V00B0100\narc: C0 V02S0601\narc: C1 V02S0601\narc: C2 V02S0601\narc: C3 V02S0601\narc: C4 V00T0100\narc: C5 H02E0401\narc: C7 S1_V02N0201\narc: CLK1 G_HPBX0000\narc: D0 V01S0100\narc: D1 V01S0100\narc: D2 V01S0100\narc: D3 V01S0100\narc: D4 H02W0201\narc: D5 V00B0000\narc: D7 H02E0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: LSR1 V00T0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0001 Q1\narc: N1_V01N0101 Q3\narc: N1_V02N0001 Q2\narc: S1_V02S0501 F7\narc: V01S0000 F7\narc: V01S0100 F7\narc: W1_H02W0201 Q0\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R18C47:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 H01E0001\narc: H00L0000 W1_H02E0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02E0401\narc: H00R0100 H02W0501\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 V01N0101\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 H06E0203\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H06E0003\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N3_V06S0103\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 V02N0201\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0601 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: N1_V02N0201 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: A3 N1_V02S0701\narc: B0 V02S0101\narc: B1 V00T0000\narc: B3 H00R0000\narc: C0 H00L0000\narc: C1 V02S0601\narc: C3 E1_H02W0401\narc: C4 V02S0001\narc: C5 H02W0601\narc: C7 V02S0001\narc: CE0 H00R0100\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 N1_V02S0001\narc: D3 V02N0001\narc: D4 H00L0100\narc: D5 V00B0000\narc: D6 H02E0001\narc: D7 H00L0100\narc: E1_H01E0001 F4\narc: E1_H02E0201 F2\narc: E1_H02E0501 F7\narc: E3_H06E0203 F4\narc: E3_H06E0303 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: M2 H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: S1_V02S0101 F1\narc: S3_V06S0303 Q6\narc: V00B0000 F4\narc: V00T0000 Q0\narc: V01S0100 Q0\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R18C48:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 H02E0201\narc: H00R0000 V02N0601\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H01E0001\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H01E0001\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 H06E0303\narc: S3_V06S0003 H01E0001\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 S1_V02N0401\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0601 E1_H02W0301\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0501 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A1 W1_H02E0501\narc: A2 V02S0501\narc: A7 H02W0701\narc: B1 W1_H02E0101\narc: B2 V02S0301\narc: B3 H00R0100\narc: B7 H02E0101\narc: C1 H02W0601\narc: C2 H00L0000\narc: C3 V02N0401\narc: C7 V00B0100\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 V00T0100\narc: D3 V01S0100\narc: D7 H02W0001\narc: E1_H01E0001 Q4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q4\narc: LSR0 V00B0000\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 F7\narc: V00T0100 F3\narc: V01S0000 F2\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000001\nword: SLICEB.K0.INIT 1000000000000000\nword: SLICEB.K1.INIT 0000001100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R18C49:PLC2\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 H02E0201\narc: H00L0100 H02E0301\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N1_V02S0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 H02E0201\narc: V00T0100 N1_V02S0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: H01W0100 W3_H06E0303\narc: N1_V02N0001 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: B0 H01W0100\narc: B2 S1_V02N0101\narc: B4 H02E0101\narc: B5 H00R0000\narc: B6 V02S0501\narc: B7 V00B0000\narc: C0 H00L0000\narc: C1 H00L0100\narc: C2 V02S0401\narc: C4 V02S0001\narc: C5 E1_H02W0401\narc: C6 H02W0601\narc: C7 V00B0100\narc: CE0 E1_H02W0101\narc: CE1 E1_H02W0101\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 H02E0001\narc: D2 V00T0100\narc: D3 W1_H02E0001\narc: D4 H02W0001\narc: D5 H02W0201\narc: D6 H02W0001\narc: D7 H02W0201\narc: E3_H06E0103 F1\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: M2 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0201 Q0\narc: N3_V06N0203 Q4\narc: N3_V06N0303 Q6\narc: S3_V06S0303 F5\narc: V00B0000 Q6\narc: V01S0100 Q2\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R18C4:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 V06S0103\narc: E1_H02E0501 S3_V06N0303\narc: H00L0100 W1_H02E0301\narc: H00R0000 N1_V02S0401\narc: H00R0100 H02E0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0701 N1_V01S0100\narc: V00B0000 V02N0201\narc: V00B0100 V02S0101\narc: W1_H02W0501 S3_V06N0303\narc: CE0 H00L0100\narc: CE1 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: E3_H06E0003 Q0\narc: E3_H06E0303 Q6\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 H02E0601\narc: M2 V00B0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V02N0201 Q2\narc: N1_V02N0601 Q6\narc: S3_V06S0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R18C50:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0701 N3_V06S0203\narc: H00L0000 N1_V02S0001\narc: H00R0000 H02E0401\narc: H00R0100 W1_H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 V01N0001\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 H06E0203\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0303 N1_V01S0100\narc: V00B0100 V02N0101\narc: V00T0000 V02N0401\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V02S0601\narc: S1_V02S0701 W3_H06E0203\narc: S3_V06S0103 W3_H06E0103\narc: S3_V06S0203 W3_H06E0203\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: B2 H02W0301\narc: B3 H00R0000\narc: B6 V00T0000\narc: C0 H02E0601\narc: C1 V02S0401\narc: C2 H00L0000\narc: C3 E1_H02W0401\narc: C5 V00B0100\narc: C6 V02N0201\narc: C7 V02N0201\narc: CE1 H00R0100\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 W1_H02E0001\narc: D2 V02S0001\narc: D3 N1_V02S0201\narc: D5 W1_H02E0001\narc: D6 W1_H02E0201\narc: D7 W1_H02E0001\narc: E1_H01E0001 F3\narc: E1_H02E0301 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: H01W0100 F0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F5\narc: N1_V02N0601 Q6\narc: N3_V06N0103 Q2\narc: V01S0000 F7\narc: W3_H06W0103 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R18C51:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 V02N0101\narc: E1_H02E0401 S1_V02N0401\narc: E3_H06E0203 H01E0001\narc: E3_H06E0303 V06N0303\narc: H00L0000 V02S0001\narc: H00L0100 V02N0101\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0303 N1_V01S0100\narc: V00B0100 V02N0301\narc: V00T0000 E1_H02W0001\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 S1_V02N0601\narc: E1_H01E0001 W3_H06E0003\narc: W3_H06W0203 V01N0001\narc: A0 W1_H02E0501\narc: A2 E1_H02W0701\narc: B2 H02E0301\narc: B3 W1_H02E0301\narc: B4 H00L0000\narc: B5 H02W0101\narc: B6 V00T0000\narc: B7 V00B0100\narc: CE1 S1_V02N0201\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q4\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: S1_V02S0101 Q3\narc: S1_V02S0501 Q5\narc: S1_V02S0701 Q7\narc: V01S0000 Q6\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R18C52:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0501 W1_H02E0401\narc: H00R0000 H02E0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0201 V01N0001\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V01S0100\narc: V00T0000 V02S0601\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 V02N0601\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: B0 E1_H02W0101\narc: B1 H00R0100\narc: B2 H00R0000\narc: B3 V02S0101\narc: B4 S1_V02N0701\narc: B5 V02N0701\narc: B6 V02S0701\narc: B7 V00T0000\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q6\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: S1_V02S0001 Q2\narc: S1_V02S0101 Q3\narc: S1_V02S0301 Q1\narc: S1_V02S0501 Q7\narc: S1_V02S0701 Q5\narc: V01S0000 Q4\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R18C53:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 V02N0301\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 H02E0001\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 H06W0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 V01N0101\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 H02W0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 N3_V06S0303\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: S1_V02S0701 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: B0 S1_V02N0301\narc: B1 H00R0100\narc: B2 N1_V02S0301\narc: B3 H00L0000\narc: B4 E1_H02W0101\narc: B5 V02S0701\narc: B6 N1_V01S0000\narc: B7 V00B0100\narc: CE0 W1_H02E0101\narc: CE1 W1_H02E0101\narc: CE2 W1_H02E0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: S1_V02S0001 Q0\narc: S1_V02S0101 Q3\narc: S1_V02S0201 Q2\narc: S1_V02S0301 Q1\narc: S1_V02S0501 Q5\narc: S1_V02S0601 Q6\narc: V01S0000 Q7\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R18C54:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 N1_V02S0301\narc: H00L0000 H02W0001\narc: H00R0100 V02S0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 H06W0303\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 H06E0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02W0701\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: S3_V06S0003 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: B0 H00R0100\narc: B1 V02N0301\narc: B2 H02E0301\narc: B3 V02S0101\narc: B4 V00B0100\narc: B5 E1_H02W0101\narc: B6 H02W0301\narc: B7 V00B0000\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: S1_V02S0101 Q1\narc: S1_V02S0201 Q0\narc: S1_V02S0301 Q3\narc: S1_V02S0501 Q5\narc: S1_V02S0601 Q6\narc: S1_V02S0701 Q7\narc: V01S0000 Q4\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R18C55:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0401 E1_H01W0000\narc: H00L0000 V02N0001\narc: H00L0100 H02E0301\narc: H00R0100 W1_H02E0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 N3_V06S0303\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S1_V02N0401\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 H06E0303\narc: S1_V02S0701 V01N0101\narc: V00B0100 V02S0301\narc: V00T0000 V02N0401\narc: V00T0100 V02S0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 V02N0501\narc: H01W0100 W3_H06E0303\narc: S3_V06S0203 W3_H06E0203\narc: W1_H02W0101 W3_H06E0103\narc: B0 H00R0100\narc: B1 H01W0100\narc: B6 S1_V02N0701\narc: B7 V01S0000\narc: C4 V00T0000\narc: C5 W1_H02E0401\narc: C6 V00B0100\narc: C7 V00T0100\narc: CE0 H00L0000\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D4 E1_H02W0001\narc: D5 E1_H02W0201\narc: D6 H00L0100\narc: D7 N1_V02S0601\narc: E1_H01E0101 F4\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N3_V06N0303 Q6\narc: S1_V02S0101 Q1\narc: V01S0000 Q6\narc: W1_H02W0701 F5\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R18C56:PLC2\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 N1_V02S0001\narc: H00L0100 N1_V02S0301\narc: H00R0000 H02E0401\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 N1_V01S0000\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0103 N1_V02S0201\narc: V00B0000 V02N0001\narc: V00B0100 W1_H02E0701\narc: V00T0100 H02E0101\narc: W1_H02W0101 H01E0101\narc: W1_H02W0401 S1_V02N0401\narc: H01W0000 W3_H06E0103\narc: N1_V02N0001 W3_H06E0003\narc: W1_H02W0001 W3_H06E0003\narc: W3_H06W0003 E1_H01W0000\narc: A3 V00B0000\narc: A5 V00T0100\narc: B0 V02N0301\narc: B3 N1_V02S0301\narc: B5 H00L0000\narc: B6 S1_V02N0501\narc: C0 H00L0100\narc: C3 W1_H02E0401\narc: C5 V00B0100\narc: C6 N1_V02S0001\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 H00R0000\narc: D3 W1_H02E0001\narc: D5 H02E0201\narc: D6 E1_H02W0001\narc: D7 H02W0201\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M0 E1_H02W0601\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0201 Q0\narc: N1_V02N0701 Q5\narc: V01S0000 Q3\narc: V01S0100 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111111000000010\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111111000000010\nword: SLICED.K0.INIT 1100111111000000\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111110000001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R18C57:PLC2\narc: E1_H02E0601 N1_V01S0000\narc: H00L0000 N1_V02S0001\narc: H00R0000 H02E0601\narc: H00R0100 H02E0501\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0301 H06E0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H06E0203\narc: V00B0000 H02E0401\narc: V00B0100 V02S0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0701 S3_V06N0203\narc: W3_H06W0203 N3_V06S0203\narc: B0 V00B0000\narc: B1 H01W0100\narc: B6 H02W0301\narc: B7 V01S0000\narc: C0 H00L0000\narc: C1 V02S0401\narc: C6 N1_V02S0001\narc: C7 N1_V02S0201\narc: CE0 H00R0100\narc: CE2 V02S0601\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H00R0000\narc: D6 W1_H02E0001\narc: D7 N1_V02S0601\narc: E3_H06E0103 F1\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q0\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: N1_V02N0001 Q0\narc: N1_V02N0601 Q4\narc: N3_V06N0203 Q4\narc: N3_V06N0303 Q6\narc: S3_V06S0003 Q0\narc: V01S0000 Q6\narc: W3_H06W0003 Q0\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1100111111000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R18C58:PLC2\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0601 H02E0601\narc: N3_V06N0103 S1_V02N0201\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 W3_H06E0203\narc: W1_H02W0601 W3_H06E0303\n\n.tile R18C59:PLC2\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0001 W3_H06E0003\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\n\n.tile R18C5:PLC2\narc: E1_H02E0401 E1_H01W0000\narc: H00L0000 N1_V02S0201\narc: H00R0000 N1_V02S0401\narc: H00R0100 N1_V02S0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 E1_H02W0301\narc: S1_V02S0101 N3_V06S0103\narc: V00T0100 V02S0501\narc: V01S0000 S3_V06N0103\narc: A3 V00B0000\narc: A4 E1_H02W0701\narc: A5 E1_H01W0000\narc: B3 W1_H02E0301\narc: B4 V00B0100\narc: B5 V02N0501\narc: C3 H00R0100\narc: C4 H02W0601\narc: C5 V00T0100\narc: CE0 H02E0101\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: D4 H01W0000\narc: D5 H02E0201\narc: E1_H02E0601 Q6\narc: E3_H06E0003 Q0\narc: E3_H06E0203 F4\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F3\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M0 E1_H02W0601\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: V00B0000 Q6\narc: V00B0100 F5\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R18C60:PLC2\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 H06E0203\narc: S1_V02S0201 W3_H06E0103\narc: S3_V06S0003 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\n\n.tile R18C61:PLC2\narc: S3_V06S0203 W3_H06E0203\n\n.tile R18C63:PLC2\narc: S3_V06S0003 H06E0003\narc: S3_V06S0203 H06E0203\n\n.tile R18C65:PLC2\narc: E3_H06E0103 W3_H06E0103\n\n.tile R18C66:PLC2\narc: S3_V06S0003 W3_H06E0003\n\n.tile R18C69:PLC2\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\n\n.tile R18C6:PLC2\narc: E1_H02E0701 E3_H06W0203\narc: H00L0100 V02S0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 N1_V02S0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 N3_V06S0303\narc: V00B0000 V02N0001\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V02S0601\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CE2 H00L0100\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: E1_H02E0401 Q6\narc: H01W0000 Q4\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 H02W0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q0\narc: N1_V02N0201 Q2\narc: V00T0000 Q0\narc: V01S0100 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R18C7:PLC2\narc: E1_H02E0401 V01N0001\narc: E1_H02E0601 E1_H01W0000\narc: H00R0000 H02W0601\narc: H00R0100 H02W0501\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 H06W0103\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02S0201\narc: V00T0100 H02W0101\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 E1_H01W0100\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00B0000\narc: M2 W1_H02E0601\narc: M4 H02E0401\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q6\narc: N3_V06N0203 Q4\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R18C8:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0303 N3_V06S0303\narc: H00L0100 V02N0101\narc: H00R0100 V02S0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H01E0101\narc: S1_V02S0001 H06E0003\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 H02W0601\narc: V00B0100 W1_H02E0701\narc: V00T0000 H02W0001\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 N3_V06S0303\narc: E1_H02E0001 W3_H06E0003\narc: A7 H00R0000\narc: B7 V00T0000\narc: C7 V02N0201\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: H01W0100 F7\narc: LSR1 E1_H02W0501\narc: M0 H02E0601\narc: M2 V00B0100\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R18C9:PLC2\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 E1_H01W0000\narc: H00R0000 H02E0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0101 H02W0101\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0001 H02E0001\narc: S1_V02S0301 H02W0301\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: W1_H02W0601 N1_V02S0601\narc: W3_H06W0003 E1_H01W0000\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H02E0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: E3_H06E0003 Q0\narc: H01W0000 Q4\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 H02W0601\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q0\narc: N1_V02N0401 Q6\narc: V00T0000 Q2\narc: W1_H02W0001 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R19C10:PLC2\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 V02S0201\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 N1_V01S0100\narc: S1_V02S0001 H06W0003\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0601 H06W0303\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02N0301\narc: V00T0000 V02N0601\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 V06S0103\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 N1_V01S0100\narc: W3_H06W0303 E3_H06W0303\narc: CE0 V02S0201\narc: CE1 V02S0201\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 H02W0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: S1_V02S0401 Q4\narc: V01S0000 Q6\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R19C11:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V01N0001\narc: H00L0000 H02W0201\narc: H00R0000 V02S0601\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0303 H06E0303\narc: V00B0000 H02E0401\narc: V00B0100 H02W0501\narc: V00T0000 S1_V02N0601\narc: V00T0100 V02S0701\narc: W1_H02W0401 E1_H02W0401\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0203 S3_V06N0203\narc: B3 H01W0100\narc: B5 H00L0000\narc: B7 H02W0101\narc: C3 H00L0000\narc: C5 V00T0000\narc: C7 V00B0100\narc: CE0 V02S0201\narc: CE1 H00R0000\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D5 V00B0000\narc: D7 N1_V02S0601\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0203 Q7\narc: V01S0000 Q3\narc: V01S0100 Q5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111001111000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111001111000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100111111000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R19C12:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: H00L0000 H02E0001\narc: H00R0000 V02N0401\narc: N1_V02N0401 S1_V02N0101\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 H02W0601\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02N0201\narc: V00B0100 V02N0301\narc: V00T0000 S1_V02N0401\narc: V00T0100 E1_H02W0301\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0501 E1_H02W0501\narc: W3_H06W0203 S3_V06N0203\narc: A1 V01N0101\narc: A4 F5\narc: A5 V00T0000\narc: A7 H00R0000\narc: B1 V00B0000\narc: B4 F1\narc: B5 V02S0701\narc: B7 H02W0101\narc: C1 H00L0000\narc: C4 E1_H02W0601\narc: C5 H02E0401\narc: C7 V02N0001\narc: CE1 V02S0201\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D4 V02S0601\narc: D5 H02W0201\narc: D7 H02E0201\narc: E1_H01E0101 F4\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: LSR0 W1_H02E0301\narc: M2 W1_H02E0601\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N3_V06N0303 F6\narc: V01S0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000110100001000\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 0000110100001000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0100000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R19C13:PLC2\narc: E1_H02E0601 N3_V06S0303\narc: H00L0000 S1_V02N0001\narc: H00R0100 V02N0501\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 N1_V01S0000\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 S3_V06N0103\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 H02W0701\narc: V00T0100 V02N0701\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 V01N0001\narc: W3_H06W0003 N3_V06S0003\narc: W3_H06W0303 E1_H01W0100\narc: B0 H02E0301\narc: B1 V00T0000\narc: B4 V01S0000\narc: B6 E1_H02W0301\narc: C0 V02N0601\narc: C1 H02E0401\narc: C4 V00B0100\narc: C5 F4\narc: C6 H02W0401\narc: C7 F6\narc: CE1 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 N1_V01S0000\narc: D1 V01S0100\narc: D4 H02E0001\narc: D5 H01W0000\narc: D6 H02E0001\narc: D7 H00R0100\narc: E1_H01E0001 F0\narc: E1_H01E0101 F4\narc: E3_H06E0103 F1\narc: E3_H06E0203 F4\narc: E3_H06E0303 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q6\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F6\narc: N1_V01N0101 Q4\narc: N1_V02N0701 F7\narc: N3_V06N0303 F5\narc: S1_V02S0101 F1\narc: S1_V02S0401 F4\narc: S3_V06S0103 Q2\narc: S3_V06S0203 F4\narc: V00T0000 Q0\narc: V01S0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICEA.K0.INIT 1100000000000000\nword: SLICEA.K1.INIT 0011000000111111\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0000000000001111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R19C14:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 W1_H02E0501\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0401 W1_H02E0401\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 H02E0601\narc: V00T0100 W1_H02E0101\narc: W1_H02W0101 H01E0101\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V02N0601\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0203 S3_V06N0203\narc: W3_H06W0303 S3_V06N0303\narc: E3_H06E0003 W3_H06E0303\narc: B5 W1_H02E0101\narc: B7 H02W0101\narc: C5 H02W0401\narc: C7 V00T0100\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D5 S1_V02N0401\narc: D7 V00B0000\narc: E1_H01E0101 Q5\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W1_H02W0701 Q7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100111111000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111001111000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R19C15:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 S1_V02N0301\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02S0201\narc: H00R0100 V02S0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H06E0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 H02W0401\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02W0201\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0701 V06S0203\narc: N1_V02N0001 W3_H06E0003\narc: B1 V00T0000\narc: B3 H02W0101\narc: B7 V00B0000\narc: C1 H02W0401\narc: C3 H02W0401\narc: C7 V00B0100\narc: CE0 V02S0201\narc: CE1 V02S0201\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: D3 V02N0201\narc: D7 H00R0100\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0301 Q1\narc: S1_V02S0701 Q7\narc: V01S0100 Q3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111001111000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100111111000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100111111000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R19C16:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0501 V02S0501\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 H02E0201\narc: H00R0000 S1_V02N0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 H06E0203\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 V01N0001\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02S0301\narc: V00T0000 V02S0601\narc: V00T0100 V02N0701\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0601 V06S0303\narc: W3_H06W0303 E3_H06W0303\narc: A0 V02S0701\narc: A1 V02S0701\narc: A2 V02S0701\narc: A3 V02S0701\narc: A4 N1_V02S0301\narc: A5 E1_H02W0701\narc: B0 V01N0001\narc: B1 V01N0001\narc: B2 V01N0001\narc: B3 V01N0001\narc: B4 V02N0501\narc: B5 W1_H02E0301\narc: B7 N1_V02S0701\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 V02N0201\narc: C5 V00B0100\narc: C6 H02W0601\narc: C7 F6\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CLK1 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 V00B0000\narc: D5 N1_V02S0601\narc: D6 V02N0401\narc: D7 H02W0201\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q1\narc: E3_H06E0003 Q0\narc: E3_H06E0203 F7\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: LSR0 V00T0000\narc: LSR1 V00T0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q3\narc: N3_V06N0003 Q0\narc: S1_V02S0601 F6\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 1111001100110011\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R19C17:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 H02W0201\narc: H00L0100 H02E0301\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02S0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 E1_H02W0401\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02E0701\narc: V00T0000 H02W0001\narc: V00T0100 V02N0501\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0601 E3_H06W0303\narc: A2 H01E0001\narc: A6 V02N0301\narc: A7 H02W0501\narc: B1 V02S0101\narc: B2 W1_H02E0101\narc: B6 H02W0301\narc: B7 H02E0101\narc: C1 H00L0000\narc: C2 H00L0100\narc: C6 V00B0100\narc: C7 H02W0401\narc: CE0 H00R0100\narc: CE2 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: D2 H00R0000\narc: D6 S1_V02N0401\narc: D7 V00B0000\narc: E1_H02E0401 F6\narc: E3_H06E0103 F2\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M2 V00T0100\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V02N0601 Q4\narc: S1_V02S0301 Q1\narc: S3_V06S0203 Q4\narc: V01S0100 Q4\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100111111000000\nword: SLICED.K0.INIT 0011111101011111\nword: SLICED.K1.INIT 1100000010100000\nword: SLICEB.K0.INIT 0011111101011111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R19C18:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 S3_V06N0003\narc: H00L0000 E1_H02W0201\narc: H00L0100 H02W0101\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 V01N0101\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 N1_V01S0100\narc: S3_V06S0103 H06W0103\narc: V00B0100 H02W0701\narc: W1_H02W0001 V06N0003\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 N1_V01S0100\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: A0 V02S0701\narc: A1 V02S0501\narc: A2 H00L0100\narc: A3 H02E0501\narc: A5 V00T0100\narc: A7 E1_H01W0000\narc: B0 H02E0301\narc: B1 H02W0301\narc: B2 V02S0301\narc: B3 H02E0101\narc: B5 V01S0000\narc: B7 E1_H02W0101\narc: C0 H02E0601\narc: C1 H00L0000\narc: C2 H00L0000\narc: C3 H02E0601\narc: C5 V00B0100\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 H02E0201\narc: D2 H02E0201\narc: D3 S1_V02N0201\narc: D5 V02N0601\narc: D7 W1_H02E0001\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M4 H02W0401\narc: M6 H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 F3\narc: N1_V02N0201 F2\narc: N3_V06N0203 Q4\narc: N3_V06N0303 Q6\narc: V00T0100 F1\narc: V01S0000 F0\nword: SLICEB.K0.INIT 1100101000000000\nword: SLICEB.K1.INIT 0011111101011111\nword: SLICEA.K0.INIT 0011111101011111\nword: SLICEA.K1.INIT 0011010111111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111111111110111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R19C19:PLC2\narc: E1_H02E0201 V06N0103\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 V02S0701\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 V02N0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02W0401\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02W0501\narc: V00T0000 V02S0601\narc: V00T0100 V02S0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V06N0003\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V02S0501\narc: W1_H02W0701 N1_V02S0701\narc: N3_V06N0203 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: A0 V02S0701\narc: A1 V02S0701\narc: A2 V02S0701\narc: A3 V02S0701\narc: A4 V00T0100\narc: A5 H02E0701\narc: A6 V02S0301\narc: A7 H00L0000\narc: B0 V02N0301\narc: B1 V02N0101\narc: B2 V02N0101\narc: B3 V02N0301\narc: B4 S1_V02N0701\narc: B5 H02E0301\narc: B6 V02N0701\narc: B7 S1_V02N0501\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V00B0100\narc: C5 H02W0601\narc: C6 V02N0001\narc: C7 V02S0201\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CLK1 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 E1_H02W0201\narc: D2 E1_H02W0201\narc: D3 E1_H02W0201\narc: D4 S1_V02N0401\narc: D5 V02N0601\narc: D6 H02W0001\narc: D7 W1_H02E0201\narc: E1_H01E0101 F6\narc: E3_H06E0003 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: LSR0 V00T0000\narc: LSR1 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q3\narc: N3_V06N0003 Q0\narc: S3_V06S0103 Q2\narc: W1_H02W0101 Q1\nword: SLICED.K0.INIT 1010000011000000\nword: SLICED.K1.INIT 0011010111111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R19C20:PLC2\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V02N0701\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 H02W0301\narc: H00R0000 S1_V02N0401\narc: H00R0100 H02W0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 H02E0401\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02E0601\narc: V00B0100 H02W0501\narc: V00T0000 H02E0201\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 E1_H02W0301\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A0 H02E0701\narc: A1 H02E0701\narc: A2 H02E0701\narc: A3 H02E0701\narc: A4 H02E0701\narc: A5 V00T0000\narc: A7 H02E0501\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 H00R0000\narc: B5 W1_H02E0101\narc: B7 H02E0301\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V00B0100\narc: C5 N1_V02S0201\narc: C7 V02N0001\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CLK1 G_HPBX0000\narc: D0 V02S0001\narc: D1 V02S0001\narc: D2 V02S0001\narc: D3 V02S0001\narc: D4 H02W0001\narc: D5 V00B0000\narc: D7 V02S0401\narc: E1_H01E0001 F2\narc: E1_H01E0101 F7\narc: E1_H02E0001 Q2\narc: E1_H02E0101 F1\narc: E1_H02E0201 F0\narc: E1_H02E0301 Q3\narc: E3_H06E0003 Q3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q1\narc: H01W0100 Q3\narc: LSR0 W1_H02E0501\narc: LSR1 V00T0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q0\narc: S3_V06S0103 Q2\narc: V01S0000 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000010000100001\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R19C21:PLC2\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 H01E0001\narc: E3_H06E0003 V01N0001\narc: H00R0100 V02S0701\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 S1_V02N0301\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 V01N0101\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 H02W0601\narc: V00B0100 S1_V02N0301\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 V06S0203\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: A0 W1_H02E0701\narc: A1 W1_H02E0701\narc: A2 W1_H02E0701\narc: A3 W1_H02E0701\narc: A4 W1_H02E0701\narc: A5 V02S0101\narc: A7 V00T0100\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 V02N0701\narc: B7 V00T0000\narc: C0 N1_V01S0100\narc: C1 N1_V01S0100\narc: C2 N1_V01S0100\narc: C3 N1_V01S0100\narc: C4 N1_V02S0201\narc: C5 S1_V02N0001\narc: C7 E1_H01E0101\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CLK1 G_HPBX0000\narc: D0 V02S0001\narc: D1 V02S0001\narc: D2 V02S0001\narc: D3 V02S0001\narc: D4 V02S0601\narc: D5 H02W0001\narc: D7 F2\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F1\narc: E1_H02E0001 Q2\narc: E1_H02E0101 Q1\narc: E1_H02E0701 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F0\narc: LSR0 V00B0000\narc: LSR1 H02E0501\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 Q0\narc: S1_V02S0301 Q1\narc: V00T0000 Q2\narc: V00T0100 Q1\narc: V01S0100 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000010000100001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R19C22:PLC2\narc: E1_H02E0201 H01E0001\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00R0000 V02N0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 W1_H02E0301\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 H06E0103\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0401 E1_H01W0000\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 V02S0201\narc: V00T0000 W1_H02E0001\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 V06S0003\narc: W1_H02W0601 V02S0601\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0401 W3_H06E0203\narc: S1_V02S0601 W3_H06E0303\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0303 E3_H06W0203\narc: A1 H01E0001\narc: A2 W1_H02E0701\narc: A3 V00T0000\narc: A5 H02E0501\narc: A6 H00R0000\narc: A7 H02E0501\narc: B1 V02S0301\narc: B2 V02N0101\narc: B3 H00R0100\narc: B5 E1_H02W0301\narc: B6 V02N0701\narc: B7 E1_H02W0301\narc: C1 W1_H02E0401\narc: C2 H00L0100\narc: C3 H02E0601\narc: C5 V00T0100\narc: C6 E1_H01E0101\narc: C7 V00T0100\narc: D1 W1_H02E0201\narc: D2 V01S0100\narc: D3 V00B0100\narc: D5 V00B0000\narc: D6 V02S0401\narc: D7 V00B0000\narc: E1_H01E0101 F7\narc: E1_H02E0001 F2\narc: E1_H02E0601 F6\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: V00B0100 F5\narc: V01S0100 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000010000100001\nword: SLICEB.K0.INIT 1001000000000000\nword: SLICEB.K1.INIT 1000010000000000\nword: SLICED.K0.INIT 1001000000000000\nword: SLICED.K1.INIT 1111010100110001\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000110010101111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R19C23:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0401 W1_H02E0101\narc: E3_H06E0203 V01N0001\narc: H00L0000 N1_V02S0001\narc: H00L0100 H02W0101\narc: H00R0100 V02S0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0601 H02W0601\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0101 V01N0101\narc: S3_V06S0103 E3_H06W0103\narc: V00T0000 H02E0201\narc: E1_H02E0601 W3_H06E0303\narc: N1_V02N0201 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: A0 H00L0000\narc: A2 V00T0000\narc: A3 N1_V02S0501\narc: A4 V02N0301\narc: A6 N1_V01N0101\narc: A7 S1_V02N0301\narc: B0 F1\narc: B2 V02S0301\narc: B3 W1_H02E0301\narc: B4 V00B0100\narc: B6 V01S0000\narc: B7 S1_V02N0501\narc: C0 H00L0100\narc: C1 N1_V01S0100\narc: C2 V02N0601\narc: C3 H02E0601\narc: C4 W1_H02E0401\narc: C5 V02S0201\narc: C6 E1_H01E0101\narc: C7 S1_V02N0201\narc: D0 V02N0001\narc: D1 V02S0201\narc: D2 V00T0100\narc: D3 H02E0001\narc: D4 H02W0001\narc: D5 H00R0100\narc: D6 V00B0000\narc: D7 S1_V02N0601\narc: E1_H01E0101 F7\narc: E3_H06E0003 F3\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: N1_V01N0101 F2\narc: N1_V02N0701 F5\narc: N3_V06N0103 F1\narc: N3_V06N0303 F6\narc: S1_V02S0701 F5\narc: V00B0000 F4\narc: V00B0100 F5\narc: V00T0100 F3\narc: V01S0000 F0\narc: W3_H06W0103 F1\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 0111001101111111\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICEA.K0.INIT 0111001101111111\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0100111101111111\nword: SLICEB.K1.INIT 0010101010101010\nword: SLICED.K0.INIT 0000100000000000\nword: SLICED.K1.INIT 1011000010000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R19C24:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 V02S0301\narc: H00R0000 V02S0601\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 H06W0103\narc: V00B0000 H02E0401\narc: V00B0100 H02W0701\narc: V00T0000 H02E0001\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V02N0601\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A6 N1_V01N0101\narc: A7 H00L0000\narc: B6 V01S0000\narc: B7 H02W0301\narc: C6 H02E0401\narc: C7 H02W0401\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: D6 H02E0001\narc: D7 H00L0100\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: LSR0 W1_H02E0501\narc: LSR1 E1_H02W0301\narc: M0 V00B0100\narc: M2 V00B0000\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q2\narc: N1_V02N0501 F7\narc: N1_V02N0601 F6\narc: V01S0000 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1000010000100001\nword: SLICED.K1.INIT 1000010000100001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R19C25:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 H02E0201\narc: H00L0100 V02S0101\narc: H00R0000 H02E0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0003 N1_V02S0001\narc: V00B0000 V02N0201\narc: V00B0100 V02N0101\narc: W1_H02W0301 N1_V01S0100\narc: E1_H01E0001 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: B3 H00L0000\narc: C3 V02N0601\narc: CE0 H02E0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: E1_H01E0101 Q6\narc: E1_H02E0201 Q0\narc: F3 F3_SLICE\narc: M0 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0101 F3\narc: N3_V06N0003 F3\narc: V01S0100 Q0\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R19C26:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 N1_V02S0201\narc: H00R0100 S1_V02N0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H01E0001\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0401\narc: V00B0000 E1_H02W0401\narc: V00T0000 S1_V02N0401\narc: V00T0100 H02W0301\narc: W1_H02W0301 V02S0301\narc: N1_V02N0301 W3_H06E0003\narc: W3_H06W0203 V06S0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: CE0 W1_H02E0101\narc: CE1 H00R0100\narc: CE2 H02E0101\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q0\narc: E3_H06E0303 Q6\narc: H01W0100 Q4\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: S1_V02S0001 Q2\narc: V01S0000 Q6\narc: V01S0100 Q0\narc: W3_H06W0003 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R19C27:PLC2\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0701 V02N0701\narc: E3_H06E0103 W1_H02E0201\narc: H00L0100 H02E0301\narc: H00R0000 H02W0601\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0203 H01E0001\narc: V00B0000 H02W0601\narc: V00B0100 H02W0501\narc: V00T0000 H02E0201\narc: V00T0100 E1_H02W0301\narc: W1_H02W0301 S1_V02N0301\narc: N3_V06N0303 W3_H06E0303\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: A3 H00L0100\narc: A5 W1_H02E0501\narc: A6 E1_H02W0701\narc: B1 V02S0101\narc: B3 V02N0101\narc: B5 V01S0000\narc: B6 V02N0501\narc: C0 W1_H02E0401\narc: C1 F6\narc: C2 V02N0601\narc: C3 H02E0601\narc: C5 H02E0601\narc: C6 V00T0100\narc: C7 V00T0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 H02E0201\narc: D2 V00B0100\narc: D3 H00R0000\narc: D5 V00B0000\narc: D6 V02S0601\narc: D7 H01W0000\narc: E1_H01E0001 F5\narc: E1_H01E0101 F2\narc: E1_H02E0001 F2\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H01W0000 F6\narc: H01W0100 F1\narc: LSR0 H02E0501\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: S3_V06S0003 F3\narc: S3_V06S0103 F2\narc: V01S0000 F2\narc: V01S0100 F2\narc: W3_H06W0103 F2\narc: W3_H06W0203 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000100000\nword: SLICED.K0.INIT 0100000000000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000000000001111\nword: SLICEB.K1.INIT 0000000000100000\nword: SLICEA.K0.INIT 1111111100001111\nword: SLICEA.K1.INIT 0011001111110011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R19C28:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 V06N0303\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H01E0101\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 H02W0601\narc: V00B0100 H02E0701\narc: V00T0000 H02E0001\narc: W1_H02W0001 H01E0001\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 E1_H02W0601\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: S1_V02S0001 W3_H06E0003\narc: S1_V02S0401 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: A1 E1_H01E0001\narc: B1 V00T0000\narc: C1 W1_H02E0601\narc: CE1 W1_H02E0101\narc: CE2 S1_V02N0601\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: E1_H01E0001 Q6\narc: E3_H06E0203 Q4\narc: F1 F1_SLICE\narc: M2 E1_H02W0601\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0101 F1\narc: S3_V06S0103 Q2\narc: W1_H02W0401 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000100000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R19C29:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 N1_V01S0000\narc: H00R0100 V02N0501\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02E0601\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 E1_H02W0301\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N1_V01S0100\narc: V00B0100 S1_V02N0101\narc: V00T0100 V02N0701\narc: V01S0100 S3_V06N0303\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0203 S3_V06N0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: CE0 H02W0101\narc: CE1 S1_V02N0201\narc: CE2 H00R0100\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: H01W0100 Q6\narc: M0 V00B0100\narc: M2 V00T0100\narc: M4 H02W0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: S3_V06S0203 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R19C2:PLC2\narc: E1_H02E0401 N1_V01S0000\narc: N1_V02N0201 H02W0201\narc: S1_V02S0301 H02E0301\narc: S3_V06S0103 N1_V01S0100\n\n.tile R19C30:PLC2\narc: E1_H02E0101 V02N0101\narc: E3_H06E0303 H01E0101\narc: H00L0100 V02S0301\narc: H00R0100 H02W0701\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0601 S1_V02N0301\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 H06E0103\narc: S1_V02S0501 E1_H02W0501\narc: V00B0000 H02E0401\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02W0001\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 E3_H06W0303\narc: N3_V06N0303 W3_H06E0303\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0203 E3_H06W0103\narc: A5 V00B0000\narc: A7 W1_H02E0701\narc: B1 V02N0301\narc: B4 N1_V01S0000\narc: B5 H02E0301\narc: B7 H01E0101\narc: C0 N1_V01S0100\narc: C1 H00L0100\narc: C4 H02E0401\narc: C5 E1_H01E0101\narc: C7 H02E0601\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 V00B0100\narc: D4 V02N0601\narc: D5 V02S0401\narc: D7 H02E0001\narc: E1_H01E0001 F0\narc: E1_H01E0101 F7\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: M2 V00T0000\narc: MUXCLK1 CLK0\narc: N3_V06N0203 F4\narc: S3_V06S0003 F0\narc: S3_V06S0303 F5\narc: V01S0000 F5\narc: W3_H06W0003 F0\narc: W3_H06W0103 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000111111\nword: SLICEC.K1.INIT 0111000000000000\nword: SLICEA.K0.INIT 0000111111111111\nword: SLICEA.K1.INIT 0011111111111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R19C31:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0601 V02N0601\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 V02N0001\narc: H00L0100 V02N0301\narc: H00R0000 H02W0601\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 V01N0101\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 H06W0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0203 H06E0203\narc: V00B0000 V02N0201\narc: V00B0100 V02N0101\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: E1_H01E0001 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: A7 H00L0000\narc: B7 V00B0000\narc: C7 V02S0201\narc: CE1 H02W0101\narc: CLK0 G_HPBX0000\narc: D7 S1_V02N0401\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00L0100\narc: M2 V00B0100\narc: M3 H00R0000\narc: M4 V00B0100\narc: M5 H00L0100\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: N1_V02N0301 Q3\narc: N3_V06N0003 Q3\narc: V01S0100 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111111111111111\nword: SLICED.K1.INIT 0111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R19C32:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V01N0101\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0203 H01E0001\narc: H00L0000 N1_V02S0001\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 H06W0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0201\narc: V00B0100 V02S0301\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 E1_H02W0301\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A1 V02S0701\narc: B1 E1_H02W0101\narc: C1 N1_V01S0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: E1_H01E0101 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 V00B0000\narc: M1 H00L0000\narc: M2 V00B0000\narc: M4 E1_H02W0401\narc: MUXCLK2 CLK0\narc: S3_V06S0103 F1\narc: W3_H06W0103 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0001000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R19C33:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0701 V02N0701\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 H02E0201\narc: H00R0000 S1_V02N0401\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 H06W0003\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 S1_V02N0301\narc: N3_V06N0003 E1_H01W0000\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 H01E0101\narc: S3_V06S0003 H06W0003\narc: S3_V06S0303 N1_V02S0501\narc: V00T0100 S1_V02N0701\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 E1_H02W0701\narc: N1_V02N0401 W3_H06E0203\narc: S1_V02S0601 W3_H06E0303\narc: A2 V02N0501\narc: A3 V00T0000\narc: A4 H02E0701\narc: A5 H02E0501\narc: A7 H02W0501\narc: B0 E1_H02W0301\narc: B2 H02E0101\narc: B3 H01W0100\narc: B4 W1_H02E0301\narc: B5 H00L0000\narc: B7 V02S0501\narc: C0 N1_V01N0001\narc: C1 H02E0401\narc: C2 W1_H02E0601\narc: C3 N1_V01S0100\narc: C4 E1_H02W0401\narc: C5 H01E0001\narc: C7 V02N0001\narc: CE0 V02N0201\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 N1_V02S0001\narc: D2 V00T0100\narc: D3 V02S0001\narc: D4 H00R0100\narc: D5 H02E0001\narc: D7 V02N0601\narc: E1_H01E0001 F1\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0000 F3\narc: H01W0100 F4\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F1\narc: N1_V02N0701 F7\narc: S1_V02S0001 F2\narc: S3_V06S0103 F1\narc: V00T0000 F2\narc: V01S0000 F1\narc: V01S0100 F1\narc: W1_H02W0101 F1\narc: W3_H06W0003 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000010101010\nword: SLICEC.K0.INIT 0000000100000000\nword: SLICEC.K1.INIT 0000000000000001\nword: SLICEB.K0.INIT 0000000000000001\nword: SLICEB.K1.INIT 0000100000000000\nword: SLICEA.K0.INIT 1100000011001111\nword: SLICEA.K1.INIT 0000111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R19C34:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 H01E0001\narc: E1_H02E0701 S3_V06N0203\narc: E3_H06E0003 H01E0001\narc: E3_H06E0203 H01E0001\narc: H00L0000 E1_H02W0001\narc: H00R0000 V02N0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N1_V02S0401\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 H06W0303\narc: V00B0100 V02N0301\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 S3_V06N0203\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0601 W3_H06E0303\narc: S3_V06S0203 W3_H06E0203\narc: W3_H06W0203 N3_V06S0203\narc: W3_H06W0303 N1_V01S0100\narc: A1 V02N0501\narc: A3 E1_H01E0001\narc: A5 N1_V02S0301\narc: B1 H00R0100\narc: B3 H01W0100\narc: B4 H00L0000\narc: B5 H00R0000\narc: B6 V02S0501\narc: C0 H00L0100\narc: C1 V02N0401\narc: C3 N1_V01S0100\narc: C4 H02W0601\narc: C5 V00T0100\narc: C6 E1_H02W0401\narc: C7 E1_H01E0101\narc: CE0 V02S0201\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 S1_V02N0001\narc: D3 E1_H02W0001\narc: D4 H02E0001\narc: D5 V00B0000\narc: D6 E1_H02W0201\narc: D7 N1_V02S0601\narc: E1_H01E0001 Q5\narc: E1_H01E0101 Q6\narc: E3_H06E0103 Q1\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: H01W0000 Q1\narc: H01W0100 Q6\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M2 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q5\narc: N1_V02N0401 F4\narc: N1_V02N0601 Q6\narc: S1_V02S0201 F0\narc: S1_V02S0601 Q6\narc: V00B0000 F4\narc: V01S0000 F7\narc: V01S0100 F0\narc: W1_H02W0001 F0\narc: W1_H02W0201 F2\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 0000000011000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0000000000001111\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 1100000011110000\nword: SLICEC.K1.INIT 0010111100100010\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R19C35:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V01N0001\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 S3_V06N0003\narc: H00L0000 N1_V02S0001\narc: H00L0100 E1_H02W0101\narc: H00R0100 S1_V02N0701\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 H01E0101\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: V00T0100 V02S0701\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E1_H02W0701\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0303 E3_H06W0303\narc: A1 H00L0100\narc: B1 V00B0000\narc: C1 H00L0000\narc: D1 V00B0100\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00R0100\narc: M2 V00T0100\narc: M3 H02E0201\narc: M4 V00T0100\narc: M5 H00R0100\narc: M6 V00T0100\narc: S1_V02S0301 F3\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000010000001111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R19C36:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 V01N0001\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0003 H01E0001\narc: E3_H06E0203 H01E0001\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 E1_H02W0201\narc: H00L0100 S1_V02N0301\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 N1_V02S0201\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 H01E0101\narc: V00B0000 E1_H02W0601\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02N0401\narc: V00T0100 V02N0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 E1_H01W0100\narc: E1_H02E0701 W3_H06E0203\narc: W1_H02W0201 W3_H06E0103\narc: A7 H00L0000\narc: B4 H02W0301\narc: B6 E1_H02W0301\narc: B7 E1_H02W0101\narc: C4 V00T0100\narc: C6 W1_H02E0401\narc: C7 V00T0000\narc: CE0 S1_V02N0201\narc: CE1 S1_V02N0201\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D4 H00L0100\narc: D5 V00B0000\narc: D6 V02S0601\narc: D7 V02S0401\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F7\narc: E1_H02E0001 Q0\narc: E3_H06E0103 Q2\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q0\narc: M0 H02W0601\narc: M2 V00B0100\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F4\narc: N1_V01N0101 Q0\narc: N1_V02N0201 Q2\narc: S3_V06S0003 Q0\narc: V01S0100 Q0\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1100000011001111\nword: SLICED.K1.INIT 1101000100010001\nword: SLICEC.K0.INIT 1111000000110011\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R19C37:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 V01N0101\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 V06S0203\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 V02N0201\narc: H00R0000 S1_V02N0601\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 H06E0203\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0401\narc: V00B0100 V02N0301\narc: V00T0000 W1_H02E0201\narc: V00T0100 W1_H02E0301\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 S1_V02N0501\narc: S1_V02S0701 W3_H06E0203\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0203 E3_H06W0103\narc: A1 W1_H02E0701\narc: A2 V00B0000\narc: A3 V01N0101\narc: A4 N1_V01N0101\narc: A5 H02W0701\narc: A7 E1_H01W0000\narc: B1 E1_H01W0100\narc: B2 H00R0000\narc: B3 V02N0101\narc: B4 N1_V02S0701\narc: B5 V02N0501\narc: B7 V00B0100\narc: C1 H00L0000\narc: C2 H00L0100\narc: C3 H02E0401\narc: C4 V00T0100\narc: C5 H02E0601\narc: C7 V02N0001\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 V01S0100\narc: D3 V02N0201\narc: D4 W1_H02E0001\narc: D5 V02N0601\narc: D7 S1_V02N0401\narc: E1_H01E0001 F4\narc: E1_H01E0101 F2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H01W0100 Q5\narc: LSR1 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q5\narc: N1_V02N0201 F2\narc: N1_V02N0501 Q5\narc: N3_V06N0303 Q5\narc: S1_V02S0501 Q5\narc: V01S0000 Q5\narc: V01S0100 F7\narc: W1_H02W0701 F5\narc: W3_H06W0303 Q5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000001001000001\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000010000100001\nword: SLICEB.K0.INIT 1001000000000000\nword: SLICEB.K1.INIT 1001000000001001\nword: SLICEC.K0.INIT 1000000010101010\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R19C38:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V02S0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 H01E0001\narc: H00L0000 W1_H02E0201\narc: H00L0100 H02E0301\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N1_V02S0101\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 H02W0501\narc: V00T0000 H02E0201\narc: V00T0100 W1_H02E0301\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 V02N0601\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0201 W3_H06E0103\narc: W1_H02W0501 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A2 V00B0000\narc: A3 H02W0701\narc: B2 H02E0101\narc: B3 V02N0101\narc: C2 N1_V02S0601\narc: C3 H02E0601\narc: CE0 H00L0000\narc: CE2 H00L0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 V00B0100\narc: E1_H01E0101 Q0\narc: E1_H02E0201 Q0\narc: E1_H02E0401 Q4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0000 Q6\narc: H01W0100 Q0\narc: M0 E1_H02W0601\narc: M4 V00T0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F3\narc: N1_V01N0101 Q6\narc: N1_V02N0001 F2\narc: N1_V02N0401 Q6\narc: V00B0000 Q4\narc: V01S0000 Q6\narc: V01S0100 Q4\narc: W3_H06W0003 Q0\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1000001001000001\nword: SLICEB.K1.INIT 1001000000001001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R19C39:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V06N0203\narc: H00R0000 N1_V02S0401\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 H06E0303\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 H02W0701\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 N1_V02S0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02S0601\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 H01E0101\narc: H01W0000 W3_H06E0103\narc: S1_V02S0101 W3_H06E0103\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: H01W0100 Q2\narc: LSR0 V00B0100\narc: M0 H02E0601\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q0\narc: N1_V02N0401 Q4\narc: N1_V02N0601 Q4\narc: S3_V06S0003 Q0\narc: V01S0000 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R19C3:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0701 V02S0701\narc: H00R0000 V02N0601\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0201 N3_V06S0103\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 H02W0601\narc: W1_H02W0201 N3_V06S0103\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: M2 H02W0601\narc: MUXCLK1 CLK0\narc: V01S0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R19C40:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 N1_V02S0001\narc: H00L0100 H02W0101\narc: H00R0000 H02E0401\narc: H00R0100 H02E0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H01E0101\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H06W0303\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 V01N0001\narc: V00B0000 H02W0601\narc: V00B0100 V02N0301\narc: V00T0100 N1_V02S0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: W3_H06W0203 E1_H02W0401\narc: A0 H00L0100\narc: A3 N1_V02S0501\narc: A7 H02W0701\narc: B0 V00B0000\narc: B2 H02W0301\narc: B3 H00L0000\narc: B4 E1_H02W0101\narc: B6 S1_V02N0501\narc: B7 S1_V02N0701\narc: C0 N1_V01N0001\narc: C2 N1_V02S0601\narc: C3 V02S0401\narc: C4 V00T0100\narc: C6 H02E0601\narc: C7 H02E0601\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D2 H02W0201\narc: D3 H02E0001\narc: D4 H02E0001\narc: D5 F2\narc: D6 H00R0100\narc: D7 V02N0601\narc: E1_H01E0001 F6\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F4\narc: LSR1 H02E0301\narc: M0 V00B0100\narc: M4 H02W0401\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F7\narc: S1_V02S0201 F2\narc: S1_V02S0301 F3\narc: V01S0100 F6\narc: W1_H02W0201 Q2\narc: W3_H06W0003 F0\nword: SLICED.K0.INIT 0000110000111111\nword: SLICED.K1.INIT 1001010001001111\nword: SLICEB.K0.INIT 1100000011001111\nword: SLICEB.K1.INIT 0000000100100011\nword: SLICEC.K0.INIT 1111110000001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111010100110001\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R19C41:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 N1_V02S0301\narc: E3_H06E0003 H01E0001\narc: H00L0000 V02N0001\narc: H00R0000 W1_H02E0401\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 H02E0301\narc: S1_V02S0501 S3_V06N0303\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02N0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02N0601\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 V01N0101\narc: E1_H02E0401 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0001 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: A3 V00B0000\narc: A4 S1_V02N0101\narc: A5 S1_V02N0301\narc: B3 V02N0301\narc: B4 H02E0301\narc: B5 E1_H02W0101\narc: B6 S1_V02N0501\narc: B7 V02N0701\narc: C2 H00L0000\narc: C3 E1_H02W0401\narc: C4 E1_H01E0101\narc: C5 S1_V02N0001\narc: C6 H02E0601\narc: C7 H02W0601\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 H02E0001\narc: D3 H02E0001\narc: D4 N1_V02S0601\narc: D5 S1_V02N0601\narc: D6 V02N0401\narc: D7 N1_V02S0401\narc: E1_H01E0001 F6\narc: E1_H01E0101 F5\narc: E1_H02E0701 F7\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00B0100\narc: M2 V00T0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F4\narc: V01S0000 F6\narc: V01S0100 Q6\narc: W1_H02W0201 F2\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000110001\nword: SLICEC.K1.INIT 1001010001001111\nword: SLICED.K0.INIT 1100000011001111\nword: SLICED.K1.INIT 0000111100001100\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 1010100000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R19C42:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 S1_V02N0301\narc: E3_H06E0303 W1_H02E0501\narc: H00L0100 V02N0301\narc: H00R0000 N1_V02S0601\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H01E0001\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 H06E0203\narc: V00B0000 W1_H02E0401\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02W0001\narc: V00T0100 V02S0701\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0601 E1_H02W0301\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0701 W3_H06E0203\narc: S1_V02S0101 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: B0 N1_V02S0101\narc: B2 N1_V02S0301\narc: B4 S1_V02N0501\narc: B5 V01S0000\narc: B7 E1_H02W0101\narc: C0 E1_H02W0601\narc: C2 V02S0601\narc: C4 V00B0100\narc: C5 V00T0000\narc: C7 V00B0100\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 E1_H02W0201\narc: D2 H00R0000\narc: D3 E1_H02W0201\narc: D4 H00L0100\narc: D5 H02E0201\narc: D7 V01N0001\narc: E1_H01E0101 F5\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F5\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00B0000\narc: M2 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F7\narc: N1_V02N0601 F4\narc: S1_V02S0201 F0\narc: V01S0000 Q4\narc: V01S0100 F2\narc: W1_H02W0401 Q4\narc: W3_H06W0203 Q7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100000011001111\nword: SLICEC.K0.INIT 1100000011001111\nword: SLICEC.K1.INIT 0000111100001100\nword: SLICEB.K0.INIT 1100111100000011\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111110000001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R19C43:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V06S0303\narc: H00L0000 S1_V02N0201\narc: H00L0100 V02S0101\narc: H00R0100 V02N0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H06W0203\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 N1_V02S0601\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V06N0203\narc: W1_H02W0701 V06S0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A3 H02W0701\narc: B3 W1_H02E0101\narc: B4 N1_V01S0000\narc: B7 V00B0100\narc: C3 H00L0100\narc: C4 V02N0201\narc: C7 V00T0100\narc: CE0 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D2 H01E0101\narc: D3 N1_V02S0201\narc: D4 H00R0100\narc: D5 V02N0601\narc: D6 H01W0000\narc: D7 H02E0001\narc: E1_H01E0001 F4\narc: E1_H01E0101 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q1\narc: M0 V00B0000\narc: M1 H00L0000\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q6\narc: N1_V02N0101 F1\narc: N1_V02N0601 F6\narc: S1_V02S0401 F6\narc: V01S0000 Q6\narc: W1_H02W0601 F6\narc: W3_H06W0303 F6\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 1111001111000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000110010001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R19C44:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0601 V06N0303\narc: E3_H06E0003 W1_H02E0301\narc: H00L0100 S1_V02N0301\narc: H00R0100 V02S0701\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 V01N0001\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0103\narc: V00B0100 V02N0101\narc: V00T0000 H02W0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 V06S0203\narc: E1_H02E0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: A2 E1_H01E0001\narc: B0 H00R0100\narc: B2 H02E0301\narc: B4 V00B0100\narc: B6 E1_H02W0101\narc: B7 V00B0000\narc: C0 F4\narc: C1 H00L0000\narc: C2 V02S0601\narc: C3 H00L0100\narc: C4 E1_H02W0601\narc: C6 H02E0401\narc: C7 V00T0000\narc: CE0 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 V02S0001\narc: D2 N1_V02S0001\narc: D3 W1_H02E0201\narc: D4 V02N0601\narc: D5 V02N0401\narc: D6 H02E0201\narc: D7 E1_H02W0201\narc: E1_H01E0001 F3\narc: E1_H01E0101 F7\narc: E1_H02E0101 F3\narc: E1_H02E0401 Q6\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0000 F3\narc: H01W0100 Q0\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q0\narc: N1_V02N0001 F2\narc: S1_V02S0601 Q6\narc: S3_V06S0003 F3\narc: S3_V06S0303 Q6\narc: V00B0000 Q6\narc: V01S0100 F1\narc: W1_H02W0301 F3\narc: W1_H02W0401 Q6\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 1100111100000011\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 1010001010000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 0000001111001111\nword: SLICEC.K0.INIT 0000001111001111\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R19C45:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0601 H01E0001\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 H01E0001\narc: E3_H06E0303 N3_V06S0303\narc: H00L0100 N1_V02S0301\narc: H00R0000 H02W0401\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 E1_H01W0000\narc: N3_V06N0003 H01E0001\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 H02E0401\narc: V00T0000 H02W0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 V06N0303\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0701 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: N1_V02N0701 W3_H06E0203\narc: N3_V06N0203 W3_H06E0203\narc: N3_V06N0303 W3_H06E0303\narc: S1_V02S0201 W3_H06E0103\narc: S1_V02S0301 W3_H06E0003\narc: S1_V02S0401 W3_H06E0203\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: A0 V02S0701\narc: A1 V02S0701\narc: A2 V02S0701\narc: A3 V02S0701\narc: A4 V02N0301\narc: A5 H02W0701\narc: B0 H02W0301\narc: B1 H02W0301\narc: B2 H02W0301\narc: B3 H02W0301\narc: B4 N1_V02S0701\narc: B5 H00R0000\narc: B6 S1_V02N0501\narc: B7 H02E0301\narc: C0 E1_H01W0000\narc: C1 E1_H01W0000\narc: C2 E1_H01W0000\narc: C3 E1_H01W0000\narc: C4 E1_H01E0101\narc: C5 H02E0601\narc: C6 V00B0100\narc: C7 V00T0000\narc: CLK1 G_HPBX0000\narc: D0 V02S0201\narc: D1 V02S0201\narc: D2 V02S0201\narc: D3 V02S0201\narc: D4 H01W0000\narc: D5 E1_H02W0201\narc: D6 H00L0100\narc: D7 V00B0000\narc: E1_H01E0001 F6\narc: E1_H02E0101 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR1 W1_H02E0501\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0101 Q3\narc: V00B0100 F7\narc: W1_H02W0001 Q2\nword: SLICED.K0.INIT 1100110000001111\nword: SLICED.K1.INIT 0000111100110011\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R19C46:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02N0601\narc: E3_H06E0203 W1_H02E0401\narc: H00R0000 V02N0401\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 V01N0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 E1_H02W0601\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02E0301\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V06N0203\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 E1_H02W0601\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0701 W3_H06E0203\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 V01N0001\narc: A0 V01N0101\narc: A1 V01N0101\narc: A2 V01N0101\narc: A3 V01N0101\narc: A4 V00T0100\narc: A5 V00B0000\narc: B0 V02N0301\narc: B1 V02N0301\narc: B2 V02N0101\narc: B3 V02N0101\narc: B4 S1_V02N0501\narc: B5 H00R0000\narc: B7 E1_H02W0101\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 H02E0401\narc: C5 V02N0001\narc: C7 V00T0000\narc: CLK1 G_HPBX0000\narc: D0 N1_V01S0000\narc: D1 N1_V01S0000\narc: D2 N1_V01S0000\narc: D3 N1_V01S0000\narc: D4 H02E0201\narc: D5 H02W0201\narc: D7 W1_H02E0201\narc: E1_H02E0101 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0000 F7\narc: LSR1 H02W0301\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0001 F7\narc: V01S0000 Q3\narc: V01S0100 F7\narc: W1_H02W0001 Q0\narc: W1_H02W0201 Q2\narc: W1_H02W0501 F7\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R19C47:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 H01E0001\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0203 N3_V06S0203\narc: E3_H06E0303 V01N0101\narc: H00L0000 N1_V02S0201\narc: H00R0000 H02W0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 H06E0303\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 H06W0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0201\narc: V00B0100 H02W0701\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02S0701\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 N1_V02S0301\narc: N1_V02N0301 W3_H06E0003\narc: A5 H02E0501\narc: B2 H00L0000\narc: B5 E1_H02W0301\narc: B6 S1_V02N0701\narc: B7 V01S0000\narc: C2 N1_V01N0001\narc: C5 V00B0100\narc: C6 H02E0601\narc: C7 H02E0401\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D2 V02N0201\narc: D5 H02E0001\narc: D6 V02N0401\narc: D7 V00B0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00T0000\narc: M0 V00T0100\narc: M1 H00R0100\narc: M2 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F6\narc: N1_V02N0701 F7\narc: V01S0000 Q6\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000010100001100\nword: SLICED.K0.INIT 1100000011001111\nword: SLICED.K1.INIT 0000111100001100\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111000011111100\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R19C48:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0203 W1_H02E0401\narc: H00R0000 V02S0601\narc: H00R0100 V02N0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 V01N0101\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 S1_V02N0101\narc: V00T0000 E1_H02W0001\narc: V00T0100 H02E0301\narc: W1_H02W0001 V02N0001\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 N1_V02S0701\narc: N1_V02N0601 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A7 N1_V01N0101\narc: B0 N1_V02S0101\narc: B2 H00R0000\narc: B4 W1_H02E0101\narc: B7 S1_V02N0701\narc: C0 F4\narc: C2 H00L0000\narc: C3 N1_V01N0001\narc: C4 H02E0401\narc: C6 V02S0201\narc: C7 E1_H02W0401\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 V00B0100\narc: D2 V02N0201\narc: D3 V02S0201\narc: D4 E1_H02W0201\narc: D5 H02E0001\narc: D6 V00B0000\narc: D7 V00B0000\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q2\narc: E3_H06E0003 F3\narc: E3_H06E0103 Q2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: M0 V00T0100\narc: M4 V00T0000\narc: MUXCLK1 CLK0\narc: N1_V01N0001 Q2\narc: S3_V06S0203 F7\narc: W3_H06W0103 Q2\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0000000000000001\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111110000110000\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R19C49:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 V02S0701\narc: E3_H06E0003 H01E0001\narc: E3_H06E0103 N1_V01S0100\narc: H00L0100 V02N0301\narc: H00R0100 E1_H02W0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 V01N0101\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02N0301\narc: V00T0100 E1_H02W0301\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 S3_V06N0203\narc: S1_V02S0401 W3_H06E0203\narc: W3_H06W0003 E1_H02W0001\narc: A1 H00L0000\narc: A3 E1_H01E0001\narc: A5 N1_V01N0101\narc: A7 H00R0000\narc: B0 V02S0301\narc: B1 H00R0100\narc: B2 H00R0000\narc: B3 E1_H01W0100\narc: B4 H02E0301\narc: B5 V02S0501\narc: B6 V01S0000\narc: B7 H02W0101\narc: C0 E1_H02W0601\narc: C1 H00L0100\narc: C2 E1_H02W0401\narc: C3 H00L0100\narc: C4 V00T0100\narc: C5 V00B0100\narc: C6 H02E0401\narc: C7 V00B0100\narc: CE0 S1_V02N0201\narc: CE1 S1_V02N0201\narc: CE2 S1_V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 S1_V02N0001\narc: D2 H02E0201\narc: D3 S1_V02N0001\narc: D4 H01W0000\narc: D5 V00B0000\narc: D6 H01W0000\narc: D7 V00B0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q6\narc: E1_H02E0001 Q0\narc: E1_H02E0201 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00R0000 Q6\narc: H01W0100 F7\narc: LSR0 W1_H02E0501\narc: LSR1 W1_H02E0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q4\narc: S1_V02S0001 Q2\narc: S1_V02S0101 F3\narc: S1_V02S0501 F5\narc: V01S0000 Q0\narc: W1_H02W0101 F1\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0101101000111100\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0101101000111100\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0101101000111100\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 0101101000111100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R19C4:PLC2\narc: E1_H02E0401 S3_V06N0203\narc: H00L0000 V02N0201\narc: N1_V02N0201 H06W0103\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 S3_V06N0303\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 H02E0701\narc: V00T0100 E1_H02W0101\narc: W1_H02W0601 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 E1_H02W0201\narc: D2 H02W0201\narc: D3 V00T0100\narc: E1_H02E0301 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: LSR1 V00B0100\narc: M0 H02W0601\narc: M1 H00L0000\narc: M2 H02W0601\narc: M4 W1_H02E0401\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N3_V06N0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R19C50:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0501 H01E0101\narc: E1_H02E0701 V02N0701\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 H02W0001\narc: H00R0000 N1_V02S0401\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 H06E0203\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 H06W0303\narc: V00B0000 V02N0001\narc: V00B0100 V02N0101\narc: V00T0000 V02S0601\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 V06N0303\narc: E1_H02E0001 W3_H06E0003\narc: H01W0000 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: W3_H06W0203 S3_V06N0203\narc: A5 H02E0501\narc: B0 V02N0301\narc: B2 V02S0301\narc: B3 H02W0101\narc: B5 H02E0301\narc: B6 V02N0501\narc: B7 V00B0100\narc: C0 V02N0601\narc: C2 E1_H02W0401\narc: C3 S1_V02N0401\narc: C5 H02E0601\narc: C6 V00T0000\narc: C7 V00T0100\narc: CE0 H00L0000\narc: CE1 S1_V02N0201\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V02S0001\narc: D2 V02N0001\narc: D3 V02N0001\narc: D5 E1_H02W0001\narc: D6 V00B0000\narc: D7 V00B0000\narc: E1_H01E0101 Q6\narc: E1_H02E0201 Q0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: M0 E1_H02W0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q3\narc: N1_V02N0501 Q7\narc: N3_V06N0303 F5\narc: V01S0000 Q2\narc: V01S0100 Q7\narc: W1_H02W0101 Q3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000010101010\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R19C51:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 S1_V02N0501\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 W1_H02E0201\narc: H00L0100 H02W0101\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 H06W0303\narc: V00T0000 W1_H02E0001\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0501 H01E0101\narc: H01W0100 W3_H06E0303\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A0 H00L0100\narc: A2 V02N0501\narc: A3 V01N0101\narc: A4 W1_H02E0701\narc: A5 V00T0000\narc: A6 H02E0501\narc: A7 H00L0000\narc: B2 N1_V02S0301\narc: B3 V02S0101\narc: B4 H02E0101\narc: B5 V02S0501\narc: B6 N1_V01S0000\narc: B7 V02S0701\narc: E1_H01E0001 F2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: N1_V01N0001 F5\narc: W1_H02W0301 F3\narc: W1_H02W0401 F6\narc: W1_H02W0601 F4\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R19C52:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0501 V01N0101\narc: H00L0000 V02S0001\narc: H00L0100 V02N0301\narc: H00R0000 V02N0601\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02N0201\narc: V00T0000 H02E0201\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 W3_H06E0203\narc: A0 W1_H02E0701\narc: A1 H00L0100\narc: A2 V00T0000\narc: A3 V02N0501\narc: A4 H02E0501\narc: A5 V00B0000\narc: A6 S1_V02N0101\narc: A7 H00R0000\narc: B0 N1_V02S0301\narc: B1 V02S0301\narc: B2 H00L0000\narc: B3 V02S0101\narc: B4 N1_V01S0000\narc: B5 V02S0701\narc: B6 H02E0301\narc: B7 V02S0501\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: H01W0100 F3\narc: N1_V01N0001 F6\narc: S1_V02S0501 F7\narc: S1_V02S0701 F5\narc: V01S0100 F4\narc: W1_H02W0301 F1\narc: W3_H06W0003 F0\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R19C53:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0701 V02N0701\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02S0201\narc: H00R0000 V02N0601\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 E3_H06W0203\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02S0001\narc: V00T0000 V02S0601\narc: W1_H02W0101 N3_V06S0103\narc: N1_V02N0101 W3_H06E0103\narc: W3_H06W0303 N3_V06S0303\narc: E3_H06E0003 W3_H06E0303\narc: A0 H02E0501\narc: A1 H00R0000\narc: A2 S1_V02N0701\narc: A3 V02N0501\narc: A4 V02N0101\narc: A5 E1_H02W0701\narc: A6 S1_V02N0301\narc: A7 H02W0701\narc: B0 V00B0000\narc: B1 V02S0301\narc: B2 H00L0000\narc: B3 V02S0101\narc: B4 N1_V02S0501\narc: B5 V02S0501\narc: B6 V00T0000\narc: B7 N1_V01S0000\narc: E1_H01E0001 F4\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F0\narc: S1_V02S0101 F1\narc: S1_V02S0201 F2\narc: S1_V02S0301 F3\narc: S1_V02S0701 F5\narc: V01S0000 F6\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R19C54:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 V01N0101\narc: H00L0000 V02N0001\narc: H00R0000 V02N0601\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H06E0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 H01E0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02S0201\narc: V00T0000 V02S0601\narc: V00T0100 H02E0101\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V01N0101\narc: H01W0000 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0303 N3_V06S0303\narc: E3_H06E0103 W3_H06E0103\narc: A0 H00R0000\narc: A1 V02N0701\narc: A2 H02E0701\narc: A3 E1_H02W0501\narc: A4 H02W0501\narc: A5 V02N0301\narc: A6 H00L0000\narc: A7 V00T0100\narc: B0 V00B0000\narc: B1 V02S0101\narc: B2 N1_V02S0301\narc: B3 V02S0301\narc: B4 N1_V01S0000\narc: B5 V02S0501\narc: B6 V00T0000\narc: B7 V02S0701\narc: E1_H01E0001 F2\narc: E1_H02E0001 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: S1_V02S0101 F1\narc: S1_V02S0301 F3\narc: S1_V02S0401 F6\narc: S1_V02S0601 F4\narc: V01S0000 F7\narc: V01S0100 F5\nword: SLICED.K0.INIT 1001011010101010\nword: SLICED.K1.INIT 1001011010101010\nword: SLICEC.K0.INIT 1001011010101010\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R19C55:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 N1_V01S0000\narc: H00L0000 H02W0001\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 H02E0501\narc: S1_V02S0701 H06W0203\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0001\narc: V00B0100 V02N0101\narc: V00T0000 N1_V02S0601\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 E1_H02W0701\narc: N1_V02N0301 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: A0 H00L0000\narc: A1 H00R0000\narc: A2 V02S0701\narc: B0 V00T0000\narc: B1 V02S0101\narc: B6 V00B0100\narc: B7 V01S0000\narc: C6 E1_H01E0101\narc: C7 E1_H01E0101\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D6 F0\narc: D7 H00L0100\narc: E1_H01E0001 F2\narc: E1_H01E0101 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H00R0000 Q6\narc: H01W0100 Q6\narc: LSR1 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q7\narc: S1_V02S0001 F2\narc: V01S0000 Q6\narc: W3_H06W0103 F2\nword: SLICED.K0.INIT 1100111111000000\nword: SLICED.K1.INIT 1100111111000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000001010\nword: SLICEB.K0.INIT 0101101010101010\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 1001011010101010\nword: SLICEA.K1.INIT 1001011010101010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R19C56:PLC2\narc: H00L0000 H02W0001\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H01E0001\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02E0401\narc: V00B0100 H02E0501\narc: V00T0000 V02S0601\narc: V00T0100 V02S0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0501 V01N0101\narc: W1_H02W0701 V01N0101\narc: H01W0000 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: A1 V02N0501\narc: B1 V02S0101\narc: B6 V00T0000\narc: C1 H02E0601\narc: C6 V02S0001\narc: CE0 H00L0000\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D6 H01W0000\narc: D7 V00B0000\narc: E1_H01E0101 Q1\narc: F1 F1_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q4\narc: M2 N1_V01N0001\narc: M4 E1_H01E0101\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V02N0201 Q2\narc: W3_H06W0203 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010101010111000\nword: SLICED.K0.INIT 1111110000110000\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R19C57:PLC2\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0203\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0701 S1_V02N0701\narc: W3_H06W0003 E3_H06W0303\n\n.tile R19C58:PLC2\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 E3_H06W0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 S3_V06N0303\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: V01S0000 S3_V06N0103\narc: V01S0100 N3_V06S0303\narc: W3_H06W0203 N3_V06S0203\n\n.tile R19C59:PLC2\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 S3_V06N0303\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 H06W0303\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: W3_H06W0203 E3_H06W0103\n\n.tile R19C5:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 V02N0001\narc: H00R0100 V02N0701\narc: N1_V02N0501 E1_H02W0501\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H02W0401\narc: V00T0000 N1_V02S0601\narc: V01S0000 S3_V06N0103\narc: V01S0100 S3_V06N0303\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 N1_V01S0000\narc: CE0 H00L0000\narc: CE2 W1_H02E0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q6\narc: M0 V00T0000\narc: M4 V00T0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W1_H02W0201 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R19C60:PLC2\narc: N1_V02N0501 S3_V06N0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: W3_H06W0103 N3_V06S0103\narc: W3_H06W0303 S3_V06N0303\n\n.tile R19C61:PLC2\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0201 S3_V06N0103\narc: W3_H06W0103 E3_H06W0003\n\n.tile R19C62:PLC2\narc: W3_H06W0203 S3_V06N0203\narc: W3_H06W0303 S3_V06N0303\n\n.tile R19C63:PLC2\narc: W3_H06W0303 S3_V06N0303\n\n.tile R19C64:PLC2\narc: W3_H06W0203 S3_V06N0203\narc: W3_H06W0303 S3_V06N0303\n\n.tile R19C65:PLC2\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0103 S3_V06N0103\n\n.tile R19C66:PLC2\narc: S3_V06S0203 N1_V02S0401\n\n.tile R19C67:PLC2\narc: N3_V06N0203 S3_V06N0103\narc: W3_H06W0003 S3_V06N0003\n\n.tile R19C69:PLC2\narc: N1_V02N0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\n\n.tile R19C6:PLC2\narc: E1_H02E0101 V02N0101\narc: H00L0000 V02N0201\narc: H00R0000 E1_H02W0401\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0001 V01N0001\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 S3_V06N0303\narc: V00B0000 S1_V02N0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0401 E3_H06W0203\narc: A4 H02W0701\narc: A5 H02W0701\narc: A6 H02W0701\narc: B4 S1_V02N0701\narc: B5 S1_V02N0701\narc: B6 S1_V02N0701\narc: C4 H02E0401\narc: C5 H02E0401\narc: C6 H02E0401\narc: D4 V00B0000\narc: D5 V00B0000\narc: D6 V00B0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00R0000\narc: M2 V00T0100\narc: M3 H00L0000\narc: M4 V00T0100\narc: M5 H00R0000\narc: M6 V00T0100\narc: V01S0000 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111010100110001\nword: SLICEC.K1.INIT 1111010100110001\nword: SLICED.K0.INIT 1111010100110001\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R19C7:PLC2\narc: E1_H02E0201 V06S0103\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0301 N3_V06S0003\narc: S1_V02S0001 S3_V06N0003\narc: V00B0000 W1_H02E0601\narc: V00B0100 V02S0101\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0701 E1_H02W0701\narc: W3_H06W0103 N3_V06S0103\narc: CE0 H02E0101\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: H01W0000 Q6\narc: M0 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R19C8:PLC2\narc: E1_H02E0001 V02S0001\narc: H00R0100 S1_V02N0501\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02E0201\narc: S3_V06S0003 N1_V02S0301\narc: V00B0000 S1_V02N0001\narc: V00T0000 V02N0401\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 V06S0303\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R19C9:PLC2\narc: N1_V02N0001 H02W0001\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 H02W0501\narc: S1_V02S0101 H02W0101\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 H02E0001\narc: V00T0100 V02S0701\narc: W1_H02W0701 S3_V06N0203\narc: CLK0 G_HPBX0000\narc: E3_H06E0003 Q0\narc: LSR1 V00T0100\narc: M0 V00T0000\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N3_V06N0203 Q4\narc: N3_V06N0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R20C10:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 E3_H06W0303\narc: H00L0000 S1_V02N0201\narc: H00R0100 V02N0501\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 V02S0201\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: H01W0100 W3_H06E0303\narc: S1_V02S0401 W3_H06E0203\narc: W3_H06W0303 S3_V06N0303\narc: W3_H06W0003 E3_H06W0003\narc: B1 N1_V02S0301\narc: B3 H00L0000\narc: B5 H00L0000\narc: B7 N1_V01S0000\narc: C1 H00L0000\narc: C3 V02N0401\narc: C5 N1_V02S0001\narc: C7 S1_V02N0201\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V01S0100\narc: D3 V02S0001\narc: D5 V00B0000\narc: D7 V02S0601\narc: E1_H01E0101 Q5\narc: E1_H02E0101 Q1\narc: E1_H02E0301 Q3\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0000 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111001111000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111001111000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100111111000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100111111000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R20C11:PLC2\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0303 V06N0303\narc: H00L0000 H02W0001\narc: H00R0000 V02S0401\narc: S1_V02S0001 H02W0001\narc: S1_V02S0501 V01N0101\narc: S3_V06S0003 H06E0003\narc: V00B0000 V02N0001\narc: V00T0100 W1_H02E0301\narc: W1_H02W0501 V02N0501\narc: A3 V00T0000\narc: A4 N1_V01N0101\narc: B0 E1_H01W0100\narc: B2 E1_H02W0301\narc: B3 H02W0301\narc: B4 H00L0000\narc: B5 N1_V01S0000\narc: B6 H01E0101\narc: C0 H00L0000\narc: C1 E1_H01W0000\narc: C2 H02E0401\narc: C3 V02N0401\narc: C4 V00B0100\narc: C5 V00T0100\narc: C6 W1_H02E0401\narc: C7 F6\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 F0\narc: D2 V02N0001\narc: D3 S1_V02N0201\narc: D4 E1_H02W0201\narc: D5 V00B0000\narc: D6 V00B0000\narc: D7 V01N0001\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q6\narc: E1_H02E0001 F0\narc: E1_H02E0201 Q2\narc: E1_H02E0401 F6\narc: E1_H02E0501 F5\narc: E1_H02E0701 F7\narc: E3_H06E0003 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q2\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q5\narc: N1_V02N0001 F2\narc: N1_V02N0701 Q5\narc: N3_V06N0303 F5\narc: S1_V02S0701 F5\narc: S3_V06S0103 F2\narc: S3_V06S0303 F6\narc: V00B0100 F5\narc: V00T0000 F2\narc: V01S0000 F3\narc: V01S0100 F4\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0000000000001111\nword: SLICEC.K0.INIT 0100000001110000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0011000000111111\nword: SLICEA.K1.INIT 1111000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R20C12:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02S0501\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 S3_V06N0203\narc: H00L0100 N1_V02S0301\narc: H00R0100 H02E0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0103 E1_H01W0100\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02N0301\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0601 N3_V06S0303\narc: E1_H02E0701 W3_H06E0203\narc: W3_H06W0003 N3_V06S0003\narc: A1 H00L0100\narc: A3 V00T0000\narc: A7 S1_V02N0101\narc: B1 H02W0101\narc: B2 W1_H02E0301\narc: B3 V02S0101\narc: B4 H02E0301\narc: B5 H00R0000\narc: B7 V02N0701\narc: C1 H02W0401\narc: C2 H02E0601\narc: C3 E1_H01W0000\narc: C4 V02N0201\narc: C5 V00T0000\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 H02W0001\narc: D2 S1_V02N0001\narc: D3 H02E0001\narc: D4 V00B0000\narc: D5 H00R0100\narc: D7 V01N0001\narc: E1_H01E0001 F6\narc: E1_H01E0101 F2\narc: E1_H02E0201 Q0\narc: E3_H06E0303 F5\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 F4\narc: H01W0000 F2\narc: H01W0100 Q2\narc: M0 W1_H02E0601\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q0\narc: N1_V02N0401 F4\narc: N3_V06N0303 F5\narc: S1_V02S0001 Q0\narc: S1_V02S0601 F4\narc: S3_V06S0003 F0\narc: S3_V06S0203 F4\narc: V00T0000 F2\narc: V00T0100 F3\narc: V01S0000 Q0\narc: V01S0100 Q4\narc: W1_H02W0001 Q0\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0011111100101010\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0000001100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0100000000000000\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111111110101100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\n\n.tile R20C13:PLC2\narc: H00L0000 H02E0201\narc: H00R0000 V02N0401\narc: N1_V02N0101 H01E0101\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H06W0303\narc: N1_V02N0701 H02E0701\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 H01E0101\narc: S1_V02S0401 H01E0001\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0201\narc: V00B0100 V02N0301\narc: V00T0000 H02E0201\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 N1_V02S0401\narc: S3_V06S0003 W3_H06E0003\narc: W3_H06W0003 N3_V06S0003\narc: A1 H02E0501\narc: A5 N1_V01N0101\narc: A7 H00L0000\narc: B1 V00T0000\narc: B2 N1_V02S0101\narc: B4 E1_H02W0301\narc: B5 V01S0000\narc: B7 H02E0301\narc: C1 N1_V02S0601\narc: C2 H00L0000\narc: C3 V02S0401\narc: C4 H02W0601\narc: C5 E1_H01E0101\narc: C7 W1_H02E0401\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 V00B0100\narc: D3 F2\narc: D4 H02E0001\narc: D5 S1_V02N0401\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: H01W0100 F4\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F4\narc: S1_V02S0601 Q4\narc: V01S0000 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0010110101111000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0100101101111000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0000000100000010\nword: SLICEB.K0.INIT 0011000000111111\nword: SLICEB.K1.INIT 0000000000001111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R20C14:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 V06S0203\narc: E1_H02E0701 V06S0203\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 W1_H02E0401\narc: H00L0100 V02S0101\narc: H00R0000 V02N0601\narc: H00R0100 V02S0701\narc: N1_V02N0201 H02W0201\narc: N1_V02N0601 H01E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0501 V01N0101\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02S0101\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02N0701\narc: E1_H02E0001 W3_H06E0003\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: B1 V00T0000\narc: B3 H00R0100\narc: B7 S1_V02N0701\narc: C1 H00L0100\narc: C3 H00L0100\narc: C7 V00B0100\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D3 H02W0001\narc: D7 V00B0000\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q3\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0301 Q1\narc: W1_H02W0701 Q7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100111111000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100111111000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100111111000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R20C15:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0501 V02N0501\narc: H00L0000 H02E0001\narc: H00R0000 V02S0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0601 H02W0601\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 H02W0501\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 V02S0101\narc: V00T0000 H02W0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0301 N1_V01S0100\narc: B0 N1_V02S0301\narc: B2 H01W0100\narc: B3 V02S0301\narc: C0 H00R0100\narc: C1 H02W0401\narc: C2 V02N0401\narc: C3 H00L0000\narc: C4 V00T0000\narc: C5 S1_V02N0201\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 V00B0100\narc: D2 V02N0001\narc: D3 N1_V02S0001\narc: D4 V02S0401\narc: D5 V02S0401\narc: E1_H01E0001 F0\narc: E1_H01E0101 F4\narc: E1_H02E0301 F1\narc: E1_H02E0701 F5\narc: E3_H06E0003 F0\narc: E3_H06E0103 F1\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F5\narc: H01W0100 Q3\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F3\narc: N1_V02N0001 Q0\narc: N1_V02N0301 Q3\narc: N3_V06N0003 Q3\narc: N3_V06N0103 F2\narc: S3_V06S0003 F3\narc: V01S0000 F3\narc: V01S0100 F1\narc: W1_H02W0101 F3\narc: W1_H02W0201 Q0\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000000000110000\nword: SLICEB.K1.INIT 1100110011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R20C16:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 V06S0303\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0103 H01E0101\narc: H00L0000 H02W0001\narc: H00L0100 H02E0301\narc: H00R0000 V02N0601\narc: H00R0100 V02N0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 V01N0001\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 H01E0101\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 H06W0303\narc: V00B0000 S1_V02N0201\narc: V00B0100 W1_H02E0701\narc: V00T0000 V02S0601\narc: V00T0100 V02S0701\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 N3_V06S0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\narc: A0 N1_V02S0701\narc: A1 N1_V02S0701\narc: A2 N1_V02S0701\narc: A3 N1_V02S0701\narc: A4 S1_V02N0101\narc: A5 V02N0301\narc: A7 V00T0100\narc: B0 H01W0100\narc: B1 H01W0100\narc: B2 H01W0100\narc: B3 H01W0100\narc: B4 W1_H02E0301\narc: B5 V02N0701\narc: B7 H02E0101\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 V01N0101\narc: C5 E1_H02W0601\narc: C6 Q6\narc: C7 V00T0000\narc: CE0 V02S0201\narc: CE1 V02S0201\narc: CE3 H00L0000\narc: CLK1 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 H02E0201\narc: D5 H00L0100\narc: D6 V02N0601\narc: D7 H02W0201\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q0\narc: E1_H02E0101 Q3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q6\narc: LSR0 V00B0000\narc: LSR1 V00B0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXCLK3 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q2\narc: S1_V02S0101 Q1\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1100010001000100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R20C17:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0601 V06N0303\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 H02E0001\narc: H00L0100 W1_H02E0301\narc: H00R0100 H02W0501\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 V01N0101\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0701 W1_H02E0701\narc: V00B0000 V02N0201\narc: V00T0000 V02S0601\narc: V00T0100 H02E0101\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0601 H01E0001\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: A0 H02E0701\narc: A1 H02E0701\narc: A2 H02E0701\narc: A3 H02E0701\narc: A4 H02E0701\narc: A5 V02N0101\narc: A6 V00T0100\narc: A7 N1_V01N0101\narc: B0 V02N0301\narc: B1 V02N0301\narc: B2 V02N0301\narc: B3 V02N0301\narc: B4 H00L0000\narc: B5 V02N0701\narc: B6 V02N0501\narc: B7 H02W0301\narc: C0 E1_H02W0601\narc: C1 E1_H02W0601\narc: C2 E1_H02W0601\narc: C3 E1_H02W0601\narc: C4 V02S0001\narc: C5 H02W0601\narc: C6 V00T0000\narc: C7 H02W0401\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK1 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02N0001\narc: D2 V02N0001\narc: D3 V02N0001\narc: D4 S1_V02N0601\narc: D5 H00L0100\narc: D6 V02N0401\narc: D7 V00B0000\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q0\narc: E1_H02E0501 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q1\narc: LSR0 H02E0301\narc: LSR1 H02E0501\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q3\narc: V01S0100 Q2\nword: SLICED.K0.INIT 1100000010100000\nword: SLICED.K1.INIT 1100000010100000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R20C18:PLC2\narc: E1_H02E0401 H01E0001\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V02N0701\narc: H00L0000 W1_H02E0001\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 H06E0003\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02S0101\narc: V00T0000 V02N0401\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 V06N0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 V02N0601\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A0 H02W0701\narc: A1 H02W0701\narc: A2 H02W0701\narc: A3 H02W0701\narc: A4 H02W0701\narc: A5 V02S0301\narc: B0 H02E0301\narc: B1 H02E0301\narc: B2 H02E0301\narc: B3 H02E0301\narc: B4 H00L0000\narc: B5 H02W0101\narc: B7 V00B0100\narc: C0 H02W0601\narc: C1 H02W0601\narc: C2 H02W0601\narc: C3 H02W0601\narc: C4 H02E0601\narc: C5 V02S0001\narc: C6 V00T0000\narc: C7 F6\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK1 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02N0001\narc: D2 V02N0001\narc: D3 V02N0001\narc: D4 S1_V02N0601\narc: D5 N1_V02S0601\narc: D6 V00B0000\narc: D7 H02W0201\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0100 Q2\narc: LSR0 H02W0501\narc: LSR1 E1_H02W0501\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q1\narc: N1_V02N0001 Q0\narc: N1_V02N0701 F7\narc: N3_V06N0003 Q0\narc: S1_V02S0401 F6\narc: S1_V02S0701 F7\narc: W1_H02W0101 Q3\narc: W1_H02W0501 F7\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 1111001100110011\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R20C19:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 N1_V02S0701\narc: H00L0000 V02N0001\narc: H00L0100 V02N0101\narc: H00R0000 N1_V02S0401\narc: H00R0100 H02W0701\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 V01N0101\narc: S1_V02S0001 N1_V02S0001\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 E1_H02W0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0601\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A0 S1_V02N0701\narc: A1 H00R0000\narc: A2 S1_V02N0701\narc: A3 S1_V02N0701\narc: A4 H02E0701\narc: A5 V02N0301\narc: A6 N1_V01N0101\narc: A7 H00L0000\narc: B0 E1_H01W0100\narc: B1 E1_H01W0100\narc: B2 E1_H01W0100\narc: B3 E1_H01W0100\narc: B4 H02W0301\narc: B5 V02S0701\narc: B6 V00B0100\narc: B7 H02W0101\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V00T0000\narc: C5 H02E0601\narc: C6 N1_V02S0201\narc: C7 E1_H02W0601\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK1 G_HPBX0000\narc: D0 H02W0201\narc: D1 H02W0201\narc: D2 H02W0201\narc: D3 H02W0201\narc: D4 V02N0401\narc: D5 E1_H02W0201\narc: D6 V02S0401\narc: D7 H02W0001\narc: E1_H01E0001 Q3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00T0100\narc: LSR1 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q2\narc: N1_V02N0201 Q0\narc: S1_V02S0301 Q1\narc: V01S0000 F7\narc: V01S0100 F6\nword: SLICED.K0.INIT 1100101000000000\nword: SLICED.K1.INIT 1100000010100000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R20C20:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 V02N0701\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 E1_H02W0001\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 V01N0101\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 V02N0201\narc: V00T0000 E1_H02W0001\narc: V00T0100 H02W0101\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V01N0101\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 N1_V02S0601\narc: N1_V02N0101 W3_H06E0103\narc: W3_H06W0203 V06S0203\narc: W3_H06W0303 E1_H02W0601\narc: E3_H06E0203 W3_H06E0203\narc: A0 H01E0001\narc: A1 N1_V02S0501\narc: A3 V00T0000\narc: A7 N1_V01N0101\narc: B0 H02E0301\narc: B1 V02N0301\narc: B3 N1_V02S0301\narc: B5 H00L0000\narc: B7 F1\narc: C0 E1_H02W0401\narc: C1 H02W0601\narc: C2 H02E0401\narc: C3 F4\narc: C4 V02S0201\narc: C5 F4\narc: C7 W1_H02E0401\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 S1_V02N0001\narc: D2 V02N0001\narc: D3 V02N0201\narc: D4 V02N0601\narc: D5 V00B0000\narc: D7 H02E0001\narc: E1_H02E0501 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 F3\narc: H01W0000 Q2\narc: H01W0100 Q2\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M6 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F5\narc: N1_V01N0101 F0\narc: N1_V02N0601 F4\narc: N3_V06N0303 Q6\narc: S1_V02S0301 F3\narc: S1_V02S0701 F5\narc: S3_V06S0103 Q2\narc: S3_V06S0303 F5\narc: V01S0000 Q2\narc: W1_H02W0701 F5\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 1111001100110011\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1100010001000100\nword: SLICEA.K0.INIT 1100101000000000\nword: SLICEA.K1.INIT 1010000011000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111110\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R20C21:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 V01N0001\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 N1_V02S0301\narc: H00R0100 S1_V02N0701\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0601 H02E0601\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0401\narc: V00B0000 H02E0601\narc: V00B0100 E1_H02W0701\narc: V00T0000 H02W0201\narc: V00T0100 V02N0701\narc: W1_H02W0101 V02N0101\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 E1_H01W0000\narc: S1_V02S0701 W3_H06E0203\narc: S3_V06S0003 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0303 E3_H06W0303\narc: A0 V02N0701\narc: A1 V02N0701\narc: A2 V02N0701\narc: A3 V02N0701\narc: A4 V00T0100\narc: A5 V00T0000\narc: A7 N1_V01S0100\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 H02E0101\narc: B5 V02N0501\narc: B7 E1_H02W0101\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V02S0201\narc: C5 E1_H02W0401\narc: C6 V00B0100\narc: C7 F6\narc: CE0 W1_H02E0101\narc: CE1 W1_H02E0101\narc: CLK1 G_HPBX0000\narc: D0 N1_V02S0001\narc: D1 N1_V02S0001\narc: D2 N1_V02S0001\narc: D3 N1_V02S0001\narc: D4 V02S0601\narc: D5 V02S0401\narc: D6 V02N0401\narc: D7 V01N0001\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F2\narc: E1_H02E0101 F3\narc: E1_H02E0201 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q3\narc: LSR0 W1_H02E0501\narc: LSR1 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F6\narc: N1_V01N0101 Q1\narc: N1_V02N0001 Q2\narc: N1_V02N0301 Q3\narc: N3_V06N0303 F6\narc: S1_V02S0401 F6\narc: W1_H02W0501 F7\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R20C22:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 S1_V02N0501\narc: H00L0000 H02E0201\narc: H00R0000 H02E0401\narc: H00R0100 H02W0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H01E0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0601 H02W0601\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 H06W0303\narc: V00B0000 V02S0001\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0203 N3_V06S0203\narc: W3_H06W0303 E3_H06W0203\narc: A2 W1_H02E0701\narc: A4 H02W0501\narc: B2 E1_H02W0301\narc: B4 V02N0701\narc: B5 H00L0000\narc: C2 H00L0100\narc: C3 H00R0100\narc: C4 V00B0100\narc: C5 W1_H02E0401\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 W1_H02E0001\narc: D3 H02W0201\narc: D4 V02N0601\narc: D5 W1_H02E0001\narc: E1_H01E0001 F3\narc: E3_H06E0003 F3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0100 F3\narc: H01W0000 F3\narc: H01W0100 Q0\narc: LSR1 V00B0000\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V02N0301 F3\narc: S1_V02S0001 F2\narc: S1_V02S0401 F4\narc: V00B0100 F5\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100000010100000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 1111011111100110\nword: SLICEC.K1.INIT 0000111100110011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R20C23:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V06N0103\narc: E1_H02E0401 V02N0401\narc: E3_H06E0103 S3_V06N0103\narc: H00R0100 H02W0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 H01E0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02W0401\narc: V00T0100 H02E0101\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 V02S0701\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: C1 H00L0100\narc: C7 V00T0000\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: D7 V00B0000\narc: F1 F1_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: M2 E1_H02W0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: S1_V02S0701 F7\narc: S3_V06S0203 F7\narc: V00T0000 Q2\narc: V01S0000 Q1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R20C24:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0701 V02N0701\narc: E3_H06E0003 S3_V06N0003\narc: H00L0100 E1_H02W0101\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0301 H06E0003\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 E1_H01W0100\narc: V00B0100 H02W0501\narc: V00T0000 H02W0001\narc: V00T0100 V02N0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0601 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A1 V01N0101\narc: A3 E1_H01E0001\narc: B1 H00R0100\narc: B3 H01W0100\narc: B5 H00R0000\narc: B7 V02S0701\narc: C0 H00L0100\narc: C1 H00L0000\narc: C3 E1_H01W0000\narc: C5 V00T0000\narc: C7 V02N0001\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 N1_V02S0201\narc: D3 W1_H02E0201\narc: D5 V02N0401\narc: D6 H01W0000\narc: D7 E1_H02W0201\narc: E1_H01E0001 Q1\narc: E1_H01E0101 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 F0\narc: H00R0000 Q6\narc: H01W0000 F5\narc: H01W0100 Q6\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M2 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q1\narc: N3_V06N0103 F2\narc: N3_V06N0303 Q6\narc: S1_V02S0001 F0\narc: S1_V02S0401 Q6\narc: V01S0100 Q6\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011000000111111\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 1111000100000001\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000110000001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R20C25:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V01N0101\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 W1_H02E0101\narc: H00R0000 E1_H02W0601\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 H02E0601\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0301 N1_V01S0100\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 H06W0103\narc: V00B0000 W1_H02E0401\narc: V00B0100 H02E0701\narc: V00T0000 H02E0201\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 V06S0303\narc: W3_H06W0203 E3_H06W0203\narc: A3 V02S0501\narc: A5 N1_V01N0101\narc: A6 N1_V01N0101\narc: A7 V02N0101\narc: B3 E1_H02W0301\narc: B5 H00R0000\narc: B6 H01E0101\narc: B7 V00T0000\narc: C3 H02W0601\narc: C5 E1_H02W0401\narc: C6 H02E0401\narc: C7 V00B0100\narc: CE0 V02N0201\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D5 N1_V02S0601\narc: D6 V02N0401\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 F6\narc: E3_H06E0203 Q7\narc: E3_H06E0303 F6\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0000 Q0\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q7\narc: N3_V06N0203 Q7\narc: S3_V06S0203 Q7\narc: S3_V06S0303 F6\narc: V01S0000 Q0\narc: V01S0100 Q7\narc: W1_H02W0501 Q7\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010101010001010\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1010000010100011\nword: SLICED.K0.INIT 1000000011110000\nword: SLICED.K1.INIT 1000111110000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R20C26:PLC2\narc: E1_H02E0201 H01E0001\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 V02N0201\narc: H00R0100 H02W0501\narc: N1_V02N0101 H01E0101\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0501 V01N0101\narc: S3_V06S0303 H06W0303\narc: V00B0000 V02S0201\narc: V00B0100 V02N0101\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 H01E0101\narc: E1_H02E0601 W3_H06E0303\narc: N1_V02N0201 W3_H06E0103\narc: S1_V02S0601 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: A5 E1_H02W0701\narc: A7 H02W0701\narc: B0 V00T0000\narc: B5 E1_H02W0301\narc: B7 V00B0100\narc: C0 H00L0100\narc: C1 H00L0000\narc: C5 H02E0601\narc: C7 H02E0401\narc: CE1 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 V02N0001\narc: D5 H00R0100\narc: D7 V00B0000\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F7\narc: E1_H02E0001 Q2\narc: E1_H02E0301 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: M2 V00T0100\narc: M4 E1_H01E0101\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N3_V06N0203 F4\narc: V00T0000 Q0\narc: V01S0100 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 1100000011111111\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R20C27:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V02N0601\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 H02E0001\narc: H00L0100 H02W0101\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H06W0303\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 H02W0601\narc: V00B0100 H02E0501\narc: V00T0100 N1_V02S0501\narc: V01S0100 S3_V06N0303\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 V01N0101\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 N1_V02S0701\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0401 W3_H06E0203\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0303 E3_H06W0203\narc: A1 H00L0100\narc: A3 V00B0000\narc: A4 W1_H02E0501\narc: A6 N1_V02S0301\narc: A7 H00L0000\narc: B1 E1_H01W0100\narc: B3 H00R0000\narc: B4 V02N0701\narc: B5 V01S0000\narc: B6 V02N0501\narc: B7 N1_V01S0000\narc: C1 E1_H01W0000\narc: C3 H00R0100\narc: C4 V02N0201\narc: C5 V00T0100\narc: C6 N1_V02S0201\narc: C7 V02N0001\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D3 H02E0201\narc: D4 S1_V02N0401\narc: D5 E1_H02W0001\narc: D6 V00B0000\narc: D7 V02S0601\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H00R0100 F7\narc: LSR1 W1_H02E0301\narc: M0 V00B0100\narc: M2 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: S3_V06S0003 F0\narc: S3_V06S0103 F2\narc: S3_V06S0303 F5\narc: V01S0000 Q4\nword: SLICEC.K0.INIT 1000000011001100\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 0101001111111111\nword: SLICED.K1.INIT 0000000000100000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111011101110011\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111011101110011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R20C28:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 S1_V02N0701\narc: H00R0000 W1_H02E0601\narc: H00R0100 V02S0501\narc: N1_V02N0301 V01N0101\narc: N1_V02N0501 H06W0303\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 H06E0303\narc: V00B0000 H02W0601\narc: V00B0100 H02W0501\narc: V00T0000 V02S0601\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V01N0101\narc: E1_H01E0001 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A1 V02N0701\narc: A4 V00B0000\narc: A5 N1_V01N0101\narc: A7 V02N0301\narc: B1 H02E0301\narc: B4 V02N0501\narc: B5 V02S0701\narc: B7 S1_V02N0501\narc: C1 V02S0401\narc: C4 N1_V02S0201\narc: C5 V00T0000\narc: C7 H02E0601\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D4 S1_V02N0601\narc: D5 N1_V02S0601\narc: D7 H00R0100\narc: E1_H02E0201 Q2\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F5\narc: H01W0100 F4\narc: M2 E1_H02W0601\narc: M6 V00T0100\narc: MUXCLK1 CLK0\narc: N1_V01N0101 Q2\narc: V00T0100 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 1010101010001010\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R20C29:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0103 V01N0101\narc: E3_H06E0203 W1_H02E0401\narc: H00R0000 V02N0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 E1_H02W0001\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 V02S0201\narc: V00B0100 H02E0701\narc: V00T0000 H02E0201\narc: V00T0100 V02N0501\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 V01N0001\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0303 E3_H06W0303\narc: A1 N1_V02S0701\narc: A5 V00T0000\narc: A7 E1_H02W0701\narc: B1 S1_V02N0301\narc: B5 H00R0000\narc: B7 W1_H02E0101\narc: C1 H02E0401\narc: C5 V00T0100\narc: C7 V00B0100\narc: CE1 V02N0201\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D5 H00R0100\narc: D7 H02E0001\narc: E1_H02E0201 Q2\narc: E1_H02E0501 F7\narc: F0 F5A_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: M0 V00B0000\narc: M2 E1_H02W0601\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F5\narc: S3_V06S0203 F7\narc: V01S0000 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111010100010000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R20C2:PLC2\narc: E1_H02E0201 E1_H01W0000\narc: H00R0100 E1_H02W0501\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 E1_H02W0601\narc: V00B0100 V02S0301\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: V01S0000 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R20C30:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0303 N1_V01S0100\narc: H00R0100 V02S0501\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 H06W0303\narc: V00B0100 N1_V02S0301\narc: V00T0000 N1_V02S0601\narc: W1_H02W0601 V01N0001\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0301 W3_H06E0003\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 V06S0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A1 E1_H02W0501\narc: B1 V00T0000\narc: C1 E1_H02W0601\narc: D1 H02E0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00R0100\narc: M2 V00B0100\narc: M3 E1_H02W0201\narc: M4 V00B0100\narc: M5 H00R0100\narc: M6 V00B0100\narc: V01S0000 F3\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000011100001111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R20C31:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 N1_V02S0001\narc: H00R0000 E1_H02W0401\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0601 E3_H06W0303\narc: N3_V06N0103 S1_V02N0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 H06W0003\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 E1_H02W0401\narc: V00B0100 W1_H02E0701\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02N0501\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0601 V02N0601\narc: N1_V02N0101 W3_H06E0103\narc: S1_V02S0601 W3_H06E0303\narc: S3_V06S0303 W3_H06E0303\narc: W1_H02W0501 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0203 E3_H06W0103\narc: A3 E1_H01E0001\narc: A6 H02E0501\narc: B3 H01W0100\narc: B5 V02S0501\narc: B6 V00T0000\narc: B7 V02S0701\narc: C2 H02E0601\narc: C3 H00L0000\narc: C4 E1_H01E0101\narc: C5 V02N0001\narc: C6 W1_H02E0601\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 V02S0201\narc: D4 V00B0000\narc: D5 E1_H02W0001\narc: D6 H02W0001\narc: D7 H00R0100\narc: E1_H01E0001 Q5\narc: E1_H01E0101 F5\narc: E3_H06E0103 Q2\narc: E3_H06E0203 F4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q5\narc: H01W0100 Q2\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F3\narc: N1_V01N0101 Q2\narc: N1_V02N0501 F7\narc: S1_V02S0301 F3\narc: S1_V02S0401 F6\narc: V01S0000 Q0\narc: V01S0100 F4\narc: W1_H02W0101 F3\narc: W3_H06W0003 F3\narc: W3_H06W0103 F2\narc: W3_H06W0303 Q5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000111111111111\nword: SLICEB.K1.INIT 0001010101010101\nword: SLICED.K0.INIT 0001010100111111\nword: SLICED.K1.INIT 0011001100001111\nword: SLICEC.K0.INIT 0000000000001111\nword: SLICEC.K1.INIT 0000111100001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R20C32:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0601 V02S0601\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0103 W1_H02E0201\narc: H00L0100 V02S0301\narc: H00R0000 V02S0401\narc: H00R0100 H02W0701\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: V00B0100 E1_H02W0701\narc: V00T0100 H02W0101\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0501 S1_V02N0501\narc: E1_H02E0301 W3_H06E0003\narc: H01W0000 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0303 E3_H06W0203\narc: A2 V02S0701\narc: A3 V00T0000\narc: B2 H00R0000\narc: B3 E1_H01W0100\narc: B7 V00T0000\narc: C2 H00L0100\narc: C3 V02S0601\narc: C7 V00T0100\narc: CE0 H00R0100\narc: CE1 H02E0101\narc: CE2 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 H02E0001\narc: D7 V02S0601\narc: E1_H01E0001 Q0\narc: E1_H02E0001 Q2\narc: E3_H06E0203 Q4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: M0 H02W0601\narc: M4 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: N1_V02N0601 Q4\narc: S1_V02S0601 Q4\narc: S3_V06S0203 Q4\narc: V00T0000 Q2\narc: V01S0000 Q4\narc: W1_H02W0101 F3\narc: W1_H02W0701 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEB.K0.INIT 0001000000000000\nword: SLICEB.K1.INIT 1010000010000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R20C33:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 V02S0201\narc: H00L0100 V02S0301\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 E3_H06W0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 E1_H01W0100\narc: V00B0100 H02W0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 V06S0203\narc: E1_H01E0101 W3_H06E0203\narc: S1_V02S0001 W3_H06E0003\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: A2 E1_H01E0001\narc: A3 V02N0501\narc: B2 W1_H02E0301\narc: B3 H02W0301\narc: B5 H00R0000\narc: C2 H02E0601\narc: C3 H00L0100\narc: C5 H01E0001\narc: CE0 H02W0101\narc: CE1 E1_H02W0101\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D2 E1_H02W0001\narc: D3 V00B0100\narc: D5 V02S0401\narc: E1_H01E0001 Q3\narc: E1_H02E0001 Q0\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H00R0000 Q6\narc: H01W0000 F2\narc: H01W0100 Q3\narc: M0 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: V00T0000 Q0\narc: V00T0100 Q3\narc: W1_H02W0101 Q3\narc: W1_H02W0501 F5\narc: W3_H06W0303 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011000000000000\nword: SLICEB.K0.INIT 0000000010111111\nword: SLICEB.K1.INIT 0001000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R20C34:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 W1_H02E0001\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 W1_H02E0001\narc: H00L0100 W1_H02E0301\narc: H00R0000 V02S0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 H02E0101\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00T0000 V02S0601\narc: V00T0100 S1_V02N0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0701 S1_V02N0701\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 N1_V01S0000\narc: A0 H01E0001\narc: A2 V02S0501\narc: A6 H02E0501\narc: B0 V00T0000\narc: B1 V00B0000\narc: B2 S1_V02N0101\narc: B6 N1_V02S0701\narc: C0 H00L0000\narc: C1 N1_V02S0601\narc: C2 H00R0100\narc: C6 E1_H01E0101\narc: C7 N1_V02S0001\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H01E0101\narc: D1 F0\narc: D2 H00R0000\narc: D6 H00L0100\narc: D7 W1_H02E0201\narc: E1_H01E0001 F2\narc: E1_H01E0101 F7\narc: E1_H02E0201 F2\narc: E1_H02E0301 F1\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F7\narc: LSR0 H02E0301\narc: M2 H02E0601\narc: M4 V00T0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q4\narc: N1_V02N0701 F7\narc: N3_V06N0203 F7\narc: S1_V02S0501 F7\narc: V01S0000 F7\narc: W1_H02W0201 F2\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000001000\nword: SLICEA.K1.INIT 0000000011001111\nword: SLICED.K0.INIT 1011000010000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0011000100010001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R20C35:PLC2\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0103 H01E0101\narc: H00L0000 H02E0201\narc: H00L0100 V02S0101\narc: H00R0100 S1_V02N0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H06E0203\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 H01E0101\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 H01E0101\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0201\narc: V00T0000 H02E0001\narc: V00T0100 N1_V02S0501\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 E1_H02W0601\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: W3_H06W0003 S3_V06N0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0203 E3_H06W0103\narc: A0 E1_H01E0001\narc: A3 V02S0701\narc: A6 N1_V01N0101\narc: B0 V02S0301\narc: B1 H02E0301\narc: B2 H01W0100\narc: B3 H00L0000\narc: B4 V00B0100\narc: B6 V00T0000\narc: C0 N1_V02S0401\narc: C1 H00L0100\narc: C2 E1_H02W0601\narc: C3 H02W0601\narc: C4 F6\narc: C5 W1_H02E0401\narc: C6 V02S0001\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 V01S0100\narc: D2 W1_H02E0001\narc: D3 S1_V02N0001\narc: D4 H00R0100\narc: D5 V02N0401\narc: D6 V02S0401\narc: E1_H01E0001 F1\narc: E1_H01E0101 F1\narc: E1_H02E0001 Q0\narc: E3_H06E0003 Q3\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 F4\narc: H01W0000 Q3\narc: H01W0100 Q3\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: N1_V02N0101 F1\narc: N3_V06N0003 Q3\narc: V00B0100 F5\narc: V01S0000 F1\narc: V01S0100 F6\narc: W1_H02W0001 F2\narc: W1_H02W0101 F1\narc: W1_H02W0301 Q3\narc: W1_H02W0401 F6\narc: W1_H02W0701 F5\narc: W3_H06W0103 F1\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 0000000011000000\nword: SLICEB.K1.INIT 0000100000000000\nword: SLICEA.K0.INIT 1110110010100000\nword: SLICEA.K1.INIT 1111001111111111\nword: SLICEC.K0.INIT 1111001111111111\nword: SLICEC.K1.INIT 0000000000001111\nword: SLICED.K0.INIT 1000111111001111\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R20C36:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 N3_V06S0303\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 H01E0001\narc: E3_H06E0303 N1_V01S0100\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H02W0401\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 H01E0101\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0501 E3_H06W0303\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00B0100 H02W0701\narc: V00T0100 W1_H02E0101\narc: W1_H02W0101 V02S0101\narc: W1_H02W0601 H01E0001\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N3_V06N0203 W3_H06E0203\narc: S1_V02S0401 W3_H06E0203\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: CE0 V02N0201\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q0\narc: H01W0100 Q0\narc: M0 V00B0100\narc: M2 V00B0000\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q0\narc: N1_V02N0201 Q0\narc: V00T0000 Q2\narc: V01S0100 Q0\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R20C37:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0701 V01N0101\narc: E3_H06E0103 V01N0101\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 H02E0201\narc: H00L0100 V02S0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 V01N0001\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0501 H02E0501\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 H01E0101\narc: V00B0000 V02N0201\narc: V00B0100 V02S0301\narc: V00T0100 N1_V02S0701\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 V02S0701\narc: E1_H02E0601 W3_H06E0303\narc: S3_V06S0203 W3_H06E0203\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: B2 H02E0301\narc: B3 H02E0301\narc: B5 H02W0101\narc: C2 V02S0401\narc: C3 H00L0100\narc: C5 V00T0100\narc: CE0 H00L0000\narc: CE1 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V02N0001\narc: D3 V02S0001\narc: D5 V00B0000\narc: E1_H01E0001 F5\narc: E1_H01E0101 Q6\narc: E3_H06E0003 F3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q0\narc: M0 H02E0601\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: V01S0000 Q0\narc: W3_H06W0103 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011000000111111\nword: SLICEB.K0.INIT 1100000011001111\nword: SLICEB.K1.INIT 0000000011111100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R20C38:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0003 N1_V01S0000\narc: H00L0000 W1_H02E0201\narc: H00R0100 H02W0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 H02E0701\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N1_V02S0501\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 H06E0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0201\narc: V00B0100 W1_H02E0701\narc: V00T0100 H02E0301\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 H01E0101\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0001 W3_H06E0003\narc: N3_V06N0203 W3_H06E0203\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: B1 V00B0000\narc: B2 S1_V02N0101\narc: B7 E1_H02W0301\narc: C1 H02W0601\narc: C2 H00L0100\narc: C7 V02S0001\narc: CE2 H00L0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 V02N0001\narc: D3 S1_V02N0001\narc: D7 F2\narc: E3_H06E0203 Q4\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0000 Q4\narc: H01W0100 Q4\narc: M2 V00T0100\narc: M4 W1_H02E0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W3_H06W0203 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0011001100001111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100000011001111\nword: SLICEB.K0.INIT 1111000000110011\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R20C39:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0303 W1_H02E0601\narc: H00L0100 E1_H02W0101\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 H01E0101\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02W0401\narc: V00B0100 V02N0101\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 S1_V02N0701\narc: H01W0000 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: B5 V02S0701\narc: C3 W1_H02E0401\narc: C5 H02E0401\narc: C7 E1_H02W0601\narc: CE0 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 H02E0201\narc: D2 V00B0100\narc: D3 H02E0001\narc: D5 H00R0100\narc: D7 H02W0001\narc: E1_H01E0001 F1\narc: E1_H02E0301 Q1\narc: E1_H02E0701 F7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: M0 V00B0000\narc: M1 H00L0100\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: N3_V06N0103 Q1\narc: V01S0000 F1\narc: W3_H06W0103 Q1\narc: W3_H06W0303 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011111100000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R20C3:PLC2\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0401 V02S0401\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02W0401\narc: H00R0100 H02W0701\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0601 H02W0601\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 S1_V02N0201\narc: V00T0000 V02S0601\narc: V01S0000 S3_V06N0103\narc: CE2 H00L0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 N1_V01S0000\narc: D2 E1_H02W0001\narc: D3 V01S0100\narc: E1_H01E0001 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q4\narc: M0 V00B0000\narc: M1 H00R0100\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R20C40:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 H01E0001\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 H02E0201\narc: H00L0100 V02S0301\narc: H00R0000 H02W0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 E1_H02W0401\narc: V00B0100 W1_H02E0501\narc: V00T0000 E1_H02W0201\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0301 E1_H02W0301\narc: E1_H02E0701 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: N1_V02N0301 W3_H06E0003\narc: S1_V02S0301 W3_H06E0003\narc: S1_V02S0401 W3_H06E0203\narc: S1_V02S0701 W3_H06E0203\narc: S3_V06S0003 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: A1 H02W0501\narc: A3 H02W0501\narc: A5 H02W0501\narc: B1 H00R0100\narc: B3 H00R0100\narc: B5 W1_H02E0301\narc: B6 N1_V02S0701\narc: C1 V02N0401\narc: C3 H00L0000\narc: C5 V00T0000\narc: C6 V02S0201\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D3 E1_H02W0001\narc: D5 V00B0000\narc: D6 H00L0100\narc: D7 E1_H01W0100\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F4\narc: M0 V00T0100\narc: M2 V00T0100\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F2\narc: S3_V06S0303 Q6\narc: V01S0000 F0\nword: SLICED.K0.INIT 0000000011110011\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1110001100110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1110001100110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1110001100110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R20C41:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 N1_V02S0701\narc: H00L0100 S1_V02N0301\narc: H00R0100 V02S0501\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 V01N0001\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 H06E0003\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02E0701\narc: V00T0000 N1_V02S0601\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0701 S3_V06N0203\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: H01W0000 W3_H06E0103\narc: N1_V02N0001 W3_H06E0003\narc: S1_V02S0001 W3_H06E0003\narc: S1_V02S0101 W3_H06E0103\narc: S1_V02S0301 W3_H06E0003\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A0 S1_V02N0501\narc: A4 V02S0301\narc: B0 H00R0100\narc: B4 H02E0101\narc: C0 H00L0100\narc: C4 V00T0000\narc: C6 V02N0201\narc: C7 V02S0201\narc: CE1 W1_H02E0101\narc: CE2 W1_H02E0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 N1_V02S0001\narc: D4 V00B0000\narc: D5 N1_V02S0601\narc: D6 V02N0401\narc: D7 H02E0001\narc: E1_H01E0101 F0\narc: F0 F5A_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F4\narc: M0 V00B0100\narc: M2 E1_H02W0601\narc: M4 E1_H01E0101\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q6\narc: N1_V02N0601 Q4\narc: N3_V06N0203 Q4\narc: S3_V06S0303 Q6\narc: V01S0000 F4\narc: V01S0100 Q6\narc: W1_H02W0501 F7\narc: W1_H02W0601 Q6\narc: W3_H06W0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEC.K0.INIT 1111000111110011\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111010100110001\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R20C42:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V06S0203\narc: H00L0000 H02E0001\narc: H00L0100 V02N0101\narc: H00R0000 W1_H02E0401\narc: H00R0100 V02S0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0203 S1_V02N0401\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02E0701\narc: V00T0100 H02E0101\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 V01N0001\narc: W1_H02W0701 V02N0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0101 W3_H06E0103\narc: S1_V02S0401 W3_H06E0203\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0303 E3_H06W0303\narc: A7 H00L0000\narc: B0 E1_H01W0100\narc: B3 H00R0100\narc: B5 V00B0100\narc: B7 H02W0301\narc: C0 H00L0100\narc: C2 H02E0401\narc: C3 N1_V02S0401\narc: C5 W1_H02E0601\narc: C6 H01E0001\narc: C7 H02W0401\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 N1_V02S0201\narc: D1 H02E0201\narc: D2 S1_V02N0201\narc: D3 H00R0000\narc: D5 V02N0401\narc: D6 V02N0601\narc: D7 V02N0601\narc: E3_H06E0103 F2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q3\narc: H01W0100 Q5\narc: M0 V00T0100\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F6\narc: N3_V06N0303 Q5\narc: S1_V02S0201 F0\narc: V01S0100 Q5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000110000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1111110000110000\nword: SLICEA.K0.INIT 1111110000001100\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 1010100000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R20C43:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V02S0701\narc: E3_H06E0003 S3_V06N0003\narc: H00L0100 V02S0301\narc: H00R0000 H02W0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 V01N0001\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H01E0101\narc: S3_V06S0103 H01E0101\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02N0001\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02N0601\narc: V00T0100 W1_H02E0301\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E1_H01W0000\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A5 V00T0100\narc: B1 V02S0101\narc: B2 H02W0101\narc: B3 H00L0000\narc: B5 V02N0701\narc: B6 H02E0301\narc: B7 V00B0000\narc: C1 H02W0601\narc: C2 H02W0601\narc: C3 H00L0100\narc: C4 V00T0100\narc: C5 S1_V02N0201\narc: C6 E1_H01E0101\narc: C7 N1_V02S0001\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 V01S0100\narc: D3 N1_V02S0201\narc: D4 V02N0401\narc: D5 V02N0401\narc: D6 V02S0601\narc: D7 S1_V02N0601\narc: E1_H01E0001 F3\narc: E1_H01E0101 F7\narc: E1_H02E0201 F2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 Q1\narc: H01W0100 F6\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: N1_V02N0301 F1\narc: V01S0100 F4\narc: W3_H06W0103 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100000011001111\nword: SLICED.K0.INIT 1100110000001111\nword: SLICED.K1.INIT 0000111100110011\nword: SLICEB.K0.INIT 1100000011001111\nword: SLICEB.K1.INIT 0000111100001100\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1010100000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R20C44:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 V06S0003\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 H02W0201\narc: H00L0100 H02W0301\narc: H00R0000 E1_H02W0401\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 H01E0001\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 H02E0601\narc: V00B0100 H02E0701\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0601 V06N0303\narc: W1_H02W0701 S3_V06N0203\narc: E1_H01E0001 W3_H06E0003\narc: H01W0000 W3_H06E0103\narc: S1_V02S0401 W3_H06E0203\narc: S3_V06S0303 W3_H06E0303\narc: A3 V00B0000\narc: A5 V00B0000\narc: B0 H02W0101\narc: B3 H00L0000\narc: B5 S1_V02N0701\narc: B6 N1_V02S0701\narc: C0 H02W0601\narc: C2 H02E0601\narc: C3 S1_V02N0601\narc: C4 H02E0601\narc: C5 S1_V02N0001\narc: C6 E1_H01E0101\narc: C7 V02S0001\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V00T0100\narc: D2 V02N0001\narc: D3 V02N0001\narc: D4 H00L0100\narc: D5 H00L0100\narc: D6 V02N0601\narc: D7 H02W0001\narc: E1_H01E0101 F0\narc: E1_H02E0001 F2\narc: E3_H06E0203 F7\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M0 V00B0100\narc: M2 W1_H02E0601\narc: M4 H02E0401\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: V01S0100 Q6\narc: W1_H02W0401 F4\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1100111100000011\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 0000001111001111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 1010100000000000\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1010100000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R20C45:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 N1_V02S0601\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02S0601\narc: H00R0100 H02E0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 H02W0301\narc: N1_V02N0501 S1_V02N0501\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0001\narc: V00B0100 V02S0101\narc: V00T0000 H02E0201\narc: V00T0100 W1_H02E0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V06N0003\narc: W1_H02W0401 E1_H01W0000\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A1 H00L0000\narc: B0 H02W0101\narc: B1 E1_H02W0101\narc: B2 V02N0301\narc: B3 H01W0100\narc: B4 N1_V02S0501\narc: B6 V02S0701\narc: C0 H02E0601\narc: C1 N1_V02S0401\narc: C2 H02E0601\narc: C3 E1_H02W0601\narc: C4 H02W0601\narc: C6 H02E0401\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 H00R0000\narc: D2 H02E0001\narc: D3 V00B0100\narc: D4 V02N0601\narc: D5 V02N0401\narc: D6 H00L0100\narc: D7 F2\narc: E1_H01E0101 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q0\narc: H01W0000 F0\narc: H01W0100 Q2\narc: LSR0 V00B0000\narc: M4 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V02N0001 F2\narc: S1_V02S0101 F1\narc: V01S0000 F6\narc: W1_H02W0601 F4\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\nword: SLICEA.K0.INIT 1100000011001111\nword: SLICEA.K1.INIT 1101000100010001\nword: SLICEB.K0.INIT 1100000011001111\nword: SLICEB.K1.INIT 0000111100001100\nword: SLICED.K0.INIT 1111110000001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R20C46:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0701 V02N0701\narc: E3_H06E0203 W1_H02E0701\narc: H00R0000 V02N0401\narc: H00R0100 V02S0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02E0201\narc: V00T0100 W1_H02E0101\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 N1_V01S0000\narc: E1_H01E0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A7 H02W0701\narc: B1 H02E0101\narc: B3 E1_H02W0301\narc: B4 H00R0000\narc: B7 V00B0000\narc: C1 H00R0100\narc: C3 H02W0401\narc: C4 V00T0100\narc: C7 V00T0000\narc: D1 V02S0201\narc: D3 V02S0201\narc: D4 S1_V02N0401\narc: D5 V02N0601\narc: D7 H02W0001\narc: E1_H01E0101 F3\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 F7\narc: M4 V00B0100\narc: N1_V01N0101 F3\narc: N1_V02N0101 F1\narc: N1_V02N0301 F1\narc: S1_V02S0101 F1\narc: S1_V02S0401 F4\narc: S3_V06S0103 F1\narc: W3_H06W0003 F3\narc: W3_H06W0103 F1\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0101111100010011\nword: SLICEC.K0.INIT 1111110000001100\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R20C47:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 H02E0201\narc: H00L0100 V02N0101\narc: H00R0000 E1_H02W0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 V01N0001\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 E1_H01W0000\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 H01E0101\narc: V00B0100 H02E0501\narc: V00T0000 V02S0601\narc: V00T0100 V02S0501\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 E1_H02W0601\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: H01W0000 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: S1_V02S0201 W3_H06E0103\narc: S1_V02S0301 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A1 H00R0000\narc: A5 V02N0301\narc: B1 H00R0100\narc: B2 E1_H01W0100\narc: B5 H00L0000\narc: B6 N1_V02S0701\narc: C1 W1_H02E0601\narc: C2 H00L0100\narc: C4 H02E0401\narc: C5 S1_V02N0001\narc: C6 H02W0601\narc: C7 V00T0100\narc: CE1 V02N0201\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D2 S1_V02N0201\narc: D3 E1_H02W0001\narc: D4 H02E0001\narc: D5 H02E0001\narc: D6 V02N0401\narc: D7 H02W0201\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F2\narc: E3_H06E0203 F7\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: M2 V00T0000\narc: M4 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F4\narc: N1_V01N0101 Q6\narc: N1_V02N0201 F2\narc: S3_V06S0103 F1\narc: V01S0000 Q6\narc: V01S0100 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0101111100010011\nword: SLICED.K0.INIT 0000111100000011\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 0000110011111100\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1100100000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R20C48:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0201 V02S0201\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 N3_V06S0103\narc: H00L0000 E1_H02W0001\narc: H00R0000 V02S0401\narc: H00R0100 W1_H02E0701\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 H02W0501\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 H06E0203\narc: V00B0000 H02W0401\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02W0201\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0601 V02S0601\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0601 W3_H06E0303\narc: N1_V02N0501 W3_H06E0303\narc: S1_V02S0601 W3_H06E0303\narc: S3_V06S0303 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A1 H01E0001\narc: B0 V02N0301\narc: B1 W1_H02E0301\narc: B4 H01E0101\narc: B6 V02N0501\narc: B7 H02E0101\narc: C0 H00L0000\narc: C1 H00R0100\narc: C4 E1_H02W0401\narc: C6 H02E0401\narc: C7 E1_H02W0401\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 S1_V02N0001\narc: D4 H00L0100\narc: D5 F0\narc: D6 V00B0000\narc: D7 V02N0601\narc: E1_H01E0001 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0000 Q6\narc: H01W0100 Q0\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M2 V00T0000\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q2\narc: N1_V02N0001 F0\narc: S1_V02S0401 F4\narc: V01S0000 F7\narc: V01S0100 F6\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1100000011001111\nword: SLICED.K1.INIT 1111110000001100\nword: SLICEA.K0.INIT 1100000011001111\nword: SLICEA.K1.INIT 0000000001011100\nword: SLICEC.K0.INIT 0000000011001111\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R20C49:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 S1_V02N0001\narc: H00L0100 S1_V02N0301\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 V01N0001\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H06W0003\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00B0100 V02N0101\narc: V00T0000 W1_H02E0201\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 V02N0701\narc: H01W0100 W3_H06E0303\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: A1 E1_H01E0001\narc: A3 H02E0701\narc: A5 E1_H02W0701\narc: A7 H00R0000\narc: B0 H02W0301\narc: B1 E1_H01W0100\narc: B3 V02S0301\narc: B5 H00L0000\narc: B6 V00B0000\narc: B7 V02N0501\narc: C0 V02S0601\narc: C1 H00L0100\narc: C3 W1_H02E0601\narc: C4 V00T0000\narc: C5 V00T0000\narc: C6 H02W0601\narc: C7 V00T0100\narc: CE0 V02N0201\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 E1_H02W0201\narc: D3 H02W0201\narc: D4 N1_V02S0601\narc: D5 N1_V02S0601\narc: D6 H02E0201\narc: D7 E1_H02W0201\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q6\narc: E3_H06E0003 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q6\narc: LSR1 W1_H02E0501\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0101 F3\narc: S1_V02S0101 F1\narc: W1_H02W0401 F4\narc: W1_H02W0501 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000010101010\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0101101000111100\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 0101101000111100\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1110000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R20C4:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: H00R0000 H02E0401\narc: N1_V02N0201 H06W0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0701\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 S3_V06N0203\narc: A1 V02N0501\narc: A2 V02N0501\narc: B1 H02W0301\narc: B2 H02W0301\narc: B4 V02N0701\narc: B5 V00B0100\narc: C1 F4\narc: C2 F4\narc: C4 H02W0401\narc: C5 H01E0001\narc: CE2 E1_H02W0101\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D2 H02W0201\narc: D4 H02E0201\narc: D5 V00B0000\narc: E1_H01E0001 Q6\narc: E1_H02E0301 F1\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: M0 V00T0000\narc: M1 H00R0000\narc: M2 N1_V01N0001\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000110011111100\nword: SLICEC.K1.INIT 0000111111001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000101011001111\nword: SLICEB.K0.INIT 1000101011001111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R20C50:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0401 V06N0203\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 H01E0001\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0303 V06S0303\narc: H00L0000 S1_V02N0201\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02E0601\narc: V00T0000 H02W0001\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0103 V01N0101\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: B1 V02S0101\narc: B2 V02S0301\narc: B3 H01W0100\narc: B4 V00B0100\narc: B5 N1_V01S0000\narc: B6 V00B0000\narc: B7 V01S0000\narc: C1 H00L0000\narc: C2 H00R0100\narc: C3 S1_V02N0401\narc: C4 V00T0000\narc: C5 V00T0100\narc: C6 H02W0601\narc: C7 E1_H02W0401\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D2 H02E0001\narc: D3 H02E0001\narc: D4 H02E0001\narc: D5 H02E0001\narc: D6 H02E0001\narc: D7 H02E0001\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q7\narc: E1_H02E0101 Q3\narc: E1_H02E0201 Q2\narc: E1_H02E0301 Q1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: H01W0100 Q4\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q3\narc: N1_V02N0101 Q1\narc: V00B0100 Q5\narc: V01S0000 Q2\narc: V01S0100 Q5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000110011\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R20C51:PLC2\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0103 V06N0103\narc: H00L0000 H02E0201\narc: H00L0100 V02N0301\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 V01N0001\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 V01N0101\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H06E0303\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 H02E0601\narc: V00B0100 V02S0301\narc: V00T0100 V02S0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02N0701\narc: E1_H02E0101 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0303 S3_V06N0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: A1 E1_H01E0001\narc: A3 V00T0000\narc: A5 H02E0501\narc: A7 H00R0000\narc: B0 W1_H02E0301\narc: B1 H02E0301\narc: B2 H00R0000\narc: B3 H00L0000\narc: B4 H02W0101\narc: B5 H01E0101\narc: B6 V00B0000\narc: B7 H02E0101\narc: C0 N1_V02S0601\narc: C1 H02W0601\narc: C2 V02S0401\narc: C3 H02W0601\narc: C4 V00T0100\narc: C5 H02W0601\narc: C6 V00B0100\narc: C7 H02W0601\narc: CE0 V02S0201\narc: CE1 V02S0201\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 V02N0201\narc: D2 H02W0201\narc: D3 V02N0201\narc: D4 H02W0201\narc: D5 V02N0601\narc: D6 H02W0201\narc: D7 V02N0601\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q6\narc: H01W0000 F7\narc: H01W0100 Q4\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q0\narc: S1_V02S0701 F5\narc: V00T0000 Q2\narc: V01S0000 F1\narc: V01S0100 Q4\narc: W1_H02W0301 F3\narc: W3_H06W0003 Q0\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0101101000111100\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0101101000111100\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 0101101000111100\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0101101000111100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R20C52:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 H02E0201\narc: H00L0100 H02E0301\narc: H00R0100 V02S0701\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0401\narc: V00B0000 H02W0601\narc: V00B0100 H02W0501\narc: V00T0100 V02S0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 V02N0601\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A1 E1_H01E0001\narc: A3 V00T0000\narc: A5 N1_V01N0101\narc: A7 H00R0000\narc: B0 V00T0000\narc: B1 E1_H01W0100\narc: B2 V02N0301\narc: B3 H00L0000\narc: B4 H00R0000\narc: B5 V00B0100\narc: B6 V01S0000\narc: B7 V00B0000\narc: C0 H00R0100\narc: C1 H02E0601\narc: C2 N1_V01S0100\narc: C3 H02E0601\narc: C4 V00T0100\narc: C5 H02E0601\narc: C6 N1_V02S0201\narc: C7 H02E0601\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 H00L0100\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 E1_H02W0001\narc: D2 V02S0201\narc: D3 E1_H02W0001\narc: D4 H02W0001\narc: D5 V02N0601\narc: D6 H02W0001\narc: D7 V02N0601\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q6\narc: H01W0000 F1\narc: H01W0100 F7\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q4\narc: N1_V02N0201 Q2\narc: N1_V02N0601 Q6\narc: V00T0000 Q2\narc: V01S0000 Q0\narc: V01S0100 Q0\narc: W1_H02W0501 F5\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 0101001110101100\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0101001110101100\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0101001110101100\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0101001110101100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R20C53:PLC2\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 W1_H02E0201\narc: H00L0100 H02W0101\narc: H00R0000 H02W0601\narc: H00R0100 V02S0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 V01N0101\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 H01E0101\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0601\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0401 E1_H01W0000\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0501 W3_H06E0303\narc: E1_H02E0601 W3_H06E0303\narc: S1_V02S0501 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: B2 H00R0100\narc: B3 S1_V02N0101\narc: B4 H02E0301\narc: B5 H00L0000\narc: B6 V00B0100\narc: B7 V01S0000\narc: C1 H00L0100\narc: C2 V02N0401\narc: C3 S1_V02N0401\narc: C4 W1_H02E0401\narc: C5 V02N0201\narc: C6 S1_V02N0001\narc: C7 H02W0401\narc: CE1 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 V00B0000\narc: D5 V00B0000\narc: D6 V00B0000\narc: D7 V00B0000\narc: E1_H02E0101 Q3\narc: E1_H02E0201 Q2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q5\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q3\narc: N1_V02N0301 F1\narc: S1_V02S0401 Q6\narc: V00B0100 Q7\narc: V01S0000 Q4\narc: V01S0100 Q6\narc: W1_H02W0501 Q7\narc: W1_H02W0601 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R20C54:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0701 E1_H01W0100\narc: H00L0100 V02N0101\narc: H00R0000 S1_V02N0601\narc: H00R0100 V02N0701\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 V01N0101\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0201 H01E0001\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 E1_H02W0401\narc: V00B0100 V02S0301\narc: V00T0100 V02N0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 H01E0001\narc: S3_V06S0103 W3_H06E0103\narc: W3_H06W0303 E1_H01W0100\narc: A1 E1_H01E0001\narc: A3 V00T0000\narc: A5 N1_V01N0101\narc: A7 H02W0701\narc: B0 V01N0001\narc: B1 V02N0301\narc: B2 H00L0000\narc: B3 H02E0101\narc: B4 S1_V02N0701\narc: B5 H00R0000\narc: B6 V02S0701\narc: B7 V00B0000\narc: C0 N1_V01S0100\narc: C1 H02W0601\narc: C2 V02S0401\narc: C3 H02W0601\narc: C4 H02E0401\narc: C5 V02N0001\narc: C6 V00B0100\narc: C7 V02N0001\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 V00T0100\narc: D2 H02W0001\narc: D3 V00T0100\narc: D4 H02W0001\narc: D5 H00R0100\narc: D6 H02W0001\narc: D7 H00R0100\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q6\narc: E3_H06E0103 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0000 F7\narc: H01W0100 Q6\narc: LSR0 H02E0301\narc: LSR1 H02E0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q4\narc: N1_V02N0001 Q0\narc: V00T0000 Q2\narc: W1_H02W0301 F1\narc: W1_H02W0501 F5\narc: W3_H06W0003 F3\narc: W3_H06W0103 Q2\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 0101001110101100\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0101001110101100\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0101001110101100\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0101001110101100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R20C55:PLC2\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V02N0601\narc: H00L0000 E1_H02W0201\narc: H00L0100 V02N0301\narc: H00R0100 V02S0501\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: V00B0100 H02W0501\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02S0701\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 H01E0101\narc: N1_V02N0401 W3_H06E0203\narc: N3_V06N0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A0 E1_H01E0001\narc: A2 H02E0701\narc: B0 H00R0100\narc: B1 V00T0000\narc: B2 N1_V02S0301\narc: B3 V02S0101\narc: C0 E1_H02W0601\narc: C1 S1_V02N0401\narc: C2 E1_H02W0601\narc: C3 H00L0000\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 W1_H02E0001\narc: D2 H02E0201\narc: D3 W1_H02E0001\narc: E1_H01E0001 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0000 F0\narc: H01W0100 Q3\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q1\narc: S3_V06S0303 Q6\narc: V01S0100 Q4\narc: W3_H06W0003 Q3\narc: W3_H06W0103 F2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0011010111001010\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 0011010111001010\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R20C56:PLC2\narc: H00L0000 H02E0201\narc: H00R0000 H02E0601\narc: H00R0100 H02W0701\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0501 H02E0501\narc: N3_V06N0003 H06W0003\narc: S1_V02S0001 H06E0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: V00T0100 W1_H02E0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N1_V02S0501\narc: N1_V02N0401 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A1 E1_H01E0001\narc: A3 V02S0501\narc: A5 H02W0701\narc: B0 E1_H02W0101\narc: B1 S1_V02N0101\narc: B2 H00R0100\narc: B3 V01N0001\narc: B4 V00B0100\narc: B5 V02N0701\narc: B6 V02S0701\narc: B7 V00B0000\narc: C0 V02S0601\narc: C1 H00L0000\narc: C2 H02E0401\narc: C3 H02W0601\narc: C4 V00T0100\narc: C5 V02N0201\narc: C6 V02S0201\narc: C7 V02S0001\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 W1_H02E0201\narc: D2 V02S0201\narc: D3 W1_H02E0201\narc: D4 V02S0601\narc: D5 W1_H02E0201\narc: D6 V02S0401\narc: D7 V02S0601\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q6\narc: H01W0100 Q0\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q2\narc: V00B0000 Q6\narc: V00B0100 Q7\narc: V01S0000 F5\narc: V01S0100 Q7\narc: W1_H02W0601 Q6\narc: W1_H02W0701 Q7\narc: W3_H06W0003 F3\narc: W3_H06W0103 F1\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0101001110101100\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0101001110101100\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 0100011110111000\nword: SLICED.K0.INIT 1100111111000000\nword: SLICED.K1.INIT 1100110011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R20C57:PLC2\narc: N1_V02N0201 H02W0201\narc: N3_V06N0003 V01N0001\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 H01E0101\narc: N3_V06N0103 W3_H06E0103\narc: S1_V02S0701 W3_H06E0203\narc: S3_V06S0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\n\n.tile R20C58:PLC2\narc: N1_V02N0201 N1_V01S0000\narc: N3_V06N0103 S3_V06N0003\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0303 H06E0303\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 E1_H01W0100\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0101 W3_H06E0103\n\n.tile R20C59:PLC2\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: H01W0100 W3_H06E0303\narc: S3_V06S0003 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\n\n.tile R20C5:PLC2\narc: E1_H02E0301 V02S0301\narc: E1_H02E0601 N1_V01S0000\narc: H00L0000 S1_V02N0001\narc: H00L0100 E1_H02W0301\narc: H00R0000 V02S0401\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00B0100 V02N0301\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 E1_H02W0101\narc: A0 H00L0100\narc: A6 V00T0100\narc: B0 V00B0000\narc: B6 V00B0000\narc: C0 H02W0601\narc: C6 H02W0601\narc: D0 V02N0001\narc: D6 V02N0601\narc: E1_H02E0101 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00L0000\narc: M2 V00B0100\narc: M3 H00R0000\narc: M4 V00B0100\narc: M5 H00L0000\narc: M6 V00B0100\nword: SLICEA.K0.INIT 1010001011110011\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1010001011110011\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R20C60:PLC2\narc: S1_V02S0301 N1_V02S0201\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 H06E0303\narc: W1_H02W0101 W3_H06E0103\n\n.tile R20C62:PLC2\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: E3_H06E0003 W3_H06E0303\n\n.tile R20C63:PLC2\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\n\n.tile R20C64:PLC2\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\n\n.tile R20C65:PLC2\narc: S3_V06S0003 H06E0003\narc: W3_H06W0303 E3_H06W0203\n\n.tile R20C66:PLC2\narc: S3_V06S0103 H06E0103\n\n.tile R20C69:PLC2\narc: E1_H02E0301 V02N0301\n\n.tile R20C6:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V01N0101\narc: H00L0000 H02W0001\narc: H00L0100 E1_H02W0301\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0501 N3_V06S0303\narc: V00B0000 V02N0201\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02S0601\narc: V00T0100 V02N0501\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V02N0601\narc: A1 V02N0701\narc: A2 V02N0701\narc: A3 V02N0701\narc: B1 H02E0301\narc: B2 H00L0000\narc: B3 H00L0000\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 V00T0000\narc: C5 F4\narc: C6 V00B0100\narc: C7 V00T0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D2 V02N0001\narc: D3 V02N0001\narc: D4 S1_V02N0601\narc: D5 S1_V02N0401\narc: D6 V00B0000\narc: D7 V02N0401\narc: E1_H02E0301 F1\narc: E1_H02E0401 Q6\narc: E1_H02E0501 Q5\narc: E3_H06E0203 Q7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: M0 H02E0601\narc: M1 V01S0100\narc: M2 H02E0601\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F4\narc: N1_V02N0701 F5\narc: V01S0100 F6\nword: SLICED.K0.INIT 0000000000001111\nword: SLICED.K1.INIT 0000000000001111\nword: SLICEC.K0.INIT 0000000000001111\nword: SLICEC.K1.INIT 0000000000001111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010001011110011\nword: SLICEB.K0.INIT 1010001011110011\nword: SLICEB.K1.INIT 1010001011110011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R20C7:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0201 H01E0001\narc: E1_H02E0401 V02N0401\narc: H00L0000 S1_V02N0001\narc: H00L0100 H02W0301\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0601 H06W0303\narc: S1_V02S0501 S3_V06N0303\narc: S3_V06S0003 H06W0003\narc: V00T0100 H02E0301\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0701 S1_V02N0701\narc: W3_H06W0103 S3_V06N0103\narc: A1 V01N0101\narc: B1 W1_H02E0101\narc: C1 H02E0601\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: E3_H06E0003 Q3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H02E0001\narc: M2 V00T0100\narc: M3 H00L0000\narc: M4 V00T0100\narc: M5 H02E0001\narc: M6 V00T0100\narc: MUXCLK1 CLK0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R20C8:PLC2\narc: E1_H02E0701 W1_H02E0701\narc: H00R0100 V02N0501\narc: N1_V02N0401 W1_H02E0401\narc: S1_V02S0101 N3_V06S0103\narc: S3_V06S0003 H01E0001\narc: V00B0100 W1_H02E0501\narc: V00T0000 S1_V02N0401\narc: V00T0100 V02N0701\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0301 E3_H06W0003\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: E1_H02E0401 Q4\narc: E3_H06E0003 Q0\narc: E3_H06E0303 Q6\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 H02E0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0401 Q6\narc: S3_V06S0103 Q2\narc: S3_V06S0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R20C9:PLC2\narc: E1_H02E0301 H01E0101\narc: H00L0000 H02W0201\narc: H00R0000 V02N0601\narc: H00R0100 E1_H02W0501\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0301 E1_H01W0100\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02E0701\narc: V00T0100 H02W0101\narc: W1_H02W0301 S1_V02N0301\narc: B3 V02S0101\narc: C3 H00L0000\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D3 W1_H02E0201\narc: E1_H02E0401 Q6\narc: E1_H02E0601 Q4\narc: F3 F3_SLICE\narc: M0 V00B0000\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0003 Q3\narc: S3_V06S0203 Q4\narc: V01S0000 Q6\narc: V01S0100 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100111111000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R21C10:PLC2\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 E1_H01W0100\narc: H00L0000 V02N0201\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02N0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H06W0303\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 H06W0303\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00T0000 N1_V02S0401\narc: V00T0100 E1_H02W0301\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 E3_H06W0203\narc: B1 V00T0000\narc: B3 H02E0101\narc: B5 V02S0501\narc: B7 V00B0000\narc: C1 H00L0000\narc: C3 H00L0000\narc: C5 V02N0201\narc: C7 V00T0100\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D3 S1_V02N0001\narc: D5 H00L0100\narc: D7 V02S0601\narc: E1_H01E0101 Q5\narc: E1_H02E0301 Q1\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0000 Q7\narc: V01S0100 Q3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100111111000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100111111000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100111111000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111001111000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R21C11:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: H00R0000 S1_V02N0401\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 H06W0003\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0001\narc: V00T0000 H02E0201\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: W3_H06W0103 E3_H06W0003\narc: A0 H00L0100\narc: A3 E1_H01E0001\narc: A6 V02N0301\narc: B0 V00B0000\narc: B1 V00T0000\narc: B3 H00L0000\narc: B4 H02E0301\narc: B6 V00B0000\narc: B7 H01E0101\narc: C0 V02N0401\narc: C1 H02E0401\narc: C2 V02N0601\narc: C3 N1_V01S0100\narc: C4 W1_H02E0401\narc: C5 F4\narc: C6 V00B0100\narc: C7 W1_H02E0601\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H02W0001\narc: D2 V02N0001\narc: D3 F2\narc: D4 H02W0001\narc: D5 E1_H01W0100\narc: D6 N1_V02S0601\narc: D7 H02W0001\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q4\narc: E1_H02E0301 Q1\narc: E1_H02E0501 F5\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H00L0100 Q1\narc: H01W0100 F4\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 F4\narc: N1_V02N0301 F3\narc: S1_V02S0101 F1\narc: S1_V02S0501 F7\narc: S3_V06S0203 F4\narc: V00B0100 F7\narc: V01S0000 F1\narc: V01S0100 Q7\nword: SLICED.K0.INIT 0100000001110000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0000000000001111\nword: SLICEA.K0.INIT 0000101100001000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 0000000000001111\nword: SLICEB.K1.INIT 0000000000000001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R21C12:PLC2\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 V06S0303\narc: H00L0000 H02E0201\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02W0401\narc: H00R0100 V02N0701\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 S1_V02N0501\narc: S1_V02S0001 V01N0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 V01N0001\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00B0100 H02E0501\narc: V00T0000 V02S0601\narc: W1_H02W0001 V06S0003\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V06S0303\narc: A1 V02N0501\narc: A2 V00B0000\narc: A3 E1_H01E0001\narc: A5 W1_H02E0501\narc: A7 N1_V01S0100\narc: B0 V02S0101\narc: B1 H00R0100\narc: B2 H02E0101\narc: B3 V02N0301\narc: B4 H01E0101\narc: B5 H02W0101\narc: B7 N1_V01S0000\narc: C0 H00L0000\narc: C1 H00L0100\narc: C2 E1_H02W0601\narc: C3 N1_V02S0601\narc: C4 V02S0001\narc: C5 F4\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 V00B0100\narc: D2 S1_V02N0201\narc: D3 V00T0100\narc: D4 H02W0001\narc: D5 V01N0001\narc: D7 V02N0601\narc: E1_H01E0001 F2\narc: E3_H06E0003 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F4\narc: LSR0 E1_H02W0501\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F5\narc: N1_V02N0101 F3\narc: N1_V02N0701 F7\narc: S3_V06S0003 F0\narc: V00T0100 F1\narc: V01S0100 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1011010010000111\nword: SLICEC.K0.INIT 0011000000111111\nword: SLICEC.K1.INIT 0101111101001100\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 0000000000010010\nword: SLICEB.K0.INIT 0010110101111000\nword: SLICEB.K1.INIT 0100000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R21C13:PLC2\narc: E1_H02E0101 V06N0103\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 V06S0203\narc: H00R0000 E1_H02W0401\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 S1_V02N0101\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 V01N0101\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 V02S0601\narc: V00T0100 V02N0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0601 V02N0601\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: W3_H06W0103 E3_H06W0003\narc: B7 V00T0000\narc: C6 E1_H01E0101\narc: C7 H02E0401\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D6 E1_H02W0001\narc: D7 H02W0001\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F7\narc: E1_H02E0201 Q0\narc: E1_H02E0401 Q4\narc: E3_H06E0303 F6\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00B0100\narc: M2 V00B0000\narc: M4 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: V01S0000 F7\narc: V01S0100 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000111100000000\nword: SLICED.K1.INIT 0011000000111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R21C14:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 H01E0001\narc: H00L0000 V02N0001\narc: H00L0100 H02E0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0103 H06W0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0100 S1_V02N0101\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 E1_H01W0000\narc: E1_H02E0101 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: A0 H00L0100\narc: A1 H00L0100\narc: A2 H00L0100\narc: A3 H00L0100\narc: A4 V02N0101\narc: A5 V02S0101\narc: B0 E1_H02W0301\narc: B1 E1_H02W0301\narc: B2 E1_H02W0301\narc: B3 E1_H02W0301\narc: B4 V02S0501\narc: B5 H02E0101\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 V00B0100\narc: C5 V02N0201\narc: C7 H02W0601\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE3 H00R0000\narc: CLK1 G_HPBX0000\narc: D0 H02W0201\narc: D1 H02W0201\narc: D2 H02W0201\narc: D3 H02W0201\narc: D4 E1_H02W0201\narc: D5 V02N0401\narc: D7 E1_H02W0201\narc: E1_H01E0001 Q7\narc: E1_H01E0101 F1\narc: E1_H02E0301 Q1\narc: E1_H02E0501 Q7\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: H01W0100 Q2\narc: LSR0 H02E0501\narc: LSR1 V00T0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXCLK3 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q7\narc: S1_V02S0001 Q0\narc: S1_V02S0701 Q7\narc: S3_V06S0103 Q1\narc: V01S0000 F0\narc: V01S0100 Q0\narc: W1_H02W0101 F1\narc: W1_H02W0201 Q2\narc: W1_H02W0301 Q1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R21C15:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 N1_V01S0100\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0103 V01N0101\narc: H00L0000 S1_V02N0201\narc: H00R0000 S1_V02N0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H01E0101\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0401\narc: V00B0100 V02S0101\narc: V00T0000 V02N0401\narc: V00T0100 H02E0101\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0601 H01E0001\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A1 E1_H01E0001\narc: A2 V01N0101\narc: A6 N1_V01N0101\narc: B1 H01W0100\narc: B2 H00L0000\narc: B3 V02N0101\narc: B4 N1_V02S0701\narc: B5 V02N0701\narc: B6 V01S0000\narc: B7 S1_V02N0701\narc: C1 H00L0100\narc: C2 H02E0601\narc: C3 W1_H02E0401\narc: C4 V00T0100\narc: C5 N1_V02S0001\narc: C6 E1_H01E0101\narc: C7 V00T0000\narc: CE2 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: D2 W1_H02E0201\narc: D3 H00R0000\narc: D4 E1_H02W0201\narc: D5 V02N0601\narc: D6 H02E0201\narc: D7 H00R0100\narc: E1_H01E0001 F2\narc: E1_H01E0101 F3\narc: E3_H06E0203 F4\narc: E3_H06E0303 F5\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H01W0000 F4\narc: H01W0100 F7\narc: LSR0 V00B0000\narc: M0 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 F2\narc: N1_V02N0401 Q4\narc: N3_V06N0003 F0\narc: N3_V06N0203 Q4\narc: N3_V06N0303 F6\narc: V01S0000 F7\narc: V01S0100 F4\narc: W1_H02W0501 F5\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 1100001100000000\nword: SLICEB.K0.INIT 1000001001000001\nword: SLICEB.K1.INIT 1100001100000000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0000001100000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R21C16:PLC2\narc: E1_H02E0501 V02N0501\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0103 V01N0101\narc: H00L0100 H02W0101\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0401 W1_H02E0401\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 S1_V02N0101\narc: V00T0100 V02N0701\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0203 E3_H06W0103\narc: A6 N1_V02S0101\narc: A7 V02N0301\narc: B1 Q1\narc: B3 Q3\narc: B5 H02E0101\narc: B6 V00B0100\narc: B7 H02W0301\narc: C1 H00L0000\narc: C3 H02W0401\narc: C5 E1_H01E0101\narc: C6 H02W0601\narc: C7 E1_H02W0401\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 Q0\narc: D1 H02E0201\narc: D2 Q2\narc: D3 H02W0001\narc: D4 V00B0000\narc: D5 N1_V02S0401\narc: D6 V02N0401\narc: D7 H00L0100\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q4\narc: E1_H02E0001 Q2\narc: E1_H02E0301 Q3\narc: E1_H02E0601 F6\narc: E1_H02E0701 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0000 Q4\narc: H01W0100 Q5\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q1\narc: N1_V01N0101 Q1\narc: N1_V02N0001 Q0\narc: N1_V02N0401 Q4\narc: N1_V02N0501 Q5\narc: N1_V02N0601 Q4\narc: S1_V02S0001 Q0\narc: S1_V02S0101 Q1\narc: S1_V02S0201 Q2\narc: S1_V02S0501 Q5\narc: S1_V02S0601 Q4\narc: V00B0000 Q4\narc: V01S0000 Q3\narc: V01S0100 Q3\narc: W1_H02W0201 Q0\narc: W1_H02W0501 Q5\narc: W1_H02W0601 Q4\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0011110011001100\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0011110011001100\nword: SLICED.K0.INIT 1100000010100000\nword: SLICED.K1.INIT 1010000011000000\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 0011110011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R21C17:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 V02S0201\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V02N0701\narc: H00L0000 V02N0001\narc: H00L0100 H02W0101\narc: H00R0000 N1_V02S0401\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0601 V01N0001\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 V02N0201\narc: V00B0100 V02S0301\narc: V00T0000 H02W0201\narc: V00T0100 H02W0301\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 H01E0101\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\narc: A0 H02E0501\narc: A1 V01N0101\narc: A6 V02N0301\narc: A7 V02N0301\narc: B0 W1_H02E0301\narc: B1 S1_V02N0301\narc: B2 N1_V02S0301\narc: B5 H00L0000\narc: B6 V02S0501\narc: B7 V02N0501\narc: C0 N1_V02S0601\narc: C1 H02W0401\narc: C2 H00L0100\narc: C3 H02W0601\narc: C5 V00T0100\narc: C6 H02W0401\narc: C7 S1_V02N0201\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 V02N0201\narc: D2 V00B0100\narc: D3 W1_H02E0001\narc: D5 V00B0000\narc: D6 V00B0000\narc: D7 V02N0401\narc: E1_H01E0001 F2\narc: E1_H01E0101 F3\narc: E1_H02E0101 F1\narc: E1_H02E0301 F3\narc: E3_H06E0003 F0\narc: E3_H06E0103 F2\narc: E3_H06E0303 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: H01W0100 F3\narc: LSR0 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F7\narc: N1_V01N0101 F6\narc: N1_V02N0101 F3\narc: N3_V06N0103 Q2\narc: W3_H06W0103 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000111100110011\nword: SLICEA.K0.INIT 1010000011000000\nword: SLICEA.K1.INIT 1100000010100000\nword: SLICED.K0.INIT 1010000011000000\nword: SLICED.K1.INIT 1000010000100001\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1111000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R21C18:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 H01E0101\narc: H00L0100 W1_H02E0301\narc: H00R0100 V02S0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02W0701\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0203 H01E0001\narc: V00B0100 V02S0301\narc: V00T0000 V02S0401\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0601 H01E0001\narc: W3_H06W0103 E3_H06W0103\narc: A0 V02N0701\narc: A1 V02N0701\narc: A2 V02N0701\narc: A3 V02N0701\narc: A4 H02E0701\narc: A5 V02S0101\narc: A7 N1_V02S0101\narc: B0 V00B0000\narc: B1 V00B0000\narc: B2 H00R0000\narc: B3 H00R0000\narc: B4 S1_V02N0501\narc: B5 V02N0701\narc: B7 V00B0100\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V00T0100\narc: C5 V02N0001\narc: C6 Q6\narc: C7 V00T0000\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE3 H02W0101\narc: CLK1 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 W1_H02E0001\narc: D2 W1_H02E0001\narc: D3 W1_H02E0001\narc: D4 V02N0601\narc: D5 V02N0401\narc: D6 W1_H02E0001\narc: D7 H02E0201\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F7\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q6\narc: H01W0000 Q6\narc: H01W0100 Q6\narc: LSR0 H02W0501\narc: LSR1 E1_H02W0501\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXCLK3 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F2\narc: N1_V01N0101 Q2\narc: S1_V02S0001 Q0\narc: S1_V02S0101 Q1\narc: S1_V02S0201 F0\narc: S1_V02S0601 Q6\narc: S3_V06S0003 Q0\narc: S3_V06S0103 Q1\narc: V00B0000 Q6\narc: V01S0000 F1\narc: V01S0100 Q6\narc: W1_H02W0501 F7\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1100010001000100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R21C19:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V06S0303\narc: H00L0000 E1_H02W0001\narc: H00R0000 V02N0401\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 V01N0001\narc: S1_V02S0401 H02W0401\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02N0401\narc: V00T0100 V02N0501\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 V06N0203\narc: H01W0100 W3_H06E0303\narc: S1_V02S0501 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A0 V02N0701\narc: A1 V02N0701\narc: A2 V02N0701\narc: A3 V02N0701\narc: A4 V00B0000\narc: A5 H02E0701\narc: A7 N1_V01S0100\narc: B0 V00T0000\narc: B1 V00T0000\narc: B2 H00R0000\narc: B3 H00R0000\narc: B4 E1_H02W0301\narc: B5 V00B0100\narc: B7 N1_V01S0000\narc: C0 H00L0000\narc: C1 H00L0000\narc: C2 H00L0000\narc: C3 H00L0000\narc: C4 H02W0601\narc: C5 W1_H02E0601\narc: C7 H02E0601\narc: CE0 S1_V02N0201\narc: CE1 S1_V02N0201\narc: CLK1 G_HPBX0000\narc: D0 V02S0001\narc: D1 V02S0001\narc: D2 V02S0001\narc: D3 V02S0001\narc: D4 N1_V02S0601\narc: D5 W1_H02E0001\narc: D7 H02E0201\narc: E1_H01E0101 Q1\narc: E1_H02E0301 Q3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: LSR0 V00T0100\narc: LSR1 H02E0501\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXCLK3 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q0\narc: N1_V02N0001 Q2\narc: N3_V06N0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111110\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R21C20:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 V01N0001\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0203 W1_H02E0401\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 H02W0201\narc: H00L0100 V02S0301\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H01E0101\narc: S1_V02S0001 H02E0001\narc: S1_V02S0501 N3_V06S0303\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V06S0303\narc: E1_H02E0301 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 V01N0101\narc: A1 V01N0101\narc: B0 V02N0101\narc: B1 V02N0301\narc: B3 Q3\narc: B5 V02S0501\narc: C0 H00L0000\narc: C1 S1_V02N0601\narc: C3 N1_V01N0001\narc: C5 V00B0100\narc: C7 E1_H01E0101\narc: CE1 H00L0100\narc: CE2 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 N1_V02S0201\narc: D1 S1_V02N0001\narc: D2 Q2\narc: D3 N1_V01S0000\narc: D4 V00B0000\narc: D5 V00B0000\narc: D7 V00B0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q7\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q5\narc: H01W0100 Q2\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q7\narc: N1_V02N0001 Q2\narc: N1_V02N0501 Q5\narc: S1_V02S0201 Q2\narc: S1_V02S0301 Q3\narc: S1_V02S0401 Q4\narc: S1_V02S0701 Q5\narc: V00B0000 Q4\narc: V00B0100 Q5\narc: V01S0000 F1\narc: V01S0100 Q3\narc: W1_H02W0101 Q3\narc: W1_H02W0401 Q4\narc: W1_H02W0701 Q7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 1010110000000000\nword: SLICEA.K1.INIT 1000010000100001\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0011110011001100\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 0011110011110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R21C21:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 V02N0601\narc: H00L0000 V02S0201\narc: H00L0100 W1_H02E0101\narc: H00R0000 V02S0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 H02W0701\narc: S1_V02S0101 H02E0101\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N1_V02S0501\narc: V00B0000 S1_V02N0201\narc: V00T0000 V02N0401\narc: V00T0100 E1_H02W0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 N3_V06S0203\narc: E1_H02E0101 W3_H06E0103\narc: S3_V06S0303 W3_H06E0303\narc: W3_H06W0203 N3_V06S0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A0 V02N0501\narc: A1 N1_V02S0701\narc: A4 N1_V02S0301\narc: A7 N1_V01N0101\narc: B0 V00B0000\narc: B1 V02N0101\narc: B4 H02W0301\narc: B7 F1\narc: C0 H02W0401\narc: C1 H00L0000\narc: C3 H02E0601\narc: C4 V00B0100\narc: C5 V02S0201\narc: C7 V00T0100\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 H02E0201\narc: D3 N1_V02S0001\narc: D4 V02S0401\narc: D5 H02E0201\narc: D7 H00L0100\narc: E1_H01E0101 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q3\narc: H01W0100 Q3\narc: LSR0 W1_H02E0501\narc: LSR1 W1_H02E0501\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F0\narc: N1_V02N0301 Q3\narc: N1_V02N0601 Q6\narc: N3_V06N0303 F5\narc: V00B0100 F5\narc: W1_H02W0301 Q3\nword: SLICEA.K0.INIT 1100000010100000\nword: SLICEA.K1.INIT 1100000010100000\nword: SLICEC.K0.INIT 0001001101011111\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111110\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111111110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R21C22:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 V06N0103\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0203 V06N0203\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H02W0701\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 H02E0401\narc: W1_H02W0101 V06S0103\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 V06N0203\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A4 V02N0101\narc: A6 V02N0301\narc: B0 H02E0301\narc: B4 F3\narc: B5 H00R0000\narc: B6 H02E0101\narc: C0 H00L0100\narc: C1 N1_V02S0401\narc: C2 S1_V02N0601\narc: C3 H00R0100\narc: C4 V02N0001\narc: C5 V02S0201\narc: C6 E1_H01E0101\narc: CLK0 G_HPBX0000\narc: D0 H01E0101\narc: D1 H02E0201\narc: D2 V00T0100\narc: D3 H02W0201\narc: D4 F0\narc: D5 V02S0601\narc: D6 V00B0000\narc: E1_H01E0101 F3\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 F1\narc: H00R0000 Q4\narc: LSR1 H02E0501\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V02N0401 F6\narc: N3_V06N0003 F3\narc: N3_V06N0103 F1\narc: S3_V06S0303 F5\narc: V00T0000 F2\narc: V00T0100 F1\narc: V01S0100 F3\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0011111100000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 1000000011110000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 0001001101011111\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R21C23:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02S0501\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 E1_H02W0001\narc: H00R0100 V02N0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0201 H02W0201\narc: V00B0000 V02N0201\narc: V00B0100 E1_H02W0701\narc: V00T0000 H02W0201\narc: V00T0100 V02N0701\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0701 V06S0203\narc: H01W0000 W3_H06E0103\narc: S1_V02S0101 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0103 N3_V06S0103\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 E1_H01E0001\narc: A1 H00R0000\narc: A7 H02W0701\narc: B0 V02N0301\narc: B1 N1_V02S0101\narc: B2 H01W0100\narc: B7 V01S0000\narc: C0 H00L0000\narc: C1 H02W0401\narc: C2 E1_H01W0000\narc: C7 E1_H01E0101\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 V00B0100\narc: D2 S1_V02N0001\narc: D3 V00T0100\narc: D7 H00R0100\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F1\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 Q4\narc: H01W0100 Q2\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: S3_V06S0303 F6\narc: V01S0000 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0001001101011111\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0100000011000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R21C24:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 H02W0201\narc: H00L0100 H02W0101\narc: H01W0000 E3_H06W0103\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0701 V01N0101\narc: S3_V06S0303 H06E0303\narc: V00B0000 V02N0201\narc: V00B0100 H02E0501\narc: V00T0000 V02S0401\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 V06N0203\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 N1_V02S0701\narc: S1_V02S0101 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: B0 H01W0100\narc: B5 N1_V02S0701\narc: B6 V02N0501\narc: B7 V00T0000\narc: C0 H00L0000\narc: C1 H00L0100\narc: C5 V00T0000\narc: C6 E1_H01E0101\narc: C7 E1_H01E0101\narc: CE1 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 S1_V02N0201\narc: D5 H02E0201\narc: D6 F0\narc: D7 F0\narc: E1_H01E0001 F6\narc: E1_H01E0101 F1\narc: E1_H02E0201 F0\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M2 V00T0100\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F0\narc: N1_V01N0101 F5\narc: N1_V02N0201 F0\narc: S1_V02S0201 F0\narc: S1_V02S0301 F1\narc: S3_V06S0103 Q2\narc: V01S0100 Q2\narc: W3_H06W0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000111100110011\nword: SLICEA.K0.INIT 1100000000000000\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 0000000000001100\nword: SLICED.K1.INIT 0000000000001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R21C25:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0701 V01N0101\narc: E3_H06E0103 N1_V01S0100\narc: H00L0000 V02N0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 N1_V02S0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 H01E0001\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 V02N0301\narc: V00T0100 H02W0301\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 V02N0201\narc: W1_H02W0701 V02N0701\narc: W3_H06W0303 N3_V06S0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: A1 E1_H02W0701\narc: A2 H00L0100\narc: A4 S1_V02N0301\narc: A5 S1_V02N0101\narc: B1 H00R0100\narc: B2 V01N0001\narc: B4 H00L0000\narc: B5 H02E0101\narc: B7 S1_V02N0701\narc: C0 H02W0601\narc: C1 N1_V01N0001\narc: C2 H00R0100\narc: C4 V00T0000\narc: C5 V00B0100\narc: C6 S1_V02N0201\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V01S0100\narc: D2 F0\narc: D4 H00R0100\narc: D5 V02N0601\narc: D6 H01W0000\narc: D7 V02N0601\narc: E1_H01E0001 F5\narc: E1_H01E0101 F6\narc: E1_H02E0001 F2\narc: E1_H02E0201 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F4\narc: LSR0 H02E0301\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F0\narc: N1_V01N0101 Q1\narc: N1_V02N0601 F6\narc: V00T0000 F0\narc: V01S0100 F7\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 1111111011111111\nword: SLICED.K0.INIT 0000000000001111\nword: SLICED.K1.INIT 0011000011110000\nword: SLICEC.K0.INIT 1000101011001111\nword: SLICEC.K1.INIT 1110000011000000\nword: SLICEB.K0.INIT 0001001101011111\nword: SLICEB.K1.INIT 1111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R21C26:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 V02S0601\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 W1_H02E0201\narc: H00L0000 S1_V02N0001\narc: H00R0100 V02N0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0701 V01N0101\narc: S3_V06S0203 H06E0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02W0701\narc: V00T0100 W1_H02E0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: S1_V02S0601 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0203 E3_H06W0103\narc: A2 V00T0000\narc: A3 H02E0701\narc: A4 V00B0000\narc: A7 V02N0301\narc: B0 H02E0301\narc: B1 H02E0101\narc: B2 F3\narc: B3 H00R0100\narc: B4 V02S0501\narc: B5 H00R0000\narc: B7 F1\narc: C0 N1_V01N0001\narc: C1 W1_H02E0401\narc: C2 N1_V01S0100\narc: C3 H00L0000\narc: C4 H01E0001\narc: C5 E1_H01E0101\narc: C6 H02W0401\narc: C7 V02S0001\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 W1_H02E0001\narc: D2 H01E0101\narc: D3 V00T0100\narc: D4 V01N0001\narc: D5 H02E0201\narc: D6 N1_V02S0601\narc: D7 V02N0401\narc: E1_H01E0001 F3\narc: E1_H01E0101 F0\narc: E1_H02E0501 F7\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 F5\narc: N1_V02N0201 F0\narc: S3_V06S0103 Q2\narc: V00T0000 Q2\narc: V01S0000 F6\narc: W1_H02W0301 F1\nword: SLICEA.K0.INIT 0000110000000000\nword: SLICEA.K1.INIT 1100110011111100\nword: SLICEB.K0.INIT 1111111100100000\nword: SLICEB.K1.INIT 0000010000001111\nword: SLICED.K0.INIT 0000000000001111\nword: SLICED.K1.INIT 0010000000000000\nword: SLICEC.K0.INIT 1100100011011000\nword: SLICEC.K1.INIT 1111110000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R21C27:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 N1_V01S0100\narc: H00L0000 H02E0201\narc: H00L0100 N1_V02S0101\narc: H00R0000 H02W0401\narc: H00R0100 H02E0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 V02S0401\narc: W1_H02W0101 V06N0103\narc: W1_H02W0401 H01E0001\narc: W1_H02W0701 V02N0701\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A1 E1_H01E0001\narc: B1 H00R0100\narc: B2 H02W0101\narc: B7 H02E0301\narc: C0 N1_V01N0001\narc: C1 H02E0401\narc: C2 V02S0601\narc: C7 V00T0000\narc: CE2 H00L0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 V02S0201\narc: D2 H00R0000\narc: D3 H02W0201\narc: D7 V02N0601\narc: E1_H01E0001 Q1\narc: E1_H01E0101 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q0\narc: M2 V00B0100\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: V01S0000 Q4\narc: V01S0100 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110000001100\nword: SLICEA.K0.INIT 1111111111110000\nword: SLICEA.K1.INIT 1111110011111110\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R21C28:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0601 V02S0601\narc: H00L0000 E1_H02W0201\narc: H00L0100 H02W0101\narc: H00R0000 W1_H02E0601\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 V01N0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 N1_V01S0000\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0401\narc: V00B0100 H02E0501\narc: V00T0000 H02W0001\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 H01E0101\narc: H01W0000 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: A4 E1_H01W0000\narc: A5 V02N0301\narc: A6 N1_V01N0101\narc: B4 H00L0000\narc: B5 N1_V02S0701\narc: B6 H02E0301\narc: B7 H02E0101\narc: C4 V00T0100\narc: C5 V00T0000\narc: C6 N1_V02S0001\narc: C7 H02E0401\narc: CE0 H00R0000\narc: CE1 S1_V02N0201\narc: CLK0 G_HPBX0000\narc: D4 V02N0601\narc: D5 S1_V02N0401\narc: D6 H00L0100\narc: D7 H02E0201\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q7\narc: E1_H02E0501 Q7\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q7\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q7\narc: M0 V00B0000\narc: M2 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q7\narc: N1_V02N0701 Q7\narc: N3_V06N0203 F7\narc: S1_V02S0701 F7\narc: V01S0000 F4\narc: V01S0100 Q0\narc: W1_H02W0001 Q2\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 1010101010001010\nword: SLICED.K0.INIT 0001001101011111\nword: SLICED.K1.INIT 0000000000000011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R21C29:PLC2\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0003 H01E0001\narc: H00R0000 H02W0601\narc: H00R0100 S1_V02N0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0501 S1_V02N0501\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 H01E0101\narc: V00B0000 V02N0201\narc: V00B0100 H02W0701\narc: V00T0100 V02N0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V06N0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E3_H06W0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A1 E1_H01E0001\narc: B1 V02N0101\narc: B2 H01W0100\narc: B4 H02W0301\narc: B6 V01S0000\narc: C1 H00R0100\narc: C2 E1_H02W0601\narc: C4 V00B0100\narc: C6 E1_H02W0601\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 H00R0000\narc: D3 E1_H02W0201\narc: D4 H02E0201\narc: D5 V02N0401\narc: D6 H02E0201\narc: D7 E1_H02W0201\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q4\narc: E1_H02E0301 F1\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q2\narc: M2 H02E0601\narc: M4 V00B0000\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V02N0401 Q6\narc: V01S0000 Q6\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R21C2:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: H00R0000 V02N0401\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 V02N0201\narc: CE2 V02S0601\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 H02E0201\narc: D2 N1_V01S0000\narc: D3 V01S0100\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q4\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M4 H02E0401\narc: M6 H02E0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R21C30:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 V02S0701\narc: E3_H06E0003 V06N0003\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 V06S0203\narc: H00L0100 V02N0301\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0401\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S1_V02N0101\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0501 W1_H02E0501\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H06E0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02W0501\narc: V00T0000 V02S0601\narc: V00T0100 H02W0301\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02N0701\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0001 W3_H06E0003\narc: W3_H06W0303 E1_H02W0501\narc: W3_H06W0103 E3_H06W0103\narc: B0 H02W0101\narc: B2 V02N0101\narc: B6 V02S0501\narc: C0 H02E0601\narc: C1 H02W0401\narc: C2 V02N0601\narc: C6 E1_H02W0401\narc: CE0 S1_V02N0201\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 V00B0100\narc: D2 V02N0001\narc: D3 H02W0001\narc: D6 V02N0401\narc: D7 H02W0001\narc: E1_H01E0001 F0\narc: E1_H01E0101 Q2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F0\narc: M0 V00B0000\narc: M2 V00T0100\narc: M4 H02E0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F0\narc: N1_V01N0101 Q6\narc: S1_V02S0001 F0\narc: S1_V02S0601 Q4\narc: S3_V06S0003 F0\narc: V01S0000 Q0\narc: V01S0100 Q2\narc: W1_H02W0201 Q2\narc: W3_H06W0003 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000110011001100\nword: SLICEA.K1.INIT 0000111111111111\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R21C31:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0303 W1_H02E0601\narc: H00L0100 S1_V02N0101\narc: H00R0000 V02S0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 E3_H06W0303\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02N0001\narc: V00B0100 H02E0501\narc: V00T0000 V02S0401\narc: V00T0100 H02W0301\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V06N0003\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E1_H01W0000\narc: H01W0000 W3_H06E0103\narc: W3_H06W0003 N1_V01S0000\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A4 H02E0701\narc: A7 H00L0000\narc: B4 V02S0701\narc: B7 H01E0101\narc: C4 V00T0100\narc: C5 H02E0601\narc: C7 V00B0100\narc: CE0 H00R0000\narc: CE1 H02E0101\narc: CLK0 G_HPBX0000\narc: D4 H00R0100\narc: D5 H02E0201\narc: D7 H00L0100\narc: E1_H01E0001 F4\narc: E1_H01E0101 Q2\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q0\narc: M0 E1_H02W0601\narc: M2 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F6\narc: N1_V01N0101 F5\narc: N3_V06N0103 Q2\narc: N3_V06N0303 F5\narc: V01S0100 Q2\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000010\nword: SLICEC.K1.INIT 0000000000001111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R21C32:PLC2\narc: E1_H02E0201 V01N0001\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 V02S0701\narc: H00L0000 V02S0201\narc: H00L0100 W1_H02E0301\narc: H00R0000 V02N0401\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 E1_H01W0000\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H06E0203\narc: V00B0000 V02N0201\narc: V00T0000 V02N0601\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 E1_H02W0401\narc: E1_H02E0401 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: B1 H02E0301\narc: B4 S1_V02N0701\narc: B5 V01S0000\narc: C1 H00L0100\narc: C4 V00T0100\narc: C5 N1_V02S0001\narc: CE0 H00R0000\narc: CE1 W1_H02E0101\narc: CE2 H00L0000\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: D4 H02W0001\narc: D5 V02S0401\narc: E1_H02E0001 Q2\narc: E1_H02E0301 Q1\narc: E3_H06E0103 Q2\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q6\narc: M2 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: N1_V02N0201 Q2\narc: N3_V06N0103 Q1\narc: S3_V06S0303 F5\narc: V01S0000 Q4\narc: V01S0100 Q1\narc: W1_H02W0501 F5\narc: W3_H06W0103 Q1\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1111001111111111\nword: SLICEC.K1.INIT 1100000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R21C33:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 V02N0601\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 H02E0201\narc: H00L0100 V02S0101\narc: H00R0000 V02N0401\narc: H00R0100 V02S0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 H02E0701\narc: V00T0000 W1_H02E0201\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 E1_H01W0000\narc: S1_V02S0401 W3_H06E0203\narc: W3_H06W0103 N3_V06S0103\narc: E3_H06E0003 W3_H06E0003\narc: B1 V02N0101\narc: B3 H02W0301\narc: B5 H00L0000\narc: B7 V00B0100\narc: C0 H00R0100\narc: C1 H00L0100\narc: C3 H02E0401\narc: C5 V00T0000\narc: C7 V02N0201\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H02W0001\narc: D3 V01S0100\narc: D5 H01W0000\narc: D7 H01W0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 F1\narc: E1_H02E0101 F1\narc: E1_H02E0501 Q7\narc: E3_H06E0303 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q5\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 F0\narc: N1_V02N0301 Q3\narc: S3_V06S0103 F1\narc: V01S0000 F1\narc: V01S0100 F1\narc: W3_H06W0003 Q3\narc: W3_H06W0203 Q7\narc: W3_H06W0303 Q5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0011000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R21C34:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0203 N1_V01S0000\narc: H00L0100 E1_H02W0301\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 N1_V01S0100\narc: N3_V06N0103 E1_H01W0100\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02N0401\narc: V00T0100 H02W0301\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 S3_V06N0203\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0701 W3_H06E0203\narc: N3_V06N0203 W3_H06E0203\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A1 H00L0000\narc: A5 N1_V01N0101\narc: B0 H02W0101\narc: B1 H02E0301\narc: B5 V01S0000\narc: B7 H02W0301\narc: C0 H02E0401\narc: C1 H00R0100\narc: C5 V00T0000\narc: C7 V02N0001\narc: CE0 V02N0201\narc: CE1 H00R0000\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H01E0101\narc: D1 N1_V01S0000\narc: D4 V02N0401\narc: D5 E1_H02W0001\narc: D7 V02S0401\narc: E1_H01E0101 F1\narc: E3_H06E0003 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0000 Q4\narc: M2 V00T0100\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q2\narc: N3_V06N0003 Q0\narc: V01S0000 F7\narc: W1_H02W0401 Q4\narc: W3_H06W0003 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1010110000000000\nword: SLICEC.K0.INIT 1111111100000000\nword: SLICEC.K1.INIT 1111110011111010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\n\n.tile R21C35:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0103 H01E0101\narc: H00R0000 W1_H02E0601\narc: H00R0100 H02W0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 E1_H02W0601\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 V02N0301\narc: E1_H02E0101 W3_H06E0103\narc: S1_V02S0301 W3_H06E0003\narc: S3_V06S0203 W3_H06E0203\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: A1 H00L0000\narc: A3 V02N0701\narc: B0 V02N0101\narc: B1 V00T0000\narc: B2 E1_H02W0301\narc: B3 H02E0301\narc: C0 H02E0601\narc: C1 H02W0401\narc: C2 H00R0100\narc: C3 H02W0401\narc: CE0 S1_V02N0201\narc: CE1 H00R0000\narc: CE2 V02S0601\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 V02S0201\narc: D2 V00T0100\narc: D3 V02S0201\narc: E1_H01E0001 F3\narc: E1_H01E0101 Q4\narc: E1_H02E0301 F1\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H00L0000 Q0\narc: H01W0100 Q6\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q6\narc: N3_V06N0003 Q0\narc: N3_V06N0303 Q6\narc: V01S0100 Q2\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1010110000000000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1010110000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R21C36:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 H01E0001\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0203 W1_H02E0401\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 S1_V02N0201\narc: H00L0100 W1_H02E0101\narc: H00R0000 V02S0401\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 V01N0101\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 V02N0001\narc: V00B0100 V02S0301\narc: V00T0000 S1_V02N0601\narc: V00T0100 V02N0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V06S0303\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0101 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: S1_V02S0401 W3_H06E0203\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 V06S0303\narc: A3 H02W0701\narc: B1 N1_V02S0301\narc: B3 V01N0001\narc: B5 V02S0501\narc: B6 H01E0101\narc: C1 H00L0100\narc: C3 V02N0601\narc: C5 V02S0001\narc: C6 E1_H01E0101\narc: CE1 S1_V02N0201\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 V00T0100\narc: D3 V02N0001\narc: D5 H01W0000\narc: D6 V00B0000\narc: D7 H02W0201\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: H01W0100 Q5\narc: M2 V00T0000\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: W3_H06W0103 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0011001100001111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100000011001111\nword: SLICED.K0.INIT 1111000000110011\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111110011101110\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R21C37:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V02S0701\narc: E3_H06E0203 N1_V01S0000\narc: H00L0100 W1_H02E0101\narc: H00R0000 W1_H02E0601\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H06W0003\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02W0401\narc: V00B0100 H02E0701\narc: V00T0000 N1_V02S0601\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V06N0303\narc: W1_H02W0701 V01N0101\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0203\narc: A3 V02S0701\narc: B3 S1_V02N0301\narc: C3 H00L0100\narc: CE0 E1_H02W0101\narc: CE2 H00R0000\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: E1_H01E0001 Q6\narc: E1_H01E0101 F1\narc: E3_H06E0103 Q1\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q6\narc: H01W0100 Q1\narc: M0 V00B0000\narc: M1 H02W0001\narc: M2 V00B0000\narc: M4 W1_H02E0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q6\narc: S3_V06S0203 Q4\narc: V01S0000 Q4\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R21C38:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 V01N0001\narc: E3_H06E0303 H01E0101\narc: H00R0100 H02W0501\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 E1_H02W0501\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0301 H06E0003\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H06E0303\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H06E0203\narc: V00B0000 H02W0601\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02E0201\narc: V00T0100 V02N0701\narc: V01S0000 N3_V06S0103\narc: E1_H02E0001 W3_H06E0003\narc: W3_H06W0003 N1_V01S0000\narc: A2 H02E0501\narc: A5 V00B0000\narc: A6 N1_V02S0301\narc: B1 H00R0100\narc: B2 V02S0301\narc: B3 V02S0101\narc: B5 H02E0301\narc: B6 V02N0501\narc: C1 S1_V02N0401\narc: C2 W1_H02E0401\narc: C3 H00L0000\narc: C5 V00T0000\narc: C6 E1_H02W0401\narc: D1 V02N0201\narc: D2 V00B0100\narc: D3 V01S0100\narc: D5 V02N0601\narc: D6 H00L0100\narc: E1_H01E0101 F3\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 F2\narc: H00L0100 F1\narc: H01W0000 F3\narc: M4 V00T0100\narc: M6 V00B0100\narc: N1_V01N0001 F4\narc: N3_V06N0003 F3\narc: V01S0100 F1\narc: W1_H02W0001 F2\narc: W1_H02W0401 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000110000111111\nword: SLICEB.K0.INIT 1010110000000000\nword: SLICEB.K1.INIT 1111000011110011\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0110101110110000\nword: SLICED.K0.INIT 1111101011111110\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R21C39:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 V01N0001\narc: E1_H02E0401 V01N0001\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 H02E0001\narc: H00L0100 H02W0301\narc: H00R0100 V02S0701\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 H01E0101\narc: V00B0000 W1_H02E0601\narc: V00B0100 H02E0501\narc: V00T0000 N1_V02S0601\narc: V00T0100 H02E0301\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V01N0101\narc: H01W0100 W3_H06E0303\narc: N3_V06N0203 W3_H06E0203\narc: S3_V06S0003 W3_H06E0003\narc: A3 W1_H02E0701\narc: A4 S1_V02N0301\narc: A6 H02W0701\narc: B3 V02S0101\narc: B4 V02N0501\narc: B6 V02S0501\narc: C3 H00L0000\narc: C4 V02S0001\narc: C6 V00T0100\narc: CE0 W1_H02E0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D3 H02W0001\narc: D4 H00L0100\narc: D6 V02N0401\narc: E1_H01E0001 F6\narc: E3_H06E0103 F1\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H00R0100\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 F4\narc: N3_V06N0303 Q6\narc: V01S0000 Q1\narc: V01S0100 Q1\narc: W3_H06W0103 Q1\nword: SLICEC.K0.INIT 1111101011111110\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111111111111111\nword: SLICED.K0.INIT 0100110011001100\nword: SLICED.K1.INIT 1111111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R21C3:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 V02N0001\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V02N0601\narc: H00L0100 S1_V02N0101\narc: H00R0000 V02N0401\narc: V00B0000 S1_V02N0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 E1_H02W0001\narc: C3 H00L0100\narc: C7 S1_V02N0201\narc: D1 N1_V01S0000\narc: D2 V00B0100\narc: D3 N1_V01S0000\narc: D5 H02W0201\narc: D6 V00B0000\narc: D7 V00B0000\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H02E0001\narc: M2 V00T0000\narc: M3 H00R0000\narc: M4 V00T0000\narc: M5 H02E0001\narc: M6 V00T0000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000000011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R21C40:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V02S0301\narc: E1_H02E0601 V02N0601\narc: E3_H06E0003 H01E0001\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 E1_H02W0201\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0701 H06W0203\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 E1_H01W0100\narc: V00B0100 H02W0501\narc: V00T0000 H02W0201\narc: V00T0100 V02S0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0701 V02S0701\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0701 W3_H06E0203\narc: N3_V06N0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: A4 V00T0100\narc: A6 V02S0301\narc: B0 W1_H02E0101\narc: B1 S1_V02N0301\narc: B2 H00R0100\narc: B3 S1_V02N0301\narc: B4 H02W0301\narc: B6 V02N0501\narc: C0 H02E0601\narc: C1 H00L0000\narc: C2 E1_H01W0000\narc: C3 W1_H02E0601\narc: C4 F6\narc: C6 N1_V02S0001\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 V02N0001\narc: D2 V01S0100\narc: D3 V00B0100\narc: D4 W1_H02E0201\narc: D6 H00L0100\narc: E1_H01E0001 F2\narc: E1_H01E0101 F0\narc: E3_H06E0203 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 F3\narc: H01W0000 F1\narc: H01W0100 F2\narc: M4 V00T0000\narc: M6 E1_H02W0401\narc: MUXCLK2 CLK0\narc: N3_V06N0203 Q4\narc: V01S0000 F4\narc: V01S0100 F3\narc: W1_H02W0301 F1\narc: W3_H06W0003 F0\narc: W3_H06W0103 F2\nword: SLICEA.K0.INIT 1111000011110011\nword: SLICEA.K1.INIT 0000110000111111\nword: SLICEB.K0.INIT 1111000011110011\nword: SLICEB.K1.INIT 0000110000111111\nword: SLICED.K0.INIT 1111101011111110\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0111000011110000\nword: SLICEC.K1.INIT 1111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R21C41:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 V06S0203\narc: E3_H06E0103 N3_V06S0103\narc: H00L0000 H02W0001\narc: H00L0100 V02S0101\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0203 H01E0001\narc: N3_V06N0303 H01E0101\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 H01E0001\narc: V00B0000 H02W0401\narc: V00B0100 V02N0101\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02E0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0501 V06N0303\narc: W1_H02W0601 N1_V01S0000\narc: H01W0000 W3_H06E0103\narc: S3_V06S0303 W3_H06E0303\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A7 V02S0301\narc: B0 V02S0101\narc: B1 S1_V02N0101\narc: B2 H02E0301\narc: B5 V02N0701\narc: B7 S1_V02N0701\narc: C0 H00L0000\narc: C1 H00L0100\narc: C2 V02N0601\narc: C4 E1_H01E0101\narc: C5 H02E0601\narc: C6 V02S0001\narc: C7 V00T0000\narc: CE1 W1_H02E0101\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H02W0001\narc: D2 V02N0201\narc: D3 V00T0100\narc: D4 V02N0401\narc: D5 V02S0601\narc: D6 S1_V02N0401\narc: D7 S1_V02N0401\narc: E1_H01E0001 F0\narc: E1_H01E0101 Q5\narc: E1_H02E0201 F2\narc: E3_H06E0203 F4\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F0\narc: M0 H02W0601\narc: M2 V00B0000\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F6\narc: N1_V01N0101 Q2\narc: N3_V06N0103 Q2\narc: W3_H06W0003 F0\narc: W3_H06W0103 Q2\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 1111110000110000\nword: SLICEA.K0.INIT 1111001111110000\nword: SLICEA.K1.INIT 1111111100001100\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 1010100000000000\nword: SLICEB.K0.INIT 0000001111001111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R21C42:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V06S0203\narc: E3_H06E0003 S3_V06N0003\narc: H00L0000 H02E0001\narc: H00L0100 V02S0101\narc: H00R0000 V02S0401\narc: H00R0100 H02E0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 H01E0001\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 H02E0501\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0303 H01E0101\narc: V00B0000 H02E0401\narc: V00B0100 H02E0701\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 H01E0101\narc: S1_V02S0001 W3_H06E0003\narc: S1_V02S0201 W3_H06E0103\narc: S1_V02S0701 W3_H06E0203\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: A1 H00L0000\narc: B1 V02S0301\narc: B3 H00R0100\narc: B4 V02S0701\narc: B7 V02N0701\narc: C0 V02S0601\narc: C1 H02W0401\narc: C3 H00L0100\narc: C4 N1_V02S0001\narc: C6 H02E0601\narc: C7 N1_V02S0201\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0201\narc: D1 W1_H02E0201\narc: D3 H02E0201\narc: D4 N1_V02S0401\narc: D5 W1_H02E0001\narc: D6 V00B0000\narc: D7 H02E0201\narc: E1_H01E0001 F6\narc: E3_H06E0203 Q4\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: M0 H02W0601\narc: M4 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F0\narc: N1_V02N0301 Q3\narc: S3_V06S0203 Q7\narc: V01S0000 Q4\narc: V01S0100 Q3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111110000110000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1111110000110000\nword: SLICEC.K0.INIT 1100000011110011\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111111100001111\nword: SLICEA.K1.INIT 1010100000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\n\n.tile R21C43:PLC2\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 V02N0601\narc: E3_H06E0003 H01E0001\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 N1_V02S0001\narc: H00L0100 E1_H02W0101\narc: H00R0000 H02E0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 W1_H02E0401\narc: V00T0000 H02E0201\narc: V00T0100 E1_H02W0301\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V02S0701\narc: E1_H01E0101 W3_H06E0203\narc: S1_V02S0401 W3_H06E0203\narc: S1_V02S0601 W3_H06E0303\narc: S3_V06S0303 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0103 E3_H06W0003\narc: A0 V02N0501\narc: A1 V02N0501\narc: A2 V02N0501\narc: A3 V02N0501\narc: A4 V00T0100\narc: A5 H02E0701\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 H00L0000\narc: B5 N1_V02S0501\narc: B7 V02N0701\narc: C0 H02W0601\narc: C1 H02W0601\narc: C2 H02W0601\narc: C3 H02W0601\narc: C4 E1_H02W0401\narc: C5 V02S0001\narc: C6 V00B0100\narc: C7 V02S0201\narc: CE3 H00R0000\narc: CLK1 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 E1_H02W0001\narc: D2 E1_H02W0001\narc: D3 E1_H02W0001\narc: D4 E1_H02W0201\narc: D5 N1_V02S0401\narc: D6 V00B0000\narc: D7 H00L0100\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q3\narc: LSR1 V00T0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXCLK3 CLK1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q1\narc: N1_V02N0001 Q0\narc: V00B0100 Q7\narc: V01S0100 Q7\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1111110000110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R21C44:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 H01E0101\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0203 N3_V06S0203\narc: H00L0000 E1_H02W0201\narc: H00L0100 V02N0301\narc: H00R0000 H02E0601\narc: H00R0100 H02W0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 N3_V06S0003\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 H06E0303\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 V06N0103\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 E3_H06W0203\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: B1 E1_H02W0301\narc: B2 E1_H01W0100\narc: B6 V01S0000\narc: C1 H00L0000\narc: C2 E1_H02W0601\narc: C6 V00T0000\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 V02N0201\narc: D6 H00L0100\narc: D7 V02S0601\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q4\narc: M2 V00T0100\narc: M4 V00B0100\narc: M6 H02E0401\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F6\narc: V01S0000 F2\narc: V01S0100 Q4\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0011001100001111\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 0000001111110011\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R21C45:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 V02N0501\narc: E3_H06E0003 V06S0003\narc: H00L0000 V02N0001\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 H02E0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 H02E0401\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02W0501\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02W0101\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 V02S0501\narc: E1_H02E0601 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 E1_H02W0001\narc: A0 V02N0501\narc: A1 V02N0501\narc: A2 V02N0501\narc: A3 V02N0501\narc: A4 N1_V02S0301\narc: A5 V00T0100\narc: B0 V02N0101\narc: B1 V02N0101\narc: B2 V02N0301\narc: B3 V02N0301\narc: B4 V00B0100\narc: B5 H00L0000\narc: B7 H02E0101\narc: C0 H02W0401\narc: C1 H02W0401\narc: C2 H02W0401\narc: C3 H02W0401\narc: C4 V00T0000\narc: C5 V02N0201\narc: C7 V02S0001\narc: CLK1 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 S1_V02N0201\narc: D2 S1_V02N0201\narc: D3 S1_V02N0201\narc: D4 V00B0000\narc: D5 H00R0100\narc: D7 S1_V02N0401\narc: E1_H01E0001 Q1\narc: E1_H01E0101 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q3\narc: H01W0100 Q0\narc: LSR1 E1_H02W0301\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0101 F7\narc: N3_V06N0203 F7\narc: S1_V02S0701 F7\narc: V01S0100 F7\narc: W1_H02W0701 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R21C46:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 V02N0701\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0303 N3_V06S0303\narc: H00L0100 V02N0101\narc: H00R0000 V02N0401\narc: H00R0100 H02W0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 H02E0301\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 W1_H02E0701\narc: V00T0000 W1_H02E0001\narc: V00T0100 N1_V02S0701\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 S3_V06N0203\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: S1_V02S0001 W3_H06E0003\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: A0 H02E0501\narc: A1 H02E0501\narc: A2 H02E0501\narc: A3 H02E0501\narc: A4 N1_V02S0301\narc: A5 E1_H02W0501\narc: B0 H02E0101\narc: B1 H02E0101\narc: B2 H02E0101\narc: B3 H02E0101\narc: B4 S1_V02N0501\narc: B5 H00R0000\narc: B6 V02S0701\narc: C0 S1_V02N0401\narc: C1 S1_V02N0401\narc: C2 S1_V02N0401\narc: C3 S1_V02N0401\narc: C4 V00T0100\narc: C5 V02N0001\narc: C6 V00T0000\narc: CLK1 G_HPBX0000\narc: D0 H02E0201\narc: D1 H02E0201\narc: D2 H02E0201\narc: D3 H02E0201\narc: D4 V00B0000\narc: D5 H00R0100\narc: D6 V02N0601\narc: D7 H00L0100\narc: E1_H02E0101 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: LSR1 W1_H02E0301\narc: M6 V00B0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q3\narc: N1_V02N0401 F6\narc: W1_H02W0201 Q2\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R21C47:PLC2\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0303 H01E0101\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02N0501\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 H02E0501\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 N1_V02S0201\narc: V00T0000 N1_V02S0601\narc: V00T0100 S1_V02N0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 N1_V01S0100\narc: N1_V02N0101 W3_H06E0103\narc: S1_V02S0101 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: S3_V06S0103 W3_H06E0103\narc: S3_V06S0303 W3_H06E0303\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0003 E1_H02W0001\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: A1 V02S0501\narc: A7 E1_H02W0701\narc: B1 V00B0000\narc: B3 H02E0301\narc: B4 H02E0101\narc: B7 H02W0301\narc: C1 H00R0100\narc: C2 V02N0401\narc: C3 H02E0401\narc: C4 H02E0601\narc: C6 V02S0201\narc: C7 V02S0201\narc: CE0 S1_V02N0201\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 W1_H02E0001\narc: D2 S1_V02N0001\narc: D3 H02E0201\narc: D4 H02E0001\narc: D5 H01W0000\narc: D6 S1_V02N0401\narc: D7 S1_V02N0401\narc: E1_H01E0001 F0\narc: E1_H01E0101 F0\narc: E3_H06E0103 F2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q3\narc: M0 V00T0000\narc: M4 V00T0100\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F6\narc: N1_V01N0101 F4\narc: N1_V02N0001 Q0\narc: S3_V06S0003 Q3\narc: V01S0000 Q3\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1111110000110000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111111110111000\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 1110000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R21C48:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 V02S0201\narc: E1_H02E0701 S1_V02N0701\narc: H00R0000 H02E0601\narc: H00R0100 H02W0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 N1_V02S0101\narc: V00T0000 S1_V02N0601\narc: W1_H02W0001 H01E0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 E1_H02W0701\narc: N1_V02N0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: A0 W1_H02E0701\narc: A2 V00T0000\narc: B2 H02W0301\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 N1_V02S0701\narc: B6 H02W0101\narc: B7 V02S0501\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V02N0501 Q7\narc: W3_H06W0003 Q3\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R21C49:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0003 V06N0003\narc: H00L0000 V02S0001\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 H02W0401\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0601\narc: V00T0000 H02E0201\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 E1_H02W0601\narc: E1_H02E0001 W3_H06E0003\narc: S1_V02S0701 W3_H06E0203\narc: W3_H06W0003 E1_H02W0001\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: B0 V02S0101\narc: B1 V00B0000\narc: B2 V02S0301\narc: B3 H00R0100\narc: B4 H00L0000\narc: B5 H00R0000\narc: B6 V00T0000\narc: B7 V02S0501\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0001 Q2\narc: S1_V02S0301 Q1\narc: S1_V02S0501 Q7\narc: S1_V02S0601 Q4\narc: V01S0000 Q6\narc: V01S0100 Q3\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R21C4:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: H00L0100 V02N0301\narc: H00R0100 N1_V02S0501\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0401 V01N0001\narc: S3_V06S0003 N3_V06S0303\narc: V00B0000 V02N0001\narc: V00B0100 H02W0701\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 E1_H02W0701\narc: A1 H02E0501\narc: A2 H02E0501\narc: B1 S1_V02N0301\narc: B2 S1_V02N0301\narc: C1 S1_V02N0601\narc: C2 S1_V02N0401\narc: D1 V00B0100\narc: D2 V00B0100\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0000\narc: M1 H00R0100\narc: M2 V00B0000\narc: M3 H00L0100\narc: M4 V00B0000\narc: M5 H00R0100\narc: M6 V00B0000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000100001\nword: SLICEB.K0.INIT 0000000000100001\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R21C50:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 E3_H06W0203\narc: H00L0000 E1_H02W0201\narc: H00R0100 H02W0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00B0100 E1_H02W0501\narc: V00T0000 E1_H02W0001\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 V02S0601\narc: E1_H01E0101 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: N1_V02N0101 W3_H06E0103\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0103 W3_H06E0003\narc: B0 V00T0000\narc: B1 H00R0100\narc: B2 E1_H02W0101\narc: B3 H02W0301\narc: B4 V00B0100\narc: B5 H00L0000\narc: B6 V00B0000\narc: B7 H02E0101\narc: CE0 W1_H02E0101\narc: CE1 W1_H02E0101\narc: CE2 W1_H02E0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: S1_V02S0201 Q0\narc: S3_V06S0103 Q1\narc: V01S0000 Q3\narc: W1_H02W0701 Q7\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R21C51:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 H01E0101\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0303 H01E0101\narc: H00L0000 E1_H02W0201\narc: H00R0000 V02S0401\narc: H00R0100 H02E0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02S0701\narc: E3_H06E0103 W3_H06E0003\narc: B0 W1_H02E0301\narc: B1 H00R0100\narc: B2 H02E0301\narc: B3 H00R0000\narc: B4 H02W0301\narc: B5 V00B0100\narc: B6 V00B0000\narc: B7 H02E0101\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0003 Q3\narc: S3_V06S0103 Q2\narc: V01S0100 Q5\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q1\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R21C52:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 E1_H01W0100\narc: H00R0100 H02E0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0201\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0501 E1_H02W0501\narc: N3_V06N0203 W3_H06E0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: B0 V00B0000\narc: B1 V02S0101\narc: B4 V01S0000\narc: B5 H00R0000\narc: B6 V00B0100\narc: B7 H02W0101\narc: C4 S1_V02N0001\narc: C5 V01N0101\narc: C6 V02N0001\narc: C7 H02W0601\narc: CE0 E1_H02W0101\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D4 V02S0601\narc: D5 V02S0601\narc: D6 V02S0601\narc: D7 V02S0601\narc: E1_H01E0101 Q7\narc: E1_H02E0401 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q6\narc: H01W0100 Q6\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q5\narc: V00B0100 Q7\narc: V01S0000 Q5\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q1\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111000011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R21C53:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0501 V02S0501\narc: E1_H02E0701 N1_V02S0701\narc: H00L0100 N1_V02S0301\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02S0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0601 V02N0601\narc: S1_V02S0001 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: A1 H00L0000\narc: A3 V02S0701\narc: A5 V02N0301\narc: A7 H02E0701\narc: B0 V02S0301\narc: B1 V00T0000\narc: B2 V02N0301\narc: B3 H02E0301\narc: B4 H00R0000\narc: B5 W1_H02E0101\narc: B6 V01S0000\narc: B7 H01E0101\narc: C0 H02E0601\narc: C1 H00R0100\narc: C2 H00L0100\narc: C3 H00R0100\narc: C4 N1_V02S0201\narc: C5 W1_H02E0601\narc: C6 V00B0100\narc: C7 W1_H02E0401\narc: CE0 E1_H02W0101\narc: CE1 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 V00T0100\narc: D2 E1_H02W0001\narc: D3 V00T0100\narc: D4 E1_H02W0001\narc: D5 S1_V02N0601\narc: D6 E1_H02W0001\narc: D7 S1_V02N0601\narc: E1_H01E0001 F5\narc: E1_H01E0101 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00R0000 Q6\narc: H01W0000 F1\narc: H01W0100 Q6\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q2\narc: V01S0000 Q0\narc: V01S0100 Q4\narc: W1_H02W0301 F3\narc: W1_H02W0501 F7\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0101001110101100\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0101001110101100\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0101001110101100\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 0101001110101100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R21C54:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 V02S0401\narc: H00L0000 E1_H02W0201\narc: H00L0100 E1_H02W0301\narc: H00R0000 W1_H02E0401\narc: H00R0100 V02S0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 H02E0701\narc: V00T0000 E1_H02W0001\narc: V00T0100 S1_V02N0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 H01E0001\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A3 V02S0501\narc: A5 V00B0000\narc: A7 V02N0301\narc: B2 H00R0100\narc: B3 V01N0001\narc: B4 H01E0101\narc: B5 H00R0000\narc: B6 V00B0000\narc: B7 V02N0501\narc: C0 E1_H02W0401\narc: C1 H00L0100\narc: C2 N1_V02S0601\narc: C3 H00L0000\narc: C4 N1_V02S0001\narc: C5 V00T0000\narc: C6 V00B0100\narc: C7 V00T0000\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 F0\narc: D2 H02W0001\narc: D3 V00T0100\narc: D4 H02W0001\narc: D5 S1_V02N0601\narc: D6 H02W0001\narc: D7 S1_V02N0601\narc: E1_H01E0001 F0\narc: E1_H01E0101 F0\narc: E3_H06E0003 F0\narc: E3_H06E0203 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q6\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q2\narc: N1_V02N0201 F0\narc: V00B0000 Q4\narc: V01S0100 Q6\narc: W1_H02W0101 F1\narc: W1_H02W0201 F0\narc: W1_H02W0301 F3\narc: W1_H02W0501 F5\narc: W1_H02W0701 F7\narc: W3_H06W0003 F0\narc: W3_H06W0103 F1\nword: SLICEA.K0.INIT 0000111100000000\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0101001110101100\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 0101001110101100\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0101001110101100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R21C55:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0401 H01E0001\narc: E1_H02E0601 H01E0001\narc: H00L0000 H02W0001\narc: H00L0100 E1_H02W0301\narc: H00R0000 H02W0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H01E0001\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0001 V01N0001\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02W0501\narc: V00T0100 H02W0101\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 E1_H01W0100\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0401 W3_H06E0203\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0203 E1_H01W0000\narc: A2 E1_H01E0001\narc: A4 N1_V01N0101\narc: B2 E1_H01W0100\narc: B3 V02N0301\narc: B4 H00L0000\narc: B5 V01S0000\narc: C2 V02S0601\narc: C3 S1_V02N0601\narc: C4 V00T0100\narc: C5 V02N0201\narc: CE0 H00L0100\narc: CE1 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 H00R0000\narc: D4 H00R0100\narc: D5 H02E0201\narc: E1_H01E0001 Q3\narc: E1_H01E0101 Q5\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F4\narc: H01W0100 Q6\narc: M0 E1_H02W0601\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q5\narc: V01S0000 Q3\narc: V01S0100 Q0\narc: W3_H06W0103 F2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0001110111100010\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 0001110111100010\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R21C56:PLC2\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0501 V02S0501\narc: H00L0100 H02W0301\narc: H00R0000 W1_H02E0401\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0601 H02E0601\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00T0000 H02E0201\narc: V00T0100 H02E0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V02S0601\narc: N1_V02N0101 W3_H06E0103\narc: W3_H06W0203 N1_V01S0000\narc: B4 V02S0701\narc: B5 V00B0100\narc: B7 H01E0101\narc: C3 H02E0401\narc: C4 V02N0001\narc: C5 V02N0201\narc: C7 V00T0100\narc: CE0 H00L0100\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: D4 V00B0000\narc: D5 V02S0601\narc: D7 V02S0601\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F3\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 Q0\narc: M0 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q5\narc: N1_V02N0201 Q0\narc: N1_V02N0401 Q4\narc: N1_V02N0701 Q7\narc: V00B0100 Q7\narc: V01S0100 Q0\narc: W1_H02W0001 Q0\narc: W1_H02W0201 Q0\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R21C57:PLC2\narc: H00L0100 V02N0301\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 E1_H01W0100\narc: W1_H02W0101 H01E0101\narc: W1_H02W0601 N3_V06S0303\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0001 W3_H06E0003\narc: S1_V02S0001 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: H01W0000 Q6\narc: LSR0 H02E0501\narc: M6 H02W0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R21C58:PLC2\narc: N1_V02N0201 W1_H02E0201\narc: N3_V06N0103 S1_V02N0201\narc: S1_V02S0201 H01E0001\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 H01E0001\narc: S3_V06S0303 N3_V06S0203\narc: V01S0000 S3_V06N0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0401 V02N0401\narc: H01W0100 W3_H06E0303\narc: N1_V02N0401 W3_H06E0203\narc: S1_V02S0701 W3_H06E0203\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\n\n.tile R21C59:PLC2\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\n\n.tile R21C5:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 S1_V02N0401\narc: H00L0000 H02W0001\narc: H00L0100 V02N0101\narc: H00R0000 W1_H02E0601\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 H02W0601\narc: V00B0100 V02S0101\narc: V00T0000 H02W0001\narc: V00T0100 E1_H02W0101\narc: W1_H02W0001 S1_V02N0001\narc: A1 H02W0501\narc: A7 H00L0000\narc: B0 V02N0301\narc: B1 E1_H02W0301\narc: B5 H02E0101\narc: B6 V00T0000\narc: B7 V00B0000\narc: C0 V02N0601\narc: C1 E1_H02W0401\narc: C5 E1_H02W0401\narc: C6 H02W0601\narc: C7 E1_H02W0601\narc: CE0 V02N0201\narc: CE1 H02W0101\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 S1_V02N0201\narc: D5 H00L0100\narc: D6 V02N0401\narc: D7 V02N0401\narc: E1_H01E0001 F0\narc: E1_H02E0501 Q5\narc: E3_H06E0003 Q0\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: M2 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V02N0301 F1\narc: N1_V02N0401 F6\narc: W1_H02W0701 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000110011111100\nword: SLICED.K0.INIT 0000000011111100\nword: SLICED.K1.INIT 0000000000001110\nword: SLICEA.K0.INIT 0000111111001100\nword: SLICEA.K1.INIT 1100010000000100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R21C60:PLC2\narc: S3_V06S0103 H06E0103\narc: S3_V06S0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\n\n.tile R21C61:PLC2\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 H06E0303\n\n.tile R21C62:PLC2\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H06E0203\narc: V01S0100 N3_V06S0303\n\n.tile R21C63:PLC2\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\n\n.tile R21C64:PLC2\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0401 N3_V06S0203\narc: V01S0100 N3_V06S0303\narc: S3_V06S0303 W3_H06E0303\n\n.tile R21C65:PLC2\narc: S3_V06S0203 W3_H06E0203\n\n.tile R21C66:PLC2\narc: S3_V06S0103 H06E0103\narc: E3_H06E0003 W3_H06E0303\n\n.tile R21C67:PLC2\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0003\n\n.tile R21C69:PLC2\narc: N1_V02N0301 H06E0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\n\n.tile R21C6:PLC2\narc: H00L0000 N1_V02S0001\narc: H00L0100 N1_V02S0301\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 V01N0001\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 E1_H02W0201\narc: V00B0000 V02N0001\narc: V00B0100 E1_H02W0701\narc: V00T0000 V02N0401\narc: W1_H02W0001 V06N0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: A0 E1_H02W0501\narc: A1 E1_H02W0501\narc: A3 E1_H02W0501\narc: A5 E1_H02W0701\narc: B0 H01W0100\narc: B1 H01W0100\narc: B2 H00R0100\narc: B3 H01W0100\narc: B4 V00B0100\narc: B5 H02E0301\narc: C0 N1_V02S0401\narc: C1 N1_V02S0401\narc: C2 N1_V01N0001\narc: C3 N1_V02S0401\narc: C4 H02W0401\narc: C5 H02W0401\narc: C6 E1_H01E0101\narc: C7 V02N0201\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02N0001\narc: D2 V02N0001\narc: D3 V02N0001\narc: D4 H00L0100\narc: D5 H00L0100\narc: D6 V00B0000\narc: D7 V02N0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: E1_H02E0501 F5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F7\narc: M0 V00T0000\narc: M1 H00L0000\narc: M2 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q6\narc: S1_V02S0701 F7\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000110011111100\nword: SLICEC.K1.INIT 1100010000000100\nword: SLICED.K0.INIT 0000000000001111\nword: SLICED.K1.INIT 0000000000001111\nword: SLICEA.K0.INIT 0000010100000111\nword: SLICEA.K1.INIT 0000010100000111\nword: SLICEB.K0.INIT 0011001100111111\nword: SLICEB.K1.INIT 0000010100000111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R21C70:PLC2\narc: S3_V06S0103 N3_V06S0003\n\n.tile R21C7:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0401 V02N0401\narc: H00R0000 V02N0601\narc: H00R0100 H02E0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0401 S1_V02N0401\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 H01E0001\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 W1_H02E0401\narc: V00B0100 H02E0501\narc: V00T0100 V02S0501\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: A0 H00R0000\narc: A1 H00R0000\narc: A6 H00R0000\narc: A7 H00R0000\narc: B0 H00R0100\narc: B1 H00R0100\narc: B6 V00B0100\narc: B7 V00B0100\narc: C0 N1_V01S0100\narc: C1 N1_V01S0100\narc: C6 V00T0100\narc: C7 V00T0100\narc: D0 S1_V02N0001\narc: D1 S1_V02N0001\narc: D6 V01N0001\narc: D7 V01N0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0000\narc: M1 H02W0001\narc: M2 V00B0000\narc: M3 E1_H02W0201\narc: M4 W1_H02E0401\narc: M5 H02W0001\narc: M6 W1_H02E0401\narc: N1_V01N0101 F3\nword: SLICEA.K0.INIT 0000000000000001\nword: SLICEA.K1.INIT 0000000000000010\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000001\nword: SLICED.K1.INIT 0000000000000010\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R21C8:PLC2\narc: E1_H02E0401 N3_V06S0203\narc: H00L0100 V02N0301\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0501 E1_H02W0501\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H06W0103\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 E1_H01W0100\narc: V00T0100 V02N0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 V01N0001\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 E1_H02W0601\narc: H01W0000 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: B5 V02N0501\narc: B7 E1_H02W0301\narc: C5 H02E0401\narc: C7 H02E0401\narc: CE1 H00R0100\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D5 H00L0100\narc: D7 H01W0000\narc: E1_H01E0001 F7\narc: E3_H06E0103 Q2\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: M2 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0701 Q5\narc: S3_V06S0103 Q2\narc: V01S0000 Q7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000110011111100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000110011111100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R21C9:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0601 V01N0001\narc: E3_H06E0103 N1_V01S0100\narc: H00R0100 S1_V02N0501\narc: H01W0000 E3_H06W0103\narc: H01W0100 E3_H06W0303\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0601 E3_H06W0303\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0201\narc: V00B0100 V02S0301\narc: V00T0000 W1_H02E0001\narc: W1_H02W0201 H01E0001\narc: W3_H06W0203 E1_H02W0701\narc: CE0 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q6\narc: E1_H02E0201 Q0\narc: E1_H02E0401 Q4\narc: M0 V00B0000\narc: M2 E1_H02W0601\narc: M4 V00B0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0103 Q2\narc: S1_V02S0401 Q4\narc: V01S0000 Q6\narc: V01S0100 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R22C10:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0103 H01E0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H06W0203\narc: S1_V02S0301 H02W0301\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02W0401\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E3_H06W0003\narc: N1_V02N0101 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: A6 E1_H02W0501\narc: A7 E1_H02W0501\narc: B6 V02S0501\narc: B7 V02S0501\narc: C5 V00T0100\narc: C6 H01E0001\narc: C7 H01E0001\narc: CE0 H02E0101\narc: CLK0 G_HPBX0000\narc: D5 V02S0401\narc: D6 H00R0100\narc: D7 H00R0100\narc: E1_H01E0101 Q2\narc: E3_H06E0303 F6\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00R0100 F5\narc: H01W0000 Q0\narc: M0 V00T0000\narc: M2 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: V01S0000 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 0000000000100011\nword: SLICED.K1.INIT 0000000010001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R22C11:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 V06S0203\narc: H00L0000 N1_V02S0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 S1_V02N0601\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 V01N0101\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 H02W0401\narc: V00B0100 V02N0301\narc: V00T0000 H02W0001\narc: V00T0100 V02S0501\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V06N0303\narc: W1_H02W0701 E1_H02W0601\narc: W3_H06W0003 E3_H06W0003\narc: A0 H02E0701\narc: A1 H02E0701\narc: A3 H02E0501\narc: A4 V02S0101\narc: A6 N1_V01N0101\narc: A7 N1_V01S0100\narc: B0 V02N0301\narc: B1 V00B0000\narc: B2 H02E0301\narc: B3 H00L0000\narc: B4 N1_V02S0501\narc: B6 V01S0000\narc: B7 V00B0000\narc: C0 H02W0401\narc: C1 S1_V02N0401\narc: C2 W1_H02E0401\narc: C3 N1_V01N0001\narc: C4 H02W0601\narc: C6 E1_H01E0101\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V00B0100\narc: D2 V02S0001\narc: D3 V02N0201\narc: D4 V02S0601\narc: D6 H02E0201\narc: D7 H00L0100\narc: E1_H01E0001 F4\narc: E1_H01E0101 F3\narc: E1_H02E0201 F0\narc: E1_H02E0401 F6\narc: E3_H06E0003 F0\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: M4 V00T0000\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F2\narc: N1_V01N0101 F1\narc: S3_V06S0103 F2\narc: V01S0000 F7\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 1010110000000000\nword: SLICEA.K1.INIT 0100000001110000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1011010010000111\nword: SLICED.K0.INIT 0000000000010000\nword: SLICED.K1.INIT 0000101100001000\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R22C12:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 V01N0001\narc: E1_H02E0401 V02S0401\narc: E3_H06E0303 N1_V01S0100\narc: H00R0100 H02E0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H02W0701\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 H06E0303\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02N0101\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0701\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 N1_V01S0100\narc: W3_H06W0003 V06N0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A1 V02N0501\narc: A7 H02E0501\narc: B0 H00R0100\narc: B1 V00T0000\narc: B3 H00R0000\narc: B5 H02E0101\narc: B6 H02E0301\narc: B7 H02W0101\narc: C0 W1_H02E0401\narc: C1 H00L0000\narc: C2 H00L0100\narc: C3 V02S0401\narc: C4 V02S0001\narc: C5 V00T0000\narc: C6 V00T0100\narc: C7 E1_H01E0101\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 V02N0001\narc: D2 S1_V02N0201\narc: D3 V00B0100\narc: D4 S1_V02N0601\narc: D5 V02N0601\narc: D6 V00B0000\narc: D7 V02S0601\narc: E1_H01E0001 F3\narc: E1_H01E0101 F3\narc: E1_H02E0601 F4\narc: E3_H06E0103 F2\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H00L0100 F3\narc: H00R0000 Q6\narc: H01W0000 F6\narc: H01W0100 F6\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F7\narc: N1_V02N0301 F1\narc: S3_V06S0303 F6\narc: V01S0000 F0\narc: V01S0100 Q0\narc: W1_H02W0001 F0\narc: W1_H02W0601 F6\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1011010010000111\nword: SLICEB.K0.INIT 0000111100000000\nword: SLICEB.K1.INIT 0011000000111111\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000111100000000\nword: SLICEC.K1.INIT 0011000000111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R22C13:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 V01N0001\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 S1_V02N0201\narc: H00L0100 V02S0301\narc: H00R0000 H02E0401\narc: H00R0100 V02N0701\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 S1_V02N0501\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0303 E3_H06W0303\narc: V00T0000 V02S0401\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S3_V06N0303\narc: W3_H06W0203 N3_V06S0203\narc: W3_H06W0003 E3_H06W0303\narc: A1 E1_H01E0001\narc: A2 H00L0100\narc: A3 H00L0100\narc: A5 V00B0000\narc: A6 N1_V01N0101\narc: A7 V00T0100\narc: B0 H02W0301\narc: B1 V00T0000\narc: B2 H00L0000\narc: B3 H00R0000\narc: B4 H02E0101\narc: B5 H00R0000\narc: B6 V00T0000\narc: B7 V01S0000\narc: C0 V02N0401\narc: C1 N1_V01N0001\narc: C2 V02S0401\narc: C3 W1_H02E0601\narc: C4 H02W0401\narc: C5 F4\narc: C6 F4\narc: C7 W1_H02E0401\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 H02W0001\narc: D2 V02S0001\narc: D3 S1_V02N0201\narc: D4 H02E0001\narc: D5 S1_V02N0601\narc: D6 H00R0100\narc: D7 N1_V02S0401\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F2\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F1\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F0\narc: N1_V01N0101 Q4\narc: N1_V02N0601 F4\narc: N3_V06N0203 F7\narc: S3_V06S0203 F4\narc: V00B0000 Q4\narc: V00T0100 F3\narc: V01S0000 F6\narc: V01S0100 Q0\narc: W1_H02W0201 F0\narc: W1_H02W0701 F5\nword: SLICEB.K0.INIT 1010110000000000\nword: SLICEB.K1.INIT 0100000001110000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 0100101101111000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 0100000001110000\nword: SLICED.K0.INIT 0000101100001000\nword: SLICED.K1.INIT 0001000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R22C14:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 H01E0101\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 H02W0001\narc: H00L0100 S1_V02N0101\narc: H00R0000 V02S0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 H06W0303\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02N0101\narc: V00T0000 S1_V02N0401\narc: V00T0100 V02N0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V02N0601\narc: W3_H06W0203 S3_V06N0203\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 H00L0100\narc: A1 H00L0100\narc: A2 H00L0100\narc: A3 H00L0100\narc: A4 S1_V02N0101\narc: A5 E1_H02W0701\narc: A6 N1_V01S0100\narc: A7 N1_V01N0101\narc: B0 V02S0301\narc: B1 V02S0301\narc: B2 V02S0301\narc: B3 V02S0301\narc: B4 V02S0701\narc: B5 H02E0301\narc: B6 N1_V01S0000\narc: B7 H02W0301\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 V00B0100\narc: C5 N1_V02S0201\narc: C6 H02W0401\narc: C7 E1_H01E0101\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CLK1 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 E1_H02W0001\narc: D5 W1_H02E0201\narc: D6 V00B0000\narc: D7 E1_H02W0201\narc: E1_H01E0001 F7\narc: E1_H01E0101 F2\narc: E1_H02E0101 Q3\narc: E1_H02E0301 Q1\narc: E1_H02E0401 F6\narc: E3_H06E0103 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q0\narc: LSR0 V00T0000\narc: LSR1 V00T0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 Q3\narc: N1_V01N0101 Q2\narc: V01S0000 F3\narc: V01S0100 Q3\nword: SLICED.K0.INIT 1001000000000000\nword: SLICED.K1.INIT 1010010100100001\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R22C15:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 S3_V06N0003\narc: H00L0000 H02E0201\narc: H00R0100 H02W0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0401\narc: V00T0000 H02E0201\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0401 H01E0001\narc: A0 H00L0000\narc: A1 H00L0000\narc: A2 V00T0000\narc: A3 V00T0000\narc: A4 V02S0101\narc: A5 H02E0701\narc: A7 V02S0301\narc: B0 S1_V02N0301\narc: B1 S1_V02N0301\narc: B2 S1_V02N0301\narc: B3 S1_V02N0301\narc: B4 V02S0501\narc: B5 W1_H02E0101\narc: B7 V02S0701\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 E1_H02W0401\narc: C5 W1_H02E0601\narc: C7 S1_V02N0001\narc: CE0 V02S0201\narc: CE1 V02S0201\narc: CLK1 G_HPBX0000\narc: D0 V02S0001\narc: D1 V02S0001\narc: D2 V02S0001\narc: D3 V02S0001\narc: D4 H02W0001\narc: D5 V02N0401\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: E1_H01E0101 Q2\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q1\narc: H01W0100 Q3\narc: LSR0 H02W0301\narc: LSR1 H02E0501\narc: M6 V00T0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q3\narc: N3_V06N0303 F6\narc: S1_V02S0001 F0\narc: S1_V02S0201 F2\narc: S1_V02S0301 Q1\narc: V01S0000 Q0\narc: V01S0100 Q2\narc: W1_H02W0301 Q3\narc: W3_H06W0003 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0010111111111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R22C16:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0003 V01N0001\narc: E3_H06E0303 N1_V01S0100\narc: H00L0100 S1_V02N0101\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0203 N3_V06S0203\narc: V00B0100 V02N0301\narc: V00T0100 V02N0501\narc: W1_H02W0001 V02S0001\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 V02S0501\narc: W1_H02W0701 N1_V02S0701\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A0 H00L0100\narc: A1 H00L0100\narc: A2 H00L0100\narc: A3 H00L0100\narc: A4 S1_V02N0101\narc: A5 H02E0501\narc: A7 H00L0000\narc: B0 E1_H02W0301\narc: B1 E1_H02W0101\narc: B2 E1_H02W0301\narc: B3 E1_H02W0101\narc: B4 S1_V02N0501\narc: B5 V02N0701\narc: B7 H02W0301\narc: C0 N1_V01S0100\narc: C1 N1_V01S0100\narc: C2 N1_V01S0100\narc: C3 N1_V01S0100\narc: C4 V02N0001\narc: C5 W1_H02E0601\narc: C7 V00T0000\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK1 G_HPBX0000\narc: D0 V02S0201\narc: D1 V02S0201\narc: D2 V02S0201\narc: D3 V02S0201\narc: D4 H02W0201\narc: D5 V02N0401\narc: D7 E1_H02W0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q1\narc: E1_H02E0201 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 F7\narc: H01W0100 Q0\narc: LSR0 V00B0100\narc: LSR1 V00T0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q1\narc: N1_V02N0301 Q3\narc: S1_V02S0001 Q2\narc: S1_V02S0101 Q1\narc: S1_V02S0201 Q0\narc: S3_V06S0103 Q2\narc: V00T0000 F2\narc: V01S0000 Q3\narc: V01S0100 F3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010010100100001\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R22C17:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 V01N0001\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 S1_V02N0201\narc: H00L0100 H02E0101\narc: H00R0000 V02S0401\narc: H00R0100 H02W0701\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0001 V01N0001\narc: S1_V02S0201 V01N0001\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 N1_V01S0000\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02E0201\narc: V00T0100 N1_V02S0701\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 V06S0303\narc: E1_H02E0001 W3_H06E0003\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 V06S0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A0 H00L0100\narc: A1 H00L0100\narc: A2 H00L0100\narc: A3 H00L0100\narc: A4 V02N0101\narc: A5 H02E0701\narc: A6 W1_H02E0701\narc: A7 W1_H02E0701\narc: B0 V02S0301\narc: B1 V02S0301\narc: B2 H00R0000\narc: B3 H00R0000\narc: B4 H00L0000\narc: B5 W1_H02E0101\narc: B6 V00B0100\narc: B7 V00T0000\narc: C0 H02E0401\narc: C1 H02E0601\narc: C2 H02E0601\narc: C3 H02E0601\narc: C4 V01N0101\narc: C5 V00T0100\narc: C6 H02W0401\narc: C7 N1_V02S0001\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK1 G_HPBX0000\narc: D0 V02S0001\narc: D1 V02S0001\narc: D2 V02S0001\narc: D3 V02S0001\narc: D4 V01N0001\narc: D5 W1_H02E0001\narc: D6 V00B0000\narc: D7 W1_H02E0201\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F6\narc: E1_H02E0201 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q3\narc: LSR0 H02E0301\narc: LSR1 H02E0501\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F2\narc: N1_V01N0101 Q1\narc: N1_V02N0001 Q0\narc: N1_V02N0301 Q3\narc: S1_V02S0301 Q3\narc: V01S0000 F3\narc: V01S0100 Q2\nword: SLICED.K0.INIT 1010000011000000\nword: SLICED.K1.INIT 1001000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R22C18:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 V01N0101\narc: E1_H02E0701 S1_V02N0701\narc: H00R0000 N1_V02S0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 H06W0003\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 H01E0001\narc: S1_V02S0601 N1_V01S0000\narc: S3_V06S0203 H06W0203\narc: V00B0000 V02S0001\narc: V00B0100 H02E0501\narc: V00T0100 H02W0301\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 V02S0401\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0401 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A0 H01E0001\narc: A1 V01N0101\narc: A3 N1_V02S0501\narc: A4 V02N0301\narc: A5 V02S0101\narc: A7 N1_V01N0101\narc: B0 V00B0000\narc: B1 V02N0101\narc: B2 H00R0100\narc: B3 H00R0000\narc: B4 H02E0301\narc: B5 N1_V01S0000\narc: B7 H02E0101\narc: C0 V02N0601\narc: C1 V02N0601\narc: C2 E1_H02W0601\narc: C3 S1_V02N0401\narc: C4 V02N0001\narc: C5 V00T0000\narc: C7 E1_H01E0101\narc: D0 V02S0201\narc: D1 V00T0100\narc: D2 N1_V02S0001\narc: D3 V01S0100\narc: D4 V01N0001\narc: D5 H00L0100\narc: D7 W1_H02E0001\narc: E1_H01E0101 F5\narc: E3_H06E0103 F2\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 F3\narc: M6 V00B0100\narc: N1_V01N0101 F4\narc: N3_V06N0303 F6\narc: V00T0000 F0\narc: V01S0100 F1\nword: SLICEC.K0.INIT 1000101001000101\nword: SLICEC.K1.INIT 1101000000000000\nword: SLICEB.K0.INIT 0011111100000000\nword: SLICEB.K1.INIT 1001000000000000\nword: SLICEA.K0.INIT 1100010000110001\nword: SLICEA.K1.INIT 1100111101000101\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R22C19:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0203 N3_V06S0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 H02W0301\narc: H00R0000 V02N0601\narc: H00R0100 H02W0701\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02S0101\narc: V00T0100 S1_V02N0501\narc: W1_H02W0301 V02N0301\narc: W1_H02W0701 S1_V02N0701\narc: N3_V06N0103 W3_H06E0103\narc: S1_V02S0101 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0303 E3_H06W0203\narc: A0 S1_V02N0701\narc: A1 S1_V02N0701\narc: A2 S1_V02N0701\narc: A3 S1_V02N0701\narc: A4 H02E0701\narc: A5 S1_V02N0101\narc: A6 N1_V01N0101\narc: B0 V02N0101\narc: B1 V02N0101\narc: B2 V02N0101\narc: B3 V02N0101\narc: B4 V02S0701\narc: B5 V02N0701\narc: B6 V00T0000\narc: B7 V02N0501\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V02S0001\narc: C5 H02E0401\narc: C6 E1_H01E0101\narc: C7 V02N0001\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CLK1 G_HPBX0000\narc: D0 V00B0100\narc: D1 V00B0100\narc: D2 V00B0100\narc: D3 V00B0100\narc: D4 V02S0401\narc: D5 V02N0401\narc: D6 F2\narc: D7 H02W0201\narc: E1_H01E0001 F0\narc: E1_H01E0101 F1\narc: E1_H02E0001 Q2\narc: E1_H02E0401 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q0\narc: LSR0 V00T0100\narc: LSR1 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 Q3\narc: N1_V01N0101 Q1\narc: N1_V02N0101 Q3\narc: N3_V06N0003 Q0\narc: S1_V02S0001 Q2\narc: S1_V02S0201 Q0\narc: S1_V02S0301 Q3\narc: S3_V06S0103 Q1\narc: V00T0000 Q2\narc: V01S0000 F3\narc: V01S0100 Q2\nword: SLICED.K0.INIT 1000010000100001\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R22C20:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 V02N0201\narc: H00L0100 V02N0301\narc: H00R0100 N1_V02S0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 W1_H02E0401\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0701 E1_H02W0701\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02N0101\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02W0301\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0303 E1_H02W0501\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A0 H02E0701\narc: A1 H02E0701\narc: A2 H02E0701\narc: A3 H02E0701\narc: A4 H02E0701\narc: A5 H02W0701\narc: A6 V00T0100\narc: B0 S1_V02N0101\narc: B1 S1_V02N0101\narc: B2 S1_V02N0101\narc: B3 S1_V02N0101\narc: B4 N1_V02S0501\narc: B5 H00L0000\narc: B6 V02N0701\narc: B7 W1_H02E0101\narc: C0 N1_V01S0100\narc: C1 N1_V01S0100\narc: C2 N1_V01S0100\narc: C3 N1_V01S0100\narc: C4 V02S0001\narc: C5 V00T0000\narc: C6 V00B0100\narc: C7 H01E0001\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK1 G_HPBX0000\narc: D0 V02S0201\narc: D1 V02S0201\narc: D2 V02S0201\narc: D3 V02S0201\narc: D4 V02S0401\narc: D5 H00L0100\narc: D6 V01N0001\narc: D7 S1_V02N0401\narc: E1_H01E0101 Q1\narc: E1_H02E0001 Q0\narc: E1_H02E0401 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F2\narc: LSR0 H02E0501\narc: LSR1 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q3\narc: N1_V02N0201 Q2\narc: S1_V02S0101 Q3\narc: S3_V06S0103 Q2\narc: V01S0000 F3\narc: V01S0100 Q3\nword: SLICED.K0.INIT 1000010000100001\nword: SLICED.K1.INIT 1100001100000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R22C21:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0601 N1_V01S0000\narc: H00L0000 W1_H02E0001\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02E0401\narc: H00R0100 H02W0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 E3_H06W0103\narc: V00B0000 W1_H02E0401\narc: V00B0100 V02S0101\narc: V00T0000 H02W0001\narc: V00T0100 V02N0701\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A3 V00B0000\narc: A4 N1_V01N0101\narc: A5 H02E0501\narc: A7 H00L0000\narc: B3 H00R0000\narc: B4 S1_V02N0501\narc: B5 V02S0501\narc: B7 W1_H02E0301\narc: C3 W1_H02E0601\narc: C4 V00T0000\narc: C5 V00B0100\narc: C7 H02W0401\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 H02E0201\narc: D4 V02N0601\narc: D5 V02S0401\narc: D7 H00L0100\narc: E1_H01E0001 F4\narc: E1_H02E0701 F7\narc: E3_H06E0003 Q0\narc: E3_H06E0203 F4\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: M0 H02E0601\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q5\narc: N1_V02N0001 F2\narc: S3_V06S0003 Q0\narc: V01S0000 Q5\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010000011000000\nword: SLICEC.K0.INIT 1100110010000000\nword: SLICEC.K1.INIT 1110101011000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R22C22:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 V02N0401\narc: E3_H06E0003 H01E0001\narc: H00L0000 N1_V02S0001\narc: H00R0100 H02E0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 H06E0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 H02E0301\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0601\narc: V00B0100 V02N0301\narc: V00T0000 W1_H02E0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0701 E1_H02W0701\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A2 V00B0000\narc: A5 V00T0000\narc: A6 F5\narc: B2 H00R0100\narc: B3 H01W0100\narc: B5 V02S0501\narc: B6 V00B0000\narc: B7 V01S0000\narc: C2 H00L0000\narc: C3 V02S0601\narc: C5 V02S0201\narc: C6 V00B0100\narc: C7 H02W0601\narc: CLK0 G_HPBX0000\narc: D2 V02N0001\narc: D3 S1_V02N0001\narc: D5 H02E0201\narc: D6 N1_V02S0401\narc: D7 V02S0601\narc: E1_H01E0101 F3\narc: E3_H06E0203 F7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: V01S0000 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011111101011111\nword: SLICEB.K0.INIT 1010100010101010\nword: SLICEB.K1.INIT 1100111111000000\nword: SLICED.K0.INIT 0100110011001100\nword: SLICED.K1.INIT 1100110011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R22C23:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0103 H01E0101\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 V02N0101\narc: H00R0100 N1_V02S0701\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H02W0601\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00B0100 H02W0501\narc: V00T0100 H02E0301\narc: W1_H02W0601 N1_V02S0601\narc: N1_V02N0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: A2 V02N0701\narc: B2 V02N0301\narc: B4 H00R0000\narc: C2 H00L0100\narc: C4 E1_H02W0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D4 H02E0201\narc: D5 E1_H02W0001\narc: E1_H01E0101 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: M0 V00T0100\narc: M1 H00R0100\narc: M2 V00T0100\narc: M4 V00B0000\narc: M6 H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0101 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0011011100111111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R22C24:PLC2\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 S3_V06N0303\narc: E3_H06E0003 V01N0001\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 H02W0201\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 V01N0001\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 W1_H02E0401\narc: V00B0100 S1_V02N0301\narc: V00T0000 S1_V02N0401\narc: V00T0100 H02W0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 V02S0101\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V01N0001\narc: N1_V02N0401 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0303 E1_H02W0501\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: A5 V02S0301\narc: A6 H02E0501\narc: A7 H00L0000\narc: B4 V02S0701\narc: B5 H00R0000\narc: B6 H01E0101\narc: B7 W1_H02E0101\narc: C4 V00B0100\narc: C5 W1_H02E0401\narc: C6 V00T0000\narc: C7 H02W0401\narc: CE0 H02E0101\narc: CE1 S1_V02N0201\narc: CLK0 G_HPBX0000\narc: D4 V01N0001\narc: D5 N1_V02S0601\narc: D6 H02W0201\narc: D7 V02N0601\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q0\narc: E1_H02E0001 Q2\narc: E1_H02E0701 Q5\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H01W0100 Q7\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00B0000\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q7\narc: N1_V01N0101 Q5\narc: N1_V02N0501 Q7\narc: S1_V02S0501 Q5\narc: V01S0000 F6\narc: W1_H02W0001 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111000011101110\nword: SLICED.K0.INIT 0001010100111111\nword: SLICED.K1.INIT 1111100011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R22C25:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 E1_H01W0100\narc: H00R0000 S1_V02N0401\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02S0101\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 V02N0601\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: CE0 H00R0000\narc: CE1 H02W0101\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q4\narc: H01W0000 Q2\narc: LSR1 H02E0301\narc: M0 V00B0100\narc: M2 V00B0100\narc: M4 V00B0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q6\narc: N1_V02N0001 Q0\narc: V01S0000 Q4\narc: V01S0100 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R22C26:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V02N0701\narc: E3_H06E0303 V06N0303\narc: H00L0100 H02W0101\narc: H00R0100 H02W0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H06W0103\narc: V00B0000 H02W0401\narc: V00B0100 H02E0701\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02N0501\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 S1_V02N0701\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0303 E1_H02W0601\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0203\narc: A1 H02W0701\narc: A2 V02S0701\narc: A5 V00B0000\narc: A6 V02S0301\narc: B0 H00R0100\narc: B1 V00T0000\narc: B2 F3\narc: B3 H00L0000\narc: B5 H02E0301\narc: B6 H02E0101\narc: C0 E1_H01W0000\narc: C1 E1_H01W0000\narc: C2 E1_H01W0000\narc: C3 V02S0401\narc: C5 V02S0201\narc: C6 E1_H01E0101\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 V00T0100\narc: D3 W1_H02E0201\narc: D5 H00L0100\narc: D6 H02E0201\narc: D7 S1_V02N0601\narc: E1_H01E0101 F7\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 Q2\narc: H01W0100 Q0\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F6\narc: N1_V02N0501 F7\narc: V01S0100 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 1110010011001100\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 0010001110101111\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 1100000000000000\nword: SLICEA.K1.INIT 1011000100110011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R22C27:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 W1_H02E0001\narc: H00L0000 V02N0001\narc: H00L0100 V02N0101\narc: H00R0000 W1_H02E0601\narc: H00R0100 E1_H02W0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H01E0101\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 V02N0201\narc: V00T0000 H02E0201\narc: V00T0100 H02W0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0701 V02N0701\narc: S1_V02S0301 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: A4 V00B0000\narc: A5 W1_H02E0701\narc: A7 H00R0000\narc: B3 H02W0301\narc: B4 V02S0701\narc: B5 H00L0000\narc: B7 H02E0301\narc: C3 F6\narc: C4 S1_V02N0001\narc: C5 V00T0100\narc: C7 F4\narc: CE0 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D3 W1_H02E0001\narc: D4 V02N0601\narc: D5 H00R0100\narc: D7 V02S0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q1\narc: E3_H06E0303 F6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F1\narc: LSR1 E1_H02W0301\narc: M0 V00T0000\narc: M1 E1_H02W0001\narc: M2 V00T0000\narc: M6 N1_V01N0101\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0001 F5\narc: S3_V06S0103 F1\narc: V01S0000 F1\narc: W3_H06W0103 F1\nword: SLICEC.K0.INIT 0001010100111111\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R22C28:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 H02W0101\narc: H00R0000 H02W0401\narc: H00R0100 H02W0701\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 H01E0101\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0701\narc: V00T0000 W1_H02E0201\narc: V00T0100 W1_H02E0101\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0701 V02N0701\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A7 W1_H02E0701\narc: B3 H00R0100\narc: B7 N1_V01S0000\narc: C3 W1_H02E0601\narc: C4 W1_H02E0401\narc: C5 H02E0601\narc: C7 N1_V02S0001\narc: CE0 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 V02S0201\narc: D3 H02W0201\narc: D4 H01W0000\narc: D5 H00L0100\narc: D7 V02S0401\narc: E1_H01E0101 F5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F5\narc: H01W0100 F1\narc: LSR0 H02W0301\narc: M0 V00T0000\narc: M1 H00R0000\narc: M2 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F5\narc: N3_V06N0303 F5\narc: S1_V02S0101 Q1\narc: S1_V02S0601 F6\narc: S3_V06S0303 F5\narc: V01S0000 F5\narc: V01S0100 F5\narc: W1_H02W0601 F4\narc: W3_H06W0103 F1\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 0000111100000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0011111111111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111011101110011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R22C29:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 S1_V02N0501\narc: E3_H06E0103 H01E0101\narc: H00R0100 W1_H02E0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0203 V01N0001\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0201 H02E0201\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02W0601\narc: V00B0100 W1_H02E0701\narc: V00T0000 H02W0201\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 V02N0701\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0601 W3_H06E0303\narc: W3_H06W0103 N3_V06S0103\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0303 E3_H06W0303\narc: A1 E1_H01E0001\narc: B0 V02S0301\narc: B1 H01W0100\narc: B6 V01S0000\narc: C0 N1_V01N0001\narc: C1 W1_H02E0401\narc: C6 V00T0000\narc: CE1 E1_H02W0101\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V00T0100\narc: D6 V02N0401\narc: D7 H00R0100\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q4\narc: M2 V00B0100\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: V01S0000 Q6\narc: V01S0100 F1\narc: W1_H02W0201 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0011111100000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R22C2:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 E1_H01W0100\narc: H00R0000 H02E0401\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 H02E0401\narc: N3_V06N0303 S3_V06N0303\narc: V00B0000 S1_V02N0201\narc: V00T0000 H02E0201\narc: CE2 S1_V02N0601\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H02E0001\narc: D2 H02W0201\narc: D3 V02N0201\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q4\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R22C30:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 E3_H06W0303\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 V06N0203\narc: E3_H06E0303 H01E0101\narc: H00L0000 E1_H02W0201\narc: H00L0100 S1_V02N0301\narc: H00R0100 W1_H02E0501\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0401\narc: V00B0000 H02E0401\narc: V00B0100 H02E0501\narc: V00T0000 V02S0601\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 V01N0101\narc: N1_V02N0001 W3_H06E0003\narc: W3_H06W0203 E1_H02W0701\narc: W3_H06W0303 E1_H01W0100\narc: W3_H06W0103 E3_H06W0103\narc: A1 V02S0501\narc: A3 V00T0000\narc: A5 S1_V02N0101\narc: B1 E1_H02W0101\narc: B3 W1_H02E0301\narc: B5 N1_V01S0000\narc: B7 H02E0101\narc: C1 W1_H02E0601\narc: C3 H00R0100\narc: C5 V00T0100\narc: C6 V02N0001\narc: C7 V01N0101\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D3 V00B0100\narc: D5 V00B0000\narc: D6 H00L0100\narc: D7 H02W0201\narc: E1_H02E0101 F3\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q6\narc: LSR0 H02W0301\narc: M0 E1_H02W0601\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N3_V06N0003 F0\narc: S3_V06S0303 F5\narc: V01S0000 Q6\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0000111100000000\nword: SLICED.K1.INIT 0000000000001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R22C31:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 S1_V02N0201\narc: H00L0100 H02E0101\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 H02W0301\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 N1_V02S0501\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0401\narc: V00B0100 H02W0501\narc: V00T0000 V02S0601\narc: V00T0100 N1_V02S0501\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0501 E1_H01W0100\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0201 W3_H06E0103\narc: S1_V02S0701 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0303 E3_H06W0203\narc: A3 S1_V02N0701\narc: A4 V00T0000\narc: A5 V02S0301\narc: A7 H00R0000\narc: B3 V02N0301\narc: B4 S1_V02N0501\narc: B5 W1_H02E0301\narc: B7 V00B0100\narc: C1 E1_H02W0401\narc: C3 V02N0601\narc: C4 S1_V02N0001\narc: C5 N1_V02S0201\narc: C6 V00T0100\narc: C7 H02E0401\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D3 V02N0001\narc: D4 H00R0100\narc: D5 H00L0100\narc: D6 V02S0401\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: E1_H01E0101 Q4\narc: E1_H02E0501 F5\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H00R0100 F5\narc: H01W0000 F1\narc: H01W0100 F6\narc: LSR0 H02E0301\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0001 F4\narc: N1_V01N0101 F6\narc: N1_V02N0401 F6\narc: N1_V02N0601 F6\narc: N3_V06N0303 F6\narc: S1_V02S0601 F6\narc: S3_V06S0203 F7\narc: V01S0000 F4\narc: V01S0100 F1\narc: W1_H02W0401 F4\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0111000001111100\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 1111000011111111\nword: SLICED.K1.INIT 0000000100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R22C32:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 S1_V02N0401\narc: E3_H06E0103 N1_V01S0100\narc: H00L0100 V02N0101\narc: H00R0000 E1_H02W0401\narc: H00R0100 E1_H02W0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0101 H06E0103\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 E3_H06W0303\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 H02W0601\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02N0601\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V06N0003\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 E3_H06W0203\narc: E1_H01E0101 W3_H06E0203\narc: W3_H06W0103 E1_H02W0101\narc: E3_H06E0003 W3_H06E0303\narc: A1 H00L0100\narc: B1 S1_V02N0301\narc: B3 H00L0000\narc: B5 E1_H02W0301\narc: B7 V02S0701\narc: C1 V02S0601\narc: C2 H00L0000\narc: C3 V02N0401\narc: C5 S1_V02N0201\narc: C7 E1_H01E0101\narc: CE0 H00R0100\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0001\narc: D2 H01E0101\narc: D3 V02N0001\narc: D5 V00B0000\narc: D7 V00B0000\narc: E3_H06E0203 Q7\narc: E3_H06E0303 Q5\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0000 F2\narc: H01W0100 Q0\narc: M0 V00B0100\narc: M2 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0701 Q5\narc: N3_V06N0203 Q7\narc: W1_H02W0001 Q0\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q7\narc: W3_H06W0303 Q5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111100011110000\nword: SLICEB.K0.INIT 1111111111110000\nword: SLICEB.K1.INIT 1111001111000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R22C33:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0601 W1_H02E0301\narc: H00L0100 N1_V02S0301\narc: H00R0000 W1_H02E0401\narc: H00R0100 W1_H02E0701\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0501 V01N0101\narc: N1_V02N0701 H06W0203\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N3_V06S0303\narc: V00T0000 H02E0001\narc: V00T0100 H02E0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 N1_V01S0000\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0303 E3_H06W0203\narc: A1 H02W0501\narc: A6 N1_V01N0101\narc: B1 V01N0001\narc: B5 V02N0501\narc: B6 N1_V02S0701\narc: C1 V02N0601\narc: C2 H00L0100\narc: C3 N1_V01N0001\narc: C5 V00T0000\narc: C6 H02E0401\narc: C7 V00T0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D2 E1_H02W0201\narc: D3 H00R0000\narc: D5 H02W0201\narc: D6 N1_V02S0401\narc: D7 V02S0601\narc: E1_H01E0001 F6\narc: E1_H01E0101 F2\narc: E1_H02E0401 F6\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 F5\narc: LSR0 H02E0301\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F2\narc: N1_V01N0101 Q7\narc: N1_V02N0301 F1\narc: N1_V02N0401 F6\narc: N1_V02N0601 F6\narc: N3_V06N0203 Q7\narc: V01S0000 F6\narc: W1_H02W0001 F2\narc: W3_H06W0203 Q7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000010101010\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0000000000001111\nword: SLICED.K0.INIT 1100110010000000\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R22C34:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V02S0601\narc: E3_H06E0203 V06N0203\narc: H00R0000 H02E0401\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H02W0701\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 H01E0101\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 V02S0101\narc: V00T0100 V02N0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 V06S0303\narc: W1_H02W0701 E1_H02W0601\narc: H01W0000 W3_H06E0103\narc: W3_H06W0203 N3_V06S0203\narc: E3_H06E0303 W3_H06E0203\narc: A1 H00L0000\narc: A3 V00T0000\narc: A7 N1_V01N0101\narc: B0 E1_H02W0101\narc: B1 H02W0101\narc: B2 N1_V02S0101\narc: B3 V02N0101\narc: B6 V00B0100\narc: B7 H02E0101\narc: C0 V02N0401\narc: C1 H00R0100\narc: C2 S1_V02N0401\narc: C3 H00R0100\narc: C6 N1_V02S0001\narc: C7 S1_V02N0201\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 V02N0601\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 V02S0201\narc: D2 H02E0201\narc: D3 V02S0201\narc: D6 H02E0201\narc: D7 V02S0401\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q4\narc: E1_H02E0301 F1\narc: E1_H02E0701 F7\narc: E3_H06E0003 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: N3_V06N0003 Q0\narc: N3_V06N0103 Q2\narc: N3_V06N0303 Q6\narc: S1_V02S0601 Q4\narc: V00T0000 Q2\narc: V01S0000 F1\narc: V01S0100 F7\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1010110000000000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1010110000000000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1010110000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R22C35:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0301 V02N0301\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 H01E0101\narc: E3_H06E0003 W1_H02E0001\narc: H00L0000 H02E0001\narc: H00L0100 N1_V02S0301\narc: H00R0000 H02E0601\narc: H00R0100 H02E0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 V01N0101\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 S1_V02N0401\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 H06E0103\narc: S1_V02S0401 H02E0401\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 N1_V02S0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0701 N3_V06S0203\narc: E1_H02E0401 W3_H06E0203\narc: S1_V02S0101 W3_H06E0103\narc: W3_H06W0203 E3_H06W0103\narc: A0 N1_V02S0501\narc: A7 N1_V01N0101\narc: B0 S1_V02N0301\narc: B1 V00T0000\narc: B2 H00R0000\narc: B5 V02N0701\narc: B6 V02S0701\narc: B7 S1_V02N0501\narc: C0 V02S0601\narc: C1 H00R0100\narc: C2 V02N0401\narc: C3 N1_V01N0001\narc: C4 H02E0601\narc: C5 V02S0001\narc: C6 W1_H02E0601\narc: C7 H02W0401\narc: CE0 V02S0201\narc: CE2 N1_V02S0601\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 E1_H02W0201\narc: D2 V00T0100\narc: D3 S1_V02N0001\narc: D4 F0\narc: D5 F0\narc: D6 W1_H02E0201\narc: D7 H00L0100\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q0\narc: E1_H02E0201 Q0\narc: E3_H06E0103 F1\narc: E3_H06E0203 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 Q4\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F0\narc: N1_V01N0101 Q6\narc: N3_V06N0303 Q6\narc: S1_V02S0301 F3\narc: S3_V06S0003 Q0\narc: S3_V06S0203 Q4\narc: V00T0000 Q0\narc: V00T0100 F3\narc: W1_H02W0401 F4\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1010110000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0000000011110000\nword: SLICEA.K0.INIT 1011000110100000\nword: SLICEA.K1.INIT 1100000011110000\nword: SLICEC.K0.INIT 0000111100000000\nword: SLICEC.K1.INIT 0000000000110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R22C36:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 H01E0101\narc: H00L0100 S1_V02N0301\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0501 V01N0101\narc: N3_V06N0003 V01N0001\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 V01N0101\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 H02W0201\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V02S0101\narc: W1_H02W0401 S1_V02N0401\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: S1_V02S0501 W3_H06E0303\narc: W3_H06W0303 E1_H01W0100\narc: W3_H06W0103 E3_H06W0003\narc: A7 H02W0501\narc: B0 V00T0000\narc: B3 H02E0301\narc: B5 V00B0100\narc: B6 S1_V02N0701\narc: B7 V02S0501\narc: C0 H02W0601\narc: C3 S1_V02N0601\narc: C4 H02W0401\narc: C5 N1_V02S0001\narc: C6 V02S0001\narc: C7 V00B0100\narc: D0 S1_V02N0001\narc: D1 E1_H02W0201\narc: D3 S1_V02N0201\narc: D4 H01W0000\narc: D5 H00L0100\narc: D6 V00B0000\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 F4\narc: E1_H02E0001 F0\narc: E1_H02E0401 F4\narc: E3_H06E0203 F4\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: H01W0100 F4\narc: M0 V00B0100\narc: N1_V01N0001 F7\narc: N1_V01N0101 F4\narc: N1_V02N0601 F6\narc: N1_V02N0701 F7\narc: S1_V02S0401 F4\narc: V01S0000 F4\narc: W1_H02W0501 F5\narc: W1_H02W0601 F4\narc: W3_H06W0203 F4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0011001100001111\nword: SLICEC.K0.INIT 0000111111111111\nword: SLICEC.K1.INIT 0000001100000000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1010101011000000\nword: SLICEA.K0.INIT 1111000000110011\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R22C37:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0103 N3_V06S0103\narc: H00L0000 H02E0201\narc: H00L0100 V02S0301\narc: H00R0000 H02E0401\narc: H00R0100 V02N0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 H06W0003\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 W1_H02E0701\narc: V00T0000 S1_V02N0601\narc: V00T0100 H02W0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 H01E0001\narc: E1_H01E0101 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: B4 H00L0000\narc: B5 H00L0000\narc: C4 H02W0401\narc: C5 V00T0100\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE2 H00R0000\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D4 H00R0100\narc: D5 H02W0001\narc: E3_H06E0003 Q0\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: M0 W1_H02E0601\narc: M2 V00B0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: N1_V02N0001 Q2\narc: N1_V02N0201 Q0\narc: N3_V06N0303 F5\narc: S3_V06S0103 Q2\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100000011001111\nword: SLICEC.K1.INIT 0000000011111100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R22C38:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0303 W1_H02E0501\narc: H00L0100 E1_H02W0301\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 H02W0301\narc: S1_V02S0601 H02W0601\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 W1_H02E0601\narc: V00B0100 H02W0501\narc: V00T0000 S1_V02N0401\narc: V00T0100 V02S0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V06S0203\narc: S1_V02S0501 W3_H06E0303\narc: S3_V06S0203 W3_H06E0203\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0103 W3_H06E0003\narc: A0 H00L0100\narc: A1 H02W0501\narc: A2 H02E0701\narc: B0 N1_V02S0101\narc: B1 H00R0100\narc: B2 V02N0301\narc: B4 V02N0701\narc: B5 V02N0701\narc: B6 V02N0501\narc: B7 V02N0501\narc: C0 N1_V02S0401\narc: C1 S1_V02N0401\narc: C2 H00L0000\narc: C4 V02S0001\narc: C5 V00T0100\narc: C6 W1_H02E0601\narc: C7 V00T0000\narc: CE1 H02W0101\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 V02N0001\narc: D2 V02N0201\narc: D4 W1_H02E0001\narc: D5 S1_V02N0601\narc: D6 V02N0601\narc: D7 V00B0000\narc: E1_H01E0001 F2\narc: E1_H01E0101 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 F0\narc: H01W0000 F1\narc: M2 W1_H02E0601\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q2\narc: N3_V06N0103 Q2\narc: N3_V06N0303 F6\narc: V01S0000 F6\narc: W3_H06W0203 Q4\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 0011001100110010\nword: SLICEA.K1.INIT 1100010010000000\nword: SLICED.K0.INIT 1111001111110000\nword: SLICED.K1.INIT 1111111100110000\nword: SLICEB.K0.INIT 0111000011110000\nword: SLICEB.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 1100000011001111\nword: SLICEC.K1.INIT 0000000011111100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R22C39:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 S3_V06N0303\narc: E3_H06E0003 N3_V06S0003\narc: E3_H06E0103 N3_V06S0103\narc: E3_H06E0203 H01E0001\narc: E3_H06E0303 H01E0101\narc: H00L0100 V02S0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02S0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 H06E0203\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 H06W0203\narc: V00B0100 H02E0701\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02N0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0601 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: A1 H00L0000\narc: B0 H02W0101\narc: B1 W1_H02E0301\narc: B2 H00R0100\narc: B3 E1_H02W0301\narc: B4 E1_H02W0101\narc: B5 E1_H02W0101\narc: B6 V02S0501\narc: B7 H02E0101\narc: C0 V02S0601\narc: C1 V02N0401\narc: C2 H02E0601\narc: C3 H00R0100\narc: C4 H02E0401\narc: C5 E1_H02W0601\narc: C6 V00B0100\narc: C7 H02W0601\narc: CE0 N1_V02S0201\narc: CE2 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 H00R0000\narc: D2 S1_V02N0201\narc: D3 W1_H02E0001\narc: D4 H00L0100\narc: D5 H02E0001\narc: D6 S1_V02N0601\narc: D7 H02E0201\narc: E1_H01E0001 F2\narc: E1_H01E0101 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q0\narc: H01W0000 F2\narc: H01W0100 F6\narc: M2 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V02N0601 F6\narc: N3_V06N0103 F2\narc: N3_V06N0303 F5\narc: S1_V02S0101 F1\narc: W3_H06W0203 Q4\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 1111001111000000\nword: SLICEA.K1.INIT 1011100011110000\nword: SLICEC.K0.INIT 1100000011001111\nword: SLICEC.K1.INIT 0000000011111100\nword: SLICEB.K0.INIT 1111001111110000\nword: SLICEB.K1.INIT 1111111100001100\nword: SLICED.K0.INIT 1111001111110000\nword: SLICED.K1.INIT 1111111100001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R22C3:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 H02W0001\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 H01E0001\narc: V00B0100 H02E0501\narc: C1 H02E0401\narc: CE1 H00L0000\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: H01W0100 Q6\narc: M2 W1_H02E0601\narc: M4 H02W0401\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0000 Q4\narc: W1_H02W0201 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R22C40:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0103 H01E0101\narc: H00L0100 N1_V02S0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 H02E0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 H02W0701\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 H01E0001\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0203 H06W0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02W0201\narc: V00T0100 V02S0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 N1_V02S0601\narc: S3_V06S0003 W3_H06E0003\narc: W3_H06W0103 E1_H02W0201\narc: W3_H06W0303 S3_V06N0303\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: B0 H00R0100\narc: B5 V02S0501\narc: B7 V02S0501\narc: C0 H02E0601\narc: C5 V02N0201\narc: C7 V02N0201\narc: CE0 H02E0101\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D2 E1_H02W0001\narc: D4 V02N0401\narc: D5 V02N0601\narc: D6 V01N0001\narc: D7 V02N0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q1\narc: E1_H02E0601 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q4\narc: M0 V00B0000\narc: M1 H00L0100\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N1_V02N0401 Q6\narc: N3_V06N0103 Q1\narc: N3_V06N0303 Q6\narc: S3_V06S0303 Q6\narc: V01S0100 Q4\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 1111000011110011\nword: SLICEC.K0.INIT 1111111100000000\nword: SLICEC.K1.INIT 1111000011110011\nword: SLICEA.K0.INIT 1100111111111111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R22C41:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 W1_H02E0301\narc: H00R0000 H02W0401\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 E1_H01W0000\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02N0601\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0501 V06N0303\narc: W1_H02W0601 N1_V01S0000\narc: E1_H02E0001 W3_H06E0003\narc: S1_V02S0101 W3_H06E0103\narc: S1_V02S0701 W3_H06E0203\narc: W3_H06W0103 E1_H02W0201\narc: W3_H06W0303 V06N0303\narc: A0 F5\narc: A1 V02S0501\narc: A3 S1_V02N0701\narc: A6 V00T0100\narc: A7 H02E0501\narc: B0 S1_V02N0301\narc: B1 H02E0301\narc: B3 S1_V02N0301\narc: B4 N1_V02S0501\narc: B6 H02W0101\narc: B7 H02W0301\narc: C0 H00L0100\narc: C1 E1_H02W0601\narc: C3 H02W0601\narc: C4 S1_V02N0001\narc: C5 E1_H01E0101\narc: C6 V00T0000\narc: C7 V02N0001\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 V02N0201\narc: D3 V00B0100\narc: D4 V02N0601\narc: D5 V00B0000\narc: D6 V02S0401\narc: D7 S1_V02N0401\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q6\narc: E1_H02E0701 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0000 F3\narc: H01W0100 Q4\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F5\narc: N1_V02N0501 F5\narc: S1_V02S0501 F5\narc: S1_V02S0601 Q4\narc: V00B0000 Q4\narc: V01S0000 F0\narc: V01S0100 Q4\narc: W1_H02W0401 Q6\narc: W1_H02W0701 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100010010000000\nword: SLICEA.K0.INIT 1111010100110001\nword: SLICEA.K1.INIT 1001010001001111\nword: SLICEC.K0.INIT 0000110000000000\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 0001000000000000\nword: SLICED.K1.INIT 1011000011110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R22C42:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0701 V06S0203\narc: E3_H06E0203 N3_V06S0203\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 S1_V02N0001\narc: H00L0100 E1_H02W0301\narc: H00R0000 N1_V02S0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V02S0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 V02S0701\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0601 W3_H06E0303\narc: N3_V06N0103 W3_H06E0103\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A1 H02E0501\narc: A3 V02S0501\narc: B1 S1_V02N0101\narc: B2 H00R0100\narc: B3 E1_H02W0101\narc: B5 W1_H02E0101\narc: B6 V02S0701\narc: B7 V02S0701\narc: C1 H02E0601\narc: C2 N1_V01N0001\narc: C3 H00L0100\narc: C4 V00B0100\narc: C5 N1_V02S0201\narc: C6 V02S0001\narc: C7 V02S0001\narc: CE0 H00R0000\narc: CE2 H00R0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D2 W1_H02E0201\narc: D3 H02W0001\narc: D4 E1_H02W0201\narc: D5 H02E0201\narc: D6 F2\narc: D7 H02E0001\narc: E1_H01E0001 F6\narc: E1_H01E0101 F4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q1\narc: H01W0100 Q5\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F3\narc: N1_V02N0401 Q6\narc: S1_V02S0701 Q5\narc: V00B0100 Q5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111010100110000\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 1111110000110000\nword: SLICEB.K0.INIT 0000000011110011\nword: SLICEB.K1.INIT 1001010001001111\nword: SLICED.K0.INIT 1111000011110011\nword: SLICED.K1.INIT 1111000011110011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R22C43:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 V01N0001\narc: H00L0000 V02S0001\narc: H00L0100 H02E0301\narc: H00R0100 V02S0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H06W0303\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0203 E1_H01W0000\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00T0000 N1_V02S0401\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 N3_V06S0203\narc: H01W0000 W3_H06E0103\narc: S3_V06S0003 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A5 E1_H02W0701\narc: A7 E1_H02W0701\narc: B1 E1_H02W0301\narc: B3 H00R0100\narc: B5 H00L0000\narc: B7 W1_H02E0301\narc: C1 H02W0601\narc: C3 H02W0601\narc: C4 V02S0001\narc: C5 E1_H02W0601\narc: C6 V02S0001\narc: C7 E1_H02W0601\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V01S0100\narc: D3 H00R0000\narc: D4 V02N0601\narc: D5 V02N0601\narc: D6 V02N0401\narc: D7 V02N0401\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 F4\narc: H01W0100 Q1\narc: LSR1 V00B0000\narc: M4 W1_H02E0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: N1_V02N0101 F1\narc: N3_V06N0003 F3\narc: N3_V06N0103 F1\narc: V01S0100 F6\narc: W1_H02W0101 Q3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100000011001111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100000011001111\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 1100100000000000\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1100100000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R22C44:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 V01N0101\narc: E3_H06E0003 V01N0001\narc: E3_H06E0103 V01N0101\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 S1_V02N0001\narc: H00L0100 V02N0301\narc: H00R0000 H02E0401\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 H06W0203\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 W1_H02E0701\narc: V00T0000 H02W0201\narc: V00T0100 H02W0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 V02S0701\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0601 W3_H06E0303\narc: A5 N1_V01N0101\narc: B4 H00R0000\narc: B5 H00L0000\narc: C4 N1_V02S0201\narc: C5 W1_H02E0601\narc: CE0 S1_V02N0201\narc: CE1 S1_V02N0201\narc: CE2 H02E0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D4 H02E0201\narc: D5 W1_H02E0201\narc: E3_H06E0203 Q4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q0\narc: M0 V00T0000\narc: M2 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: S1_V02S0401 Q6\narc: V01S0100 Q2\narc: W3_H06W0303 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100111100000011\nword: SLICEC.K1.INIT 1010110011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R22C45:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0301 W1_H02E0301\narc: E3_H06E0103 V01N0101\narc: H00L0000 V02S0201\narc: H00L0100 H02W0301\narc: H00R0000 N1_V02S0601\narc: H00R0100 H02E0501\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 W1_H02E0601\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02N0601\narc: V00T0100 H02E0301\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 V02N0701\narc: E1_H02E0201 W3_H06E0103\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: B0 E1_H01W0100\narc: B3 V02S0101\narc: B5 H00R0000\narc: B7 V00B0000\narc: C0 H00L0000\narc: C3 H00L0100\narc: C5 S1_V02N0001\narc: C7 V00T0000\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 N1_V02S0201\narc: D1 S1_V02N0201\narc: D2 V00B0100\narc: D3 H02E0001\narc: D5 V02N0401\narc: D7 V02N0401\narc: E1_H01E0001 F0\narc: E1_H01E0101 Q0\narc: E1_H02E0001 F2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: H01W0100 F2\narc: M0 V00T0100\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q2\narc: N1_V02N0001 F0\narc: N1_V02N0201 F2\narc: N1_V02N0501 F7\narc: N3_V06N0203 F7\narc: N3_V06N0303 F5\narc: S1_V02S0501 F5\narc: S1_V02S0701 F7\narc: V01S0000 F5\narc: V01S0100 Q0\narc: W1_H02W0501 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 1100111111000000\nword: SLICEA.K0.INIT 0000110011111100\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R22C46:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 N3_V06S0203\narc: H00L0100 W1_H02E0301\narc: H00R0000 W1_H02E0601\narc: H00R0100 V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 V01N0001\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 H01E0001\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 E1_H02W0601\narc: V00T0100 W1_H02E0101\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 E1_H02W0701\narc: E1_H01E0001 W3_H06E0003\narc: W3_H06W0303 S3_V06N0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0103 E3_H06W0003\narc: A5 E1_H02W0701\narc: B0 H00R0100\narc: B1 V00T0000\narc: B3 H02E0301\narc: B5 E1_H02W0101\narc: B7 H02W0301\narc: C0 W1_H02E0401\narc: C1 H00L0100\narc: C3 W1_H02E0401\narc: C4 N1_V02S0201\narc: C5 N1_V02S0201\narc: C7 W1_H02E0401\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 V02S0201\narc: D3 V01S0100\narc: D4 V00B0000\narc: D5 V00B0000\narc: D7 E1_H02W0201\narc: E1_H01E0101 F1\narc: E1_H02E0101 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q7\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F7\narc: V00T0000 Q0\narc: V01S0000 F3\narc: V01S0100 F4\narc: W1_H02W0001 F0\narc: W1_H02W0501 F7\narc: W3_H06W0003 Q3\narc: W3_H06W0203 Q7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100000011001111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100000011001111\nword: SLICEA.K0.INIT 1100000011001111\nword: SLICEA.K1.INIT 0000111100001100\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1110000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R22C47:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0103 V01N0101\narc: H00L0000 N1_V02S0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02E0501\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H06W0303\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 H06E0303\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H06E0203\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V01S0100\narc: V00B0100 V02S0101\narc: V00T0000 S1_V02N0601\narc: V00T0100 W1_H02E0101\narc: W1_H02W0301 E1_H02W0301\narc: W3_H06W0103 E3_H06W0003\narc: A3 H00L0100\narc: A5 V02N0301\narc: B3 H02E0101\narc: B5 H02W0101\narc: B7 S1_V02N0501\narc: C3 H00L0000\narc: C4 N1_V02S0201\narc: C5 N1_V02S0201\narc: C6 V00T0000\narc: C7 V00T0000\narc: CE0 V02N0201\narc: CLK0 G_HPBX0000\narc: D2 H01E0101\narc: D3 S1_V02N0201\narc: D4 H00R0100\narc: D5 H00R0100\narc: D6 H01W0000\narc: D7 W1_H02E0201\narc: E1_H01E0001 F4\narc: E1_H01E0101 F7\narc: E1_H02E0501 F7\narc: E3_H06E0303 F6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F1\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 F1\narc: N1_V02N0701 F7\narc: S1_V02S0101 Q1\narc: V01S0000 F7\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1100000011001000\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1110000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R22C48:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 V01N0101\narc: E3_H06E0003 V01N0001\narc: E3_H06E0103 V01N0101\narc: H00L0000 H02E0201\narc: H00L0100 V02N0101\narc: H00R0000 N1_V02S0601\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 H06E0203\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 H01E0101\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 H06W0303\narc: V00B0000 W1_H02E0601\narc: V00B0100 H02W0701\narc: V00T0000 H02E0201\narc: V00T0100 V02S0501\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 V02N0701\narc: E1_H02E0601 W3_H06E0303\narc: W3_H06W0003 N3_V06S0003\narc: E3_H06E0303 W3_H06E0203\narc: A3 V02N0701\narc: A7 E1_H02W0501\narc: B1 H00R0100\narc: B3 E1_H02W0301\narc: B4 H02W0101\narc: B7 E1_H02W0301\narc: C0 H02E0401\narc: C1 N1_V02S0401\narc: C2 H00L0000\narc: C3 H00L0000\narc: C4 V00T0100\narc: C6 V00T0000\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 H01E0101\narc: D1 W1_H02E0001\narc: D2 V02S0201\narc: D3 V02S0201\narc: D4 V02S0401\narc: D5 H02W0201\narc: D6 H00L0100\narc: D7 H00L0100\narc: E1_H01E0101 Q4\narc: E1_H02E0201 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q1\narc: H01W0100 Q4\narc: M2 V00B0100\narc: M4 W1_H02E0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F6\narc: S3_V06S0103 Q1\narc: V01S0100 Q4\narc: W1_H02W0201 F2\narc: W3_H06W0103 Q1\narc: W3_H06W0203 Q4\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 1111110000110000\nword: SLICEC.K0.INIT 1111001111000000\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 1110000000000000\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 1110000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R22C49:PLC2\narc: E1_H02E0501 W1_H02E0501\narc: H00L0100 W1_H02E0101\narc: N1_V02N0001 H02W0001\narc: N1_V02N0301 H02E0301\narc: N1_V02N0501 H02E0501\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 H01E0101\narc: V00B0000 W1_H02E0601\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02E0001\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 V02S0701\narc: E1_H02E0101 W3_H06E0103\narc: N3_V06N0203 W3_H06E0203\narc: W3_H06W0003 N1_V01S0000\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: B4 S1_V02N0701\narc: B6 N1_V02S0701\narc: C0 H00L0100\narc: C1 H02W0401\narc: C2 H02E0601\narc: C3 E1_H02W0401\narc: C4 V02S0201\narc: C6 V01N0101\narc: C7 V00T0000\narc: CE2 N1_V02S0601\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 V00B0100\narc: D2 V00B0100\narc: D3 V00B0100\narc: D4 V01N0001\narc: D5 V00B0000\narc: D6 V00B0000\narc: D7 V02S0401\narc: E1_H01E0101 F1\narc: E1_H02E0001 F0\narc: E1_H02E0201 F2\narc: E1_H02E0301 F3\narc: E1_H02E0701 F7\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q6\narc: M4 H02E0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0601 Q6\narc: S1_V02S0401 Q4\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 1100111100000011\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 1111111111000000\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R22C4:PLC2\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 W1_H02E0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H06W0203\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 E1_H02W0101\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02N0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0401 V01N0001\narc: A0 W1_H02E0701\narc: A3 H02W0701\narc: A5 W1_H02E0701\narc: A6 W1_H02E0701\narc: B0 V00B0000\narc: B3 H02E0301\narc: B5 H01E0101\narc: B6 H01E0101\narc: C0 H00R0100\narc: C2 H02E0601\narc: C3 S1_V02N0601\narc: C5 V00B0100\narc: C6 V00B0100\narc: C7 S1_V02N0201\narc: CE1 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D2 H02E0001\narc: D3 V00B0100\narc: D5 E1_H01W0100\narc: D6 E1_H01W0100\narc: D7 S1_V02N0401\narc: E3_H06E0103 Q2\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: M0 H01E0001\narc: M2 V00T0100\narc: M4 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F7\narc: N1_V02N0001 F2\narc: N1_V02N0201 F0\narc: V00B0100 F7\narc: V01S0100 F4\nword: SLICED.K0.INIT 0010000000110011\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEB.K0.INIT 1111111111110000\nword: SLICEB.K1.INIT 1010100000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1101111111001100\nword: SLICEA.K0.INIT 0010000000110011\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R22C50:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 N1_V01S0100\narc: E3_H06E0303 V01N0101\narc: H00L0000 H02E0201\narc: H00R0000 V02S0401\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 E1_H01W0100\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00T0000 H02E0001\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 E1_H02W0301\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0601 W3_H06E0303\narc: N3_V06N0303 W3_H06E0303\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0203 N1_V01S0000\narc: W3_H06W0303 S3_V06N0303\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A0 S1_V02N0501\narc: A2 H02E0501\narc: B2 H02E0101\narc: B3 H00R0000\narc: B4 H02E0301\narc: B5 H00L0000\narc: B6 H01E0101\narc: B7 V00T0000\narc: E1_H01E0101 F4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V01N0001 F5\narc: N1_V01N0101 F3\narc: N1_V02N0201 F2\narc: N1_V02N0701 F7\narc: V01S0000 F6\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R22C51:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0701 W1_H02E0701\narc: H00L0000 V02N0201\narc: N1_V02N0301 H01E0101\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 H01E0001\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0303 N1_V01S0100\narc: W3_H06W0103 E3_H06W0003\narc: B0 H02E0301\narc: B1 H02E0101\narc: B2 S1_V02N0301\narc: B3 V01N0001\narc: B4 H00L0000\narc: B5 E1_H02W0101\narc: B6 V00B0100\narc: B7 V00B0000\narc: E1_H01E0001 F3\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 F2\narc: N1_V01N0001 F5\narc: N1_V02N0001 F0\narc: N1_V02N0401 F6\narc: N1_V02N0601 F4\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R22C52:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V02N0401\narc: H00L0000 H02W0201\narc: H00R0000 H02W0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 H06E0103\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 V02S0001\narc: V00T0000 S1_V02N0401\narc: W1_H02W0301 E3_H06W0003\narc: H01W0000 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: B0 V00T0000\narc: B1 V02S0101\narc: B2 H00R0000\narc: B3 H00R0100\narc: B4 V02S0501\narc: B5 H00L0000\narc: B6 V00B0000\narc: B7 E1_H02W0101\narc: E1_H01E0001 F1\narc: E1_H02E0001 F0\narc: E1_H02E0601 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V01N0001 F5\narc: N1_V01N0101 F3\narc: N1_V02N0001 F2\narc: V01S0000 F4\narc: V01S0100 F7\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R22C53:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0401 V02S0401\narc: H00R0000 H02E0401\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H01E0001\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V02S0601\narc: V00B0100 S1_V02N0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 N1_V02S0501\narc: H01W0100 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: B0 H02W0301\narc: B1 V02N0301\narc: B2 S1_V02N0301\narc: B3 V02N0101\narc: B4 H02E0101\narc: B5 H00R0000\narc: B6 E1_H02W0101\narc: B7 V00B0100\narc: E1_H01E0001 F5\narc: E1_H02E0101 F1\narc: E1_H02E0201 F0\narc: E1_H02E0601 F4\narc: E3_H06E0003 F3\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V01N0001 F7\narc: N1_V02N0401 F6\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R22C54:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0601 N3_V06S0303\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H06E0203\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 H02W0401\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 S1_V02N0301\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0201 W3_H06E0103\narc: W1_H02W0501 W3_H06E0303\narc: B0 H00R0100\narc: B1 W1_H02E0301\narc: B4 V01S0000\narc: B5 H00R0000\narc: B6 V00B0100\narc: B7 V00B0000\narc: C4 W1_H02E0601\narc: C5 V02S0201\narc: C6 H01E0001\narc: C7 H02E0601\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D4 N1_V02S0601\narc: D5 N1_V02S0601\narc: D6 H00L0100\narc: D7 H00L0100\narc: E1_H01E0001 F0\narc: E1_H01E0101 Q4\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q6\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q7\narc: N1_V01N0101 Q6\narc: N1_V02N0501 Q5\narc: N1_V02N0601 Q4\narc: V00B0100 Q7\narc: V01S0000 Q5\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R22C55:PLC2\narc: H00L0000 H02E0001\narc: H00L0100 V02N0301\narc: H00R0000 H02W0601\narc: H00R0100 V02S0701\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H01E0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02N0301\narc: V00T0000 H02E0201\narc: V00T0100 V02S0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 E1_H01W0000\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: A0 N1_V02S0701\narc: A2 H00L0100\narc: B0 V00T0000\narc: B1 V00B0000\narc: B2 F3\narc: B3 H02W0101\narc: B5 F3\narc: C0 V02N0401\narc: C1 V02S0401\narc: C2 H00R0100\narc: C3 H02E0601\narc: C5 V00B0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 H00R0000\narc: D2 F0\narc: D3 V01S0100\narc: D4 E1_H01W0100\narc: D5 F0\narc: E1_H01E0001 F3\narc: E1_H02E0101 F3\narc: E1_H02E0201 F0\narc: E1_H02E0401 F4\narc: E3_H06E0003 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: H01W0100 Q6\narc: M4 V00T0100\narc: M6 W1_H02E0401\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F4\narc: V01S0000 F1\narc: V01S0100 F1\narc: W1_H02W0201 F2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111110\nword: SLICEA.K1.INIT 0011001100001111\nword: SLICEB.K0.INIT 0000000011001101\nword: SLICEB.K1.INIT 0000000011000000\nword: SLICEC.K0.INIT 1111111100000000\nword: SLICEC.K1.INIT 1111111100110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R22C56:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 V02S0301\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 H02E0201\narc: H00R0000 V02N0601\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 E1_H02W0301\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H01E0001\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 H01E0101\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02S0101\narc: V00T0000 H02W0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02N0701\narc: N3_V06N0003 W3_H06E0003\narc: B2 H02E0101\narc: B3 W1_H02E0301\narc: B4 W1_H02E0301\narc: B5 S1_V02N0701\narc: B7 V02S0701\narc: C2 N1_V02S0401\narc: C3 H00L0000\narc: C4 S1_V02N0001\narc: C5 H02W0401\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 V01S0100\narc: D4 H00R0100\narc: D5 V00B0000\narc: D7 H00L0100\narc: E1_H01E0001 F2\narc: E1_H01E0101 Q0\narc: E1_H02E0001 F2\narc: E1_H02E0701 F7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H00R0100 F5\narc: H01W0000 Q0\narc: H01W0100 F4\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q0\narc: V00T0100 F3\narc: V01S0000 Q0\narc: V01S0100 F5\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0011000011111100\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 1111001111000000\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 0000110000111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R22C57:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 E1_H01W0100\narc: E3_H06E0203 N3_V06S0203\narc: H00L0000 V02S0001\narc: H00R0000 S1_V02N0401\narc: H00R0100 H02E0701\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 H02W0301\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02N0201\narc: V00B0100 H02W0701\narc: V00T0000 V02S0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 S1_V02N0601\narc: A2 V00B0000\narc: A3 E1_H01E0001\narc: A5 S1_V02N0301\narc: B0 S1_V02N0301\narc: B2 H01W0100\narc: B3 H02E0301\narc: B5 V00B0100\narc: B7 H02E0101\narc: C0 V02S0401\narc: C2 H00R0100\narc: C3 H02W0401\narc: C5 V00T0000\narc: C7 V02N0001\narc: CE1 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 S1_V02N0001\narc: D2 E1_H02W0001\narc: D3 H00R0000\narc: D5 V02N0601\narc: D6 V01N0001\narc: D7 H02E0201\narc: E1_H01E0001 Q2\narc: E1_H02E0201 F0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: H01W0100 F5\narc: M0 V00B0100\narc: M6 E1_H02W0401\narc: MUXCLK1 CLK0\narc: S1_V02S0201 Q2\narc: W3_H06W0003 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000010010001100\nword: SLICEB.K0.INIT 0101111101001110\nword: SLICEB.K1.INIT 0101010100111111\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 1111111100000011\nword: SLICEA.K0.INIT 1111110000110000\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R22C58:PLC2\narc: H00L0000 V02N0001\narc: H00L0100 H02E0301\narc: H00R0000 S1_V02N0401\narc: H00R0100 W1_H02E0701\narc: N1_V02N0401 H06E0203\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0301 H06E0003\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0303 N3_V06S0203\narc: V00T0000 V02S0401\narc: V00T0100 H02E0101\narc: W1_H02W0001 V01N0001\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0701 V02S0701\narc: E3_H06E0003 W3_H06E0003\narc: A1 E1_H01E0001\narc: A3 V00B0000\narc: A5 V00B0000\narc: A7 H02E0501\narc: B0 V02N0101\narc: B1 H01W0100\narc: B3 H02E0101\narc: B4 E1_H02W0101\narc: B5 H02E0101\narc: B6 E1_H02W0101\narc: B7 V01S0000\narc: C0 H00L0000\narc: C1 H00L0100\narc: C3 V02S0401\narc: C4 V02N0001\narc: C5 V00T0000\narc: C6 H02E0401\narc: C7 V00T0100\narc: CE0 V02S0201\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 H00R0000\narc: D3 H00R0000\narc: D4 H00R0100\narc: D5 S1_V02N0401\narc: D6 H02E0201\narc: D7 S1_V02N0401\narc: E1_H01E0001 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V00B0000 Q4\narc: V01S0000 Q6\narc: W3_H06W0003 F3\narc: W3_H06W0103 F1\narc: W3_H06W0203 F7\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111101110111\nword: SLICED.K0.INIT 1100000011110011\nword: SLICED.K1.INIT 0011001101011111\nword: SLICEA.K0.INIT 0000110000001111\nword: SLICEA.K1.INIT 0011001101011111\nword: SLICEC.K0.INIT 0000110000001111\nword: SLICEC.K1.INIT 0101010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R22C59:PLC2\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0401 S1_V02N0401\narc: W3_H06W0003 E3_H06W0303\n\n.tile R22C5:PLC2\narc: H00R0100 H02E0701\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 V01N0001\narc: S1_V02S0501 H02W0501\narc: S3_V06S0303 H06W0303\narc: V00B0100 S1_V02N0101\narc: V00T0000 N1_V02S0601\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0701 V02S0701\narc: B1 V00B0000\narc: C0 V02N0601\narc: C1 N1_V01N0001\narc: CE2 H00R0100\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 S1_V02N0001\narc: E1_H01E0001 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 F1\narc: M0 V00B0100\narc: M1 W1_H02E0001\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: V00B0000 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111100001111\nword: SLICEA.K1.INIT 0000111100110011\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R22C60:PLC2\narc: S1_V02S0301 N1_V02S0301\narc: S3_V06S0203 H06E0203\narc: W1_H02W0101 V02N0101\n\n.tile R22C61:PLC2\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\n\n.tile R22C62:PLC2\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 N1_V01S0100\n\n.tile R22C64:PLC2\narc: S1_V02S0501 N3_V06S0303\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N3_V06S0103\narc: E3_H06E0003 W3_H06E0003\n\n.tile R22C65:PLC2\narc: W3_H06W0303 E3_H06W0203\n\n.tile R22C66:PLC2\narc: S1_V02S0101 N3_V06S0103\n\n.tile R22C67:PLC2\narc: S1_V02S0101 N3_V06S0103\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\n\n.tile R22C6:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 N1_V01S0100\narc: H00R0000 H02W0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 V02N0101\narc: V00T0000 S1_V02N0401\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 S3_V06N0303\narc: W3_H06W0103 S3_V06N0103\narc: D0 H02W0001\narc: D1 V02S0201\narc: D2 V00B0100\narc: D3 E1_H02W0001\narc: E1_H02E0101 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H00R0000\narc: M2 V00T0000\narc: M3 H00R0100\narc: M4 V00T0000\narc: M5 H00R0000\narc: M6 V00T0000\narc: N1_V01N0001 F3\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R22C70:PLC2\narc: E1_H02E0301 N3_V06S0003\narc: S1_V02S0201 H06E0103\narc: S3_V06S0303 H06E0303\narc: S3_V06S0003 W3_H06E0003\n\n.tile R22C7:PLC2\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0701 S3_V06N0203\narc: H00L0000 E1_H02W0201\narc: H00L0100 H02E0101\narc: H00R0000 S1_V02N0601\narc: H00R0100 H02E0501\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0201 S3_V06N0103\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 S1_V02N0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02S0401\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 S1_V02N0401\narc: W3_H06W0203 S3_V06N0203\narc: A1 E1_H01E0001\narc: A5 V02N0101\narc: A6 E1_H02W0701\narc: B1 H02W0301\narc: B4 H02W0101\narc: B5 V02N0701\narc: B6 H02E0301\narc: C1 V02S0601\narc: C4 V00B0100\narc: C5 V00B0100\narc: C6 H02W0401\narc: C7 V02N0201\narc: CE1 H00R0000\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D4 H02E0201\narc: D5 H02W0201\narc: D6 H00L0100\narc: D7 H00R0100\narc: E1_H01E0001 F6\narc: E1_H02E0401 Q4\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: H01W0100 F7\narc: M0 V00B0000\narc: M2 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F5\narc: N1_V02N0001 F0\narc: N1_V02N0601 F4\narc: V01S0000 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000101000101010\nword: SLICED.K1.INIT 0000000000001111\nword: SLICEC.K0.INIT 0000110011111100\nword: SLICEC.K1.INIT 1100010000000100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R22C8:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0203 N3_V06S0203\narc: H00R0000 H02W0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02W0601\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 V02S0101\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: B5 S1_V02N0701\narc: C5 S1_V02N0001\narc: CE0 H00R0100\narc: CE2 H00R0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D5 H02E0201\narc: F5 F5_SLICE\narc: M0 V00B0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V02N0701 Q5\narc: W1_H02W0001 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000110011111100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R22C9:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 V02N0101\narc: H00R0100 V02N0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 H06W0003\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 H06W0303\narc: V00B0000 H02W0601\narc: V00B0100 H02E0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 H01E0001\narc: W1_H02W0501 V06N0303\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 V02N0701\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q0\narc: E1_H02E0201 Q2\narc: E1_H02E0401 Q4\narc: E3_H06E0303 Q6\narc: M0 V00B0100\narc: M2 H02E0601\narc: M4 H02E0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: S1_V02S0401 Q4\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R23C10:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 V01N0101\narc: E3_H06E0203 N1_V01S0000\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 S3_V06N0303\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0701 H02E0701\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0203\narc: V00T0000 H02W0201\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V02N0601\narc: A0 V02N0701\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 V01S0000\narc: B6 V00B0000\narc: B7 V00B0100\narc: CE1 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q3\narc: E1_H02E0601 Q4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: LSR1 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: S1_V02S0001 Q2\narc: S1_V02S0401 Q6\narc: V00B0000 Q6\narc: V00B0100 Q7\narc: V01S0000 Q5\narc: V01S0100 Q7\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R23C11:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 N3_V06S0303\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02W0701\narc: V00T0100 N1_V02S0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0201 V02N0201\narc: W1_H02W0701 S1_V02N0701\narc: A6 N1_V01S0100\narc: B0 V00T0000\narc: B1 H00R0100\narc: B4 H02E0101\narc: B6 V00B0100\narc: C4 V00T0000\narc: C5 E1_H01E0101\narc: C6 H02W0401\narc: C7 V00T0100\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 H00L0100\narc: D6 V02N0601\narc: D7 V02N0601\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q5\narc: E3_H06E0203 F7\narc: E3_H06E0303 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H00R0100 Q5\narc: H01W0000 Q5\narc: H01W0100 Q5\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q5\narc: N3_V06N0203 F7\narc: N3_V06N0303 F6\narc: S1_V02S0401 F4\narc: V00T0000 Q0\narc: V01S0100 Q5\nword: SLICED.K0.INIT 1010110000000000\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 1111111111110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R23C12:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 N1_V02S0401\narc: E3_H06E0203 H01E0001\narc: H00L0000 W1_H02E0001\narc: H00R0100 H02W0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 H06E0303\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02N0001\narc: V00B0100 H02E0501\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0701 E1_H02W0701\narc: W3_H06W0103 N3_V06S0103\narc: W3_H06W0203 E3_H06W0103\narc: A2 S1_V02N0701\narc: A5 N1_V02S0301\narc: B1 H02E0301\narc: B2 H00L0000\narc: B5 V02N0501\narc: B6 H01E0101\narc: B7 H02E0101\narc: C0 H00L0100\narc: C1 N1_V02S0401\narc: C2 N1_V02S0401\narc: C3 H02E0601\narc: C5 N1_V02S0201\narc: C6 W1_H02E0601\narc: C7 V00T0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 E1_H02W0201\narc: D2 V00B0100\narc: D3 V00B0100\narc: D5 V02S0401\narc: D6 V02N0401\narc: D7 V00B0000\narc: E1_H01E0001 F7\narc: E1_H01E0101 F2\narc: E1_H02E0701 F7\narc: E3_H06E0003 F3\narc: E3_H06E0103 F2\narc: E3_H06E0303 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0000 Q7\narc: H01W0100 F6\narc: LSR0 H02W0301\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F3\narc: N1_V02N0301 F1\narc: N3_V06N0003 F0\narc: S3_V06S0203 F7\narc: V01S0100 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1001000000001001\nword: SLICEA.K0.INIT 0000111100000000\nword: SLICEA.K1.INIT 0011000000111111\nword: SLICEB.K0.INIT 1100101000000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 1111110000110000\nword: SLICED.K1.INIT 1100110011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R23C13:PLC2\narc: E1_H02E0201 V01N0001\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V02S0601\narc: E3_H06E0003 H01E0001\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 V02S0201\narc: H00R0000 V02N0401\narc: H00R0100 V02N0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 H06W0003\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 V02S0101\narc: V00T0100 V02N0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 N1_V02S0701\narc: A2 V01N0101\narc: A3 V00T0000\narc: A5 S1_V02N0301\narc: A6 N1_V02S0101\narc: A7 N1_V01S0100\narc: B2 E1_H02W0101\narc: B3 H00R0000\narc: B5 H00L0000\narc: B6 S1_V02N0701\narc: B7 S1_V02N0501\narc: C2 V02S0401\narc: C3 E1_H02W0601\narc: C5 E1_H02W0401\narc: C6 H02E0401\narc: C7 H02E0401\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 V02N0001\narc: D3 H02W0001\narc: D5 H00L0100\narc: D6 H02E0201\narc: D7 H02E0201\narc: E1_H01E0001 F4\narc: E1_H01E0101 F2\narc: E1_H02E0401 F6\narc: E3_H06E0303 F6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: LSR0 V00T0100\narc: M0 V00B0100\narc: M4 E1_H01E0101\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F7\narc: V00T0000 Q0\narc: V01S0000 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1010110000000000\nword: SLICED.K1.INIT 1010110000000000\nword: SLICEB.K0.INIT 1001000000001001\nword: SLICEB.K1.INIT 1000001001000001\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1011000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R23C14:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 N3_V06S0203\narc: H00R0000 N1_V02S0401\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 H06W0103\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 H06W0003\narc: S3_V06S0303 H06W0303\narc: V00B0100 H02W0701\narc: V00T0000 V02N0401\narc: V00T0100 H02W0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V01N0001\narc: W1_H02W0701 S1_V02N0701\narc: A3 H02E0501\narc: A6 H00L0000\narc: A7 H00L0000\narc: B3 V02N0301\narc: B6 H02W0301\narc: B7 V00B0000\narc: C3 V02S0601\narc: C6 V02S0001\narc: C7 V00T0100\narc: CE0 H00R0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: D6 H02E0201\narc: D7 E1_H01W0100\narc: E1_H01E0001 F7\narc: E1_H01E0101 F6\narc: E3_H06E0003 F3\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00T0100\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: V00B0000 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0011111101011111\nword: SLICED.K0.INIT 1101000011011101\nword: SLICED.K1.INIT 1000110000100011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R23C15:PLC2\narc: E1_H02E0401 N1_V01S0000\narc: E3_H06E0003 V06S0003\narc: H00L0000 H02W0201\narc: H00R0000 H02W0601\narc: H00R0100 H02W0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 H06W0103\narc: S3_V06S0303 H06W0303\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02E0701\narc: V00T0000 H02W0201\narc: V00T0100 H02W0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 V02N0701\narc: A0 H00L0000\narc: A1 H00L0000\narc: A2 V00T0000\narc: A3 V00T0000\narc: A4 V00T0000\narc: A5 V02N0101\narc: A7 N1_V01N0101\narc: B0 V02N0301\narc: B1 V02N0301\narc: B2 V02N0301\narc: B3 V02N0301\narc: B4 N1_V02S0501\narc: B5 H02E0101\narc: B7 H02E0301\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 V00T0100\narc: C5 W1_H02E0601\narc: C7 E1_H01E0101\narc: CE0 N1_V02S0201\narc: CE1 N1_V02S0201\narc: CLK1 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 H02W0001\narc: D5 V00B0000\narc: D7 H02E0201\narc: E1_H01E0001 F3\narc: E1_H01E0101 F1\narc: E1_H02E0001 Q2\narc: E1_H02E0101 Q3\narc: E3_H06E0103 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: LSR0 H02W0301\narc: LSR1 V00B0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F0\narc: N1_V01N0101 Q1\narc: N1_V02N0201 Q0\narc: S1_V02S0001 Q0\narc: S1_V02S0101 Q3\narc: S1_V02S0201 F2\narc: V01S0000 F7\narc: V01S0100 Q2\narc: W1_H02W0001 Q0\narc: W1_H02W0101 Q3\narc: W1_H02W0301 Q1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000010000100001\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R23C16:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 H02E0001\narc: H00L0100 H02W0101\narc: H00R0000 V02N0601\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02S0001\narc: V00T0000 V02S0401\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V01N0101\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 N1_V02S0601\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: A0 H00L0000\narc: A3 V00B0000\narc: B0 V00T0000\narc: B3 V02N0301\narc: C0 V02S0601\narc: C3 H00L0100\narc: C4 H02W0601\narc: C5 V02N0001\narc: C6 W1_H02E0601\narc: C7 F6\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D3 H02W0201\narc: D4 H02W0001\narc: D5 H02W0001\narc: D6 V02N0401\narc: D7 N1_V02S0401\narc: E1_H01E0001 F5\narc: E1_H01E0101 F4\narc: E3_H06E0003 F0\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0100 F6\narc: LSR0 E1_H02W0301\narc: M0 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q6\narc: N1_V02N0601 F4\narc: N3_V06N0303 Q6\narc: S3_V06S0303 F6\narc: V00T0100 F3\narc: V01S0100 F6\narc: W1_H02W0401 Q6\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010000011000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0000111100000000\nword: SLICED.K1.INIT 1111111111110000\nword: SLICEA.K0.INIT 0101111100111111\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R23C17:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 V02S0201\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0103 N3_V06S0103\narc: E3_H06E0303 N3_V06S0303\narc: H00L0000 H02W0001\narc: H00R0100 H02E0701\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H01E0101\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0401\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0601 E1_H02W0301\narc: E1_H02E0401 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0103 N3_V06S0103\narc: W3_H06W0303 N3_V06S0303\narc: W3_H06W0003 E3_H06W0003\narc: A0 H00L0000\narc: A1 H00R0000\narc: B0 V00B0000\narc: B1 V00T0000\narc: B5 V00B0100\narc: C0 H00R0100\narc: C1 N1_V01S0100\narc: C5 V02S0001\narc: CE1 N1_V02S0201\narc: CE2 S1_V02N0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 H02E0201\narc: D4 V02S0401\narc: D5 V02N0601\narc: E1_H01E0001 Q5\narc: E1_H01E0101 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0000 Q6\narc: H01W0000 Q5\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M2 V00B0000\narc: M6 H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q5\narc: N3_V06N0303 Q5\narc: V00B0100 Q5\narc: V00T0000 Q2\narc: V01S0000 F1\narc: V01S0100 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 0011110011001100\nword: SLICEA.K0.INIT 1000001001000001\nword: SLICEA.K1.INIT 1000010000100001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R23C18:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 V02N0501\narc: H00L0000 W1_H02E0001\narc: H00L0100 N1_V02S0301\narc: H00R0000 N1_V02S0601\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0401 H02W0401\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 N1_V02S0101\narc: V00T0000 N1_V02S0601\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 V02S0401\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0701 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A0 H02W0701\narc: A1 H02W0701\narc: A2 H02W0701\narc: A3 H02W0701\narc: A4 H02W0701\narc: A5 V02S0101\narc: A7 V00T0100\narc: B0 V00T0000\narc: B1 V00T0000\narc: B2 H00R0000\narc: B3 H00R0000\narc: B4 H00L0000\narc: B5 N1_V02S0701\narc: B7 V00B0100\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 H01E0001\narc: C5 V02N0001\narc: C7 E1_H01E0101\narc: CE0 V02S0201\narc: CE1 V02S0201\narc: CLK1 G_HPBX0000\narc: D0 H02E0001\narc: D1 H02E0001\narc: D2 H02E0001\narc: D3 H02E0001\narc: D4 H02E0201\narc: D5 E1_H01W0100\narc: D7 V02S0601\narc: E1_H01E0101 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q2\narc: LSR0 H02E0501\narc: LSR1 H02W0501\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q3\narc: N1_V02N0001 F2\narc: N1_V02N0301 Q1\narc: N3_V06N0003 Q0\narc: S1_V02S0001 Q0\narc: S3_V06S0003 Q3\narc: V00T0100 Q3\narc: V01S0000 F7\narc: V01S0100 Q1\narc: W1_H02W0001 Q0\narc: W1_H02W0201 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000110010101111\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R23C19:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0203 S3_V06N0203\narc: H00L0100 H02W0301\narc: H00R0000 H02W0601\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 H01E0001\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 H01E0001\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 H06W0303\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02W0701\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 V02N0701\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: N3_V06N0303 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A0 V02N0701\narc: A1 V02N0701\narc: A2 V02N0701\narc: A3 V02N0701\narc: A4 E1_H02W0701\narc: A5 V02S0101\narc: A7 V00T0100\narc: B0 H02W0101\narc: B1 H02W0101\narc: B2 H02W0101\narc: B3 H02W0101\narc: B4 N1_V02S0701\narc: B5 N1_V02S0501\narc: B7 V00T0000\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V00B0100\narc: C5 V02N0001\narc: C7 H02E0401\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CLK1 G_HPBX0000\narc: D0 H02W0201\narc: D1 H02W0201\narc: D2 H02W0201\narc: D3 H02W0201\narc: D4 V02S0401\narc: D5 V02N0601\narc: D7 F2\narc: E1_H01E0001 Q1\narc: E1_H01E0101 Q1\narc: E1_H02E0201 Q2\narc: E1_H02E0301 Q3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: LSR0 H02E0501\narc: LSR1 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F3\narc: N1_V01N0101 F0\narc: N1_V02N0501 F7\narc: S1_V02S0301 Q3\narc: V00T0000 Q2\narc: V00T0100 Q1\narc: V01S0000 Q2\narc: V01S0100 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000010000100001\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R23C20:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0401 W1_H02E0101\narc: H00L0100 N1_V02S0301\narc: H00R0100 V02S0701\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 H02E0701\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 H01E0001\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02N0201\narc: V00B0100 V02S0101\narc: V00T0000 H02W0201\narc: V00T0100 N1_V02S0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0301 W3_H06E0003\narc: A0 V02N0701\narc: A1 V02N0701\narc: A2 V02N0701\narc: A3 V02N0701\narc: A4 H02W0701\narc: A5 V00T0000\narc: B0 V02N0101\narc: B1 V02N0101\narc: B2 V02N0101\narc: B3 V02N0101\narc: B4 V02S0501\narc: B5 V02N0701\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V00T0100\narc: C5 V02S0001\narc: CE0 V02S0201\narc: CE1 V02S0201\narc: CE3 H02W0101\narc: CLK1 G_HPBX0000\narc: D0 N1_V02S0201\narc: D1 N1_V02S0201\narc: D2 N1_V02S0201\narc: D3 N1_V02S0201\narc: D4 N1_V02S0401\narc: D5 H00R0100\narc: E1_H01E0001 Q1\narc: E1_H01E0101 Q1\narc: E1_H02E0101 Q1\narc: E1_H02E0201 Q2\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q2\narc: LSR0 H02E0501\narc: LSR1 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXCLK3 CLK1\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F2\narc: N1_V01N0101 Q0\narc: N1_V02N0001 F0\narc: N1_V02N0101 F1\narc: S1_V02S0001 Q0\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R23C21:PLC2\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0203 N1_V01S0000\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0103 H06E0103\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0501 E1_H01W0100\narc: S3_V06S0003 H06W0003\narc: V00B0000 W1_H02E0401\narc: V00T0100 H02E0101\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 V06S0203\narc: W1_H02W0701 V02N0701\narc: E3_H06E0103 W3_H06E0003\narc: A5 S1_V02N0301\narc: A7 H00L0000\narc: B5 W1_H02E0101\narc: B7 V00T0000\narc: C4 V00B0100\narc: C5 E1_H01E0101\narc: C7 H01E0001\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CLK0 G_HPBX0000\narc: D4 V02N0401\narc: D5 V02N0601\narc: D7 H02E0201\narc: E1_H01E0101 F7\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 V00B0000\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: N3_V06N0203 F4\narc: N3_V06N0303 F5\narc: V00B0100 F5\narc: V00T0000 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000010000100001\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 1101000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R23C22:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0203 V01N0001\narc: H00L0100 V02N0101\narc: H00R0100 V02N0701\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 V01N0101\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H06W0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 S1_V02N0401\narc: V00T0100 H02W0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V02N0601\narc: N1_V02N0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A4 N1_V01N0101\narc: B4 S1_V02N0501\narc: C4 H02E0401\narc: C5 V00B0100\narc: CE0 H00R0100\narc: CE1 H00L0100\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D4 V02N0401\narc: D5 N1_V02S0401\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q5\narc: E1_H02E0401 Q4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: M0 V00T0100\narc: M2 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q5\narc: S1_V02S0501 Q5\narc: S3_V06S0103 Q2\narc: S3_V06S0203 Q4\narc: V01S0100 Q0\narc: W3_H06W0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1110101011000000\nword: SLICEC.K1.INIT 1111000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R23C23:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 H01E0101\narc: H00L0000 N1_V02S0001\narc: H00L0100 V02N0301\narc: H00R0000 H02W0601\narc: H00R0100 V02S0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 H02E0701\narc: S3_V06S0203 N3_V06S0103\narc: V00B0100 V02S0101\narc: V00T0000 V02N0401\narc: V00T0100 E1_H02W0101\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 V02N0601\narc: S1_V02S0101 W3_H06E0103\narc: S1_V02S0501 W3_H06E0303\narc: S3_V06S0103 W3_H06E0103\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A5 V00T0000\narc: A7 N1_V01N0101\narc: B3 H01W0100\narc: B5 H02E0101\narc: B6 V00B0100\narc: B7 V01S0000\narc: C2 H00L0000\narc: C3 N1_V01N0001\narc: C5 V00T0100\narc: C6 E1_H02W0401\narc: C7 E1_H01E0101\narc: CE0 H00L0100\narc: CLK0 G_HPBX0000\narc: D2 H00R0000\narc: D3 E1_H02W0201\narc: D5 H00R0100\narc: D6 H02W0201\narc: D7 E1_H02W0001\narc: E1_H01E0001 F7\narc: E1_H02E0001 Q0\narc: E1_H02E0101 F3\narc: E3_H06E0003 F3\narc: E3_H06E0203 F4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F6\narc: M0 H02E0601\narc: M4 H02W0401\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F2\narc: N1_V01N0101 F2\narc: S3_V06S0003 F3\narc: V01S0000 F6\narc: V01S0100 F3\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0011000000000000\nword: SLICED.K1.INIT 0000000000010101\nword: SLICEB.K0.INIT 0000000000001111\nword: SLICEB.K1.INIT 0000001100001111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R23C24:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 S3_V06N0103\narc: H00R0100 V02S0701\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0601 H02E0601\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 E3_H06W0103\narc: V00B0100 N1_V02S0301\narc: V00T0100 H02W0301\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 V06S0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: A1 E1_H01E0001\narc: A4 V02N0301\narc: A6 H02E0501\narc: B0 H01W0100\narc: B1 H00R0100\narc: B2 H01W0100\narc: B3 H00R0000\narc: B4 V02S0501\narc: B5 E1_H02W0101\narc: B6 V01S0000\narc: B7 E1_H02W0101\narc: C0 H00L0100\narc: C1 E1_H02W0401\narc: C2 V02S0401\narc: C3 V02N0601\narc: C4 V00B0100\narc: C5 H01E0001\narc: C6 E1_H01E0101\narc: C7 H01E0001\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 V02S0001\narc: D2 V00T0100\narc: D3 V02S0001\narc: D4 V02S0601\narc: D5 W1_H02E0001\narc: D6 H00R0100\narc: D7 W1_H02E0001\narc: E1_H01E0001 F0\narc: E1_H01E0101 F7\narc: E1_H02E0001 F2\narc: E1_H02E0201 F2\narc: E1_H02E0501 F7\narc: E1_H02E0701 F5\narc: E3_H06E0203 F7\narc: E3_H06E0303 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: H00R0000 F6\narc: H01W0000 F7\narc: H01W0100 Q3\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F5\narc: N1_V01N0101 F4\narc: N1_V02N0701 F7\narc: S3_V06S0203 F7\narc: S3_V06S0303 F5\narc: V01S0000 Q1\narc: V01S0100 Q3\narc: W3_H06W0203 F7\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0011000000000000\nword: SLICEB.K1.INIT 1111000000110011\nword: SLICED.K0.INIT 0011001111110101\nword: SLICED.K1.INIT 0000000000110000\nword: SLICEC.K0.INIT 0011111100110101\nword: SLICEC.K1.INIT 1111000011000000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111000011101110\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R23C25:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 H02E0201\narc: H00R0000 H02W0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 V01N0101\narc: S1_V02S0001 V01N0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 H06W0303\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02S0401\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 V06S0303\narc: S1_V02S0101 W3_H06E0103\narc: W3_H06W0203 V06S0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A2 H00L0100\narc: A3 W1_H02E0701\narc: A5 E1_H02W0701\narc: B2 H00R0000\narc: B3 H00R0100\narc: B5 H02E0101\narc: B6 N1_V01S0000\narc: B7 H02E0301\narc: C2 H00L0000\narc: C3 V02S0601\narc: C5 V00T0000\narc: C6 E1_H01E0101\narc: C7 V02S0001\narc: CE0 V02N0201\narc: CLK0 G_HPBX0000\narc: D2 V01S0100\narc: D3 S1_V02N0201\narc: D5 V02N0601\narc: D6 N1_V02S0601\narc: D7 V00B0000\narc: E1_H01E0001 F2\narc: E1_H01E0101 F7\narc: E1_H02E0001 Q0\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: M0 E1_H02W0601\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F4\narc: N1_V02N0501 F7\narc: S1_V02S0301 Q3\narc: S3_V06S0003 Q3\narc: V01S0100 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0011000000000000\nword: SLICED.K1.INIT 1111000011000000\nword: SLICEB.K0.INIT 0000111100001000\nword: SLICEB.K1.INIT 1110101011000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011001101111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R23C26:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V06N0303\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 V06N0003\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 V02N0001\narc: H00R0100 V02S0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 H06W0103\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 V02N0301\narc: V00T0100 V02N0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 V01N0001\narc: H01W0000 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: A0 V01N0101\narc: A3 V00B0000\narc: A6 V02S0301\narc: A7 H02E0501\narc: B0 H02E0101\narc: B1 V00T0000\narc: B3 N1_V02S0101\narc: B4 H02W0301\narc: B6 V02N0501\narc: B7 H02E0301\narc: C0 H02W0401\narc: C1 N1_V01S0100\narc: C3 H00L0000\narc: C4 N1_V02S0001\narc: C6 H02E0401\narc: C7 F6\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 V02N0201\narc: D3 S1_V02N0001\narc: D4 V02S0401\narc: D5 E1_H02W0201\narc: D6 H00R0100\narc: D7 H00L0100\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q4\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: V00B0000 Q4\narc: V00T0000 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0001001101011111\nword: SLICED.K1.INIT 0111000000000000\nword: SLICEA.K0.INIT 0001001101011111\nword: SLICEA.K1.INIT 1100000000000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R23C27:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 H01E0001\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0201\narc: V00B0100 H02W0501\narc: V00T0000 E1_H02W0201\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 N1_V01S0000\narc: E1_H02E0101 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: B2 H01W0100\narc: B4 H00R0000\narc: B6 V01S0000\narc: C2 E1_H02W0401\narc: C4 E1_H02W0401\narc: C6 N1_V02S0201\narc: CE0 V02N0201\narc: CLK0 G_HPBX0000\narc: D2 H02E0001\narc: D3 E1_H02W0001\narc: D4 H02E0201\narc: D5 E1_H02W0001\narc: D6 N1_V02S0401\narc: D7 H02W0001\narc: E1_H01E0101 Q4\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 Q4\narc: H01W0100 Q2\narc: M0 H02E0601\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0201 Q0\narc: V01S0000 Q6\narc: V01S0100 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R23C28:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 V06S0203\narc: E3_H06E0203 W1_H02E0401\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02S0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 V01N0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 V02S0001\narc: V00B0100 N1_V02S0301\narc: V00T0100 V02S0701\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 V06N0303\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0401 W3_H06E0203\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: A0 E1_H01E0001\narc: A1 H00L0000\narc: A4 W1_H02E0701\narc: A6 V00T0100\narc: A7 V02N0101\narc: B0 H02W0301\narc: B1 S1_V02N0101\narc: B2 V02S0101\narc: B3 H00R0000\narc: B4 H01E0101\narc: B6 V01S0000\narc: B7 V02S0501\narc: C0 E1_H02W0601\narc: C1 V02S0401\narc: C2 E1_H02W0401\narc: C3 H02W0601\narc: C4 S1_V02N0201\narc: C5 V00B0100\narc: C6 E1_H01E0101\narc: C7 E1_H02W0401\narc: CE0 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 S1_V02N0001\narc: D2 E1_H02W0201\narc: D3 V02N0001\narc: D4 H00L0100\narc: D5 H00R0100\narc: D6 F2\narc: D7 V00B0000\narc: E1_H01E0001 Q1\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: H01W0100 F1\narc: LSR0 E1_H02W0301\narc: M2 E1_H02W0601\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F5\narc: S1_V02S0701 F5\narc: S3_V06S0303 F5\narc: V01S0000 F7\narc: V01S0100 F4\narc: W1_H02W0701 F5\narc: W3_H06W0103 F1\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 1011001100000000\nword: SLICEA.K1.INIT 0111000001111100\nword: SLICEB.K0.INIT 1111001111111111\nword: SLICEB.K1.INIT 1100000011110000\nword: SLICED.K0.INIT 0000111000000000\nword: SLICED.K1.INIT 1111001101010011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R23C29:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 V06S0303\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 W1_H02E0201\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 W1_H02E0701\narc: V00T0100 V02N0701\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 E1_H01W0000\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0001 W3_H06E0003\narc: S1_V02S0101 W3_H06E0103\narc: S3_V06S0003 W3_H06E0003\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A5 V00T0000\narc: A6 E1_H02W0701\narc: B2 H00L0000\narc: B5 N1_V02S0501\narc: B6 V02S0501\narc: B7 V01S0000\narc: C2 W1_H02E0401\narc: C3 N1_V02S0601\narc: C5 V00B0100\narc: C6 E1_H02W0401\narc: C7 V02S0001\narc: CE0 H02E0101\narc: CE1 S1_V02N0201\narc: CLK0 G_HPBX0000\narc: D2 E1_H02W0001\narc: D3 W1_H02E0201\narc: D5 V02N0601\narc: D6 V00B0000\narc: D7 W1_H02E0001\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: H01W0100 Q2\narc: LSR1 H02W0301\narc: M0 E1_H02W0601\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: N1_V01N0101 F5\narc: V00T0000 Q0\narc: V01S0000 F6\narc: W1_H02W0001 F2\narc: W1_H02W0701 F7\narc: W3_H06W0103 F2\narc: W3_H06W0203 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0100010000000100\nword: SLICED.K1.INIT 0000000000000011\nword: SLICEB.K0.INIT 0000110011001100\nword: SLICEB.K1.INIT 0000111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R23C2:PLC2\narc: E1_H02E0201 E1_H01W0000\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 H02W0201\narc: S3_V06S0203 N3_V06S0103\n\n.tile R23C30:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 E3_H06W0003\narc: E3_H06E0003 V01N0001\narc: H00L0100 H02W0301\narc: H00R0000 W1_H02E0401\narc: H00R0100 H02W0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H06W0303\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 N1_V02S0301\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 V02S0001\narc: V00B0100 V02N0301\narc: V00T0000 V02S0601\narc: V00T0100 H02W0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 N1_V01S0000\narc: N1_V02N0601 W3_H06E0303\narc: S3_V06S0203 W3_H06E0203\narc: S3_V06S0303 W3_H06E0303\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 N1_V01S0100\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A0 V02S0701\narc: A1 H00L0000\narc: A4 H02E0501\narc: A5 W1_H02E0701\narc: B0 N1_V02S0101\narc: B1 W1_H02E0301\narc: B2 V02N0101\narc: B4 V02N0701\narc: B5 V02S0701\narc: C0 E1_H02W0601\narc: C1 N1_V01S0100\narc: C2 H00L0100\narc: C4 S1_V02N0201\narc: C5 V02S0201\narc: CE0 H02W0101\narc: CE2 H02W0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 H02E0001\narc: D2 H00R0000\narc: D3 N1_V02S0001\narc: D4 V00B0000\narc: D5 S1_V02N0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q4\narc: E1_H02E0601 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0000 Q0\narc: H01W0000 Q0\narc: H01W0100 Q4\narc: M2 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q0\narc: S1_V02S0601 Q6\narc: V01S0100 Q2\narc: W1_H02W0001 Q0\narc: W1_H02W0201 Q0\narc: W1_H02W0401 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1010000010100011\nword: SLICEC.K1.INIT 0000111101000100\nword: SLICEA.K0.INIT 1111110011101100\nword: SLICEA.K1.INIT 1110111111100101\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R23C31:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 W1_H02E0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00T0000 V02N0401\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 H01E0101\narc: E1_H01E0001 W3_H06E0003\narc: H01W0000 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: W3_H06W0203 N3_V06S0203\narc: E3_H06E0203 W3_H06E0203\narc: A0 V02S0701\narc: A2 H02W0501\narc: A3 N1_V02S0501\narc: A4 V00B0000\narc: A5 V00T0000\narc: A6 N1_V01S0100\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: S1_V02S0301 F3\narc: S1_V02S0501 F5\narc: S3_V06S0003 F3\narc: S3_V06S0303 F6\narc: V01S0000 F4\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R23C32:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 E1_H01W0100\narc: E3_H06E0003 N3_V06S0003\narc: H00L0000 W1_H02E0001\narc: H00L0100 H02E0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N1_V02S0401\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 H02E0401\narc: V00B0100 H02W0701\narc: V00T0000 S1_V02N0401\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 V06N0003\narc: W1_H02W0201 V06N0103\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 E1_H02W0301\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: H01W0000 W3_H06E0103\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A3 V00B0000\narc: A4 S1_V02N0301\narc: A7 E1_H02W0501\narc: B3 H02W0301\narc: B4 H00L0000\narc: B7 H02W0101\narc: C3 H00L0100\narc: C4 V00T0000\narc: C7 S1_V02N0001\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: D4 E1_H02W0201\narc: D7 H02W0001\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: LSR1 W1_H02E0301\narc: M2 N1_V01N0001\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F7\narc: N1_V02N0401 Q4\narc: N3_V06N0103 F2\narc: S3_V06S0203 F4\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0010101010101010\nword: SLICEC.K1.INIT 1111111111111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R23C33:PLC2\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0303 W1_H02E0601\narc: H00L0100 E1_H02W0301\narc: H00R0000 H02E0601\narc: H00R0100 N1_V02S0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0003 H06W0003\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0001\narc: V00B0100 E1_H02W0501\narc: V00T0000 V02N0401\narc: V00T0100 H02W0101\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 V01N0101\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 V02S0701\narc: E1_H02E0001 W3_H06E0003\narc: W3_H06W0003 E1_H02W0001\narc: A4 F5\narc: A5 V00B0000\narc: B4 H00R0000\narc: B5 V02N0701\narc: C4 V02S0001\narc: C5 V01N0101\narc: CE0 H00R0100\narc: CE1 H02E0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D4 H00L0100\narc: D5 V02S0601\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F5\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q2\narc: M0 V00T0100\narc: M2 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N3_V06N0203 F4\narc: N3_V06N0303 F5\narc: S1_V02S0701 F5\narc: V01S0000 Q2\narc: V01S0100 Q6\narc: W3_H06W0303 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0111000000000000\nword: SLICEC.K1.INIT 0000000000000001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R23C34:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 V06S0203\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0303 V06S0303\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 H02E0701\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H01E0101\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 S1_V02N0101\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0501 S1_V02N0501\narc: H01W0000 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: S1_V02S0201 W3_H06E0103\narc: W3_H06W0003 N3_V06S0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: A4 V00B0000\narc: B4 V01S0000\narc: C4 H01E0001\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D4 V02S0601\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q6\narc: F4 F5C_SLICE\narc: H01W0100 Q0\narc: M0 V00T0100\narc: M2 H02E0601\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0203 F4\narc: V00B0000 Q6\narc: V00T0000 Q0\narc: V01S0000 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R23C35:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0303 N3_V06S0303\narc: H00L0000 V02S0001\narc: H00R0000 H02E0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 E1_H01W0000\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 S1_V02N0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 V06S0303\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0701 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: B2 W1_H02E0301\narc: B3 W1_H02E0301\narc: C1 S1_V02N0601\narc: C2 V02S0401\narc: C3 H00L0000\narc: CE2 H00R0100\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 H02W0201\narc: D3 H00R0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 F2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0100 F1\narc: M4 V00B0000\narc: M6 H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F1\narc: V00B0000 Q6\narc: V01S0000 F1\narc: W1_H02W0401 Q4\narc: W3_H06W0003 F3\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001111\nword: SLICEB.K0.INIT 0011001100001111\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R23C36:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 V02S0501\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0203 V06N0203\narc: E3_H06E0303 W1_H02E0501\narc: H00L0100 V02S0101\narc: H00R0000 N1_V02S0401\narc: H00R0100 V02S0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H01E0001\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 H06E0303\narc: V00B0000 N1_V02S0201\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02S0601\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V06S0003\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0701 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\narc: A1 H02E0501\narc: B1 V02S0301\narc: C1 H00R0100\narc: CE1 H02W0101\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V01S0100\narc: E1_H01E0101 F0\narc: E3_H06E0003 F0\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: H01W0000 F0\narc: H01W0100 Q0\narc: M2 V00B0100\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0103 F1\narc: S3_V06S0203 Q4\narc: V01S0000 Q6\narc: W1_H02W0001 Q2\narc: W1_H02W0401 Q4\narc: W3_H06W0003 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 1000110010001000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\n\n.tile R23C37:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0103 W1_H02E0201\narc: H00L0000 W1_H02E0201\narc: H00L0100 W1_H02E0301\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 H01E0101\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 W1_H02E0601\narc: V00B0100 H02E0501\narc: V00T0100 V02N0501\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0701 V06S0203\narc: W3_H06W0003 E1_H02W0001\narc: E3_H06E0203 W3_H06E0203\narc: A3 H02E0701\narc: B3 H00R0100\narc: C3 H00L0100\narc: CE0 E1_H02W0101\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: E1_H01E0001 Q4\narc: E1_H01E0101 F1\narc: E1_H02E0401 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q6\narc: M0 E1_H02W0601\narc: M1 H02E0001\narc: M2 E1_H02W0601\narc: M4 V00B0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V02N0101 Q1\narc: N1_V02N0401 Q6\narc: N1_V02N0601 Q4\narc: N3_V06N0203 Q4\narc: V01S0000 Q1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111111111111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R23C38:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 H01E0001\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 N1_V01S0000\narc: H00L0100 N1_V02S0301\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 H01E0001\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: V00B0100 H02W0501\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: H01W0100 W3_H06E0303\narc: N1_V02N0201 W3_H06E0103\narc: B4 H02E0101\narc: C4 E1_H02W0401\narc: CE1 H02W0101\narc: CLK0 G_HPBX0000\narc: D4 H00L0100\narc: D6 H02W0201\narc: E1_H01E0101 F3\narc: E3_H06E0003 Q3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 E1_H02W0001\narc: M2 V00B0100\narc: M3 E1_H02W0201\narc: M4 V00B0100\narc: M5 E1_H02W0001\narc: M6 V00B0100\narc: MUXCLK1 CLK0\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 0011111111111111\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R23C39:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0103 H01E0101\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 E1_H02W0201\narc: H00L0100 S1_V02N0101\narc: H00R0100 V02S0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0003 H06E0003\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 V01N0101\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02E0601\narc: V00B0100 H02W0501\narc: V00T0000 W1_H02E0001\narc: V00T0100 H02W0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0501 N1_V02S0501\narc: A4 V00T0100\narc: A5 V02N0101\narc: B0 W1_H02E0301\narc: B1 W1_H02E0301\narc: B2 H02W0301\narc: B4 N1_V02S0501\narc: B5 S1_V02N0701\narc: B6 V00B0000\narc: C0 N1_V02S0401\narc: C1 H00L0000\narc: C2 N1_V01N0001\narc: C4 E1_H02W0601\narc: C5 S1_V02N0201\narc: C6 H02E0401\narc: CE0 H00R0100\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V02S0001\narc: D2 V02N0001\narc: D3 W1_H02E0201\narc: D4 H01W0000\narc: D5 S1_V02N0601\narc: D6 H02E0001\narc: D7 E1_H02W0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 F2\narc: E1_H02E0001 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F5\narc: M2 V00B0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V02N0201 Q2\narc: N3_V06N0103 Q2\narc: V01S0100 F6\narc: W1_H02W0001 Q0\narc: W1_H02W0601 F4\nword: SLICEC.K0.INIT 0011001100110010\nword: SLICEC.K1.INIT 1100010010000000\nword: SLICEA.K0.INIT 1100000011001111\nword: SLICEA.K1.INIT 0000000011111100\nword: SLICEB.K0.INIT 0000001111001111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1111000000110011\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R23C3:PLC2\narc: E1_H02E0001 V02N0001\narc: H00R0000 V02N0401\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0501 S1_V02N0401\narc: N3_V06N0003 S3_V06N0303\narc: S3_V06S0003 N3_V06S0303\narc: V00B0000 V02N0201\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0201 N1_V01S0000\narc: CE2 H02W0101\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 V00T0100\narc: D2 V01S0100\narc: D3 V00B0100\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q4\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R23C40:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V06N0103\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 N1_V01S0100\narc: E3_H06E0003 H01E0001\narc: E3_H06E0303 H01E0101\narc: H00L0100 W1_H02E0301\narc: H00R0000 N1_V02S0401\narc: H00R0100 H02E0501\narc: H01W0100 E3_H06W0303\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 S1_V02N0401\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0601\narc: V00T0000 V02S0401\narc: V00T0100 V02N0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V06S0003\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 N1_V02S0501\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0201 W3_H06E0103\narc: W1_H02W0401 W3_H06E0203\narc: A2 W1_H02E0501\narc: A4 V00T0000\narc: A5 H02W0501\narc: A6 V02N0301\narc: B0 F1\narc: B1 H01W0100\narc: B2 W1_H02E0101\narc: B3 H00R0100\narc: B4 H02W0301\narc: B5 H00R0000\narc: B6 E1_H02W0101\narc: B7 V02S0701\narc: C0 S1_V02N0401\narc: C1 V02N0401\narc: C2 V02N0601\narc: C3 H00L0000\narc: C4 V00B0100\narc: C5 E1_H01E0101\narc: C6 E1_H02W0401\narc: C7 E1_H02W0601\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 V02N0201\narc: D2 W1_H02E0201\narc: D3 F0\narc: D4 F0\narc: D5 E1_H02W0001\narc: D6 H00L0100\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: E1_H01E0101 F1\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F2\narc: H01W0000 F4\narc: MUXCLK3 CLK0\narc: N1_V02N0601 F6\narc: N3_V06N0203 Q7\narc: S3_V06S0103 F1\narc: V00B0000 F6\narc: V00B0100 F5\narc: W1_H02W0101 F3\narc: W1_H02W0201 F2\narc: W3_H06W0003 F3\narc: W3_H06W0103 F1\nword: SLICEA.K0.INIT 0011000000111111\nword: SLICEA.K1.INIT 0000000000001100\nword: SLICEC.K0.INIT 1111101101100010\nword: SLICEC.K1.INIT 1001010001001111\nword: SLICEB.K0.INIT 1100101000000000\nword: SLICEB.K1.INIT 1111000011110011\nword: SLICED.K0.INIT 1110010001000100\nword: SLICED.K1.INIT 1111000011110011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R23C41:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0003 V06S0003\narc: H00L0100 S1_V02N0301\narc: H00R0100 H02W0501\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 H01E0001\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 H06W0303\narc: V00B0100 H02W0701\narc: V00T0100 V02S0501\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0501 N1_V02S0501\narc: N1_V02N0601 W3_H06E0303\narc: S1_V02S0401 W3_H06E0203\narc: W3_H06W0203 V06N0203\narc: E3_H06E0303 W3_H06E0203\narc: A0 E1_H02W0501\narc: A1 N1_V02S0701\narc: A3 N1_V02S0501\narc: A5 N1_V02S0301\narc: B0 H02E0101\narc: B1 H00R0100\narc: B2 N1_V02S0101\narc: B3 H00R0100\narc: B5 H02E0301\narc: C0 H00L0100\narc: C1 H02E0401\narc: C2 N1_V01N0001\narc: C3 S1_V02N0401\narc: C5 V01N0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 S1_V02N0001\narc: D2 V02N0201\narc: D3 S1_V02N0201\narc: D5 E1_H02W0201\narc: E1_H01E0001 F0\narc: E1_H01E0101 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: H01W0000 F0\narc: H01W0100 F0\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F3\narc: N1_V01N0101 F1\narc: W1_H02W0601 F4\narc: W3_H06W0003 F0\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000011110011\nword: SLICEB.K1.INIT 1001010001001111\nword: SLICEA.K0.INIT 1010111100001100\nword: SLICEA.K1.INIT 1001010001001111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0110101110110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R23C42:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0203 H01E0001\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 H06W0203\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00B0100 H02E0701\narc: V00T0000 V02S0401\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V06N0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 V01N0101\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: H01W0000 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: N3_V06N0003 W3_H06E0003\narc: S3_V06S0003 W3_H06E0003\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: CE0 E1_H02W0101\narc: CE1 H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: E1_H02E0001 Q0\narc: H01W0100 Q6\narc: M0 V00B0100\narc: M2 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0201 Q2\narc: W3_H06W0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R23C43:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 V02S0601\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 W1_H02E0401\narc: H00L0000 E1_H02W0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 N1_V02S0401\narc: H00R0100 H02E0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 S1_V02N0401\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 H01E0101\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0601\narc: V00T0000 H02E0001\narc: V00T0100 W1_H02E0301\narc: W1_H02W0201 V02N0201\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0101 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A1 H00L0000\narc: A2 W1_H02E0501\narc: A3 V00T0000\narc: A4 W1_H02E0501\narc: A5 V00T0000\narc: A7 E1_H01W0000\narc: B1 V02S0301\narc: B2 H02W0301\narc: B3 V02N0301\narc: B4 H02W0301\narc: B5 V02N0701\narc: B7 V02S0701\narc: C1 V02N0401\narc: C2 V02S0401\narc: C3 N1_V02S0601\narc: C4 N1_V02S0201\narc: C5 S1_V02N0201\narc: C7 V00T0100\narc: D1 V00B0100\narc: D2 H02E0201\narc: D3 H00R0000\narc: D4 H00L0100\narc: D5 H00R0100\narc: D7 H01W0000\narc: E1_H01E0001 F0\narc: E1_H01E0101 F6\narc: E3_H06E0003 F0\narc: E3_H06E0303 F6\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00B0000\narc: M6 N1_V01N0101\narc: N1_V01N0101 F2\narc: N3_V06N0003 F0\narc: N3_V06N0303 F6\narc: V00B0000 F4\narc: V00B0100 F5\narc: V01S0100 F6\nword: SLICEC.K0.INIT 1000010000100001\nword: SLICEC.K1.INIT 1000001001000001\nword: SLICEB.K0.INIT 1000001001000001\nword: SLICEB.K1.INIT 1000001001000001\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000001000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000001000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R23C44:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 H01E0101\narc: H00R0100 W1_H02E0701\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H02W0301\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H06W0103\narc: S1_V02S0501 H06E0303\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 H02E0601\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0201 W3_H06E0103\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0103 V06N0103\narc: W3_H06W0303 E3_H06W0203\narc: A7 H02W0701\narc: B3 N1_V02S0301\narc: B4 E1_H02W0301\narc: B7 V00B0000\narc: C1 H00R0100\narc: C3 N1_V01N0001\narc: C4 V00B0100\narc: C5 V00T0000\narc: C6 W1_H02E0601\narc: C7 W1_H02E0601\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D3 H00R0000\narc: D4 V01N0001\narc: D5 N1_V02S0601\narc: D6 E1_H02W0201\narc: D7 E1_H02W0201\narc: E1_H01E0001 Q1\narc: E1_H01E0101 F3\narc: E1_H02E0501 F5\narc: E3_H06E0103 F1\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 F6\narc: H01W0000 Q1\narc: LSR1 W1_H02E0301\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F5\narc: N1_V01N0101 F1\narc: N3_V06N0303 F5\narc: S1_V02S0401 F4\narc: S3_V06S0103 F1\narc: S3_V06S0303 F5\narc: V00B0100 F5\narc: V01S0000 F1\narc: W1_H02W0101 F1\narc: W3_H06W0003 Q3\narc: W3_H06W0203 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100000011001111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEC.K0.INIT 1100000011001111\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 1110000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R23C45:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 V02S0601\narc: E3_H06E0003 V06N0003\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 W1_H02E0701\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 E1_H02W0101\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 W1_H02E0401\narc: V00B0100 H02W0501\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0001 H01E0001\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0701 E3_H06W0203\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0203 N3_V06S0203\narc: W3_H06W0303 E3_H06W0203\narc: A0 V02S0701\narc: A1 V02S0701\narc: A2 V02S0701\narc: A3 V02S0701\narc: A4 S1_V02N0301\narc: A5 V02N0101\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 V02N0501\narc: B7 V00T0000\narc: C0 N1_V01N0001\narc: C1 N1_V01N0001\narc: C2 N1_V01N0001\narc: C3 N1_V01N0001\narc: C4 S1_V02N0201\narc: C5 H02W0601\narc: C7 E1_H02W0401\narc: CLK1 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 V00T0100\narc: D3 V00T0100\narc: D4 V02N0401\narc: D5 H00L0100\narc: D7 S1_V02N0401\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: LSR1 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q2\narc: N3_V06N0203 F7\narc: S1_V02S0301 Q3\narc: V01S0000 Q1\narc: V01S0100 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R23C46:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 V01N0001\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0303 N3_V06S0303\narc: H00L0100 H02W0101\narc: H00R0100 V02S0701\narc: H01W0000 E3_H06W0103\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 H01E0101\narc: V00B0000 E1_H02W0601\narc: V00B0100 H02W0701\narc: V00T0000 S1_V02N0401\narc: V00T0100 E1_H02W0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 E1_H02W0301\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0501 W3_H06E0303\narc: S1_V02S0201 W3_H06E0103\narc: W3_H06W0003 E1_H02W0001\narc: W3_H06W0303 E1_H01W0100\narc: A0 H02W0501\narc: A1 H02W0501\narc: A2 H02W0501\narc: A3 H02W0501\narc: A4 V00T0000\narc: A5 E1_H02W0501\narc: B0 V02S0101\narc: B1 V02S0101\narc: B2 V02S0101\narc: B3 V02S0101\narc: B4 E1_H02W0101\narc: B5 V02S0701\narc: B6 H02E0101\narc: C0 V02S0601\narc: C1 V02S0601\narc: C2 V02S0601\narc: C3 V02S0601\narc: C4 V00B0100\narc: C5 V00T0100\narc: C6 V01N0101\narc: CLK1 G_HPBX0000\narc: D0 V02S0001\narc: D1 V02S0001\narc: D2 V02S0001\narc: D3 V02S0001\narc: D4 V02N0401\narc: D5 H00L0100\narc: D6 H00R0100\narc: D7 H02E0001\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: LSR1 H02W0301\narc: M6 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: S1_V02S0101 Q1\narc: S1_V02S0301 Q3\narc: V01S0100 Q0\nword: SLICED.K0.INIT 1111110000110000\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R23C47:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 H01E0101\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 V02S0601\narc: E3_H06E0303 W1_H02E0501\narc: H00L0100 V02N0301\narc: H00R0000 H02E0601\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0201\narc: V00T0000 V02N0401\narc: V00T0100 H02E0301\narc: V01S0100 N3_V06S0303\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V06S0303\narc: W1_H02W0701 N1_V02S0701\narc: S3_V06S0003 W3_H06E0003\narc: W3_H06W0003 N1_V01S0000\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A3 H00L0100\narc: B3 H02E0301\narc: B4 V02N0701\narc: B7 H02E0101\narc: C3 W1_H02E0601\narc: C4 H01E0001\narc: C5 V00T0000\narc: C6 V00B0100\narc: C7 V01N0101\narc: CE0 V02S0201\narc: CE2 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 V02N0201\narc: D4 W1_H02E0201\narc: D5 H02W0201\narc: D6 N1_V02S0401\narc: D7 W1_H02E0201\narc: E1_H01E0001 F1\narc: E1_H02E0701 F5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q1\narc: H01W0100 Q7\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F6\narc: N3_V06N0203 Q4\narc: V00B0100 Q7\narc: V01S0000 Q4\narc: W1_H02W0101 F1\narc: W3_H06W0103 F1\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1100111100000011\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1100000011001000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R23C48:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0201 H01E0001\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0003 V06N0003\narc: H00L0000 E1_H02W0201\narc: H00L0100 V02S0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02W0701\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 H06W0203\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0001\narc: V00T0000 H02W0201\narc: V00T0100 V02S0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V02N0601\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0301 W3_H06E0003\narc: S3_V06S0003 W3_H06E0003\narc: S3_V06S0203 W3_H06E0203\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: A3 E1_H02W0501\narc: A6 W1_H02E0701\narc: A7 V02N0301\narc: B0 V02S0101\narc: B3 E1_H02W0301\narc: B4 H02E0301\narc: B6 V02N0701\narc: B7 S1_V02N0701\narc: C0 H00L0100\narc: C2 H02E0601\narc: C3 H00L0000\narc: C4 W1_H02E0401\narc: C6 V00T0100\narc: C7 S1_V02N0001\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 W1_H02E0201\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 S1_V02N0601\narc: D5 W1_H02E0201\narc: D6 H01W0000\narc: D7 V00B0000\narc: E1_H01E0001 F0\narc: E1_H01E0101 F2\narc: E1_H02E0401 F4\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M0 H02W0601\narc: M2 V00T0000\narc: M4 E1_H02W0401\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q6\narc: N1_V02N0601 Q6\nword: SLICED.K0.INIT 0000000010110100\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0011001100001111\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 1110000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R23C49:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 N1_V02S0001\narc: H00L0100 E1_H02W0301\narc: H00R0100 H02E0701\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 W1_H02E0601\narc: V00B0100 N1_V02S0101\narc: V00T0000 N1_V02S0601\narc: V00T0100 V02S0701\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0701 E1_H02W0601\narc: E1_H01E0001 W3_H06E0003\narc: S1_V02S0501 W3_H06E0303\narc: S3_V06S0003 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0303 E3_H06W0203\narc: A1 H01E0001\narc: A5 S1_V02N0301\narc: A7 H02W0501\narc: B0 V00T0000\narc: B1 N1_V02S0101\narc: B2 H00R0100\narc: B4 H00L0000\narc: B5 V00B0100\narc: B7 H02W0301\narc: C0 E1_H01W0000\narc: C1 V02N0401\narc: C2 H02E0401\narc: C4 V02S0001\narc: C5 V02N0201\narc: C6 E1_H02W0401\narc: C7 E1_H02W0401\narc: CE0 H00L0100\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 H02E0201\narc: D2 H02E0201\narc: D3 F0\narc: D4 E1_H01W0100\narc: D5 V02N0601\narc: D6 V00B0000\narc: D7 V00B0000\narc: E1_H01E0101 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F5\narc: LSR1 H02E0301\narc: M2 H02E0601\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F1\narc: N1_V01N0101 F2\narc: S1_V02S0601 F4\narc: V01S0000 F6\narc: V01S0100 F0\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 1100000011001111\nword: SLICEC.K1.INIT 0011001000000010\nword: SLICEA.K0.INIT 1100110000001111\nword: SLICEA.K1.INIT 0011001000000010\nword: SLICEB.K0.INIT 0011000011111100\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1111000011111111\nword: SLICED.K1.INIT 1110000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R23C4:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 E1_H01W0000\narc: H00L0000 V02S0001\narc: H00L0100 V02N0101\narc: H00R0000 E1_H02W0401\narc: H00R0100 V02N0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0701 V01N0101\narc: S1_V02S0201 N3_V06S0103\narc: V00T0000 V02N0401\narc: V00T0100 V02N0501\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 S1_V02N0201\narc: A5 S1_V02N0301\narc: B1 V00B0000\narc: B5 H00R0000\narc: C0 S1_V02N0401\narc: C1 H00L0100\narc: C4 E1_H02W0401\narc: C5 E1_H02W0601\narc: CE2 H00L0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 V02N0201\narc: D4 V02N0601\narc: D5 N1_V02S0401\narc: E1_H01E0101 F1\narc: E3_H06E0203 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: M0 V00T0000\narc: M1 H02E0001\narc: M2 V00T0000\narc: M4 E1_H01E0101\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0401 F4\narc: N1_V02N0601 F4\narc: V00B0000 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111111110000\nword: SLICEC.K1.INIT 1010100000000000\nword: SLICEA.K0.INIT 1111111100001111\nword: SLICEA.K1.INIT 0011001100001111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R23C50:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 V06N0103\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 E1_H01W0000\narc: H00L0000 V02S0201\narc: H00R0000 V02S0601\narc: H00R0100 H02W0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02S0001\narc: V00B0100 H02E0501\narc: V00T0000 N1_V02S0601\narc: V00T0100 E1_H02W0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 E1_H01W0100\narc: N1_V02N0301 W3_H06E0003\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: A1 H00R0000\narc: A3 N1_V02S0701\narc: B1 V02S0301\narc: B3 V02S0301\narc: B4 H01E0101\narc: B6 V02N0701\narc: C0 H00L0000\narc: C1 H00L0000\narc: C2 E1_H02W0401\narc: C3 E1_H02W0401\narc: C4 V02N0201\narc: C6 V02N0001\narc: C7 E1_H01E0101\narc: CE2 H00R0100\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 H02W0201\narc: D2 V02S0201\narc: D3 V02S0201\narc: D4 W1_H02E0001\narc: D5 E1_H02W0201\narc: D6 E1_H02W0201\narc: D7 V00B0000\narc: E1_H01E0101 Q6\narc: E1_H02E0401 Q4\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: H01W0100 F0\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: N3_V06N0203 F7\narc: V01S0100 Q4\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1100111100000011\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 1111111111000000\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111111100001111\nword: SLICEA.K1.INIT 1110000000000000\nword: SLICEB.K0.INIT 1111000011111111\nword: SLICEB.K1.INIT 1110000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R23C51:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 S3_V06N0303\narc: H00L0100 H02E0101\narc: H00R0100 H02E0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 H02E0501\narc: V00T0000 V02S0401\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02S0701\narc: E1_H02E0601 W3_H06E0303\narc: S1_V02S0401 W3_H06E0203\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: C0 N1_V01S0100\narc: C1 H00L0100\narc: C2 V02N0601\narc: C3 H02W0601\narc: C6 V02N0001\narc: C7 H02E0401\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 V00B0100\narc: D2 V00B0100\narc: D3 V00B0100\narc: D6 H00R0100\narc: D7 H00R0100\narc: E1_H01E0001 F0\narc: E1_H02E0101 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q4\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F6\narc: N1_V02N0001 F2\narc: N1_V02N0301 F3\narc: N1_V02N0601 Q4\narc: V01S0000 Q4\narc: V01S0100 F7\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 0000111111110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R23C52:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 V02N0201\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 H02W0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 W1_H02E0601\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 H02E0101\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 W1_H02E0601\narc: W1_H02W0101 V02N0101\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 N3_V06S0203\narc: E1_H02E0301 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: A1 E1_H01E0001\narc: A3 V00T0000\narc: B0 V02N0301\narc: B1 V00B0000\narc: B3 H00R0000\narc: C0 H02E0401\narc: C1 H00L0000\narc: C3 H00L0000\narc: CE0 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 H02E0201\narc: D3 H02E0201\narc: E1_H01E0001 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: MUXCLK0 CLK0\narc: V00T0000 Q0\narc: W1_H02W0301 F3\narc: W3_H06W0103 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001111011111\nword: SLICEA.K0.INIT 0000110000001111\nword: SLICEA.K1.INIT 0100011101110111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R23C53:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 H02W0001\narc: H00L0100 E1_H02W0301\narc: H00R0100 V02N0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02W0601\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 V02N0201\narc: V00B0100 H02W0701\narc: V00T0000 V02N0401\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V02S0001\narc: E1_H02E0001 W3_H06E0003\narc: H01W0100 W3_H06E0303\narc: S1_V02S0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: A0 H00L0100\narc: A1 E1_H01E0001\narc: A3 V02S0501\narc: A5 N1_V01N0101\narc: A7 H00R0000\narc: B0 S1_V02N0101\narc: B1 H02W0301\narc: B3 S1_V02N0301\narc: B4 E1_H02W0301\narc: B5 V00B0100\narc: B7 V01S0000\narc: C0 H00R0100\narc: C1 V02N0401\narc: C3 V02N0401\narc: C4 W1_H02E0401\narc: C5 V00T0000\narc: C6 V02S0201\narc: C7 V00T0000\narc: CE0 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 V02S0001\narc: D3 V02S0001\narc: D4 V00B0000\narc: D5 V02S0601\narc: D6 H02W0201\narc: D7 V02S0601\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q6\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: V01S0000 Q0\narc: W1_H02W0101 F3\narc: W3_H06W0103 F1\narc: W3_H06W0203 F7\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0011010100111111\nword: SLICEC.K0.INIT 0000110000001111\nword: SLICEC.K1.INIT 0101001101011111\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 0011010100111111\nword: SLICEA.K0.INIT 0000000110101011\nword: SLICEA.K1.INIT 0011010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R23C54:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 N1_V02S0001\narc: H00L0100 W1_H02E0101\narc: H00R0000 W1_H02E0601\narc: H00R0100 V02N0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 H02E0001\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 H06E0203\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 W1_H02E0601\narc: V00T0000 V02S0601\narc: V00T0100 V02N0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0701 S1_V02N0701\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0501 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: N3_V06N0203 W3_H06E0203\narc: W1_H02W0501 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: A1 H02E0701\narc: A3 E1_H01E0001\narc: A5 N1_V01N0101\narc: A7 H02E0701\narc: B1 V00T0000\narc: B2 E1_H02W0301\narc: B3 E1_H02W0101\narc: B5 E1_H02W0101\narc: B6 E1_H02W0301\narc: B7 V00T0000\narc: C1 W1_H02E0601\narc: C2 H00L0100\narc: C3 V02S0601\narc: C5 V00T0000\narc: C6 H02E0401\narc: C7 W1_H02E0601\narc: CE1 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 W1_H02E0201\narc: D3 H00R0000\narc: D5 V00B0000\narc: D6 V02N0401\narc: D7 H00R0100\narc: E1_H01E0001 Q2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q6\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: V01S0100 F5\narc: W1_H02W0101 F1\narc: W3_H06W0003 F3\narc: W3_H06W0203 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000011111110111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011001101011111\nword: SLICEB.K0.INIT 0000110000001111\nword: SLICEB.K1.INIT 0101010100111111\nword: SLICED.K0.INIT 0000110000001111\nword: SLICED.K1.INIT 0101001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R23C55:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V02S0401\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 V02N0001\narc: H00L0100 V02N0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02S0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H06W0203\narc: V00B0000 V02S0201\narc: V00B0100 H02W0501\narc: V00T0000 H02E0001\narc: V00T0100 V02S0501\narc: W1_H02W0001 V06S0003\narc: W1_H02W0301 V02N0301\narc: E3_H06E0103 W3_H06E0103\narc: A0 H00L0100\narc: A1 E1_H01E0001\narc: A3 V02N0501\narc: A7 N1_V01N0101\narc: B0 H02E0101\narc: B1 V00B0000\narc: B2 V02N0301\narc: B3 V02S0301\narc: B4 V00B0100\narc: B6 H02W0301\narc: B7 V01S0000\narc: C0 S1_V02N0401\narc: C1 H02W0401\narc: C2 H00L0000\narc: C3 V02S0401\narc: C4 V00T0100\narc: C6 H02E0401\narc: C7 V02S0201\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 N1_V02S0001\narc: D1 H02E0201\narc: D2 E1_H02W0001\narc: D3 H02E0201\narc: D4 H00R0100\narc: D5 W1_H02E0201\narc: D6 E1_H02W0201\narc: D7 V02N0401\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: V01S0000 Q6\narc: V01S0100 Q6\narc: W3_H06W0003 F3\narc: W3_H06W0103 F1\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 0000110000001111\nword: SLICED.K1.INIT 0011001101011111\nword: SLICEB.K0.INIT 1100111100000011\nword: SLICEB.K1.INIT 0011001101011111\nword: SLICEA.K0.INIT 0101010011111110\nword: SLICEA.K1.INIT 0101010100111111\nword: SLICEC.K0.INIT 0000001111001111\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R23C56:PLC2\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 V06N0303\narc: H00L0000 H02W0201\narc: H00R0000 H02W0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02W0601\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N1_V02S0501\narc: V00B0100 V02N0301\narc: V00T0000 E1_H02W0201\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 E1_H02W0501\narc: N1_V02N0701 W3_H06E0203\narc: N3_V06N0003 W3_H06E0003\narc: W3_H06W0003 E1_H01W0000\narc: A1 H02W0501\narc: A5 W1_H02E0701\narc: A7 N1_V01N0101\narc: B0 V02N0301\narc: B1 V02S0301\narc: B3 H00R0100\narc: B5 N1_V01S0000\narc: B6 V00B0100\narc: B7 V00B0000\narc: C0 H00L0000\narc: C1 N1_V02S0401\narc: C3 V02S0601\narc: C5 V02S0001\narc: C6 V00T0000\narc: C7 N1_V02S0001\narc: CE0 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 H00R0000\narc: D3 H02E0201\narc: D5 V02N0401\narc: D6 H01W0000\narc: D7 V02N0401\narc: E1_H01E0001 F3\narc: E1_H01E0101 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: V00B0000 Q6\narc: W3_H06W0103 F1\narc: W3_H06W0203 F7\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000111101110111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100000011110011\nword: SLICEA.K0.INIT 0011111100001100\nword: SLICEA.K1.INIT 0011001101011111\nword: SLICED.K0.INIT 0000111100001100\nword: SLICED.K1.INIT 0011001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R23C57:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0401 V06N0203\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 V01N0101\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 E1_H02W0501\narc: V00T0000 V02S0601\narc: V00T0100 H02E0301\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0701 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: A5 N1_V01N0101\narc: A7 H00R0000\narc: B0 V02N0101\narc: B1 V00T0000\narc: B2 V02N0101\narc: B3 W1_H02E0101\narc: B4 E1_H02W0101\narc: B5 V01S0000\narc: B6 E1_H02W0101\narc: B7 V00B0000\narc: C0 H00L0100\narc: C1 E1_H02W0601\narc: C2 H02W0601\narc: C3 V02S0601\narc: C4 V00B0100\narc: C5 W1_H02E0401\narc: C6 E1_H02W0401\narc: C7 W1_H02E0401\narc: CE2 S1_V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 V00T0100\narc: D2 V01S0100\narc: D3 E1_H02W0001\narc: D4 V02S0401\narc: D5 V02N0401\narc: D6 E1_H02W0201\narc: D7 V02N0401\narc: E1_H01E0001 F3\narc: E1_H02E0201 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H00R0000 Q4\narc: H01W0000 F7\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F2\narc: N1_V01N0101 Q6\narc: S1_V02S0301 F3\narc: V00B0000 Q6\narc: V01S0000 Q4\narc: V01S0100 F1\narc: W3_H06W0303 F5\nword: SLICED.K0.INIT 1100000011110011\nword: SLICED.K1.INIT 0011001101011111\nword: SLICEA.K0.INIT 1111110000110000\nword: SLICEA.K1.INIT 0000110000111111\nword: SLICEC.K0.INIT 0000110000001111\nword: SLICEC.K1.INIT 0011001101011111\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 0011000000111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R23C58:PLC2\narc: H00L0100 V02S0301\narc: H00R0000 V02N0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 W1_H02E0201\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 H06E0303\narc: S1_V02S0201 H02E0201\narc: S1_V02S0701 H02E0701\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0001\narc: V00B0100 V02S0301\narc: V00T0000 V02N0601\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 H01E0001\narc: A4 V00T0000\narc: A5 V00T0100\narc: A7 V00T0100\narc: B0 H00R0100\narc: B1 V00T0000\narc: B3 H00R0000\narc: B4 N1_V02S0501\narc: B5 V02N0701\narc: B7 V02N0701\narc: C0 H00L0100\narc: C1 H00L0000\narc: C2 V02N0601\narc: C3 H00L0000\narc: C4 H02E0401\narc: C5 W1_H02E0401\narc: C7 W1_H02E0401\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 F0\narc: D2 V00B0100\narc: D3 V02S0001\narc: D4 V00B0000\narc: D5 V02N0401\narc: D7 V02N0401\narc: E1_H01E0001 F0\narc: E1_H01E0101 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F2\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q1\narc: N1_V02N0001 F2\narc: S3_V06S0103 F2\narc: V00T0100 Q3\narc: V01S0100 Q4\narc: W1_H02W0101 Q1\narc: W1_H02W0201 F2\narc: W3_H06W0103 F2\narc: W3_H06W0203 F7\narc: W3_H06W0303 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0101010100111111\nword: SLICEC.K0.INIT 0101010011111110\nword: SLICEC.K1.INIT 0011001101011111\nword: SLICEA.K0.INIT 1100000011110011\nword: SLICEA.K1.INIT 0000111100001100\nword: SLICEB.K0.INIT 0000000011110000\nword: SLICEB.K1.INIT 0000111100001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R23C59:PLC2\narc: E1_H02E0301 N3_V06S0003\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0303 S1_V02N0501\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 H01E0101\narc: S1_V02S0001 W3_H06E0003\narc: S3_V06S0003 W3_H06E0003\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\n\n.tile R23C5:PLC2\narc: E1_H02E0201 V02N0201\narc: H00L0100 V02N0101\narc: H00R0000 V02N0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 V01N0001\narc: S1_V02S0001 H06W0003\narc: S1_V02S0601 E1_H02W0601\narc: V00B0000 V02N0001\narc: V00T0100 H02W0301\narc: W1_H02W0201 E1_H02W0701\narc: CE2 H02E0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H00R0000\narc: D2 H02E0201\narc: D3 H02W0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q6\narc: M0 V00B0000\narc: M1 H00L0100\narc: M2 V00B0000\narc: M4 V00T0100\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: V01S0100 Q4\narc: W1_H02W0101 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R23C60:PLC2\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0601 H06E0303\narc: N1_V02N0101 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\n\n.tile R23C61:PLC2\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0501 H02W0501\narc: W1_H02W0501 W3_H06E0303\n\n.tile R23C62:PLC2\narc: S1_V02S0201 H06E0103\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: W1_H02W0501 N3_V06S0303\n\n.tile R23C63:PLC2\narc: S1_V02S0501 W3_H06E0303\narc: E3_H06E0303 W3_H06E0303\n\n.tile R23C64:PLC2\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0303 N3_V06S0203\n\n.tile R23C65:PLC2\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\narc: H01W0000 W3_H06E0103\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\n\n.tile R23C66:PLC2\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 N3_V06S0303\n\n.tile R23C68:PLC2\narc: S1_V02S0401 H06E0203\n\n.tile R23C69:PLC2\narc: S3_V06S0203 N3_V06S0203\n\n.tile R23C6:PLC2\narc: H00R0000 H02W0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 E1_H02W0301\narc: S3_V06S0203 E3_H06W0203\narc: V00T0000 V02N0401\narc: W1_H02W0001 V01N0001\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0601 V02N0601\narc: D0 S1_V02N0001\narc: D1 H02W0001\narc: D2 V02N0201\narc: D3 V02S0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H00R0000\narc: M2 V00T0000\narc: M3 H00R0100\narc: M4 V00T0000\narc: M5 H00R0000\narc: M6 V00T0000\narc: N1_V01N0001 F3\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R23C70:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0701 N3_V06S0203\n\n.tile R23C7:PLC2\narc: H00R0000 V02N0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 E1_H02W0701\narc: S3_V06S0203 N3_V06S0203\narc: V00B0100 E1_H02W0501\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02N0701\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 S3_V06N0203\narc: D0 V00T0100\narc: D1 V00B0100\narc: D2 H02W0001\narc: D3 E1_H02W0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00T0000\narc: M1 H00R0000\narc: M2 V00T0000\narc: M3 H00R0100\narc: M4 V00T0000\narc: M5 H00R0000\narc: M6 V00T0000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R23C8:PLC2\narc: E1_H02E0001 V02N0001\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 E1_H02W0601\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02S0101\narc: V00T0000 V02N0401\narc: V01S0000 N3_V06S0103\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V06S0003\narc: W3_H06W0003 V06S0003\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 S1_V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q6\narc: H01W0000 Q4\narc: M0 V00B0100\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W1_H02W0001 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R23C9:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0303 N1_V01S0100\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0501 N1_V02S0401\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02S0201\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0501 H01E0101\narc: W1_H02W0701 E1_H02W0701\narc: B7 V02S0701\narc: C7 V02N0201\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D7 H02E0001\narc: E1_H02E0201 Q0\narc: F7 F7_SLICE\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111111001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R24C10:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0701 V02N0701\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 H02W0001\narc: H00L0100 E1_H02W0101\narc: H00R0100 V02S0501\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 V02S0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0601 V02N0601\narc: B6 V00T0000\narc: B7 V00B0000\narc: C6 V02S0201\narc: C7 V02S0201\narc: CE0 H00R0100\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D6 W1_H02E0201\narc: D7 H00L0100\narc: E1_H01E0101 F6\narc: E1_H02E0001 Q2\narc: E1_H02E0601 Q4\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M0 V00B0100\narc: M2 V00T0100\narc: M4 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q0\narc: N1_V02N0001 Q2\narc: S1_V02S0701 F7\narc: V01S0100 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111110000001100\nword: SLICED.K1.INIT 1111110000001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R24C11:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0701 V06S0203\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 N1_V02S0001\narc: H00R0100 H02E0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 H06W0303\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 H01E0101\narc: S1_V02S0701 H06W0203\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0401 V02N0401\narc: A5 S1_V02N0301\narc: B0 N1_V02S0101\narc: B1 N1_V02S0101\narc: B2 N1_V02S0101\narc: B5 E1_H02W0101\narc: C0 H02E0401\narc: C1 V02S0601\narc: C2 H00R0100\narc: C3 N1_V01S0100\narc: C5 H02W0401\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02S0201\narc: D2 V02N0201\narc: D3 H02W0201\narc: D5 H02E0201\narc: E1_H01E0001 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q5\narc: LSR1 H02W0501\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 Q5\narc: S1_V02S0101 F3\narc: V01S0000 F2\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000100011111111\nword: SLICEA.K0.INIT 1111110000110000\nword: SLICEA.K1.INIT 1111110000110000\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 1111111100001111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R24C12:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 N1_V02S0501\narc: E3_H06E0003 V06S0003\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0303 N1_V01S0100\narc: H00L0100 S1_V02N0101\narc: H00R0000 V02N0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0001 H01E0001\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0103 N3_V06S0103\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0501 H01E0101\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0303 E3_H06W0203\narc: A2 V00B0000\narc: A5 V00T0100\narc: A6 F7\narc: A7 W1_H02E0701\narc: B0 V00B0000\narc: B1 V02N0101\narc: B2 W1_H02E0301\narc: B3 V02N0101\narc: B5 H00R0000\narc: B6 V02S0501\narc: B7 H02E0101\narc: C0 V02S0401\narc: C1 H00L0000\narc: C2 H00L0100\narc: C3 N1_V01N0001\narc: C5 W1_H02E0601\narc: C6 H02E0401\narc: C7 S1_V02N0001\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 F2\narc: D2 V02S0001\narc: D3 V02N0201\narc: D5 F0\narc: D6 H02E0001\narc: D7 H02E0201\narc: E1_H01E0001 F3\narc: E1_H01E0101 F2\narc: E1_H02E0701 F7\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: LSR0 E1_H02W0301\narc: M4 E1_H01E0101\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F2\narc: N1_V02N0101 F3\narc: N3_V06N0203 F4\narc: S1_V02S0201 F0\narc: S1_V02S0301 F1\narc: S3_V06S0003 F3\narc: V00B0000 Q6\narc: V01S0000 F1\nword: SLICEA.K0.INIT 1100111100000000\nword: SLICEA.K1.INIT 0000111100000011\nword: SLICEB.K0.INIT 0000111100001011\nword: SLICEB.K1.INIT 0000110000000000\nword: SLICED.K0.INIT 0000000001001111\nword: SLICED.K1.INIT 0001010101010101\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000010\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R24C13:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 S3_V06N0203\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0203 H01E0001\narc: H00R0000 H02E0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 V01N0001\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N1_V01S0100\narc: V00B0100 V02N0101\narc: V00T0000 H02W0001\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 S1_V02N0101\narc: S1_V02S0001 W3_H06E0003\narc: W3_H06W0303 E3_H06W0203\narc: A7 H00R0000\narc: B7 H02W0101\narc: C6 V01N0101\narc: C7 V00B0100\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D6 V02N0601\narc: D7 V00B0000\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q0\narc: N1_V02N0401 Q4\narc: V00B0000 F6\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000001111\nword: SLICED.K1.INIT 0101010001010101\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R24C14:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0601 E1_H01W0000\narc: H00R0000 H02W0601\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 H02E0301\narc: S1_V02S0501 H06E0303\narc: S1_V02S0701 W1_H02E0701\narc: V00T0100 V02S0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 N3_V06S0203\narc: S3_V06S0103 W3_H06E0103\narc: W3_H06W0003 V01N0001\narc: W3_H06W0303 N3_V06S0303\narc: A4 H02W0501\narc: A5 H02W0501\narc: B2 H01W0100\narc: B4 N1_V01S0000\narc: B5 N1_V01S0000\narc: C2 V02S0401\narc: C3 H00L0000\narc: C4 V00T0100\narc: C5 V00T0100\narc: CE0 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 F2\narc: D2 H00R0000\narc: D3 H02E0001\narc: D4 H02W0001\narc: D5 H02W0001\narc: E1_H02E0301 Q1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: H00L0000 F2\narc: H00L0100 F3\narc: H01W0100 Q1\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F2\narc: V00B0000 Q4\narc: W3_H06W0103 F2\narc: W3_H06W0203 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000000001100\nword: SLICEB.K1.INIT 1111111111110000\nword: SLICEC.K0.INIT 0100000000000000\nword: SLICEC.K1.INIT 1011111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R24C15:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 V06S0303\narc: H00L0000 V02S0001\narc: H00L0100 V02S0101\narc: H00R0000 V02S0401\narc: H00R0100 V02S0701\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0001 H06W0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0701 H06W0203\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0401\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 V06S0203\narc: A1 H00L0000\narc: A3 H00L0100\narc: A4 N1_V02S0301\narc: A5 N1_V01S0100\narc: B0 H01W0100\narc: B1 V00T0000\narc: B3 H00R0000\narc: B4 V02S0501\narc: B5 V02S0501\narc: C0 H02E0601\narc: C1 V02N0401\narc: C3 H02W0401\narc: C4 N1_V02S0201\narc: C5 N1_V02S0201\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 N1_V01S0000\narc: D3 N1_V02S0001\narc: D4 V02S0601\narc: D5 V00B0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F3\narc: H01W0100 F4\narc: LSR0 H02W0501\narc: M6 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V02N0001 F0\narc: N1_V02N0401 Q6\narc: V00T0100 F1\narc: V01S0000 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000010000100001\nword: SLICEA.K0.INIT 1100000000000000\nword: SLICEA.K1.INIT 1001000000000000\nword: SLICEC.K0.INIT 1000101001000101\nword: SLICEC.K1.INIT 1010001001010001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R24C16:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0103 N1_V01S0100\narc: H00L0100 N1_V02S0301\narc: H00R0100 V02S0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 H06W0003\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 N1_V02S0101\narc: V00T0000 S1_V02N0601\narc: V00T0100 V02S0701\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 S3_V06N0303\narc: E1_H02E0501 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: A3 H00L0100\narc: B3 W1_H02E0301\narc: C3 H00R0100\narc: C7 H02E0401\narc: CE0 H02W0101\narc: CE2 H02W0101\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D3 W1_H02E0001\narc: D7 H02W0001\narc: E1_H01E0001 Q7\narc: E1_H01E0101 Q0\narc: E1_H02E0401 Q4\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q7\narc: N1_V02N0501 Q7\narc: N3_V06N0103 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000010000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111111110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R24C17:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V02N0201\narc: E3_H06E0203 V01N0001\narc: E3_H06E0303 V01N0101\narc: H00L0000 V02S0201\narc: H00R0000 S1_V02N0401\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H01E0001\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H01E0001\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 E1_H02W0201\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 V02S0401\narc: W3_H06W0203 E1_H01W0000\narc: A1 H02W0701\narc: A2 H02W0701\narc: A3 H02E0701\narc: A4 V00B0000\narc: A5 V00B0000\narc: A7 N1_V01N0101\narc: B1 V02N0301\narc: B2 V02N0301\narc: B3 V02N0101\narc: B4 H01E0101\narc: B5 H00L0000\narc: B7 V01S0000\narc: C1 V02S0401\narc: C2 H00L0100\narc: C3 F4\narc: C4 V00T0000\narc: C5 V00T0000\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: D1 H00R0000\narc: D2 S1_V02N0201\narc: D3 N1_V01S0000\narc: D4 H02E0001\narc: D5 S1_V02N0401\narc: D6 H00R0100\narc: D7 S1_V02N0601\narc: E1_H01E0101 F2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H00R0100 F7\narc: N1_V01N0101 F1\narc: N3_V06N0103 F2\narc: N3_V06N0203 F7\narc: N3_V06N0303 F6\narc: V01S0000 F5\nword: SLICEC.K0.INIT 1000110010101111\nword: SLICEC.K1.INIT 1111010100110001\nword: SLICEB.K0.INIT 1101000000000000\nword: SLICEB.K1.INIT 1001000000000000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1011000010111011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R24C18:PLC2\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0701 V06S0203\narc: E3_H06E0003 N3_V06S0003\narc: E3_H06E0203 V01N0001\narc: H00R0100 V02N0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0501 N1_V01S0100\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 H06W0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 H02E0201\narc: V00T0100 H02W0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0401 V06S0203\narc: W1_H02W0701 N1_V01S0100\narc: E1_H02E0101 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: B7 H02W0101\narc: C6 H02W0401\narc: C7 V02N0201\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D6 V00B0000\narc: D7 V02S0401\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q2\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: H01W0100 Q4\narc: LSR0 W1_H02E0501\narc: LSR1 W1_H02E0501\narc: M0 V00T0000\narc: M2 V00T0100\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: V01S0100 Q0\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000111100000000\nword: SLICED.K1.INIT 0000110011001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R24C19:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0003 H01E0001\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02S0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H06E0203\narc: N3_V06N0203 H06E0203\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0201\narc: V00B0100 N1_V02S0301\narc: V00T0100 N1_V02S0701\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 E3_H06W0303\narc: N1_V02N0001 W3_H06E0003\narc: N3_V06N0003 W3_H06E0003\narc: W1_H02W0001 W3_H06E0003\narc: W3_H06W0203 E1_H02W0701\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: A3 H00L0100\narc: A4 N1_V01S0100\narc: A5 N1_V01S0100\narc: A6 V02S0301\narc: A7 N1_V01N0101\narc: B3 W1_H02E0101\narc: B4 V00B0100\narc: B5 H01E0101\narc: B6 V00B0000\narc: B7 V02N0501\narc: C3 H00L0000\narc: C4 V02S0001\narc: C5 V02N0001\narc: C6 V00T0100\narc: C7 V02S0201\narc: CE0 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: D4 H00R0100\narc: D5 S1_V02N0601\narc: D6 N1_V02S0601\narc: D7 V00B0000\narc: E1_H01E0001 F5\narc: E1_H01E0101 F3\narc: E1_H02E0401 F4\narc: E1_H02E0701 F7\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 H02E0501\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F6\narc: N1_V01N0101 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1000001001000001\nword: SLICED.K1.INIT 1000010000100001\nword: SLICEC.K0.INIT 1000001001000001\nword: SLICEC.K1.INIT 1001000000001001\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000001001000001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R24C20:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 V01N0001\narc: E3_H06E0103 V01N0101\narc: H00L0000 H02W0001\narc: H00R0000 H02W0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 H06W0303\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 H06W0303\narc: V00B0000 V02N0201\narc: V00T0000 H02W0201\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 E1_H02W0701\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A3 V00T0000\narc: A4 H02E0501\narc: A5 H02E0501\narc: A6 E1_H01W0000\narc: A7 N1_V01S0100\narc: B2 F3\narc: B3 E1_H01W0100\narc: B4 H00L0000\narc: B5 H00R0000\narc: B6 V02S0501\narc: B7 V02S0701\narc: C2 F4\narc: C3 V02S0401\narc: C4 H02E0601\narc: C5 V02N0201\narc: C6 H01E0001\narc: C7 V00B0100\narc: CE0 H02W0101\narc: CLK0 G_HPBX0000\narc: D2 H01E0101\narc: D3 H02E0201\narc: D4 V00B0000\narc: D5 H02E0001\narc: D6 H01W0000\narc: D7 H00R0100\narc: E1_H01E0001 F2\narc: E1_H02E0401 F6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q0\narc: LSR1 E1_H02W0501\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N3_V06N0303 F6\narc: V00B0100 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100111101000101\nword: SLICEC.K1.INIT 1000110010101111\nword: SLICEB.K0.INIT 1100000000000000\nword: SLICEB.K1.INIT 1111010100110001\nword: SLICED.K0.INIT 1011000000000000\nword: SLICED.K1.INIT 1001000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R24C21:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 V02S0501\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 H06E0003\narc: S1_V02S0301 N1_V02S0201\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0101\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 H02E0201\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0701 S1_V02N0701\narc: W3_H06W0303 N3_V06S0303\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: H01W0000 Q2\narc: H01W0100 Q0\narc: LSR1 H02W0501\narc: M0 W1_H02E0601\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: V01S0100 Q6\narc: W1_H02W0001 Q0\narc: W1_H02W0201 Q2\narc: W1_H02W0401 Q6\narc: W1_H02W0601 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R24C22:PLC2\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02S0501\narc: E3_H06E0103 W1_H02E0101\narc: H00L0100 H02W0301\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0201 H06W0103\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 V02S0101\narc: V00T0000 H02E0201\narc: V00T0100 H02W0301\narc: W1_H02W0201 N3_V06S0103\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: N3_V06N0103 W3_H06E0103\narc: N3_V06N0203 W3_H06E0203\narc: W1_H02W0501 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0103 N3_V06S0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: A3 H02E0501\narc: A4 N1_V01S0100\narc: B3 H02E0101\narc: B4 H02E0101\narc: B5 V02S0701\narc: C3 N1_V01N0001\narc: C4 E1_H01E0101\narc: C5 S1_V02N0201\narc: CE0 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D4 H00L0100\narc: D5 V02S0401\narc: E1_H01E0001 F3\narc: E1_H01E0101 F5\narc: E1_H02E0601 F4\narc: E3_H06E0303 Q6\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q0\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M0 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F5\narc: N3_V06N0303 F5\narc: S1_V02S0701 F5\narc: S3_V06S0303 F5\narc: V01S0100 Q0\narc: W3_H06W0303 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000001000000000\nword: SLICEC.K0.INIT 1010100010101010\nword: SLICEC.K1.INIT 0011000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R24C23:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V06S0303\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 N1_V02S0301\narc: H00R0000 H02W0601\narc: H00R0100 H02W0501\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0301 H02W0301\narc: S1_V02S0601 H02W0601\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 H02W0501\narc: V00T0100 H02E0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 N1_V01S0100\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A0 V02N0701\narc: A1 H00L0100\narc: B0 V00B0000\narc: B1 H02W0101\narc: B2 V02N0101\narc: B4 H02E0301\narc: B6 V00B0000\narc: C0 W1_H02E0401\narc: C1 N1_V01S0100\narc: C2 H00R0100\narc: C4 H02W0401\narc: C6 V00B0100\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 H01E0101\narc: D2 V02S0001\narc: D3 H00R0000\narc: D4 N1_V02S0601\narc: D5 H02E0201\narc: D6 N1_V02S0601\narc: D7 E1_H02W0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q4\narc: M2 V00T0100\narc: M4 E1_H02W0401\narc: M6 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0201 Q2\narc: N1_V02N0401 Q4\narc: S3_V06S0303 Q6\narc: V00B0000 Q6\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 0101001111111111\nword: SLICEA.K1.INIT 1010101010001010\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R24C24:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 W1_H02E0601\narc: H00L0000 S1_V02N0201\narc: H00L0100 V02N0301\narc: H00R0100 H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0203 H06W0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 H02E0301\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02N0201\narc: V00B0100 V02S0301\narc: V00T0000 E1_H02W0001\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 E1_H02W0301\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: A2 H02W0501\narc: A4 E1_H02W0501\narc: A7 E1_H02W0701\narc: B2 H00L0000\narc: B3 N1_V02S0301\narc: B4 V02N0501\narc: B7 H01E0101\narc: C2 S1_V02N0601\narc: C3 H00L0100\narc: C4 E1_H02W0401\narc: C7 H01E0001\narc: CE0 N1_V02S0201\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 H02W0201\narc: D3 V02S0201\narc: D4 H01W0000\narc: D7 H02E0001\narc: E1_H01E0001 F4\narc: E1_H01E0101 Q3\narc: E1_H02E0001 Q0\narc: E3_H06E0003 Q0\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: H01W0100 Q4\narc: LSR0 V00B0100\narc: M0 V00T0000\narc: M4 W1_H02E0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q0\narc: N1_V02N0301 Q3\narc: N3_V06N0003 Q3\narc: N3_V06N0103 F2\narc: V01S0100 Q3\narc: W3_H06W0203 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0001010100111111\nword: SLICEB.K1.INIT 1111000000110011\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111011101110011\nword: SLICEC.K0.INIT 1111111110001111\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R24C25:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 V02S0701\narc: E3_H06E0003 H01E0001\narc: E3_H06E0103 W1_H02E0201\narc: H00L0100 V02S0301\narc: H00R0000 V02S0601\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0601 H02E0601\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 V01N0001\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 E1_H02W0601\narc: V00T0000 E1_H02W0201\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 V06S0303\narc: E1_H01E0001 W3_H06E0003\narc: W3_H06W0103 V06S0103\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0303 E3_H06W0303\narc: A1 H00L0100\narc: B1 E1_H01W0100\narc: B4 S1_V02N0701\narc: B5 E1_H02W0301\narc: C1 E1_H01W0000\narc: C2 S1_V02N0601\narc: C3 V02N0601\narc: C4 V02S0001\narc: C5 V00T0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 V01S0100\narc: D3 H00R0000\narc: D4 V02S0601\narc: D5 V00B0000\narc: E1_H01E0101 F3\narc: E1_H02E0101 F3\narc: E3_H06E0303 F5\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0000 F2\narc: H01W0000 F3\narc: H01W0100 F2\narc: LSR0 H02E0301\narc: M6 H02E0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q6\narc: N1_V02N0301 F1\narc: N1_V02N0401 F4\narc: V01S0000 Q6\narc: V01S0100 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000011101110111\nword: SLICEC.K0.INIT 1100000000000000\nword: SLICEC.K1.INIT 1100000000000000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 1111000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R24C26:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 E1_H02W0001\narc: H00L0100 V02S0101\narc: H00R0000 H02E0601\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 E1_H02W0301\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 E1_H01W0100\narc: V00B0000 V02S0201\narc: V00B0100 H02E0701\narc: V00T0000 H02E0001\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0701 E1_H02W0701\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: B3 N1_V02S0101\narc: B4 H00L0000\narc: C3 V02N0401\narc: C4 V02N0201\narc: C5 V00B0100\narc: CE0 W1_H02E0101\narc: CE2 W1_H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 N1_V02S0201\narc: D3 H00R0000\narc: D4 V02N0601\narc: D5 E1_H02W0001\narc: E1_H01E0101 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q1\narc: LSR0 W1_H02E0301\narc: LSR1 W1_H02E0301\narc: M0 V00T0000\narc: M1 H00L0100\narc: M2 V00T0000\narc: M4 H02E0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q1\narc: N1_V01N0101 Q6\narc: N1_V02N0601 Q6\narc: N3_V06N0103 F1\narc: S1_V02S0401 Q4\narc: S1_V02S0601 F4\narc: S3_V06S0203 F4\narc: V01S0000 F1\narc: W1_H02W0301 F1\narc: W1_H02W0601 F4\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0011111111111111\nword: SLICEC.K0.INIT 0000110011001100\nword: SLICEC.K1.INIT 0000111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R24C27:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 V02N0701\narc: E3_H06E0203 S3_V06N0203\narc: H00R0000 N1_V02S0401\narc: H00R0100 V02S0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00B0100 H02E0501\narc: V00T0000 H02E0201\narc: V00T0100 H02W0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 S3_V06N0303\narc: W3_H06W0203 S3_V06N0203\narc: A0 H02E0701\narc: A7 H02W0701\narc: B0 F1\narc: B1 H01W0100\narc: B3 W1_H02E0301\narc: B7 H02W0101\narc: C0 E1_H01W0000\narc: C1 N1_V01N0001\narc: C3 V02S0601\narc: C7 V00T0000\narc: CE1 H00R0100\narc: CE2 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 V02S0201\narc: D3 H00R0000\narc: D7 V01N0001\narc: E1_H01E0101 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q0\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F3\narc: S1_V02S0401 F6\narc: V01S0100 Q3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1110010011001100\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111011101110011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R24C28:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 S3_V06N0303\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0203 V01N0001\narc: H00L0000 E1_H02W0001\narc: H00L0100 E1_H02W0101\narc: H00R0100 V02N0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0701 V01N0101\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 V02N0301\narc: V00T0000 V02N0401\narc: V00T0100 V02S0501\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0701 V02S0701\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A0 H02E0501\narc: A1 H02W0701\narc: A7 H02E0701\narc: B0 W1_H02E0101\narc: B1 V02N0101\narc: B4 F3\narc: B7 H01E0101\narc: C0 H02W0401\narc: C1 V02S0401\narc: C3 H02E0601\narc: C4 H02W0601\narc: C7 S1_V02N0201\narc: CE0 H00L0000\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 F0\narc: D3 V00B0100\narc: D4 N1_V02S0601\narc: D5 H00L0100\narc: D7 E1_H01W0100\narc: E1_H01E0001 F4\narc: E1_H02E0601 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 F6\narc: H01W0000 F1\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M4 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0001 F1\narc: N1_V01N0101 F1\narc: N1_V02N0101 Q1\narc: N3_V06N0003 F0\narc: S3_V06S0103 F1\narc: V01S0000 F4\narc: W1_H02W0301 F1\narc: W3_H06W0203 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 1000000000000000\nword: SLICEA.K1.INIT 0111000001111100\nword: SLICEC.K0.INIT 1111111111001111\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R24C29:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 V01N0101\narc: E1_H02E0701 E1_H01W0100\narc: H00R0100 V02N0501\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 H02W0701\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 H01E0001\narc: S3_V06S0203 N3_V06S0203\narc: V00T0100 H02W0301\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 E1_H02W0701\narc: H01W0100 W3_H06E0303\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: A2 H00L0100\narc: B2 W1_H02E0101\narc: B3 H02E0101\narc: B7 H02E0301\narc: C2 V02N0401\narc: C3 H02W0401\narc: C7 E1_H02W0601\narc: CE0 H00R0100\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: D2 S1_V02N0001\narc: D3 H02W0201\narc: D7 V02N0601\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q3\narc: E1_H02E0001 Q0\narc: E3_H06E0003 Q3\narc: E3_H06E0203 F7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: H01W0000 Q4\narc: M0 H02E0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q3\narc: N1_V01N0101 F7\narc: N3_V06N0003 Q3\narc: N3_V06N0103 F2\narc: S1_V02S0701 F7\narc: S3_V06S0003 F3\narc: V01S0000 F7\narc: V01S0100 Q3\narc: W3_H06W0003 F3\narc: W3_H06W0203 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0011000000000000\nword: SLICEB.K0.INIT 0001010100111111\nword: SLICEB.K1.INIT 0000000011000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R24C2:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: H00R0000 H02E0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0201 H06W0103\narc: N1_V02N0601 E1_H02W0601\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02N0301\narc: V00T0100 H02E0101\narc: B7 V00T0000\narc: C6 E1_H01E0101\narc: C7 S1_V02N0001\narc: CE0 H00R0100\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D6 E1_H02W0201\narc: D7 E1_H02W0201\narc: E1_H01E0101 Q4\narc: E3_H06E0303 F6\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: V00T0000 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000111111111111\nword: SLICED.K1.INIT 0011001100001111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R24C30:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 V06N0203\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0203 V01N0001\narc: E3_H06E0303 V01N0101\narc: H00L0100 N1_V02S0101\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 H06W0303\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0301\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 V06S0203\narc: W1_H02W0701 E3_H06W0203\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: N3_V06N0303 W3_H06E0303\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: B5 V00B0100\narc: C4 H02W0401\narc: C5 V00T0100\narc: D4 S1_V02N0401\narc: D5 E1_H02W0201\narc: D6 S1_V02N0401\narc: D7 S1_V02N0401\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0000\narc: M1 W1_H02E0001\narc: M2 V00B0000\narc: M3 H00L0100\narc: M4 H02E0401\narc: M5 W1_H02E0001\narc: M6 H02E0401\narc: N3_V06N0003 F3\narc: V01S0000 F3\narc: W3_H06W0003 F3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000011111111\nword: SLICEC.K1.INIT 0011111111111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R24C31:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0203 H01E0001\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 H02E0201\narc: H00L0100 E1_H02W0301\narc: H00R0000 V02N0601\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 H02E0201\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N1_V01S0000\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 V02N0201\narc: V00B0100 N1_V02S0301\narc: V00T0100 S1_V02N0701\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0701 V06S0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0103 V06S0103\narc: A0 V01N0101\narc: A1 V02N0701\narc: A3 H02W0501\narc: A4 H02W0701\narc: B0 H00R0100\narc: B1 V00B0000\narc: B3 S1_V02N0301\narc: B4 F1\narc: B6 V02S0701\narc: C0 V02N0601\narc: C1 S1_V02N0601\narc: C2 H00L0100\narc: C3 S1_V02N0601\narc: C4 E1_H01E0101\narc: C6 S1_V02N0201\narc: C7 V02S0201\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 H00R0000\narc: D2 V00T0100\narc: D3 S1_V02N0001\narc: D4 F0\narc: D6 S1_V02N0401\narc: D7 V02S0401\narc: E1_H01E0101 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: LSR1 V00B0100\narc: M4 V00T0000\narc: M6 H02E0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: S3_V06S0303 F6\narc: V00T0000 F2\narc: W3_H06W0203 F4\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 0000000000000010\nword: SLICEA.K1.INIT 0000100000000000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0000001000000000\nword: SLICED.K0.INIT 0000110011001100\nword: SLICED.K1.INIT 0000111111111111\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R24C32:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V06N0103\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0103 N3_V06S0103\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 V02S0201\narc: H00L0100 H02E0101\narc: H00R0000 H02E0401\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H02E0001\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0601\narc: V00B0100 V02S0101\narc: V00T0000 H02E0001\narc: V00T0100 S1_V02N0701\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0701 V02N0701\narc: E1_H01E0001 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A1 H00L0000\narc: A2 N1_V02S0701\narc: A3 V00T0000\narc: A4 V02N0101\narc: A6 V02S0301\narc: A7 E1_H02W0501\narc: B1 S1_V02N0101\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 V02N0701\narc: B6 S1_V02N0701\narc: B7 V02N0501\narc: C1 V02S0401\narc: C2 E1_H01W0000\narc: C3 H02E0601\narc: C4 V00T0100\narc: C6 H02E0601\narc: C7 V02N0201\narc: D1 H02E0201\narc: D2 V01S0100\narc: D3 H00R0000\narc: D4 H01W0000\narc: D6 H00L0100\narc: D7 V00B0000\narc: E1_H01E0101 F7\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: H01W0100 F2\narc: M0 V00B0100\narc: M4 E1_H01E0101\narc: V01S0100 F3\narc: W3_H06W0003 F0\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 0000000000000010\nword: SLICED.K1.INIT 0000100000000000\nword: SLICEB.K0.INIT 0000000000000111\nword: SLICEB.K1.INIT 0000000000000010\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000010000000000\nword: SLICEC.K0.INIT 0000000000010011\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R24C33:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 V02S0701\narc: E3_H06E0103 V06N0103\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 H02E0001\narc: H00R0000 N1_V02S0601\narc: H00R0100 V02N0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0303 N3_V06S0303\narc: V00T0000 H02E0001\narc: V00T0100 E1_H02W0301\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0701 S3_V06N0203\narc: W3_H06W0203 S3_V06N0203\narc: W3_H06W0303 N1_V01S0100\narc: A1 S1_V02N0701\narc: A2 S1_V02N0501\narc: A3 S1_V02N0501\narc: A5 H02W0701\narc: A7 V00T0100\narc: B1 V00T0000\narc: B2 H00L0000\narc: B3 H02W0301\narc: B5 H00R0000\narc: B7 V02S0501\narc: C1 H02E0601\narc: C2 H02E0601\narc: C3 E1_H02W0601\narc: C5 H02W0401\narc: C7 V01N0101\narc: D1 H02E0201\narc: D2 H02E0201\narc: D3 V02N0201\narc: D5 S1_V02N0401\narc: D7 H00R0100\narc: E1_H01E0101 F3\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F2\narc: M6 V00B0100\narc: N1_V01N0001 F6\narc: V00B0100 F5\narc: V01S0000 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000100000000000\nword: SLICEB.K0.INIT 0000100000000000\nword: SLICEB.K1.INIT 1100110010100000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R24C34:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V06S0203\narc: H00L0000 H02W0001\narc: H00L0100 V02N0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 S3_V06N0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02S0201\narc: V00T0000 H02W0001\narc: V00T0100 S1_V02N0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 V06S0203\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: A1 H00L0000\narc: A5 V00T0000\narc: A7 H00L0000\narc: B1 H00R0100\narc: B5 V02N0501\narc: B7 V02S0701\narc: C1 H02E0401\narc: C5 V02N0001\narc: C7 V02N0201\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D5 V02N0601\narc: D7 H00L0100\narc: E1_H01E0001 F5\narc: E1_H01E0101 F6\narc: F0 F5A_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q2\narc: M0 V00T0100\narc: M2 V00B0000\narc: M6 H02W0401\narc: MUXCLK1 CLK0\narc: N1_V01N0001 Q2\narc: N3_V06N0003 F0\narc: S3_V06S0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R24C35:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 H01E0001\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0203 W1_H02E0701\narc: E3_H06E0303 N1_V01S0100\narc: H00R0100 V02N0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0103 H01E0101\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0601\narc: V00B0100 W1_H02E0701\narc: V00T0100 V02S0501\narc: W1_H02W0101 V02S0101\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0601 V02N0601\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0501 W3_H06E0303\narc: H01W0000 W3_H06E0103\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: A3 H02E0701\narc: A5 V00B0000\narc: A7 H02W0701\narc: B3 H02W0301\narc: B5 V00B0100\narc: B7 H02W0301\narc: C3 H00R0100\narc: C5 H02W0401\narc: C7 V02N0201\narc: CE0 H02W0101\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D5 V02N0401\narc: D7 H02W0201\narc: E1_H01E0101 F7\narc: E3_H06E0003 Q0\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F3\narc: M0 H02E0601\narc: M4 E1_H01E0101\narc: MUXCLK0 CLK0\narc: N3_V06N0203 F4\narc: V01S0000 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R24C36:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0303 N3_V06S0303\narc: H00L0100 H02W0101\narc: H00R0000 N1_V02S0401\narc: H00R0100 H02E0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0203\narc: V00T0000 H02E0001\narc: V00T0100 H02E0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 S3_V06N0203\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0301 W3_H06E0003\narc: S1_V02S0001 W3_H06E0003\narc: S1_V02S0301 W3_H06E0003\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: A1 H00L0100\narc: A5 V00T0100\narc: B1 H00R0100\narc: B3 W1_H02E0101\narc: B5 V02S0501\narc: B6 N1_V01S0000\narc: C1 V02S0401\narc: C3 S1_V02N0401\narc: C5 H02W0401\narc: C6 E1_H02W0601\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 H02W0001\narc: D3 V01S0100\narc: D5 W1_H02E0201\narc: D6 H02W0201\narc: D7 E1_H02W0001\narc: E1_H01E0101 F0\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: V00B0100 F5\narc: V01S0100 F6\narc: W3_H06W0003 Q3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100000011001111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 1111000000110011\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R24C37:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V06S0203\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 W1_H02E0201\narc: H00L0100 W1_H02E0301\narc: H00R0000 H02E0401\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H01E0001\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 H02E0501\narc: N3_V06N0103 V01N0101\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0401\narc: V00B0100 W1_H02E0501\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 V01N0001\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: N3_V06N0303 W3_H06E0303\narc: W3_H06W0203 N3_V06S0203\narc: A1 H00L0100\narc: A3 V02S0501\narc: A5 V00T0000\narc: B1 V00B0000\narc: B3 H00L0000\narc: B5 H00R0000\narc: C1 N1_V01S0100\narc: C3 H02W0401\narc: C5 V02S0201\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D3 H02E0201\narc: D5 V02S0401\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: H01W0000 F4\narc: M0 H02E0601\narc: M4 W1_H02E0401\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: N1_V02N0201 F0\narc: N1_V02N0601 Q6\narc: N3_V06N0003 F3\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000010101010\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R24C38:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 H01E0101\narc: E3_H06E0303 N3_V06S0303\narc: H00R0100 H02W0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H06W0203\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0101\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02S0201\narc: V00T0000 H02W0201\narc: V00T0100 V02N0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V01N0101\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0501 W3_H06E0303\narc: H01W0000 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: CE0 H02W0101\narc: CE1 H02E0101\narc: CE2 H00R0100\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 N1_V01N0101\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: V01S0100 Q4\narc: W3_H06W0103 Q2\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R24C39:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 V01N0001\narc: H00L0000 H02E0201\narc: H00L0100 V02N0101\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02N0401\narc: V00T0100 S1_V02N0501\narc: V01S0000 S3_V06N0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0701 V02N0701\narc: B5 H00L0000\narc: B6 V02S0501\narc: B7 V02S0501\narc: C4 W1_H02E0401\narc: C5 H02E0401\narc: C6 V02N0001\narc: C7 S1_V02N0001\narc: CE0 H00L0100\narc: CE1 N1_V02S0201\narc: CLK0 G_HPBX0000\narc: D4 H02E0201\narc: D5 H00R0100\narc: D6 S1_V02N0401\narc: D7 W1_H02E0001\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q2\narc: E3_H06E0303 F6\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q2\narc: M0 V00B0000\narc: M2 V00T0100\narc: M4 V00B0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 F6\narc: S1_V02S0401 F6\narc: S1_V02S0601 F4\narc: W1_H02W0201 Q0\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000011110000\nword: SLICEC.K1.INIT 1111001100000000\nword: SLICED.K0.INIT 1111001111110000\nword: SLICED.K1.INIT 1111111100110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R24C3:PLC2\narc: E1_H02E0701 S1_V02N0701\narc: H00R0000 E1_H02W0401\narc: H00R0100 H02W0501\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H06W0303\narc: S1_V02S0201 E1_H02W0201\narc: S3_V06S0003 N3_V06S0303\narc: V00B0100 S1_V02N0101\narc: V00T0000 E1_H02W0201\narc: D0 V00B0100\narc: D1 V02N0201\narc: D2 V02N0001\narc: D3 S1_V02N0001\narc: E1_H02E0101 F3\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H00R0000\narc: M2 V00T0000\narc: M3 H00R0100\narc: M4 V00T0000\narc: M5 H00R0000\narc: M6 V00T0000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R24C40:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0003 H01E0001\narc: H00L0100 V02N0301\narc: H00R0100 W1_H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 H06E0103\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 H02W0401\narc: V00B0100 H02W0501\narc: V00T0000 S1_V02N0601\narc: V00T0100 H02W0301\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0701 N3_V06S0203\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A0 H02E0501\narc: A4 S1_V02N0301\narc: A5 E1_H02W0701\narc: A7 V00T0100\narc: B0 V02S0301\narc: B2 V02N0301\narc: B3 V02N0101\narc: B4 H00R0000\narc: B5 H02E0301\narc: B7 V02S0501\narc: C0 S1_V02N0401\narc: C1 H00R0100\narc: C2 N1_V02S0601\narc: C3 H00L0100\narc: C4 H02E0401\narc: C5 H02W0401\narc: C7 E1_H02W0601\narc: D0 H02W0001\narc: D1 S1_V02N0201\narc: D2 H02E0201\narc: D3 H02E0201\narc: D4 H01W0000\narc: D5 V02S0401\narc: D7 V00B0000\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 F6\narc: H01W0000 F5\narc: H01W0100 F2\narc: M2 V00T0000\narc: M6 V00B0100\narc: N3_V06N0203 F4\narc: S3_V06S0003 F0\narc: S3_V06S0103 F1\narc: V01S0000 F2\nword: SLICEA.K0.INIT 1100101010101010\nword: SLICEA.K1.INIT 0000000011110000\nword: SLICEC.K0.INIT 0000111100001110\nword: SLICEC.K1.INIT 1100010010000000\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 1100111111000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0110101110110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R24C41:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 E3_H06W0303\narc: E3_H06E0103 N3_V06S0103\narc: H00L0100 V02N0301\narc: H00R0000 W1_H02E0601\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H02W0701\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 H02E0101\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H06E0303\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0303 N1_V02S0601\narc: V00B0100 N1_V02S0101\narc: V00T0000 S1_V02N0401\narc: V00T0100 V02N0501\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V06N0203\narc: W1_H02W0501 N1_V02S0501\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0101 W3_H06E0103\narc: S1_V02S0001 W3_H06E0003\narc: S1_V02S0701 W3_H06E0203\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0303 W3_H06E0203\narc: A1 N1_V02S0701\narc: A2 H02W0701\narc: A3 V02S0501\narc: A7 H02W0501\narc: B1 S1_V02N0101\narc: B2 F3\narc: B3 H02W0301\narc: B4 S1_V02N0501\narc: B5 H02E0301\narc: B7 V00T0000\narc: C1 F6\narc: C2 V02N0601\narc: C3 H00L0100\narc: C4 E1_H02W0601\narc: C5 S1_V02N0001\narc: C7 V02S0201\narc: CE0 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D1 H02W0001\narc: D2 H00R0000\narc: D3 E1_H02W0001\narc: D4 S1_V02N0601\narc: D5 S1_V02N0601\narc: D7 H00R0100\narc: E1_H01E0001 F4\narc: E3_H06E0003 F3\narc: E3_H06E0203 F4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F3\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: N1_V01N0101 F4\narc: N1_V02N0201 F2\narc: V01S0000 F3\narc: W3_H06W0003 F3\narc: W3_H06W0103 Q1\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000111100101110\nword: SLICEB.K0.INIT 1101000010000000\nword: SLICEB.K1.INIT 1100001000000010\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 1100111111000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1011001101111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R24C42:PLC2\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 N1_V02S0601\narc: H00R0100 V02N0701\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 W1_H02E0401\narc: N3_V06N0003 V01N0001\narc: N3_V06N0303 H06E0303\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H01E0001\narc: V00B0000 W1_H02E0601\narc: V00B0100 W1_H02E0701\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V01N0101\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0103 V01N0101\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0203 E3_H06W0103\narc: B2 V02N0301\narc: B3 V02N0301\narc: B5 N1_V02S0701\narc: B6 V02N0501\narc: B7 V02N0501\narc: C2 H00R0100\narc: C3 E1_H02W0601\narc: C5 S1_V02N0201\narc: C6 V00T0100\narc: C7 V02N0201\narc: CE0 H02W0101\narc: CLK0 G_HPBX0000\narc: D2 H01E0101\narc: D3 V02N0201\narc: D5 H02E0201\narc: D6 H00R0100\narc: D7 H02E0001\narc: E1_H01E0101 F6\narc: E1_H02E0001 Q0\narc: E3_H06E0103 F2\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M2 W1_H02E0601\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F2\narc: N1_V01N0101 Q0\narc: N1_V02N0601 F6\narc: S3_V06S0303 F5\narc: V01S0000 Q0\narc: V01S0100 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100000000000000\nword: SLICEB.K0.INIT 1111001111000000\nword: SLICEB.K1.INIT 1111001111000000\nword: SLICED.K0.INIT 1111110000110000\nword: SLICED.K1.INIT 1111110000110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R24C43:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0501 V06S0303\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 W1_H02E0201\narc: H00L0100 V02N0101\narc: H00R0000 H02E0601\narc: H00R0100 V02S0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 H06W0303\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 H01E0101\narc: V00B0000 E1_H02W0401\narc: V00B0100 S1_V02N0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0601 V02S0601\narc: E1_H02E0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0303 E3_H06W0303\narc: A0 H02W0501\narc: A5 H02W0701\narc: A6 H02E0501\narc: A7 H02E0501\narc: B0 H00R0100\narc: B5 H00R0000\narc: B6 N1_V02S0501\narc: B7 N1_V02S0501\narc: C0 F6\narc: C1 H00L0100\narc: C4 H02E0601\narc: C5 N1_V02S0201\narc: C6 S1_V02N0201\narc: C7 S1_V02N0201\narc: D0 H02W0201\narc: D1 V01S0100\narc: D4 E1_H02W0001\narc: D5 E1_H02W0001\narc: D6 H02W0001\narc: D7 H02W0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F1\narc: M0 V00B0000\narc: M1 H00L0000\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 W1_H02E0401\narc: S1_V02S0601 F4\narc: V01S0100 F6\narc: W1_H02W0401 F6\nword: SLICEA.K0.INIT 1101000111100010\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1100110110001100\nword: SLICED.K1.INIT 1111000110110000\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1100100000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R24C44:PLC2\narc: E1_H02E0201 V02S0201\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 N1_V01S0000\narc: H00R0000 H02W0601\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0601 S1_V02N0301\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 V02N0401\narc: V00T0100 H02W0301\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 V02S0701\narc: E1_H02E0501 W3_H06E0303\narc: S1_V02S0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: A3 V02S0701\narc: B3 N1_V02S0301\narc: B5 H00R0000\narc: B7 N1_V02S0701\narc: C2 W1_H02E0601\narc: C3 W1_H02E0601\narc: C5 V00T0100\narc: C6 E1_H01E0101\narc: C7 N1_V02S0001\narc: CE0 H02E0101\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D2 H02E0001\narc: D3 H02E0001\narc: D5 E1_H02W0201\narc: D6 H02W0201\narc: D7 V00B0000\narc: E1_H01E0101 Q7\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: H01W0100 Q0\narc: M0 V00B0100\narc: M2 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F2\narc: N1_V01N0101 F6\narc: N3_V06N0303 Q5\narc: S3_V06S0303 Q5\narc: V01S0000 Q7\narc: V01S0100 Q5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000110000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1111110000110000\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 1110000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R24C45:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 W1_H02E0401\narc: H00L0100 V02S0101\narc: H00R0000 V02S0601\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02W0501\narc: V00T0100 N1_V02S0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 N3_V06S0303\narc: E1_H02E0401 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0003 V06N0003\narc: E3_H06E0103 W3_H06E0003\narc: A0 N1_V02S0701\narc: A1 N1_V02S0701\narc: A2 N1_V02S0701\narc: A3 N1_V02S0701\narc: A4 V02N0301\narc: A5 S1_V02N0101\narc: B0 N1_V02S0101\narc: B1 N1_V02S0101\narc: B2 N1_V02S0101\narc: B3 N1_V02S0101\narc: B4 H00R0000\narc: B5 V00B0100\narc: B7 V02N0701\narc: C0 H02W0601\narc: C1 H02W0601\narc: C2 H02W0601\narc: C3 H02W0601\narc: C4 V02N0201\narc: C5 E1_H02W0401\narc: C6 V02N0001\narc: C7 V02S0001\narc: CE3 H00L0100\narc: CLK1 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 V00T0100\narc: D3 V00T0100\narc: D4 S1_V02N0401\narc: D5 H02E0201\narc: D6 V00B0000\narc: D7 H02W0201\narc: E1_H01E0101 Q2\narc: E1_H02E0101 Q1\narc: E1_H02E0201 Q0\narc: E1_H02E0301 Q3\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR1 E1_H02W0301\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXCLK3 CLK1\narc: V01S0000 Q7\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1111110000110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R24C46:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V06S0303\narc: E3_H06E0203 N1_V01S0000\narc: H00L0100 H02W0101\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 S1_V02N0401\narc: N3_V06N0003 V01N0001\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 V02N0401\narc: V00T0100 V02S0701\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0601 W3_H06E0303\narc: N3_V06N0103 W3_H06E0103\narc: S3_V06S0103 W3_H06E0103\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: A0 H02W0501\narc: A1 H02W0501\narc: A2 H02W0501\narc: A3 H02W0501\narc: A4 V00T0000\narc: A5 V02N0301\narc: B0 N1_V02S0101\narc: B1 N1_V02S0101\narc: B2 N1_V02S0101\narc: B3 N1_V02S0101\narc: B4 V02S0501\narc: B5 N1_V02S0501\narc: B6 V01S0000\narc: C0 N1_V02S0601\narc: C1 N1_V02S0601\narc: C2 N1_V02S0601\narc: C3 N1_V02S0601\narc: C4 V02N0201\narc: C5 H02W0401\narc: C6 V00B0100\narc: CLK1 G_HPBX0000\narc: D0 N1_V02S0001\narc: D1 N1_V02S0001\narc: D2 N1_V02S0001\narc: D3 N1_V02S0001\narc: D4 S1_V02N0401\narc: D5 N1_V02S0401\narc: D6 V02N0601\narc: D7 H00L0100\narc: E1_H01E0101 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: LSR1 V00T0100\narc: M6 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 F6\narc: S1_V02S0301 Q1\narc: V01S0000 Q3\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R24C47:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 W1_H02E0701\narc: H00L0100 N1_V02S0101\narc: H00R0000 V02S0401\narc: H00R0100 H02W0501\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 H06W0203\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: V00B0100 H02E0501\narc: V00T0000 E1_H02W0001\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 N3_V06S0203\narc: E1_H01E0001 W3_H06E0003\narc: S3_V06S0203 W3_H06E0203\narc: W3_H06W0203 N1_V01S0000\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A1 H00L0000\narc: A2 H00L0100\narc: B0 H00R0100\narc: B1 V02N0101\narc: B2 F3\narc: B3 W1_H02E0301\narc: B5 W1_H02E0101\narc: B6 V00T0000\narc: C0 N1_V01S0100\narc: C1 N1_V02S0401\narc: C2 H02W0601\narc: C3 S1_V02N0601\narc: C5 W1_H02E0601\narc: C6 H02E0401\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 E1_H02W0201\narc: D2 E1_H02W0001\narc: D3 V00B0100\narc: D5 S1_V02N0401\narc: D6 V02S0601\narc: D7 W1_H02E0001\narc: E1_H01E0101 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q0\narc: H01W0000 F2\narc: H01W0100 Q0\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: N1_V01N0101 F6\narc: V01S0000 F5\narc: V01S0100 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 0000000010101100\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1111110000110000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICED.K0.INIT 0000001100001111\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R24C48:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 S1_V02N0501\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 N1_V02S0001\narc: H00L0100 V02N0301\narc: H00R0000 H02W0601\narc: H00R0100 E1_H02W0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 V01N0001\narc: N3_V06N0103 V01N0101\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V02S0601\narc: V00B0100 S1_V02N0101\narc: V00T0000 W1_H02E0001\narc: V00T0100 W1_H02E0101\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 V02N0101\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 E1_H01W0000\narc: S1_V02S0101 W3_H06E0103\narc: W3_H06W0103 E1_H02W0201\narc: E3_H06E0103 W3_H06E0103\narc: A3 H00L0100\narc: B3 H00L0000\narc: B4 H02E0101\narc: C3 W1_H02E0601\narc: C4 V00T0100\narc: CE0 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 N1_V02S0001\narc: D3 W1_H02E0201\narc: D4 V02N0601\narc: D5 H01W0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 F1\narc: E1_H02E0601 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: H01W0000 Q1\narc: H01W0100 Q1\narc: M0 V00B0100\narc: M1 E1_H02W0001\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F1\narc: N1_V02N0401 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000111100110011\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1100000011001000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R24C49:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02S0101\narc: H00R0000 V02S0601\narc: H00R0100 W1_H02E0501\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 V01N0101\narc: N3_V06N0203 V01N0001\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 H06E0203\narc: V00B0000 H02E0401\narc: V00B0100 W1_H02E0701\narc: V00T0000 H02E0201\narc: V00T0100 E1_H02W0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 E1_H02W0601\narc: H01W0000 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\narc: A3 V02S0701\narc: B0 V00B0000\narc: B3 N1_V02S0301\narc: B5 N1_V02S0501\narc: B6 W1_H02E0301\narc: C0 H02E0601\narc: C2 H00L0000\narc: C3 W1_H02E0601\narc: C5 E1_H01E0101\narc: C6 V00B0100\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H01E0101\narc: D1 H00R0000\narc: D2 V02S0001\narc: D3 V02S0001\narc: D5 W1_H02E0001\narc: D6 H02E0001\narc: D7 H00R0100\narc: E1_H01E0001 F0\narc: E1_H01E0101 F2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: LSR0 H02E0301\narc: M0 H02W0601\narc: M2 V00T0100\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: S1_V02S0701 F5\narc: V01S0100 F6\narc: W3_H06W0303 Q5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100110000001111\nword: SLICEA.K0.INIT 0011000011111100\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 1110000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R24C4:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S3_V06N0303\narc: H00L0000 S1_V02N0201\narc: H00R0000 E1_H02W0601\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0203\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 H02W0401\narc: V00B0100 H02E0701\narc: V00T0100 S1_V02N0501\narc: V01S0100 S3_V06N0303\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 S1_V02N0601\narc: B1 H01W0100\narc: C0 S1_V02N0401\narc: C1 H00L0000\narc: CE2 V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 H02W0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 Q6\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F1\narc: V01S0000 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111100001111\nword: SLICEA.K1.INIT 0011001100001111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R24C50:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V02N0501\narc: E3_H06E0003 N3_V06S0003\narc: H00L0000 E1_H02W0201\narc: H00L0100 V02S0101\narc: H00R0000 H02W0601\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02S0001\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02N0601\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 N3_V06S0203\narc: H01W0000 W3_H06E0103\narc: S1_V02S0601 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0203 N3_V06S0203\narc: E3_H06E0103 W3_H06E0003\narc: A3 H00L0100\narc: B3 N1_V02S0301\narc: C2 H00L0000\narc: C3 H00L0000\narc: CE0 H00R0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 N1_V02S0201\narc: D3 N1_V02S0201\narc: E1_H01E0101 Q4\narc: E1_H02E0201 Q0\narc: F2 F5B_SLICE\narc: H01W0100 F2\narc: M0 V00B0000\narc: M2 V00B0100\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111000011111111\nword: SLICEB.K1.INIT 1110000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R24C51:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 W1_H02E0501\narc: H00R0000 V02N0601\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 H06E0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0601 N1_V01S0000\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 H01E0101\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0501\narc: V00T0000 N1_V02S0601\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V02N0601\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: B1 H02W0101\narc: C1 S1_V02N0401\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: E1_H02E0101 F1\narc: E3_H06E0103 Q2\narc: F1 F1_SLICE\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0000 Q6\narc: V01S0100 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111110000110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R24C52:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 V02N0601\narc: H00L0000 V02N0201\narc: H00L0100 V02S0101\narc: H00R0000 H02E0401\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H01E0001\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0101\narc: V00T0100 V02S0501\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 V02N0501\narc: H01W0100 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: A1 E1_H01E0001\narc: A3 V00T0000\narc: B1 V00B0000\narc: B2 H02W0301\narc: B3 H00R0000\narc: B6 V02N0701\narc: C1 H02W0601\narc: C2 H00L0100\narc: C3 H02W0601\narc: C6 V00T0100\narc: CE1 V02N0201\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H02W0001\narc: D2 E1_H02W0201\narc: D3 H02W0001\narc: D6 V02S0601\narc: D7 V02N0401\narc: E1_H01E0001 Q2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: M4 W1_H02E0401\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: S3_V06S0203 Q4\narc: V00T0000 Q2\narc: W3_H06W0003 F3\narc: W3_H06W0103 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0100011101110111\nword: SLICEB.K0.INIT 0000111100001100\nword: SLICEB.K1.INIT 0001110100111111\nword: SLICED.K0.INIT 1111110000110000\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R24C53:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 W1_H02E0601\narc: H00L0000 V02N0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 N1_V02S0601\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H06W0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 V01N0001\narc: S1_V02S0301 H02E0301\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 H02W0601\narc: V00B0100 W1_H02E0701\narc: V00T0000 W1_H02E0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0701 W3_H06E0203\narc: N3_V06N0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A0 H00L0100\narc: A1 E1_H01E0001\narc: A3 V00T0000\narc: A5 V00T0000\narc: A7 N1_V01N0101\narc: B0 H01W0100\narc: B1 H02W0101\narc: B2 S1_V02N0101\narc: B3 H02W0301\narc: B4 S1_V02N0701\narc: B5 H02W0301\narc: B6 V00B0000\narc: B7 V01S0000\narc: C0 E1_H01W0000\narc: C1 W1_H02E0401\narc: C2 H02E0401\narc: C3 N1_V01N0001\narc: C4 V00T0100\narc: C5 V00B0100\narc: C6 H02W0401\narc: C7 W1_H02E0401\narc: CE0 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 H00R0000\narc: D2 V00T0100\narc: D3 E1_H02W0001\narc: D4 W1_H02E0201\narc: D5 H01W0000\narc: D6 H02E0001\narc: D7 N1_V02S0601\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q0\narc: E3_H06E0003 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F5\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F2\narc: N1_V01N0101 Q0\narc: V01S0000 Q6\narc: W3_H06W0103 F1\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 1111001111000000\nword: SLICEB.K1.INIT 0000000100100011\nword: SLICEA.K0.INIT 0000000110101011\nword: SLICEA.K1.INIT 0011010100111111\nword: SLICEC.K0.INIT 0011111100001100\nword: SLICEC.K1.INIT 0010000000110001\nword: SLICED.K0.INIT 1111001111000000\nword: SLICED.K1.INIT 0011010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R24C54:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 V06N0303\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 N3_V06S0003\narc: E3_H06E0103 W1_H02E0201\narc: H00L0000 V02N0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02E0601\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H02W0501\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N3_V06S0103\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H06E0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00T0000 S1_V02N0401\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 V06N0303\narc: W1_H02W0701 N1_V01S0100\narc: N1_V02N0101 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A4 S1_V02N0301\narc: A7 S1_V02N0301\narc: B0 H02W0301\narc: B2 V02N0301\narc: B4 H00L0000\narc: B5 S1_V02N0701\narc: B6 S1_V02N0701\narc: B7 V00B0000\narc: C0 F6\narc: C2 E1_H02W0601\narc: C4 V00B0100\narc: C5 W1_H02E0601\narc: C6 V00T0000\narc: C7 H02E0401\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 S1_V02N0201\narc: D2 S1_V02N0201\narc: D3 E1_H02W0201\narc: D4 S1_V02N0601\narc: D5 S1_V02N0401\narc: D6 H00L0100\narc: D7 V02S0601\narc: E1_H01E0001 F5\narc: E1_H01E0101 F6\narc: E1_H02E0001 F0\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M0 V00B0000\narc: M2 V00T0100\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F6\narc: N1_V01N0101 F4\narc: V00B0100 F5\narc: V01S0100 Q2\nword: SLICEC.K0.INIT 0000000100100011\nword: SLICEC.K1.INIT 1111110000110000\nword: SLICED.K0.INIT 1111110000110000\nword: SLICED.K1.INIT 1100010010000000\nword: SLICEB.K0.INIT 0000110000111111\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 0000110000111111\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R24C55:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 V02N0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02W0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 N1_V01S0100\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0401 H02E0401\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02E0601\narc: V00B0100 H02E0501\narc: V00T0000 H02E0201\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0501 S1_V02N0501\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: A5 V02N0101\narc: A7 N1_V01N0101\narc: B0 E1_H02W0301\narc: B2 E1_H02W0301\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 V01S0000\narc: B6 V00B0000\narc: B7 H02E0101\narc: C0 W1_H02E0401\narc: C2 H00L0100\narc: C3 E1_H01W0000\narc: C4 H02W0401\narc: C5 N1_V02S0201\narc: C6 V02S0201\narc: C7 N1_V02S0201\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H01E0101\narc: D1 F2\narc: D2 S1_V02N0001\narc: D3 F2\narc: D4 H02E0001\narc: D5 V02S0401\narc: D6 E1_H02W0001\narc: D7 V02S0401\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 Q6\narc: M0 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: N1_V02N0001 F0\narc: S3_V06S0203 F7\narc: V01S0000 Q4\narc: V01S0100 Q6\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 0011111100001100\nword: SLICEC.K1.INIT 0011001101011111\nword: SLICEB.K0.INIT 1111001111000000\nword: SLICEB.K1.INIT 1111001111000000\nword: SLICED.K0.INIT 0000111100001100\nword: SLICED.K1.INIT 0011001101011111\nword: SLICEA.K0.INIT 1111001111000000\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R24C56:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 V06S0103\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0203 W1_H02E0701\narc: H00R0000 E1_H02W0401\narc: H00R0100 W1_H02E0701\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0203 V01N0001\narc: N3_V06N0303 H06E0303\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02E0701\narc: V00T0100 H02E0101\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 V02N0601\narc: E1_H02E0101 W3_H06E0103\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0003\narc: B0 H00R0100\narc: B1 H02W0301\narc: B2 H00R0000\narc: B3 H02W0301\narc: B4 S1_V02N0701\narc: B5 H02W0301\narc: B6 V00B0000\narc: B7 H02W0301\narc: C0 S1_V02N0401\narc: C1 H02E0601\narc: C2 N1_V02S0601\narc: C3 N1_V02S0601\narc: C4 H02E0401\narc: C5 F4\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: D0 V00T0100\narc: D1 F0\narc: D2 V01S0100\narc: D3 N1_V02S0201\narc: D4 H02E0201\narc: D5 N1_V02S0401\narc: D6 H00L0100\narc: D7 V02S0401\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H01W0000 F5\narc: N1_V01N0001 F4\narc: N1_V02N0001 F0\narc: V01S0000 F7\narc: V01S0100 F3\narc: W1_H02W0201 F2\narc: W1_H02W0401 F6\nword: SLICED.K0.INIT 1111110000110000\nword: SLICED.K1.INIT 1111110000110000\nword: SLICEA.K0.INIT 1111110000110000\nword: SLICEA.K1.INIT 1111110000110000\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 0011000011111100\nword: SLICEB.K0.INIT 1100000011110011\nword: SLICEB.K1.INIT 0000110000111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R24C57:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 N3_V06S0203\narc: H00L0100 V02N0101\narc: H00R0000 H02W0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 H02E0501\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0301 H06E0003\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02E0001\narc: V00T0100 H02E0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 N3_V06S0203\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0601 W3_H06E0303\narc: W1_H02W0401 W3_H06E0203\narc: A3 V00T0000\narc: A5 V00B0000\narc: A7 H02W0501\narc: B3 H00R0000\narc: B5 N1_V02S0501\narc: B7 V00B0100\narc: C3 H00R0100\narc: C5 V02N0001\narc: C7 E1_H02W0401\narc: CE0 H00L0100\narc: CLK0 G_HPBX0000\narc: D3 E1_H02W0001\narc: D5 V02S0401\narc: D7 H02W0201\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F3\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: N1_V01N0101 Q0\narc: N3_V06N0203 F7\narc: W3_H06W0303 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000010101010\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000111101110111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100100001000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R24C58:PLC2\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02N0401\narc: H00R0100 H02E0501\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H02E0701\narc: S3_V06S0203 H06E0203\narc: V00B0000 E1_H02W0401\narc: V00B0100 W1_H02E0701\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 S1_V02N0501\narc: E3_H06E0003 W3_H06E0003\narc: B0 H02E0301\narc: B1 V00B0000\narc: B2 H00R0000\narc: B3 H02E0101\narc: B4 V00B0100\narc: B5 H02E0301\narc: B6 H02E0301\narc: C0 S1_V02N0401\narc: C1 N1_V01N0001\narc: C2 V02N0601\narc: C3 H00L0100\narc: C4 V02S0201\narc: C5 F4\narc: C6 V02N0201\narc: D0 S1_V02N0001\narc: D1 F0\narc: D2 V00T0100\narc: D3 V01S0100\narc: D4 S1_V02N0601\narc: D5 H02W0201\narc: D6 H00R0100\narc: D7 F0\narc: E1_H01E0001 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M6 E1_H02W0401\narc: N1_V01N0001 F5\narc: N1_V02N0001 F2\narc: S1_V02S0101 F3\narc: V00T0100 F3\narc: V01S0000 F5\narc: V01S0100 F4\narc: W3_H06W0103 F1\nword: SLICEA.K0.INIT 1111001111000000\nword: SLICEA.K1.INIT 1111001111000000\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 0011111100001100\nword: SLICEC.K0.INIT 1111001111000000\nword: SLICEC.K1.INIT 1111001111000000\nword: SLICED.K0.INIT 1111001111000000\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R24C59:PLC2\narc: E3_H06E0103 V06S0103\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 H06E0203\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H02W0001\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 V02N0401\narc: N1_V02N0001 W3_H06E0003\n\n.tile R24C5:PLC2\narc: E1_H02E0401 W1_H02E0101\narc: H00R0000 V02S0601\narc: H00R0100 S1_V02N0701\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 S1_V02N0101\narc: S1_V02S0501 H02W0501\narc: V00B0000 V02S0001\narc: V00B0100 H02E0501\narc: V00T0000 S1_V02N0601\narc: V00T0100 H02E0101\narc: W1_H02W0401 E1_H02W0101\narc: A2 S1_V02N0701\narc: B2 V02N0101\narc: B3 H00R0100\narc: C2 V02S0601\narc: C3 H02E0601\narc: CE0 S1_V02N0201\narc: CE2 V02N0601\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D2 H02E0001\narc: D3 H00R0000\narc: E1_H01E0001 F2\narc: F2 F5B_SLICE\narc: H01W0000 F2\narc: H01W0100 Q6\narc: M0 V00T0000\narc: M2 V00T0100\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N1_V02N0001 F2\narc: N1_V02N0201 F2\narc: N1_V02N0601 Q4\narc: N3_V06N0103 F2\narc: S1_V02S0001 F2\narc: S3_V06S0103 F2\narc: W1_H02W0201 F2\narc: W3_H06W0103 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000011110111\nword: SLICEB.K1.INIT 1111111100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R24C60:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H02W0701\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 S3_V06N0203\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\n\n.tile R24C61:PLC2\narc: S1_V02S0001 H02E0001\narc: W1_H02W0701 N3_V06S0203\narc: S3_V06S0203 W3_H06E0203\n\n.tile R24C62:PLC2\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N1_V02S0701\narc: E3_H06E0003 W3_H06E0003\n\n.tile R24C63:PLC2\narc: E1_H02E0401 N3_V06S0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0701 N3_V06S0203\n\n.tile R24C64:PLC2\narc: S1_V02S0501 N1_V02S0501\narc: E3_H06E0003 W3_H06E0003\n\n.tile R24C65:PLC2\narc: S1_V02S0001 H06E0003\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0101 W3_H06E0103\n\n.tile R24C66:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0401 N1_V02S0101\narc: E1_H02E0501 W3_H06E0303\n\n.tile R24C67:PLC2\narc: S1_V02S0101 N1_V02S0101\n\n.tile R24C68:PLC2\narc: E3_H06E0303 W1_H02E0501\narc: S1_V02S0001 W1_H02E0001\n\n.tile R24C69:PLC2\narc: E1_H02E0201 N3_V06S0103\narc: S3_V06S0003 N3_V06S0303\n\n.tile R24C6:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 H01E0001\narc: E3_H06E0203 H01E0001\narc: H00L0000 V02S0201\narc: H00R0000 H02E0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 E3_H06W0303\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0201 H01E0001\narc: S3_V06S0003 H01E0001\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 E3_H06W0303\narc: W3_H06W0303 E1_H01W0100\narc: W3_H06W0003 E3_H06W0303\narc: A2 E1_H02W0501\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00L0000\narc: B3 H00R0100\narc: C0 H00L0000\narc: C1 H00L0000\narc: C2 S1_V02N0401\narc: C3 H00L0000\narc: CE2 S1_V02N0601\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 V00B0000\narc: M1 H02W0001\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q6\narc: W1_H02W0301 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111111111100\nword: SLICEA.K1.INIT 1111111111111100\nword: SLICEB.K0.INIT 1111000011100000\nword: SLICEB.K1.INIT 1111111111111100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R24C70:PLC2\narc: N1_V02N0301 W3_H06E0003\narc: S1_V02S0301 W3_H06E0003\n\n.tile R24C7:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 S1_V02N0101\narc: H00R0100 H02E0501\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0303 S3_V06N0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0103\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0401 N3_V06S0203\narc: D0 S1_V02N0001\narc: D1 E1_H02W0001\narc: D2 S1_V02N0201\narc: D3 N1_V02S0201\narc: E1_H01E0001 F3\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 H02E0601\narc: M1 H00L0100\narc: M2 H02E0601\narc: M3 H00R0100\narc: M4 H02E0401\narc: M5 H00L0100\narc: M6 H02E0401\narc: N1_V02N0101 F3\narc: V01S0000 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R24C8:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 W1_H02E0401\narc: H00L0100 H02E0101\narc: H00R0000 H02W0401\narc: H00R0100 H02W0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0701 H02E0701\narc: S1_V02S0201 H01E0001\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 W1_H02E0401\narc: V00B0100 N1_V02S0101\narc: V00T0000 E1_H02W0001\narc: W1_H02W0501 V02N0501\narc: E1_H02E0601 W3_H06E0303\narc: CE2 W1_H02E0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 H00R0000\narc: D2 V01S0100\narc: D3 H02W0201\narc: E1_H01E0001 F1\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 Q4\narc: M0 W1_H02E0601\narc: M1 H00L0100\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R24C9:PLC2\narc: E1_H02E0401 N1_V02S0401\narc: H00R0100 S1_V02N0701\narc: N1_V02N0201 H01E0001\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02E0601\narc: V00B0100 V02S0101\narc: V00T0000 H02W0201\narc: V00T0100 H02W0301\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0701 S1_V02N0701\narc: A4 N1_V01N0101\narc: A5 V00T0000\narc: B4 W1_H02E0101\narc: B5 V00B0100\narc: C4 H02E0401\narc: C5 F4\narc: CE1 H00R0100\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 H02E0001\narc: E1_H02E0501 F5\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: M2 H02W0601\narc: M6 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: W1_H02W0401 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111110100000000\nword: SLICEC.K1.INIT 0101001100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R26C10:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 S1_V02N0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0301 E1_H02W0301\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 H06E0203\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02S0001\narc: V00B0100 H02W0701\narc: V00T0000 V02N0401\narc: V00T0100 V02S0701\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 V06S0303\narc: A7 V00T0100\narc: B7 V00B0000\narc: C7 V00B0100\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D7 H02W0201\narc: E1_H01E0101 F6\narc: E1_H02E0601 F6\narc: F6 F5D_SLICE\narc: H00R0000 F6\narc: H01W0000 F6\narc: M0 V00T0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: N1_V01N0101 Q0\narc: N1_V02N0601 F6\narc: N3_V06N0303 F6\narc: S1_V02S0601 F6\narc: V01S0000 F6\narc: V01S0100 F6\narc: W1_H02W0001 Q0\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R26C11:PLC2\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0601 E3_H06W0303\narc: E3_H06E0103 N3_V06S0103\narc: E3_H06E0303 N3_V06S0303\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 H02E0301\narc: N1_V02N0701 E3_H06W0203\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 V06S0203\n\n.tile R26C12:PLC2\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0601 V06N0303\narc: H00L0000 N1_V02S0201\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02S0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0501 E1_H01W0100\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0601 W1_H02E0601\narc: V00B0100 V02S0101\narc: V00T0000 N1_V02S0601\narc: V00T0100 H02W0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0301 V06N0003\narc: A3 H02W0501\narc: B3 V02S0301\narc: C3 H00L0000\narc: C4 E1_H01E0101\narc: C5 H02W0601\narc: C6 V00T0000\narc: C7 V02S0201\narc: CE0 H00R0000\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 V01S0100\narc: D4 H00L0100\narc: D5 H02E0201\narc: D6 V00B0000\narc: D7 H01W0000\narc: E1_H01E0101 Q5\narc: E3_H06E0103 F2\narc: E3_H06E0203 F7\narc: E3_H06E0303 F6\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: LSR0 V00B0100\narc: M0 V00T0100\narc: M2 H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q5\narc: N1_V02N0701 Q5\narc: N3_V06N0103 F2\narc: N3_V06N0203 F7\narc: V00B0000 F4\narc: V01S0100 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000000011110000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 0010001110101111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R26C13:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 V02N0101\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 S3_V06N0203\narc: H00R0100 V02N0701\narc: N1_V02N0301 H02E0301\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 E3_H06W0303\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0201\narc: V00B0100 N1_V02S0101\narc: V00T0000 N1_V02S0401\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V02S0601\narc: N1_V02N0101 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: H01W0100 Q0\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00B0000\narc: M2 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: N1_V02N0001 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R26C14:PLC2\narc: H00R0000 S1_V02N0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0101 H06E0103\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 V01N0101\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0501 H02W0501\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 W1_H02E0601\narc: V00B0100 H02E0701\narc: V00T0000 W1_H02E0201\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 E1_H01W0000\narc: W3_H06W0103 E3_H06W0103\narc: A0 E1_H01E0001\narc: A1 H02W0701\narc: A2 V02N0701\narc: B0 V00T0000\narc: B1 V00B0000\narc: B2 S1_V02N0301\narc: C0 H02W0601\narc: C1 H00R0100\narc: C2 V02N0401\narc: C5 V00B0100\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 V02N0201\narc: D2 S1_V02N0201\narc: D5 H02E0001\narc: E1_H01E0001 Q1\narc: E1_H02E0201 F2\narc: E1_H02E0601 Q6\narc: E3_H06E0003 F0\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q1\narc: M2 N1_V01N0001\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V02N0301 Q1\narc: N3_V06N0103 F1\narc: W1_H02W0101 Q1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0100000000000000\nword: SLICEA.K1.INIT 1010001000000000\nword: SLICEB.K0.INIT 0001010100111111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R26C15:PLC2\narc: E1_H02E0401 N1_V02S0401\narc: E3_H06E0003 N3_V06S0003\narc: H00L0000 E1_H02W0001\narc: H00R0000 H02W0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0701 H02W0701\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 N3_V06S0303\narc: V00B0000 V02N0001\narc: V00B0100 E1_H02W0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0003 E3_H06W0303\narc: A2 E1_H01E0001\narc: A3 V02N0501\narc: A7 V02N0101\narc: B2 H01W0100\narc: B3 W1_H02E0101\narc: B6 V01S0000\narc: B7 V02N0701\narc: C2 E1_H02W0401\narc: C3 H02W0401\narc: C6 W1_H02E0601\narc: C7 E1_H01E0101\narc: CE0 H00R0100\narc: CE1 H00L0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 V01S0100\narc: D6 S1_V02N0601\narc: D7 H02E0201\narc: E1_H01E0001 Q3\narc: E1_H01E0101 F2\narc: E3_H06E0203 F7\narc: E3_H06E0303 F6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 Q0\narc: M0 V00T0100\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F3\narc: S1_V02S0101 F3\narc: V00T0100 F3\narc: V01S0000 Q4\narc: V01S0100 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0011001100001111\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0001001101011111\nword: SLICEB.K1.INIT 0111000001111100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R26C16:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E3_H06E0303 V06S0303\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02N0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N1_V02S0001\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 N1_V02S0301\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0003 E3_H06W0003\narc: A3 V00T0000\narc: B3 V01N0001\narc: C3 H00L0000\narc: CE0 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D3 E1_H02W0001\narc: E1_H01E0101 F3\narc: E1_H02E0401 Q6\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00B0000\narc: M4 V00B0100\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q4\narc: V00T0000 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000010000100001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R26C17:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0501 V02N0501\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 H02E0401\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 H02W0501\narc: V00T0000 H02E0201\narc: V00T0100 H02W0101\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 V02N0701\narc: W3_H06W0203 E1_H02W0701\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A7 H00L0000\narc: B6 N1_V02S0501\narc: B7 V00B0000\narc: C6 V02S0201\narc: C7 V02N0201\narc: CE0 S1_V02N0201\narc: CE1 S1_V02N0201\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D6 H00R0100\narc: D7 E1_H02W0001\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00R0100 F7\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q2\narc: N1_V02N0601 F6\narc: V00B0000 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111001100000000\nword: SLICED.K1.INIT 1000010000100001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R26C18:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 E3_H06W0303\narc: H00L0100 V02S0101\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 H02W0501\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0001\narc: V00B0100 V02S0101\narc: V00T0000 W1_H02E0201\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0501 N1_V02S0501\narc: W3_H06W0003 S3_V06N0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: A1 H00R0000\narc: B1 H01W0100\narc: C1 H00L0100\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: F1 F1_SLICE\narc: H00R0000 Q4\narc: H01W0000 F1\narc: H01W0100 Q6\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000010000100001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R26C19:PLC2\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0401 V02S0401\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 E1_H01W0000\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 H06W0103\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0303\narc: V00B0000 H02W0601\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02E0201\narc: V00T0100 H02W0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V02N0001\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 E3_H06W0203\narc: W3_H06W0003 E1_H02W0001\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A2 V00T0000\narc: A3 V00B0000\narc: B2 V02N0101\narc: B3 V02N0301\narc: C1 V02N0401\narc: C2 E1_H02W0601\narc: C3 H00R0100\narc: C7 V02N0201\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 V01S0100\narc: D3 V00B0100\narc: D7 S1_V02N0401\narc: E1_H02E0301 F1\narc: E3_H06E0103 F2\narc: E3_H06E0203 F7\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: LSR1 H02E0301\narc: M4 V00T0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V02N0601 Q4\narc: V01S0100 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0000011100000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R26C20:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0601 S3_V06N0303\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02S0001\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02S0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 W1_H02E0501\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 H06W0103\narc: V00B0000 V02N0001\narc: V00T0000 H02E0201\narc: V00T0100 E1_H02W0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0701 E3_H06W0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0203 E3_H06W0103\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q0\narc: E1_H02E0201 Q2\narc: H01W0000 Q2\narc: H01W0100 Q4\narc: M0 V00T0100\narc: M2 V00B0000\narc: M4 H02E0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0001 Q0\narc: N3_V06N0103 Q2\narc: W1_H02W0601 Q6\narc: W3_H06W0103 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R26C21:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 H01E0101\narc: E1_H02E0701 V02N0701\narc: H00R0000 V02S0601\narc: H00R0100 H02W0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02W0401\narc: V00B0100 V02N0101\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0601 V02N0601\narc: E1_H02E0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0303 E3_H06W0203\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0100\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q4\narc: E3_H06E0103 Q2\narc: E3_H06E0303 Q6\narc: M0 V00B0000\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0401 Q6\narc: N3_V06N0103 Q2\narc: N3_V06N0303 Q6\narc: V00T0000 Q0\narc: V01S0000 Q0\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R26C22:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 V01N0101\narc: E3_H06E0003 H01E0001\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 V06S0203\narc: E3_H06E0303 H01E0101\narc: H00L0000 S1_V02N0001\narc: H00R0000 N1_V02S0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H06E0203\narc: N1_V02N0701 H02W0701\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N3_V06S0303\narc: V00B0100 S1_V02N0301\narc: V00T0100 N1_V02S0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0701 N1_V02S0701\narc: W1_H02W0501 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0103 E1_H02W0101\narc: W3_H06W0303 V06S0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0203\narc: A1 S1_V02N0501\narc: A2 V02N0501\narc: A3 V00T0000\narc: A5 V02N0301\narc: A6 N1_V01N0101\narc: A7 H02E0501\narc: B1 H02E0101\narc: B2 S1_V02N0101\narc: B3 H00R0000\narc: B5 H00L0000\narc: B6 N1_V02S0501\narc: B7 H02E0101\narc: C1 S1_V02N0601\narc: C2 H02W0601\narc: C3 H00R0100\narc: C5 E1_H02W0401\narc: C6 N1_V02S0201\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D1 H02W0001\narc: D2 H02E0001\narc: D3 V00B0100\narc: D5 W1_H02E0001\narc: D6 V02N0601\narc: D7 H02W0001\narc: E1_H01E0101 F5\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: MUXCLK1 CLK0\narc: N1_V01N0101 Q2\narc: S1_V02S0401 F6\narc: V00T0000 Q2\narc: V01S0000 F1\narc: V01S0100 F7\narc: W1_H02W0201 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000001000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1111111110000000\nword: SLICEB.K1.INIT 0000000011001010\nword: SLICED.K0.INIT 0101001111111111\nword: SLICED.K1.INIT 1010100010101010\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R26C23:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 V02N0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02E0601\narc: H00R0100 V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 E1_H02W0401\narc: V00B0100 V02N0101\narc: V00T0100 W1_H02E0301\narc: W1_H02W0001 V06S0003\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V06S0203\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A4 H02W0501\narc: A7 S1_V02N0101\narc: B1 V00T0000\narc: B4 V00B0100\narc: B6 E1_H02W0301\narc: B7 H01E0101\narc: C0 H02E0401\narc: C1 H02W0601\narc: C4 E1_H02W0601\narc: C6 W1_H02E0401\narc: C7 V02N0201\narc: CE0 H00L0000\narc: CE1 H00L0100\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 N1_V01S0000\narc: D4 V02N0401\narc: D6 H00R0100\narc: D7 H01W0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 F4\narc: E3_H06E0103 Q1\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: H01W0100 Q2\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M2 V00B0000\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N3_V06N0003 F0\narc: N3_V06N0103 F1\narc: S3_V06S0203 Q4\narc: V00T0000 F0\narc: V01S0000 F7\narc: V01S0100 F1\narc: W1_H02W0401 Q4\narc: W3_H06W0003 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000111111\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 1111111110001111\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000001111\nword: SLICEA.K1.INIT 0011000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R26C24:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0203 H01E0001\narc: H00L0000 W1_H02E0201\narc: H00R0100 V02S0701\narc: H01W0000 E3_H06W0103\narc: H01W0100 E3_H06W0303\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02S0001\narc: V00T0000 H02W0001\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 V06S0203\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0203 E1_H02W0401\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0303 E3_H06W0303\narc: A6 V02N0101\narc: A7 V00T0100\narc: B3 V02N0301\narc: B6 H02E0301\narc: B7 N1_V01S0000\narc: C3 V02N0401\narc: C6 V02N0001\narc: C7 F6\narc: CE0 H00L0000\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 H02E0201\narc: D3 E1_H02W0201\narc: D6 V02N0601\narc: D7 H02W0201\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 H02E0601\narc: M1 H00R0100\narc: M2 H02E0601\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: N1_V02N0401 F6\narc: N3_V06N0203 Q4\narc: V01S0000 F1\narc: V01S0100 Q4\narc: W1_H02W0101 Q1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0010000000000000\nword: SLICED.K1.INIT 1100110010000000\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 1111111111000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R26C25:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 V06N0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V06N0303\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 H01E0001\narc: H00L0000 S1_V02N0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 V02N0601\narc: H00R0100 V02N0501\narc: N1_V02N0101 H02W0101\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02W0701\narc: N3_V06N0103 H06W0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 V01N0101\narc: S1_V02S0301 H01E0101\narc: S1_V02S0401 H06E0203\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 N1_V02S0201\narc: V00B0100 W1_H02E0501\narc: V00T0000 W1_H02E0001\narc: V00T0100 H02W0301\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 E3_H06W0303\narc: N3_V06N0003 W3_H06E0003\narc: W3_H06W0203 E1_H02W0701\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A1 H02E0701\narc: A4 S1_V02N0101\narc: A5 W1_H02E0701\narc: A7 H02W0501\narc: B1 V00B0000\narc: B4 V00B0100\narc: B5 E1_H02W0101\narc: B7 V01S0000\narc: C1 H00L0000\narc: C4 V02N0201\narc: C5 V00T0000\narc: C7 V02S0201\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D4 H02W0001\narc: D5 H00R0100\narc: D7 V02N0401\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q2\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M0 E1_H02W0601\narc: M2 H02W0601\narc: M6 V00T0100\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F5\narc: N1_V02N0201 F0\narc: V01S0000 F4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 1010101010001010\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111011101110011\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R26C26:PLC2\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 H01E0101\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0303 V06N0303\narc: H00L0100 N1_V02S0301\narc: H00R0000 N1_V02S0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 H06W0003\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0301 N1_V02S0301\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: V00B0100 E1_H02W0701\narc: V00T0000 E1_H02W0001\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0601 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A0 S1_V02N0501\narc: A1 H00L0000\narc: A2 V02S0701\narc: A5 S1_V02N0101\narc: B0 N1_V02S0301\narc: B1 V02S0101\narc: B2 V02S0301\narc: B3 V02N0101\narc: B4 H00R0000\narc: B5 V01S0000\narc: B6 V00B0000\narc: C0 V02S0601\narc: C1 W1_H02E0401\narc: C2 E1_H02W0601\narc: C3 V02S0401\narc: C4 V00T0000\narc: C5 S1_V02N0001\narc: C6 V02S0001\narc: CE1 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 S1_V02N0201\narc: D2 V00B0100\narc: D3 W1_H02E0201\narc: D4 V01N0001\narc: D5 H02E0001\narc: D6 H00R0100\narc: D7 H00L0100\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q3\narc: E1_H02E0001 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q0\narc: H01W0100 F3\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q3\narc: N3_V06N0103 F2\narc: N3_V06N0303 Q6\narc: V00B0000 Q6\narc: V01S0000 F4\narc: V01S0100 F1\nword: SLICEA.K0.INIT 1111111110000000\nword: SLICEA.K1.INIT 0000000011001010\nword: SLICEC.K0.INIT 1100000000000000\nword: SLICEC.K1.INIT 0001001100000000\nword: SLICEB.K0.INIT 0000010000001100\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R26C27:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0701 N1_V01S0100\narc: H00L0000 W1_H02E0201\narc: H00L0100 W1_H02E0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 V02S0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0401 V01N0001\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0201\narc: S1_V02S0001 H02E0001\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 W1_H02E0701\narc: V00T0100 E1_H02W0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 H01E0101\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0501 W3_H06E0303\narc: W3_H06W0203 S3_V06N0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A3 H00L0100\narc: A4 V02N0101\narc: A5 W1_H02E0501\narc: B0 H01W0100\narc: B3 H00R0100\narc: B4 V02S0701\narc: B5 V02S0701\narc: C0 H00L0000\narc: C3 E1_H01W0000\narc: C4 H02W0401\narc: C5 V00T0100\narc: C7 E1_H02W0601\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02N0201\narc: D3 E1_H02W0201\narc: D4 V02S0401\narc: D5 N1_V02S0401\narc: D7 V02N0601\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F4\narc: E1_H02E0201 F0\narc: E1_H02E0301 Q3\narc: E1_H02E0601 F4\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 F7\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0101 F3\narc: N1_V02N0201 F0\narc: N1_V02N0501 F5\narc: N3_V06N0203 Q4\narc: N3_V06N0303 Q5\narc: S3_V06S0203 Q4\narc: W1_H02W0701 F5\narc: W3_H06W0003 Q3\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1011100010111011\nword: SLICEC.K0.INIT 1011101100001011\nword: SLICEC.K1.INIT 1011101100001011\nword: SLICEA.K0.INIT 1111111111001111\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R26C28:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 V06N0203\narc: H00L0000 V02S0201\narc: H00R0000 E1_H02W0401\narc: H00R0100 S1_V02N0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H01E0101\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 H02E0701\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0201\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02N0701\narc: W1_H02W0001 V06N0003\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0101 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: N3_V06N0003 W3_H06E0003\narc: W3_H06W0003 V06N0003\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0303 V06S0303\narc: W3_H06W0203 E3_H06W0103\narc: A4 H02W0501\narc: A5 W1_H02E0501\narc: A7 H00L0000\narc: B3 V02S0101\narc: B4 V02N0501\narc: B5 H02E0101\narc: B7 V01S0000\narc: C3 V02N0401\narc: C4 V00T0000\narc: C5 V02S0001\narc: C7 V00B0100\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 E1_H02W0001\narc: D4 V00B0000\narc: D5 V02N0601\narc: D7 V01N0001\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: M0 H01E0001\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: S1_V02S0101 Q3\narc: S3_V06S0003 F3\narc: V00B0100 F5\narc: V01S0000 F4\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 0000000000010000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0011001100110111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R26C29:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 V06S0303\narc: E3_H06E0003 W1_H02E0301\narc: H00L0000 V02N0201\narc: H00R0000 W1_H02E0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0203 N3_V06S0103\narc: V00B0100 H02W0701\narc: V00T0000 H02E0001\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V02S0601\narc: E1_H02E0101 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: S1_V02S0301 W3_H06E0003\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0203 E3_H06W0203\narc: A5 V02N0101\narc: B5 H00L0000\narc: C5 V00B0100\narc: CE1 V02S0201\narc: CLK0 G_HPBX0000\narc: D5 E1_H02W0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F3\narc: LSR0 H02W0301\narc: M0 V00T0000\narc: M1 H00R0100\narc: M2 V00T0000\narc: M3 H00R0000\narc: M4 V00T0000\narc: M5 H00R0100\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 Q3\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010101010101\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R26C2:PLC2\narc: E1_H02E0401 V06S0203\narc: H00R0000 S1_V02N0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0501 E1_H02W0501\narc: N3_V06N0003 S3_V06N0003\narc: V00B0000 V02S0001\narc: V00T0000 V02S0601\narc: CE1 E1_H02W0101\narc: CE2 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: H01W0000 Q4\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0001 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R26C30:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 V02N0601\narc: H00L0100 V02N0301\narc: H00R0000 H02W0601\narc: H00R0100 V02S0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 H01E0001\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 H02W0101\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 E1_H01W0100\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02S0301\narc: V00T0000 V02N0601\narc: V00T0100 H02E0101\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 V06S0203\narc: W1_H02W0701 N1_V02S0701\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0701 W3_H06E0203\narc: N3_V06N0103 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: W3_H06W0003 V06S0003\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0203 E3_H06W0103\narc: A3 V00B0000\narc: A7 V02N0101\narc: B2 F3\narc: B3 E1_H01W0100\narc: B7 V00T0000\narc: C2 N1_V01N0001\narc: C3 V02N0601\narc: C5 H02W0401\narc: C7 H02W0601\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 V01S0100\narc: D3 H00R0000\narc: D5 V02N0601\narc: D7 H00L0100\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR0 V00B0100\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q0\narc: V01S0100 F7\narc: W3_H06W0103 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000010\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000000000000011\nword: SLICEB.K1.INIT 0000100000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R26C31:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V01N0101\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 W1_H02E0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02N0601\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 V01N0101\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0201 V01N0001\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 H02E0601\narc: V00B0100 V02N0101\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02N0501\narc: W1_H02W0101 V01N0101\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 V02N0701\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: A0 H00L0000\narc: A1 H00L0100\narc: A2 V02N0501\narc: A5 H02W0501\narc: A6 V02N0301\narc: B0 V00B0000\narc: B1 H01W0100\narc: B2 H00R0100\narc: B5 V01S0000\narc: B6 F1\narc: C0 V02N0601\narc: C1 H02E0601\narc: C2 V02N0401\narc: C4 N1_V02S0001\narc: C5 V01N0101\narc: C6 E1_H01E0101\narc: D0 V00B0100\narc: D1 H00R0000\narc: D2 V02N0001\narc: D4 N1_V02S0601\narc: D5 V02N0601\narc: D6 H02E0001\narc: E1_H01E0001 F4\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00R0100 F5\narc: H01W0100 F4\narc: M2 V00T0000\narc: M6 V00T0100\narc: N1_V01N0001 F4\narc: N1_V01N0101 F4\narc: V01S0000 F4\narc: W1_H02W0001 F2\narc: W3_H06W0303 F6\nword: SLICEC.K0.INIT 0000000011110000\nword: SLICEC.K1.INIT 0000100000000000\nword: SLICEA.K0.INIT 0000000000000010\nword: SLICEA.K1.INIT 0000100000000000\nword: SLICED.K0.INIT 0000000100000011\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R26C32:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0401 N1_V01S0000\narc: E3_H06E0003 N3_V06S0003\narc: E3_H06E0103 V06S0103\narc: E3_H06E0203 N3_V06S0203\narc: H00L0000 S1_V02N0001\narc: H00L0100 H02E0301\narc: H00R0000 V02N0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 H06W0003\narc: N3_V06N0103 H06E0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0203 N3_V06S0103\narc: V00B0100 H02W0501\narc: V00T0000 V02S0401\narc: V00T0100 H02E0301\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 S1_V02N0501\narc: N1_V02N0401 W3_H06E0203\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0203\narc: A0 H00L0000\narc: A1 S1_V02N0701\narc: A3 V02N0701\narc: A4 H02E0501\narc: A5 E1_H02W0701\narc: A7 H02W0701\narc: B0 H02E0301\narc: B1 W1_H02E0101\narc: B2 H00R0100\narc: B3 H02E0301\narc: B4 V02S0701\narc: B5 W1_H02E0101\narc: B6 H02W0101\narc: B7 H02E0301\narc: C0 N1_V01N0001\narc: C1 H00L0100\narc: C2 S1_V02N0401\narc: C3 H02E0601\narc: C4 E1_H01E0101\narc: C5 V00T0100\narc: C6 V00T0000\narc: C7 H02E0601\narc: D0 V00B0100\narc: D1 H00R0000\narc: D2 H02W0201\narc: D3 H02E0201\narc: D4 V02N0401\narc: D5 V02N0601\narc: D6 H02W0201\narc: D7 H02E0001\narc: E1_H01E0101 F3\narc: E1_H02E0201 F2\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F0\narc: N1_V01N0001 F1\narc: N1_V01N0101 F5\narc: V01S0000 F7\nword: SLICEC.K0.INIT 0000000100000000\nword: SLICEC.K1.INIT 0000100000000000\nword: SLICEB.K0.INIT 0000111100110011\nword: SLICEB.K1.INIT 0000000000000010\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 0000000000000010\nword: SLICEA.K0.INIT 0000000000000111\nword: SLICEA.K1.INIT 0000100000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R26C33:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 N3_V06S0303\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 N1_V02S0001\narc: H00L0100 V02N0301\narc: H00R0100 V02N0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02W0501\narc: V00T0000 E1_H02W0001\narc: V01S0000 N3_V06S0103\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0701 E1_H01W0100\narc: E1_H02E0601 W3_H06E0303\narc: S1_V02S0701 W3_H06E0203\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A1 H00L0000\narc: A5 H02W0501\narc: A7 N1_V02S0301\narc: B0 V00B0000\narc: B1 W1_H02E0301\narc: B2 H02W0301\narc: B4 V00B0100\narc: B5 W1_H02E0301\narc: B7 V02N0701\narc: C0 N1_V02S0601\narc: C1 W1_H02E0601\narc: C2 S1_V02N0401\narc: C4 N1_V02S0201\narc: C5 W1_H02E0601\narc: C7 V02S0201\narc: D0 E1_H02W0201\narc: D1 W1_H02E0001\narc: D2 V02S0001\narc: D3 S1_V02N0001\narc: D4 E1_H02W0201\narc: D5 H00L0100\narc: D7 H00R0100\narc: E1_H01E0001 F6\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M2 V00T0000\narc: M6 N1_V01N0101\narc: N1_V01N0001 F1\narc: N3_V06N0103 F2\narc: N3_V06N0203 F4\narc: W1_H02W0501 F5\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 0000000000000010\nword: SLICEC.K0.INIT 0000111100110011\nword: SLICEC.K1.INIT 0000000000000010\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 1111000000110011\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R26C34:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 H01E0101\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0003 H01E0001\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 V06S0303\narc: H00L0000 E1_H02W0001\narc: H00R0000 S1_V02N0601\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 H02E0301\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 N1_V02S0501\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02E0501\narc: V00T0000 V02N0401\narc: V00T0100 H02W0301\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0701 W3_H06E0203\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A5 V00T0000\narc: B0 V02N0301\narc: B5 H00L0000\narc: B6 V02S0701\narc: C0 V02N0601\narc: C1 V02N0601\narc: C5 H02W0401\narc: C6 H02E0601\narc: CE1 H00R0000\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 H02E0001\narc: D5 V02S0601\narc: D6 V00B0000\narc: D7 E1_H01W0100\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F1\narc: H01W0100 Q2\narc: M2 V00T0100\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0401 Q6\narc: N1_V02N0701 F5\narc: W3_H06W0003 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0011000011110000\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 0000110000111111\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R26C35:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 V02S0601\narc: E3_H06E0003 H01E0001\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 V06S0303\narc: H00L0000 N1_V02S0001\narc: H00L0100 N1_V02S0301\narc: H00R0000 E1_H02W0401\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0601 H02E0601\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 V01N0101\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 N1_V02S0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E1_H02W0301\narc: H01W0100 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A1 V02N0701\narc: A5 S1_V02N0101\narc: B1 E1_H02W0101\narc: B2 H00L0000\narc: B3 H00L0000\narc: B5 H02E0301\narc: B6 V02N0501\narc: B7 V02N0501\narc: C0 E1_H02W0601\narc: C1 N1_V01N0001\narc: C2 S1_V02N0401\narc: C3 N1_V02S0601\narc: C5 E1_H01E0101\narc: C6 V02N0201\narc: C7 V00T0100\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 W1_H02E0201\narc: D2 H02W0201\narc: D3 V00B0100\narc: D4 H01W0000\narc: D5 H02E0001\narc: D6 H02W0201\narc: D7 H00L0100\narc: E1_H01E0001 F6\narc: E1_H01E0101 F1\narc: E1_H02E0201 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F0\narc: N1_V02N0001 F0\narc: N3_V06N0003 F0\narc: S3_V06S0003 F0\narc: V01S0000 F0\narc: V01S0100 F2\narc: W1_H02W0001 F0\narc: W1_H02W0101 F3\narc: W1_H02W0501 F7\narc: W3_H06W0003 F0\narc: W3_H06W0203 Q4\nword: SLICEB.K0.INIT 0011001100001111\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 1100110010100000\nword: SLICED.K0.INIT 0011001100001111\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 1111111100000000\nword: SLICEC.K1.INIT 1111110011111010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\n\n.tile R26C36:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 S3_V06N0303\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V02S0701\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 W1_H02E0201\narc: H00L0100 V02N0101\narc: H00R0000 N1_V02S0401\narc: H00R0100 H02W0501\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 H06E0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0601\narc: V00T0000 V02N0601\narc: V00T0100 S1_V02N0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0401 E3_H06W0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: S1_V02S0101 W3_H06E0103\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0303 N3_V06S0303\narc: B1 H00R0100\narc: B2 S1_V02N0301\narc: B6 H02E0101\narc: C1 H00L0100\narc: C2 H00L0000\narc: C6 H01E0001\narc: CE0 S1_V02N0201\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D2 N1_V02S0001\narc: D3 V00T0100\narc: D6 W1_H02E0001\narc: D7 S1_V02N0401\narc: E1_H02E0201 F2\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: M2 H02E0601\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F6\narc: N1_V01N0101 Q4\narc: N3_V06N0203 Q4\narc: V01S0100 Q4\narc: W3_H06W0103 Q1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100000011001111\nword: SLICED.K0.INIT 1111000000110011\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 1111000000110011\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R26C37:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V01N0101\narc: H00L0000 E1_H02W0001\narc: H00L0100 V02S0301\narc: H00R0000 V02N0401\narc: H00R0100 V02N0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H06W0103\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02W0001\narc: V00T0100 H02W0101\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 E1_H02W0301\narc: E1_H01E0101 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: A3 V00T0000\narc: A7 N1_V02S0301\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 V02N0501\narc: B7 N1_V02S0701\narc: C3 H02E0601\narc: C4 E1_H02W0401\narc: C5 H02W0601\narc: C7 V02S0201\narc: CE0 H00L0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D4 H02E0201\narc: D5 V00B0000\narc: D7 W1_H02E0001\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M0 E1_H02W0601\narc: M1 H00L0100\narc: M2 E1_H02W0601\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V02N0301 Q1\narc: N3_V06N0303 F6\narc: S3_V06S0303 F5\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 1100000011001111\nword: SLICEC.K1.INIT 0000000011111100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R26C38:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0003 V01N0001\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 H02W0201\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0501 S1_V02N0401\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02N0001\narc: V00T0100 E1_H02W0101\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0601 N1_V01S0000\narc: N1_V02N0301 W3_H06E0003\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0103 V01N0101\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0303 E3_H06W0303\narc: A1 W1_H02E0701\narc: B1 H00R0100\narc: B2 W1_H02E0301\narc: B4 V02N0501\narc: B5 V02N0501\narc: C1 N1_V02S0601\narc: C2 V02N0601\narc: C4 H02W0401\narc: C5 V02S0201\narc: CE2 H00L0000\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D2 W1_H02E0001\narc: D3 V00T0100\narc: D4 F2\narc: D5 V02N0401\narc: E1_H01E0101 F5\narc: E1_H02E0601 Q6\narc: E3_H06E0103 F1\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: M2 V00B0000\narc: M6 H02E0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: V01S0100 Q6\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0011011100111111\nword: SLICEC.K0.INIT 1100000011001111\nword: SLICEC.K1.INIT 0000000011111100\nword: SLICEB.K0.INIT 1111000000110011\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R26C39:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0203 N3_V06S0203\narc: E3_H06E0303 H01E0101\narc: H00L0000 E1_H02W0001\narc: H00L0100 S1_V02N0101\narc: H00R0000 E1_H02W0401\narc: H00R0100 H02W0501\narc: H01W0100 E3_H06W0303\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 H02W0401\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02S0501\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 N1_V01S0000\narc: N1_V02N0501 W3_H06E0303\narc: S3_V06S0103 W3_H06E0103\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0203 E1_H02W0701\narc: A1 H02E0701\narc: A3 V00B0000\narc: A4 N1_V02S0301\narc: A5 H02W0701\narc: B1 V02S0301\narc: B3 V02N0101\narc: B4 V02N0701\narc: B5 E1_H02W0301\narc: B6 W1_H02E0301\narc: C1 H02W0601\narc: C2 H00L0000\narc: C3 W1_H02E0601\narc: C4 E1_H01E0101\narc: C5 E1_H02W0401\narc: C6 V00T0100\narc: C7 W1_H02E0601\narc: D1 H00R0000\narc: D2 H02W0201\narc: D3 V01S0100\narc: D4 H01W0000\narc: D5 H00L0100\narc: D6 H00R0100\narc: D7 W1_H02E0001\narc: E1_H01E0001 F3\narc: E1_H01E0101 F0\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F5\narc: M0 V00T0000\narc: M6 H02W0401\narc: V01S0000 F2\narc: V01S0100 F6\narc: W1_H02W0601 F4\nword: SLICEC.K0.INIT 0011001100110010\nword: SLICEC.K1.INIT 1100010010000000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1000000011111111\nword: SLICED.K0.INIT 0000110000111111\nword: SLICED.K1.INIT 1111000011111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0110101110110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R26C3:PLC2\narc: E1_H02E0401 N3_V06S0203\narc: H00R0000 E1_H02W0401\narc: H00R0100 H02W0501\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0401 N3_V06S0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02W0701\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 H01E0101\narc: D2 W1_H02E0001\narc: D3 E1_H02W0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 H02E0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V02N0401 Q4\narc: N3_V06N0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R26C40:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 W1_H02E0601\narc: H00L0000 V02N0001\narc: H00L0100 H02E0101\narc: H00R0000 V02N0601\narc: H00R0100 E1_H02W0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 H06W0303\narc: V00B0000 S1_V02N0001\narc: V00T0000 E1_H02W0201\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 V02N0701\narc: E1_H02E0001 W3_H06E0003\narc: S1_V02S0201 W3_H06E0103\narc: W3_H06W0103 N3_V06S0103\narc: W3_H06W0003 E3_H06W0003\narc: A0 N1_V02S0501\narc: A1 H00R0000\narc: B0 V00B0000\narc: B1 W1_H02E0301\narc: B2 V02N0101\narc: B4 N1_V02S0701\narc: B7 E1_H02W0301\narc: C0 S1_V02N0401\narc: C1 H00L0000\narc: C2 H00L0100\narc: C3 H02E0601\narc: C4 E1_H01E0101\narc: C5 H02W0601\narc: C6 S1_V02N0201\narc: C7 V00T0100\narc: D0 V02N0001\narc: D1 V02S0001\narc: D2 N1_V02S0201\narc: D3 V00T0100\narc: D4 V02N0401\narc: D5 W1_H02E0001\narc: D6 H00R0100\narc: D7 V02S0401\narc: E1_H01E0001 F5\narc: E1_H01E0101 F5\narc: E3_H06E0103 F2\narc: E3_H06E0303 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F5\narc: H01W0100 F0\narc: M2 V00T0000\narc: M6 E1_H02W0401\narc: N1_V01N0001 F6\narc: N3_V06N0103 F2\narc: S1_V02S0501 F5\narc: V01S0000 F2\narc: V01S0100 F1\narc: W3_H06W0203 F4\nword: SLICEC.K0.INIT 0000001100001111\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 1110001010101010\nword: SLICEA.K1.INIT 1111111110000000\nword: SLICEB.K0.INIT 1111001111000000\nword: SLICEB.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 0000000000110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R26C41:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V06N0103\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0303 V01N0101\narc: H00L0000 W1_H02E0001\narc: H00L0100 H02E0301\narc: H00R0000 V02N0601\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 V06N0003\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0501 W3_H06E0303\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A1 V02N0501\narc: A5 E1_H02W0701\narc: B1 V00B0000\narc: B2 V02S0301\narc: B3 V02S0301\narc: B5 N1_V02S0701\narc: B6 V00B0100\narc: C0 N1_V02S0401\narc: C1 H00L0000\narc: C2 V02N0601\narc: C3 H02E0401\narc: C5 S1_V02N0201\narc: C6 V00T0100\narc: C7 V02N0001\narc: CE0 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 F0\narc: D2 V02S0001\narc: D3 H00R0000\narc: D5 H02E0001\narc: D6 W1_H02E0201\narc: D7 H00L0100\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F6\narc: E1_H02E0001 Q0\narc: E1_H02E0701 F5\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q0\narc: H01W0100 F6\narc: M2 V00T0000\narc: M6 N1_V01N0101\narc: MUXCLK0 CLK0\narc: N1_V01N0101 Q0\narc: N1_V02N0201 F2\narc: N3_V06N0003 F0\narc: N3_V06N0103 F1\narc: S3_V06S0003 Q0\narc: V00T0000 Q0\narc: V01S0000 Q0\narc: V01S0100 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000010101010\nword: SLICEA.K0.INIT 1111000011111111\nword: SLICEA.K1.INIT 0000001001010111\nword: SLICEB.K0.INIT 1111001111000000\nword: SLICEB.K1.INIT 1111001111000000\nword: SLICED.K0.INIT 1111110000110000\nword: SLICED.K1.INIT 0000111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R26C42:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0103 H01E0101\narc: H00L0000 H02E0001\narc: H00L0100 V02S0101\narc: H00R0000 N1_V02S0601\narc: H00R0100 S1_V02N0701\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0701 H06E0203\narc: N3_V06N0103 E1_H01W0100\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 H06W0203\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00B0100 H02E0501\narc: V00T0000 H02E0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 S1_V02N0501\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0103 E3_H06W0003\narc: A2 V00B0000\narc: A3 V02N0501\narc: B1 V02N0101\narc: B2 H00R0000\narc: B3 H00L0000\narc: B4 V02S0501\narc: B5 V02S0501\narc: B6 V02S0501\narc: B7 V02S0501\narc: C0 N1_V01N0001\narc: C1 V02S0601\narc: C2 H02W0401\narc: C3 H00L0100\narc: C4 E1_H01E0101\narc: C5 W1_H02E0601\narc: C6 V00T0100\narc: C7 V00T0100\narc: CE1 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 H02E0201\narc: D2 V00B0100\narc: D3 F0\narc: D4 H02W0201\narc: D5 H02W0201\narc: D6 H02W0001\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: E3_H06E0003 F3\narc: E3_H06E0203 F4\narc: E3_H06E0303 F6\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q2\narc: M0 H01E0001\narc: M4 V00T0000\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q2\narc: N1_V02N0601 F6\narc: S1_V02S0001 Q2\narc: S3_V06S0003 F3\narc: V01S0000 F3\narc: V01S0100 Q2\narc: W1_H02W0601 F4\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 1100110011001110\nword: SLICEB.K1.INIT 0001000011111111\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 1111001111000000\nword: SLICED.K0.INIT 1111001111000000\nword: SLICED.K1.INIT 1111110000110000\nword: SLICEA.K0.INIT 0000111111111111\nword: SLICEA.K1.INIT 0000110000111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R26C43:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 V02N0601\narc: E3_H06E0103 V01N0101\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 V02N0001\narc: H00L0100 N1_V02S0101\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 H02E0401\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 H06W0003\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 H06E0103\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 W1_H02E0601\narc: V00B0100 W1_H02E0501\narc: V00T0100 V02S0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 V02S0401\narc: W1_H02W0701 N3_V06S0203\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: A1 H00L0000\narc: A2 H02W0501\narc: A3 H02E0701\narc: A4 V02S0101\narc: A5 V00T0100\narc: A6 H02E0701\narc: A7 H00R0000\narc: B0 W1_H02E0101\narc: B1 V00B0000\narc: B2 H00R0100\narc: B3 V02S0301\narc: B4 V00B0100\narc: B5 V00B0100\narc: B6 V00T0000\narc: B7 S1_V02N0701\narc: C0 N1_V01N0001\narc: C1 S1_V02N0401\narc: C2 V02N0401\narc: C3 H00L0000\narc: C4 V02S0001\narc: C5 H02W0601\narc: C6 E1_H02W0401\narc: C7 H02W0401\narc: CE1 H02E0101\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 H02W0001\narc: D2 H02E0001\narc: D3 S1_V02N0001\narc: D4 H02W0201\narc: D5 V02S0401\narc: D6 N1_V02S0401\narc: D7 V02N0601\narc: E1_H01E0001 F5\narc: E1_H01E0101 Q2\narc: E1_H02E0001 Q2\narc: E1_H02E0701 F7\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H01W0000 F0\narc: H01W0100 Q4\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q2\narc: N1_V02N0601 F6\narc: N3_V06N0003 F3\narc: N3_V06N0303 F6\narc: S1_V02S0101 F3\narc: S1_V02S0201 Q2\narc: S1_V02S0301 F3\narc: S3_V06S0203 Q4\narc: V00T0000 Q2\narc: V01S0000 Q2\narc: V01S0100 Q4\narc: W3_H06W0003 F3\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q4\narc: W3_H06W0303 F6\nword: SLICEC.K0.INIT 0000001011111111\nword: SLICEC.K1.INIT 0001010111111111\nword: SLICEB.K0.INIT 1000111110000000\nword: SLICEB.K1.INIT 0101000101000000\nword: SLICED.K0.INIT 1001000110000000\nword: SLICED.K1.INIT 0000001100000101\nword: SLICEA.K0.INIT 0000000011110011\nword: SLICEA.K1.INIT 1001001000101111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R26C44:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V06S0303\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 S3_V06N0103\narc: H00L0100 V02N0301\narc: H00R0000 H02W0601\narc: H00R0100 E1_H02W0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 V01N0101\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 H06W0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 H02E0101\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 H02E0501\narc: S1_V02S0701 H01E0101\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V02S0601\narc: V00T0000 V02S0601\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 N3_V06S0303\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0401 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: A0 H00L0100\narc: A1 H00L0100\narc: A2 H00L0100\narc: A3 H00L0100\narc: A4 S1_V02N0301\narc: A5 V02S0101\narc: A6 W1_H02E0701\narc: B0 H02W0101\narc: B1 H02W0101\narc: B2 H02W0101\narc: B3 H02W0101\narc: B4 H00R0000\narc: B5 H02W0301\narc: B6 H01E0101\narc: B7 V00B0000\narc: C0 E1_H02W0601\narc: C1 E1_H02W0601\narc: C2 E1_H02W0601\narc: C3 E1_H02W0601\narc: C4 V00T0100\narc: C5 H02E0401\narc: C6 V02S0201\narc: C7 H02E0601\narc: CLK1 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02N0001\narc: D2 V02N0001\narc: D3 V02N0001\narc: D4 H02W0001\narc: D5 S1_V02N0401\narc: D6 V02N0401\narc: D7 H00R0100\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F6\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: LSR1 V00T0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N3_V06N0303 F6\narc: S1_V02S0201 Q0\narc: V00B0000 F6\narc: V01S0000 Q3\narc: V01S0100 Q1\narc: W3_H06W0303 F6\nword: SLICED.K0.INIT 0101010000010000\nword: SLICED.K1.INIT 0011000000111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R26C45:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 V02S0601\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 W1_H02E0701\narc: E3_H06E0303 H01E0101\narc: H00L0000 N1_V02S0201\narc: H00L0100 S1_V02N0301\narc: H00R0100 V02N0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 H01E0001\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00B0100 H02E0501\narc: V00T0000 H02W0201\narc: V00T0100 E1_H02W0301\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V06N0103\narc: W1_H02W0301 V01N0101\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V06S0303\narc: E1_H02E0501 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: N3_V06N0003 W3_H06E0003\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\narc: A0 H00L0000\narc: A1 H00L0000\narc: A2 N1_V02S0701\narc: A3 N1_V02S0701\narc: A4 V02S0301\narc: A5 V00T0000\narc: B0 S1_V02N0101\narc: B1 S1_V02N0101\narc: B2 S1_V02N0101\narc: B3 S1_V02N0101\narc: B4 V02S0701\narc: B5 V02N0501\narc: C0 H02W0601\narc: C1 H02W0601\narc: C2 H02W0601\narc: C3 H02W0601\narc: C4 V00B0100\narc: C5 W1_H02E0401\narc: CE3 H00R0100\narc: CLK1 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 S1_V02N0001\narc: D2 S1_V02N0001\narc: D3 S1_V02N0001\narc: D4 V00B0000\narc: D5 H00L0100\narc: E1_H01E0101 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR1 H02E0301\narc: M6 V00T0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXCLK3 CLK1\narc: N1_V01N0101 Q3\narc: S1_V02S0201 Q2\narc: S3_V06S0003 Q0\narc: V01S0000 Q1\narc: W1_H02W0401 Q6\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R26C46:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 H01E0101\narc: E3_H06E0203 W1_H02E0401\narc: H00L0100 V02N0101\narc: H00R0000 V02N0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 H02W0701\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02W0601\narc: V00B0100 V02S0101\narc: V00T0100 V02N0701\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 N3_V06S0203\narc: E1_H02E0201 W3_H06E0103\narc: N3_V06N0303 W3_H06E0303\narc: S1_V02S0601 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: A0 V02N0501\narc: B0 H02E0101\narc: B1 E1_H02W0301\narc: B3 N1_V02S0301\narc: B4 N1_V02S0501\narc: B6 V00B0000\narc: C0 V02S0601\narc: C1 H00L0000\narc: C3 V02S0401\narc: C4 H02W0601\narc: C6 N1_V02S0201\narc: CE2 H00R0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 E1_H02W0001\narc: D3 H00R0000\narc: D4 E1_H01W0100\narc: D5 W1_H02E0001\narc: D6 N1_V02S0401\narc: D7 W1_H02E0001\narc: E1_H01E0001 F3\narc: E1_H01E0101 F1\narc: E3_H06E0003 F0\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 F0\narc: H01W0000 F0\narc: H01W0100 Q4\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F0\narc: N3_V06N0003 F0\narc: N3_V06N0203 Q4\narc: S1_V02S0001 F0\narc: V01S0000 Q6\narc: W1_H02W0001 F0\narc: W3_H06W0003 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 0101010000010000\nword: SLICEA.K1.INIT 0011001100001111\nword: SLICEC.K0.INIT 1111111111000000\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1100000011001111\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R26C47:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 V06S0203\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0303 H01E0101\narc: H00R0000 H02W0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0003 V01N0001\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02N0301\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0701 S3_V06N0203\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0101 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A0 H02E0701\narc: A1 H00L0000\narc: A2 H02E0501\narc: A7 H00R0000\narc: B0 E1_H02W0301\narc: B1 H00R0100\narc: B2 W1_H02E0101\narc: B3 V02S0101\narc: B6 V02S0501\narc: B7 N1_V02S0501\narc: C0 H02W0401\narc: C1 V02N0601\narc: C2 V02N0401\narc: C3 H00R0100\narc: C4 V02N0001\narc: C5 S1_V02N0201\narc: C6 H02E0601\narc: C7 S1_V02N0001\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 H02E0201\narc: D2 N1_V02S0201\narc: D3 V00B0100\narc: D4 E1_H02W0201\narc: D5 V00B0000\narc: D6 E1_H02W0001\narc: D7 S1_V02N0401\narc: E1_H01E0001 F2\narc: E1_H01E0101 F3\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H01W0100 F7\narc: LSR0 H02E0301\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F2\narc: N3_V06N0103 F2\narc: V00B0000 F4\narc: V01S0000 F4\narc: V01S0100 F0\narc: W1_H02W0601 F6\narc: W3_H06W0003 F0\narc: W3_H06W0103 F2\narc: W3_H06W0203 F4\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000000011110000\nword: SLICEA.K0.INIT 0000101000001100\nword: SLICEA.K1.INIT 0100011100011101\nword: SLICEB.K0.INIT 1001000110000000\nword: SLICEB.K1.INIT 0011000000111111\nword: SLICED.K0.INIT 1100000011001111\nword: SLICED.K1.INIT 0010001100000001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R26C48:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0103 H01E0101\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02S0301\narc: H00R0000 H02W0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 H02E0101\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 H02E0701\narc: N3_V06N0203 V01N0001\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 H01E0001\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02N0001\narc: V00T0000 H02E0201\narc: V00T0100 S1_V02N0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V01N0101\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V02S0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0001 W3_H06E0003\narc: N3_V06N0003 W3_H06E0003\narc: S1_V02S0201 W3_H06E0103\narc: S1_V02S0501 W3_H06E0303\narc: S1_V02S0701 W3_H06E0203\narc: W3_H06W0003 E1_H02W0001\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A3 H00L0100\narc: B3 W1_H02E0101\narc: B4 V01S0000\narc: B6 V01S0000\narc: C3 H00L0000\narc: C4 V02S0201\narc: C6 H02E0601\narc: CE0 H02W0101\narc: CLK0 G_HPBX0000\narc: D2 H02E0001\narc: D3 V00T0100\narc: D4 H00R0100\narc: D5 H01W0000\narc: D6 W1_H02E0001\narc: D7 H01W0000\narc: E1_H01E0101 F6\narc: E1_H02E0401 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F1\narc: H01W0100 F1\narc: M0 V00T0000\narc: M1 H00R0000\narc: M2 V00T0000\narc: M4 E1_H02W0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: N1_V01N0101 F1\narc: V01S0000 Q1\nword: SLICED.K0.INIT 0011001100001111\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0011001100001111\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1100000011001000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R26C49:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V02N0501\narc: H00R0000 H02E0401\narc: H00R0100 N1_V02S0701\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0601 H06E0303\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0100 H02W0701\narc: V00T0000 V02N0401\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 V01N0101\narc: W1_H02W0601 E1_H02W0601\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: B0 H00R0100\narc: B2 H00R0100\narc: B4 H02W0301\narc: B5 V01S0000\narc: B6 V02N0701\narc: C0 W1_H02E0401\narc: C2 H02W0601\narc: C4 V02N0001\narc: C5 E1_H01E0101\narc: C6 H02E0601\narc: C7 V00T0000\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 E1_H02W0201\narc: D2 H01E0101\narc: D3 E1_H02W0201\narc: D4 V02N0601\narc: D5 V02S0401\narc: D6 E1_H02W0001\narc: D7 S1_V02N0401\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: E1_H02E0601 F6\narc: E3_H06E0103 Q2\narc: E3_H06E0303 F5\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: H01W0100 F4\narc: M0 V00T0100\narc: M2 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q0\narc: N1_V02N0001 Q0\narc: N3_V06N0203 F4\narc: V01S0000 F4\narc: V01S0100 F7\narc: W1_H02W0701 F7\narc: W3_H06W0003 Q0\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 0000001111001111\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEC.K0.INIT 0000000000001100\nword: SLICEC.K1.INIT 0000001111110011\nword: SLICEB.K0.INIT 1100000011001111\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1100000011001111\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R26C4:PLC2\narc: H00L0000 E1_H02W0001\narc: H00R0000 S1_V02N0401\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 E3_H06W0303\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 E3_H06W0303\narc: V00B0000 H02E0401\narc: V00B0100 V02S0301\narc: V00T0100 V02N0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0701 V02S0701\narc: CE0 E1_H02W0101\narc: CE1 H00L0000\narc: CE2 H00R0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q6\narc: M0 V00T0100\narc: M2 V00B0000\narc: M4 H02E0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: N1_V02N0201 Q2\narc: N1_V02N0401 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R26C50:PLC2\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0303 H01E0101\narc: H00L0000 W1_H02E0201\narc: H00R0100 H02E0501\narc: N1_V02N0301 H06E0003\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H06E0203\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 N1_V02S0201\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0601\narc: V00T0100 N1_V02S0501\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0001 W3_H06E0003\narc: N3_V06N0103 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: A4 E1_H02W0701\narc: A7 V02S0101\narc: B1 V00T0000\narc: B4 E1_H02W0101\narc: B5 H00L0000\narc: B7 H02W0301\narc: C0 S1_V02N0601\narc: C1 V02S0601\narc: C2 H02E0401\narc: C3 H02E0401\narc: C4 V00B0100\narc: C5 V02S0201\narc: C6 V02N0001\narc: C7 H01E0001\narc: D0 H00R0000\narc: D1 V02N0201\narc: D2 V00T0100\narc: D3 H00R0000\narc: D4 V02N0401\narc: D5 V00B0000\narc: D6 H00R0100\narc: D7 E1_H01W0100\narc: E1_H01E0001 F0\narc: E1_H01E0101 F6\narc: E1_H02E0101 F1\narc: E1_H02E0401 F6\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H01W0000 F6\narc: H01W0100 F4\narc: N1_V01N0001 F2\narc: N1_V01N0101 F7\narc: N1_V02N0201 F0\narc: N3_V06N0003 F3\narc: S1_V02S0401 F6\narc: S1_V02S0501 F5\narc: V00B0100 F5\narc: V00T0000 F0\narc: V01S0100 F3\narc: W1_H02W0001 F0\narc: W3_H06W0003 F3\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0000101000011011\nword: SLICEC.K1.INIT 1111110000110000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000001111110011\nword: SLICED.K0.INIT 0000000000001111\nword: SLICED.K1.INIT 0111000001111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R26C51:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0303 H01E0101\narc: H00R0000 H02E0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0203 H01E0001\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: V00B0000 H02E0401\narc: V00B0100 E1_H02W0701\narc: V00T0000 H02W0201\narc: V00T0100 V02S0501\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0301 H01E0101\narc: W1_H02W0601 V02N0601\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0001 W3_H06E0003\narc: H01W0100 W3_H06E0303\narc: N1_V02N0001 W3_H06E0003\narc: N3_V06N0003 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: A1 H00R0000\narc: B0 F1\narc: B1 V00B0000\narc: C0 E1_H01W0000\narc: C1 V02S0601\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 E1_H02W0201\narc: E1_H01E0001 F0\narc: E1_H02E0301 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: M2 V00B0100\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0203 Q4\narc: S3_V06S0303 Q6\narc: V01S0000 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111110000001100\nword: SLICEA.K1.INIT 0111000001111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R26C52:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 H01E0001\narc: H00L0000 W1_H02E0201\narc: H00L0100 V02N0101\narc: H00R0000 H02E0401\narc: H00R0100 W1_H02E0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 H02W0501\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 H06E0203\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0501 N1_V02S0401\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 H02E0401\narc: V00B0100 V02S0101\narc: V00T0000 W1_H02E0201\narc: V00T0100 W1_H02E0101\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0101 W3_H06E0103\narc: H01W0000 W3_H06E0103\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: B2 H00L0000\narc: B3 H00L0000\narc: B4 H00R0000\narc: B5 H02W0101\narc: B6 V00B0000\narc: B7 V00T0000\narc: C2 H00L0100\narc: C3 H02W0601\narc: C4 V00T0100\narc: C5 V02S0201\narc: C6 V00T0100\narc: C7 E1_H02W0601\narc: CE0 V02N0201\narc: CLK0 G_HPBX0000\narc: D2 E1_H02W0001\narc: D3 V02N0001\narc: D4 E1_H02W0001\narc: D5 V02N0401\narc: D6 H00R0100\narc: D7 V02N0601\narc: E1_H01E0001 F6\narc: E1_H01E0101 F2\narc: E1_H02E0001 F2\narc: E1_H02E0501 F7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F5\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F3\narc: N1_V02N0401 F4\narc: N1_V02N0601 F6\narc: S1_V02S0201 Q0\narc: V01S0000 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111001111000000\nword: SLICED.K1.INIT 1111001111000000\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 1111001111000000\nword: SLICEB.K0.INIT 1111001111000000\nword: SLICEB.K1.INIT 1111001111000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R26C53:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V02N0701\narc: H00L0000 W1_H02E0001\narc: H00R0000 H02W0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 H02W0701\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0501 H06E0303\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 W1_H02E0601\narc: V00B0100 H02W0701\narc: V00T0000 W1_H02E0001\narc: V00T0100 H02W0301\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 V02S0701\narc: E1_H02E0501 W3_H06E0303\narc: H01W0000 W3_H06E0103\narc: S1_V02S0601 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: A7 H00L0000\narc: B0 E1_H02W0101\narc: B2 H00R0000\narc: B3 H02E0101\narc: B4 V02N0701\narc: B6 V00B0100\narc: B7 V02N0701\narc: C0 V02S0601\narc: C2 H00L0100\narc: C3 E1_H02W0601\narc: C4 V02S0201\narc: C6 H01E0001\narc: C7 F6\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 F2\narc: D2 H01E0101\narc: D3 H02E0201\narc: D4 V02N0601\narc: D5 H02W0201\narc: D6 H02E0001\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: M0 V00T0000\narc: M4 V00T0100\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F0\narc: N1_V01N0101 F7\narc: N1_V02N0601 Q4\narc: S1_V02S0401 F6\narc: V01S0100 F2\nword: SLICEB.K0.INIT 1111001111000000\nword: SLICEB.K1.INIT 1111110000110000\nword: SLICED.K0.INIT 1111110000110000\nword: SLICED.K1.INIT 0010000000110001\nword: SLICEC.K0.INIT 0000001111001111\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111001111000000\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R26C54:PLC2\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0501 V02N0501\narc: H00L0000 V02N0201\narc: H00R0000 H02E0401\narc: H00R0100 W1_H02E0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 H06E0003\narc: N1_V02N0601 V01N0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\narc: V00T0000 H02W0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0601 V02N0601\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0701 W3_H06E0203\narc: N3_V06N0003 W3_H06E0003\narc: N3_V06N0203 W3_H06E0203\narc: N3_V06N0303 W3_H06E0303\narc: S1_V02S0701 W3_H06E0203\narc: W1_H02W0301 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\narc: A3 V02S0501\narc: A4 V00T0000\narc: B0 H02E0101\narc: B1 H02W0101\narc: B2 W1_H02E0101\narc: B3 E1_H02W0301\narc: B4 H00L0000\narc: B5 H02W0101\narc: B6 W1_H02E0101\narc: B7 W1_H02E0101\narc: C0 V02N0401\narc: C1 W1_H02E0601\narc: C2 N1_V01N0001\narc: C3 E1_H02W0601\narc: C4 V00B0100\narc: C5 H01E0001\narc: C6 V00T0100\narc: C7 V00T0100\narc: D0 E1_H02W0001\narc: D1 S1_V02N0001\narc: D2 V02S0201\narc: D3 H00R0000\narc: D4 S1_V02N0401\narc: D5 H02W0201\narc: D6 H00R0100\narc: D7 H02E0201\narc: E1_H01E0001 F7\narc: E1_H02E0001 F2\narc: E3_H06E0203 F4\narc: E3_H06E0303 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: N1_V01N0001 F3\narc: N1_V02N0201 F0\narc: N1_V02N0401 F6\narc: V00B0100 F5\narc: V01S0000 F1\nword: SLICEA.K0.INIT 1111110000110000\nword: SLICEA.K1.INIT 1111001111000000\nword: SLICEC.K0.INIT 0000001000010011\nword: SLICEC.K1.INIT 1111110000110000\nword: SLICED.K0.INIT 1111001111000000\nword: SLICED.K1.INIT 1111110000110000\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 0111000001111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R26C55:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 S3_V06N0003\narc: H00L0000 E1_H02W0001\narc: H00R0000 H02E0401\narc: H00R0100 V02N0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0501 E1_H01W0100\narc: N3_V06N0103 H06E0103\narc: S1_V02S0001 H01E0001\narc: S1_V02S0201 H02W0201\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 H02E0401\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02W0201\narc: V00T0100 H02W0101\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 H01E0001\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: A0 H00L0000\narc: B0 H00R0100\narc: B1 V00B0000\narc: B2 H00R0000\narc: B3 H02E0301\narc: B4 H00R0000\narc: B5 E1_H02W0101\narc: B6 V00T0000\narc: B7 V00B0000\narc: C0 F4\narc: C1 E1_H02W0401\narc: C2 N1_V01N0001\narc: C3 H02W0401\narc: C4 V01N0101\narc: C5 F4\narc: C6 W1_H02E0601\narc: C7 F6\narc: D0 V01S0100\narc: D1 S1_V02N0001\narc: D2 V00T0100\narc: D3 V00B0100\narc: D4 H02E0001\narc: D5 H00L0100\narc: D6 V02N0601\narc: D7 H02E0001\narc: E1_H01E0001 F6\narc: E1_H01E0101 F1\narc: E1_H02E0201 F2\narc: E1_H02E0301 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: N1_V01N0001 F3\narc: N1_V01N0101 F7\narc: N1_V02N0601 F4\narc: N1_V02N0701 F7\narc: N3_V06N0303 F5\narc: V01S0000 F0\narc: V01S0100 F1\nword: SLICEA.K0.INIT 0000100001001100\nword: SLICEA.K1.INIT 1111110000110000\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 1111001111000000\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 1111110000110000\nword: SLICED.K0.INIT 1111001111000000\nword: SLICED.K1.INIT 1111001111000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R26C56:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0701 W1_H02E0701\narc: H00L0000 W1_H02E0201\narc: H00L0100 H02W0301\narc: H00R0000 H02W0601\narc: N1_V02N0001 H02W0001\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 H01E0101\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N1_V02S0501\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V01S0100\narc: V00B0000 V02N0201\narc: V00B0100 W1_H02E0501\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02N0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: N1_V02N0601 W3_H06E0303\narc: S1_V02S0201 W3_H06E0103\narc: S1_V02S0601 W3_H06E0303\narc: S3_V06S0303 W3_H06E0303\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0401 W3_H06E0203\narc: W1_H02W0501 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: B0 V02N0101\narc: B1 V00T0000\narc: B2 H02W0101\narc: B4 V02N0701\narc: B6 W1_H02E0301\narc: B7 H02E0101\narc: C0 H00L0000\narc: C1 H02E0601\narc: C2 V02N0601\narc: C4 V02S0001\narc: C6 E1_H02W0401\narc: C7 F6\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H02E0001\narc: D2 V00B0100\narc: D3 H00R0000\narc: D4 V00B0000\narc: D5 H02W0201\narc: D6 W1_H02E0201\narc: D7 E1_H02W0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: E1_H02E0601 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F0\narc: H01W0100 Q4\narc: M2 V00T0100\narc: M4 H02E0401\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F2\narc: N1_V01N0101 F7\narc: N1_V02N0201 F0\narc: V01S0100 F1\nword: SLICED.K0.INIT 1111110000110000\nword: SLICED.K1.INIT 1111001111000000\nword: SLICEA.K0.INIT 1111110000110000\nword: SLICEA.K1.INIT 0011000000111111\nword: SLICEC.K0.INIT 0000110000111111\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 0000001111001111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R26C57:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 H01E0101\narc: H00L0000 W1_H02E0201\narc: H00L0100 V02N0301\narc: H00R0000 V02N0401\narc: H00R0100 W1_H02E0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0203 H06E0203\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: V00B0100 V02S0301\narc: V00T0000 V02S0401\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 V01N0001\narc: E1_H02E0301 W3_H06E0003\narc: H01W0100 W3_H06E0303\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: S1_V02S0001 W3_H06E0003\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: B0 V00T0000\narc: B1 V02S0301\narc: B2 H00R0100\narc: B4 W1_H02E0101\narc: B5 H02E0101\narc: B6 V00B0100\narc: B7 V02N0701\narc: C0 N1_V01N0001\narc: C1 H00L0000\narc: C2 F6\narc: C4 H02E0601\narc: C5 H01E0001\narc: C6 F4\narc: C7 F6\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 H00R0000\narc: D2 S1_V02N0001\narc: D3 H02W0201\narc: D4 H01W0000\narc: D5 V02S0601\narc: D6 W1_H02E0201\narc: D7 E1_H01W0100\narc: E1_H01E0001 F5\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: M2 E1_H02W0601\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F1\narc: N1_V02N0201 F0\narc: N1_V02N0701 F7\narc: V01S0000 F4\narc: W3_H06W0103 Q2\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 1111110000110000\nword: SLICED.K0.INIT 1111001111000000\nword: SLICED.K1.INIT 1111110000110000\nword: SLICEA.K0.INIT 1111110000110000\nword: SLICEA.K1.INIT 1111001111000000\nword: SLICEB.K0.INIT 0000110000111111\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R26C58:PLC2\narc: H00L0000 W1_H02E0201\narc: H00L0100 V02S0301\narc: H00R0000 V02N0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 H01E0001\narc: N3_V06N0003 H06E0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0601\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02N0401\narc: V00T0100 H02E0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0701 H01E0101\narc: N1_V02N0701 W3_H06E0203\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: A1 W1_H02E0501\narc: B0 V00T0000\narc: B1 H02E0301\narc: B3 H00R0000\narc: B4 H00L0000\narc: B5 H02E0301\narc: B7 V00B0100\narc: C0 V02N0601\narc: C1 V02N0601\narc: C3 V02N0601\narc: C4 V02N0201\narc: C5 F4\narc: C7 S1_V02N0001\narc: D0 V02N0001\narc: D1 V02S0201\narc: D3 V01S0100\narc: D4 V00B0000\narc: D5 H00R0100\narc: D6 H02E0201\narc: D7 H00L0100\narc: E1_H01E0001 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: H01W0100 F1\narc: M6 V00T0100\narc: N1_V01N0001 F5\narc: N1_V02N0401 F4\narc: S1_V02S0701 F5\narc: V01S0000 F1\narc: V01S0100 F6\narc: W1_H02W0201 F0\narc: W3_H06W0003 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100000011110011\nword: SLICEA.K0.INIT 1100000011110011\nword: SLICEA.K1.INIT 0001111100001110\nword: SLICED.K0.INIT 1111111100000000\nword: SLICED.K1.INIT 0011111100001100\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 1111110000110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R26C59:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 V06S0303\narc: N1_V02N0101 H06E0103\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 N3_V06S0303\narc: S1_V02S0001 N3_V06S0003\narc: W1_H02W0201 H01E0001\narc: W1_H02W0601 V02N0601\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0203 E3_H06W0203\n\n.tile R26C5:PLC2\narc: H00L0100 E1_H02W0101\narc: H00R0000 H02W0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0601 S3_V06N0303\narc: V00B0000 N1_V02S0001\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0401 E1_H02W0101\narc: D0 H00R0000\narc: D1 E1_H02W0201\narc: D2 H02W0201\narc: D3 V02N0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0000\narc: M1 H00L0100\narc: M2 V00B0000\narc: M3 H00R0100\narc: M4 V00B0000\narc: M5 H00L0100\narc: M6 V00B0000\narc: N1_V02N0101 F3\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R26C60:PLC2\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\narc: W1_H02W0401 V02N0401\narc: W3_H06W0203 E1_H01W0000\n\n.tile R26C61:PLC2\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0701 H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0203 W3_H06E0103\n\n.tile R26C62:PLC2\narc: E1_H02E0101 V06S0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 N3_V06S0303\narc: H01W0000 W3_H06E0103\n\n.tile R26C63:PLC2\narc: N1_V02N0101 H02E0101\narc: S3_V06S0103 N3_V06S0103\n\n.tile R26C64:PLC2\narc: E3_H06E0303 V06S0303\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 N3_V06S0203\narc: E3_H06E0003 W3_H06E0303\n\n.tile R26C65:PLC2\narc: E1_H02E0701 V06S0203\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0301 W3_H06E0003\narc: W3_H06W0203 E3_H06W0203\n\n.tile R26C66:PLC2\narc: N1_V02N0701 H02E0701\narc: S3_V06S0103 N3_V06S0103\n\n.tile R26C67:PLC2\narc: N1_V02N0001 H06E0003\narc: N1_V02N0601 H06E0303\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0701 W3_H06E0203\n\n.tile R26C68:PLC2\narc: N1_V02N0501 H01E0101\n\n.tile R26C69:PLC2\narc: E1_H02E0301 V02S0301\narc: E1_H02E0701 V06S0203\n\n.tile R26C6:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 V06S0203\narc: H00L0000 S1_V02N0201\narc: H00R0000 S1_V02N0401\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0401 V01N0001\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0601 E1_H02W0601\narc: V00B0000 E1_H02W0601\narc: V00T0000 V02N0601\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 H00L0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: H01W0000 Q6\narc: M0 V00T0000\narc: M2 E1_H02W0601\narc: M4 V00B0000\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0201 Q0\narc: W1_H02W0201 Q2\narc: W1_H02W0601 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R26C7:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 V02S0001\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 V02N0001\narc: H00R0000 E1_H02W0401\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 N3_V06S0003\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02E0701\narc: V00T0000 H02E0201\narc: V00T0100 H02W0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0401 V06S0203\narc: A6 H02E0501\narc: A7 H02W0501\narc: B6 E1_H02W0101\narc: B7 V00B0000\narc: C6 V02S0201\narc: C7 E1_H01E0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 V00T0100\narc: D2 H02W0001\narc: D3 H02W0201\narc: D6 V01N0001\narc: D7 V02N0601\narc: E1_H01E0001 Q7\narc: E1_H02E0101 F1\narc: E3_H06E0203 Q7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: H01W0100 Q7\narc: LSR0 V00B0100\narc: M0 V00T0000\narc: M1 H00L0000\narc: M2 V00T0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F1\narc: N1_V02N0301 F1\narc: N1_V02N0701 Q7\narc: N3_V06N0303 F6\narc: S3_V06S0203 Q7\nword: SLICED.K0.INIT 0000001000110010\nword: SLICED.K1.INIT 1011101100001011\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R26C8:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: H00L0000 N1_V02S0201\narc: H00L0100 H02E0101\narc: H00R0100 V02S0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 E3_H06W0103\narc: S1_V02S0701 N1_V02S0601\narc: V00B0000 V02N0201\narc: V00T0100 H02W0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 V01N0001\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V06S0303\narc: W3_H06W0103 S3_V06N0103\narc: C3 H00L0100\narc: C7 H01E0001\narc: D1 V02N0001\narc: D2 H02E0001\narc: D3 V02N0001\narc: D5 W1_H02E0001\narc: D6 V00B0000\narc: D7 V00B0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00R0100\narc: M2 V00T0100\narc: M3 H00L0000\narc: M4 V00T0100\narc: M5 H00R0100\narc: M6 V00T0100\narc: N1_V02N0301 F3\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000000011110000\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0000000011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R26C9:PLC2\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 S1_V02N0401\narc: H00R0000 W1_H02E0601\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H02W0001\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 S1_V02N0601\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 V02S0201\narc: V00B0100 H02W0501\narc: V00T0000 V02N0601\narc: V00T0100 H02W0301\narc: W1_H02W0101 V02S0101\narc: W1_H02W0401 E1_H02W0401\narc: W3_H06W0103 E3_H06W0003\narc: CE0 H00R0000\narc: CE1 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: H01W0000 Q6\narc: H01W0100 Q4\narc: M0 V00T0100\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0201 Q0\narc: W1_H02W0201 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R27C10:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: H00R0000 V02S0601\narc: N1_V02N0401 S1_V02N0101\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 V01N0101\narc: S3_V06S0203 N1_V01S0000\narc: V00B0100 V02S0301\narc: V00T0000 V02N0401\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0701 N3_V06S0203\narc: N1_V02N0201 W3_H06E0103\narc: CE1 H00R0000\narc: CE2 V02S0601\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: E1_H02E0001 Q2\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R27C11:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 E1_H01W0100\narc: H00R0000 H02E0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0101 H06E0103\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 H06E0203\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02N0301\narc: V00T0000 H02E0001\narc: W1_H02W0301 N3_V06S0003\narc: A0 H02E0501\narc: A1 E1_H01E0001\narc: A2 V02N0701\narc: A3 H01E0001\narc: B0 V00T0000\narc: B1 V00B0000\narc: B2 E1_H02W0301\narc: B3 H00R0000\narc: C0 E1_H02W0601\narc: C1 H02E0401\narc: C2 H00L0000\narc: C3 H00R0100\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 H02W0201\narc: D2 V01S0100\narc: D3 V00T0100\narc: E1_H01E0001 Q6\narc: E1_H02E0401 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H00L0000 F0\narc: H01W0100 Q4\narc: M4 V00B0100\narc: M6 H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F2\narc: V00B0000 Q4\narc: V00T0100 F1\narc: V01S0100 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1101000000000000\nword: SLICEB.K1.INIT 1001000000000000\nword: SLICEA.K0.INIT 1100001101000001\nword: SLICEA.K1.INIT 1100010011110101\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R27C12:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0401 E3_H06W0203\narc: E3_H06E0003 V06S0003\narc: H00R0000 V02N0601\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0701 H06E0203\narc: S1_V02S0101 V01N0101\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 N1_V02S0601\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 V01N0001\narc: A0 H02E0701\narc: A1 E1_H01E0001\narc: B0 W1_H02E0301\narc: B1 V00B0000\narc: C0 H00L0100\narc: C1 W1_H02E0401\narc: CE1 W1_H02E0101\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 H00R0000\narc: E1_H01E0001 Q2\narc: E3_H06E0103 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: H00L0100 F1\narc: H01W0100 Q6\narc: M2 H02E0601\narc: M4 H02W0401\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0401 Q4\narc: V01S0100 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1001000000000000\nword: SLICEA.K1.INIT 1100111101000101\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R27C13:PLC2\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0601 N3_V06S0303\narc: H00L0000 V02N0201\narc: H00L0100 V02N0301\narc: H00R0100 H02W0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 H02W0001\narc: V00T0100 V02N0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 V01N0001\narc: A1 E1_H01E0001\narc: A2 E1_H02W0501\narc: A3 V02S0701\narc: A7 V00T0100\narc: B1 V02N0101\narc: B2 H02W0301\narc: B3 V02N0101\narc: B7 V00T0000\narc: C1 H00R0100\narc: C2 H00L0100\narc: C3 H00R0100\narc: C7 E1_H01E0101\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D2 V00B0100\narc: D3 V02S0001\narc: D7 E1_H01W0100\narc: E1_H01E0001 Q4\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: M4 E1_H02W0401\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F3\narc: V01S0000 F2\narc: W3_H06W0303 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000001000000000\nword: SLICEB.K0.INIT 0101001111111111\nword: SLICEB.K1.INIT 1010100010101010\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111011101110011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R27C14:PLC2\narc: E1_H02E0301 E1_H01W0100\narc: H00L0000 V02N0001\narc: H00L0100 V02S0101\narc: H00R0100 V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 S1_V02N0301\narc: V00T0000 S1_V02N0401\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 E3_H06W0303\narc: A1 E1_H02W0701\narc: A2 E1_H01E0001\narc: A3 H00L0100\narc: B1 V00T0000\narc: B2 H00L0000\narc: B3 V02N0101\narc: B6 V00B0000\narc: C1 V02N0401\narc: C2 H02E0601\narc: C3 E1_H02W0601\narc: C6 W1_H02E0401\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 V02S0001\narc: D3 E1_H02W0001\narc: D6 H00R0100\narc: D7 E1_H02W0201\narc: E1_H01E0001 Q6\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F3\narc: M6 E1_H02W0401\narc: MUXCLK3 CLK0\narc: V00B0000 Q6\narc: V01S0100 Q6\narc: W1_H02W0001 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0101001111111111\nword: SLICEB.K1.INIT 1010100010101010\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R27C15:PLC2\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02S0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 V01N0001\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 H01E0101\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H06E0103\narc: S1_V02S0601 E3_H06W0303\narc: V00B0000 H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 N3_V06S0203\narc: A1 V01N0101\narc: B1 V02N0301\narc: B6 H02E0301\narc: C1 H00L0100\narc: C6 V00T0000\narc: CE1 H00R0000\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D6 V00B0000\narc: D7 N1_V02S0601\narc: E1_H01E0101 Q4\narc: F1 F1_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q6\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0101 F1\narc: V01S0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R27C16:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0501 E3_H06W0303\narc: N1_V02N0101 H02W0101\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0101 V01N0101\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E3_H06W0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 H01E0101\narc: W3_H06W0103 E3_H06W0003\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: LSR0 V00B0000\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R27C17:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0501 S1_V02N0501\narc: H00R0100 H02E0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0103 E3_H06W0103\narc: V00B0100 H02W0701\narc: V00T0100 N1_V02S0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 E1_H02W0401\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0203 Q4\narc: S3_V06S0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R27C18:PLC2\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 H02W0201\narc: H00R0000 S1_V02N0401\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0301 H06W0003\narc: S1_V02S0501 H02W0501\narc: S1_V02S0701 H02W0701\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0201\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02W0201\narc: V00T0100 W1_H02E0101\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0203 E1_H02W0401\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: A1 V02S0501\narc: A6 S1_V02N0101\narc: A7 H02E0501\narc: B1 V02N0101\narc: B2 H01W0100\narc: B4 V01S0000\narc: B6 H02W0101\narc: B7 H02W0101\narc: C1 H00R0100\narc: C2 H00L0000\narc: C4 V00T0000\narc: C6 V00B0100\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D1 V01S0100\narc: D2 H00R0000\narc: D3 V02N0001\narc: D4 S1_V02N0601\narc: D5 H02W0001\narc: D6 H02E0001\narc: D7 H02E0001\narc: E1_H01E0101 Q4\narc: E1_H02E0001 Q2\narc: E1_H02E0201 F0\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0100 Q2\narc: M0 E1_H02W0601\narc: M2 V00T0100\narc: M4 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: V01S0000 Q4\narc: V01S0100 F6\nword: SLICED.K0.INIT 0000001000000000\nword: SLICED.K1.INIT 1010100010101010\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111011101110011\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R27C19:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 H02E0001\narc: H00R0100 H02W0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0401 N1_V02S0101\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0201\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02W0001\narc: V00T0100 V02S0501\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 V06S0303\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0203 E1_H02W0701\narc: A1 V02N0701\narc: A5 V00T0100\narc: A6 H00L0000\narc: A7 H02E0701\narc: B1 N1_V02S0101\narc: B5 H00R0000\narc: B6 H01E0101\narc: B7 V00B0100\narc: C1 H00R0100\narc: C5 H02E0601\narc: C6 S1_V02N0001\narc: C7 V00T0000\narc: CE1 H02W0101\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0001\narc: D5 H00L0100\narc: D6 V02S0601\narc: D7 W1_H02E0001\narc: E3_H06E0203 F4\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H00R0000 F6\narc: H01W0000 F7\narc: H01W0100 Q2\narc: LSR0 E1_H02W0301\narc: M2 V00B0000\narc: M4 H02E0401\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000001000000000\nword: SLICED.K0.INIT 0101001111111111\nword: SLICED.K1.INIT 1010100010101010\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0111011101110011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R27C20:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V02N0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V01N0101\narc: H00L0000 V02S0201\narc: H00L0100 S1_V02N0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 V02N0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 V01N0001\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0001 H06W0003\narc: S1_V02S0301 H01E0101\narc: S1_V02S0501 H01E0101\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 H02W0501\narc: V00T0100 V02N0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 E3_H06W0303\narc: W3_H06W0303 E3_H06W0303\narc: A2 H02E0501\narc: A7 W1_H02E0501\narc: B2 H00L0000\narc: B3 H02E0101\narc: B4 H00R0000\narc: B7 H02W0101\narc: C1 H02E0601\narc: C2 S1_V02N0601\narc: C3 V02N0601\narc: C4 E1_H01E0101\narc: C7 V00T0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: D2 V00B0100\narc: D3 H02W0001\narc: D4 W1_H02E0201\narc: D5 H00L0100\narc: D7 H02E0001\narc: E1_H01E0101 F1\narc: E3_H06E0203 F4\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: LSR1 H02W0301\narc: M4 H02E0401\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N3_V06N0003 F3\narc: N3_V06N0303 F6\narc: S1_V02S0401 Q4\narc: V00T0000 F2\narc: W3_H06W0203 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0001001101011111\nword: SLICEB.K1.INIT 0011001100001111\nword: SLICEC.K0.INIT 1111111111110011\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R27C21:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 N1_V02S0301\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0001 H02W0001\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 V02N0001\narc: V00B0100 V02S0301\narc: V00T0100 V02S0701\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 E3_H06W0203\narc: W3_H06W0003 E1_H02W0301\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A3 H02E0701\narc: A7 H00L0000\narc: B0 V00T0000\narc: B3 H00R0000\narc: B7 H02W0301\narc: C0 V02S0401\narc: C3 H00R0100\narc: C7 E1_H02W0601\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 E1_H02W0001\narc: D3 H02E0201\narc: D7 H02E0001\narc: E3_H06E0103 F2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0100 Q4\narc: M0 V00B0100\narc: M2 N1_V01N0001\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F7\narc: V00T0000 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R27C22:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0701 V02S0701\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 V06S0303\narc: H00R0000 V02S0401\narc: H00R0100 H02W0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 H02E0501\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 E1_H02W0701\narc: V00T0000 S1_V02N0601\narc: V00T0100 H02W0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 E1_H01W0100\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A0 V02S0501\narc: A3 V00T0000\narc: A4 W1_H02E0501\narc: A5 W1_H02E0501\narc: B0 H02E0301\narc: B3 H00R0000\narc: B4 S1_V02N0701\narc: B5 V02N0701\narc: C0 H02W0401\narc: C3 N1_V01S0100\narc: C4 E1_H02W0601\narc: C5 W1_H02E0601\narc: CE0 V02N0201\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 F2\narc: D3 H02E0201\narc: D4 S1_V02N0401\narc: D5 H00R0100\narc: E1_H01E0001 F5\narc: E1_H01E0101 F0\narc: E1_H02E0401 F4\narc: E3_H06E0003 F0\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q0\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 H02E0601\narc: M2 V00B0100\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q6\narc: V01S0000 Q0\narc: W3_H06W0003 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0001001101011111\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111011101110011\nword: SLICEA.K0.INIT 1111111110001111\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R27C23:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 V06S0203\narc: E3_H06E0303 H01E0101\narc: H00L0000 N1_V02S0201\narc: H00L0100 E1_H02W0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 S1_V02N0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 E1_H02W0401\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 E3_H06W0303\narc: S1_V02S0701 N1_V02S0701\narc: V00B0000 V02N0001\narc: V00B0100 E1_H02W0501\narc: V00T0100 H02E0301\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 V06N0303\narc: W1_H02W0601 E1_H02W0301\narc: W3_H06W0303 V06N0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0103\narc: A0 H02E0701\narc: A7 H00R0000\narc: B0 V02S0101\narc: B4 H00L0000\narc: B7 H02W0301\narc: C0 H00R0100\narc: C4 V00T0100\narc: C5 V01N0101\narc: C6 V00T0100\narc: C7 V02N0201\narc: D0 V02S0201\narc: D4 H00L0100\narc: D5 E1_H02W0201\narc: D6 V00B0000\narc: D7 H01W0000\narc: E1_H01E0101 F6\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: M0 V00B0100\narc: M1 V01S0100\narc: M2 V00B0100\narc: N1_V01N0001 F5\narc: N1_V01N0101 F4\narc: N3_V06N0103 F1\narc: N3_V06N0303 F6\narc: S3_V06S0303 F6\narc: V01S0100 F7\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1100000000000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000010011\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R27C24:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 V02N0701\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 V06S0303\narc: H00L0000 H02W0001\narc: H00R0000 H02W0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H06W0203\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 H01E0101\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 W1_H02E0401\narc: V00T0100 V02S0501\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 E1_H02W0701\narc: W3_H06W0203 E1_H02W0701\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A3 V02N0701\narc: A4 N1_V01N0101\narc: A5 N1_V02S0301\narc: A7 V02N0301\narc: B1 H02E0101\narc: B3 V02N0101\narc: B4 V01S0000\narc: B5 H02E0101\narc: B7 E1_H02W0101\narc: C0 N1_V01S0100\narc: C1 N1_V01N0001\narc: C3 H00L0000\narc: C4 V00B0100\narc: C5 V02N0201\narc: C6 V01N0101\narc: C7 F6\narc: D0 E1_H02W0201\narc: D1 V02N0201\narc: D3 H00R0000\narc: D4 V00B0000\narc: D5 H02E0201\narc: D6 H00R0100\narc: D7 F0\narc: E1_H01E0001 F1\narc: E1_H01E0101 F6\narc: E1_H02E0201 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M2 V00T0100\narc: N1_V01N0001 F0\narc: N1_V01N0101 F2\narc: N3_V06N0203 F4\narc: V00B0100 F5\narc: V01S0000 F7\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000001100001111\nword: SLICEC.K0.INIT 0100000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0000000000000111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R27C25:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V06S0303\narc: E3_H06E0203 S3_V06N0203\narc: H00L0100 V02N0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 W1_H02E0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02E0701\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0201 H06W0103\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02W0401\narc: V00B0100 N1_V02S0301\narc: V00T0000 H02E0201\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0303 E1_H02W0601\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A3 H02E0501\narc: A4 H02E0701\narc: A6 N1_V02S0101\narc: B3 V02S0301\narc: B4 H01E0101\narc: B6 V00B0000\narc: C3 F6\narc: C4 H02E0601\narc: C6 H01E0001\narc: C7 N1_V02S0001\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 W1_H02E0001\narc: D4 V02N0601\narc: D6 H00L0100\narc: D7 H02E0001\narc: E1_H01E0001 F7\narc: E3_H06E0103 Q1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 F4\narc: LSR1 V00B0100\narc: M0 H02W0601\narc: M1 H00R0000\narc: M2 H02W0601\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0001 F1\narc: N3_V06N0103 F1\narc: V01S0000 F1\narc: V01S0100 F1\nword: SLICED.K0.INIT 0000000001110000\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1101111111111111\nword: SLICEC.K0.INIT 0000000000010011\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R27C26:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0203 V06S0203\narc: H00L0000 V02S0001\narc: H00R0000 H02E0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0501 N1_V02S0501\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02W0001\narc: V00T0100 H02E0101\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0401 V06N0203\narc: W1_H02W0601 H01E0001\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: A6 H00R0000\narc: B1 E1_H02W0301\narc: B2 E1_H01W0100\narc: B3 H00L0000\narc: B5 E1_H02W0101\narc: B6 H02E0301\narc: B7 V00T0000\narc: C1 H00R0100\narc: C2 S1_V02N0601\narc: C3 H02E0401\narc: C5 V00T0100\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: D1 E1_H02W0001\narc: D2 V01S0100\narc: D3 F2\narc: D5 E1_H02W0201\narc: D6 V02N0401\narc: D7 H00L0100\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: E1_H02E0701 F5\narc: E3_H06E0103 F2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0000 F1\narc: H01W0100 F7\narc: N1_V01N0001 F7\narc: N1_V01N0101 F5\narc: N1_V02N0401 F6\narc: N3_V06N0103 F2\narc: N3_V06N0303 F5\narc: S1_V02S0001 F2\narc: V01S0000 F2\narc: V01S0100 F1\narc: W1_H02W0201 F2\narc: W1_H02W0501 F7\narc: W1_H02W0701 F5\narc: W3_H06W0003 F3\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000110000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001100\nword: SLICED.K0.INIT 0111111100000000\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEB.K0.INIT 1100000000000000\nword: SLICEB.K1.INIT 1111110000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R27C27:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 V02S0701\narc: H00L0100 V02N0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 S1_V02N0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H02E0701\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 V01N0001\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02W0701\narc: V00T0100 V02N0501\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E1_H02W0301\narc: E1_H02E0201 W3_H06E0103\narc: S1_V02S0301 W3_H06E0003\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A1 V02N0701\narc: A2 E1_H01E0001\narc: A3 V01N0101\narc: A4 H02E0501\narc: B1 F3\narc: B2 V01N0001\narc: B3 H01W0100\narc: B4 V00B0100\narc: B5 V01S0000\narc: C1 V02N0401\narc: C2 S1_V02N0601\narc: C3 H00L0100\narc: C4 V02N0201\narc: C5 H02E0601\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D2 S1_V02N0201\narc: D3 V00T0100\narc: D4 H01W0000\narc: D5 H00R0100\narc: E1_H01E0001 Q6\narc: E1_H01E0101 F4\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F5\narc: H01W0100 F2\narc: M0 V00B0000\narc: M6 N1_V01N0101\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F0\narc: S1_V02S0401 Q6\narc: S3_V06S0303 Q6\narc: V01S0000 F2\narc: W1_H02W0001 F2\narc: W1_H02W0701 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000010\nword: SLICEB.K1.INIT 1101110000000000\nword: SLICEC.K0.INIT 0001010100111111\nword: SLICEC.K1.INIT 1100000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R27C28:PLC2\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 H01E0001\narc: E3_H06E0303 N1_V01S0100\narc: H00R0000 W1_H02E0401\narc: H00R0100 H02E0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 V01N0001\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 E1_H02W0501\narc: V00T0100 W1_H02E0301\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V01N0101\narc: W1_H02W0501 V06N0303\narc: W1_H02W0701 V06S0203\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0103 V01N0101\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 E3_H06W0203\narc: A2 V00B0000\narc: A3 V00T0000\narc: A4 F5\narc: A6 H00L0000\narc: A7 H02E0701\narc: B1 E1_H02W0101\narc: B2 H00R0000\narc: B3 V02N0301\narc: B4 H01E0101\narc: B5 S1_V02N0701\narc: B6 V02S0701\narc: B7 H02E0101\narc: C0 H02W0401\narc: C1 E1_H02W0601\narc: C2 N1_V02S0601\narc: C3 E1_H02W0401\narc: C4 F6\narc: C5 V00T0100\narc: C6 S1_V02N0001\narc: C7 V02S0001\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V00B0100\narc: D2 H02W0001\narc: D3 W1_H02E0201\narc: D4 V02N0401\narc: D5 S1_V02N0401\narc: D6 H02E0001\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 Q2\narc: E3_H06E0103 F1\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 F1\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 F1\narc: N1_V02N0301 F1\narc: V00T0000 Q2\narc: V01S0100 F1\narc: W1_H02W0601 F4\narc: W3_H06W0003 F0\nword: SLICED.K0.INIT 0001001101011111\nword: SLICED.K1.INIT 0101010101000101\nword: SLICEB.K0.INIT 1111111110000000\nword: SLICEB.K1.INIT 0000000011001010\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 0011111100000000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000001100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R27C29:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 E3_H06W0303\narc: E3_H06E0303 V06N0303\narc: H00L0000 H02W0001\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02W0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0501 H01E0101\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0401 H06E0203\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0001\narc: V00T0000 E1_H02W0201\narc: V00T0100 N1_V02S0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 N1_V01S0000\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 E1_H02W0601\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: A0 H02E0701\narc: A1 E1_H02W0701\narc: A3 V02N0501\narc: A4 V00B0000\narc: A5 V02N0101\narc: B0 V00T0000\narc: B1 V02N0301\narc: B3 V02S0101\narc: B4 E1_H02W0101\narc: B5 E1_H02W0101\narc: C0 N1_V02S0401\narc: C1 H00L0000\narc: C3 H02W0601\narc: C4 E1_H01E0101\narc: C5 E1_H02W0601\narc: CE0 V02S0201\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 V02N0201\narc: D3 H00R0000\narc: D4 H02W0201\narc: D5 H00R0100\narc: E1_H01E0001 F5\narc: E1_H01E0101 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F4\narc: H01W0100 Q1\narc: LSR1 H02W0301\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR1\narc: N3_V06N0003 F0\narc: N3_V06N0303 Q6\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000100000000000\nword: SLICEC.K0.INIT 0000000000000111\nword: SLICEC.K1.INIT 0000000000000010\nword: SLICEA.K0.INIT 0101000000000011\nword: SLICEA.K1.INIT 0111000001111100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R27C2:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0401 S1_V02N0401\narc: S1_V02S0001 H02W0001\narc: S1_V02S0601 H02W0601\narc: S3_V06S0103 N3_V06S0003\n\n.tile R27C30:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 E1_H01W0100\narc: E3_H06E0203 V06S0203\narc: H00L0000 E1_H02W0001\narc: H00L0100 E1_H02W0101\narc: H00R0000 V02S0401\narc: H00R0100 V02N0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0601 E1_H01W0000\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0101 V01N0101\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 V02N0001\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02W0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 E1_H01W0100\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: N1_V02N0401 W3_H06E0203\narc: W3_H06W0303 E1_H01W0100\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A0 E1_H02W0701\narc: A2 V00B0000\narc: A4 H02E0501\narc: A5 V02N0301\narc: A6 H00R0000\narc: A7 V02N0101\narc: B0 V02S0101\narc: B2 H00R0100\narc: B4 V02S0501\narc: B5 H00L0000\narc: B6 H02W0101\narc: B7 V02S0501\narc: C0 F4\narc: C2 E1_H01W0000\narc: C4 V00T0100\narc: C5 H02E0401\narc: C6 H02W0601\narc: C7 H02E0401\narc: D0 V00B0100\narc: D2 V01S0100\narc: D4 H00L0100\narc: D5 E1_H01W0100\narc: D6 E1_H01W0100\narc: D7 H00L0100\narc: E1_H01E0101 F0\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: M0 V00T0000\narc: M2 N1_V01N0001\narc: N1_V01N0001 F7\narc: V00B0100 F5\narc: V01S0100 F6\nword: SLICEC.K0.INIT 0000100000000000\nword: SLICEC.K1.INIT 0000001000000000\nword: SLICED.K0.INIT 0000000000000010\nword: SLICED.K1.INIT 0000100000000000\nword: SLICEA.K0.INIT 0000000000000111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000010011\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R27C31:PLC2\narc: E1_H02E0201 V02S0201\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 V02N0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 S1_V02N0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0501 V01N0101\narc: N1_V02N0701 H01E0101\narc: N3_V06N0203 H06W0203\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0701 N3_V06S0203\narc: V00B0000 H02W0401\narc: V00B0100 S1_V02N0301\narc: V00T0100 V02S0501\narc: W1_H02W0401 V01N0001\narc: W1_H02W0701 N3_V06S0203\narc: S1_V02S0401 W3_H06E0203\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0303 V06S0303\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A2 H00L0100\narc: A4 V00T0100\narc: A6 E1_H02W0501\narc: B1 V00B0000\narc: B2 F1\narc: B3 H02E0301\narc: B4 H00L0000\narc: B6 V01S0000\narc: B7 V02S0501\narc: C0 H02W0601\narc: C1 H02E0601\narc: C2 F4\narc: C3 H00R0100\narc: C4 H01E0001\narc: C5 H01E0001\narc: C6 H02E0401\narc: C7 V02N0001\narc: D0 H02E0001\narc: D1 H00R0000\narc: D2 V01S0100\narc: D3 N1_V01S0000\narc: D4 H00R0100\narc: D5 H00R0100\narc: D6 V02S0601\narc: D7 N1_V02S0601\narc: E1_H01E0001 F7\narc: E1_H01E0101 F4\narc: E1_H02E0001 F0\narc: E1_H02E0301 F3\narc: E1_H02E0401 F4\narc: E1_H02E0601 F4\narc: E1_H02E0701 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 F3\narc: M4 V00B0100\narc: N1_V01N0001 F3\narc: N1_V01N0101 F1\narc: N1_V02N0001 F2\narc: N1_V02N0101 F3\narc: N1_V02N0401 F6\narc: N1_V02N0601 F4\narc: S1_V02S0101 F1\narc: S1_V02S0301 F3\narc: S1_V02S0501 F7\narc: S1_V02S0601 F4\narc: S3_V06S0003 F3\narc: S3_V06S0103 F1\narc: S3_V06S0203 F4\narc: V01S0000 F7\narc: V01S0100 F3\narc: W1_H02W0101 F1\narc: W1_H02W0601 F4\narc: W3_H06W0103 F1\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000000011000000\nword: SLICED.K0.INIT 0000001000000000\nword: SLICED.K1.INIT 0000000011001111\nword: SLICEB.K0.INIT 0000000000000010\nword: SLICEB.K1.INIT 0000000011110011\nword: SLICEC.K0.INIT 0100010000000100\nword: SLICEC.K1.INIT 1111111100001111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R27C32:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0401 W1_H02E0401\narc: H00L0000 W1_H02E0201\narc: H00L0100 E1_H02W0101\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 H01E0101\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 H06E0303\narc: S1_V02S0201 H01E0001\narc: S1_V02S0301 H02E0301\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 E1_H02W0401\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 V01N0101\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0203 E1_H02W0401\narc: W3_H06W0303 N3_V06S0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0103 E3_H06W0103\narc: A1 S1_V02N0501\narc: A3 H00L0100\narc: A5 N1_V02S0301\narc: B1 V00T0000\narc: B2 E1_H02W0101\narc: B3 H00L0000\narc: B4 H02W0301\narc: B5 H00L0000\narc: B6 V00B0000\narc: C1 W1_H02E0401\narc: C2 H02W0401\narc: C3 H02E0601\narc: C4 V00T0100\narc: C5 H02E0401\narc: C6 H01E0001\narc: D1 H01E0101\narc: D2 H02W0201\narc: D3 V00B0100\narc: D4 H02W0201\narc: D5 H02E0201\narc: D6 H02E0201\narc: D7 H02W0001\narc: E1_H01E0001 F3\narc: E1_H01E0101 F4\narc: E1_H02E0301 F1\narc: E3_H06E0103 F2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M6 W1_H02E0401\narc: N1_V02N0401 F6\narc: S1_V02S0701 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000100000000000\nword: SLICEC.K0.INIT 0000111100110011\nword: SLICEC.K1.INIT 0000000000000010\nword: SLICEB.K0.INIT 0000111100110011\nword: SLICEB.K1.INIT 0000000000000010\nword: SLICED.K0.INIT 1111001111111111\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R27C33:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0303 H01E0101\narc: H00L0000 E1_H02W0001\narc: H00L0100 W1_H02E0301\narc: H00R0000 N1_V02S0601\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0203 S1_V02N0401\narc: S1_V02S0001 H02E0001\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 H02E0401\narc: V00B0100 H02W0501\narc: V00T0100 H02E0301\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 N1_V02S0501\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\narc: A0 V02N0701\narc: A3 E1_H02W0701\narc: A4 V02N0101\narc: A7 H00L0000\narc: B0 F3\narc: B3 H00R0100\narc: B4 V02N0701\narc: B6 E1_H02W0301\narc: B7 V00B0000\narc: C0 N1_V01N0001\narc: C2 H02W0601\narc: C3 H02E0401\narc: C4 H02E0401\narc: C6 V00B0100\narc: C7 W1_H02E0601\narc: D0 H00R0000\narc: D2 H02E0201\narc: D3 V02S0001\narc: D4 N1_V02S0401\narc: D6 H02W0201\narc: D7 H00L0100\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M0 V00T0000\narc: M4 V00T0100\narc: N1_V01N0001 F7\narc: V00T0000 F2\narc: V01S0000 F6\narc: W3_H06W0003 F0\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 0000000000000010\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0000001000000000\nword: SLICEC.K0.INIT 0000000000010011\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000001\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R27C34:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V06S0303\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 N1_V01S0100\narc: H00L0100 N1_V02S0301\narc: H00R0100 V02S0501\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 H02W0501\narc: S3_V06S0003 H01E0001\narc: S3_V06S0303 H06W0303\narc: V00B0000 H02E0601\narc: V00B0100 V02S0101\narc: V00T0100 V02S0501\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 N3_V06S0203\narc: E1_H02E0601 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: B0 V02S0101\narc: B1 V02S0101\narc: B2 V02S0101\narc: B3 V02S0101\narc: B4 V00B0100\narc: B5 V00B0100\narc: C0 E1_H02W0601\narc: C1 H02E0401\narc: C2 H00L0100\narc: C3 H02W0401\narc: C4 V01N0101\narc: C5 V02N0201\narc: C7 S1_V02N0001\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 V00T0100\narc: D3 V00T0100\narc: D4 H00R0100\narc: D5 H00R0100\narc: D7 V00B0000\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F3\narc: N1_V02N0701 F7\narc: S1_V02S0001 F0\narc: S1_V02S0301 F1\narc: S1_V02S0701 F5\narc: S3_V06S0203 F7\narc: V01S0000 F7\narc: V01S0100 F2\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111000011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R27C35:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0303 N1_V01S0100\narc: H00L0100 S1_V02N0101\narc: H00R0000 E1_H02W0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0103 H01E0101\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 H02E0401\narc: V00B0100 V02S0101\narc: V00T0000 N1_V02S0401\narc: V00T0100 S1_V02N0501\narc: V01S0100 S3_V06N0303\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0701 E1_H01W0100\narc: W3_H06W0303 E1_H02W0501\narc: W3_H06W0203 E3_H06W0103\narc: B6 V00T0000\narc: B7 V02N0701\narc: C6 V02S0001\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D6 V02S0601\narc: D7 V02S0601\narc: E1_H01E0101 Q4\narc: E3_H06E0203 Q4\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: H01W0100 Q2\narc: M0 V00B0100\narc: M2 V00B0000\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q2\narc: W1_H02W0001 Q2\narc: W1_H02W0501 F7\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1100110011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R27C36:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 V06S0303\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0203 W1_H02E0701\narc: H00R0000 V02S0401\narc: H00R0100 H02W0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 H06W0003\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 N3_V06S0103\narc: V00T0000 H02E0201\narc: V00T0100 W1_H02E0101\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 N3_V06S0303\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: CE0 H00R0100\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q6\narc: H01W0100 Q0\narc: M0 H02W0601\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V00B0000 Q6\narc: V01S0000 Q4\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R27C37:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 W1_H02E0401\narc: H00R0100 V02S0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N3_V06S0303\narc: V00B0000 E1_H02W0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 H02W0201\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 V02S0701\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0201 W3_H06E0103\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A7 H00R0000\narc: B7 V00B0100\narc: C7 H02E0601\narc: CE0 H00R0100\narc: CE1 H02W0101\narc: CE2 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: E1_H01E0101 Q2\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: M0 H02W0601\narc: M2 W1_H02E0601\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N3_V06N0203 F7\narc: S1_V02S0001 Q2\narc: V01S0100 Q2\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010110000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R27C38:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V06S0003\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V01N0101\narc: H00L0000 H02W0001\narc: H00L0100 V02N0101\narc: H00R0100 H02W0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H06E0303\narc: N3_V06N0003 H01E0001\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02S0301\narc: V00T0000 W1_H02E0001\narc: V00T0100 N1_V02S0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 V06S0103\narc: E1_H02E0401 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: B6 V00B0100\narc: C6 H02W0601\narc: CE0 H00R0100\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D6 V02S0601\narc: D7 H00L0100\narc: E1_H01E0101 Q0\narc: E3_H06E0003 Q0\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M2 V00T0100\narc: M4 E1_H01E0101\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q2\narc: S1_V02S0601 F6\narc: W1_H02W0601 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111000000110011\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R27C39:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0701 H01E0101\narc: E3_H06E0303 N3_V06S0303\narc: H00L0100 S1_V02N0301\narc: H00R0000 S1_V02N0401\narc: H00R0100 H02E0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 S1_V02N0101\narc: V00T0000 H02E0201\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0303 N3_V06S0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: A0 V02N0501\narc: A1 N1_V02S0501\narc: A6 H00R0000\narc: A7 W1_H02E0701\narc: B0 V01N0001\narc: B1 H02W0301\narc: B2 H01W0100\narc: B5 H02E0101\narc: B6 W1_H02E0301\narc: B7 W1_H02E0301\narc: C0 V02N0601\narc: C1 V02N0601\narc: C2 W1_H02E0401\narc: C4 E1_H02W0601\narc: C5 E1_H02W0601\narc: C6 V00B0100\narc: C7 W1_H02E0601\narc: D0 V00B0100\narc: D1 V02N0001\narc: D2 N1_V02S0201\narc: D3 E1_H02W0201\narc: D4 H00L0100\narc: D5 H02E0001\narc: D6 V02N0401\narc: D7 H00R0100\narc: E1_H01E0101 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M2 V00T0000\narc: M4 H02W0401\narc: N1_V01N0001 F0\narc: N3_V06N0103 F2\narc: S1_V02S0501 F7\narc: V01S0000 F1\narc: V01S0100 F6\nword: SLICEA.K0.INIT 1100101010101010\nword: SLICEA.K1.INIT 1111111111001010\nword: SLICED.K0.INIT 1110101000101010\nword: SLICED.K1.INIT 0000000011100010\nword: SLICEC.K0.INIT 0000111111111111\nword: SLICEC.K1.INIT 0011000000111111\nword: SLICEB.K0.INIT 1111000000110011\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R27C3:PLC2\narc: E1_H02E0401 V02S0401\narc: H00R0000 W1_H02E0401\narc: S1_V02S0501 V01N0101\narc: V00B0000 H02E0401\narc: V00B0100 H02W0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0601 S1_V02N0601\narc: CE0 V02N0201\narc: CE1 H00R0000\narc: CE2 H02E0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: M0 V00B0000\narc: M2 V00B0100\narc: M4 H02E0401\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q4\narc: N1_V02N0001 Q0\narc: N1_V02N0201 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R27C40:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 V02N0001\narc: H00L0100 W1_H02E0301\narc: H00R0100 H02W0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S1_V02N0301\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 N1_V01S0100\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02N0001\narc: V00B0100 S1_V02N0301\narc: V00T0100 H02W0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0701 N3_V06S0203\narc: E1_H01E0001 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0003 N3_V06S0003\narc: W3_H06W0303 E1_H02W0601\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: A1 H02W0701\narc: A2 H00L0100\narc: A4 W1_H02E0501\narc: A6 H02E0701\narc: B1 E1_H02W0101\narc: B2 H00L0000\narc: B4 H02W0301\narc: B6 V00B0000\narc: C0 S1_V02N0601\narc: C1 V02N0601\narc: C2 H00R0100\narc: C3 W1_H02E0601\narc: C4 V02N0001\narc: C5 V00T0100\narc: C6 N1_V02S0201\narc: C7 V00B0100\narc: D0 V01S0100\narc: D1 H01E0101\narc: D2 H02W0001\narc: D3 H02E0001\narc: D4 H02W0001\narc: D5 H02E0001\narc: D6 H02W0001\narc: D7 H02E0001\narc: E1_H01E0101 F1\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F0\narc: H01W0100 F2\narc: N1_V01N0001 F7\narc: N1_V01N0101 F4\narc: N3_V06N0103 F1\narc: S1_V02S0101 F3\narc: S1_V02S0601 F6\narc: S1_V02S0701 F5\narc: V01S0100 F1\nword: SLICEC.K0.INIT 1100101010101010\nword: SLICEC.K1.INIT 0000000011110000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 0001000011111111\nword: SLICEB.K0.INIT 1110001010101010\nword: SLICEB.K1.INIT 0000000011110000\nword: SLICED.K0.INIT 1110001010101010\nword: SLICED.K1.INIT 0000000011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R27C41:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0103 H01E0101\narc: E3_H06E0303 V01N0101\narc: H00R0000 E1_H02W0401\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0203 H06W0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 V02N0401\narc: V00T0100 H02E0101\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 N1_V02S0701\narc: E1_H01E0101 W3_H06E0203\narc: S1_V02S0701 W3_H06E0203\narc: A0 S1_V02N0701\narc: A1 E1_H02W0701\narc: A3 V02S0501\narc: A7 S1_V02N0101\narc: B0 F1\narc: B1 E1_H02W0301\narc: B2 N1_V02S0101\narc: B3 H00R0000\narc: B4 H02E0301\narc: B7 H02W0301\narc: C0 N1_V02S0601\narc: C1 V02S0401\narc: C2 H00L0100\narc: C3 H02E0601\narc: C4 V00B0100\narc: C6 H02W0601\narc: C7 V00T0000\narc: CE2 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 H02W0201\narc: D2 F0\narc: D3 S1_V02N0001\narc: D4 H02E0201\narc: D5 W1_H02E0201\narc: D6 V02N0401\narc: D7 S1_V02N0401\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 F3\narc: H01W0000 F1\narc: H01W0100 F6\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: N3_V06N0103 F2\narc: V01S0100 F1\narc: W1_H02W0401 Q4\narc: W3_H06W0103 F1\narc: W3_H06W0203 Q4\nword: SLICEA.K0.INIT 1101000010000000\nword: SLICEA.K1.INIT 0101010000010000\nword: SLICEB.K0.INIT 0000000011110011\nword: SLICEB.K1.INIT 1001010001001111\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 1010101000001100\nword: SLICEC.K0.INIT 0000001111001111\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R27C42:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 E1_H02W0001\narc: H00L0100 V02N0101\narc: H00R0000 V02N0601\narc: H00R0100 N1_V02S0701\narc: H01W0000 E3_H06W0103\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 E3_H06W0203\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0201\narc: V00B0100 E1_H02W0701\narc: V00T0000 S1_V02N0601\narc: V00T0100 V02N0501\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 V06N0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0601 S1_V02N0601\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0401 W3_H06E0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: A3 V00T0000\narc: A5 V00T0000\narc: A6 E1_H01W0000\narc: A7 N1_V01N0101\narc: B0 H00R0100\narc: B1 H00R0100\narc: B3 E1_H02W0101\narc: B5 V02S0501\narc: B6 V00B0000\narc: B7 H02E0101\narc: C0 N1_V01N0001\narc: C1 H00L0000\narc: C2 S1_V02N0601\narc: C3 H00L0100\narc: C4 V00T0000\narc: C5 V00T0100\narc: C6 V02N0001\narc: C7 V02N0201\narc: D0 H00R0000\narc: D1 V00B0100\narc: D2 V00T0100\narc: D3 H02E0001\narc: D4 H00L0100\narc: D5 H02E0001\narc: D6 H02E0001\narc: D7 H02E0001\narc: E1_H01E0101 F6\narc: E3_H06E0003 F0\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F2\narc: M0 H02E0601\narc: M2 E1_H02W0601\narc: M4 V00B0000\narc: N3_V06N0003 F0\narc: S1_V02S0701 F7\narc: V01S0000 F0\narc: W1_H02W0401 F4\nword: SLICED.K0.INIT 1110001010101010\nword: SLICED.K1.INIT 1010110011001100\nword: SLICEA.K0.INIT 1111110000110000\nword: SLICEA.K1.INIT 1111001111000000\nword: SLICEC.K0.INIT 0000000011110000\nword: SLICEC.K1.INIT 1010101000001100\nword: SLICEB.K0.INIT 0000000011110000\nword: SLICEB.K1.INIT 1010101000001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R27C43:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 V02S0701\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 V02S0201\narc: H00L0100 V02N0101\narc: H00R0100 S1_V02N0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 E3_H06W0303\narc: N3_V06N0103 S1_V02N0101\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 H01E0101\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02N0001\narc: V00B0100 E1_H02W0701\narc: W1_H02W0001 V01N0001\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 V02S0701\narc: E1_H02E0301 W3_H06E0003\narc: H01W0000 W3_H06E0103\narc: W3_H06W0203 V01N0001\narc: W3_H06W0303 E1_H01W0100\narc: A0 V02S0701\narc: A2 H02W0501\narc: A3 V00B0000\narc: A4 N1_V01S0100\narc: A7 W1_H02E0701\narc: B0 N1_V02S0301\narc: B1 V00T0000\narc: B2 H02E0101\narc: B3 V02N0301\narc: B4 H00L0000\narc: B5 H00R0000\narc: B7 V02N0501\narc: C0 N1_V02S0601\narc: C1 H00R0100\narc: C2 V02N0601\narc: C3 V02N0601\narc: C4 H02E0401\narc: C5 S1_V02N0001\narc: C7 V02S0001\narc: D0 V00B0100\narc: D1 E1_H02W0001\narc: D2 W1_H02E0001\narc: D3 W1_H02E0001\narc: D4 H02E0001\narc: D5 E1_H02W0001\narc: D7 H00L0100\narc: E1_H01E0001 F0\narc: E1_H01E0101 F1\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H01W0100 F3\narc: N1_V01N0101 F5\narc: N3_V06N0003 F0\narc: N3_V06N0203 F4\narc: S1_V02S0401 F4\narc: V00T0000 F0\narc: V01S0000 F7\narc: V01S0100 F4\narc: W1_H02W0201 F0\narc: W3_H06W0003 F0\narc: W3_H06W0103 F2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100010010000000\nword: SLICEB.K0.INIT 1010110011001100\nword: SLICEB.K1.INIT 1010110011001100\nword: SLICEA.K0.INIT 0101000101000000\nword: SLICEA.K1.INIT 0000111100110011\nword: SLICEC.K0.INIT 0101010000010000\nword: SLICEC.K1.INIT 0011001100001111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R27C44:PLC2\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 V06S0203\narc: E3_H06E0003 H01E0001\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 V06N0203\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 N1_V02S0001\narc: H00R0000 H02W0401\narc: H00R0100 S1_V02N0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N1_V02S0501\narc: V00T0100 N1_V02S0701\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 V02N0701\narc: W1_H02W0001 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: A0 H00R0000\narc: A4 H02E0701\narc: B0 V02S0301\narc: B1 V00B0000\narc: B2 E1_H02W0101\narc: B3 H01W0100\narc: B4 V02S0701\narc: B5 V01S0000\narc: B6 W1_H02E0301\narc: B7 W1_H02E0301\narc: C0 H02E0601\narc: C1 N1_V01N0001\narc: C2 S1_V02N0601\narc: C3 H00L0000\narc: C4 E1_H02W0401\narc: C5 V00T0000\narc: C6 W1_H02E0601\narc: C7 W1_H02E0601\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 H02W0001\narc: D2 E1_H02W0201\narc: D3 H02W0201\narc: D4 S1_V02N0401\narc: D5 H02W0001\narc: D6 E1_H02W0001\narc: D7 W1_H02E0201\narc: E1_H01E0001 F4\narc: E1_H01E0101 F3\narc: E1_H02E0001 F2\narc: E1_H02E0101 F3\narc: E1_H02E0301 F1\narc: E1_H02E0501 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: H01W0100 Q2\narc: LSR1 E1_H02W0301\narc: M6 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F0\narc: N3_V06N0003 F0\narc: N3_V06N0203 F4\narc: N3_V06N0303 F6\narc: S1_V02S0001 F2\narc: S3_V06S0003 F0\narc: V00B0000 F4\narc: V00T0000 F0\narc: V01S0000 F4\narc: V01S0100 F6\narc: W3_H06W0003 F0\narc: W3_H06W0203 F4\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 0010001100100000\nword: SLICEA.K1.INIT 0011001100001111\nword: SLICEC.K0.INIT 0101010000010000\nword: SLICEC.K1.INIT 0000111100110011\nword: SLICEB.K0.INIT 1100000011001111\nword: SLICEB.K1.INIT 0000111100001100\nword: SLICED.K0.INIT 1111001111000000\nword: SLICED.K1.INIT 1111110000110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R27C45:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V01N0101\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 H01E0001\narc: H00R0000 H02W0601\narc: H00R0100 H02E0701\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 V01N0101\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 S1_V02N0201\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 V02S0001\narc: V00T0000 W1_H02E0201\narc: V00T0100 E1_H02W0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 V02S0301\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 E1_H02W0601\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A3 V02N0501\narc: B3 H02E0101\narc: B4 N1_V02S0501\narc: C3 N1_V01S0100\narc: C4 H02E0401\narc: CE0 H00R0100\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D2 H01E0101\narc: D3 V02N0201\narc: D4 V02N0401\narc: D5 H00L0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: H00L0100 Q1\narc: H01W0000 Q1\narc: H01W0100 Q6\narc: M0 V00T0100\narc: M1 H00R0000\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F1\narc: N1_V02N0401 Q6\narc: V01S0100 F4\narc: W1_H02W0401 Q6\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000111100110011\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000110010001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R27C46:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0201 H01E0001\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 V01N0101\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 V02N0201\narc: H00L0100 V02N0301\narc: H00R0100 V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 V01N0101\narc: N3_V06N0003 V01N0001\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H01E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02W0701\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 E1_H02W0601\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: S1_V02S0201 W3_H06E0103\narc: S1_V02S0401 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\narc: A0 N1_V02S0501\narc: A1 N1_V02S0501\narc: A2 N1_V02S0501\narc: A3 N1_V02S0501\narc: A4 V02N0101\narc: A5 S1_V02N0101\narc: B0 V02S0101\narc: B1 V02S0101\narc: B2 V02S0101\narc: B3 V02S0101\narc: B4 H00L0000\narc: B5 H01E0101\narc: B6 V02N0501\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V00B0100\narc: C5 N1_V02S0201\narc: C6 V00T0100\narc: CLK1 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 S1_V02N0001\narc: D2 S1_V02N0001\narc: D3 S1_V02N0001\narc: D4 S1_V02N0401\narc: D5 V02N0601\narc: D6 H00R0100\narc: D7 W1_H02E0201\narc: E1_H01E0001 Q0\narc: E1_H02E0401 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q1\narc: LSR1 H02W0301\narc: M6 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: V01S0000 Q2\narc: V01S0100 Q3\nword: SLICED.K0.INIT 0011001100001111\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R27C47:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 H02W0201\narc: H00R0000 V02N0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 V01N0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 V02S0601\narc: V00T0100 V02S0701\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0701 W3_H06E0203\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: A1 V02S0701\narc: A3 H02E0501\narc: A5 V00T0100\narc: B1 E1_H02W0301\narc: B2 H00L0000\narc: B3 H00R0100\narc: B5 E1_H02W0301\narc: B6 S1_V02N0501\narc: C0 V02S0601\narc: C1 V02S0601\narc: C2 F6\narc: C3 N1_V02S0601\narc: C4 V00T0000\narc: C5 V00T0000\narc: C6 H02E0401\narc: CE1 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 E1_H02W0201\narc: D2 H00R0000\narc: D3 V00B0100\narc: D4 N1_V02S0401\narc: D5 N1_V02S0401\narc: D6 H02E0201\narc: D7 H02E0001\narc: E1_H01E0001 F0\narc: E1_H01E0101 F3\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F4\narc: H01W0100 Q2\narc: M0 H02E0601\narc: M4 H02W0401\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: N1_V01N0001 Q2\narc: W3_H06W0103 Q2\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 0000000000010000\nword: SLICED.K0.INIT 1100111100000011\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1110000000000000\nword: SLICEA.K0.INIT 1111111100001111\nword: SLICEA.K1.INIT 1110000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\n\n.tile R27C48:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0601 N3_V06S0303\narc: H00L0100 V02N0301\narc: H00R0100 V02N0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 H01E0101\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 H02E0501\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 H02W0501\narc: V00T0000 E1_H02W0201\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E3_H06W0303\narc: H01W0000 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: A1 N1_V02S0701\narc: A4 E1_H01W0000\narc: A5 S1_V02N0101\narc: A6 E1_H01W0000\narc: B1 H02W0301\narc: B2 V02N0101\narc: B3 H01W0100\narc: B4 H02E0101\narc: B5 H02W0101\narc: B6 V00T0000\narc: B7 E1_H02W0301\narc: C0 V02N0601\narc: C1 V02N0601\narc: C2 E1_H02W0601\narc: C3 S1_V02N0401\narc: C4 V02N0201\narc: C5 F4\narc: C6 V02N0001\narc: C7 F6\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 H02E0001\narc: D3 V00B0100\narc: D4 H00R0100\narc: D5 N1_V02S0601\narc: D6 H00L0100\narc: D7 N1_V02S0601\narc: E1_H01E0001 F4\narc: E1_H01E0101 F6\narc: E1_H02E0501 F5\narc: E1_H02E0701 F5\narc: E3_H06E0203 F7\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F2\narc: M0 H02E0601\narc: N1_V01N0001 F2\narc: N1_V02N0601 F6\narc: S1_V02S0201 F2\narc: S1_V02S0601 F6\narc: V01S0000 F0\narc: V01S0100 F3\narc: W3_H06W0103 F2\narc: W3_H06W0203 F4\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 0000000000001100\nword: SLICEB.K1.INIT 0011001100001111\nword: SLICEC.K0.INIT 0101010000010000\nword: SLICEC.K1.INIT 0111011100001111\nword: SLICED.K0.INIT 0101010000010000\nword: SLICED.K1.INIT 0000111100110011\nword: SLICEA.K0.INIT 1111111100001111\nword: SLICEA.K1.INIT 1110000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\n\n.tile R27C49:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 N1_V02S0301\narc: E3_H06E0003 H01E0001\narc: H00L0000 H02E0201\narc: H00L0100 E1_H02W0301\narc: H00R0100 W1_H02E0701\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 N1_V02S0201\narc: V00B0100 W1_H02E0701\narc: V00T0000 N1_V02S0601\narc: V01S0000 N3_V06S0103\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0501 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: S1_V02S0301 W3_H06E0003\narc: W3_H06W0303 N1_V01S0100\narc: B3 H00L0000\narc: B4 V02S0701\narc: C2 N1_V01N0001\narc: C3 H02W0401\narc: C4 V01N0101\narc: C5 E1_H01E0101\narc: CE0 H00L0100\narc: CE1 H02E0101\narc: CE2 H02W0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D2 V02N0001\narc: D3 V00B0100\narc: D4 H00R0100\narc: D5 H02E0001\narc: E1_H01E0101 Q4\narc: E3_H06E0103 F2\narc: E3_H06E0303 F5\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: M0 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q3\narc: N1_V01N0101 Q3\narc: N3_V06N0203 Q4\narc: S1_V02S0001 Q0\narc: S1_V02S0601 Q6\narc: W3_H06W0003 Q3\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100111100000011\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1111110000110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R27C4:PLC2\narc: E1_H02E0601 V02S0601\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 V01N0001\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 N1_V02S0001\narc: V00T0100 H02W0101\narc: W1_H02W0701 N1_V02S0701\narc: B3 H01W0100\narc: C2 N1_V01N0001\narc: C3 H00L0000\narc: CE0 V02N0201\narc: CE2 V02S0601\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: E3_H06E0103 F2\narc: F2 F5B_SLICE\narc: H00L0000 Q0\narc: H01W0100 Q4\narc: M0 V00B0000\narc: M2 V00T0100\narc: M4 V00B0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 0011001100001111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R27C50:PLC2\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 V02S0001\narc: H00R0000 N1_V02S0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 H02E0601\narc: V00B0100 V02N0301\narc: V00T0000 H02E0001\narc: V00T0100 W1_H02E0301\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 V06S0203\narc: E1_H02E0001 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A0 V02N0501\narc: A5 H02W0701\narc: A7 S1_V02N0301\narc: B0 V00B0000\narc: B1 H02E0301\narc: B5 V00B0100\narc: B7 V00T0000\narc: C0 H00L0000\narc: C1 N1_V01N0001\narc: C4 V02N0201\narc: C5 V02N0201\narc: C6 V02N0201\narc: C7 V02N0201\narc: CE1 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 H00R0000\narc: D4 N1_V02S0401\narc: D5 N1_V02S0401\narc: D6 H00R0100\narc: D7 H00R0100\narc: E1_H01E0001 F4\narc: E1_H01E0101 F1\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F0\narc: M2 W1_H02E0601\narc: M4 V00T0100\narc: M6 E1_H02W0401\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F0\narc: N1_V01N0101 F1\narc: S3_V06S0103 Q2\narc: V01S0100 F6\narc: W3_H06W0003 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0011001000000010\nword: SLICEA.K1.INIT 0000111100110011\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1110000000000000\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 1110000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R27C51:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0303 H01E0101\narc: H00R0100 V02N0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02W0501\narc: V00T0000 V02N0601\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 V02S0701\narc: E1_H02E0201 W3_H06E0103\narc: CE0 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 F3\narc: E3_H06E0003 F3\narc: E3_H06E0203 Q4\narc: F3 F3_SLICE\narc: H01W0000 F3\narc: M0 V00B0000\narc: M4 H02E0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F3\narc: N1_V02N0301 F3\narc: N3_V06N0003 F3\narc: S1_V02S0201 Q0\narc: S1_V02S0301 F3\narc: V01S0000 Q6\narc: V01S0100 F3\narc: W1_H02W0301 F3\narc: W3_H06W0003 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R27C52:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 H01E0101\narc: E3_H06E0003 V06N0003\narc: H00R0000 W1_H02E0601\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 H02E0601\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 H02E0401\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02W0301\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V06S0303\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0201 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H02E0601 Q6\narc: E3_H06E0103 Q2\narc: M0 V00T0000\narc: M2 V00T0100\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0003 Q0\narc: S3_V06S0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R27C53:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 H01E0001\narc: E3_H06E0303 N1_V01S0100\narc: H00R0100 H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H06W0303\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 N1_V02S0101\narc: V00T0000 H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0301 V06S0003\narc: W1_H02W0701 E1_H02W0701\narc: H01W0100 W3_H06E0303\narc: N1_V02N0701 W3_H06E0203\narc: N3_V06N0003 W3_H06E0003\narc: N3_V06N0103 W3_H06E0103\narc: B4 V01S0000\narc: B5 V01S0000\narc: C4 H02E0601\narc: C5 H02E0601\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D4 W1_H02E0001\narc: D5 W1_H02E0001\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: M0 V00T0100\narc: M2 N1_V01N0001\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0001 Q0\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V01S0000 Q2\narc: V01S0100 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100001100111100\nword: SLICEC.K1.INIT 1111110011000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R27C54:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 W1_H02E0301\narc: H00R0000 W1_H02E0401\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 H06E0303\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 H06E0203\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: V00T0100 V02S0501\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0501 N3_V06S0303\narc: N1_V02N0701 W3_H06E0203\narc: N3_V06N0303 W3_H06E0303\narc: W3_H06W0303 S3_V06N0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: B1 W1_H02E0101\narc: B2 H02E0301\narc: B3 V02S0101\narc: B4 V00B0100\narc: B5 V02S0701\narc: B6 V00B0000\narc: B7 V02S0701\narc: C1 E1_H02W0601\narc: C2 V02N0601\narc: C3 H00L0000\narc: C4 V00T0000\narc: C5 F4\narc: C6 E1_H01E0101\narc: C7 F6\narc: D1 H00R0000\narc: D2 V00T0100\narc: D3 V02N0201\narc: D4 H02E0001\narc: D5 H02W0001\narc: D6 H02E0001\narc: D7 H00L0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 F1\narc: E1_H02E0701 F5\narc: E3_H06E0203 F7\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F2\narc: H00L0100 F3\narc: N1_V01N0001 F7\narc: N1_V01N0101 F3\narc: N1_V02N0501 F5\narc: V00T0000 F2\narc: V01S0000 F6\narc: V01S0100 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0011000000111111\nword: SLICED.K0.INIT 1111001111000000\nword: SLICED.K1.INIT 1111001111000000\nword: SLICEB.K0.INIT 0000111100110011\nword: SLICEB.K1.INIT 1111001111000000\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 1111001111000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R27C55:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 E1_H01W0000\narc: H00R0000 S1_V02N0601\narc: H00R0100 W1_H02E0701\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 H06E0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0101\narc: V00B0100 W1_H02E0501\narc: V00T0100 V02S0701\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0701 V06S0203\narc: N1_V02N0301 W3_H06E0003\narc: N3_V06N0303 W3_H06E0303\narc: B0 E1_H02W0101\narc: B1 W1_H02E0301\narc: B2 F3\narc: B3 H00R0000\narc: B5 F1\narc: B6 H02E0101\narc: B7 V02S0501\narc: C0 N1_V01N0001\narc: C1 V02N0601\narc: C2 S1_V02N0401\narc: C3 H00R0100\narc: C5 V02S0201\narc: C6 E1_H02W0601\narc: C7 V00T0100\narc: D0 W1_H02E0201\narc: D1 V00B0100\narc: D2 H02E0001\narc: D3 V00B0100\narc: D5 H00L0100\narc: D6 H02W0201\narc: D7 V00B0000\narc: E1_H01E0001 F7\narc: E1_H02E0201 F0\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: N1_V01N0001 F1\narc: N1_V01N0101 F5\narc: V00B0000 F6\narc: V01S0000 F6\narc: V01S0100 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000001100\nword: SLICEA.K0.INIT 1111001111000000\nword: SLICEA.K1.INIT 0011001100001111\nword: SLICED.K0.INIT 1111001111000000\nword: SLICED.K1.INIT 1111001111000000\nword: SLICEB.K0.INIT 1111110000001100\nword: SLICEB.K1.INIT 0011001100001111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R27C56:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: H00L0000 H02W0001\narc: H00R0000 H02E0601\narc: H00R0100 H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0501 N1_V02S0401\narc: S3_V06S0003 N1_V02S0301\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: V00T0000 H02W0201\narc: V00T0100 H02E0101\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 N3_V06S0203\narc: H01W0000 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: N1_V02N0401 W3_H06E0203\narc: N3_V06N0003 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0303 E1_H01W0100\narc: B0 W1_H02E0301\narc: B5 W1_H02E0301\narc: C0 H00R0100\narc: C5 V00T0100\narc: CE1 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 H00R0000\narc: D4 H02E0001\narc: D5 V02S0601\narc: E1_H02E0001 F0\narc: E1_H02E0401 F4\narc: F0 F5A_SLICE\narc: F4 F5C_SLICE\narc: M0 V00B0000\narc: M2 V00B0100\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0103 Q2\narc: S3_V06S0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111100000000\nword: SLICEC.K1.INIT 0000111100110011\nword: SLICEA.K0.INIT 0011001100001111\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R27C57:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 N1_V02S0301\narc: H00L0000 V02S0001\narc: H00R0000 H02W0401\narc: H00R0100 V02S0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0203 H06E0203\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H02W0601\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 N1_V02S0001\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0601 E1_H02W0301\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0001 W3_H06E0003\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0301 W3_H06E0003\narc: S1_V02S0001 W3_H06E0003\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: B2 H00L0000\narc: B3 H00R0100\narc: B4 V02S0701\narc: B5 H00L0000\narc: C2 H00L0100\narc: C3 H02E0401\narc: C4 E1_H02W0401\narc: C5 F4\narc: CE0 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 H02E0201\narc: D3 H02E0001\narc: D4 W1_H02E0201\narc: D5 H00L0100\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0100 F3\narc: H01W0000 F2\narc: H01W0100 F2\narc: M0 V00B0000\narc: M6 N1_V01N0101\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V02N0401 F4\narc: S3_V06S0003 Q0\narc: S3_V06S0303 Q6\narc: V01S0000 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111001111000000\nword: SLICEB.K1.INIT 1111110000110000\nword: SLICEC.K0.INIT 1111001111000000\nword: SLICEC.K1.INIT 1111001111000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R27C58:PLC2\narc: H00L0000 H02E0001\narc: H00R0000 V02S0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 H06E0103\narc: N1_V02N0601 V01N0001\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0601 H01E0001\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02S0101\narc: V00T0000 V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 N3_V06S0303\narc: E1_H02E0401 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: A6 H00R0000\narc: B0 V00T0000\narc: B1 E1_H02W0301\narc: B2 H02E0301\narc: B3 H00R0100\narc: B4 H00R0000\narc: B6 H02E0301\narc: B7 V02S0501\narc: C0 V02S0601\narc: C1 V02N0401\narc: C2 H02W0601\narc: C3 V02N0601\narc: C4 V00T0100\narc: C6 E1_H01E0101\narc: C7 W1_H02E0401\narc: CE0 H00L0000\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 F0\narc: D2 V01S0100\narc: D3 W1_H02E0001\narc: D4 F2\narc: D5 F0\narc: D6 H00L0100\narc: D7 H02E0201\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H01W0100 Q1\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V02N0701 F7\narc: N3_V06N0103 Q1\narc: N3_V06N0203 Q4\narc: N3_V06N0303 F6\narc: V01S0100 F3\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 1111001111000000\nword: SLICEA.K0.INIT 1100000011110011\nword: SLICEA.K1.INIT 0000111100001100\nword: SLICEC.K0.INIT 0000110000111111\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 0000001010001010\nword: SLICED.K1.INIT 1111001111000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R27C59:PLC2\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0601 H02W0601\narc: S1_V02S0001 H02W0001\narc: S3_V06S0203 N3_V06S0103\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0601 H01E0001\narc: W1_H02W0301 W3_H06E0003\n\n.tile R27C5:PLC2\narc: E1_H02E0201 V06S0103\narc: E1_H02E0601 V02S0601\narc: H00R0000 H02E0601\narc: H00R0100 V02N0501\narc: N1_V02N0001 E1_H01W0000\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0100 E1_H02W0701\narc: W1_H02W0101 V06S0103\narc: B3 H01W0100\narc: C3 E1_H02W0401\narc: CE0 H00R0100\narc: CE2 H02W0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 H02W0001\narc: F3 F3_SLICE\narc: H01W0100 Q6\narc: M0 V00B0100\narc: M4 W1_H02E0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0203 Q4\narc: S1_V02S0301 F3\narc: V01S0100 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R27C60:PLC2\narc: N1_V02N0401 W1_H02E0401\narc: S3_V06S0103 N3_V06S0103\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: W1_H02W0601 W3_H06E0303\n\n.tile R27C61:PLC2\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0203\narc: W1_H02W0101 W3_H06E0103\n\n.tile R27C62:PLC2\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0401 N3_V06S0203\narc: S3_V06S0203 N3_V06S0203\n\n.tile R27C63:PLC2\narc: S3_V06S0203 N3_V06S0103\n\n.tile R27C64:PLC2\narc: E3_H06E0303 N3_V06S0303\narc: S3_V06S0303 N3_V06S0303\narc: E3_H06E0103 W3_H06E0003\n\n.tile R27C65:PLC2\narc: N1_V02N0401 N3_V06S0203\narc: S3_V06S0303 N3_V06S0203\n\n.tile R27C66:PLC2\narc: S3_V06S0203 N3_V06S0103\n\n.tile R27C67:PLC2\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0601 H06E0303\narc: S3_V06S0103 N3_V06S0103\n\n.tile R27C69:PLC2\narc: E1_H02E0201 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\n\n.tile R27C6:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 V01N0101\narc: H00R0000 V02N0401\narc: N1_V02N0201 V01N0001\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 H06W0103\narc: S1_V02S0701 E1_H02W0701\narc: V00T0000 V02S0601\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0701 V01N0101\narc: C5 H02E0601\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D5 V02N0601\narc: F5 F5_SLICE\narc: H01W0000 Q6\narc: M0 E1_H02W0601\narc: M2 H02W0601\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V02N0001 Q0\narc: N3_V06N0303 F5\narc: V01S0100 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000001111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R27C70:PLC2\narc: V01S0000 N3_V06S0103\narc: E1_H02E0101 W3_H06E0103\n\n.tile R27C7:PLC2\narc: E1_H02E0401 N3_V06S0203\narc: H00L0000 V02S0201\narc: H00R0000 H02W0401\narc: H00R0100 V02N0701\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 V01N0001\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 E1_H02W0601\narc: V00T0000 W1_H02E0201\narc: V00T0100 H02W0301\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 V06S0203\narc: CE2 H00R0100\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 E1_H02W0201\narc: D2 V01S0100\narc: D3 H00R0000\narc: E1_H01E0001 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q4\narc: M0 V00T0000\narc: M1 H00L0000\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N3_V06N0103 F1\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R27C8:PLC2\narc: E3_H06E0103 N3_V06S0103\narc: E3_H06E0203 N3_V06S0203\narc: H00R0000 V02N0601\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 E1_H02W0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 H02E0401\narc: V00B0100 N1_V02S0301\narc: V00T0100 E1_H02W0301\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V06S0203\narc: CE0 V02N0201\narc: CE1 H00R0000\narc: CE2 E1_H02W0101\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: M0 V00T0100\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q2\narc: V01S0000 Q0\narc: W1_H02W0401 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R27C9:PLC2\narc: E1_H02E0101 V02N0101\narc: E3_H06E0203 N3_V06S0203\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0301 N3_V06S0003\narc: S3_V06S0103 N3_V06S0003\narc: V01S0000 N3_V06S0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0601 V06S0303\narc: W3_H06W0103 N3_V06S0103\n\n.tile R28C10:PLC2\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 S1_V02N0601\narc: H00R0000 V02S0601\narc: H01W0100 E3_H06W0303\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 E3_H06W0303\narc: N3_V06N0003 H06W0003\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0203 H06E0203\narc: V00T0100 H02E0301\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N3_V06S0303\narc: W3_H06W0303 E3_H06W0303\narc: CE0 E1_H02W0101\narc: CE1 H00R0000\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q2\narc: M0 H02E0601\narc: M2 V00T0100\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: V01S0000 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R28C11:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 E1_H01W0100\narc: H00L0100 V02S0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0701 H01E0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 H06W0203\narc: V00B0100 W1_H02E0501\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 E1_H02W0001\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: H01W0100 Q0\narc: M0 V00B0100\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: S1_V02S0601 Q6\narc: S3_V06S0003 Q0\narc: V01S0100 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R28C12:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 E1_H01W0100\narc: E3_H06E0103 H01E0101\narc: H00R0000 N1_V02S0601\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H01E0101\narc: S1_V02S0501 H02E0501\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 W1_H02E0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0101 W3_H06E0103\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 N1_V02S0601\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: H01W0100 Q6\narc: M0 V00B0000\narc: M2 V00B0100\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: V01S0000 Q4\narc: V01S0100 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C13:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0103 V06N0103\narc: H00L0100 N1_V02S0101\narc: H00R0000 W1_H02E0401\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 H06W0203\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H01E0101\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0201\narc: V00B0100 V02S0101\narc: V00T0000 V02S0601\narc: V00T0100 H02W0101\narc: V01S0100 N3_V06S0303\narc: W3_H06W0103 E3_H06W0003\narc: A0 E1_H02W0701\narc: A1 H00L0000\narc: A3 V02N0701\narc: A4 H02E0501\narc: A5 V02N0301\narc: A7 V00T0100\narc: B0 V02N0101\narc: B1 H02E0101\narc: B3 E1_H02W0101\narc: B4 W1_H02E0301\narc: B5 V02N0501\narc: B7 N1_V01S0000\narc: C0 E1_H01W0000\narc: C1 W1_H02E0601\narc: C3 H02W0601\narc: C4 V00B0100\narc: C5 H01E0001\narc: C7 E1_H01E0101\narc: CE0 H00R0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 V02N0001\narc: D3 H02W0001\narc: D4 H00L0100\narc: D5 E1_H01W0100\narc: D7 N1_V02S0401\narc: E1_H01E0101 F3\narc: E3_H06E0003 Q0\narc: E3_H06E0303 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q0\narc: H01W0100 Q5\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q0\narc: N3_V06N0003 Q0\narc: N3_V06N0103 F1\narc: N3_V06N0303 Q5\narc: S3_V06S0003 Q0\narc: V01S0000 F6\narc: W1_H02W0001 Q0\narc: W3_H06W0003 Q0\narc: W3_H06W0203 F4\narc: W3_H06W0303 Q5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000001000000000\nword: SLICEA.K0.INIT 1011000010111011\nword: SLICEA.K1.INIT 1100010011110101\nword: SLICEC.K0.INIT 0011110010011001\nword: SLICEC.K1.INIT 1011101110001011\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111011101110011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R28C14:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 N1_V02S0001\narc: H00L0100 S1_V02N0301\narc: H00R0100 H02E0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 H02E0401\narc: S1_V02S0701 E1_H02W0701\narc: V00B0000 H02E0601\narc: V00B0100 V02S0101\narc: V00T0000 H02E0201\narc: V00T0100 V02S0501\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0303 E3_H06W0303\narc: A1 H00L0000\narc: A3 V02N0701\narc: A7 V02S0301\narc: B1 E1_H01W0100\narc: B3 H02W0101\narc: B4 V00B0100\narc: B7 V02N0501\narc: C1 N1_V01N0001\narc: C3 S1_V02N0601\narc: C4 H02W0601\narc: C7 V02N0201\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: D3 V02N0001\narc: D4 S1_V02N0401\narc: D5 H02W0201\narc: D7 H00L0100\narc: E3_H06E0203 Q4\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F0\narc: H01W0100 F6\narc: LSR1 V00T0000\narc: M0 V00T0100\narc: M4 V00B0000\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F3\narc: N3_V06N0203 Q4\narc: W3_H06W0203 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000001000000000\nword: SLICEC.K0.INIT 1111111111001111\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111011101110011\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111011101110011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R28C15:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 E3_H06W0303\narc: H00L0000 E1_H02W0201\narc: H00R0100 W1_H02E0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0101 H06E0103\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H02W0701\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 H02W0401\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02N0601\narc: V00T0100 H02E0101\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V02N0201\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 E3_H06W0203\narc: W3_H06W0103 V06S0103\narc: A0 H00L0000\narc: A1 E1_H02W0501\narc: A5 E1_H01W0000\narc: A7 F5\narc: B0 E1_H02W0101\narc: B1 V02N0101\narc: B5 E1_H02W0301\narc: B6 N1_V01S0000\narc: B7 V00B0000\narc: C0 H00R0100\narc: C1 H02E0601\narc: C5 V00T0100\narc: C6 H02E0401\narc: C7 V00T0000\narc: CE1 N1_V02S0201\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 V02N0001\narc: D5 H02E0201\narc: D6 S1_V02N0601\narc: D7 V02N0401\narc: E1_H01E0001 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F0\narc: LSR0 H02W0301\narc: M2 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q2\narc: N3_V06N0203 F7\narc: N3_V06N0303 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0101001111111111\nword: SLICEA.K1.INIT 1010100010101010\nword: SLICED.K0.INIT 0011001100001111\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R28C16:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0501 E1_H01W0100\narc: H00L0000 N1_V02S0001\narc: H00R0000 S1_V02N0601\narc: H00R0100 W1_H02E0501\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 S1_V02N0101\narc: S1_V02S0401 E1_H02W0401\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0401\narc: V00B0100 N1_V02S0101\narc: V00T0100 V02S0501\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V06S0003\narc: W1_H02W0601 E3_H06W0303\narc: W3_H06W0203 V01N0001\narc: W3_H06W0303 E3_H06W0303\narc: A4 H02E0501\narc: A5 E1_H02W0701\narc: B0 V00T0000\narc: B4 V01S0000\narc: B5 H02E0101\narc: C0 V02N0401\narc: C4 H02E0601\narc: C5 V00T0100\narc: CE1 H00R0100\narc: CE2 H00L0000\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V01S0100\narc: D4 V00B0000\narc: D5 W1_H02E0001\narc: E1_H01E0101 Q2\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q5\narc: M0 E1_H02W0601\narc: M2 N1_V01N0001\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F5\narc: S1_V02S0501 F5\narc: S1_V02S0601 Q6\narc: V00T0000 Q0\narc: V01S0000 Q2\narc: V01S0100 F5\narc: W1_H02W0401 F4\narc: W1_H02W0701 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0001010100111111\nword: SLICEC.K1.INIT 0111000001111100\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R28C17:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 E1_H01W0000\narc: H00L0000 V02N0201\narc: H00R0000 N1_V02S0601\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 W1_H02E0601\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02W0001\narc: V00T0100 H02W0301\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 E3_H06W0303\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0203\narc: A3 V02N0701\narc: A5 H02E0501\narc: A7 H00L0000\narc: B2 F3\narc: B3 V02N0301\narc: B5 V02S0701\narc: B7 E1_H02W0301\narc: C2 H00R0100\narc: C3 E1_H02W0601\narc: C5 E1_H02W0401\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V01S0100\narc: D3 V00B0100\narc: D5 H02E0201\narc: D7 V00B0000\narc: E3_H06E0103 F2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0100 Q0\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: N3_V06N0103 F2\narc: V01S0100 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1100000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R28C18:PLC2\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 N1_V02S0001\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 V01N0001\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 V01N0101\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 N1_V02S0201\narc: V00T0000 S1_V02N0601\narc: V00T0100 V02S0501\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02S0701\narc: W3_H06W0203 V01N0001\narc: W3_H06W0003 E3_H06W0003\narc: A7 H00R0000\narc: B2 H01W0100\narc: B7 N1_V01S0000\narc: C2 H00L0000\narc: C7 E1_H02W0401\narc: CE0 H02W0101\narc: CE2 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D2 V02S0001\narc: D3 H02W0001\narc: D7 H00R0100\narc: E1_H01E0101 Q2\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0000 F7\narc: H01W0100 Q2\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R28C19:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0601 E1_H01W0000\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0501 V01N0101\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 W1_H02E0501\narc: V00T0000 N1_V02S0401\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 N3_V06S0203\narc: H01W0100 W3_H06E0303\narc: N3_V06N0103 W3_H06E0103\narc: S1_V02S0301 W3_H06E0003\narc: W3_H06W0003 E1_H02W0301\narc: W3_H06W0203 E1_H02W0401\narc: W3_H06W0303 E1_H02W0601\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0103\narc: A3 V00B0000\narc: B3 H00R0000\narc: C3 H02W0601\narc: CE0 E1_H02W0101\narc: CE2 W1_H02E0101\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: E1_H01E0001 Q0\narc: E3_H06E0103 F2\narc: F2 F5B_SLICE\narc: H00R0000 Q6\narc: M0 V00T0000\narc: M2 W1_H02E0601\narc: M4 V00T0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: N3_V06N0303 Q6\narc: V00B0000 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R28C20:PLC2\narc: H00L0000 H02W0201\narc: H00L0100 V02S0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02S0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H06W0203\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0203 H06W0203\narc: V00B0000 H02E0401\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0701 W3_H06E0203\narc: W3_H06W0303 V01N0101\narc: A0 H00L0000\narc: A4 V02N0101\narc: A5 W1_H02E0501\narc: B0 V00B0000\narc: B4 V02S0501\narc: B5 N1_V02S0501\narc: C0 H00L0100\narc: C4 V02S0001\narc: C5 V00T0100\narc: CE1 H00R0000\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D4 H02W0001\narc: D5 H00R0100\narc: E3_H06E0103 Q2\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F5\narc: M0 H02E0601\narc: M2 V00T0000\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q6\narc: S3_V06S0003 F0\narc: V01S0100 F4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000010\nword: SLICEC.K1.INIT 0000100000000000\nword: SLICEA.K0.INIT 0000000000010011\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C21:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 N3_V06S0003\narc: H00R0000 E1_H02W0601\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 E1_H02W0501\narc: S1_V02S0401 H02W0401\narc: S1_V02S0701 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 N1_V02S0601\narc: V00T0100 E1_H02W0101\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0203 V01N0001\narc: W3_H06W0303 E1_H02W0501\narc: CE0 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: LSR0 V00B0100\narc: LSR1 V00T0100\narc: M0 V00B0000\narc: M4 E1_H02W0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R28C22:PLC2\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0103 N1_V01S0100\narc: H00L0000 S1_V02N0201\narc: H00R0000 V02N0401\narc: H00R0100 H02W0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0001 H02W0001\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00B0100 S1_V02N0301\narc: V00T0100 V02S0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 N3_V06S0303\narc: W3_H06W0103 N3_V06S0103\narc: W3_H06W0303 N3_V06S0303\narc: A1 H00R0000\narc: A2 E1_H01E0001\narc: A5 H02E0701\narc: B0 H02W0301\narc: B1 E1_H02W0101\narc: B2 H00R0100\narc: B5 H02E0101\narc: C0 V02S0401\narc: C1 V02S0401\narc: C2 V02S0401\narc: C3 N1_V01N0001\narc: C5 N1_V02S0201\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02N0001\narc: D2 V00B0100\narc: D3 V00T0100\narc: D5 H02W0201\narc: E1_H01E0001 Q2\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F5\narc: H01W0100 Q6\narc: M0 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q0\narc: N3_V06N0003 F3\narc: V00T0000 Q0\narc: V01S0100 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000001000000000\nword: SLICEB.K0.INIT 1111000000100010\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 1100000000000000\nword: SLICEA.K1.INIT 1011000100110011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R28C23:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V06N0303\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 H02E0201\narc: H00L0100 V02S0101\narc: H00R0000 V02S0601\narc: H01W0100 E3_H06W0303\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 E1_H01W0100\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0401 H06W0203\narc: S1_V02S0701 N1_V02S0601\narc: V00B0000 H02W0601\narc: V00B0100 V02S0101\narc: V00T0100 V02S0501\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 N1_V02S0701\narc: E3_H06E0103 W3_H06E0103\narc: A1 W1_H02E0501\narc: A2 N1_V02S0501\narc: A3 H02E0501\narc: A6 H00L0000\narc: A7 V02N0301\narc: B1 V02S0101\narc: B2 V02S0101\narc: B3 N1_V02S0301\narc: B4 V02S0701\narc: B6 V00B0100\narc: B7 V00B0000\narc: C1 V02S0601\narc: C2 V02S0601\narc: C3 H00L0100\narc: C4 V00T0100\narc: C5 V00T0100\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: D1 W1_H02E0001\narc: D2 W1_H02E0001\narc: D3 H00R0000\narc: D4 H02W0001\narc: D5 H02W0001\narc: D6 H02W0201\narc: D7 V02S0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: E3_H06E0203 F4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: N1_V01N0001 F5\narc: N1_V02N0401 F4\narc: N1_V02N0601 F4\narc: N3_V06N0303 F5\narc: S1_V02S0601 F4\narc: S3_V06S0203 F4\narc: V01S0000 F3\narc: W1_H02W0001 F2\narc: W3_H06W0203 F4\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000010\nword: SLICEC.K0.INIT 1100000011001100\nword: SLICEC.K1.INIT 1111000011111111\nword: SLICEB.K0.INIT 0000000000000010\nword: SLICEB.K1.INIT 0000100000000000\nword: SLICED.K0.INIT 0000000000000111\nword: SLICED.K1.INIT 0000100000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R28C24:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 V01N0101\narc: H00L0000 V02S0201\narc: H00L0100 V02S0101\narc: H00R0000 N1_V02S0601\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H06E0203\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 H06W0003\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02W0601\narc: V00B0100 H02E0501\narc: V00T0100 V02S0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 V06N0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A3 E1_H02W0701\narc: A4 W1_H02E0701\narc: A5 V02S0301\narc: B3 H00R0000\narc: B4 H02E0101\narc: B5 H02E0101\narc: C0 H02E0401\narc: C1 H00L0000\narc: C3 H00L0100\narc: C4 E1_H01E0101\narc: C5 H02E0601\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V00B0100\narc: D3 V00T0100\narc: D4 H00R0100\narc: D5 V02S0601\narc: E1_H01E0101 F3\narc: E1_H02E0401 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0100 F5\narc: H01W0100 F1\narc: LSR0 V00T0000\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N3_V06N0103 F1\narc: V00T0000 F0\narc: V01S0100 F1\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000100000000000\nword: SLICEA.K0.INIT 0000111111111111\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0000000000000111\nword: SLICEC.K1.INIT 0000000000000010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R28C25:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 V01N0001\narc: H00L0000 S1_V02N0001\narc: H00L0100 V02N0301\narc: H00R0100 W1_H02E0701\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0203 N3_V06S0203\narc: V00B0100 V02N0101\narc: V00T0000 H02W0201\narc: V00T0100 E1_H02W0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V01N0101\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0003 N1_V01S0000\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 H00L0000\narc: A3 H02E0701\narc: A4 N1_V01N0101\narc: A5 N1_V01N0101\narc: B0 H00R0100\narc: B2 E1_H02W0301\narc: B3 H02E0101\narc: B4 V02N0701\narc: B5 E1_H02W0101\narc: B7 V00B0000\narc: C0 S1_V02N0401\narc: C2 V02N0401\narc: C3 H02W0601\narc: C4 V00T0000\narc: C5 E1_H02W0401\narc: C6 V02S0201\narc: C7 V02N0001\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D2 V02S0001\narc: D3 F2\narc: D4 E1_H02W0201\narc: D5 W1_H02E0201\narc: D6 H00L0100\narc: D7 E1_H02W0001\narc: E1_H01E0101 F6\narc: E1_H02E0601 F6\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F0\narc: H01W0100 F2\narc: M0 V00B0100\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q4\narc: N1_V02N0001 F2\narc: N3_V06N0103 F2\narc: N3_V06N0203 F7\narc: S1_V02S0001 F2\narc: S1_V02S0601 F6\narc: S3_V06S0103 F2\narc: V00B0000 F6\narc: W1_H02W0001 F2\narc: W1_H02W0101 F3\nword: SLICEC.K0.INIT 1111001000000010\nword: SLICEC.K1.INIT 0000011100000000\nword: SLICEB.K0.INIT 1100000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEA.K0.INIT 0001010100111111\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C26:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0303 V06S0303\narc: H00L0000 E1_H02W0201\narc: H00L0100 S1_V02N0301\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0003 V01N0001\narc: N3_V06N0203 V01N0001\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 V01N0001\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N1_V02S0301\narc: V00T0000 S1_V02N0601\narc: V00T0100 V02N0501\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0101 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: A1 H00R0000\narc: A4 V02S0301\narc: A6 H00L0000\narc: A7 V02S0101\narc: B1 W1_H02E0301\narc: B4 N1_V01S0000\narc: B6 E1_H02W0301\narc: B7 V02S0501\narc: C1 H00R0100\narc: C4 V02S0201\narc: C6 V02N0001\narc: C7 V00T0100\narc: D1 V02N0201\narc: D4 V02N0401\narc: D6 H00L0100\narc: D7 H01W0000\narc: E1_H01E0001 F7\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H01W0000 F6\narc: M0 V00B0000\narc: M1 E1_H02W0001\narc: M2 N1_V01N0001\narc: M4 V00T0000\narc: N1_V01N0001 F4\narc: S3_V06S0303 F6\narc: V00B0000 F4\nword: SLICED.K0.INIT 0100000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000111\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R28C27:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 S1_V02N0701\narc: H00R0000 V02S0601\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00B0100 S1_V02N0301\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 V01N0101\narc: W3_H06W0003 V01N0001\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: B5 V01S0000\narc: B7 E1_H02W0301\narc: C4 E1_H01E0101\narc: C5 V00T0000\narc: C6 V00B0100\narc: C7 W1_H02E0601\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 H01W0000\narc: D5 V02S0401\narc: D6 H01W0000\narc: D7 S1_V02N0601\narc: E1_H01E0001 F6\narc: E1_H01E0101 F5\narc: E1_H02E0201 Q2\narc: E3_H06E0103 Q2\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q2\narc: M0 V00B0000\narc: M2 H02W0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q2\narc: N1_V02N0401 F4\narc: N1_V02N0501 F7\narc: S1_V02S0001 Q0\narc: S1_V02S0501 F5\narc: S3_V06S0303 F5\narc: V00T0000 Q2\narc: V01S0000 Q0\narc: V01S0100 Q0\narc: W1_H02W0401 F4\narc: W1_H02W0601 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000000000110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R28C28:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 V02S0701\narc: E3_H06E0003 V01N0001\narc: E3_H06E0303 N3_V06S0303\narc: H00L0000 S1_V02N0001\narc: H00L0100 V02N0101\narc: H00R0000 S1_V02N0601\narc: H00R0100 H02W0701\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 H01E0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 H06E0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0303 N3_V06S0303\narc: V00T0100 N1_V02S0501\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 E1_H02W0701\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0103 E3_H06W0103\narc: A1 V01N0101\narc: A2 S1_V02N0701\narc: A6 N1_V02S0101\narc: A7 W1_H02E0701\narc: B1 H02W0101\narc: B2 H00R0000\narc: B3 N1_V02S0301\narc: B6 V02N0501\narc: B7 H02E0101\narc: C1 V02N0601\narc: C2 H00L0000\narc: C3 H00R0100\narc: C6 V00B0100\narc: C7 S1_V02N0201\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: D2 H02W0201\narc: D3 F2\narc: D6 H00L0100\narc: D7 H02W0201\narc: E1_H01E0001 Q4\narc: E1_H01E0101 F1\narc: E1_H02E0401 F6\narc: E3_H06E0203 Q4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F7\narc: M4 V00T0100\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F3\narc: N1_V01N0101 Q4\narc: N1_V02N0701 F7\narc: N3_V06N0203 Q4\narc: S1_V02S0401 Q4\narc: V00B0100 F7\narc: V01S0000 Q4\narc: W1_H02W0001 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000100000000\nword: SLICEB.K0.INIT 0101011111111111\nword: SLICEB.K1.INIT 0000111100001100\nword: SLICED.K0.INIT 0001001101011111\nword: SLICED.K1.INIT 0100000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R28C29:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0003 V01N0001\narc: E3_H06E0303 V01N0101\narc: H00L0100 N1_V02S0301\narc: H00R0100 H02E0701\narc: H01W0000 E3_H06W0103\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0501 W1_H02E0501\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 H01E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H06W0103\narc: S1_V02S0601 N1_V01S0000\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 H02W0601\narc: V00T0000 H02W0001\narc: V00T0100 E1_H02W0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0101 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: S3_V06S0203 W3_H06E0203\narc: W3_H06W0103 E1_H02W0201\narc: W3_H06W0303 E3_H06W0303\narc: A7 H00R0000\narc: B4 H00R0000\narc: B7 S1_V02N0701\narc: C4 V02S0001\narc: C7 S1_V02N0001\narc: CE0 H00R0100\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D4 V02S0601\narc: D5 V02S0401\narc: D7 V02N0401\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 Q4\narc: H01W0100 Q0\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N3_V06N0103 Q2\narc: W1_H02W0401 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R28C2:PLC2\narc: E1_H02E0501 E3_H06W0303\narc: H00R0000 H02W0401\narc: H00R0100 H02E0501\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 H06W0103\narc: N1_V02N0401 H06W0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02S0001\narc: V00B0100 E1_H02W0701\narc: V00T0000 E1_H02W0001\narc: A1 H00R0000\narc: A5 E1_H01W0000\narc: B1 V00T0000\narc: B5 H02W0101\narc: C1 H00R0100\narc: C5 V02N0001\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D1 H02W0001\narc: D5 S1_V02N0601\narc: E1_H01E0101 F1\narc: E3_H06E0203 F4\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: LSR1 V00B0100\narc: M4 E1_H01E0101\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: S3_V06S0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010001011110011\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1010010100100001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R28C30:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0701 V01N0101\narc: E3_H06E0003 N3_V06S0003\narc: H00R0000 H02E0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H02W0701\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 H02W0401\narc: V00B0100 V02S0301\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 E1_H02W0601\narc: W3_H06W0303 E1_H01W0100\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: A3 V00T0000\narc: A5 S1_V02N0301\narc: B2 H01W0100\narc: B3 V02S0101\narc: B4 S1_V02N0701\narc: B5 V02S0701\narc: C2 H00L0100\narc: C3 H00R0100\narc: C4 V02N0001\narc: C5 V02N0201\narc: CE0 H00R0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D2 V01S0100\narc: D3 S1_V02N0001\narc: D4 V00B0000\narc: D5 H02E0201\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0100 F3\narc: H01W0100 F5\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: M0 V00B0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q6\narc: N3_V06N0103 F2\narc: S3_V06S0203 F4\narc: V00T0000 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000111100110011\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R28C31:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 E1_H02W0201\narc: H00L0100 V02S0301\narc: H00R0100 E1_H02W0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 N1_V01S0100\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 H06W0303\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 H06E0303\narc: V00B0000 V02S0201\narc: V00B0100 H02W0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0701 N3_V06S0203\narc: N1_V02N0701 W3_H06E0203\narc: N3_V06N0203 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A0 E1_H02W0501\narc: A3 H02E0701\narc: A6 W1_H02E0701\narc: A7 H02W0501\narc: B0 V02S0101\narc: B2 H02E0101\narc: B3 V02S0101\narc: B4 H02W0101\narc: B6 V00B0000\narc: B7 V02S0501\narc: C0 F6\narc: C2 H00L0000\narc: C3 V02S0601\narc: C4 V02S0201\narc: C6 H02E0401\narc: C7 H02E0401\narc: D0 V01S0100\narc: D2 H02E0201\narc: D3 N1_V02S0201\narc: D4 V02S0601\narc: D5 H00R0100\narc: D6 V02S0601\narc: D7 H00L0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 F2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F0\narc: M0 V00B0100\narc: M4 H02E0401\narc: V01S0100 F7\nword: SLICED.K0.INIT 0000100000000000\nword: SLICED.K1.INIT 0000001000000000\nword: SLICEB.K0.INIT 0000111100110011\nword: SLICEB.K1.INIT 0000000000000010\nword: SLICEC.K0.INIT 0011111111111111\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000000000111\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C32:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0103 H01E0101\narc: H00R0000 H02E0601\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H01E0001\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 H02E0701\narc: V00B0000 S1_V02N0201\narc: V00T0000 H02E0201\narc: V00T0100 H02E0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 V02S0701\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0201 W3_H06E0103\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 V06S0103\narc: W3_H06W0203 E1_H02W0401\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A0 V02N0701\narc: A2 W1_H02E0501\narc: A3 N1_V02S0701\narc: A4 N1_V02S0101\narc: A5 V00T0100\narc: A6 N1_V02S0301\narc: A7 H00R0000\narc: B2 H02W0101\narc: B3 V02N0301\narc: B4 V01S0000\narc: B5 N1_V02S0501\narc: B6 V00T0000\narc: B7 V00B0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: N1_V01N0001 F5\narc: N1_V01N0101 F3\narc: N1_V02N0001 F2\narc: N3_V06N0203 F4\narc: W3_H06W0303 F6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C33:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0501 W1_H02E0401\narc: H00L0000 H02E0201\narc: H00R0000 V02S0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 H02E0601\narc: V00B0100 H02W0701\narc: V00T0000 V02N0601\narc: V00T0100 V02N0701\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0701 E1_H02W0601\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0101 W3_H06E0103\narc: W3_H06W0003 E1_H02W0001\narc: W3_H06W0203 E1_H02W0401\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 N1_V02S0701\narc: A1 H02E0701\narc: A2 H02W0501\narc: A3 E1_H01E0001\narc: A4 V00T0000\narc: A5 V00T0100\narc: A6 V02N0101\narc: A7 S1_V02N0301\narc: B0 V00B0000\narc: B1 W1_H02E0301\narc: B2 H00L0000\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 H00R0000\narc: B6 V02S0501\narc: B7 H02W0301\narc: E1_H01E0101 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: N1_V01N0001 F5\narc: N1_V02N0201 F2\narc: S3_V06S0203 F4\narc: S3_V06S0303 F6\narc: W1_H02W0001 F0\narc: W1_H02W0501 F7\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C34:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0103 V06N0103\narc: H00L0000 V02S0001\narc: H00L0100 W1_H02E0101\narc: H00R0000 V02N0601\narc: H00R0100 V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 H06E0203\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0103 H01E0101\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0101\narc: V00T0000 W1_H02E0001\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 V02S0701\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0301 W3_H06E0003\narc: N1_V02N0601 W3_H06E0303\narc: S1_V02S0501 W3_H06E0303\narc: S3_V06S0103 W3_H06E0103\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0303 E1_H02W0601\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: A0 H00L0100\narc: A1 V02N0501\narc: A2 V01N0101\narc: A3 V00T0000\narc: A4 S1_V02N0101\narc: A5 H02W0701\narc: A6 E1_H02W0501\narc: A7 H00R0000\narc: B0 H00R0100\narc: B1 V00B0000\narc: B2 V02S0301\narc: B3 H00L0000\narc: B4 V00B0100\narc: B5 V00B0100\narc: B6 V00B0100\narc: B7 V00B0100\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: H01W0100 F4\narc: N1_V01N0001 F5\narc: S3_V06S0003 F3\narc: V01S0000 F1\narc: V01S0100 F0\narc: W1_H02W0401 F6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C35:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0003 N3_V06S0003\narc: E3_H06E0203 N3_V06S0203\narc: H00R0000 V02S0401\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 V01N0101\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 E1_H01W0100\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0001\narc: V00T0000 V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0501 H01E0101\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0203 E1_H02W0401\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\narc: A0 S1_V02N0501\narc: A1 W1_H02E0501\narc: A2 V00B0000\narc: A3 V02S0701\narc: A4 N1_V01S0100\narc: A5 V02S0101\narc: A6 E1_H02W0501\narc: A7 V00T0100\narc: B0 V00T0000\narc: B1 V00T0000\narc: B2 H00R0000\narc: B3 H00R0000\narc: B4 H00R0000\narc: B5 H00R0000\narc: B6 V00T0000\narc: B7 V00T0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F2\narc: S1_V02S0501 F5\narc: S3_V06S0203 F7\narc: V01S0100 F3\narc: W1_H02W0001 F0\narc: W1_H02W0401 F6\narc: W1_H02W0601 F4\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C36:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 E3_H06W0203\narc: E3_H06E0203 V01N0001\narc: H00L0000 H02W0201\narc: H00L0100 N1_V02S0101\narc: H00R0100 S1_V02N0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0103 S1_V02N0201\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 W1_H02E0401\narc: V00B0100 E1_H02W0701\narc: V00T0000 V02S0601\narc: V00T0100 V02N0501\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 E3_H06W0203\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0203 E3_H06W0103\narc: A3 E1_H02W0501\narc: A5 H02E0701\narc: A7 H00L0000\narc: B3 H00R0000\narc: B4 H02E0101\narc: B5 N1_V02S0701\narc: B6 V00B0000\narc: B7 V00B0100\narc: C3 H02E0401\narc: C4 V00T0100\narc: C5 V02N0001\narc: C6 V00T0000\narc: C7 V02N0001\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 V01S0100\narc: D3 S1_V02N0001\narc: D4 H00L0100\narc: D5 V02N0401\narc: D6 H00L0100\narc: D7 V02N0401\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H01W0000 F7\narc: M2 W1_H02E0601\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F5\narc: S1_V02S0501 F5\narc: V01S0000 F4\narc: V01S0100 F7\narc: W3_H06W0103 Q2\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1100110010100000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110010100000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111110011111010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R28C37:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0103 N3_V06S0103\narc: H00R0100 N1_V02S0701\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 E1_H02W0501\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 H06W0303\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00T0000 H02E0201\narc: V00T0100 V02N0501\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 S1_V02N0501\narc: E1_H02E0201 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: B0 E1_H02W0301\narc: B6 H02E0101\narc: C0 E1_H01W0000\narc: C6 V00T0100\narc: CE1 V02S0201\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 W1_H02E0201\narc: D6 H02E0001\narc: D7 W1_H02E0001\narc: E1_H01E0101 Q2\narc: F0 F5A_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q4\narc: M0 W1_H02E0601\narc: M2 V00B0000\narc: M4 E1_H01E0101\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N3_V06N0003 F0\narc: N3_V06N0303 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111000000110011\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1111000000110011\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R28C38:PLC2\narc: E1_H02E0501 N3_V06S0303\narc: E3_H06E0003 W1_H02E0301\narc: H00L0100 V02S0101\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H06E0203\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N3_V06S0203\narc: V00T0000 H02W0001\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 E3_H06W0203\narc: H01W0000 W3_H06E0103\narc: W3_H06W0003 E1_H02W0001\narc: W3_H06W0103 E1_H02W0101\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0303 W3_H06E0303\narc: A1 H00L0100\narc: B1 V00T0000\narc: B5 H02E0301\narc: B6 H02E0301\narc: B7 E1_H02W0301\narc: C1 H02E0601\narc: C3 V02N0401\narc: C4 V02N0201\narc: C5 H02W0401\narc: C6 V02S0201\narc: C7 H02E0601\narc: D1 V01S0100\narc: D3 V01S0100\narc: D4 H00R0100\narc: D5 S1_V02N0601\narc: D6 S1_V02N0601\narc: D7 S1_V02N0601\narc: E1_H01E0001 F5\narc: E1_H01E0101 F1\narc: E1_H02E0101 F3\narc: E1_H02E0401 F4\narc: E1_H02E0601 F6\narc: E1_H02E0701 F5\narc: E3_H06E0203 F4\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0100 F7\narc: N1_V01N0101 F5\narc: V01S0100 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011001010\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011110000\nword: SLICEC.K0.INIT 0000000011110000\nword: SLICEC.K1.INIT 0011000011110000\nword: SLICED.K0.INIT 1100000000000000\nword: SLICED.K1.INIT 1100000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R28C39:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V02S0701\narc: H00L0100 V02S0301\narc: H00R0000 V02N0601\narc: H00R0100 N1_V02S0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 H01E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V02S0401\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0401\narc: V00B0000 H02E0601\narc: V00T0000 N1_V02S0601\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H02W0401\narc: E1_H01E0101 W3_H06E0203\narc: W3_H06W0003 E1_H02W0301\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E1_H01W0000\narc: A0 H00R0000\narc: A2 H02W0701\narc: A3 V00B0000\narc: A4 N1_V02S0101\narc: A5 V00T0000\narc: A6 H02E0501\narc: A7 N1_V01S0100\narc: B2 W1_H02E0101\narc: B3 H00R0100\narc: B4 N1_V01S0000\narc: B5 H01E0101\narc: B6 V02S0501\narc: B7 H02E0101\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q7\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0301 Q3\narc: N3_V06N0203 Q7\narc: W1_H02W0501 Q5\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C3:PLC2\narc: E1_H02E0401 W1_H02E0101\narc: H00R0100 E1_H02W0701\narc: N1_V02N0201 E1_H02W0201\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 H02W0401\narc: V00B0100 V02N0101\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 E1_H01W0100\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: H01W0000 Q4\narc: H01W0100 Q6\narc: M0 V00T0100\narc: M2 V00B0000\narc: M4 E1_H02W0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: S1_V02S0001 Q2\narc: S1_V02S0201 Q0\narc: S1_V02S0401 Q6\narc: S1_V02S0601 Q4\narc: S3_V06S0003 Q0\narc: V01S0000 Q6\narc: V01S0100 Q0\narc: W1_H02W0401 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R28C40:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 S1_V02N0501\narc: H00L0000 V02S0201\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 N1_V02S0101\narc: V00B0000 N1_V02S0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 S1_V02N0601\narc: V00T0100 E1_H02W0301\narc: W1_H02W0301 H01E0101\narc: W1_H02W0701 E1_H02W0601\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0601 W3_H06E0303\narc: N1_V02N0301 W3_H06E0003\narc: S3_V06S0303 W3_H06E0303\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: A0 H00R0000\narc: A1 V01N0101\narc: A2 H02E0701\narc: A3 N1_V02S0701\narc: A4 H02E0501\narc: A5 S1_V02N0301\narc: A6 V00T0100\narc: A7 H00L0000\narc: B0 V01N0001\narc: B1 V00B0000\narc: B2 H00R0100\narc: B3 V02S0101\narc: B4 V00B0100\narc: B5 V02S0501\narc: B6 V02N0501\narc: B7 V00T0000\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q3\narc: H01W0100 Q2\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0101 Q3\narc: N3_V06N0003 Q0\narc: N3_V06N0103 Q2\narc: N3_V06N0203 Q4\narc: N3_V06N0303 Q5\narc: W1_H02W0001 Q0\narc: W1_H02W0101 Q1\narc: W3_H06W0203 Q7\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C41:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V06N0303\narc: E1_H02E0701 V02S0701\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0103 N1_V01S0100\narc: H00L0100 V02N0301\narc: H00R0000 N1_V02S0601\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0601 H02E0601\narc: N3_V06N0003 H01E0001\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02E0401\narc: V00T0000 V02S0401\narc: V00T0100 E1_H02W0301\narc: W1_H02W0701 N1_V02S0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0601 W3_H06E0303\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0401 W3_H06E0203\narc: S1_V02S0301 W3_H06E0003\narc: S3_V06S0203 W3_H06E0203\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A0 H00R0000\narc: A1 H02E0501\narc: A2 H00L0100\narc: A3 V01N0101\narc: A4 E1_H02W0701\narc: A5 H02W0501\narc: A6 H02W0701\narc: A7 V00T0100\narc: B0 V02S0101\narc: B1 V00T0000\narc: B2 V02S0301\narc: B3 H02E0301\narc: B4 V02S0501\narc: B5 H02W0101\narc: B6 V00B0000\narc: B7 V00B0000\narc: CE0 W1_H02E0101\narc: CE1 W1_H02E0101\narc: CE2 W1_H02E0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: H01W0100 Q2\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V02N0701 Q7\narc: S1_V02S0001 Q0\narc: V01S0000 Q6\narc: V01S0100 Q4\narc: W1_H02W0101 Q1\narc: W1_H02W0301 Q3\narc: W3_H06W0003 Q0\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C42:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V06S0003\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 H01E0001\narc: H00L0000 V02S0001\narc: H00L0100 V02S0101\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0103 S1_V02N0201\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0203\narc: V00B0100 E1_H02W0701\narc: V00T0000 S1_V02N0401\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02S0701\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: A0 H02W0501\narc: A1 E1_H02W0501\narc: A2 S1_V02N0501\narc: A3 V02N0701\narc: A4 S1_V02N0301\narc: A5 V00T0000\narc: A6 V02N0301\narc: A7 V02N0101\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 V00B0100\narc: B6 V00B0100\narc: B7 V00B0100\narc: CE0 H00L0100\narc: CE1 H00L0000\narc: CE2 H00L0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q1\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0000 Q6\narc: V01S0100 Q4\narc: W3_H06W0003 Q3\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q7\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C43:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0303 V01N0101\narc: H00L0000 H02W0001\narc: H00R0000 W1_H02E0401\narc: H00R0100 H02W0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 V01N0101\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0201\narc: V00T0000 V02N0601\narc: V01S0100 N3_V06S0303\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 V02S0301\narc: E1_H01E0001 W3_H06E0003\narc: W3_H06W0303 N1_V01S0100\narc: A0 V02S0501\narc: A1 H00L0000\narc: A4 V00B0000\narc: A5 V02S0101\narc: A6 V02N0301\narc: A7 E1_H02W0501\narc: B0 H00R0100\narc: B1 H00R0100\narc: B4 H00R0000\narc: B5 V02N0501\narc: B6 H01E0101\narc: B7 V00T0000\narc: C4 H02E0601\narc: C5 H02E0601\narc: C6 H02E0601\narc: C7 H02E0601\narc: CE0 H02E0101\narc: CLK0 G_HPBX0000\narc: D4 W1_H02E0001\narc: D5 W1_H02E0001\narc: D6 W1_H02E0001\narc: D7 W1_H02E0001\narc: E1_H01E0101 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F4\narc: MUXCLK0 CLK0\narc: W1_H02W0501 F7\narc: W1_H02W0701 F5\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q1\nword: SLICEC.K0.INIT 1100101010101010\nword: SLICEC.K1.INIT 1010110011001100\nword: SLICED.K0.INIT 1010110011001100\nword: SLICED.K1.INIT 1010110011001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C44:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V06N0003\narc: E1_H02E0501 N3_V06S0303\narc: E3_H06E0103 V01N0101\narc: H00L0000 W1_H02E0001\narc: H00R0000 W1_H02E0401\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0401\narc: V00B0000 N1_V02S0001\narc: V00B0100 N1_V02S0101\narc: V00T0000 N1_V02S0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 V01N0001\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 H01E0101\narc: E1_H02E0601 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: B0 V02N0101\narc: B1 V02N0101\narc: B2 H02W0301\narc: B4 E1_H02W0301\narc: B6 H02W0101\narc: C0 H00L0000\narc: C1 H00L0000\narc: C2 H02E0601\narc: C4 H02E0601\narc: C6 H02W0601\narc: D0 V00T0100\narc: D1 H00R0000\narc: D2 E1_H02W0001\narc: D3 V02S0001\narc: D4 E1_H01W0100\narc: D5 V02S0401\narc: D6 E1_H01W0100\narc: D7 V02S0401\narc: E1_H01E0001 F0\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F0\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 V00T0000\narc: M6 V00B0000\narc: N1_V01N0001 F4\narc: V01S0100 F2\narc: W3_H06W0303 F6\nword: SLICED.K0.INIT 1100111100000011\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111001100000011\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 1111001100000011\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111110000001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R28C45:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V02N0701\narc: E3_H06E0003 V06N0003\narc: E3_H06E0103 V06N0103\narc: E3_H06E0203 H01E0001\narc: H00L0100 H02E0301\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02N0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0003 V01N0001\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 V02S0201\narc: V00B0100 H02W0501\narc: V00T0100 H02W0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0501 V02S0501\narc: A3 H02E0501\narc: B3 H00R0100\narc: B4 E1_H02W0101\narc: B6 S1_V02N0701\narc: C3 N1_V02S0601\narc: C4 N1_V02S0201\narc: C6 H02W0601\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 H02W0201\narc: D4 N1_V02S0401\narc: D5 V02N0401\narc: D6 H02E0001\narc: D7 V02N0401\narc: E1_H01E0001 F1\narc: E1_H01E0101 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F1\narc: H01W0100 F1\narc: M0 E1_H02W0601\narc: M1 H00L0100\narc: M2 E1_H02W0601\narc: M4 V00B0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: N1_V02N0301 F1\narc: V01S0000 Q1\narc: W1_H02W0601 F6\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000001111001111\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000110010001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R28C46:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0203 N3_V06S0203\narc: H00L0000 H02E0201\narc: H00R0000 H02E0601\narc: H00R0100 S1_V02N0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H01E0001\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 V01N0001\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02W0701\narc: V00T0000 H02E0201\narc: V00T0100 V02S0501\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 H01E0101\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 V01N0101\narc: N1_V02N0701 W3_H06E0203\narc: W3_H06W0003 N3_V06S0003\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0103 W3_H06E0003\narc: A0 V02S0701\narc: A1 V02S0701\narc: A2 V02S0701\narc: A3 V02S0701\narc: A4 H02E0501\narc: A5 S1_V02N0301\narc: B0 V00T0000\narc: B1 V00T0000\narc: B2 H00L0000\narc: B3 H00L0000\narc: B4 H02W0301\narc: B5 H00R0000\narc: B6 H02E0101\narc: B7 V01S0000\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 V00B0100\narc: C5 H02E0401\narc: C6 W1_H02E0601\narc: C7 E1_H01E0101\narc: CLK1 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 V00T0100\narc: D3 V00T0100\narc: D4 V02N0401\narc: D5 S1_V02N0601\narc: D6 E1_H02W0201\narc: D7 V00B0000\narc: E1_H01E0101 Q6\narc: E1_H02E0501 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q6\narc: LSR1 H02E0301\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXCLK3 CLK1\narc: N1_V01N0001 Q6\narc: N1_V02N0401 Q6\narc: N3_V06N0303 Q6\narc: S1_V02S0001 Q0\narc: S1_V02S0201 Q2\narc: S1_V02S0601 Q6\narc: S3_V06S0303 Q6\narc: V01S0000 Q3\narc: V01S0100 Q1\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 1111110000001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R28C47:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 V02S0301\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0303 N3_V06S0303\narc: H00L0000 V02S0001\narc: H00L0100 H02E0301\narc: H00R0100 V02S0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 H02W0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V01S0000\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N3_V06S0203\narc: V00B0100 H02E0701\narc: V00T0000 V02S0601\narc: V00T0100 V02S0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 H01E0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 V02S0701\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: S1_V02S0301 W3_H06E0003\narc: W3_H06W0003 N1_V01S0000\narc: W3_H06W0203 N1_V01S0000\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A0 S1_V02N0501\narc: A1 S1_V02N0501\narc: A2 S1_V02N0501\narc: A3 S1_V02N0501\narc: A4 W1_H02E0501\narc: A5 S1_V02N0301\narc: A6 E1_H02W0701\narc: B0 V02N0101\narc: B1 V02N0101\narc: B2 V02N0101\narc: B3 V02N0101\narc: B4 H02W0301\narc: B5 H00L0000\narc: B6 E1_H02W0301\narc: B7 V00B0000\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V00T0100\narc: C5 V02N0001\narc: C6 S1_V02N0201\narc: C7 E1_H02W0401\narc: CLK1 G_HPBX0000\narc: D0 V00B0100\narc: D1 V00B0100\narc: D2 V00B0100\narc: D3 V00B0100\narc: D4 V02N0401\narc: D5 S1_V02N0601\narc: D6 V02S0401\narc: D7 H00R0100\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q2\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F6\narc: LSR1 V00T0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0101 F7\narc: N3_V06N0303 F6\narc: S3_V06S0003 Q3\narc: S3_V06S0303 F6\narc: V00B0000 F6\narc: V01S0000 Q1\nword: SLICED.K0.INIT 0101010000010000\nword: SLICED.K1.INIT 0011001100001111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R28C48:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0103 N1_V01S0100\narc: H00L0100 H02E0301\narc: H00R0000 W1_H02E0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 H06E0203\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 H01E0101\narc: V00B0000 H02W0601\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02S0601\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 S1_V02N0701\narc: E3_H06E0003 W3_H06E0003\narc: A1 N1_V02S0701\narc: A3 H02W0501\narc: A5 V00T0000\narc: B0 V02S0301\narc: B1 H01W0100\narc: B3 H00R0100\narc: B5 V00B0100\narc: B7 V00B0000\narc: C0 E1_H02W0401\narc: C1 E1_H01W0000\narc: C3 N1_V01N0001\narc: C5 W1_H02E0401\narc: C7 E1_H02W0401\narc: D0 W1_H02E0201\narc: D1 H00R0000\narc: D3 F0\narc: D5 H00L0100\narc: D7 H02E0201\narc: E1_H01E0001 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: M2 V00T0100\narc: N1_V01N0001 F5\narc: V00T0100 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0011111111000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000010000100001\nword: SLICEA.K0.INIT 0011111111000000\nword: SLICEA.K1.INIT 0010000000010000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000010010000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R28C49:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 V01N0101\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0701 H06E0203\narc: N3_V06N0103 V01N0101\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 S1_V02N0001\narc: V00T0000 V02N0601\narc: V00T0100 H02W0101\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 S1_V02N0701\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0003 V01N0001\narc: A5 E1_H02W0701\narc: B5 W1_H02E0101\narc: B6 V02N0501\narc: C5 V02N0201\narc: C6 V02N0001\narc: CE0 E1_H02W0101\narc: CE1 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D5 H02E0001\narc: D6 V01N0001\narc: D7 H02W0001\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q2\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F5\narc: M0 V00T0100\narc: M2 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0101 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000001001000001\nword: SLICED.K0.INIT 0000001111001111\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R28C4:PLC2\narc: E1_H02E0601 E3_H06W0303\narc: H00R0100 H02W0701\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 E1_H02W0401\narc: S1_V02S0101 V01N0101\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 H01E0101\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02N0101\narc: V00T0100 E1_H02W0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 S1_V02N0701\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: H01W0000 Q0\narc: H01W0100 Q0\narc: M0 V00B0100\narc: M2 H02W0601\narc: M4 V00T0100\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q2\narc: S1_V02S0401 Q6\narc: S1_V02S0601 Q4\narc: S3_V06S0003 Q0\narc: S3_V06S0103 Q2\narc: V01S0000 Q2\narc: V01S0100 Q6\narc: W1_H02W0001 Q2\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R28C50:PLC2\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 N1_V02S0501\narc: H00L0000 V02N0201\narc: H00L0100 N1_V02S0101\narc: H00R0000 S1_V02N0601\narc: H00R0100 W1_H02E0501\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02E0601\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 H02W0101\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 H06E0303\narc: V00B0100 N1_V02S0301\narc: V00T0100 V02N0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0301 W3_H06E0003\narc: A3 S1_V02N0701\narc: B0 E1_H02W0101\narc: B1 V00T0000\narc: B2 V02S0101\narc: B3 H00R0100\narc: B4 E1_H02W0301\narc: B5 V02S0501\narc: B6 H02E0101\narc: C0 N1_V01S0100\narc: C1 H00L0000\narc: C2 H02E0401\narc: C3 E1_H02W0401\narc: C4 H02W0601\narc: C5 V02N0201\narc: C6 E1_H01E0101\narc: CE0 H00L0100\narc: CE1 H00R0000\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 H02E0001\narc: D2 V00T0100\narc: D3 H02W0001\narc: D4 V02N0601\narc: D5 H02E0001\narc: D6 H02E0201\narc: D7 F2\narc: E1_H01E0001 F4\narc: E1_H01E0101 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F5\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F6\narc: N1_V01N0101 Q4\narc: S3_V06S0003 F0\narc: V00T0000 Q0\narc: V01S0000 F1\narc: W1_H02W0001 F2\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q4\nword: SLICEB.K0.INIT 1100110000001111\nword: SLICEB.K1.INIT 0000000010101100\nword: SLICEC.K0.INIT 1100110000001111\nword: SLICEC.K1.INIT 0000111100001100\nword: SLICEA.K0.INIT 1100110000001111\nword: SLICEA.K1.INIT 0000111100001100\nword: SLICED.K0.INIT 1111110011110000\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R28C51:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 V06N0203\narc: E1_H02E0501 N1_V01S0100\narc: H00L0100 V02S0301\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 H02W0001\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V01S0100\narc: V00B0100 N1_V02S0301\narc: V00T0100 E1_H02W0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V02S0601\narc: N3_V06N0003 W3_H06E0003\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0303 W3_H06E0203\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: E1_H02E0601 Q6\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: M0 H02W0601\narc: M2 V00T0100\narc: M4 H02E0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R28C52:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 E1_H01W0000\narc: N1_V02N0401 H02E0401\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 H02E0501\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0201\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 N3_V06S0303\narc: H01W0000 W3_H06E0103\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: E1_H02E0201 Q2\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0201 Q0\narc: S3_V06S0203 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R28C53:PLC2\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 H01E0101\narc: E1_H02E0701 W1_H02E0601\narc: H00R0000 H02E0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0501 N3_V06S0303\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 V01N0101\narc: S3_V06S0203 N3_V06S0103\narc: V00B0100 S1_V02N0101\narc: V00T0000 H02W0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 V02S0301\narc: H01W0000 W3_H06E0103\narc: N3_V06N0103 W3_H06E0103\narc: N3_V06N0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\narc: B0 V00B0000\narc: B1 V00B0000\narc: C0 N1_V01S0100\narc: C1 N1_V01S0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: E1_H02E0601 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0001 Q2\narc: S3_V06S0103 F1\narc: V00B0000 Q6\narc: V01S0000 Q2\narc: V01S0100 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1100001100111100\nword: SLICEA.K1.INIT 1111110011000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R28C54:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0103 N1_V01S0100\narc: H00L0000 V02S0001\narc: H00R0100 H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 H06E0203\narc: V00B0100 H02E0701\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02S0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0601 N3_V06S0303\narc: E3_H06E0003 W3_H06E0003\narc: B0 H01W0100\narc: B1 H01W0100\narc: B2 E1_H01W0100\narc: B3 E1_H01W0100\narc: B4 E1_H02W0301\narc: B5 E1_H02W0301\narc: C0 H02E0601\narc: C1 H02E0601\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 V00T0100\narc: C5 V00T0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 V00B0100\narc: D2 V02N0201\narc: D3 V02N0201\narc: D4 V02N0401\narc: D5 V02N0401\narc: E1_H01E0101 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: M6 V00T0000\narc: MUXCLK3 CLK0\narc: S3_V06S0103 F1\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V01S0000 F3\narc: V01S0100 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100001100111100\nword: SLICEB.K1.INIT 1111110011000000\nword: SLICEC.K0.INIT 1100001100111100\nword: SLICEC.K1.INIT 1111110011000000\nword: SLICEA.K0.INIT 1100001100111100\nword: SLICEA.K1.INIT 1111110011000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R28C55:PLC2\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 V02S0601\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 H02E0001\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0601 H02E0601\narc: S1_V02S0001 V01N0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 V01N0101\narc: S3_V06S0103 H01E0101\narc: V00B0000 V02S0001\narc: V00B0100 V02N0101\narc: V00T0000 V02S0401\narc: V01S0100 N3_V06S0303\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q0\narc: H01W0100 Q2\narc: M0 V00B0100\narc: M2 V00B0000\narc: M4 H02W0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0203 Q4\narc: S3_V06S0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R28C56:PLC2\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 H02W0001\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0201 S1_V02N0701\narc: N3_V06N0203 H06W0203\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 V02S0201\narc: V00B0100 H02E0501\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 N1_V02S0401\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: M0 V00B0000\narc: M2 H02E0601\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0001 Q0\narc: S1_V02S0601 Q4\narc: V01S0000 Q2\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R28C57:PLC2\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 E1_H01W0100\narc: H00L0000 V02S0001\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 H06E0103\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V01S0100\narc: V00B0000 N1_V02S0201\narc: V00B0100 E1_H02W0701\narc: V00T0100 E1_H02W0101\narc: W1_H02W0001 V02S0001\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: M0 E1_H02W0601\narc: M2 V00T0100\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0001 Q0\narc: S1_V02S0201 Q2\narc: S3_V06S0303 Q6\narc: V01S0000 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C58:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0701 W1_H02E0601\narc: H00L0000 H02W0201\narc: H00L0100 H02W0301\narc: H00R0000 H02W0401\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H06E0303\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: V00T0000 H02W0201\narc: V00T0100 H02E0301\narc: A1 H00L0100\narc: A5 V00T0000\narc: B1 E1_H01W0100\narc: B5 V01S0000\narc: C1 E1_H01W0000\narc: C3 H00L0000\narc: C5 V00T0100\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D3 F0\narc: D5 H02W0001\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: H01W0000 Q6\narc: H01W0100 F4\narc: M0 E1_H02W0601\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: N3_V06N0003 F3\narc: V01S0000 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 1111111110000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R28C59:PLC2\narc: V00B0000 V02S0001\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V06S0203\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A0 H02E0701\narc: A2 V00B0000\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 H02E0101\narc: B6 V01S0000\narc: B7 V00B0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: H01W0100 Q5\narc: LSR0 W1_H02E0501\narc: LSR1 W1_H02E0501\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: V00B0100 Q7\narc: V01S0000 Q6\narc: W1_H02W0201 Q2\narc: W1_H02W0301 Q3\narc: W1_H02W0401 Q6\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C5:PLC2\narc: H00L0100 V02S0301\narc: H00R0000 H02E0601\narc: H00R0100 V02N0501\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 H06E0203\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0203 H06W0203\narc: V00B0000 V02N0001\narc: V00T0000 V02N0601\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 E1_H01W0100\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E1_H01W0000\narc: A7 N1_V01S0100\narc: B7 V02N0701\narc: C7 V01N0101\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: E3_H06E0003 Q3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H00L0100\narc: M2 V00T0000\narc: M3 H00R0100\narc: M4 V00T0000\narc: M5 H00L0100\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: N3_V06N0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111111111111111\nword: SLICED.K1.INIT 1110101011000000\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 1111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R28C60:PLC2\narc: W1_H02W0601 H01E0001\narc: E3_H06E0003 W3_H06E0003\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R28C65:PLC2\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\n\n.tile R28C66:PLC2\narc: E3_H06E0103 W3_H06E0003\n\n.tile R28C69:PLC2\narc: E1_H02E0101 V06S0103\narc: S3_V06S0103 H06E0103\n\n.tile R28C6:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0701 V02S0701\narc: H00L0000 S1_V02N0001\narc: H00L0100 V02N0301\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0601 H06W0303\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 V02S0201\narc: V00B0100 V02N0301\narc: V00T0000 H02W0201\narc: V00T0100 V02S0701\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0103 N3_V06S0103\narc: A3 V02S0701\narc: A7 V00T0100\narc: B3 H02W0301\narc: B7 H02W0301\narc: C3 H00L0000\narc: C7 S1_V02N0001\narc: CE0 V02N0201\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D3 V02S0201\narc: D7 H00L0100\narc: E1_H01E0101 F2\narc: E1_H02E0001 F2\narc: E1_H02E0201 F2\narc: E1_H02E0401 F6\narc: E3_H06E0103 F2\narc: E3_H06E0303 F6\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: H01W0100 F2\narc: M0 H02W0601\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F6\narc: N1_V01N0101 F6\narc: N1_V02N0001 F2\narc: N1_V02N0201 F2\narc: N3_V06N0103 F2\narc: N3_V06N0303 F6\narc: S1_V02S0201 Q0\narc: S3_V06S0303 F6\narc: V01S0000 F6\narc: V01S0100 Q4\narc: W1_H02W0401 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0010000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R28C70:PLC2\narc: E1_H02E0201 N1_V01S0000\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\n\n.tile R28C7:PLC2\narc: H00L0000 H02E0001\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 H01E0101\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0601 E3_H06W0303\narc: V00B0000 V02N0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02S0401\narc: V00T0100 H02E0301\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0601 V02S0601\narc: W3_H06W0103 E3_H06W0103\narc: A5 H02E0701\narc: B5 V00B0100\narc: C5 S1_V02N0001\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D5 E1_H02W0001\narc: E1_H01E0001 F4\narc: E3_H06E0203 F4\narc: F4 F5C_SLICE\narc: H00R0000 F4\narc: H01W0000 F4\narc: H01W0100 F4\narc: M0 E1_H02W0601\narc: M2 V00B0000\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V02N0601 F4\narc: N3_V06N0103 Q2\narc: N3_V06N0203 F4\narc: S1_V02S0001 Q0\narc: S1_V02S0401 F4\narc: S3_V06S0103 Q2\narc: S3_V06S0203 F4\narc: V01S0100 F4\narc: W3_H06W0203 F4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000001000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R28C8:PLC2\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 V02S0401\narc: H00L0000 W1_H02E0201\narc: H00R0000 W1_H02E0401\narc: H00R0100 V02N0701\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 H01E0001\narc: N3_V06N0003 H06E0003\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H01E0001\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02W0601\narc: V00T0000 E1_H02W0201\narc: V00T0100 E1_H02W0301\narc: W1_H02W0201 N3_V06S0103\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0203\narc: CE0 H00R0000\narc: CE1 H00L0000\narc: CE2 H00R0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H02E0001 Q2\narc: H01W0000 Q0\narc: H01W0100 Q6\narc: M0 V00T0000\narc: M2 V00T0100\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0003 Q0\narc: V01S0000 Q6\narc: V01S0100 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R28C9:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02N0601\narc: H00L0000 E1_H02W0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 H06E0303\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 H06E0103\narc: S3_V06S0303 H06E0303\narc: V00B0000 H02W0401\narc: V00B0100 V02S0301\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0303 E1_H01W0100\narc: A1 E1_H01E0001\narc: A2 E1_H01E0001\narc: B1 H01W0100\narc: B2 H00R0000\narc: C1 H00L0000\narc: C2 H00L0000\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D2 V02N0001\narc: E1_H01E0001 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H00R0000 Q4\narc: H01W0100 Q4\narc: M0 V00B0000\narc: M1 H02E0001\narc: M2 V00B0000\narc: M4 H02E0401\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0000 F1\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100010000110001\nword: SLICEB.K0.INIT 1100010000110001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R29C10:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 V02S0701\narc: H00L0000 V02S0001\narc: H00L0100 V02S0101\narc: H00R0000 V02N0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H06W0203\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 V02S0201\narc: V00T0100 V02N0501\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: A1 H02E0501\narc: A2 H02E0501\narc: B1 H02E0101\narc: B2 H02E0101\narc: C1 H00L0000\narc: C2 H00L0000\narc: CE2 N1_V02S0601\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: E1_H02E0401 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 Q6\narc: M0 H02W0601\narc: M1 H00R0100\narc: M2 H02W0601\narc: M4 V00B0000\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W1_H02W0101 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000101011001111\nword: SLICEB.K0.INIT 1000101011001111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R29C11:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 V01N0001\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: H00L0100 N1_V02S0101\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 H06W0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V02S0601\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02N0101\narc: V00T0000 V02S0601\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0601 H01E0001\narc: N1_V02N0201 W3_H06E0103\narc: N3_V06N0103 W3_H06E0103\narc: A2 H02E0701\narc: A3 H02E0701\narc: A4 N1_V01N0101\narc: B2 N1_V02S0301\narc: B3 N1_V02S0301\narc: B4 H02E0101\narc: B5 H00R0000\narc: C2 V02N0401\narc: C3 V02N0401\narc: C4 V02S0201\narc: C5 V00T0000\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D2 V01S0100\narc: D3 V01S0100\narc: D4 H00L0100\narc: D5 V02S0401\narc: D7 V02S0401\narc: E1_H02E0201 F2\narc: E1_H02E0501 F5\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: LSR1 V00B0000\narc: M2 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q4\narc: V01S0100 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEC.K0.INIT 1111111100101010\nword: SLICEC.K1.INIT 1100000011001100\nword: SLICEB.K0.INIT 0000000000110001\nword: SLICEB.K1.INIT 0000000011000100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R29C12:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0003 N1_V01S0000\narc: H00L0000 E1_H02W0001\narc: H00L0100 H02W0301\narc: H00R0000 N1_V02S0401\narc: H00R0100 V02S0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0501 N3_V06S0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00B0100 H02E0501\narc: V00T0000 N1_V02S0601\narc: V00T0100 E1_H02W0301\narc: V01S0000 N3_V06S0103\narc: N3_V06N0003 W3_H06E0003\narc: A1 V01N0101\narc: A3 H00L0100\narc: A4 V00T0100\narc: A5 N1_V01N0101\narc: A6 E1_H02W0501\narc: A7 H02E0701\narc: B1 V02S0101\narc: B3 V02N0301\narc: B4 H02W0101\narc: B5 H00R0000\narc: B6 H02W0101\narc: B7 H02E0301\narc: C1 H00L0000\narc: C3 N1_V01N0001\narc: C4 E1_H01E0101\narc: C5 H02E0401\narc: C6 H02W0401\narc: C7 V00B0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D3 H02W0001\narc: D4 V02N0401\narc: D5 E1_H01W0100\narc: D6 V01N0001\narc: D7 H02E0201\narc: E1_H01E0101 F2\narc: E1_H02E0701 F7\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q6\narc: LSR1 V00B0000\narc: M2 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q4\narc: N3_V06N0303 F5\narc: S3_V06S0303 Q6\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000100000\nword: SLICEC.K0.INIT 1011000010111011\nword: SLICEC.K1.INIT 1001000000000000\nword: SLICED.K0.INIT 1011101110001011\nword: SLICED.K1.INIT 1001000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111011101110011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R29C13:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 W1_H02E0601\narc: H00L0000 V02N0201\narc: H00R0000 V02N0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0701 V01N0101\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 H02W0601\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0601\narc: V00B0100 H02E0701\narc: V00T0000 H02E0201\narc: V00T0100 V02N0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 E1_H01W0000\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: A0 E1_H02W0701\narc: A1 E1_H01E0001\narc: A2 H02W0701\narc: A3 V02S0701\narc: A4 V02N0101\narc: A5 N1_V01N0101\narc: A7 V02S0301\narc: B0 H00R0100\narc: B1 V02S0101\narc: B2 F1\narc: B3 S1_V02N0301\narc: B4 V02S0501\narc: B5 H02E0101\narc: B7 V02S0701\narc: C0 E1_H02W0601\narc: C1 H02E0401\narc: C2 N1_V01N0001\narc: C3 H00L0000\narc: C4 V00T0100\narc: C5 V02N0001\narc: C7 S1_V02N0201\narc: CE0 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 N1_V01S0000\narc: D1 H00R0000\narc: D2 V00B0100\narc: D3 H02W0201\narc: D4 V02N0601\narc: D5 V00B0000\narc: D7 V02N0401\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F3\narc: E3_H06E0003 Q0\narc: E3_H06E0203 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F2\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q4\narc: N3_V06N0203 Q4\narc: W1_H02W0501 F5\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010001011110011\nword: SLICEA.K0.INIT 1011101110001011\nword: SLICEA.K1.INIT 1010010100100001\nword: SLICEC.K0.INIT 1011101110001011\nword: SLICEC.K1.INIT 1001000000001001\nword: SLICEB.K0.INIT 1000000000000000\nword: SLICEB.K1.INIT 1000101011001111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R29C14:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: H00R0000 H02W0401\narc: H00R0100 H02W0501\narc: H01W0000 E3_H06W0103\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H02W0301\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 V01N0101\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 H06W0103\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02W0401\narc: V00B0100 V02N0101\narc: V00T0000 H02W0201\narc: V00T0100 H02W0301\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 H01E0101\narc: W3_H06W0203 E3_H06W0203\narc: A1 V02N0701\narc: B1 V02S0301\narc: B2 H00L0000\narc: B4 H02E0101\narc: B6 V01S0000\narc: C1 H02E0401\narc: C2 E1_H02W0601\narc: C4 E1_H02W0601\narc: C6 H02E0601\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 H02W0001\narc: D3 H00R0000\narc: D4 H00R0100\narc: D5 V00B0000\narc: D6 H02W0001\narc: D7 N1_V02S0401\narc: E1_H01E0101 Q4\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q2\narc: H01W0100 Q4\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: N1_V02N0401 Q4\narc: S1_V02S0301 F1\narc: V01S0000 Q6\narc: V01S0100 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R29C15:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 E1_H02W0001\narc: H00L0100 H02W0301\narc: H00R0000 H02E0601\narc: H00R0100 V02N0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H06W0003\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 V01N0001\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 H06W0103\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 E1_H02W0601\narc: V00B0100 H02W0701\narc: V00T0000 S1_V02N0601\narc: V00T0100 H02E0101\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 E3_H06W0203\narc: A1 V02S0501\narc: A7 H02E0701\narc: B1 S1_V02N0101\narc: B6 V00T0000\narc: B7 V00B0000\narc: C1 H00L0000\narc: C6 E1_H01E0101\narc: C7 H02E0401\narc: CE1 V02N0201\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D6 H00R0100\narc: D7 H02W0201\narc: E1_H01E0101 F7\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q4\narc: M2 V00B0100\narc: M4 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q2\narc: N1_V02N0401 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000100000\nword: SLICED.K0.INIT 0011000011110000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R29C16:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 H02E0201\narc: H00L0100 H02W0101\narc: H00R0000 H02W0401\narc: H00R0100 H02W0701\narc: H01W0000 E3_H06W0103\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 S1_V02N0101\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0100 V02N0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0103 E3_H06W0003\narc: A0 E1_H02W0701\narc: A1 E1_H01E0001\narc: A6 E1_H02W0501\narc: B0 H00R0100\narc: B1 E1_H02W0301\narc: B6 V00T0000\narc: C0 H00L0100\narc: C1 H00L0000\narc: C5 E1_H02W0401\narc: C6 H02E0601\narc: CE0 H00R0000\narc: CE1 V02N0201\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 V02N0001\narc: D5 H00R0100\narc: D6 V02N0401\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q2\narc: E3_H06E0003 Q0\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M2 V00B0100\narc: M6 N1_V01N0101\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0101 F5\narc: N3_V06N0003 Q0\narc: N3_V06N0303 Q6\narc: W1_H02W0101 F1\narc: W3_H06W0003 Q0\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICEA.K0.INIT 1011101100001011\nword: SLICEA.K1.INIT 1011000010111011\nword: SLICED.K0.INIT 1111111110001111\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R29C17:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 E1_H01W0100\narc: E3_H06E0003 H01E0001\narc: H00L0100 V02N0101\narc: H00R0000 E1_H02W0401\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H01E0101\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00B0100 H02E0501\narc: V00T0000 W1_H02E0001\narc: V00T0100 S1_V02N0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0701 V02S0701\narc: W3_H06W0003 N3_V06S0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: A4 V00T0000\narc: A5 H02E0701\narc: A6 E1_H02W0501\narc: A7 N1_V01N0101\narc: B4 V00B0100\narc: B5 H02W0101\narc: B6 V00B0100\narc: B7 H02W0101\narc: C4 V00T0100\narc: C5 H02E0401\narc: C6 V00T0100\narc: C7 H02W0601\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 H00R0100\narc: D5 H00L0100\narc: D6 H01W0000\narc: D7 E1_H02W0201\narc: E1_H01E0101 Q2\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0000 F7\narc: H01W0100 Q4\narc: M2 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q6\narc: N1_V02N0201 Q2\narc: W1_H02W0601 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111110000000\nword: SLICEC.K1.INIT 0000000011001010\nword: SLICED.K0.INIT 1111111110000000\nword: SLICED.K1.INIT 0000000011001010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R29C18:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 H02W0001\narc: H00L0100 V02N0301\narc: H00R0100 V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 H01E0101\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 H06W0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 E1_H02W0201\narc: V00T0100 W1_H02E0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0303 E1_H02W0601\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: B4 H00R0000\narc: B6 V01S0000\narc: C4 V00B0100\narc: C6 V00B0100\narc: CE0 E1_H02W0101\narc: CE1 H00L0000\narc: CLK0 G_HPBX0000\narc: D4 H00L0100\narc: D5 H02E0201\narc: D6 H00R0100\narc: D7 H02E0201\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 Q4\narc: H01W0100 Q6\narc: M0 V00T0000\narc: M2 V00B0000\narc: M4 E1_H02W0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: S1_V02S0201 Q2\narc: S1_V02S0401 Q4\narc: V01S0000 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R29C19:PLC2\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 V02S0301\narc: H00L0000 V02N0201\narc: H00R0000 E1_H02W0601\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0201\narc: V00B0100 E1_H02W0701\narc: V00T0000 E1_H02W0201\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 E1_H01W0100\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0103\narc: A0 H00L0000\narc: A2 E1_H02W0501\narc: B2 H02W0301\narc: B3 E1_H02W0301\narc: B4 V00B0100\narc: B5 H00R0000\narc: B6 V00T0000\narc: B7 V00B0000\narc: E3_H06E0003 F3\narc: E3_H06E0103 F2\narc: E3_H06E0303 F5\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V02N0401 F6\narc: N1_V02N0701 F7\narc: N3_V06N0203 F4\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R29C20:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 V06N0303\narc: E3_H06E0003 V01N0001\narc: E3_H06E0303 V06N0303\narc: H00R0000 H02E0601\narc: H00R0100 V02N0501\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 V01N0101\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 V02S0201\narc: V00B0100 W1_H02E0701\narc: V00T0000 N1_V02S0401\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0701 E1_H01W0100\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0303 E1_H02W0501\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: B0 V00B0000\narc: B1 V00T0000\narc: B2 E1_H02W0301\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 H00R0000\narc: B6 S1_V02N0701\narc: B7 V02S0701\narc: E1_H01E0001 F3\narc: E1_H01E0101 F6\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: N1_V01N0101 F5\narc: N1_V02N0301 F1\narc: V01S0000 F0\narc: W1_H02W0601 F4\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R29C21:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0601 V06N0303\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0103 H01E0101\narc: E3_H06E0303 W1_H02E0601\narc: H00R0000 H02W0601\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 H02E0601\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 E3_H06W0303\narc: S3_V06S0103 H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0401\narc: V00T0000 W1_H02E0001\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V02N0701\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0303\narc: B0 E1_H02W0101\narc: B1 E1_H02W0301\narc: B2 H00R0100\narc: B3 S1_V02N0301\narc: B4 H00R0000\narc: B5 W1_H02E0301\narc: B6 V00B0000\narc: B7 V00T0000\narc: E1_H02E0301 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: H01W0100 F1\narc: N1_V01N0001 F5\narc: S1_V02S0001 F0\narc: V01S0000 F4\narc: W3_H06W0103 F2\narc: W3_H06W0203 F7\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R29C22:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V02S0001\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 V02N0601\narc: H00R0100 V02S0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0103 S1_V02N0201\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0601\narc: V00B0100 W1_H02E0501\narc: V00T0000 W1_H02E0001\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 N3_V06S0003\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0303 E3_H06W0203\narc: B0 V00B0000\narc: B1 H02E0101\narc: B2 H00R0100\narc: B3 S1_V02N0301\narc: B4 W1_H02E0301\narc: B5 V00B0100\narc: B6 V02N0701\narc: B7 V00T0000\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: S1_V02S0401 F6\narc: V01S0000 F3\narc: W1_H02W0201 F0\narc: W1_H02W0501 F5\narc: W1_H02W0701 F7\narc: W3_H06W0103 F2\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R29C23:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 E3_H06W0303\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0103 V06N0103\narc: E3_H06E0203 V01N0001\narc: E3_H06E0303 N3_V06S0303\narc: H00L0100 N1_V02S0101\narc: H00R0000 H02W0601\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 H02W0101\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0103 E1_H01W0100\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02E0601\narc: V00B0100 N1_V02S0101\narc: V00T0000 S1_V02N0601\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 V06S0203\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0103 E1_H02W0101\narc: W3_H06W0003 E3_H06W0003\narc: A3 V00T0000\narc: A4 E1_H02W0701\narc: B3 V02S0101\narc: B4 N1_V01S0000\narc: B6 V01S0000\narc: C2 V02S0401\narc: C3 H00L0100\narc: C4 E1_H01E0101\narc: C6 H02W0401\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 H00R0000\narc: D4 H02E0001\narc: D6 V00B0000\narc: D7 H02W0201\narc: E1_H01E0101 F3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F2\narc: M4 H02E0401\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: N1_V02N0601 Q6\narc: V01S0000 Q6\narc: W3_H06W0203 F4\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0000001000000000\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R29C24:PLC2\narc: E1_H02E0201 V01N0001\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0103 V06S0103\narc: E3_H06E0203 N3_V06S0203\narc: H00L0100 V02S0301\narc: H00R0000 N1_V02S0401\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 N3_V06S0203\narc: N3_V06N0003 S1_V02N0001\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 V02N0101\narc: V00T0000 V02S0601\narc: V00T0100 S1_V02N0701\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0301 W3_H06E0003\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0303 V01N0101\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0103\narc: A4 V00T0000\narc: A5 V00B0000\narc: B0 F1\narc: B2 H02E0301\narc: B3 V02S0101\narc: B4 H00R0000\narc: B5 V02S0701\narc: B6 E1_H02W0101\narc: C0 V02N0401\narc: C1 H00L0100\narc: C2 N1_V01N0001\narc: C3 H02W0401\narc: C4 V00T0100\narc: C5 V00B0100\narc: C6 H02W0601\narc: C7 S1_V02N0201\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 H02W0201\narc: D2 V02S0201\narc: D3 V02N0201\narc: D4 H00R0100\narc: D5 V02N0601\narc: D6 H02W0001\narc: D7 H01W0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: E1_H02E0401 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0000 F6\narc: H01W0100 F0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F3\narc: N1_V01N0101 Q4\narc: N1_V02N0601 F6\narc: N3_V06N0103 F2\narc: V00B0000 Q4\nword: SLICEC.K0.INIT 1111111110000000\nword: SLICEC.K1.INIT 0000000011001010\nword: SLICEA.K0.INIT 1100000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0011111100000000\nword: SLICEB.K1.INIT 1100000000000000\nword: SLICED.K0.INIT 1100000000000000\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R29C25:PLC2\narc: E1_H02E0101 V01N0101\narc: H00L0000 H02W0001\narc: H00R0000 H02W0401\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H06W0103\narc: N1_V02N0301 H06W0003\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H02E0701\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00B0100 W1_H02E0501\narc: V00T0000 N1_V02S0601\narc: V00T0100 E1_H02W0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 H01E0001\narc: W1_H02W0701 V02S0701\narc: N1_V02N0201 W3_H06E0103\narc: N3_V06N0003 W3_H06E0003\narc: N3_V06N0303 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: A0 H00L0000\narc: A1 E1_H02W0501\narc: A2 S1_V02N0501\narc: A3 E1_H02W0501\narc: A4 V02S0301\narc: A6 V02S0101\narc: A7 H00R0000\narc: B0 V00T0000\narc: B1 H02W0101\narc: B2 S1_V02N0301\narc: B3 H02W0101\narc: B4 E1_H02W0301\narc: B6 V00B0100\narc: B7 V01S0000\narc: C0 H00L0100\narc: C1 S1_V02N0601\narc: C2 H02W0601\narc: C3 S1_V02N0601\narc: C4 V00T0100\narc: C5 H02W0401\narc: C6 V01N0101\narc: C7 E1_H02W0401\narc: D0 S1_V02N0201\narc: D1 E1_H02W0001\narc: D2 W1_H02E0001\narc: D3 E1_H02W0001\narc: D4 V02N0601\narc: D5 H01W0000\narc: D6 V00B0000\narc: D7 E1_H01W0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 F3\narc: E1_H02E0001 F0\narc: E1_H02E0301 F1\narc: E1_H02E0501 F7\narc: E1_H02E0601 F4\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0000 F4\narc: H01W0100 F3\narc: N1_V01N0001 F5\narc: N1_V01N0101 F1\narc: N1_V02N0401 F4\narc: N3_V06N0103 F1\narc: N3_V06N0203 F7\narc: S1_V02S0001 F2\narc: S1_V02S0401 F6\narc: S1_V02S0701 F5\narc: S3_V06S0103 F1\narc: V01S0000 F4\narc: V01S0100 F7\narc: W1_H02W0101 F1\narc: W1_H02W0501 F5\narc: W1_H02W0601 F4\nword: SLICEB.K0.INIT 0001001101011111\nword: SLICEB.K1.INIT 0100000000000000\nword: SLICED.K0.INIT 0001010100111111\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0001010100111111\nword: SLICEA.K1.INIT 0100000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R29C26:PLC2\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 V01N0001\narc: H00L0000 E1_H02W0201\narc: H00L0100 H02E0101\narc: H00R0000 V02S0401\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 H06E0103\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 H01E0001\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 H06E0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0501\narc: V00T0000 E1_H02W0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 N3_V06S0203\narc: E1_H02E0601 W3_H06E0303\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A0 V02N0701\narc: A1 V02S0701\narc: A3 V00T0000\narc: A5 E1_H02W0501\narc: A6 V02S0301\narc: A7 V00T0100\narc: B0 V02N0101\narc: B1 E1_H01W0100\narc: B3 H00R0000\narc: B4 V02S0501\narc: B5 E1_H02W0101\narc: B6 V00B0000\narc: B7 S1_V02N0501\narc: C0 N1_V01N0001\narc: C1 E1_H02W0601\narc: C3 H00L0000\narc: C4 E1_H01E0101\narc: C5 H02E0601\narc: C6 H01E0001\narc: C7 V00B0100\narc: D0 V02N0001\narc: D1 V01S0100\narc: D3 H02W0201\narc: D4 H02E0001\narc: D5 H01W0000\narc: D6 H00R0100\narc: D7 H00L0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 F5\narc: E1_H02E0701 F5\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0000 F3\narc: H01W0100 F3\narc: N1_V01N0001 F1\narc: N1_V01N0101 F5\narc: N1_V02N0101 F1\narc: N3_V06N0203 F4\narc: N3_V06N0303 F5\narc: S1_V02S0301 F1\narc: S1_V02S0501 F5\narc: V00T0100 F1\narc: V01S0000 F0\narc: V01S0100 F3\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000010000\nword: SLICED.K0.INIT 0000101100000000\nword: SLICED.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0001010100111111\nword: SLICEA.K1.INIT 0100000000000000\nword: SLICEC.K0.INIT 0011111100000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\n\n.tile R29C27:PLC2\narc: E1_H02E0201 V01N0001\narc: E1_H02E0701 V02N0701\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 H02W0201\narc: H00L0100 W1_H02E0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S1_V02N0201\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 H06E0203\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 E1_H02W0601\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02S0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 E1_H01W0100\narc: E1_H02E0301 W3_H06E0003\narc: W3_H06W0203 V06S0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: A1 E1_H02W0501\narc: A3 H02W0701\narc: A4 V02S0101\narc: A5 E1_H01W0000\narc: B1 V00T0000\narc: B3 H00L0000\narc: B4 V02S0701\narc: B5 F1\narc: B7 V00T0000\narc: C1 E1_H02W0401\narc: C3 V02S0401\narc: C4 V00B0100\narc: C5 V00T0100\narc: C6 V02N0201\narc: C7 E1_H02W0401\narc: D1 H00R0000\narc: D3 V02N0001\narc: D4 H00L0100\narc: D5 V01N0001\narc: D6 H00R0100\narc: D7 V00B0000\narc: E1_H01E0001 F5\narc: E1_H01E0101 F4\narc: E1_H02E0401 F6\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 F1\narc: M2 N1_V01N0001\narc: N1_V01N0001 F7\narc: N1_V01N0101 F5\narc: N1_V02N0001 F2\narc: N1_V02N0101 F1\narc: N3_V06N0303 F5\narc: S1_V02S0501 F5\narc: V00B0100 F5\narc: V01S0000 F6\narc: W1_H02W0601 F6\narc: W3_H06W0303 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000100000000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0000001100000000\nword: SLICEC.K0.INIT 0001001101011111\nword: SLICEC.K1.INIT 0100000000000000\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 0010111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R29C28:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0103 V06N0103\narc: H00L0000 H02W0201\narc: H00R0000 N1_V02S0601\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0103 H06E0103\narc: N3_V06N0303 H01E0101\narc: S1_V02S0101 H06E0103\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 V02N0301\narc: V00T0100 V02N0501\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E1_H02W0601\narc: E1_H02E0701 W3_H06E0203\narc: W3_H06W0103 E1_H02W0101\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: A3 V00B0000\narc: B3 H00L0000\narc: C3 H02W0601\narc: CE0 H00R0000\narc: CE2 N1_V02S0601\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D3 E1_H02W0201\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q6\narc: E3_H06E0003 Q0\narc: E3_H06E0303 Q6\narc: F3 F3_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q4\narc: M0 V00B0100\narc: M4 E1_H02W0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q6\narc: N3_V06N0003 Q0\narc: N3_V06N0203 Q4\narc: V00B0000 Q6\narc: V01S0000 Q0\narc: V01S0100 F3\narc: W1_H02W0001 Q0\narc: W1_H02W0301 F3\narc: W1_H02W0401 Q6\narc: W3_H06W0003 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R29C29:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0303 N3_V06S0303\narc: H00R0100 V02N0501\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H02W0301\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 H06W0303\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0501 H01E0101\narc: W1_H02W0701 E3_H06W0203\narc: N1_V02N0401 W3_H06E0203\narc: W3_H06W0003 E1_H02W0301\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: B3 H00L0000\narc: C3 N1_V01N0001\narc: CE0 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: E1_H01E0001 Q4\narc: E1_H02E0401 Q6\narc: E3_H06E0003 Q0\narc: E3_H06E0203 Q4\narc: F3 F3_SLICE\narc: H00L0000 Q0\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: H01W0100 F3\narc: M0 V00B0000\narc: M4 V00B0100\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q6\narc: V01S0000 F3\narc: W1_H02W0001 Q0\narc: W1_H02W0101 F3\narc: W1_H02W0201 Q0\narc: W1_H02W0401 Q4\narc: W1_H02W0601 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R29C2:PLC2\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 V02S0601\narc: H00R0000 V02S0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0401 N3_V06S0203\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H02W0601\narc: V00B0000 V02N0001\narc: V00T0000 H02W0001\narc: A0 E1_H02W0701\narc: A1 E1_H02W0701\narc: A6 E1_H02W0701\narc: A7 E1_H02W0701\narc: B0 E1_H02W0301\narc: B1 E1_H02W0101\narc: B6 E1_H02W0301\narc: B7 E1_H02W0101\narc: C0 E1_H02W0401\narc: C1 E1_H02W0401\narc: C6 E1_H02W0401\narc: C7 E1_H02W0401\narc: D0 V02N0001\narc: D1 V02N0001\narc: D6 V00B0000\narc: D7 V00B0000\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H02E0001\narc: M2 V00T0000\narc: M3 H00R0000\narc: M4 V00T0000\narc: M5 H02E0001\narc: M6 V00T0000\nword: SLICEA.K0.INIT 0000100000001010\nword: SLICEA.K1.INIT 1000000010100000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000100000001010\nword: SLICED.K1.INIT 1000000010100000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R29C30:PLC2\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 H02W0001\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0601\narc: V00B0100 N1_V02S0301\narc: V00T0000 H02E0001\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 E1_H02W0601\narc: N1_V02N0401 W3_H06E0203\narc: S1_V02S0301 W3_H06E0003\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: C1 N1_V01N0001\narc: CE1 H02E0101\narc: CE2 H00L0000\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: E3_H06E0303 Q6\narc: F1 F1_SLICE\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q6\narc: V01S0100 Q2\narc: W1_H02W0101 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R29C31:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 V02N0701\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0203 W1_H02E0401\narc: H00L0100 N1_V02S0101\narc: H00R0100 N1_V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 H06W0303\narc: S3_V06S0203 H06E0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0201\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02W0201\narc: V00T0100 V02S0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V06S0103\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0701 N3_V06S0203\narc: N3_V06N0103 W3_H06E0103\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0103 E1_H02W0101\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A0 V02S0501\narc: A1 E1_H02W0701\narc: A3 S1_V02N0701\narc: A4 V02S0301\narc: A5 H02E0501\narc: A6 E1_H02W0501\narc: B0 H02W0301\narc: B1 N1_V02S0101\narc: B3 H00R0100\narc: B4 H02W0301\narc: B5 N1_V02S0501\narc: B6 V00B0100\narc: C0 H00L0100\narc: C1 N1_V01N0001\narc: C3 H00L0100\narc: C4 V00B0100\narc: C5 V00B0100\narc: C6 F4\narc: D0 S1_V02N0201\narc: D1 E1_H02W0201\narc: D3 V00T0100\narc: D4 V00B0000\narc: D5 S1_V02N0601\narc: D6 H01W0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F5\narc: H01W0100 F0\narc: M6 V00T0000\narc: N1_V01N0001 F3\narc: W1_H02W0301 F1\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000001000000000\nword: SLICEC.K0.INIT 0000100000000000\nword: SLICEC.K1.INIT 0000001000000000\nword: SLICEA.K0.INIT 0000100000000000\nword: SLICEA.K1.INIT 0000000000000111\nword: SLICED.K0.INIT 0000000000000111\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R29C32:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V06N0103\narc: E1_H02E0301 V06S0003\narc: E1_H02E0601 W1_H02E0601\narc: H00L0000 N1_V02S0201\narc: H00L0100 N1_V02S0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0103 S1_V02N0201\narc: S1_V02S0001 H06W0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 H06E0303\narc: V00B0000 E1_H02W0401\narc: V00T0000 H02E0001\narc: V00T0100 H02E0101\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0601 E1_H02W0301\narc: N3_V06N0303 W3_H06E0303\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A0 E1_H02W0501\narc: A3 S1_V02N0701\narc: A4 E1_H02W0701\narc: A5 S1_V02N0101\narc: A7 V02N0301\narc: B0 H02E0101\narc: B2 H00R0100\narc: B3 H02E0101\narc: B4 V02S0501\narc: B5 H00L0000\narc: B6 S1_V02N0501\narc: B7 H02E0101\narc: C0 F4\narc: C2 S1_V02N0401\narc: C3 H02E0601\narc: C4 V00T0100\narc: C5 V00T0100\narc: C6 V00T0000\narc: C7 H02E0601\narc: D0 V02S0001\narc: D2 H00R0000\narc: D3 V02N0001\narc: D4 H02E0201\narc: D5 H00L0100\narc: D6 V00B0000\narc: D7 H00L0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 F6\narc: E3_H06E0103 F2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M0 V00B0100\narc: N1_V01N0001 F5\narc: V00B0100 F7\narc: W3_H06W0003 F0\nword: SLICEB.K0.INIT 0000111100110011\nword: SLICEB.K1.INIT 0000000000000010\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 0000000000000010\nword: SLICEC.K0.INIT 0000100000000000\nword: SLICEC.K1.INIT 0000001000000000\nword: SLICEA.K0.INIT 0000000000000111\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R29C33:PLC2\narc: E1_H02E0501 V06N0303\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 N3_V06S0203\narc: H00L0000 V02N0201\narc: H00L0100 V02S0301\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 H06E0003\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02N0201\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02N0401\narc: V00T0100 N1_V02S0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0501 V02S0501\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0301 W3_H06E0003\narc: S1_V02S0101 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A2 V02S0701\narc: A3 H00L0100\narc: A7 V00T0100\narc: B1 E1_H02W0101\narc: B2 F3\narc: B3 H02E0301\narc: B4 V02N0701\narc: B6 N1_V02S0701\narc: B7 V00B0000\narc: C1 H02E0601\narc: C2 H00R0100\narc: C3 H00L0000\narc: C4 V00B0100\narc: C6 N1_V02S0001\narc: C7 V00T0000\narc: CE0 V02S0201\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D2 V01S0100\narc: D3 W1_H02E0201\narc: D4 H02E0001\narc: D5 H02W0201\narc: D6 E1_H02W0001\narc: D7 H02E0001\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0100 Q1\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: N3_V06N0103 Q1\narc: S3_V06S0103 Q1\narc: V01S0100 F4\narc: W3_H06W0103 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 0000000100000000\nword: SLICEB.K1.INIT 0000100000000000\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 0000000000000010\nword: SLICEC.K0.INIT 1111001111111111\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R29C34:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0601 V06S0303\narc: H00R0000 V02N0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0301 H06E0003\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 H06E0203\narc: S3_V06S0203 N3_V06S0203\narc: V00B0100 V02S0301\narc: V00T0100 H02E0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 V02S0701\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0301 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: CE0 V02S0201\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: E3_H06E0303 Q6\narc: H01W0100 Q4\narc: M0 V00B0100\narc: M2 H02W0601\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: S1_V02S0401 Q6\narc: V00T0000 Q2\narc: W1_H02W0001 Q0\narc: W1_H02W0601 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R29C35:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 V06N0303\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 V06S0203\narc: H00L0100 H02W0301\narc: H00R0100 E1_H02W0701\narc: H01W0100 E3_H06W0303\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: V00B0100 H02W0501\narc: V00T0000 H02W0201\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 V06N0103\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 N1_V01S0100\narc: N1_V02N0301 W3_H06E0003\narc: S1_V02S0301 W3_H06E0003\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: CE0 H00R0100\narc: CE1 H00L0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: H01W0000 Q6\narc: M0 V00T0000\narc: M2 V00B0100\narc: M4 E1_H01E0101\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q4\narc: W1_H02W0401 Q4\narc: W3_H06W0003 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R29C36:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0103 V06S0103\narc: E3_H06E0203 N3_V06S0203\narc: E3_H06E0303 V06S0303\narc: H00L0000 H02W0201\narc: H00L0100 V02S0101\narc: H00R0000 V02N0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 V01N0001\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 V01N0101\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0303\narc: V00B0100 N1_V02S0101\narc: V00T0100 H02E0101\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 N1_V02S0501\narc: H01W0000 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0203\narc: A7 V02N0301\narc: B7 N1_V01S0000\narc: C7 N1_V02S0001\narc: CE0 H00L0100\narc: CE1 H00L0000\narc: CE2 H00L0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D6 H00R0100\narc: D7 V02S0601\narc: E1_H01E0101 Q4\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: V00B0000 Q4\narc: W1_H02W0201 Q2\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111111100000000\nword: SLICED.K1.INIT 1111110011111010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\n\n.tile R29C37:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 H01E0101\narc: E3_H06E0303 V06S0303\narc: H00L0000 V02N0001\narc: H00L0100 W1_H02E0301\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0201 H01E0001\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 W1_H02E0601\narc: V00B0100 H02E0501\narc: V00T0000 W1_H02E0201\narc: V00T0100 H02W0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0701 V06S0203\narc: E1_H01E0101 W3_H06E0203\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: B4 V00B0100\narc: C4 V00T0100\narc: CE0 H00L0000\narc: CE1 H02E0101\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D4 V02N0401\narc: D5 H00L0100\narc: E1_H01E0001 Q2\narc: E3_H06E0103 Q2\narc: F4 F5C_SLICE\narc: H01W0000 Q6\narc: M0 H02W0601\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0003 Q0\narc: V01S0000 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000000110011\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R29C38:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0301 H01E0101\narc: E1_H02E0501 V02S0501\narc: E1_H02E0701 N1_V02S0701\narc: H00L0000 W1_H02E0001\narc: H00L0100 H02W0301\narc: H00R0000 H02E0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H06W0103\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H06E0303\narc: N3_V06N0203 S1_V02N0401\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 E1_H01W0100\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N1_V02S0401\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02S0101\narc: V00T0000 H02E0001\narc: V01S0000 N3_V06S0103\narc: W1_H02W0601 H01E0001\narc: W1_H02W0101 W3_H06E0103\narc: A1 V02S0701\narc: B0 H02E0101\narc: B1 V02N0301\narc: B2 H00L0000\narc: B4 S1_V02N0701\narc: B5 S1_V02N0701\narc: B6 V00B0100\narc: B7 V00B0100\narc: C0 N1_V01N0001\narc: C1 H00R0100\narc: C2 E1_H01W0000\narc: C4 H02W0401\narc: C5 S1_V02N0201\narc: C6 H02W0401\narc: C7 S1_V02N0201\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 H02W0001\narc: D2 V02S0001\narc: D3 H00R0000\narc: D4 V02N0401\narc: D5 V00B0000\narc: D6 N1_V02S0601\narc: D7 V00B0000\narc: E3_H06E0203 F7\narc: E3_H06E0303 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M2 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N3_V06N0003 F0\narc: S1_V02S0001 F2\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1100000011001111\nword: SLICED.K1.INIT 0000000011111100\nword: SLICEA.K0.INIT 0000000011110011\nword: SLICEA.K1.INIT 1001010001001111\nword: SLICEC.K0.INIT 1100000011001111\nword: SLICEC.K1.INIT 0000000011111100\nword: SLICEB.K0.INIT 1111000000110011\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R29C39:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0701 W1_H02E0701\narc: H00L0000 H02W0001\narc: H00L0100 E1_H02W0101\narc: H00R0000 H02W0601\narc: H00R0100 H02E0701\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0003 S1_V02N0001\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N1_V02S0601\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02W0701\narc: V00T0100 V02N0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V02S0401\narc: H01W0000 W3_H06E0103\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0301 W3_H06E0003\narc: S3_V06S0203 W3_H06E0203\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: A5 V02N0301\narc: A7 E1_H02W0701\narc: B4 H00L0000\narc: B5 V00B0100\narc: B7 V00B0000\narc: C0 E1_H02W0601\narc: C1 E1_H02W0601\narc: C2 E1_H02W0601\narc: C3 E1_H02W0601\narc: C4 E1_H01E0101\narc: C5 V02N0201\narc: C7 N1_V02S0001\narc: D0 H02W0201\narc: D1 H02E0001\narc: D2 V00T0100\narc: D3 H00R0000\narc: D4 H00R0100\narc: D5 V02N0401\narc: D7 H00L0100\narc: E1_H01E0101 F5\narc: E1_H02E0501 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F0\narc: N1_V01N0001 F7\narc: N3_V06N0303 F5\narc: S1_V02S0101 F3\narc: S1_V02S0501 F5\narc: V01S0100 F2\narc: W1_H02W0101 F1\narc: W3_H06W0203 F4\narc: W3_H06W0303 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100010010000000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 0011000011110000\nword: SLICEC.K1.INIT 1000001110000000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000111111110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R29C3:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V02S0701\narc: H00L0000 H02W0201\narc: H00R0000 H02E0601\narc: H00R0100 H02W0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 H06W0303\narc: S3_V06S0103 N3_V06S0003\narc: V00T0000 V02S0601\narc: V00T0100 V02N0701\narc: W1_H02W0001 V02S0001\narc: W1_H02W0601 H01E0001\narc: A1 N1_V02S0501\narc: A2 V00T0000\narc: A5 H02W0701\narc: A6 N1_V01S0100\narc: B1 V02S0101\narc: B2 H00R0000\narc: B5 H00L0000\narc: B6 V02S0701\narc: C1 H00R0100\narc: C2 H00R0100\narc: C5 H02E0401\narc: C6 V02N0201\narc: C7 H02W0601\narc: D1 W1_H02E0001\narc: D2 W1_H02E0001\narc: D5 H01W0000\narc: D6 V02N0601\narc: D7 E1_H02W0201\narc: E1_H01E0001 F4\narc: E1_H01E0101 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M0 V00T0100\narc: M1 E1_H02W0001\narc: M2 V00T0100\narc: M4 V00B0000\narc: V00B0000 F6\nword: SLICED.K0.INIT 1000110010101111\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000110010101111\nword: SLICEB.K0.INIT 1000110010101111\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000010001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R29C40:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 V02N0001\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0103 N3_V06S0103\narc: H00L0000 H02W0201\narc: H00L0100 W1_H02E0301\narc: H00R0000 H02E0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H02W0701\narc: N3_V06N0203 V01N0001\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 E1_H02W0601\narc: V00B0100 W1_H02E0501\narc: V00T0100 V02S0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 V06S0203\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0501 W3_H06E0303\narc: H01W0000 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: A0 H02E0701\narc: B0 H02W0301\narc: B2 H00R0000\narc: B3 H02E0301\narc: C0 V02S0401\narc: C1 H00L0100\narc: C2 H00L0000\narc: C3 H02E0401\narc: C4 H02W0601\narc: C5 H02W0601\narc: C6 H02W0601\narc: C7 H02W0601\narc: D0 V02N0001\narc: D1 H02E0001\narc: D2 V00B0100\narc: D3 H02W0201\narc: D4 V00B0000\narc: D5 E1_H02W0201\narc: D6 V02S0601\narc: D7 V02N0401\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M2 V00T0100\narc: N1_V01N0001 F1\narc: N1_V01N0101 F0\narc: N1_V02N0201 F2\narc: N3_V06N0103 F2\narc: S1_V02S0401 F6\narc: S1_V02S0601 F4\narc: S1_V02S0701 F7\narc: S3_V06S0103 F2\narc: V01S0100 F5\nword: SLICEA.K0.INIT 1110001010101010\nword: SLICEA.K1.INIT 0000000011110000\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 1111001111000000\nword: SLICEB.K1.INIT 1100111111000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R29C41:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V02S0601\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 N1_V02S0001\narc: H00L0100 V02S0301\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 V01N0001\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 E1_H01W0000\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 N1_V02S0001\narc: V00T0000 V02N0401\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 S1_V02N0701\narc: N1_V02N0601 W3_H06E0303\narc: N3_V06N0103 W3_H06E0103\narc: S3_V06S0003 W3_H06E0003\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 N1_V01S0000\narc: W3_H06W0303 N1_V01S0100\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: A2 V02S0701\narc: A3 H02E0701\narc: A6 S1_V02N0101\narc: A7 V00T0100\narc: B2 V02N0301\narc: B3 H00L0000\narc: B6 H02W0101\narc: B7 V01S0000\narc: C0 E1_H01W0000\narc: C1 E1_H01W0000\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 E1_H02W0601\narc: C5 E1_H02W0601\narc: C6 V02S0201\narc: C7 V00T0000\narc: D0 H02W0001\narc: D1 E1_H02W0001\narc: D2 V02N0001\narc: D3 V02N0001\narc: D4 N1_V02S0601\narc: D5 V02N0601\narc: D6 V00B0000\narc: D7 S1_V02N0601\narc: E1_H01E0101 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: N1_V01N0101 F2\narc: N1_V02N0301 F3\narc: N3_V06N0203 F7\narc: N3_V06N0303 F6\narc: S1_V02S0301 F1\narc: S1_V02S0501 F5\narc: S3_V06S0303 F6\narc: V01S0000 F6\narc: V01S0100 F0\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 1010110011001100\nword: SLICEB.K1.INIT 1100101010101010\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 0010001100100000\nword: SLICED.K1.INIT 1101000010000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R29C42:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0003 N3_V06S0003\narc: H00L0000 V02S0001\narc: H00L0100 V02S0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 V02S0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 V01N0101\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 E1_H02W0601\narc: V00T0100 H02E0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 V06S0003\narc: W1_H02W0701 H01E0101\narc: E1_H02E0001 W3_H06E0003\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 N1_V01S0000\narc: W3_H06W0303 N1_V01S0100\narc: W3_H06W0203 E3_H06W0203\narc: A1 H02E0501\narc: B1 V02N0101\narc: B2 H01W0100\narc: B3 H01W0100\narc: B7 V02S0701\narc: C0 N1_V01N0001\narc: C1 H00R0100\narc: C2 H00L0000\narc: C3 H00L0000\narc: C6 V00B0100\narc: C7 H02E0401\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 W1_H02E0001\narc: D2 N1_V02S0201\narc: D3 H02W0201\narc: D6 V00B0000\narc: D7 H02E0201\narc: E1_H01E0001 Q7\narc: E1_H01E0101 Q4\narc: E3_H06E0103 F2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q7\narc: H01W0100 Q4\narc: M0 H02E0601\narc: M2 V00T0100\narc: M4 W1_H02E0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 F0\narc: N1_V02N0601 Q4\narc: S3_V06S0203 Q4\narc: V00B0100 Q7\narc: V01S0100 F6\narc: W1_H02W0001 F2\narc: W1_H02W0501 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0011000000110011\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 1111110000001100\nword: SLICEA.K0.INIT 0000000011110000\nword: SLICEA.K1.INIT 1010101000001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\n\n.tile R29C43:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V02S0301\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0103 V06S0103\narc: H00L0000 H02W0001\narc: H00L0100 V02N0301\narc: H00R0100 S1_V02N0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 H02E0701\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0501\narc: V00T0100 W1_H02E0301\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 E3_H06W0203\narc: N1_V02N0201 W3_H06E0103\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0203 E3_H06W0203\narc: A2 V02N0501\narc: A3 W1_H02E0501\narc: A6 H02W0701\narc: A7 N1_V01N0101\narc: B0 W1_H02E0101\narc: B1 W1_H02E0101\narc: B2 F3\narc: B3 H02W0301\narc: B4 H01E0101\narc: B5 H01E0101\narc: B6 H02W0101\narc: B7 V00B0000\narc: C0 H00L0000\narc: C1 H00L0000\narc: C2 H00R0100\narc: C3 V02N0401\narc: C4 E1_H02W0401\narc: C5 V02N0201\narc: C6 H02E0601\narc: C7 V02S0201\narc: D0 V02S0001\narc: D1 V00B0100\narc: D2 S1_V02N0001\narc: D3 N1_V02S0201\narc: D4 H02W0001\narc: D5 H00L0100\narc: D6 F2\narc: D7 E1_H01W0100\narc: E1_H01E0101 F7\narc: E3_H06E0203 F4\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F0\narc: M0 V00T0100\narc: M4 V00T0100\narc: N1_V01N0101 F3\narc: N1_V02N0101 F3\narc: N3_V06N0003 F0\narc: S3_V06S0003 F0\narc: W1_H02W0001 F0\narc: W3_H06W0003 F3\narc: W3_H06W0303 F6\nword: SLICED.K0.INIT 0000000000001101\nword: SLICED.K1.INIT 1000011001011101\nword: SLICEB.K0.INIT 1101000010000000\nword: SLICEB.K1.INIT 0000101000001100\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111110000001100\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1111110000001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R29C44:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0103 N3_V06S0103\narc: E3_H06E0303 N3_V06S0303\narc: H00L0000 V02N0201\narc: H00L0100 N1_V02S0301\narc: H00R0000 W1_H02E0401\narc: H00R0100 H02E0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 H06E0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02E0601\narc: V00T0000 N1_V02S0601\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 S3_V06N0203\narc: E1_H02E0501 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: A3 V02N0701\narc: B0 H02E0101\narc: B1 H02E0101\narc: B2 H00R0100\narc: B3 V02N0101\narc: B5 V02N0501\narc: B6 H02E0101\narc: B7 H02E0101\narc: C0 V02N0601\narc: C1 H00L0000\narc: C2 N1_V01S0100\narc: C3 V02S0601\narc: C4 V00B0100\narc: C5 V00T0000\narc: C6 N1_V02S0201\narc: C7 V02N0201\narc: CE1 H00R0000\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 V00T0100\narc: D2 W1_H02E0001\narc: D3 V02N0001\narc: D4 H02E0001\narc: D5 V02N0401\narc: D6 H00L0100\narc: D7 E1_H02W0201\narc: E1_H01E0001 F0\narc: E1_H01E0101 F6\narc: E1_H02E0701 Q5\narc: E3_H06E0003 F0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F6\narc: M0 H02E0601\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F3\narc: N3_V06N0003 F0\narc: N3_V06N0203 F4\narc: V00B0100 Q5\narc: V01S0000 Q5\narc: V01S0100 Q2\narc: W1_H02W0201 F0\narc: W1_H02W0601 F6\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 1010110011001100\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 1111110000110000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111110000001100\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111110000001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R29C45:PLC2\narc: E1_H02E0101 V06N0103\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V06S0203\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0103 H01E0101\narc: H00L0000 H02W0001\narc: H00L0100 W1_H02E0301\narc: H00R0100 S1_V02N0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 H01E0101\narc: N3_V06N0103 H01E0101\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02S0001\narc: V00B0100 H02W0501\narc: V00T0100 H02E0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V02N0501\narc: E1_H02E0201 W3_H06E0103\narc: A0 E1_H02W0501\narc: A1 E1_H02W0501\narc: A2 E1_H02W0501\narc: A3 E1_H02W0501\narc: A4 V02S0101\narc: A5 V02N0101\narc: A6 H02E0701\narc: A7 H00R0000\narc: B0 H02W0101\narc: B1 H02W0101\narc: B2 H02W0101\narc: B3 H02W0101\narc: B4 S1_V02N0501\narc: B5 H00L0000\narc: B6 H02E0301\narc: B7 H02W0301\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 H02E0601\narc: C5 S1_V02N0201\narc: C6 N1_V02S0001\narc: C7 H02W0401\narc: CLK1 G_HPBX0000\narc: D0 V00B0100\narc: D1 V00B0100\narc: D2 V00B0100\narc: D3 V00B0100\narc: D4 H00R0100\narc: D5 H02E0201\narc: D6 V00B0000\narc: D7 E1_H02W0001\narc: E1_H01E0001 Q1\narc: E1_H01E0101 Q3\narc: E1_H02E0601 F6\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H01W0000 F6\narc: LSR1 V00T0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0001 F6\narc: N3_V06N0303 F6\narc: V01S0000 Q0\narc: V01S0100 Q2\narc: W3_H06W0303 F6\nword: SLICED.K0.INIT 0011001000000010\nword: SLICED.K1.INIT 0101000000110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R29C46:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V01N0101\narc: E3_H06E0303 V06S0303\narc: H00L0100 V02N0101\narc: H00R0000 V02S0401\narc: H00R0100 H02E0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0103\narc: V00B0100 H02W0701\narc: V00T0100 N1_V02S0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 S1_V02N0501\narc: H01W0000 W3_H06E0103\narc: W3_H06W0203 V06S0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: A0 N1_V02S0701\narc: A1 N1_V02S0701\narc: A2 N1_V02S0701\narc: A3 N1_V02S0701\narc: A4 V02S0101\narc: A5 V02N0301\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 H00R0000\narc: B5 E1_H02W0101\narc: B7 V00T0000\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V00B0100\narc: C5 S1_V02N0001\narc: C7 V02S0201\narc: CLK1 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 V00T0100\narc: D3 V00T0100\narc: D4 V02N0401\narc: D5 V02N0601\narc: D7 N1_V02S0601\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR1 H02E0301\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: S1_V02S0101 Q1\narc: V00T0000 Q2\narc: V01S0000 Q3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R29C47:PLC2\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0203 N3_V06S0203\narc: H00L0100 E1_H02W0101\narc: H00R0000 H02E0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H02W0501\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 W1_H02E0401\narc: V00T0000 E1_H02W0001\narc: V00T0100 S1_V02N0501\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 V06S0303\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: S1_V02S0301 W3_H06E0003\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0303 E3_H06W0203\narc: A0 V02N0501\narc: A1 V02N0501\narc: A2 V02N0501\narc: A3 V02N0501\narc: A4 V02S0301\narc: A5 H02E0701\narc: B0 H02E0101\narc: B1 H02E0101\narc: B2 H02E0101\narc: B3 H02E0101\narc: B4 H02E0301\narc: B5 H02W0101\narc: B6 V02S0501\narc: C0 S1_V02N0601\narc: C1 S1_V02N0601\narc: C2 S1_V02N0601\narc: C3 S1_V02N0601\narc: C4 V00T0100\narc: C5 S1_V02N0201\narc: C6 V01N0101\narc: CLK1 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 V00B0000\narc: D5 H02W0201\narc: D6 H00R0100\narc: D7 H00L0100\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: LSR1 W1_H02E0301\narc: M6 V00T0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0001 Q1\narc: N1_V01N0101 Q3\narc: V01S0000 Q2\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R29C48:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0701 V06N0203\narc: H00L0000 N1_V02S0201\narc: H00R0000 H02W0601\narc: H00R0100 H02E0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0103 H01E0101\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0401\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 V06N0103\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 E1_H01W0100\narc: E1_H02E0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: A1 H02E0701\narc: A2 E1_H02W0501\narc: A3 N1_V02S0501\narc: A4 V02N0301\narc: A7 H00R0000\narc: B1 E1_H02W0301\narc: B2 N1_V02S0101\narc: B3 H00R0100\narc: B4 V02S0701\narc: B5 H00L0000\narc: B7 H02W0301\narc: C1 S1_V02N0401\narc: C2 N1_V01N0001\narc: C3 E1_H01W0000\narc: C4 H02E0401\narc: C5 F4\narc: C7 V00T0000\narc: D1 V00B0100\narc: D2 V01S0100\narc: D3 V02S0201\narc: D4 H02W0201\narc: D5 E1_H02W0201\narc: D7 V00B0000\narc: E1_H01E0001 F2\narc: E3_H06E0203 F4\narc: E3_H06E0303 F5\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F4\narc: N1_V01N0001 F7\narc: N1_V01N0101 F4\narc: N1_V02N0401 F4\narc: S3_V06S0203 F4\narc: V01S0000 F1\narc: V01S0100 F3\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1001000000001001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1001000000001001\nword: SLICEB.K0.INIT 1001000000000000\nword: SLICEB.K1.INIT 1000010000100001\nword: SLICEC.K0.INIT 0011001000000010\nword: SLICEC.K1.INIT 0000111100110011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R29C49:PLC2\narc: E1_H02E0401 N3_V06S0203\narc: H00L0000 E1_H02W0201\narc: H00R0000 V02N0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 H02E0101\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N1_V02S0601\narc: V00B0100 N1_V02S0301\narc: V00T0000 H02W0001\narc: V00T0100 E1_H02W0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0701 E3_H06W0203\narc: E1_H01E0101 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A3 V00T0000\narc: A4 H02W0701\narc: B3 E1_H02W0301\narc: B4 V02N0701\narc: B5 V02S0501\narc: C3 H02W0401\narc: C4 V00B0100\narc: C5 N1_V02S0201\narc: C7 S1_V02N0201\narc: CE0 H02W0101\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 H00R0000\narc: D4 W1_H02E0201\narc: D5 H00R0100\narc: D7 V02S0601\narc: E1_H01E0001 F7\narc: E1_H02E0501 F5\narc: E3_H06E0203 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F1\narc: M0 W1_H02E0601\narc: M1 H00L0000\narc: M2 W1_H02E0601\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 F4\narc: V01S0100 Q1\narc: W1_H02W0101 Q1\narc: W1_H02W0601 F4\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001111\nword: SLICEC.K0.INIT 0011001000000010\nword: SLICEC.K1.INIT 0011001100001111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1100000011001000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R29C4:PLC2\narc: E1_H02E0201 H01E0001\narc: H00L0000 E1_H02W0201\narc: H00R0000 V02N0601\narc: H00R0100 V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 H06W0203\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 V01N0101\narc: S3_V06S0103 H06W0103\narc: V00B0000 H02E0601\narc: V00B0100 V02N0101\narc: V00T0000 H02E0201\narc: V00T0100 V02S0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 E1_H01W0100\narc: A0 N1_V02S0701\narc: A1 H02E0701\narc: A3 F7\narc: A6 S1_V02N0101\narc: A7 N1_V01S0100\narc: B0 V00B0000\narc: B1 H02E0101\narc: B3 H01W0100\narc: B6 V00T0000\narc: B7 V02S0701\narc: C0 E1_H02W0601\narc: C1 H00L0000\narc: C3 H00L0100\narc: C6 V02N0201\narc: C7 E1_H02W0401\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 H00R0000\narc: D3 H01E0101\narc: D6 H00R0100\narc: D7 H02E0001\narc: E1_H01E0001 Q4\narc: E1_H01E0101 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0100 F0\narc: M2 N1_V01N0001\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F6\narc: N1_V01N0101 Q4\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111001101010001\nword: SLICEA.K1.INIT 1111001101010001\nword: SLICED.K0.INIT 1000001001000001\nword: SLICED.K1.INIT 1100001101000001\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R29C50:PLC2\narc: E1_H02E0401 V06S0203\narc: E3_H06E0103 H01E0101\narc: H00L0100 V02S0101\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H02W0401\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 N1_V02S0401\narc: W1_H02W0001 V02S0001\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 H01E0101\narc: W1_H02W0701 S1_V02N0701\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: S1_V02S0601 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 V01N0001\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0003 Q0\narc: S3_V06S0203 Q4\narc: V01S0000 Q6\narc: V01S0100 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R29C51:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0501 N3_V06S0303\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 V06S0203\narc: E3_H06E0303 S3_V06N0303\narc: H00R0100 V02S0501\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 H06E0003\narc: N1_V02N0601 N1_V01S0000\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00B0100 N1_V02S0101\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0701 E1_H02W0601\narc: N1_V02N0401 W3_H06E0203\narc: N3_V06N0103 W3_H06E0103\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H02E0601 Q6\narc: M0 V00B0000\narc: M2 V00B0100\narc: M4 H02E0401\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0001 Q0\narc: S1_V02S0401 Q4\narc: V01S0000 Q6\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R29C52:PLC2\narc: H00R0100 V02S0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H02E0001\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0401\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 H06E0303\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 V02N0001\narc: V00B0100 V02S0101\narc: V00T0000 V02S0401\narc: V00T0100 H02E0301\narc: W1_H02W0501 N3_V06S0303\narc: N1_V02N0201 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: E3_H06E0203 Q4\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0601 Q6\narc: V01S0000 Q0\narc: V01S0100 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R29C53:PLC2\narc: H00R0100 V02S0501\narc: N1_V02N0101 N3_V06S0103\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 H01E0101\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0601\narc: V00T0100 N1_V02S0501\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H02E0001 Q2\narc: E1_H02E0201 Q0\narc: M0 V00T0000\narc: M2 V00T0100\narc: M4 V00B0100\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: V01S0000 Q4\narc: V01S0100 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R29C54:PLC2\narc: E1_H02E0401 V02S0401\narc: H00L0000 N1_V02S0001\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 N3_V06S0203\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02S0101\narc: V00T0000 H02W0001\narc: V00T0100 N1_V02S0501\narc: W1_H02W0401 N1_V02S0401\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: H01W0000 Q0\narc: M0 V00T0000\narc: M2 V00B0100\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q2\narc: S1_V02S0201 Q0\narc: S1_V02S0401 Q6\narc: V01S0100 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R29C55:PLC2\narc: H00L0100 N1_V02S0301\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 H06E0303\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S1_V02N0201\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 H06E0203\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02S0301\narc: V00T0000 V02S0601\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 N3_V06S0003\narc: N3_V06N0203 W3_H06E0203\narc: W3_H06W0203 N3_V06S0203\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: H01W0000 Q2\narc: H01W0100 Q6\narc: M0 V00T0000\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q2\narc: V01S0000 Q0\narc: V01S0100 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R29C56:PLC2\narc: H00L0000 H02W0001\narc: H00R0000 V02S0601\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0001 V01N0001\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0103 N3_V06S0103\narc: V00B0100 N1_V02S0101\narc: V00T0000 S1_V02N0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0601 N3_V06S0303\narc: N3_V06N0103 W3_H06E0103\narc: B2 H00R0000\narc: B3 H00R0000\narc: C2 N1_V01S0100\narc: C3 N1_V01S0100\narc: CE0 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D2 N1_V01S0000\narc: D3 N1_V01S0000\narc: E1_H01E0101 F3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0100 F2\narc: M0 V00T0000\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0201 Q0\narc: S1_V02S0401 Q4\narc: V01S0000 Q4\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100001100111100\nword: SLICEB.K1.INIT 1111110011000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R29C57:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: H00L0000 N1_V02S0001\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0401 N3_V06S0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 H01E0101\narc: V00B0100 N1_V02S0101\narc: V00T0000 N1_V02S0601\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 N1_V02S0001\narc: N1_V02N0301 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: H01W0000 Q0\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0601 Q6\narc: V01S0000 Q4\narc: V01S0100 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R29C58:PLC2\narc: H00L0000 H02E0001\narc: S1_V02S0101 N1_V02S0001\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0201\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0401 V06S0203\narc: CE1 H00L0000\narc: CLK0 G_HPBX0000\narc: M2 V00B0000\narc: MUXCLK1 CLK0\narc: S1_V02S0201 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R29C59:PLC2\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\n\n.tile R29C5:PLC2\narc: H00L0000 H02E0201\narc: H00L0100 E1_H02W0101\narc: H00R0000 V02S0601\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0401 H06W0203\narc: N1_V02N0701 H02W0701\narc: S1_V02S0101 V01N0101\narc: S1_V02S0501 H02W0501\narc: V00B0100 V02S0101\narc: V00T0000 E1_H02W0001\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 S1_V02N0201\narc: A1 E1_H01E0001\narc: A4 V00T0000\narc: B1 V01N0001\narc: B2 F3\narc: B3 H00L0000\narc: B4 H00R0000\narc: B5 F3\narc: C1 N1_V02S0401\narc: C2 V02N0401\narc: C3 H00L0100\narc: C4 E1_H02W0601\narc: C5 E1_H02W0401\narc: C7 V02N0201\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 V02N0001\narc: D3 H01E0101\narc: D4 H02W0001\narc: D5 V02N0601\narc: D7 V02S0601\narc: E1_H01E0001 Q1\narc: E3_H06E0103 F2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q1\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0101 F5\narc: N1_V02N0501 F7\narc: N1_V02N0601 F4\narc: V01S0000 F3\narc: V01S0100 Q1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111100101010\nword: SLICEC.K0.INIT 0100110011001100\nword: SLICEC.K1.INIT 1111111111000000\nword: SLICEB.K0.INIT 0000000000000011\nword: SLICEB.K1.INIT 0000110000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R29C62:PLC2\narc: S3_V06S0203 N3_V06S0103\n\n.tile R29C64:PLC2\narc: S3_V06S0103 N3_V06S0003\n\n.tile R29C65:PLC2\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\n\n.tile R29C6:PLC2\narc: H00L0000 V02S0201\narc: H00L0100 H02W0301\narc: H00R0000 V02S0601\narc: H00R0100 V02N0501\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 N1_V01S0000\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0201\narc: V00B0100 H02W0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 N1_V01S0100\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A1 H00L0000\narc: A3 V00B0000\narc: B1 V02S0301\narc: B3 V02S0101\narc: C1 V02N0401\narc: C3 V02N0401\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D3 S1_V02N0201\narc: E3_H06E0003 Q3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00L0100\narc: M2 V00B0100\narc: M3 H00R0100\narc: M4 V00B0100\narc: M5 H00L0100\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: N3_V06N0003 F3\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1110101011000000\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 1110101011000000\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 1111111111111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R29C7:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0401 V06S0203\narc: E3_H06E0203 V06S0203\narc: H00L0000 V02S0001\narc: H00R0000 V02S0401\narc: N1_V02N0201 H06W0103\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0101 V01N0101\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N1_V01S0100\narc: V00B0000 V02N0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 S1_V02N0601\narc: V00T0100 E1_H02W0301\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A7 H00L0000\narc: B7 H02W0101\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D7 E1_H02W0001\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q4\narc: M0 V00B0100\narc: M2 V00B0000\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: W1_H02W0001 Q2\narc: W1_H02W0501 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0101001111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R29C8:PLC2\narc: E1_H02E0201 N1_V01S0000\narc: H00R0100 H02W0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0701 H02W0701\narc: S1_V02S0201 N3_V06S0103\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0601\narc: V00T0100 N1_V02S0701\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0701 E1_H02W0601\narc: W3_H06W0203 E3_H06W0203\narc: CE0 H00R0100\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: E1_H02E0001 Q0\narc: H01W0100 Q4\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0601 Q6\narc: V01S0100 Q0\narc: W1_H02W0201 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R29C9:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 N3_V06S0303\narc: H00L0100 H02W0101\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 H02W0501\narc: S1_V02S0701 E1_H01W0100\narc: V00B0100 S1_V02N0301\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0301 V02S0301\narc: W1_H02W0701 V06S0203\narc: A5 V02N0301\narc: B5 N1_V01S0000\narc: C5 V01N0101\narc: D5 S1_V02N0401\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00L0100\narc: M2 V00B0100\narc: M3 H02E0201\narc: M4 V00B0100\narc: M5 H00L0100\narc: M6 V00B0100\narc: N3_V06N0003 F3\narc: W1_H02W0101 F3\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 1011111111111111\nword: SLICED.K0.INIT 1111111111111111\nword: SLICED.K1.INIT 1111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R2C10:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 S1_V02N0401\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: CLK0 G_HPBX0000\narc: D3 S1_V02N0201\narc: E1_H02E0601 Q6\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: M6 E1_H02W0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00T0100 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R2C11:PLC2\narc: V00T0000 S1_V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: F1 F1_SLICE\narc: LSR0 V00T0100\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: V00T0100 F1\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R2C12:PLC2\narc: E3_H06E0203 W1_H02E0401\narc: S1_V02S0101 V01N0101\narc: S1_V02S0301 H06E0003\narc: S1_V02S0601 W1_H02E0601\narc: V00T0100 S1_V02N0701\narc: W1_H02W0401 S1_V02N0401\narc: CLK0 G_HPBX0000\narc: D7 W1_H02E0201\narc: F7 F7_SLICE\narc: LSR0 V00B0100\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V00B0100 F7\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R2C13:PLC2\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0701 E1_H01W0100\narc: V00B0100 S1_V02N0301\narc: CLK0 G_HPBX0000\narc: D3 H02W0001\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V00T0100 F3\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R2C14:PLC2\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0103 V06N0103\narc: H00R0100 E1_H02W0501\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 E1_H02W0501\narc: CLK0 G_HPBX0000\narc: D5 H00R0100\narc: F5 F5_SLICE\narc: H01W0100 Q2\narc: LSR0 V00B0100\narc: M2 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: V00B0100 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R2C15:PLC2\narc: H00R0100 H02W0501\narc: V00T0100 S1_V02N0701\narc: CLK0 G_HPBX0000\narc: D7 H00R0100\narc: F7 F7_SLICE\narc: LSR1 V00B0100\narc: M2 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00B0100 F7\narc: W1_H02W0201 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R2C16:PLC2\narc: V00B0000 W1_H02E0601\narc: W1_H02W0501 S1_V02N0501\narc: CLK0 G_HPBX0000\narc: D5 S1_V02N0401\narc: F5 F5_SLICE\narc: LSR0 V00B0100\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00B0100 F5\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R2C17:PLC2\narc: S1_V02S0401 E1_H02W0401\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 E3_H06W0103\narc: V00B0100 V02N0301\narc: A0 V02N0501\narc: B2 V01N0001\narc: B3 V02N0101\narc: B4 V00B0100\narc: B5 S1_V02N0701\narc: B6 V02N0701\narc: E1_H02E0401 F4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: N1_V01N0001 F6\narc: S1_V02S0101 F3\narc: S1_V02S0701 F5\narc: V01S0000 F2\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R2C18:PLC2\narc: E1_H02E0501 V02N0501\narc: H00R0100 H02W0501\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0303 E3_H06W0303\narc: E3_H06E0303 W3_H06E0203\narc: B3 E1_H01W0100\narc: C2 H00R0100\narc: C3 E1_H01W0000\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 H02W0201\narc: E1_H01E0001 F3\narc: E1_H01E0101 F3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0000 Q2\narc: LSR1 E1_H02W0301\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: S1_V02S0001 Q2\narc: S1_V02S0301 F3\narc: V00T0100 F3\narc: V01S0000 F2\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0000000000110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R2C19:PLC2\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 V02S0301\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 H01E0001\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02S0201\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 E3_H06W0203\narc: A4 N1_V01N0101\narc: A6 N1_V01N0101\narc: B4 H01E0101\narc: B6 V00B0100\narc: C4 V02S0001\narc: C6 Q6\narc: C7 H02W0601\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D4 S1_V02N0401\narc: D5 H00R0100\narc: D6 V00B0000\narc: D7 V02N0601\narc: E1_H01E0001 Q5\narc: E1_H01E0101 F4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 Q5\narc: H01W0000 Q6\narc: H01W0100 Q7\narc: LSR0 H02E0501\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q5\narc: S3_V06S0303 Q5\narc: V00B0100 Q7\narc: V01S0000 Q7\narc: W1_H02W0501 Q5\nword: SLICED.K0.INIT 0111100011110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 1111111101001111\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R2C20:PLC2\narc: H00L0000 S1_V02N0201\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0103 E3_H06W0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0601 H01E0001\narc: E3_H06E0203 W3_H06E0103\narc: CE0 S1_V02N0201\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: M0 V00B0000\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: S1_V02S0001 Q0\narc: S1_V02S0401 Q4\narc: V00B0000 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R2C21:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: V00T0100 V02N0501\narc: A0 W1_H02E0701\narc: A2 V02N0701\narc: A3 V01N0101\narc: A4 V02N0101\narc: A5 V00T0100\narc: A6 V02N0301\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: H01W0000 F6\narc: S1_V02S0001 F2\narc: S1_V02S0101 F3\narc: S1_V02S0501 F5\narc: V01S0100 F4\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R2C22:PLC2\narc: E1_H02E0501 S1_V02N0501\narc: CLK0 G_HPBX0000\narc: LSR0 H02W0301\narc: M6 H02E0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: S1_V02S0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R2C23:PLC2\narc: E1_H02E0301 V06N0003\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S3_V06N0303\narc: H00R0100 V02N0501\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 E1_H01W0000\narc: V00B0100 V02S0301\narc: V01S0100 S3_V06N0303\narc: W1_H02W0301 S1_V02N0301\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H02E0001 Q2\narc: LSR0 H02E0501\narc: M2 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: W3_H06W0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R2C24:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V01N0101\narc: H00R0000 H02E0601\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 E1_H01W0000\narc: V00B0000 V02S0001\narc: V00B0100 H02W0701\narc: V00T0000 H02W0201\narc: V00T0100 H02E0301\narc: E3_H06E0303 W3_H06E0303\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q4\narc: E1_H02E0601 Q6\narc: H01W0000 Q2\narc: H01W0100 Q4\narc: LSR0 W1_H02E0501\narc: LSR1 W1_H02E0501\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: V01S0000 Q0\narc: V01S0100 Q2\narc: W3_H06W0003 Q0\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R2C25:PLC2\narc: E1_H02E0501 V06N0303\narc: H00L0000 W1_H02E0001\narc: H00R0000 V02N0401\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 H01E0101\narc: V00T0000 S1_V02N0401\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0701 N1_V01S0100\narc: W3_H06W0203 E3_H06W0103\narc: A0 S1_V02N0701\narc: A2 V00T0000\narc: A3 H01E0001\narc: A4 W1_H02E0501\narc: A5 S1_V02N0101\narc: A6 H00L0000\narc: A7 H00R0000\narc: E1_H02E0201 F2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F4\narc: S1_V02S0701 F5\narc: S3_V06S0303 F6\narc: W1_H02W0101 F3\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R2C26:PLC2\narc: E1_H02E0301 V02N0301\narc: H00L0000 W1_H02E0201\narc: H00R0000 W1_H02E0601\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 W1_H02E0401\narc: V00T0000 W1_H02E0001\narc: W1_H02W0001 E1_H01W0000\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0003\narc: A0 H00L0000\narc: A1 H00R0000\narc: A2 V00B0000\narc: A3 V00T0000\narc: A4 W1_H02E0501\narc: A5 H02E0501\narc: A6 V02N0101\narc: A7 S1_V02N0101\narc: E1_H01E0001 F4\narc: E1_H01E0101 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: S1_V02S0001 F2\narc: S1_V02S0201 F0\narc: S1_V02S0701 F7\narc: S3_V06S0303 F6\narc: V01S0000 F3\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 0101101010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R2C27:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0601 S1_V02N0601\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0601 H01E0001\narc: S3_V06S0103 H01E0101\narc: V00B0000 V02N0201\narc: V00B0100 V02N0301\narc: V00T0100 S1_V02N0501\narc: A0 V02N0701\narc: A1 V02N0501\narc: B4 S1_V02N0501\narc: B5 E1_H02W0101\narc: B7 V00B0100\narc: C4 H02W0401\narc: C5 V00T0100\narc: C7 V00T0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 V00B0000\narc: D7 V00B0000\narc: E1_H01E0001 Q7\narc: E1_H02E0401 Q4\narc: E1_H02E0501 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0000 F1\narc: LSR0 H02E0301\narc: LSR1 E1_H02W0501\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: S1_V02S0001 F0\narc: S1_V02S0701 Q7\narc: V01S0100 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110011111111\nword: SLICEC.K0.INIT 1111110011111111\nword: SLICEC.K1.INIT 1111001111111111\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R2C28:PLC2\narc: E3_H06E0003 V06N0003\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 V02N0001\narc: H00R0000 V02N0601\narc: H00R0100 H02E0501\narc: V00B0000 H02E0401\narc: W1_H02W0401 V01N0001\narc: A6 V00T0100\narc: B1 S1_V02N0101\narc: B3 H00L0000\narc: B5 H00R0000\narc: B6 V01S0000\narc: C1 H02E0601\narc: C3 H02E0601\narc: C5 H02E0601\narc: C6 H01E0001\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: D3 H02E0201\narc: D5 H02E0201\narc: D6 V00B0000\narc: E1_H01E0101 F6\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: S1_V02S0101 Q1\narc: S1_V02S0301 Q3\narc: S3_V06S0303 F6\narc: V00B0100 Q5\narc: V00T0100 Q3\narc: V01S0000 Q1\narc: V01S0100 Q5\nword: SLICED.K0.INIT 0000000000000001\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111110011111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111110011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R2C29:PLC2\narc: S1_V02S0401 E1_H01W0000\narc: S3_V06S0203 E3_H06W0203\narc: V00T0000 V02N0401\narc: W1_H02W0101 H01E0101\narc: W1_H02W0501 E1_H01W0100\narc: A0 E1_H02W0501\narc: A2 E1_H01E0001\narc: A3 H00L0100\narc: A4 V00B0000\narc: A5 Q5\narc: A6 H00R0000\narc: A7 Q7\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q7\narc: E1_H02E0301 Q3\narc: E1_H02E0401 Q4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: H00R0000 Q6\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: S1_V02S0601 Q6\narc: V00B0000 Q4\narc: V01S0000 Q5\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R2C2:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0601 V06N0303\n\n.tile R2C30:PLC2\narc: V00B0000 H02E0401\narc: V00B0100 V02N0101\narc: V00T0100 H02E0301\narc: H01W0100 W3_H06E0303\narc: W1_H02W0501 W3_H06E0303\narc: A0 H00L0000\narc: A1 H00L0100\narc: A2 E1_H01E0001\narc: A6 N1_V01N0101\narc: A7 V00T0100\narc: B6 V00T0000\narc: B7 H01E0101\narc: C6 E1_H01E0101\narc: C7 H01E0001\narc: CLK0 G_HPBX0000\narc: D6 H00R0100\narc: D7 V00B0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00L0100 Q1\narc: H00R0100 F7\narc: H01W0000 F6\narc: LSR1 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: N1_V01N0101 Q1\narc: V00T0000 Q0\nword: SLICED.K0.INIT 0000000100000000\nword: SLICED.K1.INIT 0000000000000001\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000001010\nword: SLICEB.K0.INIT 0101101010101010\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R2C31:PLC2\narc: S1_V02S0501 S3_V06N0303\narc: V00B0000 V02S0201\narc: V01S0000 S3_V06N0103\narc: W1_H02W0501 S1_V02N0501\narc: CLK0 G_HPBX0000\narc: M0 V00B0000\narc: M2 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: V00T0000 Q0\narc: W3_H06W0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R2C32:PLC2\narc: S1_V02S0101 E3_H06W0103\narc: S3_V06S0103 E3_H06W0103\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\n\n.tile R2C33:PLC2\narc: H00R0000 E1_H02W0401\narc: H00R0100 V02S0701\narc: V00B0000 V02N0001\narc: V00T0000 H02W0201\narc: V00T0100 H02W0301\narc: V01S0000 S3_V06N0103\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: M0 V00T0000\narc: M2 H02W0601\narc: M4 V00B0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0201 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R2C34:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0301 S1_V02N0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 V02N0501\narc: S1_V02S0601 H02W0601\narc: V00B0000 V02N0001\narc: V00T0100 H02W0101\narc: W1_H02W0201 V06N0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 V01N0001\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: A3 V01N0101\narc: A5 N1_V01N0101\narc: B3 E1_H02W0101\narc: B5 H01E0101\narc: C3 H00R0100\narc: C5 V02N0201\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D5 V02N0601\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: S3_V06S0103 F1\narc: V00B0100 F5\narc: V01S0000 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000001001000001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 0111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R2C35:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 V06N0103\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 S3_V06N0203\narc: H00R0000 E1_H02W0401\narc: S1_V02S0201 H06W0103\narc: V00B0000 E1_H02W0601\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02N0401\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0601 S3_V06N0303\narc: W3_H06W0203 E3_H06W0203\narc: A1 E1_H01E0001\narc: A2 E1_H01E0001\narc: B1 V01N0001\narc: B2 V01N0001\narc: C1 H02W0401\narc: C2 H02W0401\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: E1_H01E0001 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 V00T0000\narc: M1 V01S0100\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q6\narc: W1_H02W0101 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1010001011110011\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010001011110011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R2C36:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0701 S3_V06N0203\narc: E3_H06E0203 S3_V06N0203\narc: H00R0000 S1_V02N0401\narc: H00R0100 H02E0701\narc: S1_V02S0301 E1_H02W0301\narc: V00B0000 H02E0601\narc: V00B0100 V02S0301\narc: V00T0000 V02S0601\narc: V00T0100 V02N0501\narc: W1_H02W0401 E1_H02W0401\narc: A1 H01E0001\narc: A2 H01E0001\narc: B1 H02E0301\narc: B2 H02E0301\narc: C1 V02N0601\narc: C2 V02N0601\narc: CE2 H00R0100\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: E1_H02E0401 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 V00B0100\narc: M1 V01S0100\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q6\narc: W1_H02W0101 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100111101000101\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100111101000101\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R2C37:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 S1_V02N0601\narc: H00R0100 W1_H02E0701\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0103 H06E0103\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 H02W0401\narc: V00B0100 H02W0701\narc: V00T0000 W1_H02E0201\narc: V00T0100 S1_V02N0501\narc: V01S0000 S3_V06N0103\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 V02N0601\narc: A1 V02N0501\narc: A2 V02N0501\narc: B1 V02N0301\narc: B2 V02N0101\narc: C1 S1_V02N0401\narc: C2 S1_V02N0401\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 V00T0100\narc: E1_H01E0001 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H00R0000 Q6\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000110010101111\nword: SLICEB.K0.INIT 1000110010101111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R2C38:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0701 W1_H02E0701\narc: H00R0000 W1_H02E0401\narc: H00R0100 H02E0501\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 V02N0101\narc: V00T0000 E1_H02W0201\narc: V00T0100 W1_H02E0101\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0701 S1_V02N0701\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0303 E3_H06W0203\narc: A3 H01E0001\narc: A4 V00B0000\narc: A5 H02W0701\narc: B3 V02S0101\narc: B4 H00R0000\narc: B5 H02W0101\narc: C3 S1_V02N0401\narc: C4 V02N0001\narc: C5 V00T0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 V01S0100\narc: D4 V02S0601\narc: D5 W1_H02E0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 F1\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 F1\narc: M0 V00B0100\narc: M1 H02W0001\narc: M2 V00B0100\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F4\narc: S1_V02S0101 F1\narc: S3_V06S0103 F1\narc: V00B0000 Q6\narc: V01S0100 F5\narc: W1_H02W0301 F1\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1000010000100001\nword: SLICEC.K1.INIT 1000001001000001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 0111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R2C39:PLC2\narc: E1_H02E0201 V06N0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0601 S3_V06N0303\narc: H00L0000 H02E0001\narc: H00R0100 H02E0701\narc: S1_V02S0001 H01E0001\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 H01E0101\narc: V00B0100 S1_V02N0101\narc: V00T0100 H02E0301\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: A1 E1_H01E0001\narc: A2 V00B0000\narc: B1 E1_H01W0100\narc: B2 E1_H01W0100\narc: C1 W1_H02E0601\narc: C2 H00L0000\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: D2 V02N0201\narc: E1_H01E0001 Q4\narc: E1_H02E0401 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H00R0000 Q6\narc: H01W0100 Q4\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: M4 E1_H02W0401\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V00B0000 Q4\narc: V01S0000 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111001101010001\nword: SLICEB.K0.INIT 1111001101010001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R2C3:PLC2\narc: E1_H02E0601 V01N0001\narc: H00L0100 S1_V02N0301\narc: H00R0100 V02N0501\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 S3_V06N0303\narc: V00B0100 H02W0701\narc: V00T0000 H02E0001\narc: V01S0000 S3_V06N0103\narc: V01S0100 S3_V06N0303\narc: A7 H00L0000\narc: B7 H02E0301\narc: C7 V00T0000\narc: CE0 H00L0100\narc: CE1 V02N0201\narc: CLK0 G_HPBX0000\narc: D7 H00R0100\narc: E1_H01E0101 Q2\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0100 Q0\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00B0100\narc: M2 H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: S1_V02S0701 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R2C40:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0401 W1_H02E0401\narc: H00R0000 H02E0401\narc: H00R0100 E1_H02W0701\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 E1_H02W0701\narc: V00B0100 V02N0101\narc: V00T0100 S1_V02N0701\narc: W1_H02W0201 V02N0201\narc: S1_V02S0101 W3_H06E0103\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: A1 V01N0101\narc: A2 V01N0101\narc: B1 W1_H02E0101\narc: B2 H00R0000\narc: C1 V02N0601\narc: C2 V02N0601\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: D2 H02E0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 Q4\narc: M0 H02E0601\narc: M1 V01S0100\narc: M2 H02E0601\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0000 F1\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100010011110101\nword: SLICEB.K0.INIT 1100010011110101\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R2C41:PLC2\narc: H00R0000 H02W0401\narc: N1_V01N0001 S3_V06N0003\narc: S1_V02S0201 H06E0103\narc: S1_V02S0401 H02W0401\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 H06W0203\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02N0601\narc: V00T0100 S1_V02N0501\narc: W1_H02W0401 S1_V02N0401\narc: W3_H06W0203 E3_H06W0103\narc: A1 E1_H01E0001\narc: A2 V00B0000\narc: B1 W1_H02E0301\narc: B2 W1_H02E0301\narc: C1 H02E0401\narc: C2 H02E0401\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D2 S1_V02N0001\narc: E1_H01E0001 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 Q6\narc: M0 V00B0100\narc: M1 V01S0100\narc: M2 N1_V01N0001\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0101 F1\narc: V00B0000 Q6\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000110010101111\nword: SLICEB.K0.INIT 1000110010101111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R2C42:PLC2\narc: S1_V02S0701 W3_H06E0203\narc: W1_H02W0401 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\n\n.tile R2C43:PLC2\narc: E1_H02E0001 V01N0001\narc: H00L0000 V02N0001\narc: H00R0100 V02N0701\narc: A3 V01N0101\narc: B3 H00R0100\narc: C3 H00L0000\narc: D3 S1_V02N0001\narc: E1_H02E0101 F3\narc: F3 F3_SLICE\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R2C44:PLC2\narc: H00L0000 V02N0001\narc: E3_H06E0303 W3_H06E0303\narc: A1 V01N0101\narc: A3 V02N0701\narc: A5 V02N0301\narc: A7 V00T0100\narc: B1 V01N0001\narc: B3 S1_V02N0301\narc: B5 V02N0501\narc: B7 H02E0101\narc: C1 V02N0601\narc: C3 H00L0000\narc: C5 V02N0201\narc: C7 E1_H02W0401\narc: D1 H02E0001\narc: D3 H02W0001\narc: D5 V02N0401\narc: D6 H00R0100\narc: D7 F2\narc: E3_H06E0203 F7\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: M2 V00B0100\narc: S1_V02S0401 F6\narc: S3_V06S0203 F7\narc: V00B0100 F5\narc: V00T0100 F1\narc: V01S0100 F6\narc: W3_H06W0203 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000001\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R2C45:PLC2\narc: H00R0000 V02N0401\narc: S1_V02S0701 V01N0101\narc: W1_H02W0001 V02N0001\narc: A3 V01N0101\narc: B3 V01N0001\narc: C3 S1_V02N0601\narc: D3 H00R0000\narc: E1_H01E0001 F3\narc: F3 F3_SLICE\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R2C46:PLC2\narc: E3_H06E0203 V06N0203\narc: S1_V02S0001 E1_H02W0001\narc: W1_H02W0401 H01E0001\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\n\n.tile R2C47:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0301 S3_V06N0003\narc: E3_H06E0003 S3_V06N0003\narc: S3_V06S0203 H06E0203\narc: W3_H06W0103 E3_H06W0003\n\n.tile R2C48:PLC2\narc: E1_H02E0501 S3_V06N0303\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0003 H01E0001\narc: W1_H02W0001 S3_V06N0003\n\n.tile R2C49:PLC2\narc: S1_V02S0201 H02W0201\n\n.tile R2C4:PLC2\narc: E1_H02E0501 S1_V02N0501\narc: H00L0100 E1_H02W0301\narc: S1_V02S0701 H01E0101\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02W0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0701 V06N0203\narc: A7 H00L0000\narc: B7 V00T0000\narc: C7 E1_H02W0601\narc: CE0 H02W0101\narc: CE1 H00L0100\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D7 E1_H02W0201\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0100 F7\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 H02E0601\narc: M2 W1_H02E0601\narc: M4 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q2\narc: V01S0100 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R2C50:PLC2\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0301 H06E0003\narc: S1_V02S0501 W1_H02E0501\narc: W1_H02W0201 E1_H02W0701\narc: N1_V02N0501 W3_H06E0303\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\n\n.tile R2C52:PLC2\narc: W1_H02W0701 S3_V06N0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\n\n.tile R2C53:PLC2\narc: S3_V06S0303 H06E0303\narc: W3_H06W0003 E3_H06W0303\n\n.tile R2C56:PLC2\narc: E3_H06E0003 W3_H06E0303\n\n.tile R2C58:PLC2\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\n\n.tile R2C59:PLC2\narc: S3_V06S0003 H06E0003\narc: W3_H06W0303 E3_H06W0203\n\n.tile R2C5:PLC2\narc: E1_H02E0401 V06N0203\narc: H00L0100 H02W0301\narc: H00R0100 E1_H02W0701\narc: S1_V02S0101 V01N0101\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0401 V01N0001\narc: CE0 H00R0100\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M0 E1_H02W0601\narc: M2 E1_H02W0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: S1_V02S0201 Q0\narc: V01S0000 Q2\narc: W1_H02W0001 Q2\narc: W1_H02W0201 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R2C64:PLC2\narc: E1_H02E0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\n\n.tile R2C65:PLC2\narc: W3_H06W0203 E3_H06W0203\n\n.tile R2C66:PLC2\narc: N1_V02N0701 W1_H02E0701\n\n.tile R2C67:PLC2\narc: N1_V02N0201 H06E0103\n\n.tile R2C6:PLC2\narc: H00L0100 E1_H02W0301\narc: H00R0100 H02W0701\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0601 H06W0303\narc: V00B0000 H02E0401\narc: V00T0100 V02N0501\narc: V01S0000 S3_V06N0103\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0601 S1_V02N0601\narc: CE0 H00L0100\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 V00T0100\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: S1_V02S0201 Q0\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R2C70:PLC2\narc: E1_H02E0701 V02S0701\narc: E1_H01E0001 W3_H06E0003\n\n.tile R2C7:PLC2\narc: E1_H02E0301 V02S0301\narc: H00L0100 H02W0301\narc: H00R0100 E1_H02W0701\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 E1_H02W0601\narc: V00B0100 V02S0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 E1_H02W0701\narc: A3 V00B0000\narc: B3 E1_H01W0100\narc: C3 S1_V02N0601\narc: CE0 H00R0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D3 H02W0001\narc: F3 F3_SLICE\narc: H01W0100 F3\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 V00B0100\narc: M4 E1_H02W0401\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: S1_V02S0001 Q0\narc: V00B0000 Q4\narc: V01S0000 Q0\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R2C8:PLC2\narc: H00L0100 S1_V02N0301\narc: S1_V02S0301 H02E0301\narc: V00T0000 V02N0601\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 E1_H02W0401\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: H01W0100 Q2\narc: LSR1 E1_H02W0301\narc: M2 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R2C9:PLC2\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 V06N0203\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 S3_V06N0203\narc: W3_H06W0303 S3_V06N0303\narc: CLK0 G_HPBX0000\narc: D7 H02W0201\narc: E3_H06E0003 Q0\narc: F7 F7_SLICE\narc: LSR0 V00B0100\narc: M0 E1_H02W0601\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V00B0100 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R30C10:PLC2\narc: E1_H02E0401 V06S0203\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 N1_V02S0001\narc: H00R0000 V02N0401\narc: H01W0100 E3_H06W0303\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 E3_H06W0303\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 E3_H06W0303\narc: V00B0000 W1_H02E0601\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02S0401\narc: V00T0100 H02E0101\narc: W1_H02W0001 V02S0001\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 V02S0701\narc: W3_H06W0003 E3_H06W0303\narc: A1 E1_H01E0001\narc: A2 E1_H01E0001\narc: B1 V00B0000\narc: B2 H02E0301\narc: C1 H00L0000\narc: C2 H00L0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: E1_H01E0001 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 V00T0000\narc: M1 V01S0100\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: S1_V02S0401 Q6\narc: V01S0100 Q4\narc: W1_H02W0301 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111010100110001\nword: SLICEB.K0.INIT 1111010100110001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R30C11:PLC2\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 E3_H06W0203\narc: H00R0000 H02E0401\narc: H00R0100 V02N0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0301 E1_H02W0301\narc: V00B0000 V02S0001\narc: V00B0100 H02W0501\narc: V00T0100 V02S0501\narc: W1_H02W0501 V06S0303\narc: W3_H06W0303 V06S0303\narc: A7 N1_V01N0101\narc: B7 V00T0000\narc: C7 V00B0100\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D7 S1_V02N0601\narc: F7 F7_SLICE\narc: M0 V00T0100\narc: M2 E1_H02W0601\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q4\narc: V00T0000 Q2\narc: V01S0000 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000010000100001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R30C12:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V01N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 V02S0301\narc: H00R0000 V02N0401\narc: H00R0100 H02W0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 H02E0401\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02N0101\narc: V00T0000 S1_V02N0601\narc: V00T0100 V02S0701\narc: W1_H02W0501 S1_V02N0501\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A1 H00L0100\narc: A5 H02E0501\narc: B1 V00T0000\narc: B5 H00R0000\narc: C1 V02N0601\narc: C5 V02S0001\narc: CE1 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D5 H02W0001\narc: F0 F5A_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q2\narc: M0 V00T0100\narc: M2 V00B0100\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F0\narc: N1_V01N0101 Q6\narc: V01S0100 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000100000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111011101110011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R30C13:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0701 W1_H02E0701\narc: H00L0000 H02W0001\narc: H00R0000 H02W0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02W0701\narc: V00T0000 N1_V02S0601\narc: V00T0100 H02E0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 E3_H06W0203\narc: A3 H02E0701\narc: B0 H01W0100\narc: B3 V02N0101\narc: C0 S1_V02N0401\narc: C3 H00L0000\narc: CE2 H00R0100\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V00B0100\narc: D3 H02E0201\narc: E1_H01E0001 Q0\narc: E1_H02E0301 F3\narc: E1_H02E0601 Q4\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: H01W0100 Q0\narc: M0 V00T0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R30C14:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V02N0301\narc: H00L0000 S1_V02N0201\narc: H00L0100 H02E0301\narc: H00R0000 H02E0601\narc: H00R0100 H02E0701\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 V01N0101\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 V02S0601\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 H01E0101\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 V06S0203\narc: A0 E1_H02W0701\narc: A1 H00L0000\narc: A3 H01E0001\narc: A5 V00B0000\narc: B0 F1\narc: B1 W1_H02E0101\narc: B3 H00R0000\narc: B5 V02N0501\narc: C0 H00L0100\narc: C1 W1_H02E0401\narc: C3 H00R0100\narc: C5 V02N0001\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 F2\narc: D1 H02W0001\narc: D3 H02E0201\narc: D5 V02N0601\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: N1_V02N0401 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0111011101110011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R30C15:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0601 N3_V06S0303\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0103 N3_V06S0103\narc: V00B0100 H02W0501\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 V02N0301\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A5 V00T0000\narc: B5 H00R0000\narc: C5 V00B0100\narc: CE0 E1_H02W0101\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D5 H02E0201\narc: F5 F5_SLICE\narc: H00R0000 Q6\narc: LSR0 H02W0301\narc: LSR1 H02E0301\narc: M0 V00T0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: V00T0000 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R30C16:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 E3_H06W0303\narc: H00L0000 E1_H02W0001\narc: H00R0000 N1_V02S0601\narc: H00R0100 E1_H02W0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0201\narc: V00T0000 V02S0601\narc: V00T0100 V02S0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 N3_V06S0303\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0303 E3_H06W0203\narc: A4 E1_H01W0000\narc: A5 S1_V02N0301\narc: A7 H02W0701\narc: B4 H00R0000\narc: B5 H00L0000\narc: B7 W1_H02E0101\narc: C4 H02E0601\narc: C5 V01N0101\narc: C7 V00T0100\narc: CE0 H00R0100\narc: CE1 H02W0101\narc: CLK0 G_HPBX0000\narc: D4 H02E0001\narc: D5 V02N0601\narc: D7 E1_H02W0001\narc: E1_H01E0101 Q0\narc: E3_H06E0203 F4\narc: E3_H06E0303 F5\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00B0000\narc: M2 N1_V01N0001\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: N1_V01N0101 Q2\narc: W1_H02W0701 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1100101000000000\nword: SLICEC.K1.INIT 0111000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R30C17:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0501 V02S0501\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02N0601\narc: H00R0100 V02S0701\narc: N1_V02N0101 H02E0101\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 E3_H06W0303\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 H02W0401\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0701 V02N0701\narc: W3_H06W0203 E1_H02W0401\narc: W3_H06W0303 E3_H06W0203\narc: A1 E1_H01E0001\narc: B1 H01W0100\narc: C1 H00R0100\narc: CE1 H00R0000\narc: CE2 H00L0100\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: E1_H01E0001 Q2\narc: E3_H06E0103 F1\narc: F1 F1_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q4\narc: M2 V00B0000\narc: M4 H02W0401\narc: M6 H02E0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R30C18:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 V02N0701\narc: H00L0000 V02S0201\narc: H00L0100 E1_H02W0101\narc: H00R0000 V02S0601\narc: H00R0100 S1_V02N0701\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0201\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02S0401\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 S1_V02N0701\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E1_H02W0701\narc: W3_H06W0303 E3_H06W0203\narc: A0 H00L0000\narc: A1 H02E0501\narc: A2 H02W0501\narc: A3 S1_V02N0501\narc: A5 N1_V01N0101\narc: B0 V00T0000\narc: B1 V00T0000\narc: B2 H02E0101\narc: B3 E1_H01W0100\narc: B5 V02N0501\narc: C0 H02W0401\narc: C1 H02W0601\narc: C2 H00L0100\narc: C3 S1_V02N0601\narc: C5 V00B0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 H00R0000\narc: D2 H02W0001\narc: D3 F2\narc: D5 E1_H01W0100\narc: E1_H01E0101 F0\narc: E3_H06E0003 F3\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: LSR1 H02W0301\narc: M4 E1_H01E0101\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q6\narc: N1_V02N0101 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0001001101011111\nword: SLICEA.K1.INIT 0101001111111111\nword: SLICEB.K0.INIT 0001010100111111\nword: SLICEB.K1.INIT 0111000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R30C19:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0301 V06S0003\narc: E1_H02E0601 N3_V06S0303\narc: H00L0100 E1_H02W0101\narc: H00R0000 V02N0401\narc: H00R0100 V02N0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 H06W0303\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 S1_V02N0201\narc: V00B0100 E1_H02W0701\narc: V00T0000 W1_H02E0201\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V02S0701\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A7 E1_H02W0501\narc: B2 V02S0101\narc: B7 V00T0000\narc: C1 H02W0601\narc: C2 V02S0601\narc: C7 V00B0100\narc: CE1 H00R0100\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D2 S1_V02N0001\narc: D3 H02W0201\narc: D7 H00L0100\narc: E1_H02E0501 Q7\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q7\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M2 V00B0000\narc: M4 H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q4\narc: N1_V02N0301 F1\narc: V01S0000 Q2\narc: W1_H02W0501 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111110000000\nword: SLICEB.K0.INIT 1111111111001111\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R30C20:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0401 V02S0401\narc: E3_H06E0203 W1_H02E0701\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 E1_H02W0401\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00T0000 V02S0401\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 E3_H06W0203\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: CE0 H00R0100\narc: CE1 H02E0101\narc: CE2 H00R0100\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: E1_H02E0601 Q4\narc: E3_H06E0003 Q0\narc: E3_H06E0303 Q6\narc: H01W0100 Q2\narc: M0 V00B0000\narc: M2 H02E0601\narc: M4 V00T0000\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R30C21:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 V06S0003\narc: E1_H02E0501 S1_V02N0501\narc: H00R0000 N1_V02S0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0701 H02W0701\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 H02W0501\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02N0201\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02E0201\narc: V00T0100 V02N0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 V02N0701\narc: W3_H06W0003 N3_V06S0003\narc: W3_H06W0203 N1_V01S0000\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: B0 V00B0000\narc: B2 H00R0100\narc: C0 E1_H02W0601\narc: C2 E1_H02W0601\narc: C5 V02S0001\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D2 V00T0100\narc: D5 V02S0401\narc: E1_H01E0001 F5\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: M6 V00T0000\narc: MUXCLK3 CLK0\narc: N1_V02N0601 Q6\narc: W1_H02W0101 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICEA.K0.INIT 0000110011001100\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000110011001100\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R30C22:PLC2\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 H01E0001\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0303 N3_V06S0303\narc: H00L0100 S1_V02N0301\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 H06E0203\narc: N3_V06N0303 H06W0303\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 E1_H02W0401\narc: V00B0100 E1_H02W0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 V02S0501\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0303 E1_H02W0501\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A3 H02W0701\narc: A6 H00R0000\narc: B3 E1_H02W0101\narc: B6 V02N0701\narc: C3 V02N0601\narc: C6 V00B0100\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D3 V02N0001\narc: D6 H01W0000\narc: D7 H01W0000\narc: E1_H01E0101 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 Q6\narc: H01W0000 F1\narc: M0 V00B0000\narc: M1 H00L0100\narc: M2 V00B0000\narc: M4 W1_H02E0401\narc: M6 E1_H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0401 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0100110011001100\nword: SLICED.K0.INIT 1111111100110010\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R30C23:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0701 H01E0101\narc: H00L0100 V02S0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H02E0701\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 H06W0203\narc: V00B0000 V02N0201\narc: V00T0000 H02W0201\narc: V00T0100 E1_H02W0101\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 E1_H01W0100\narc: N1_V02N0201 W3_H06E0103\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A4 V00B0000\narc: A6 W1_H02E0501\narc: B1 H00R0100\narc: B3 V02N0301\narc: B4 E1_H02W0301\narc: B5 H02E0301\narc: B6 W1_H02E0301\narc: C1 H02W0601\narc: C2 H00L0100\narc: C3 H02W0601\narc: C4 V00B0100\narc: C5 V02S0201\narc: C6 V00T0100\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H02E0201\narc: D3 H00R0000\narc: D4 W1_H02E0201\narc: D5 E1_H02W0001\narc: D6 S1_V02N0401\narc: E1_H01E0001 F3\narc: E1_H01E0101 F2\narc: E3_H06E0103 F1\narc: E3_H06E0303 Q6\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q6\narc: H01W0100 F1\narc: LSR1 V00T0000\narc: M6 H02E0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q6\narc: N3_V06N0103 F1\narc: N3_V06N0203 F4\narc: N3_V06N0303 F5\narc: S3_V06S0103 F1\narc: S3_V06S0303 F5\narc: V00B0100 F5\narc: V01S0000 F1\narc: V01S0100 F2\narc: W3_H06W0303 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100000000000000\nword: SLICEB.K0.INIT 0000111100000000\nword: SLICEB.K1.INIT 1100000000000000\nword: SLICEC.K0.INIT 0001001101011111\nword: SLICEC.K1.INIT 0011001100110000\nword: SLICED.K0.INIT 1111111110001111\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R30C24:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 H01E0001\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 V01N0101\narc: H00L0100 W1_H02E0301\narc: H00R0100 V02S0501\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02W0701\narc: V00T0100 V02N0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 N1_V01S0100\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 H02E0701\narc: A3 H00L0100\narc: A4 S1_V02N0301\narc: A5 N1_V02S0301\narc: B0 V02N0101\narc: B1 V02N0301\narc: B3 V02S0301\narc: B4 V01S0000\narc: B5 V02S0501\narc: C0 N1_V01N0001\narc: C1 H00L0000\narc: C3 H00R0100\narc: C4 V02S0001\narc: C5 H02W0601\narc: C7 W1_H02E0601\narc: D0 E1_H02W0001\narc: D1 V00B0100\narc: D3 V00T0100\narc: D4 V02N0401\narc: D5 H01W0000\narc: D7 V02S0601\narc: E1_H01E0001 F4\narc: E1_H01E0101 F1\narc: E1_H02E0701 F5\narc: E3_H06E0303 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H01W0000 F7\narc: H01W0100 F1\narc: M2 V00B0000\narc: N1_V01N0001 F5\narc: N1_V01N0101 F5\narc: N3_V06N0303 F5\narc: S1_V02S0701 F5\narc: S3_V06S0303 F5\narc: W1_H02W0501 F5\narc: W3_H06W0103 F2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEA.K0.INIT 0001010100111111\nword: SLICEA.K1.INIT 0011000011110000\nword: SLICEC.K0.INIT 0001001101011111\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R30C25:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 V02S0701\narc: E3_H06E0303 H01E0101\narc: H00L0000 S1_V02N0201\narc: H00L0100 N1_V02S0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02W0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0003 H01E0001\narc: N3_V06N0203 V01N0001\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 H02W0601\narc: V00B0000 V02N0001\narc: V00B0100 H02W0701\narc: V00T0000 E1_H02W0201\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 N1_V01S0100\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0203\narc: A0 S1_V02N0701\narc: A2 E1_H01E0001\narc: A3 V02S0501\narc: A4 H02E0501\narc: A5 V00T0000\narc: A6 H00L0000\narc: B0 V00B0000\narc: B1 F3\narc: B2 H02W0101\narc: B3 V02S0101\narc: B4 V02N0701\narc: B5 V02S0701\narc: B6 S1_V02N0501\narc: B7 F3\narc: C0 N1_V01N0001\narc: C1 H02W0401\narc: C2 V02N0401\narc: C3 H00L0100\narc: C4 E1_H01E0101\narc: C5 E1_H02W0401\narc: C6 V02N0201\narc: C7 V00B0100\narc: D0 V01S0100\narc: D1 V02S0201\narc: D2 V00T0100\narc: D3 H00R0000\narc: D4 H02E0001\narc: D5 W1_H02E0201\narc: D6 H00R0100\narc: D7 V02S0601\narc: E1_H01E0001 F3\narc: E1_H01E0101 F5\narc: E1_H02E0401 F4\narc: E1_H02E0501 F5\narc: E3_H06E0003 F3\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F7\narc: N1_V01N0001 F5\narc: N1_V01N0101 F1\narc: N1_V02N0301 F1\narc: N1_V02N0501 F7\narc: N1_V02N0701 F5\narc: N3_V06N0103 F2\narc: N3_V06N0303 F6\narc: S1_V02S0501 F5\narc: S3_V06S0103 F2\narc: S3_V06S0203 F7\narc: S3_V06S0303 F5\narc: V01S0000 F7\narc: V01S0100 F1\narc: W1_H02W0201 F0\narc: W3_H06W0103 F2\narc: W3_H06W0303 F5\nword: SLICEA.K0.INIT 0001001101011111\nword: SLICEA.K1.INIT 1100000000000000\nword: SLICED.K0.INIT 0001001101011111\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEC.K0.INIT 0001001101011111\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 1000000000000000\nword: SLICEB.K1.INIT 0001000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R30C26:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 V02S0701\narc: H00L0000 S1_V02N0001\narc: H00R0000 V02S0401\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 V01N0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 H06W0203\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 H06E0103\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0701\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 E1_H02W0701\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A0 N1_V02S0701\narc: A1 H02W0701\narc: A2 V00B0000\narc: A3 V00T0000\narc: A5 V00T0000\narc: A6 V02N0101\narc: B0 H02W0301\narc: B1 E1_H02W0301\narc: B2 V02S0101\narc: B3 H00L0000\narc: B4 H00R0000\narc: B5 S1_V02N0501\narc: B6 H02E0101\narc: B7 H02W0101\narc: C0 V02S0401\narc: C1 E1_H01W0000\narc: C2 V02N0601\narc: C3 V02S0601\narc: C4 H02E0601\narc: C5 N1_V02S0001\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 F0\narc: D2 V00T0100\narc: D3 W1_H02E0201\narc: D4 E1_H01W0100\narc: D5 H01W0000\narc: D6 H01W0000\narc: D7 H02E0201\narc: E1_H01E0001 F4\narc: E1_H01E0101 F7\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F5\narc: N1_V02N0601 F4\narc: N3_V06N0003 F0\narc: N3_V06N0103 F1\narc: N3_V06N0203 F4\narc: N3_V06N0303 F6\narc: S1_V02S0601 F4\narc: S3_V06S0003 F0\narc: S3_V06S0203 F4\narc: V00T0000 Q2\narc: V00T0100 F3\narc: V01S0000 F0\narc: V01S0100 F0\narc: W1_H02W0201 F0\narc: W3_H06W0003 F0\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 0001001101011111\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEC.K0.INIT 1100000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 1000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 1111111110000000\nword: SLICEB.K1.INIT 0000000011001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R30C27:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 H01E0001\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 V06S0303\narc: H00L0000 H02W0001\narc: H00L0100 N1_V02S0301\narc: H00R0000 H02W0601\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 N1_V01S0000\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 N3_V06S0303\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0701\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02S0701\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A5 E1_H01W0000\narc: A6 S1_V02N0301\narc: A7 V02S0301\narc: B1 V00B0000\narc: B2 V02N0101\narc: B5 H00R0000\narc: B6 V02N0501\narc: B7 F1\narc: C1 V02S0601\narc: C2 H00L0000\narc: C5 H02W0401\narc: C6 E1_H01E0101\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D2 V00T0100\narc: D3 V00B0100\narc: D5 S1_V02N0401\narc: D6 H00L0100\narc: D7 H00R0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0000 F7\narc: H01W0100 F5\narc: M2 V00T0000\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F5\narc: N1_V02N0301 F1\narc: N1_V02N0401 F6\narc: N1_V02N0701 F7\narc: N3_V06N0103 F1\narc: N3_V06N0203 F7\narc: N3_V06N0303 F5\narc: S3_V06S0203 F7\narc: V01S0000 F5\narc: V01S0100 Q2\narc: W1_H02W0001 Q2\narc: W1_H02W0301 F1\narc: W3_H06W0203 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000001000000\nword: SLICED.K0.INIT 0001010100111111\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R30C28:PLC2\narc: E1_H02E0501 H01E0101\narc: E3_H06E0003 N3_V06S0003\narc: H00L0000 H02E0001\narc: H00R0100 V02S0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 N1_V02S0301\narc: V00B0000 N1_V02S0201\narc: V00T0000 V02N0401\narc: V00T0100 V02N0701\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 N1_V01S0100\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: A3 V00T0000\narc: A4 V02S0101\narc: A5 N1_V01N0101\narc: B3 V01N0001\narc: B4 W1_H02E0101\narc: B5 E1_H02W0301\narc: C3 H00L0000\narc: C4 V00T0100\narc: C5 E1_H02W0601\narc: CE0 H00R0100\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D3 W1_H02E0201\narc: D4 V02S0601\narc: D5 W1_H02E0001\narc: E1_H01E0001 F2\narc: E3_H06E0303 Q6\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q6\narc: M0 V00B0000\narc: M2 W1_H02E0601\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q4\narc: N1_V02N0401 Q6\narc: N3_V06N0303 Q6\narc: V01S0100 Q0\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111110000000\nword: SLICEC.K1.INIT 0000000011001010\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R30C29:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0401 W1_H02E0101\narc: E3_H06E0003 N3_V06S0003\narc: E3_H06E0103 N1_V01S0100\narc: H00L0000 E1_H02W0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 V02N0401\narc: H00R0100 V02S0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 V01N0101\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 H01E0001\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0301 H06E0003\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 H06E0003\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 V02S0001\narc: V00B0100 V02S0101\narc: V00T0000 V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 N3_V06S0203\narc: E1_H02E0501 W3_H06E0303\narc: N3_V06N0303 W3_H06E0303\narc: S1_V02S0201 W3_H06E0103\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0303 E1_H01W0100\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: B0 H00R0100\narc: C0 E1_H01W0000\narc: C1 H00L0000\narc: C3 V02S0601\narc: CE0 H00R0000\narc: CE2 H00L0100\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 V00T0100\narc: D3 N1_V02S0001\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: H01W0100 Q4\narc: LSR0 V00B0000\narc: M0 V00B0100\narc: M4 V00T0000\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N3_V06N0003 Q0\narc: V01S0000 F0\narc: W1_H02W0101 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111100000000\nword: SLICEA.K0.INIT 0000110011001100\nword: SLICEA.K1.INIT 0000111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R30C2:PLC2\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 V02N0101\narc: H00R0000 H02W0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0003 N3_V06S0303\narc: V00B0000 H02W0601\narc: A0 H00R0000\narc: A1 N1_V02S0501\narc: A7 V00T0100\narc: B0 V02N0301\narc: B1 V00B0000\narc: B7 F1\narc: C0 H00R0100\narc: C1 H00R0100\narc: C3 H00L0100\narc: C7 V02S0201\narc: D0 S1_V02N0001\narc: D1 E1_H02W0201\narc: D3 S1_V02N0201\narc: D7 V02S0601\narc: E1_H02E0601 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: M6 V00T0000\narc: V00T0000 F0\narc: V00T0100 F3\narc: V01S0000 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011110000\nword: SLICEA.K0.INIT 1111010100110001\nword: SLICEA.K1.INIT 1000101011001111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000010000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R30C30:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 V02S0201\narc: H00R0100 V02N0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H02E0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 H02W0601\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02S0701\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 V02S0601\narc: H01W0000 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: N3_V06N0203 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A1 V01N0101\narc: A3 E1_H02W0501\narc: B0 H01W0100\narc: B1 V01N0001\narc: B2 E1_H02W0101\narc: B3 V02N0101\narc: B4 H00R0000\narc: B6 V02N0701\narc: C0 H00L0000\narc: C1 H02E0401\narc: C2 E1_H02W0601\narc: C3 H02W0401\narc: C4 V00T0000\narc: C6 N1_V02S0001\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H02E0201\narc: D2 N1_V02S0201\narc: D3 V02N0201\narc: D4 V02S0601\narc: D5 V02S0401\narc: D6 H00L0100\narc: D7 H00R0100\narc: E1_H01E0101 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H00R0000 Q4\narc: H01W0100 Q4\narc: M4 V00B0000\narc: MUXCLK2 CLK0\narc: N3_V06N0003 F0\narc: S1_V02S0401 F6\narc: V01S0100 F1\narc: W1_H02W0701 F7\nword: SLICEB.K0.INIT 0000111100110011\nword: SLICEB.K1.INIT 0000000000000010\nword: SLICED.K0.INIT 0000000000110000\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 0011111100000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R30C31:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0303 H01E0101\narc: H00L0000 N1_V02S0001\narc: H00L0100 H02W0301\narc: H00R0100 V02N0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 H06E0003\narc: N1_V02N0701 H06E0203\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 N1_V01S0000\narc: V00B0000 V02N0001\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02N0401\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 V02S0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0601 W3_H06E0303\narc: S3_V06S0203 W3_H06E0203\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0303 N3_V06S0303\narc: A1 V02S0501\narc: A3 V00B0000\narc: A4 H02W0701\narc: A7 H00L0000\narc: B1 V02S0301\narc: B2 S1_V02N0301\narc: B3 V02N0101\narc: B4 H02E0301\narc: B7 S1_V02N0501\narc: C0 N1_V02S0401\narc: C1 V02N0401\narc: C2 H00L0100\narc: C3 H00R0100\narc: C4 V00T0100\narc: C7 V00T0000\narc: D0 H02E0001\narc: D1 V02N0201\narc: D2 H02E0201\narc: D3 V00B0100\narc: D4 H02W0201\narc: D7 H00R0100\narc: E1_H01E0101 F1\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F0\narc: M4 E1_H01E0101\narc: S1_V02S0101 F3\narc: V01S0000 F7\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000100000000000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000100000000000\nword: SLICEB.K0.INIT 0000111100110011\nword: SLICEB.K1.INIT 0000000000000010\nword: SLICEC.K0.INIT 0000000100000011\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R30C32:PLC2\narc: E1_H02E0301 V01N0101\narc: H00L0100 H02E0101\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0303 H06E0303\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 H02E0401\narc: V00B0100 V02N0301\narc: V00T0100 H02E0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0701 W3_H06E0203\narc: N3_V06N0003 W3_H06E0003\narc: N3_V06N0103 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0303\narc: A0 E1_H02W0501\narc: A3 H02W0701\narc: A5 V02N0301\narc: A7 N1_V02S0101\narc: B0 H00R0100\narc: B2 E1_H01W0100\narc: B3 H02E0101\narc: B4 V00B0100\narc: B5 H02E0101\narc: B7 N1_V02S0501\narc: C0 H00L0100\narc: C2 S1_V02N0401\narc: C3 H02E0401\narc: C4 W1_H02E0401\narc: C5 H02E0401\narc: C7 V00T0100\narc: D0 V01S0100\narc: D2 H02W0201\narc: D3 H02E0001\narc: D4 H02W0201\narc: D5 H02E0001\narc: D7 V00B0000\narc: E1_H01E0001 F7\narc: E1_H02E0401 F4\narc: E3_H06E0103 F2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 F0\narc: M0 H02W0601\narc: V01S0100 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000100000000000\nword: SLICEC.K0.INIT 0000111100110011\nword: SLICEC.K1.INIT 0000000000000010\nword: SLICEB.K0.INIT 0000111100110011\nword: SLICEB.K1.INIT 0000000000000010\nword: SLICEA.K0.INIT 0000000000010011\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R30C33:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0701 W1_H02E0601\narc: H00L0000 V02S0001\narc: H00L0100 V02S0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0601 N1_V01S0000\narc: S3_V06S0003 N1_V01S0000\narc: V00B0100 H02E0701\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 V02S0701\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: B1 E1_H02W0101\narc: B3 S1_V02N0101\narc: B5 S1_V02N0701\narc: C1 S1_V02N0401\narc: C3 H00L0100\narc: C5 S1_V02N0201\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: D3 V02N0201\narc: D5 V02N0401\narc: E1_H02E0301 Q3\narc: E1_H02E0601 Q6\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q6\narc: N1_V02N0101 Q3\narc: N3_V06N0103 Q1\narc: N3_V06N0303 Q5\narc: S3_V06S0103 Q1\narc: S3_V06S0303 Q5\narc: W3_H06W0003 Q3\narc: W3_H06W0103 Q1\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100110011110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R30C34:PLC2\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V02S0701\narc: E3_H06E0203 W1_H02E0401\narc: H00R0000 V02S0601\narc: H00R0100 H02E0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 N1_V01S0000\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 V02N0201\narc: V00B0100 H02E0701\narc: V00T0000 N1_V02S0601\narc: W1_H02W0201 V06S0103\narc: W1_H02W0501 V02S0501\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: A6 V02N0101\narc: B6 V00B0100\narc: C6 V02N0001\narc: CE1 H02E0101\narc: CLK0 G_HPBX0000\narc: D6 V00B0000\narc: E1_H02E0101 Q3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H00R0000\narc: M2 V00T0000\narc: M3 H00R0100\narc: M4 V00T0000\narc: M5 H00R0000\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: N1_V02N0301 F3\narc: N3_V06N0003 Q3\narc: S3_V06S0003 Q3\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0111111111111111\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R30C35:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 W1_H02E0601\narc: H00L0000 N1_V02S0201\narc: H00L0100 N1_V02S0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 H02W0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0501 H06E0303\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02W0601\narc: V00T0000 V02S0601\narc: V00T0100 V02N0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0501 N1_V02S0501\narc: W3_H06W0103 N1_V01S0100\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: A3 H00L0100\narc: A7 V02S0301\narc: B2 H02W0101\narc: B3 H02W0301\narc: B7 F3\narc: C2 H00L0000\narc: C3 V02N0601\narc: C7 E1_H01E0101\narc: CE0 V02S0201\narc: CE2 W1_H02E0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 V02S0001\narc: D3 H00R0000\narc: D6 H01W0000\narc: D7 V00B0000\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F2\narc: E3_H06E0003 Q0\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: H01W0100 Q4\narc: M0 V00T0100\narc: M4 H02W0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1100110010100000\nword: SLICED.K0.INIT 1111111100000000\nword: SLICED.K1.INIT 1111110011101110\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\n\n.tile R30C36:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 V01N0001\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0103 W1_H02E0101\narc: H00L0000 H02W0001\narc: H00R0000 V02S0401\narc: H00R0100 V02S0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0701 H06W0203\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02W0501\narc: V00T0000 V02S0601\narc: V00T0100 H02E0301\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 N3_V06S0203\narc: E1_H01E0101 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: A1 W1_H02E0701\narc: A2 V00T0000\narc: A7 E1_H02W0501\narc: B1 H01W0100\narc: B2 H02W0301\narc: B6 W1_H02E0301\narc: B7 V02S0501\narc: C1 F6\narc: C2 H02E0401\narc: C6 W1_H02E0601\narc: C7 V02S0001\narc: CE0 H00R0100\narc: CE1 H00L0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 S1_V02N0001\narc: D2 W1_H02E0201\narc: D6 H02E0001\narc: D7 V02N0401\narc: E1_H01E0001 F2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q2\narc: N1_V02N0201 Q2\narc: V01S0100 F7\narc: W1_H02W0001 Q2\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1010101011000000\nword: SLICEB.K0.INIT 0100110011001100\nword: SLICEB.K1.INIT 1111111111111111\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111110011101110\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\n\n.tile R30C37:PLC2\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 V06S0003\narc: E3_H06E0203 H01E0001\narc: H00L0000 E1_H02W0001\narc: H00R0000 H02W0401\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 H06E0303\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02S0201\narc: V00B0100 H02E0701\narc: V00T0000 H02E0001\narc: V00T0100 H02W0101\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 E1_H02W0301\narc: H01W0000 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: B4 H00R0000\narc: B6 N1_V02S0501\narc: C4 V00T0100\narc: C6 V00B0100\narc: CE0 H02E0101\narc: CE1 H00L0000\narc: CLK0 G_HPBX0000\narc: D4 H02E0201\narc: D5 N1_V02S0601\narc: D6 H02E0201\narc: D7 V00B0000\narc: E3_H06E0003 Q0\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: M0 W1_H02E0601\narc: M2 N1_V01N0001\narc: M4 V00T0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 Q0\narc: S1_V02S0401 F6\narc: S1_V02S0601 F4\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000000110011\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1111000000110011\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R30C38:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 V02S0501\narc: H00L0100 V02S0301\narc: H00R0000 H02W0401\narc: N1_V02N0301 H02E0301\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 E1_H01W0000\narc: N3_V06N0303 V01N0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 H06E0203\narc: V00B0000 S1_V02N0201\narc: V00B0100 S1_V02N0301\narc: V00T0100 H02W0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 E3_H06W0303\narc: E1_H01E0001 W3_H06E0003\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: A1 N1_V02S0701\narc: A4 V00T0100\narc: A5 V02N0101\narc: B1 E1_H02W0101\narc: B2 V02N0301\narc: B4 H00L0000\narc: B5 S1_V02N0701\narc: B6 E1_H02W0301\narc: C1 H00L0100\narc: C2 E1_H02W0401\narc: C4 H02W0601\narc: C5 S1_V02N0001\narc: C6 W1_H02E0401\narc: D1 S1_V02N0001\narc: D2 H00R0000\narc: D3 H02E0201\narc: D4 H01W0000\narc: D5 E1_H02W0201\narc: D6 N1_V02S0601\narc: D7 N1_V02S0401\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 F0\narc: H01W0000 F5\narc: H01W0100 F4\narc: M0 V00B0000\narc: M2 V00B0100\narc: M6 V00B0100\narc: N1_V02N0401 F6\narc: V01S0000 F2\nword: SLICEC.K0.INIT 0000111100001110\nword: SLICEC.K1.INIT 1100010010000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0110101110110000\nword: SLICEB.K0.INIT 1111000000110011\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1111000000110011\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R30C39:PLC2\narc: E1_H02E0501 V02N0501\narc: H00L0000 H02W0001\narc: H00R0000 H02W0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 E1_H01W0100\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 H06W0103\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 H01E0001\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0201\narc: V00T0000 H02E0201\narc: V00T0100 V02S0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 V06S0303\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0203 E3_H06W0103\narc: A0 S1_V02N0501\narc: A2 H02W0501\narc: A3 H02E0501\narc: A4 V00T0100\narc: A5 V02S0301\narc: A6 V02S0101\narc: A7 N1_V01S0100\narc: B2 V02N0101\narc: B3 H00R0100\narc: B4 H00L0000\narc: B5 H00R0000\narc: B6 V00T0000\narc: B7 V00B0000\narc: E3_H06E0103 F2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: N1_V02N0101 F3\narc: N1_V02N0601 F6\narc: N3_V06N0203 F4\narc: N3_V06N0303 F5\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R30C3:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 N1_V02S0001\narc: H00R0000 V02S0401\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H02E0701\narc: S1_V02S0001 H06W0003\narc: S1_V02S0401 E1_H02W0401\narc: V00B0000 N1_V02S0201\narc: V00B0100 S1_V02N0301\narc: V00T0100 E1_H02W0101\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 N1_V02S0601\narc: A1 E1_H02W0501\narc: A7 E1_H01W0000\narc: B1 V00B0000\narc: B7 V00B0000\narc: C1 S1_V02N0601\narc: C7 V00B0100\narc: D1 E1_H02W0201\narc: D7 E1_H02W0201\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00R0000\narc: M2 V00T0100\narc: M3 H00L0000\narc: M4 V00T0100\narc: M5 H00R0000\narc: M6 V00T0100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000110010101111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000110010101111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R30C40:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 V06S0003\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 E3_H06W0303\narc: H00L0000 N1_V02S0001\narc: H00R0000 V02S0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N1_V02S0301\narc: V00B0000 W1_H02E0401\narc: V00B0100 V02N0301\narc: V00T0000 V02S0401\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 E1_H02W0701\narc: W1_H02W0301 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: A0 V02N0501\narc: A1 V01N0101\narc: A2 V02S0701\narc: A3 V00T0000\narc: A4 V02N0101\narc: A5 H02E0501\narc: A6 N1_V01S0100\narc: A7 H00R0000\narc: B0 H02W0301\narc: B1 H00R0100\narc: B2 H02W0101\narc: B3 H00L0000\narc: B4 W1_H02E0101\narc: B5 N1_V01S0000\narc: B6 V00B0100\narc: B7 V00B0000\narc: E1_H01E0101 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 F2\narc: N1_V01N0001 F7\narc: N3_V06N0003 F0\narc: N3_V06N0103 F1\narc: N3_V06N0303 F5\narc: V01S0000 F6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R30C41:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V02S0601\narc: E3_H06E0003 N3_V06S0003\narc: H00L0000 H02E0201\narc: H00L0100 S1_V02N0301\narc: H00R0100 V02S0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 V01N0001\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0103 H06W0103\narc: N3_V06N0303 H01E0101\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0601 N3_V06S0303\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V02S0101\narc: V00B0000 H02W0601\narc: V00T0000 V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 V06S0303\narc: W3_H06W0203 N1_V01S0000\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A0 H02E0501\narc: A1 H02W0501\narc: A2 V01N0101\narc: A3 H00L0100\narc: A4 V02S0301\narc: A5 N1_V01S0100\narc: A6 V00T0100\narc: A7 H00L0000\narc: B0 V02N0301\narc: B1 N1_V02S0101\narc: B2 H00R0100\narc: B3 H02E0301\narc: B4 H02E0101\narc: B5 N1_V02S0501\narc: B6 V00T0000\narc: B7 V00B0000\narc: E1_H01E0001 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F7\narc: S1_V02S0401 F6\narc: V01S0000 F2\narc: V01S0100 F1\narc: W1_H02W0601 F4\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R30C42:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 N1_V01S0000\narc: H00L0100 V02N0101\narc: H00R0100 V02S0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0103 H06W0103\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 N1_V02S0201\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02W0001\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 E3_H06W0203\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0103 E3_H06W0103\narc: A0 H02W0701\narc: A1 E1_H02W0701\narc: A2 H00L0100\narc: A3 S1_V02N0701\narc: A4 H02W0501\narc: A5 E1_H01W0000\narc: A6 S1_V02N0301\narc: A7 S1_V02N0101\narc: B0 V00T0000\narc: B1 V00B0000\narc: B2 H00R0100\narc: B3 E1_H02W0101\narc: B4 V02S0501\narc: B5 H02E0101\narc: B6 H02W0101\narc: B7 V00B0100\narc: E1_H01E0101 F0\narc: E1_H02E0101 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: N1_V01N0001 F2\narc: N1_V01N0101 F7\narc: S1_V02S0401 F6\narc: S1_V02S0501 F5\narc: S3_V06S0203 F4\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R30C43:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 V02S0701\narc: E3_H06E0103 N3_V06S0103\narc: H00R0100 S1_V02N0701\narc: H01W0100 E3_H06W0303\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 E1_H01W0000\narc: N3_V06N0003 S1_V02N0301\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 H01E0101\narc: V00B0000 V02S0201\narc: V00T0000 E1_H02W0201\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 V01N0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 N3_V06S0303\narc: N1_V02N0301 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0303 E3_H06W0303\narc: A0 S1_V02N0501\narc: A1 H02E0701\narc: B0 V00T0000\narc: B1 N1_V02S0101\narc: C4 W1_H02E0601\narc: C5 W1_H02E0601\narc: C6 W1_H02E0601\narc: C7 W1_H02E0601\narc: D4 N1_V02S0601\narc: D5 V00B0000\narc: D6 V02N0601\narc: D7 H00R0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: V01S0000 F1\narc: V01S0100 F0\narc: W1_H02W0501 F7\narc: W1_H02W0701 F5\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R30C44:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0203 N3_V06S0203\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 E1_H02W0001\narc: H00R0000 H02W0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 H01E0001\narc: N3_V06N0203 E1_H01W0000\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 E1_H02W0401\narc: V00B0100 V02S0301\narc: V00T0000 H02E0201\narc: V00T0100 V02S0501\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 V01N0101\narc: W1_H02W0701 H01E0101\narc: A1 H02W0501\narc: A5 V02N0301\narc: B0 V02N0101\narc: B1 E1_H02W0101\narc: B2 N1_V02S0301\narc: B5 H02E0101\narc: B6 N1_V02S0701\narc: B7 V02N0701\narc: C0 H02W0601\narc: C1 N1_V01N0001\narc: C2 H00L0000\narc: C5 H02E0401\narc: C6 V00T0100\narc: C7 V02N0201\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 H00R0000\narc: D2 V02N0001\narc: D3 V00B0100\narc: D5 V02N0601\narc: D6 V00B0000\narc: D7 N1_V02S0401\narc: E1_H01E0001 F1\narc: E1_H01E0101 F6\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 F2\narc: LSR0 W1_H02E0301\narc: M2 V00T0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: N3_V06N0103 F1\narc: S1_V02S0101 F1\narc: S1_V02S0501 F7\narc: S1_V02S0601 F6\narc: S3_V06S0203 F7\narc: V01S0000 F0\narc: V01S0100 Q6\narc: W3_H06W0103 F1\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1011000000001011\nword: SLICEA.K0.INIT 0000110011111100\nword: SLICEA.K1.INIT 1101000000000000\nword: SLICED.K0.INIT 1100000011001111\nword: SLICED.K1.INIT 0000111100001100\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R30C45:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 H01E0001\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0003 H01E0001\narc: E3_H06E0103 V01N0101\narc: E3_H06E0203 H01E0001\narc: H00L0100 V02N0301\narc: H00R0000 N1_V02S0601\narc: H00R0100 H02E0501\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 H01E0001\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 H01E0101\narc: S3_V06S0203 N1_V02S0701\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02N0101\narc: V00T0000 V02N0601\narc: V00T0100 H02W0301\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 H01E0001\narc: N3_V06N0203 W3_H06E0203\narc: N3_V06N0303 W3_H06E0303\narc: W3_H06W0003 N3_V06S0003\narc: B0 H00R0100\narc: B4 N1_V01S0000\narc: B6 S1_V02N0501\narc: C0 H02E0601\narc: C4 E1_H02W0401\narc: C6 V00T0100\narc: CE0 H00R0000\narc: CE1 V02S0201\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 E1_H02W0001\narc: D4 H02E0001\narc: D5 H00L0100\narc: D6 S1_V02N0601\narc: D7 E1_H02W0001\narc: E1_H01E0001 F4\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q2\narc: M0 H02W0601\narc: M2 V00B0100\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0001 Q0\narc: N3_V06N0003 Q0\narc: V01S0000 Q6\narc: W3_H06W0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000111100110011\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1100000011110011\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1100000011110011\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R30C46:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 V01N0001\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0203 N3_V06S0203\narc: H00L0100 V02S0301\narc: H00R0000 W1_H02E0401\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H01E0001\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 V02S0101\narc: V00T0000 V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 N1_V01S0100\narc: W3_H06W0303 V01N0101\narc: E3_H06E0003 W3_H06E0303\narc: A3 V00T0000\narc: B3 V02N0301\narc: B4 H02E0101\narc: B7 V00B0100\narc: C3 H00L0100\narc: C4 E1_H01E0101\narc: C7 V00T0100\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V02S0001\narc: D3 E1_H02W0201\narc: D4 H02E0201\narc: D5 H01W0000\narc: D7 N1_V02S0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: E1_H02E0301 Q1\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q1\narc: M0 H02W0601\narc: M1 H02E0001\narc: M2 H02W0601\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: N1_V01N0101 F1\narc: N1_V02N0301 F1\narc: N3_V06N0203 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 0011001100001111\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1100000011100000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R30C47:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0003 W1_H02E0301\narc: H00L0100 H02E0301\narc: H00R0100 H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0103 H06E0103\narc: N3_V06N0303 H06E0303\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H02E0401\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 V02N0001\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02N0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 N1_V02S0601\narc: H01W0000 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A0 S1_V02N0501\narc: A1 S1_V02N0501\narc: A2 S1_V02N0501\narc: A3 S1_V02N0501\narc: A4 V00B0000\narc: A5 W1_H02E0701\narc: B0 V02N0101\narc: B1 V02N0101\narc: B2 V02N0101\narc: B3 V02N0101\narc: B4 E1_H02W0101\narc: B5 V02S0701\narc: B6 H02W0101\narc: C0 V02N0601\narc: C1 V02N0601\narc: C2 V02N0601\narc: C3 V02N0601\narc: C4 V00T0100\narc: C5 V02N0201\narc: C6 N1_V02S0201\narc: CLK1 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 E1_H02W0201\narc: D2 E1_H02W0201\narc: D3 E1_H02W0201\narc: D4 S1_V02N0401\narc: D5 S1_V02N0601\narc: D6 H00R0100\narc: D7 H00L0100\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q2\narc: LSR1 H02W0301\narc: M6 V00T0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0101 Q3\narc: S1_V02S0001 Q0\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R30C48:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 E1_H01W0000\narc: E3_H06E0003 W1_H02E0001\narc: H00L0000 E1_H02W0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02W0401\narc: H00R0100 V02S0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 V01N0101\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 H06E0203\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02E0201\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 V06S0203\narc: N1_V02N0101 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: A3 V02N0501\narc: B0 W1_H02E0101\narc: B2 H00L0000\narc: B3 V02S0301\narc: B4 N1_V02S0501\narc: B5 V02N0701\narc: B6 E1_H02W0101\narc: C0 H02E0401\narc: C2 V02S0601\narc: C3 H02W0601\narc: C4 E1_H02W0601\narc: C5 V00T0100\narc: C6 E1_H01E0101\narc: CE1 H00R0100\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 V00B0100\narc: D2 H00R0000\narc: D3 V00T0100\narc: D4 N1_V02S0401\narc: D5 V02N0601\narc: D6 H00L0100\narc: D7 F2\narc: E1_H01E0101 F3\narc: E1_H02E0601 F6\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M0 V00B0000\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F2\narc: S1_V02S0001 F0\narc: S1_V02S0501 F5\narc: S1_V02S0601 F4\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 1100000011001111\nword: SLICEC.K1.INIT 0000110011111100\nword: SLICEB.K0.INIT 1100000011001111\nword: SLICEB.K1.INIT 0000000010101100\nword: SLICEA.K0.INIT 0000111100110011\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1111110011110000\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R30C49:PLC2\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0303 V06N0303\narc: H00L0000 H02E0201\narc: H00L0100 S1_V02N0101\narc: H00R0100 H02W0501\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N1_V02S0401\narc: V00B0000 V02S0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 H02W0001\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 V06S0303\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0003 E1_H01W0000\narc: A3 V00T0000\narc: B3 N1_V02S0301\narc: B5 N1_V02S0701\narc: B6 E1_H02W0301\narc: C3 H00L0000\narc: C4 H02E0401\narc: C5 H02E0601\narc: C6 V02N0001\narc: CE0 E1_H02W0101\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 V00T0100\narc: D4 H00R0100\narc: D5 H00L0100\narc: D6 V02N0601\narc: D7 E1_H01W0100\narc: E1_H01E0001 F6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q5\narc: M0 W1_H02E0601\narc: M1 E1_H02W0001\narc: M2 W1_H02E0601\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N3_V06N0203 F4\narc: S1_V02S0101 F1\narc: V01S0000 F1\narc: V01S0100 Q1\narc: W1_H02W0301 F1\narc: W3_H06W0303 Q5\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 1111110000110000\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000100011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R30C4:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0601 W1_H02E0601\narc: H00L0000 E1_H02W0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 V02S0601\narc: H00R0100 H02W0701\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N1_V02S0401\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 H02E0401\narc: V00B0100 W1_H02E0701\narc: V00T0100 H02W0301\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0501 N1_V01S0100\narc: A0 H00R0000\narc: A1 H02E0501\narc: A3 H00L0100\narc: A7 H02E0701\narc: B0 V02S0301\narc: B1 V00B0000\narc: B3 S1_V02N0301\narc: B7 F3\narc: C0 V02N0401\narc: C1 H00L0000\narc: C3 H02W0601\narc: C7 H01E0001\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 H02W0201\narc: D3 V00B0100\narc: D7 V01N0001\narc: E1_H01E0101 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q4\narc: H01W0100 F1\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: N3_V06N0303 F6\narc: S1_V02S0601 Q4\narc: V00T0000 F0\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100111101000101\nword: SLICEA.K0.INIT 1000110000100011\nword: SLICEA.K1.INIT 1111001101010001\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R30C50:PLC2\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 V02S0001\narc: H00R0000 H02E0401\narc: H00R0100 V02S0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 H06E0003\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 H06E0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 E1_H02W0501\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 E1_H02W0701\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0101 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: A3 V00B0000\narc: B3 H00L0000\narc: B6 S1_V02N0501\narc: C3 H00R0100\narc: C6 H01E0001\narc: CE0 H02W0101\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D2 V02S0001\narc: D3 H00R0000\narc: D6 H00L0100\narc: D7 V02N0401\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 F1\narc: H01W0000 F1\narc: H01W0100 Q1\narc: M0 H02E0601\narc: M1 E1_H02W0001\narc: M2 E1_H02W0601\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F1\narc: S1_V02S0301 F1\narc: S1_V02S0401 Q4\narc: V01S0000 Q1\narc: V01S0100 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1100111100000011\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000100011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R30C51:PLC2\narc: E1_H02E0201 N1_V01S0000\narc: H00R0000 S1_V02N0601\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 S1_V02N0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 N3_V06S0203\narc: N1_V02N0001 W3_H06E0003\narc: N3_V06N0303 W3_H06E0303\narc: S1_V02S0301 W3_H06E0003\narc: W3_H06W0203 E1_H01W0000\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 S1_V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q0\narc: E1_H02E0601 Q4\narc: M0 V00T0000\narc: M2 V00B0100\narc: M4 E1_H02W0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0201 Q2\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R30C52:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 H01E0101\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0203 V06S0203\narc: H00R0000 V02N0601\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0401 N3_V06S0203\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 N1_V02S0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 E1_H02W0001\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 E1_H02W0301\narc: H01W0000 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: N3_V06N0003 W3_H06E0003\narc: W1_H02W0701 W3_H06E0203\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: E1_H02E0201 Q2\narc: E1_H02E0401 Q6\narc: E3_H06E0103 Q2\narc: M0 V00T0100\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0001 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R30C53:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0401 N1_V01S0000\narc: H00L0000 V02S0001\narc: H00R0000 H02W0601\narc: H00R0100 V02N0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0501 N3_V06S0303\narc: N3_V06N0003 S1_V02N0301\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0501 H01E0101\narc: S3_V06S0103 N1_V02S0101\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 N1_V02S0201\narc: V00T0100 V02S0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0401 S1_V02N0401\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: B2 H02E0101\narc: B3 V02S0301\narc: B4 N1_V02S0701\narc: B5 H02E0101\narc: B6 N1_V01S0000\narc: B7 N1_V02S0701\narc: C2 H00L0000\narc: C3 V02S0401\narc: C4 W1_H02E0601\narc: C5 V02S0001\narc: C6 V02S0201\narc: C7 W1_H02E0601\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 H00R0000\narc: D3 W1_H02E0201\narc: D4 V00B0000\narc: D5 N1_V02S0601\narc: D6 H02W0201\narc: D7 V00B0000\narc: E1_H01E0101 Q0\narc: E1_H02E0201 Q0\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: S1_V02S0201 F2\narc: S1_V02S0301 F3\narc: S1_V02S0601 F4\narc: S1_V02S0701 F7\narc: V01S0100 F6\narc: W1_H02W0501 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100001100111100\nword: SLICEC.K1.INIT 1111110011000000\nword: SLICED.K0.INIT 1100001100111100\nword: SLICED.K1.INIT 1111110011000000\nword: SLICEB.K0.INIT 1100001100111100\nword: SLICEB.K1.INIT 1100001100111100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R30C54:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 W1_H02E0201\narc: H00L0100 V02N0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 N1_V02S0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 V02S0201\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02E0201\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0301 W3_H06E0003\narc: B0 V00T0000\narc: B1 V00B0000\narc: B2 H02E0101\narc: B3 N1_V02S0301\narc: B4 V02S0701\narc: B5 H01E0101\narc: B6 N1_V02S0501\narc: B7 V02S0701\narc: C0 N1_V01S0100\narc: C1 H02E0401\narc: C2 V02S0601\narc: C3 W1_H02E0401\narc: C4 W1_H02E0601\narc: C5 N1_V02S0001\narc: C6 W1_H02E0401\narc: C7 W1_H02E0601\narc: D0 V00B0100\narc: D1 N1_V02S0201\narc: D2 H00R0000\narc: D3 V02N0201\narc: D4 V02N0601\narc: D5 H00R0100\narc: D6 H00L0100\narc: D7 V02N0601\narc: E1_H01E0101 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V01N0101 F2\narc: S1_V02S0101 F1\narc: S1_V02S0301 F3\narc: S1_V02S0401 F6\narc: S1_V02S0501 F5\narc: S1_V02S0701 F7\narc: V01S0100 F0\nword: SLICEA.K0.INIT 1100001100111100\nword: SLICEA.K1.INIT 1111110011000000\nword: SLICED.K0.INIT 1100001100111100\nword: SLICED.K1.INIT 1111110011000000\nword: SLICEB.K0.INIT 1100001100111100\nword: SLICEB.K1.INIT 1111110011000000\nword: SLICEC.K0.INIT 1100001100111100\nword: SLICEC.K1.INIT 1111110011000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R30C55:PLC2\narc: E1_H02E0601 V02S0601\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 H01E0101\narc: S1_V02S0401 H06E0203\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02S0001\narc: V00T0100 V02S0501\narc: W1_H02W0101 V06S0103\narc: N3_V06N0303 W3_H06E0303\narc: B3 H00L0000\narc: B6 V00T0000\narc: B7 N1_V02S0701\narc: C2 N1_V01N0001\narc: C3 N1_V01S0100\narc: C6 N1_V02S0001\narc: C7 V02S0201\narc: CE0 H02E0101\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D2 H02E0201\narc: D3 V02S0001\narc: D6 V00B0000\narc: D7 V02S0401\narc: E1_H01E0101 F2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: M0 V00T0100\narc: M4 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q4\narc: S1_V02S0501 F7\narc: S3_V06S0303 F6\narc: V00T0000 Q0\narc: V01S0000 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1100001100111100\nword: SLICED.K1.INIT 1111110011000000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1111110011000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R30C56:PLC2\narc: H00L0100 E1_H02W0301\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 S1_V02N0301\narc: V00T0100 E1_H02W0101\narc: C6 V00T0000\narc: C7 V00T0000\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D6 H01W0000\narc: D7 H01W0000\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: M0 V00B0100\narc: M2 H02E0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q4\narc: S1_V02S0601 F6\narc: V00T0000 Q0\narc: V01S0000 F7\narc: V01S0100 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R30C57:PLC2\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 V01N0101\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: W1_H02W0401 V02S0401\narc: A5 H02W0501\narc: B5 V02N0501\narc: C0 N1_V01S0100\narc: C1 N1_V01S0100\narc: C2 V02S0601\narc: C3 V02S0601\narc: C5 V02N0201\narc: C6 N1_V02S0001\narc: C7 N1_V02S0001\narc: D0 N1_V02S0201\narc: D1 N1_V02S0201\narc: D2 V02S0201\narc: D3 V02S0201\narc: D5 H02W0001\narc: D6 N1_V02S0601\narc: D7 N1_V02S0601\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F0\narc: N3_V06N0303 F5\narc: S1_V02S0101 F3\narc: S1_V02S0301 F1\narc: S1_V02S0601 F6\narc: S1_V02S0701 F7\narc: V01S0100 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000010101010\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R30C58:PLC2\narc: N1_V02N0401 N1_V01S0000\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V01S0100\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0401 W3_H06E0203\n\n.tile R30C59:PLC2\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S3_V06S0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\n\n.tile R30C5:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0601 V02N0601\narc: H00L0100 N1_V02S0101\narc: H00R0000 N1_V02S0401\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 V01N0001\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 E1_H01W0100\narc: V00B0100 V02N0101\narc: V00T0000 H02E0001\narc: V00T0100 H02W0101\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 N1_V02S0701\narc: A1 V02N0701\narc: B1 W1_H02E0301\narc: C1 V02N0601\narc: CE1 H00L0100\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: E1_H01E0001 F0\narc: E1_H02E0201 F0\narc: F0 F5A_SLICE\narc: H01W0100 Q2\narc: M0 H02E0601\narc: M2 V00T0000\narc: M4 E1_H02W0401\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q6\narc: S1_V02S0601 Q4\narc: S3_V06S0303 Q6\narc: V01S0000 Q4\narc: V01S0100 Q4\narc: W1_H02W0401 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000010\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R30C60:PLC2\narc: N3_V06N0203 S3_V06N0203\narc: W1_H02W0501 S3_V06N0303\n\n.tile R30C61:PLC2\narc: S3_V06S0203 N3_V06S0203\n\n.tile R30C62:PLC2\narc: S3_V06S0103 H06E0103\n\n.tile R30C65:PLC2\narc: S3_V06S0103 W3_H06E0103\narc: S3_V06S0303 W3_H06E0303\n\n.tile R30C69:PLC2\narc: S3_V06S0003 N3_V06S0003\n\n.tile R30C6:PLC2\narc: H00L0000 H02E0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02E0601\narc: H00R0100 V02S0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0501 H06W0303\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 V02S0001\narc: V00B0100 V02S0101\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0501 S1_V02N0501\narc: W3_H06W0003 E3_H06W0003\narc: A1 E1_H01E0001\narc: A2 V00B0000\narc: A6 E1_H02W0501\narc: B1 W1_H02E0101\narc: B2 E1_H02W0101\narc: B3 H00R0000\narc: B6 V02S0501\narc: C1 H00L0000\narc: C2 H02E0601\narc: C3 H00L0100\narc: C6 H02W0601\narc: C7 V02S0201\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 V02N0001\narc: D3 V02N0001\narc: D6 V02N0601\narc: D7 H00R0100\narc: E1_H01E0001 Q4\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q4\narc: M0 V00T0000\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: N3_V06N0003 F0\narc: S1_V02S0601 F6\narc: V00T0000 F2\narc: V00T0100 F3\narc: V01S0000 F3\narc: V01S0100 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0101001111111111\nword: SLICEB.K1.INIT 0000000011111100\nword: SLICED.K0.INIT 1100001101000001\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R30C7:PLC2\narc: E1_H02E0301 N1_V02S0301\narc: H00L0100 V02S0301\narc: H00R0100 V02S0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 S1_V02N0101\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H06W0003\narc: S1_V02S0701 V01N0101\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02S0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 N1_V02S0601\narc: A1 H00R0000\narc: A2 V00B0000\narc: B1 E1_H01W0100\narc: B2 E1_H01W0100\narc: C1 V02N0401\narc: C2 V02N0401\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 V00B0100\narc: E1_H01E0101 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H00R0000 Q6\narc: H01W0100 F1\narc: M0 V00T0000\narc: M1 H00R0100\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: V00B0000 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010010100100001\nword: SLICEB.K0.INIT 1010010100100001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R30C8:PLC2\narc: E1_H02E0401 E1_H01W0000\narc: H00L0100 H02E0301\narc: H00R0000 V02S0601\narc: H00R0100 V02N0501\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 H06W0303\narc: V00B0000 V02S0201\narc: V00B0100 E1_H02W0501\narc: V00T0000 E1_H02W0001\narc: V00T0100 H02W0101\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 H01E0101\narc: A1 E1_H01E0001\narc: A2 E1_H01E0001\narc: B1 S1_V02N0101\narc: B2 S1_V02N0301\narc: C1 H00L0100\narc: C2 H00L0100\narc: CE2 N1_V02S0601\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 V00B0100\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q6\narc: E1_H02E0601 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 Q4\narc: M0 V00T0000\narc: M1 H00R0000\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0601 Q6\narc: V01S0000 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000110010101111\nword: SLICEB.K0.INIT 1000110010101111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R30C9:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 H01E0101\narc: H00L0100 N1_V02S0101\narc: H00R0000 V02N0601\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0701 N1_V02S0601\narc: V00B0100 H02W0701\narc: V00T0000 V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0101 V06S0103\narc: W1_H02W0401 E3_H06W0203\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A0 H00L0000\narc: A5 S1_V02N0301\narc: B0 V01N0001\narc: B5 V02S0701\narc: C0 H02W0601\narc: C1 H02E0401\narc: C5 V00T0000\narc: CE1 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V00T0100\narc: D5 E1_H01W0100\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: H00L0000 Q2\narc: H01W0000 Q6\narc: M2 N1_V01N0001\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F5\narc: N1_V02N0301 F1\narc: V01S0000 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1010111100100011\nword: SLICEA.K0.INIT 1010010100100001\nword: SLICEA.K1.INIT 0000111111110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R31C10:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0701 N1_V02S0701\narc: H00R0000 V02S0401\narc: H00R0100 H02E0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 H02E0601\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 V01N0101\narc: V00B0100 N1_V02S0301\narc: V00T0000 N1_V02S0601\narc: V00T0100 V02N0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 V01N0101\narc: W1_H02W0701 V06S0203\narc: W3_H06W0103 E3_H06W0103\narc: A1 E1_H01E0001\narc: A2 V00B0000\narc: B1 N1_V02S0101\narc: B2 H00R0000\narc: C1 H02W0601\narc: C2 H02W0601\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 V00B0100\narc: E1_H01E0001 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 E1_H02W0601\narc: M1 V01S0100\narc: M2 E1_H02W0601\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: V00B0000 Q6\narc: V01S0100 Q4\narc: W1_H02W0301 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1000101011001111\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000101011001111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R31C11:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 E1_H01W0100\narc: H00R0000 H02E0401\narc: H00R0100 W1_H02E0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0501 W1_H02E0501\narc: S1_V02S0201 E3_H06W0103\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02E0701\narc: W1_H02W0601 E1_H02W0301\narc: CE1 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: M2 V00B0000\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R31C12:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0501 E1_H01W0100\narc: H00L0000 E1_H02W0001\narc: H00L0100 N1_V02S0301\narc: H00R0000 H02W0601\narc: H00R0100 H02W0501\narc: N1_V02N0101 H06W0103\narc: N1_V02N0401 H06W0203\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0401 H06W0203\narc: V00B0000 V02S0001\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 V06S0303\narc: W3_H06W0303 E3_H06W0203\narc: A1 H00L0100\narc: A4 V00T0100\narc: A5 H02E0701\narc: A6 H00L0000\narc: A7 S1_V02N0301\narc: B1 H02W0101\narc: B4 H00R0000\narc: B5 H01E0101\narc: B6 W1_H02E0301\narc: B7 W1_H02E0101\narc: C1 N1_V01S0100\narc: C4 E1_H01E0101\narc: C5 H02E0401\narc: C6 S1_V02N0001\narc: C7 S1_V02N0201\narc: CE1 H02E0101\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D4 H02W0001\narc: D5 H00R0100\narc: D6 H02E0201\narc: D7 V00B0000\narc: E1_H01E0001 F7\narc: E1_H01E0101 F0\narc: E3_H06E0203 Q4\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q4\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 E1_H02W0601\narc: M2 H02E0601\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 F6\narc: V01S0100 Q2\narc: W1_H02W0501 F5\narc: W3_H06W0203 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0101001111111111\nword: SLICED.K1.INIT 1010101010001010\nword: SLICEC.K0.INIT 1011000010111011\nword: SLICEC.K1.INIT 1000010000100001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111011101110011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R31C13:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 H02W0001\narc: H00L0100 N1_V02S0101\narc: H00R0100 V02N0501\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 W1_H02E0301\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 V02N0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 H02E0201\narc: V00T0100 V02S0701\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V06S0303\narc: A3 E1_H01E0001\narc: A7 H02E0501\narc: B3 H00L0000\narc: B4 H00R0000\narc: B7 E1_H02W0101\narc: C3 V02S0601\narc: C4 V02S0201\narc: C7 V00T0100\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: D4 N1_V02S0601\narc: D5 V01N0001\narc: D7 H00L0100\narc: E1_H01E0001 Q4\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 Q4\narc: H01W0100 Q0\narc: M0 V00T0000\narc: M4 V00B0000\narc: M6 N1_V01N0101\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 F3\narc: V01S0000 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R31C14:PLC2\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 H02W0201\narc: H00L0100 N1_V02S0101\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H02E0601\narc: S1_V02S0201 H02E0201\narc: S1_V02S0401 E3_H06W0203\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 S1_V02N0201\narc: V00B0100 E1_H02W0701\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0103 E3_H06W0103\narc: A0 H00L0100\narc: A1 E1_H01E0001\narc: A2 H02W0501\narc: A3 V00T0000\narc: A4 E1_H02W0501\narc: A5 V02N0301\narc: A6 H02E0501\narc: A7 S1_V02N0301\narc: B0 V02N0101\narc: B1 V00B0000\narc: B2 V02N0101\narc: B3 H00L0000\narc: B4 E1_H02W0101\narc: B5 S1_V02N0701\narc: B6 V00B0100\narc: B7 S1_V02N0701\narc: C0 H02W0401\narc: C1 H02W0601\narc: C2 H02W0401\narc: C3 H00R0100\narc: C4 V02S0001\narc: C5 V02N0001\narc: C6 V02S0001\narc: C7 V02N0001\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 H02E0201\narc: D2 V01S0100\narc: D3 V02S0201\narc: D4 E1_H02W0001\narc: D5 V02S0601\narc: D6 E1_H02W0001\narc: D7 V02S0601\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: H01W0100 F4\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0101 F7\narc: N1_V02N0401 F6\narc: V00T0000 Q2\narc: V00T0100 F1\narc: V01S0100 F3\narc: W1_H02W0001 Q2\narc: W3_H06W0003 Q0\nword: SLICED.K0.INIT 0101001111111111\nword: SLICED.K1.INIT 1010101010001010\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 1010101010001010\nword: SLICEB.K0.INIT 1111111110000000\nword: SLICEB.K1.INIT 0000000011001010\nword: SLICEA.K0.INIT 1111111110000000\nword: SLICEA.K1.INIT 0000000011001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R31C15:PLC2\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 E3_H06W0203\narc: H00L0000 V02S0201\narc: H00L0100 E1_H02W0301\narc: H00R0000 H02E0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 E3_H06W0003\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 N3_V06S0103\narc: V00B0100 V02N0101\narc: V00T0000 V02N0401\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V02S0601\narc: W3_H06W0103 E1_H02W0101\narc: W3_H06W0203 N3_V06S0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A1 V01N0101\narc: A3 H02E0501\narc: B1 V00T0000\narc: B3 V01N0001\narc: B6 V00B0000\narc: C1 H00R0100\narc: C3 H00L0000\narc: C6 E1_H02W0601\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0001\narc: D3 H00R0000\narc: D6 N1_V02S0601\narc: D7 E1_H02W0201\narc: E1_H01E0001 F0\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q6\narc: M0 V00T0100\narc: M4 H02W0401\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0601 Q4\narc: V00B0000 Q6\narc: V00T0100 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R31C16:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 E3_H06W0303\narc: H00L0000 N1_V02S0001\narc: H00L0100 V02N0101\narc: H00R0100 H02W0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 H06W0203\narc: N1_V02N0601 H01E0001\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 N1_V02S0001\narc: V00B0000 H02W0601\narc: V00T0000 H02W0001\narc: V00T0100 H02W0101\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0701 E1_H02W0601\narc: W3_H06W0103 E3_H06W0003\narc: A1 H00L0000\narc: A7 H00R0000\narc: B1 V02S0101\narc: B7 V00T0000\narc: C1 V02S0401\narc: C7 H02W0401\narc: CE1 H00R0100\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D7 W1_H02E0201\narc: F0 F5A_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: M0 W1_H02E0601\narc: M2 V00T0100\narc: M4 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 F7\narc: N1_V02N0001 F0\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111011101110011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R31C17:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 V06S0203\narc: H00L0000 H02W0201\narc: H00L0100 H02E0101\narc: H00R0000 V02N0601\narc: H00R0100 H02W0701\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0501 N1_V01S0100\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 V02N0001\narc: V00B0100 V02S0101\narc: V00T0000 H02E0201\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 V02N0701\narc: W3_H06W0303 E1_H01W0100\narc: W3_H06W0103 E3_H06W0003\narc: A0 H02W0501\narc: A1 E1_H01E0001\narc: A4 V00B0000\narc: A5 H02E0501\narc: B0 V00T0000\narc: B1 W1_H02E0301\narc: B2 H01W0100\narc: B4 V02N0501\narc: B5 H00L0000\narc: C0 W1_H02E0401\narc: C1 H00R0100\narc: C2 H02E0601\narc: C4 S1_V02N0001\narc: C5 N1_V02S0001\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V00B0100\narc: D2 H00R0000\narc: D3 H02E0201\narc: D4 H02E0001\narc: D5 H00L0100\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q2\narc: M2 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q6\narc: V01S0000 Q0\narc: V01S0100 F1\narc: W1_H02W0001 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111110000000\nword: SLICEA.K1.INIT 0000000011001010\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 1010101010001010\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R31C18:PLC2\narc: E1_H02E0701 E3_H06W0203\narc: H00L0100 E1_H02W0301\narc: H00R0000 V02S0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0501 E1_H01W0100\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 H02W0401\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 V02N0201\narc: V00B0100 V02S0101\narc: V00T0000 H02W0201\narc: V00T0100 V02S0701\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0701 N1_V02S0701\narc: N1_V02N0701 W3_H06E0203\narc: N3_V06N0203 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: B0 H02E0301\narc: B1 H02E0301\narc: B2 H01W0100\narc: B6 V02S0501\narc: C0 H00R0100\narc: C1 H02E0401\narc: C2 E1_H02W0601\narc: C6 E1_H02W0601\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 V02S0001\narc: D2 H00R0000\narc: D3 V00T0100\narc: D6 S1_V02N0601\narc: D7 H02W0001\narc: E1_H01E0101 F1\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q2\narc: M2 V00B0100\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: V01S0000 F0\narc: W1_H02W0601 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000111111\nword: SLICEA.K1.INIT 0000111100110011\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R31C19:PLC2\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V06S0203\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0103 H01E0101\narc: H00R0000 H02W0401\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 N1_V02S0501\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 H02W0001\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 E1_H01W0000\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0103\narc: CE0 W1_H02E0101\narc: CE1 H02W0101\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H02E0001 Q2\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: H01W0100 Q0\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 V00B0000\narc: M2 E1_H02W0601\narc: M4 V00T0000\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N3_V06N0103 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R31C20:PLC2\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 E1_H01W0100\narc: H00L0100 H02E0301\narc: H00R0000 V02N0401\narc: H01W0000 E3_H06W0103\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 H02E0601\narc: V00B0100 H02E0701\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V02N0601\narc: W3_H06W0203 E3_H06W0203\narc: A0 E1_H02W0501\narc: A1 S1_V02N0501\narc: A7 H02E0501\narc: B0 V00T0000\narc: B1 N1_V02S0301\narc: B2 H00L0000\narc: B7 V02N0501\narc: C0 N1_V01N0001\narc: C1 H02E0601\narc: C2 H00R0100\narc: C5 E1_H02W0401\narc: C7 N1_V02S0001\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 E1_H02W0001\narc: D2 S1_V02N0001\narc: D3 V00T0100\narc: D5 H00L0100\narc: D7 V00B0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H00R0100 F5\narc: LSR0 H02W0301\narc: M2 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F7\narc: N1_V02N0001 Q2\narc: N3_V06N0103 Q2\narc: V01S0000 Q2\narc: V01S0100 F1\narc: W3_H06W0103 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000100000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0000000000000111\nword: SLICEA.K1.INIT 0000000000000010\nword: SLICEB.K0.INIT 1111111111110011\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R31C21:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 W1_H02E0001\narc: H00R0000 H02W0401\narc: H00R0100 V02N0701\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 H02W0401\narc: V00B0100 E1_H02W0701\narc: V00T0000 V02N0601\narc: V00T0100 V02S0501\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 E1_H01W0000\narc: W3_H06W0203 E1_H02W0701\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A3 V02S0701\narc: A5 V02N0101\narc: A7 H02E0701\narc: B3 E1_H02W0301\narc: B4 N1_V02S0501\narc: B5 H00R0000\narc: B6 E1_H02W0101\narc: B7 V00B0000\narc: C3 H02W0601\narc: C4 E1_H01E0101\narc: C5 V00T0000\narc: C6 H02E0601\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D3 H02W0201\narc: D4 H00L0100\narc: D5 E1_H02W0001\narc: D6 H00L0100\narc: D7 W1_H02E0201\narc: E1_H01E0101 F5\narc: E1_H02E0601 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0000 F7\narc: H01W0100 Q6\narc: M0 V00B0100\narc: M1 H00R0100\narc: M2 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q4\nword: SLICED.K0.INIT 1111110011110000\nword: SLICED.K1.INIT 0000000011001010\nword: SLICEC.K0.INIT 1111110011110000\nword: SLICEC.K1.INIT 0000000011001010\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0100110011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R31C22:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 E1_H01W0000\narc: E3_H06E0103 N1_V01S0100\narc: H00L0100 V02S0301\narc: H00R0000 H02E0601\narc: H00R0100 W1_H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N1_V02S0601\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 E1_H02W0501\narc: W3_H06W0103 N1_V01S0100\narc: W3_H06W0303 E1_H01W0100\narc: W3_H06W0003 E3_H06W0003\narc: A1 V01N0101\narc: A2 V02S0501\narc: A4 H02E0701\narc: A6 H00R0000\narc: B1 W1_H02E0301\narc: B2 S1_V02N0301\narc: B3 H02W0301\narc: B4 H02E0101\narc: B6 V00T0000\narc: B7 V02S0701\narc: C1 H00L0100\narc: C2 H02E0401\narc: C3 S1_V02N0601\narc: C4 V02N0001\narc: C6 V02S0201\narc: C7 F6\narc: CE1 E1_H02W0101\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: D2 V02S0001\narc: D3 V00B0100\narc: D4 H02E0201\narc: D5 E1_H02W0001\narc: D6 H00R0100\narc: D7 F0\narc: E1_H02E0101 F3\narc: E3_H06E0003 F0\narc: E3_H06E0303 F6\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 Q5\narc: M0 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q3\narc: N1_V02N0001 F0\narc: N1_V02N0601 F6\narc: V00B0000 F4\narc: V00B0100 F7\narc: V00T0000 F2\narc: V01S0000 F7\narc: V01S0100 F3\narc: W1_H02W0201 F0\narc: W1_H02W0601 F6\nword: SLICEB.K0.INIT 0001010100111111\nword: SLICEB.K1.INIT 1111000011111100\nword: SLICED.K0.INIT 0100000011000000\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEC.K0.INIT 0001010100111111\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R31C23:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0101 V02N0101\narc: E1_H02E0401 V06S0203\narc: H01W0100 E3_H06W0303\narc: N1_V02N0301 H02W0301\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 V01N0001\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00T0000 H02E0001\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 N1_V01S0100\narc: W3_H06W0103 E3_H06W0003\narc: C3 N1_V02S0601\narc: C4 V00T0000\narc: C5 H02W0601\narc: CE0 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: D4 H00R0100\narc: D5 V02N0601\narc: E1_H01E0001 Q6\narc: E1_H02E0701 F5\narc: E3_H06E0003 F3\narc: E3_H06E0303 F5\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0100 F3\narc: H00R0100 F5\narc: H01W0000 F5\narc: M0 V00B0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F5\narc: N1_V02N0201 Q0\narc: N3_V06N0003 F3\narc: N3_V06N0303 F5\narc: S1_V02S0101 F3\narc: S1_V02S0701 F5\narc: S3_V06S0003 F3\narc: V00B0100 F5\narc: V01S0000 F4\narc: W1_H02W0501 F5\narc: W1_H02W0601 F4\narc: W1_H02W0701 F5\narc: W3_H06W0003 F3\narc: W3_H06W0303 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 1111000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R31C24:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 V02N0101\narc: E3_H06E0103 S3_V06N0103\narc: H00L0100 N1_V02S0101\narc: H00R0000 H02E0401\narc: H00R0100 V02N0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 H02E0701\narc: N3_V06N0203 E1_H01W0000\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02N0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V01N0101\narc: E1_H02E0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0103 E3_H06W0103\narc: B4 H02W0101\narc: C4 E1_H02W0601\narc: CE0 H00R0100\narc: CE1 V02N0201\narc: CE2 H00R0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D4 E1_H02W0201\narc: D5 H00L0100\narc: E3_H06E0203 Q4\narc: F4 F5C_SLICE\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 H02W0401\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q6\narc: N3_V06N0103 Q2\narc: V01S0100 Q0\narc: W1_H02W0201 Q2\narc: W3_H06W0203 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111111001111\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R31C25:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0701 V06S0203\narc: E3_H06E0103 W1_H02E0101\narc: H00R0100 H02W0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 H01E0001\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 V02S0001\narc: V00T0000 S1_V02N0601\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 V01N0101\narc: W1_H02W0601 E1_H02W0301\narc: H01W0100 W3_H06E0303\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: B1 S1_V02N0101\narc: C1 V02S0601\narc: CE1 W1_H02E0101\narc: CE2 H00R0100\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q6\narc: E3_H06E0303 Q6\narc: F1 F1_SLICE\narc: H01W0000 Q6\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q2\narc: N3_V06N0103 Q2\narc: N3_V06N0203 Q4\narc: S3_V06S0103 F1\narc: V01S0000 Q4\narc: V01S0100 F1\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R31C26:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 V02S0701\narc: H00L0000 N1_V02S0001\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H06E0303\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 H06E0003\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02E0701\narc: V00T0100 V02S0701\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 V02N0701\narc: W3_H06W0303 V06S0303\narc: W3_H06W0203 E3_H06W0103\narc: C1 H00R0100\narc: C3 H00L0000\narc: CE2 W1_H02E0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: D3 V00B0100\narc: E1_H01E0001 F1\narc: E1_H02E0101 F3\narc: E3_H06E0103 F1\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q6\narc: N1_V02N0301 F1\narc: S1_V02S0101 F1\narc: V01S0100 Q4\narc: W1_H02W0101 F1\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R31C27:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 S1_V02N0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S3_V06N0303\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 V02N0001\narc: V00B0100 H02E0701\narc: V00T0100 V02N0501\narc: W1_H02W0101 H01E0101\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 V06S0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A5 N1_V01N0101\narc: B2 H00L0000\narc: B5 H02E0301\narc: C2 V02N0601\narc: C5 H02E0401\narc: CE0 H00L0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 H02W0201\narc: D3 N1_V02S0201\narc: D5 H00R0100\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H00L0000 Q2\narc: M0 V00T0100\narc: M2 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: N3_V06N0303 Q6\narc: S1_V02S0201 Q0\narc: S1_V02S0501 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R31C28:PLC2\narc: E1_H02E0301 V06S0003\narc: E1_H02E0501 E3_H06W0303\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 E1_H02W0201\narc: H00L0100 V02N0301\narc: H00R0000 H02W0401\narc: H00R0100 V02N0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0101 H06W0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 V02S0201\narc: V00B0100 H02W0701\narc: V00T0000 V02N0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0203 E3_H06W0203\narc: A0 H00L0100\narc: A3 N1_V02S0501\narc: B0 V00T0000\narc: B3 V02N0101\narc: C0 H00L0000\narc: C3 V02N0601\narc: CE0 H00R0000\narc: CE2 H02W0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 F2\narc: D3 S1_V02N0001\narc: E1_H02E0001 Q0\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 V00B0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V02N0401 Q4\narc: N3_V06N0003 Q0\narc: W3_H06W0003 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111011101110011\nword: SLICEA.K0.INIT 1111111110001111\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R31C29:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V06S0003\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02S0301\narc: H00R0000 H02W0401\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0401 N3_V06S0203\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0103 H06E0103\narc: V00B0000 V02N0001\narc: V00T0000 N1_V02S0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 S1_V02N0701\narc: E1_H01E0001 W3_H06E0003\narc: H01W0100 W3_H06E0303\narc: S1_V02S0301 W3_H06E0003\narc: W3_H06W0003 N1_V01S0000\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A3 V02N0501\narc: B3 H00L0000\narc: B6 V01S0000\narc: C3 H00L0100\narc: C6 E1_H02W0601\narc: CE0 H00R0000\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D6 V02S0601\narc: D7 H02W0001\narc: E1_H01E0101 Q4\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00T0000\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: V01S0000 Q6\narc: V01S0100 Q6\narc: W1_H02W0601 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R31C2:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0701 V02N0701\narc: H00L0100 H02W0301\narc: H00R0000 V02N0601\narc: H00R0100 V02S0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 E1_H02W0301\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 E3_H06W0103\narc: V00B0000 V02N0001\narc: V00T0000 V02N0401\narc: V00T0100 H02W0301\narc: A2 E1_H02W0701\narc: A3 H00L0100\narc: A5 N1_V01N0101\narc: A6 V00T0100\narc: B2 E1_H02W0101\narc: B3 H00R0100\narc: B5 V00B0100\narc: B6 V02S0501\narc: C1 V02S0401\narc: C2 H02W0601\narc: C3 V02N0401\narc: C5 F6\narc: C6 V00T0000\narc: C7 H02W0401\narc: D1 H02W0001\narc: D2 V02N0201\narc: D3 H00R0000\narc: D5 H01W0000\narc: D6 V02N0601\narc: D7 V00B0000\narc: E1_H01E0001 F4\narc: E1_H01E0101 F2\narc: E1_H02E0401 F4\narc: E1_H02E0601 F4\narc: E3_H06E0203 F4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: M4 E1_H01E0101\narc: N1_V01N0101 F1\narc: V00B0100 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011110000\nword: SLICEB.K0.INIT 1100010011110101\nword: SLICEB.K1.INIT 1100010011110101\nword: SLICED.K0.INIT 1010111100100011\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R31C30:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V06S0203\narc: H00L0000 E1_H02W0001\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02W0701\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 V01N0001\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 H01E0001\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 V01N0101\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N1_V02S0301\narc: V00B0000 H02W0401\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02E0301\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 N3_V06S0303\narc: S1_V02S0701 W3_H06E0203\narc: W3_H06W0003 E1_H02W0301\narc: W3_H06W0103 V06S0103\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A0 H00R0000\narc: A6 H00L0000\narc: A7 V00T0100\narc: B0 H00R0100\narc: B6 S1_V02N0701\narc: B7 V02N0501\narc: C0 S1_V02N0401\narc: C6 H02W0401\narc: C7 S1_V02N0001\narc: CE1 E1_H02W0101\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D6 H02W0201\narc: D7 V00B0000\narc: E3_H06E0103 Q2\narc: F0 F5A_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q2\narc: V00B0100 F7\narc: V01S0100 F6\narc: W1_H02W0201 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000010\nword: SLICED.K1.INIT 0000100000000000\nword: SLICEA.K0.INIT 0000000000010011\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R31C31:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V06S0303\narc: E3_H06E0103 W1_H02E0201\narc: H00L0000 N1_V02S0001\narc: H00L0100 S1_V02N0101\narc: H00R0000 V02N0401\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 H06E0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 S1_V02N0301\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V06S0203\narc: E1_H02E0701 W3_H06E0203\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0103\narc: A1 E1_H02W0701\narc: A3 H02E0501\narc: A5 V02S0301\narc: A6 H00R0000\narc: B1 V00B0000\narc: B3 H00L0000\narc: B5 V02N0501\narc: B6 N1_V01S0000\narc: C1 H00L0100\narc: C2 E1_H02W0401\narc: C3 H00L0100\narc: C5 S1_V02N0201\narc: C6 E1_H01E0101\narc: D1 V00B0100\narc: D2 H02E0001\narc: D3 V00B0100\narc: D5 S1_V02N0401\narc: D6 V02S0401\narc: E1_H01E0001 F1\narc: E1_H01E0101 F3\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M6 V00T0000\narc: S1_V02S0701 F5\narc: V00T0000 F2\narc: W3_H06W0303 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000100000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000001000000000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0000001000000000\nword: SLICED.K0.INIT 0000000000000001\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R31C32:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 V02N0601\narc: H00R0000 H02E0601\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0401\narc: V00B0100 V02N0301\narc: V00T0000 V02S0601\narc: V00T0100 W1_H02E0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: A4 V02S0101\narc: A5 H02W0501\narc: A7 S1_V02N0301\narc: B4 V00B0100\narc: B5 H02E0101\narc: B6 S1_V02N0501\narc: B7 H02E0101\narc: C4 V02S0201\narc: C5 H01E0001\narc: C6 V00T0000\narc: C7 H02E0401\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 H00R0100\narc: D6 H02W0201\narc: D7 H02E0201\narc: E1_H01E0001 Q2\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: E3_H06E0303 F6\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: M0 W1_H02E0601\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0101 Q0\narc: N1_V02N0001 Q2\narc: N3_V06N0003 Q0\narc: W1_H02W0001 Q2\narc: W3_H06W0203 F4\narc: W3_H06W0303 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 0000000000000010\nword: SLICEC.K0.INIT 0000100000000000\nword: SLICEC.K1.INIT 0000000000000111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R31C33:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0203 N3_V06S0203\narc: H00L0000 N1_V02S0001\narc: H00L0100 N1_V02S0301\narc: H00R0000 N1_V02S0601\narc: H01W0000 E3_H06W0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 W1_H02E0601\narc: V00B0000 V02N0001\narc: V00B0100 W1_H02E0701\narc: V00T0100 S1_V02N0701\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 V06S0303\narc: W1_H02W0701 V01N0101\narc: W3_H06W0003 E1_H01W0000\narc: B0 H02W0101\narc: B3 E1_H01W0100\narc: B5 H01E0101\narc: B7 S1_V02N0501\narc: C0 E1_H02W0401\narc: C3 H00L0100\narc: C5 H02E0601\narc: C7 H02E0401\narc: CE0 H00R0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 V00B0100\narc: D3 V00T0100\narc: D5 S1_V02N0401\narc: D7 S1_V02N0401\narc: E1_H01E0101 F0\narc: E1_H02E0201 Q0\narc: E3_H06E0003 Q0\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0101 Q3\narc: N1_V02N0701 Q5\narc: S3_V06S0003 Q3\narc: S3_V06S0303 Q5\narc: V01S0000 Q5\narc: V01S0100 Q7\narc: W3_H06W0203 Q7\narc: W3_H06W0303 Q5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 0000001111001111\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R31C34:PLC2\narc: E1_H02E0401 V02N0401\narc: E3_H06E0303 H01E0101\narc: H00L0000 V02N0201\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02E0401\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0601 H02E0601\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 V01N0101\narc: V00B0000 V02N0001\narc: V00B0100 H02E0501\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 E3_H06W0203\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0201 W3_H06E0103\narc: W3_H06W0303 E1_H01W0100\narc: B2 S1_V02N0101\narc: C2 H00L0000\narc: CE0 H02W0101\narc: CE1 H00L0100\narc: CE2 H00R0000\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 W1_H02E0201\narc: E3_H06E0103 Q2\narc: F2 F5B_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q2\narc: M0 H02W0601\narc: M2 V00B0000\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0103 F2\narc: V01S0000 Q6\narc: V01S0100 Q2\narc: W1_H02W0201 Q2\narc: W3_H06W0203 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000001111001111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R31C35:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0103 V06S0103\narc: H00L0000 V02N0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 N1_V02S0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0601 V01N0001\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S3_V06N0303\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00B0100 E1_H02W0701\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02N0701\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0401 E1_H01W0000\narc: N1_V02N0701 W3_H06E0203\narc: W3_H06W0203 V06S0203\narc: A1 H00L0100\narc: A3 V00T0000\narc: B1 F3\narc: B2 H00R0000\narc: B3 H00R0100\narc: C1 N1_V01N0001\narc: C2 H02W0601\narc: C3 H00L0000\narc: CE0 H02W0101\narc: CE2 V02S0601\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H02W0001\narc: D2 N1_V02S0001\narc: D3 V00T0100\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0100 Q6\narc: M0 V00B0000\narc: M4 H02W0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F2\narc: V01S0100 F3\narc: W1_H02W0601 Q4\narc: W3_H06W0003 Q0\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110010100000\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111110011101110\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\n\n.tile R31C36:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0701 V02S0701\narc: H00L0000 S1_V02N0001\narc: H00R0000 E1_H02W0601\narc: H00R0100 S1_V02N0701\narc: H01W0000 E3_H06W0103\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 S1_V02N0401\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 H06E0003\narc: S3_V06S0003 H06E0003\narc: V00B0000 V02N0201\narc: V00B0100 V02S0101\narc: V00T0000 H02E0201\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0601 E1_H01W0000\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: A1 H02E0701\narc: A7 H00R0000\narc: B1 H02E0301\narc: B7 V02N0501\narc: C1 H02W0401\narc: C6 V01N0101\narc: C7 V00B0100\narc: CE1 H00L0000\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V01S0100\narc: D6 V00B0000\narc: D7 V02N0401\narc: E1_H01E0001 F7\narc: E1_H02E0001 Q2\narc: E3_H06E0203 Q4\narc: F0 F5A_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 W1_H02E0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N3_V06N0003 F0\narc: N3_V06N0203 F7\narc: V01S0000 Q2\narc: V01S0100 F6\narc: W1_H02W0401 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1011000010111011\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000010110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R31C37:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V02N0601\narc: H00L0100 H02W0101\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0601 H02W0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 H06E0103\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02E0301\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 H01E0001\narc: W1_H02W0701 N1_V01S0100\narc: H01W0000 W3_H06E0103\narc: N1_V02N0001 W3_H06E0003\narc: A1 H02E0701\narc: A5 W1_H02E0501\narc: B1 V02N0101\narc: B2 H01W0100\narc: B3 H01W0100\narc: B4 W1_H02E0101\narc: B5 N1_V02S0701\narc: B6 V00B0100\narc: B7 V00B0100\narc: C1 F4\narc: C2 H00R0100\narc: C3 H00L0100\narc: C4 V02N0001\narc: C5 W1_H02E0401\narc: C6 V00T0000\narc: C7 V02N0201\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V00T0100\narc: D2 H00R0000\narc: D3 H02W0001\narc: D4 V00B0000\narc: D5 H00R0100\narc: D6 V02S0601\narc: D7 H02W0001\narc: E3_H06E0003 F3\narc: E3_H06E0203 F7\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M0 W1_H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 F5\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 1100000011001111\nword: SLICEB.K1.INIT 0000000011111100\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1100110010100000\nword: SLICED.K0.INIT 1100000011001111\nword: SLICED.K1.INIT 0000000011111100\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111110011101110\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\n\n.tile R31C38:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V06S0203\narc: H00L0000 H02W0001\narc: H00L0100 V02S0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 S1_V02N0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 H02W0301\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 E1_H02W0601\narc: V00B0000 H02W0401\narc: V00B0100 H02E0501\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02N0501\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0501 V06S0303\narc: E1_H02E0601 W3_H06E0303\narc: S1_V02S0001 W3_H06E0003\narc: B0 V00B0000\narc: B1 V00B0000\narc: B2 H00R0100\narc: B3 H00R0000\narc: B4 E1_H02W0301\narc: B6 V02S0701\narc: B7 V02S0701\narc: C0 N1_V02S0401\narc: C1 V02N0401\narc: C2 N1_V02S0401\narc: C3 V02N0401\narc: C4 V00T0100\narc: C6 V00T0000\narc: C7 V01N0101\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 N1_V01S0000\narc: D1 V02S0201\narc: D2 N1_V02S0001\narc: D3 V02S0201\narc: D4 E1_H02W0201\narc: D5 V02N0601\narc: D6 H02E0201\narc: D7 V02S0401\narc: E1_H01E0001 F4\narc: E3_H06E0003 F3\narc: E3_H06E0103 F1\narc: E3_H06E0203 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: N1_V02N0401 F4\narc: S3_V06S0203 Q4\narc: V01S0000 F7\narc: V01S0100 Q4\narc: W1_H02W0601 Q4\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1100000011001111\nword: SLICED.K1.INIT 0000000011111100\nword: SLICEB.K0.INIT 1100000011001111\nword: SLICEB.K1.INIT 0000000011111100\nword: SLICEA.K0.INIT 1100000011001111\nword: SLICEA.K1.INIT 0000000011111100\nword: SLICEC.K0.INIT 0000110000111111\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R31C39:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 V01N0101\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0601 V02N0601\narc: E3_H06E0203 H01E0001\narc: H00L0000 V02N0001\narc: H00L0100 E1_H02W0101\narc: H00R0100 V02N0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 H02E0101\narc: N1_V02N0501 E1_H01W0100\narc: S1_V02S0101 H02W0101\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02N0101\narc: V00T0000 N1_V02S0601\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V06S0003\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0701 V06S0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A6 V02N0301\narc: A7 E1_H02W0501\narc: B2 V02S0101\narc: B3 V02S0101\narc: B4 H02E0301\narc: B6 V00B0100\narc: B7 S1_V02N0501\narc: C2 V02S0401\narc: C3 H00L0100\narc: C4 H02E0601\narc: C6 V00T0000\narc: C7 V02S0001\narc: CE0 H00R0100\narc: CE1 H00L0000\narc: CLK0 G_HPBX0000\narc: D2 H00R0000\narc: D3 H02E0001\narc: D4 V02N0401\narc: D5 V00B0000\narc: D6 H01W0000\narc: D7 V02S0601\narc: E1_H02E0201 Q0\narc: E3_H06E0003 F3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H01W0000 F7\narc: H01W0100 Q0\narc: M0 W1_H02E0601\narc: M4 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N3_V06N0003 Q0\narc: N3_V06N0303 F6\narc: V01S0100 Q0\narc: W3_H06W0103 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100000011001111\nword: SLICEB.K1.INIT 0000000011111100\nword: SLICED.K0.INIT 0000111100001110\nword: SLICED.K1.INIT 1100010010000000\nword: SLICEC.K0.INIT 1111000000110011\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R31C3:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 E1_H01W0100\narc: H00L0100 N1_V02S0301\narc: N1_V02N0001 E3_H06W0003\narc: N3_V06N0303 H06W0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 N1_V02S0601\narc: V00B0000 V02N0201\narc: W1_H02W0001 V02S0001\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 V02N0601\narc: A0 V02N0501\narc: A1 V02N0501\narc: A2 V02N0701\narc: A3 V02N0701\narc: A4 V02N0101\narc: A6 V02N0101\narc: A7 V02N0101\narc: B0 V01N0001\narc: B1 V01N0001\narc: B2 V01N0001\narc: B3 V01N0001\narc: B4 S1_V02N0701\narc: B6 V00B0000\narc: B7 V00B0000\narc: C0 S1_V02N0401\narc: C1 S1_V02N0401\narc: C2 S1_V02N0601\narc: C3 S1_V02N0601\narc: C4 S1_V02N0201\narc: C6 S1_V02N0001\narc: C7 S1_V02N0001\narc: D0 E1_H02W0201\narc: D1 E1_H02W0201\narc: D2 E1_H02W0201\narc: D3 E1_H02W0201\narc: D4 E1_H02W0201\narc: D6 E1_H02W0201\narc: D7 E1_H02W0201\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 H01E0001\narc: M1 H02E0001\narc: M2 H02E0601\narc: M3 H00L0100\narc: M4 H02E0401\narc: M5 H02E0001\narc: M6 H02E0401\nword: SLICEA.K0.INIT 1111111101111111\nword: SLICEA.K1.INIT 1111111101111111\nword: SLICEC.K0.INIT 1111111101111111\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111111101111111\nword: SLICED.K1.INIT 1111111101111111\nword: SLICEB.K0.INIT 1111111101111111\nword: SLICEB.K1.INIT 1111111101111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R31C40:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 V06S0103\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V06S0303\narc: E1_H02E0701 V02N0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 V06S0103\narc: H00L0000 H02W0201\narc: H00L0100 V02S0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 V02N0701\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 V01N0001\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 N1_V02S0301\narc: V00B0000 H02W0601\narc: V00B0100 H02W0701\narc: V00T0000 H02E0201\narc: V00T0100 N1_V02S0501\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 N3_V06S0303\narc: N3_V06N0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A1 E1_H01E0001\narc: A4 V00T0000\narc: A5 E1_H02W0501\narc: B0 H00R0100\narc: B1 V00B0000\narc: B4 V02S0501\narc: B5 V01S0000\narc: C0 N1_V01N0001\narc: C1 H02E0601\narc: C2 H00L0000\narc: C3 H00L0000\narc: C4 V01N0101\narc: C5 V00B0100\narc: C6 V00T0100\narc: C7 V00T0100\narc: D0 V01S0100\narc: D1 V02N0001\narc: D2 S1_V02N0201\narc: D3 H00R0000\narc: D4 E1_H02W0201\narc: D5 V02S0601\narc: D6 S1_V02N0401\narc: D7 H00L0100\narc: E1_H01E0001 F4\narc: E1_H01E0101 F4\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F0\narc: H01W0100 F2\narc: N1_V01N0001 F1\narc: N1_V01N0101 F6\narc: N1_V02N0101 F3\narc: N1_V02N0501 F7\narc: V01S0000 F4\narc: V01S0100 F5\narc: W3_H06W0203 F4\nword: SLICEA.K0.INIT 0000000011110011\nword: SLICEA.K1.INIT 1001001001110101\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 0000101000001100\nword: SLICEC.K1.INIT 1101000010000000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000111111110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R31C41:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 E3_H06W0303\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0203 V06S0203\narc: H00R0000 N1_V02S0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 H06E0203\narc: S1_V02S0101 H02E0101\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 V02S0201\narc: V00T0000 N1_V02S0401\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V06S0303\narc: E1_H02E0201 W3_H06E0103\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0103 W3_H06E0103\narc: A1 V02N0501\narc: A4 H02W0501\narc: A7 H02W0501\narc: B0 H00R0100\narc: B1 S1_V02N0101\narc: B4 H02W0101\narc: B7 H02W0101\narc: C0 H00L0100\narc: C1 E1_H02W0601\narc: C2 N1_V02S0601\narc: C3 N1_V02S0601\narc: C4 W1_H02E0401\narc: C5 H02E0401\narc: C7 V00T0000\narc: D0 H02E0001\narc: D1 H00R0000\narc: D2 E1_H02W0201\narc: D3 V02N0001\narc: D4 V00B0000\narc: D5 V02S0601\narc: D7 V02S0401\narc: E1_H01E0101 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0000 F7\narc: N1_V01N0001 F5\narc: N1_V01N0101 F3\narc: N3_V06N0003 F0\narc: N3_V06N0303 F5\narc: S1_V02S0501 F5\narc: V01S0000 F4\narc: V01S0100 F2\narc: W1_H02W0701 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100010010000000\nword: SLICEC.K0.INIT 1100010010000000\nword: SLICEC.K1.INIT 1111000000001111\nword: SLICEA.K0.INIT 0000000011110011\nword: SLICEA.K1.INIT 1001010001001111\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000111111110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R31C42:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 N3_V06S0303\narc: H00L0000 H02W0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 V02N0401\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 H01E0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 H02W0701\narc: S3_V06S0303 N1_V02S0501\narc: V00B0000 H02E0401\narc: V00T0000 V02N0601\narc: V00T0100 N1_V02S0701\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V02N0201\narc: E1_H01E0101 W3_H06E0203\narc: N3_V06N0303 W3_H06E0303\narc: A3 H02E0501\narc: A5 N1_V01N0101\narc: A6 N1_V01N0101\narc: B2 H00R0100\narc: B3 S1_V02N0101\narc: B5 H01E0101\narc: B6 H01E0101\narc: B7 V02S0701\narc: C0 N1_V02S0601\narc: C1 N1_V02S0601\narc: C2 N1_V01N0001\narc: C3 H00L0000\narc: C5 H02W0401\narc: C6 H02E0601\narc: C7 V00T0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 H02W0001\narc: D2 V00B0100\narc: D3 V00T0100\narc: D5 N1_V02S0401\narc: D6 H00L0100\narc: D7 V00B0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q7\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F3\narc: N1_V01N0101 Q7\narc: N1_V02N0101 F1\narc: N1_V02N0501 Q7\narc: N3_V06N0203 Q7\narc: S1_V02S0501 Q7\narc: V00B0100 F5\narc: V01S0000 F6\narc: V01S0100 F0\narc: W1_H02W0501 Q7\narc: W3_H06W0103 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100010010000000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 0000000011110011\nword: SLICEB.K1.INIT 1001010001001111\nword: SLICED.K0.INIT 1100010010000000\nword: SLICED.K1.INIT 0000000011000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R31C43:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0203 V01N0001\narc: H00L0000 S1_V02N0201\narc: H00L0100 N1_V02S0301\narc: H00R0100 N1_V02S0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H06E0203\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 H06W0203\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 H01E0001\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02W0501\narc: V00T0000 N1_V02S0601\narc: V01S0100 N3_V06S0303\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0701 W3_H06E0203\narc: W3_H06W0003 V06S0003\narc: A3 S1_V02N0701\narc: A4 H02E0701\narc: A5 V00B0000\narc: B0 N1_V02S0101\narc: B1 N1_V02S0101\narc: B3 V02N0101\narc: B4 H02W0101\narc: B5 H02E0101\narc: B6 V00T0000\narc: B7 V02S0701\narc: C0 E1_H01W0000\narc: C1 H00L0000\narc: C2 S1_V02N0401\narc: C3 H00L0100\narc: C4 E1_H02W0401\narc: C5 E1_H02W0401\narc: C6 V00B0100\narc: C7 V02S0201\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 H02E0201\narc: D2 N1_V02S0001\narc: D3 H02E0001\narc: D4 W1_H02E0001\narc: D5 W1_H02E0001\narc: D6 V02N0601\narc: D7 E1_H01W0100\narc: E1_H01E0001 F6\narc: E3_H06E0003 F0\narc: E3_H06E0103 F2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: LSR0 H02E0301\narc: M0 H02W0601\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F7\narc: N1_V01N0101 F3\narc: N3_V06N0003 F3\narc: S3_V06S0003 F3\narc: V01S0000 F3\narc: W1_H02W0001 F0\narc: W1_H02W0501 F5\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 1010110011001100\nword: SLICEC.K1.INIT 1100101010101010\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0011001000000010\nword: SLICED.K0.INIT 1100000011001111\nword: SLICED.K1.INIT 0000001111110011\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R31C44:PLC2\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 H01E0101\narc: E3_H06E0103 N3_V06S0103\narc: H00L0000 V02N0201\narc: H00L0100 V02S0301\narc: H00R0000 H02W0601\narc: H00R0100 V02S0701\narc: H01W0000 E3_H06W0103\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 H06W0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 H02W0101\narc: S1_V02S0401 H01E0001\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0103 N1_V02S0201\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 W1_H02E0201\narc: V00T0100 H02E0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V02N0601\narc: E1_H02E0301 W3_H06E0003\narc: N3_V06N0103 W3_H06E0103\narc: A3 H02W0501\narc: A6 V02N0101\narc: A7 H00L0000\narc: B3 H02E0301\narc: B4 V02N0701\narc: B5 V02N0701\narc: B6 V00B0000\narc: B7 S1_V02N0701\narc: C3 E1_H02W0401\narc: C4 V00T0100\narc: C5 V00T0000\narc: C6 H02W0401\narc: C7 H02W0401\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 H02E0001\narc: D3 V02S0201\narc: D4 W1_H02E0201\narc: D5 S1_V02N0601\narc: D6 H00L0100\narc: D7 H00L0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q1\narc: E3_H06E0203 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F1\narc: M0 E1_H02W0601\narc: M1 H00R0000\narc: M2 H02E0601\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: N1_V01N0101 F7\narc: S1_V02S0301 F1\narc: V01S0000 F4\narc: W1_H02W0401 F6\nword: SLICED.K0.INIT 1010110011001100\nword: SLICED.K1.INIT 1010110011001100\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1111110000001100\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000100011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R31C45:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 N1_V02S0701\narc: H00L0100 V02N0301\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 V01N0101\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N1_V02S0601\narc: V00B0100 E1_H02W0501\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02W0101\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 E1_H02W0601\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A0 H00L0100\narc: A1 H00L0100\narc: A2 H00L0100\narc: A3 H00L0100\narc: A4 H02W0501\narc: A5 H02E0701\narc: B0 V00T0000\narc: B1 V00T0000\narc: B2 V02S0101\narc: B3 V02S0101\narc: B4 N1_V02S0501\narc: B5 S1_V02N0501\narc: B6 V01S0000\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 H02E0601\narc: C5 V02S0001\narc: C6 E1_H02W0401\narc: CLK1 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 V02N0401\narc: D5 H02W0201\narc: D6 H02W0001\narc: D7 S1_V02N0601\narc: E1_H01E0001 Q3\narc: E1_H01E0101 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q1\narc: H01W0100 F6\narc: LSR1 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: V01S0000 Q2\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R31C46:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V06S0203\narc: E3_H06E0303 V06S0303\narc: H00L0000 H02E0001\narc: H00L0100 V02S0301\narc: H00R0000 H02E0601\narc: H00R0100 V02N0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0701 H02E0701\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 E1_H02W0401\narc: V00B0100 V02S0101\narc: V00T0000 H02W0201\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 S1_V02N0601\narc: H01W0000 W3_H06E0103\narc: S1_V02S0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: A0 H00L0000\narc: A1 H00L0000\narc: A2 N1_V02S0701\narc: A3 E1_H02W0701\narc: A4 V00B0000\narc: A5 W1_H02E0701\narc: B0 H02E0101\narc: B1 H02E0101\narc: B2 H02E0101\narc: B3 H02E0101\narc: B4 V02S0501\narc: B5 E1_H02W0101\narc: B6 V01S0000\narc: C0 H00L0100\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V02S0201\narc: C5 E1_H02W0601\narc: C6 W1_H02E0401\narc: CLK1 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 V02N0401\narc: D5 H00R0100\narc: D6 V02N0601\narc: D7 H02W0001\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F6\narc: E1_H02E0201 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q3\narc: LSR1 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: V01S0000 Q1\nword: SLICED.K0.INIT 0011001100001111\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R31C47:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0303 N3_V06S0303\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02S0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02E0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H06E0103\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 E1_H02W0601\narc: V00B0100 H02E0501\narc: V00T0000 H02W0201\narc: V00T0100 N1_V02S0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V06S0303\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0001 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0303 V06S0303\narc: A0 V02N0501\narc: A1 V02N0501\narc: A2 V02N0501\narc: A3 V02N0501\narc: A4 V00T0000\narc: A5 V02S0301\narc: B0 H02E0101\narc: B1 H02E0101\narc: B2 H02E0101\narc: B3 H02E0101\narc: B4 H00R0000\narc: B5 H02W0101\narc: B6 W1_H02E0301\narc: C0 H02E0601\narc: C1 H02E0601\narc: C2 H02E0601\narc: C3 H02E0601\narc: C4 N1_V02S0201\narc: C5 H02W0601\narc: C6 H02E0401\narc: CLK1 G_HPBX0000\narc: D0 V00B0100\narc: D1 V00B0100\narc: D2 V00B0100\narc: D3 V00B0100\narc: D4 V02N0401\narc: D5 H00R0100\narc: D6 W1_H02E0201\narc: D7 H00L0100\narc: E1_H01E0101 F6\narc: E1_H02E0101 Q1\narc: E3_H06E0003 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q2\narc: LSR1 V00T0100\narc: M6 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: S1_V02S0301 Q3\nword: SLICED.K0.INIT 0011001100001111\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R31C48:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 H02E0001\narc: H00L0100 H02W0301\narc: H00R0000 H02W0401\narc: H00R0100 H02W0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 H06E0103\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 V01N0001\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 W1_H02E0701\narc: V00T0000 H02W0001\narc: V00T0100 V02N0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 S1_V02N0701\narc: N1_V02N0301 W3_H06E0003\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: B0 S1_V02N0301\narc: B2 H02E0301\narc: B4 H02E0101\narc: B7 V00B0100\narc: C0 N1_V02S0401\narc: C2 V02S0401\narc: C4 H02E0401\narc: C6 V02S0201\narc: C7 E1_H01E0101\narc: CE0 H02W0101\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 V01S0100\narc: D2 H00R0000\narc: D3 V02N0001\narc: D4 E1_H02W0001\narc: D5 H00R0100\narc: D6 V02N0401\narc: D7 H00L0100\narc: E1_H01E0101 F2\narc: E1_H02E0401 F4\narc: E3_H06E0003 Q0\narc: E3_H06E0303 F6\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: M0 V00T0100\narc: M2 H02E0601\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q7\narc: N1_V01N0101 Q7\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q7\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1111110000110000\nword: SLICEC.K0.INIT 0000111100110011\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 1111001100000011\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111111111000000\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R31C49:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 V02S0701\narc: H00L0100 V02S0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 H02W0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H06W0303\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N3_V06S0303\narc: V00B0000 V02S0201\narc: V00B0100 E1_H02W0701\narc: V00T0000 N1_V02S0601\narc: V00T0100 N1_V02S0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 S1_V02N0601\narc: N1_V02N0301 W3_H06E0003\narc: S1_V02S0701 W3_H06E0203\narc: W3_H06W0203 N1_V01S0000\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: B0 H02E0301\narc: B2 H00R0100\narc: B6 V02N0501\narc: C0 H02E0601\narc: C2 F6\narc: C3 H00L0000\narc: C6 H02E0401\narc: CE1 E1_H02W0101\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 H02W0201\narc: D2 V02N0001\narc: D3 V02S0001\narc: D6 H00L0100\narc: D7 E1_H02W0001\narc: E1_H01E0101 F0\narc: E1_H02E0301 F3\narc: E3_H06E0103 Q2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q2\narc: H01W0100 Q2\narc: M0 V00B0000\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: S1_V02S0601 Q4\narc: W3_H06W0103 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 1100111100000011\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R31C4:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: H00L0100 N1_V02S0101\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0401 H02W0401\narc: N3_V06N0103 E3_H06W0103\narc: V00B0000 N1_V02S0001\narc: V00B0100 W1_H02E0701\narc: V00T0000 V02S0601\narc: V00T0100 V02N0501\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0701 N1_V01S0100\narc: A1 N1_V02S0701\narc: A2 V00T0000\narc: A5 H02E0501\narc: B1 V02S0301\narc: B2 V02S0101\narc: B5 S1_V02N0501\narc: C1 V02N0601\narc: C2 V02N0601\narc: C5 V00T0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 V00B0100\narc: D5 H00L0100\narc: E1_H01E0101 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: H01W0100 Q6\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M4 H02E0401\narc: M6 E1_H02W0401\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: S1_V02S0601 F4\narc: S3_V06S0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1010010100100001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100010011110101\nword: SLICEB.K0.INIT 1100010011110101\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R31C50:PLC2\narc: H00L0100 V02S0301\narc: H00R0000 V02N0601\narc: H00R0100 H02E0701\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 H02W0601\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 H02W0501\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 E1_H02W0601\narc: V00T0000 V02S0401\narc: V00T0100 H02W0301\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0701 V02S0701\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: N3_V06N0203 W3_H06E0203\narc: S1_V02S0201 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: B2 N1_V02S0101\narc: B5 V02N0701\narc: B6 H01E0101\narc: C2 N1_V01S0100\narc: C3 H02E0601\narc: C4 E1_H01E0101\narc: C5 F6\narc: C6 V00T0100\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 E1_H02W0001\narc: D3 V02S0001\narc: D4 V02S0601\narc: D5 E1_H02W0001\narc: D6 H00L0100\narc: D7 S1_V02N0401\narc: E1_H01E0101 Q5\narc: E3_H06E0003 F3\narc: E3_H06E0203 F4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q5\narc: M0 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q2\narc: N1_V02N0701 Q5\narc: N3_V06N0103 Q2\narc: V01S0100 Q0\narc: W3_H06W0103 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111110000110000\nword: SLICEB.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 1111110000110000\nword: SLICED.K0.INIT 1111110000001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R31C51:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 W1_H02E0201\narc: H00R0000 V02N0601\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 H06E0103\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00B0100 N1_V02S0101\narc: V00T0000 S1_V02N0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 E1_H01W0100\narc: N3_V06N0203 W3_H06E0203\narc: S3_V06S0303 W3_H06E0303\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0303 W3_H06E0303\narc: A3 V02N0701\narc: A5 V00B0000\narc: B3 S1_V02N0101\narc: B5 S1_V02N0501\narc: C3 H00L0000\narc: C5 V00T0100\narc: CE0 H00R0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D3 H02E0201\narc: D5 H02E0201\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: M0 V00B0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0303 F5\narc: S1_V02S0201 Q0\narc: V01S0100 Q6\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1010110000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010110000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R31C52:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V06S0103\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0203 V06S0203\narc: H00L0000 E1_H02W0201\narc: H00R0100 H02E0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0601 H02E0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0203 S3_V06N0103\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N3_V06S0303\narc: V00T0000 E1_H02W0201\narc: V00T0100 N1_V02S0701\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V01N0101\narc: H01W0100 W3_H06E0303\narc: N1_V02N0401 W3_H06E0203\narc: W1_H02W0001 W3_H06E0003\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0103 W3_H06E0103\narc: A3 H02W0501\narc: A7 V02N0301\narc: B3 V02N0101\narc: B7 S1_V02N0701\narc: C3 H00L0000\narc: C7 V00T0000\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 W1_H02E0201\narc: D7 W1_H02E0201\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: V01S0100 Q0\narc: W3_H06W0003 F3\narc: W3_H06W0203 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010110000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010110000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R31C53:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: H00R0000 H02E0601\narc: H00R0100 N1_V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0501 W1_H02E0501\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 H06E0203\narc: N3_V06N0303 H06E0303\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 N1_V01S0100\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 V02N0001\narc: V00B0100 S1_V02N0101\narc: V00T0100 V02N0701\narc: W1_H02W0501 V01N0101\narc: H01W0100 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0203 S3_V06N0203\narc: A7 V02N0101\narc: B5 H00R0000\narc: B7 V00B0100\narc: C5 V02S0001\narc: C7 V02N0201\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D5 N1_V02S0601\narc: D7 E1_H02W0001\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: M0 V00T0100\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: S1_V02S0001 Q2\narc: S1_V02S0201 Q0\narc: S1_V02S0501 F5\narc: W1_H02W0701 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110011000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010110000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R31C54:PLC2\narc: E1_H02E0401 N1_V02S0401\narc: H00L0000 V02N0201\narc: H00R0000 H02W0401\narc: H00R0100 V02N0701\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 N1_V01S0000\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 H06E0303\narc: V00B0000 V02S0001\narc: W1_H02W0201 V02N0201\narc: H01W0100 W3_H06E0303\narc: N3_V06N0003 W3_H06E0003\narc: A1 H02W0501\narc: A3 V01N0101\narc: B1 V02N0301\narc: B3 V02N0101\narc: B4 H00R0000\narc: B5 H00R0000\narc: C1 H00L0000\narc: C3 H00L0000\narc: C4 V02S0201\narc: C5 V02S0201\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: D3 E1_H02W0201\narc: D4 V00B0000\narc: D5 V00B0000\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F3\narc: M6 H02E0401\narc: MUXCLK3 CLK0\narc: S1_V02S0401 Q6\narc: V01S0000 F5\narc: V01S0100 F4\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010110000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010110000000000\nword: SLICEC.K0.INIT 1100001100111100\nword: SLICEC.K1.INIT 1111110011000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R31C55:PLC2\narc: E1_H02E0601 V06S0303\narc: H00L0100 V02S0101\narc: H00R0000 V02S0401\narc: H00R0100 N1_V02S0701\narc: N3_V06N0003 H06W0003\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 N1_V01S0000\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 N1_V02S0301\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 V01N0101\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: N3_V06N0203 W3_H06E0203\narc: W3_H06W0203 S3_V06N0203\narc: W3_H06W0303 S3_V06N0303\narc: C0 V02N0601\narc: C1 V02S0601\narc: C2 H02E0401\narc: C3 H02E0401\narc: C4 V02N0001\narc: C5 V02N0001\narc: C6 V02S0001\narc: C7 V00B0100\narc: D0 H00R0000\narc: D1 V00T0100\narc: D2 V02S0201\narc: D3 V02S0201\narc: D4 V00B0000\narc: D5 V00B0000\narc: D6 H00R0100\narc: D7 H00L0100\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V01N0101 F2\narc: S1_V02S0301 F3\narc: S1_V02S0401 F4\narc: S1_V02S0501 F7\narc: S1_V02S0701 F5\narc: V01S0000 F1\narc: V01S0100 F6\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 1111000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R31C56:PLC2\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 N1_V02S0201\narc: H00R0000 S1_V02N0601\narc: N1_V02N0401 N3_V06S0203\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 E1_H01W0000\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 V02S0001\narc: V00B0100 E1_H02W0701\narc: V00T0100 V02S0501\narc: W1_H02W0101 H01E0101\narc: H01W0000 W3_H06E0103\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0003 S3_V06N0003\narc: C0 H00L0000\narc: C1 N1_V01S0100\narc: C2 N1_V02S0601\narc: C3 H00L0000\narc: C4 V00T0100\narc: C5 V00T0100\narc: C6 N1_V02S0001\narc: C7 H02E0601\narc: D0 H00R0000\narc: D1 V02S0201\narc: D2 V00B0100\narc: D3 H00R0000\narc: D4 V00B0000\narc: D5 V00B0000\narc: D6 N1_V02S0401\narc: D7 V02S0401\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V01N0101 F7\narc: S1_V02S0301 F1\narc: S1_V02S0601 F6\narc: S1_V02S0701 F5\narc: S3_V06S0103 F2\narc: V01S0000 F3\narc: V01S0100 F4\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R31C57:PLC2\narc: E1_H02E0501 H01E0101\narc: H00L0000 S1_V02N0001\narc: H00R0000 S1_V02N0401\narc: N1_V02N0201 E1_H01W0000\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 N3_V06S0003\narc: V00B0100 H02W0701\narc: V00T0100 S1_V02N0501\narc: V01S0100 N3_V06S0303\narc: N1_V02N0501 W3_H06E0303\narc: S3_V06S0303 W3_H06E0303\narc: C0 V02N0601\narc: C1 V02S0401\narc: C2 H00L0000\narc: C3 H02E0601\narc: C4 V02S0001\narc: C5 S1_V02N0001\narc: C7 V02N0001\narc: D0 H00R0000\narc: D1 H02W0201\narc: D2 V00T0100\narc: D3 V00B0100\narc: D4 H02W0201\narc: D5 S1_V02N0601\narc: D7 S1_V02N0401\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 F2\narc: N1_V01N0101 F4\narc: S1_V02S0001 F0\narc: S1_V02S0101 F1\narc: S1_V02S0501 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 1111000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R31C58:PLC2\narc: N1_V02N0201 N3_V06S0103\narc: S1_V02S0501 H02E0501\narc: S3_V06S0103 N1_V02S0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 H01E0101\narc: H01W0000 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0103 S3_V06N0103\n\n.tile R31C59:PLC2\narc: N3_V06N0303 S3_V06N0303\n\n.tile R31C5:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: H00L0000 S1_V02N0201\narc: H00L0100 W1_H02E0101\narc: H00R0000 V02N0401\narc: H00R0100 V02N0701\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H06W0103\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H06E0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 N1_V01S0100\narc: V00B0000 H02W0601\narc: V00B0100 V02N0301\narc: V00T0000 S1_V02N0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 V06S0203\narc: A0 E1_H01E0001\narc: A3 V02N0501\narc: A5 H02E0701\narc: A6 N1_V02S0101\narc: A7 H00R0000\narc: B0 V02S0301\narc: B1 H01W0100\narc: B2 F3\narc: B3 V01N0001\narc: B5 H01E0101\narc: B6 H02E0101\narc: B7 V00B0000\narc: C0 H00L0100\narc: C1 N1_V01S0100\narc: C2 H00R0100\narc: C3 H00L0000\narc: C5 V00T0100\narc: C6 V00B0100\narc: C7 H02E0601\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 H02E0201\narc: D2 V02S0001\narc: D3 V02N0201\narc: D5 H01W0000\narc: D6 E1_H02W0001\narc: D7 E1_H02W0201\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q0\narc: LSR0 V00T0000\narc: M4 E1_H01E0101\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F3\narc: N1_V02N0001 F2\narc: V01S0000 Q0\narc: V01S0100 F4\narc: W1_H02W0101 F1\nword: SLICEA.K0.INIT 1111111100101010\nword: SLICEA.K1.INIT 1100110000001100\nword: SLICEB.K0.INIT 0000001100000000\nword: SLICEB.K1.INIT 0000000010000000\nword: SLICED.K0.INIT 1010001011110011\nword: SLICED.K1.INIT 1100010011110101\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000101000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R31C60:PLC2\narc: S3_V06S0003 N3_V06S0003\n\n.tile R31C62:PLC2\narc: S3_V06S0203 N3_V06S0103\n\n.tile R31C63:PLC2\narc: S3_V06S0103 N3_V06S0003\n\n.tile R31C66:PLC2\narc: S3_V06S0103 N3_V06S0003\n\n.tile R31C69:PLC2\narc: S1_V02S0101 N3_V06S0103\narc: S3_V06S0103 N3_V06S0103\n\n.tile R31C6:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 V06S0303\narc: H00L0100 H02W0101\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0601 E3_H06W0303\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 H06W0103\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02W0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0303 E3_H06W0203\narc: A5 N1_V01S0100\narc: B5 V02S0701\narc: C5 V00B0100\narc: D5 V02S0601\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0000\narc: M1 E1_H02W0001\narc: M2 V00B0000\narc: M3 H00L0100\narc: M4 E1_H02W0401\narc: M5 E1_H02W0001\narc: M6 E1_H02W0401\narc: S1_V02S0101 F3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111111111111\nword: SLICEC.K1.INIT 1011111111111111\nword: SLICED.K0.INIT 1111111111111111\nword: SLICED.K1.INIT 1111111111111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R31C7:PLC2\narc: E1_H02E0301 N1_V02S0301\narc: H00L0000 S1_V02N0201\narc: H00L0100 N1_V02S0301\narc: H00R0000 H02W0601\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0001 H01E0001\narc: S1_V02S0601 N1_V02S0301\narc: V00B0000 V02S0001\narc: V00T0000 H02E0001\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V02N0201\narc: W1_H02W0601 S1_V02N0601\narc: A1 V02S0701\narc: A2 V02S0701\narc: A5 N1_V01N0101\narc: B1 N1_V02S0101\narc: B2 N1_V02S0101\narc: B5 H00R0000\narc: C1 V02N0401\narc: C2 V02N0401\narc: C5 V01N0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 V00T0100\narc: D5 V00B0000\narc: E1_H01E0001 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: M0 E1_H02W0601\narc: M1 H00L0000\narc: M2 E1_H02W0601\narc: M6 V00T0000\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: W1_H02W0501 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1010111100100011\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100010011110101\nword: SLICEB.K0.INIT 1100010011110101\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R31C8:PLC2\narc: E1_H02E0301 E3_H06W0003\narc: H00L0100 H02E0301\narc: H00R0000 V02S0601\narc: H00R0100 H02W0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0501 H02W0501\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 V02S0001\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02S0601\narc: V00T0100 V02S0501\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 V06S0103\narc: W1_H02W0401 H01E0001\narc: W3_H06W0103 E3_H06W0103\narc: A1 V01N0101\narc: A2 V01N0101\narc: B1 V00T0000\narc: B2 H00R0000\narc: C1 V02N0401\narc: C2 V02N0401\narc: CE2 H00R0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 V00B0100\narc: E1_H01E0001 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 H02W0601\narc: M1 H02W0001\narc: M2 H02W0601\narc: M4 V00B0000\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: V01S0100 Q6\narc: W1_H02W0601 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100010011110101\nword: SLICEB.K0.INIT 1100010011110101\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R31C9:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 V06S0303\narc: H00L0000 V02N0001\narc: H00L0100 V02S0101\narc: H00R0000 H02W0401\narc: H00R0100 H02W0501\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 H06W0303\narc: N3_V06N0303 H06W0303\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 E3_H06W0003\narc: V00B0100 S1_V02N0101\narc: V00T0000 H02W0201\narc: V00T0100 V02S0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E1_H01W0000\narc: N1_V02N0001 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: A1 E1_H01E0001\narc: A2 E1_H01E0001\narc: B1 H01W0100\narc: B2 H01W0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: E1_H01E0001 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 Q6\narc: M0 V00T0000\narc: M1 H00L0000\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V02N0301 F1\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100010011110101\nword: SLICEB.K0.INIT 1100010011110101\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R32C10:PLC2\narc: E1_H02E0401 E1_H01W0000\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0501 N3_V06S0303\narc: V00B0000 W1_H02E0601\narc: V00T0000 N1_V02S0601\narc: V00T0100 V02N0501\narc: W1_H02W0501 V06S0303\narc: A1 N1_V02S0501\narc: A2 N1_V02S0501\narc: B1 V00B0000\narc: B2 H02E0301\narc: C1 H00R0100\narc: C2 H00R0100\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 F1\narc: M0 V00T0000\narc: M1 V01S0100\narc: M2 V00T0000\narc: M4 V00T0100\narc: MUXCLK2 CLK0\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100111101000101\nword: SLICEB.K0.INIT 1100111101000101\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R32C11:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0701 V01N0101\narc: H00L0100 N1_V02S0301\narc: H00R0000 H02E0401\narc: H00R0100 V02N0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0601 H06W0303\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02N0101\narc: V00T0000 H02W0201\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0303\narc: A5 S1_V02N0301\narc: A6 H00L0000\narc: A7 N1_V01S0100\narc: B5 V02N0701\narc: B6 E1_H02W0301\narc: B7 E1_H02W0101\narc: C5 F6\narc: C6 V00B0100\narc: C7 E1_H02W0401\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D5 V02N0601\narc: D6 H00L0100\narc: D7 H00R0100\narc: E1_H02E0601 F4\narc: E3_H06E0203 F4\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: LSR0 V00T0000\narc: M0 H02W0601\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V01S0000 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0001010100111111\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R32C12:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 V02N0101\narc: E3_H06E0303 V06S0303\narc: H00L0000 E1_H02W0201\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02E0701\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02N0501\narc: W1_H02W0201 V06S0103\narc: W1_H02W0601 E1_H01W0000\narc: W3_H06W0303 E3_H06W0303\narc: A4 H02W0701\narc: A5 H02W0501\narc: B4 H00L0000\narc: B5 H00R0000\narc: C4 V00T0100\narc: C5 S1_V02N0201\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D4 H02W0201\narc: D5 H02E0001\narc: E1_H01E0101 Q6\narc: E3_H06E0103 Q2\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00B0100\narc: M2 V00B0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q0\narc: N1_V02N0601 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 1010101010001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R32C13:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: H00L0000 W1_H02E0201\narc: H00R0100 H02W0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H02W0101\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 W1_H02E0601\narc: V00B0100 N1_V02S0301\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 E1_H01W0100\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A7 S1_V02N0301\narc: B7 V02N0701\narc: C7 H02W0401\narc: CE0 E1_H02W0101\narc: CE1 H00L0000\narc: CE2 H00R0100\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F7\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q0\narc: M0 V00T0100\narc: M2 V00T0100\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F7\narc: N3_V06N0203 Q4\narc: V01S0000 F7\narc: V01S0100 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111000001111100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R32C14:PLC2\narc: E1_H02E0601 E3_H06W0303\narc: H00L0000 E1_H02W0001\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 E3_H06W0203\narc: S1_V02S0101 V01N0101\narc: S1_V02S0501 E3_H06W0303\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0101\narc: V00T0100 W1_H02E0101\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 E3_H06W0203\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: B0 V00T0000\narc: B4 H00R0000\narc: C0 H02W0601\narc: C4 V02N0001\narc: CE1 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 S1_V02N0201\narc: D4 H02W0001\narc: D5 S1_V02N0601\narc: F0 F5A_SLICE\narc: F4 F5C_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q0\narc: H01W0100 Q4\narc: M0 V00B0000\narc: M2 V00T0100\narc: M4 V00B0100\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: N3_V06N0103 Q2\narc: V00T0000 Q0\narc: V01S0100 Q6\narc: W1_H02W0201 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R32C15:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0701 V02S0701\narc: H00L0000 E1_H02W0001\narc: H00L0100 V02S0301\narc: H00R0000 V02N0401\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 H02E0601\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 H02W0501\narc: V00T0000 H02W0201\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 V06S0103\narc: W1_H02W0601 V02N0601\narc: A3 V00B0000\narc: B3 V02N0301\narc: C3 W1_H02E0401\narc: CE0 H00L0000\narc: CE2 H00L0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: E3_H06E0003 F3\narc: F3 F3_SLICE\narc: M0 H02W0601\narc: M4 V00T0000\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q4\narc: V00B0000 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R32C16:PLC2\narc: E1_H02E0201 V01N0001\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 N1_V02S0201\narc: H00L0100 H02W0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 H02E0701\narc: N1_V02N0101 H02W0101\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 V02N0101\narc: V00T0000 V02N0601\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V02S0601\narc: A1 V01N0101\narc: A3 E1_H01E0001\narc: A7 V02S0101\narc: B1 H00R0100\narc: B3 H02E0101\narc: B7 S1_V02N0501\narc: C1 H00L0100\narc: C3 H00L0100\narc: C7 E1_H01E0101\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D3 H00R0000\narc: D7 H02W0201\narc: E1_H01E0001 Q4\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: M4 V00B0100\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: N1_V02N0401 F6\narc: V01S0000 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000100000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000100000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111011101110011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R32C17:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0501 E1_H01W0100\narc: H00L0000 V02S0001\narc: H00L0100 H02W0101\narc: H00R0000 S1_V02N0601\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H06W0203\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 H06W0203\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 E1_H02W0401\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 N1_V01S0000\narc: W3_H06W0003 V06S0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A5 H02E0701\narc: A7 F5\narc: B0 V02N0101\narc: B5 V01S0000\narc: B6 V02S0501\narc: B7 S1_V02N0501\narc: C0 H00L0100\narc: C5 N1_V02S0201\narc: C6 V00T0100\narc: C7 V00T0000\narc: CE1 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V00B0100\narc: D5 V02N0601\narc: D6 N1_V02S0601\narc: D7 H02E0201\narc: E1_H01E0001 F7\narc: E3_H06E0303 F6\narc: F0 F5A_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: M0 V00B0000\narc: M2 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: V01S0000 Q0\narc: V01S0100 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R32C18:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 H01E0001\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0203 H01E0001\narc: H00L0000 N1_V02S0201\narc: H00R0100 H02W0701\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 V02N0201\narc: V00T0000 H02E0201\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 E1_H02W0701\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A2 V00B0000\narc: A3 V01N0101\narc: A6 S1_V02N0101\narc: B2 N1_V02S0301\narc: B3 E1_H02W0301\narc: B6 H02E0301\narc: C2 H00L0000\narc: C3 H00R0100\narc: C5 V02S0201\narc: C6 S1_V02N0001\narc: CE0 H02E0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D2 V01S0100\narc: D3 H02W0201\narc: D5 V02S0401\narc: D6 S1_V02N0601\narc: E3_H06E0303 Q6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q0\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: N1_V02N0401 Q6\narc: V00B0100 F5\narc: V01S0100 F3\narc: W1_H02W0201 F2\narc: W3_H06W0303 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0000011100000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 1111111110001111\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R32C19:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 N1_V01S0100\narc: H00R0000 E1_H02W0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 E1_H01W0000\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 H06W0103\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0601 H02W0601\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 V02N0201\narc: V00B0100 V02S0301\narc: V00T0000 E1_H02W0201\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: A4 V00T0000\narc: A5 E1_H02W0501\narc: A7 H02E0701\narc: B0 F3\narc: B4 H00R0000\narc: B5 V02S0501\narc: B7 V01S0000\narc: C0 H02E0401\narc: C3 H02W0401\narc: C4 V02N0001\narc: C5 V02S0201\narc: C7 E1_H01E0101\narc: CE0 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 V02S0001\narc: D3 E1_H02W0001\narc: D4 H00R0100\narc: D5 H02W0001\narc: D7 V02N0401\narc: E1_H01E0101 F5\narc: E1_H02E0001 Q0\narc: E3_H06E0003 Q0\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: LSR0 V00B0100\narc: M0 V00T0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V01S0000 F4\narc: W3_H06W0003 Q0\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 0000001000000000\nword: SLICEA.K0.INIT 1111111111001111\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111011101110011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R32C20:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 E3_H06W0203\narc: H00L0100 N1_V02S0101\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0001 H06W0003\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0601 N1_V02S0301\narc: V00B0000 V02S0201\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02W0301\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E1_H02W0301\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E3_H06W0103\narc: A1 H00L0100\narc: B1 H02E0301\narc: C1 E1_H02W0401\narc: C5 N1_V02S0001\narc: C7 V00T0100\narc: CE0 H02W0101\narc: CE1 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0001\narc: D5 V00B0000\narc: D7 V00B0000\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q2\narc: E1_H02E0701 F7\narc: E3_H06E0203 F7\narc: E3_H06E0303 F5\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F1\narc: M2 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F7\narc: N1_V02N0701 F7\narc: N3_V06N0203 F7\narc: N3_V06N0303 F5\narc: S3_V06S0303 F5\narc: V01S0000 F1\narc: W1_H02W0301 Q1\narc: W1_H02W0501 F7\narc: W1_H02W0701 F5\narc: W3_H06W0203 F7\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111000001111100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R32C21:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 E3_H06W0303\narc: H00R0000 H02W0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 H06W0303\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H01E0001\narc: V00B0000 H02W0601\narc: V00B0100 V02N0301\narc: V00T0000 V02S0601\narc: V00T0100 H02W0101\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 H01E0101\narc: W3_H06W0003 V01N0001\narc: W3_H06W0303 V01N0101\narc: E3_H06E0003 W3_H06E0003\narc: B2 H00L0000\narc: B4 H02E0101\narc: B6 V01S0000\narc: C2 H02E0401\narc: C4 H02E0401\narc: C6 E1_H01E0101\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 H00R0000\narc: D3 H02W0201\narc: D4 H02W0001\narc: D5 H02W0201\narc: D6 V00B0000\narc: D7 S1_V02N0601\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q2\narc: H01W0000 Q6\narc: H01W0100 Q4\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0003 Q0\narc: V01S0000 Q6\narc: V01S0100 Q6\narc: W1_H02W0201 Q2\narc: W1_H02W0401 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R32C22:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 V06S0303\narc: E1_H02E0701 V01N0101\narc: H00L0000 V02S0201\narc: H00L0100 N1_V02S0101\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0701 E1_H02W0701\narc: V00B0000 V02S0201\narc: V00T0000 V02S0401\narc: V00T0100 E1_H02W0101\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 E1_H02W0601\narc: W3_H06W0103 N1_V01S0100\narc: W3_H06W0303 V06S0303\narc: B0 V02S0301\narc: B1 V02N0101\narc: B3 F1\narc: C0 H00L0000\narc: C1 H02W0601\narc: C3 H00L0100\narc: C7 V00T0000\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 V02S0001\narc: D2 F0\narc: D3 N1_V01S0000\narc: D7 S1_V02N0601\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F1\narc: M2 V00T0100\narc: M4 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q2\narc: N1_V02N0301 F1\narc: V01S0000 F1\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEA.K0.INIT 0000111100110011\nword: SLICEA.K1.INIT 0011000011110000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 1100110011111100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R32C23:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 W1_H02E0601\narc: H00L0100 S1_V02N0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 E1_H02W0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0303 H06W0303\narc: S1_V02S0501 H06E0303\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 V02S0001\narc: V00T0100 V02S0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 V02S0601\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: A4 W1_H02E0501\narc: A7 H02E0501\narc: B4 V02S0501\narc: B7 E1_H02W0101\narc: C1 H00R0100\narc: C3 N1_V02S0401\narc: C4 V02N0001\narc: C7 E1_H02W0601\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D3 V00T0100\narc: D4 E1_H01W0100\narc: D7 H00L0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 F3\narc: E3_H06E0103 F1\narc: E3_H06E0203 Q4\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q4\narc: LSR1 V00B0000\narc: M4 W1_H02E0401\narc: M6 H02E0401\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V02N0101 F3\narc: N1_V02N0301 F1\narc: N1_V02N0401 F6\narc: N3_V06N0003 F3\narc: N3_V06N0103 F1\narc: V01S0000 F3\narc: W1_H02W0101 F3\narc: W3_H06W0003 F3\narc: W3_H06W0103 F1\narc: W3_H06W0203 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111011101110011\nword: SLICEC.K0.INIT 1111100011111111\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R32C24:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V01N0101\narc: H00L0000 N1_V02S0201\narc: H00L0100 H02W0301\narc: H00R0100 N1_V02S0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 H01E0001\narc: S1_V02S0401 N1_V02S0401\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 H01E0001\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 H02E0201\narc: V00T0100 H02E0101\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 E3_H06W0203\narc: N3_V06N0303 W3_H06E0303\narc: W3_H06W0303 V06S0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A0 H02E0501\narc: A6 H00R0000\narc: A7 W1_H02E0701\narc: B0 W1_H02E0101\narc: B1 V01N0001\narc: B4 H00R0000\narc: B6 V02S0501\narc: B7 S1_V02N0701\narc: C0 H00L0100\narc: C1 H00R0100\narc: C3 H00L0000\narc: C4 H02E0601\narc: C6 V02N0201\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 F0\narc: D3 V02S0201\narc: D4 V02N0601\narc: D5 H02W0201\narc: D6 H02W0001\narc: D7 V00B0000\narc: E1_H01E0001 F7\narc: E1_H01E0101 F6\narc: E1_H02E0401 Q4\narc: E3_H06E0003 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0000 F1\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F3\narc: N1_V01N0101 F3\narc: N3_V06N0003 F3\narc: S1_V02S0301 F3\narc: W1_H02W0101 F3\narc: W3_H06W0003 F3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0101001111111111\nword: SLICED.K1.INIT 1010101010001010\nword: SLICEA.K0.INIT 0001001101011111\nword: SLICEA.K1.INIT 0011111100000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R32C25:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V06S0103\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 N1_V02S0201\narc: H00L0100 H02W0101\narc: H00R0000 H02W0601\narc: H00R0100 H02E0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0501 V01N0101\narc: N1_V02N0701 H02E0701\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0401\narc: V00B0100 E1_H02W0501\narc: V00T0000 N1_V02S0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 H01E0001\narc: S1_V02S0001 W3_H06E0003\narc: W3_H06W0103 V06S0103\narc: W3_H06W0203 N3_V06S0203\narc: E3_H06E0103 W3_H06E0003\narc: A1 E1_H01E0001\narc: A5 V00B0000\narc: B1 V02N0301\narc: B2 H01W0100\narc: B5 H00R0000\narc: B6 V01S0000\narc: C1 H00L0000\narc: C2 V02S0601\narc: C5 V02S0001\narc: C6 E1_H02W0401\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 V02S0201\narc: D3 V00B0100\narc: D5 F0\narc: D6 H00R0100\narc: D7 H00L0100\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F4\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q2\narc: M0 E1_H02W0601\narc: M2 H02E0601\narc: M4 W1_H02E0401\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: N3_V06N0203 F4\narc: V01S0000 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0111000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R32C26:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0103 V01N0101\narc: H00R0000 H02E0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0501 N1_V01S0100\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 H06E0103\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 H06E0103\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 H02W0201\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0501 W3_H06E0303\narc: E1_H02E0701 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0401 W3_H06E0203\narc: S1_V02S0501 W3_H06E0303\narc: S3_V06S0203 W3_H06E0203\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A0 V02S0501\narc: A1 H02E0501\narc: A7 H02W0701\narc: B0 V02N0301\narc: B1 H02W0301\narc: B7 H02W0101\narc: C0 V02N0401\narc: C1 N1_V02S0401\narc: C7 V02S0201\narc: CE0 W1_H02E0101\narc: CE1 N1_V02S0201\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 H01E0101\narc: D7 S1_V02N0601\narc: E1_H01E0001 F0\narc: E1_H01E0101 F1\narc: E1_H02E0201 Q2\narc: E1_H02E0401 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F1\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q1\narc: N3_V06N0303 F6\narc: V01S0100 Q4\narc: W1_H02W0101 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0001010100111111\nword: SLICEA.K1.INIT 0111000001111100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R32C27:PLC2\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 N3_V06S0003\narc: H00L0000 V02S0201\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0003 H06E0003\narc: S1_V02S0001 H02E0001\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 H06E0003\narc: S3_V06S0303 H01E0101\narc: V00B0000 N1_V02S0201\narc: V00T0000 V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 H01E0001\narc: E1_H02E0001 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A1 H00L0000\narc: A4 S1_V02N0101\narc: B1 V02S0301\narc: B4 H02W0101\narc: C1 S1_V02N0401\narc: C4 H02W0401\narc: CE1 E1_H02W0101\narc: CE2 H00R0100\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0201\narc: D4 S1_V02N0601\narc: E1_H01E0101 Q6\narc: E1_H02E0201 F0\narc: E3_H06E0203 Q4\narc: F0 F5A_SLICE\narc: F4 F5C_SLICE\narc: H01W0100 Q4\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N3_V06N0203 Q4\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1111111110001111\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R32C28:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 W1_H02E0601\narc: H00L0000 H02E0201\narc: H00L0100 H02W0301\narc: H00R0000 H02E0601\narc: H00R0100 H02E0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 V01N0001\narc: N3_V06N0303 H06E0303\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\narc: V00B0100 H02E0501\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02N0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 E1_H02W0401\narc: A0 V02S0701\narc: A1 E1_H01E0001\narc: A3 F7\narc: A7 V02N0101\narc: B0 V00T0000\narc: B1 V00T0000\narc: B2 V02S0301\narc: B3 H00L0000\narc: B7 H01E0101\narc: C0 H00R0100\narc: C1 N1_V02S0601\narc: C2 N1_V02S0401\narc: C3 N1_V01N0001\narc: C7 N1_V02S0001\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V00T0100\narc: D2 V00B0100\narc: D3 H02E0001\narc: D7 V02N0601\narc: E1_H01E0001 Q4\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: M4 H02E0401\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F1\narc: N3_V06N0003 F3\narc: N3_V06N0103 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0101001100000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000111100110011\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R32C29:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0601 V02N0601\narc: H00R0000 H02E0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N1_V01S0100\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0301 H06W0003\narc: S1_V02S0601 E1_H01W0000\narc: V00B0000 N1_V02S0201\narc: V00B0100 W1_H02E0701\narc: V00T0000 V02N0401\narc: V00T0100 V02N0501\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 V06S0303\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0101 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A1 H02W0701\narc: B1 H01W0100\narc: B2 V02S0101\narc: B4 V02S0701\narc: B6 V01S0000\narc: C1 H00R0100\narc: C2 E1_H02W0601\narc: C4 V02N0201\narc: C5 N1_V02S0001\narc: C6 E1_H02W0601\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 V02N0001\narc: D3 V01S0100\narc: D4 V02S0601\narc: D5 V02N0601\narc: D6 V02S0401\narc: D7 H01W0000\narc: E1_H01E0101 Q6\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F4\narc: H01W0100 Q4\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F4\narc: N1_V01N0101 Q2\narc: N1_V02N0201 F0\narc: N1_V02N0601 F4\narc: V01S0000 Q6\narc: V01S0100 F4\nword: SLICEC.K0.INIT 0000110011001100\nword: SLICEC.K1.INIT 0000111111111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R32C2:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0701 E3_H06W0203\narc: H00R0000 H02W0601\narc: N1_V02N0001 H06W0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0601 E3_H06W0303\narc: V00B0000 S1_V02N0201\narc: V00B0100 N1_V02S0301\narc: V00T0100 S1_V02N0501\narc: B3 V02N0101\narc: B7 V00B0100\narc: C3 S1_V02N0401\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 V02N0001\narc: D7 H02E0001\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: LSR0 V00B0000\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N3_V06N0003 Q0\narc: S3_V06S0203 F7\narc: V00T0000 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R32C30:PLC2\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V02S0701\narc: H00L0000 H02W0001\narc: H00R0000 S1_V02N0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N3_V06S0303\narc: S1_V02S0501 H01E0101\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 W1_H02E0401\narc: V00B0100 V02N0301\narc: V00T0000 N1_V02S0601\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0701 H01E0101\narc: E1_H02E0101 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: S1_V02S0001 W3_H06E0003\narc: W1_H02W0001 W3_H06E0003\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0303 W3_H06E0303\narc: A1 E1_H01E0001\narc: A4 E1_H01W0000\narc: A7 V02S0301\narc: B0 V02N0101\narc: B1 E1_H02W0101\narc: B4 H02E0101\narc: B7 V02S0501\narc: C0 H00R0100\narc: C1 W1_H02E0601\narc: C4 V00B0100\narc: C7 H02E0601\narc: CE1 H00L0000\narc: CE2 W1_H02E0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 H00R0000\narc: D4 V00B0000\narc: D7 V02N0601\narc: E1_H01E0001 Q4\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F0\narc: M2 V00T0000\narc: M4 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F4\narc: N1_V01N0101 F7\narc: N3_V06N0003 F0\narc: S1_V02S0701 Q7\narc: S3_V06S0203 F7\narc: V00T0100 F1\narc: V01S0000 F7\narc: V01S0100 Q2\narc: W1_H02W0601 F4\narc: W3_H06W0203 F4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0100110001111100\nword: SLICEA.K0.INIT 0011111100000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0010101010101010\nword: SLICEC.K1.INIT 1111111111111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R32C31:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 W1_H02E0501\narc: H00R0000 H02W0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H02E0501\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 H02W0701\narc: S3_V06S0303 H01E0101\narc: V00B0000 V02S0001\narc: V00B0100 N1_V02S0101\narc: V00T0000 S1_V02N0401\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0601 E1_H01W0000\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0003 E1_H01W0000\narc: A4 E1_H02W0501\narc: B1 V00B0000\narc: B4 V02S0701\narc: C0 V02S0401\narc: C1 V02S0401\narc: C4 V00B0100\narc: CE1 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02N0001\narc: D4 H02W0201\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q6\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: H01W0000 F0\narc: H01W0100 F4\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 W1_H02E0401\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: S1_V02S0201 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011110000\nword: SLICEA.K1.INIT 0011111100000000\nword: SLICEC.K0.INIT 0000000100000011\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R32C32:PLC2\narc: H00L0000 H02W0201\narc: H00R0000 V02S0601\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 H02W0201\narc: V00B0000 W1_H02E0601\narc: V00B0100 W1_H02E0701\narc: V00T0000 H02E0001\narc: V00T0100 N1_V02S0501\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 N1_V01S0100\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0103 E1_H01W0100\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00L0000\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: E1_H02E0401 Q6\narc: E3_H06E0003 Q0\narc: E3_H06E0303 Q6\narc: H01W0000 Q4\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: N1_V02N0001 Q0\narc: N3_V06N0103 Q2\narc: V01S0100 Q2\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R32C33:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0103 V06S0103\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 N1_V01S0100\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0203 S1_V02N0401\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0103 N3_V06S0103\narc: V00T0000 H02W0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 V01N0101\narc: N1_V02N0401 W3_H06E0203\narc: S1_V02S0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0203\narc: CE0 N1_V02S0201\narc: CE1 N1_V02S0201\narc: CE2 N1_V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: E1_H02E0601 Q6\narc: H01W0000 Q0\narc: H01W0100 Q4\narc: M0 V00T0000\narc: M2 E1_H02W0601\narc: M4 H02W0401\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: N3_V06N0303 Q6\narc: W3_H06W0103 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R32C34:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0701 N1_V01S0100\narc: H00L0100 H02W0301\narc: H00R0000 N1_V02S0401\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 H06W0103\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0701 H01E0101\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 N1_V02S0601\narc: V00B0100 E1_H02W0501\narc: V00T0000 N1_V02S0601\narc: V00T0100 H02E0301\narc: V01S0100 N3_V06S0303\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 N1_V01S0000\narc: E1_H02E0001 W3_H06E0003\narc: B6 V02N0701\narc: C6 V00B0100\narc: CE0 H02E0101\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D6 H00L0100\narc: D7 H02W0001\narc: E1_H02E0401 Q6\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: E3_H06E0303 F6\narc: F6 F5D_SLICE\narc: H01W0100 Q6\narc: M0 V00B0000\narc: M2 H02E0601\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: N3_V06N0303 Q6\narc: V00B0000 Q4\narc: W1_H02W0001 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000110000111111\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R32C35:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 N3_V06S0003\narc: H00L0000 H02W0001\narc: H00L0100 V02N0101\narc: H00R0100 H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 V01N0001\narc: V00B0100 V02N0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02E0301\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0001 W3_H06E0003\narc: W3_H06W0203 E3_H06W0103\narc: A7 N1_V01N0101\narc: B2 H00R0100\narc: B7 E1_H02W0301\narc: C2 H00L0000\narc: C7 H02W0401\narc: CE0 H02E0101\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D2 V02N0201\narc: D3 V00B0100\narc: D7 N1_V02S0401\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F7\narc: E3_H06E0103 F2\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: M0 H02W0601\narc: M2 V00T0000\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q0\narc: N3_V06N0103 Q2\narc: W1_H02W0601 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0101001100000000\nword: SLICEB.K0.INIT 0000001111001111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R32C36:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 H01E0001\narc: H00L0000 V02N0001\narc: H00L0100 V02N0301\narc: H00R0100 W1_H02E0701\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 E1_H01W0100\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 H06E0303\narc: V00B0000 V02N0201\narc: V00B0100 E1_H02W0501\narc: V00T0000 V02N0601\narc: V00T0100 H02E0301\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0501 W3_H06E0303\narc: A1 E1_H01E0001\narc: A2 E1_H01E0001\narc: A4 H02E0701\narc: A5 H02W0701\narc: B1 V01N0001\narc: B2 V01N0001\narc: B4 N1_V01S0000\narc: B5 H01E0101\narc: C1 H00R0100\narc: C2 H00R0100\narc: C4 V00B0100\narc: C5 H02E0401\narc: CE2 H00L0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: D2 H02E0201\narc: D4 W1_H02E0201\narc: D5 V00B0000\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q5\narc: M0 V00T0000\narc: M1 H02W0001\narc: M2 V00T0000\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: N3_V06N0103 F1\narc: N3_V06N0303 Q5\narc: S1_V02S0501 F5\narc: V01S0000 Q5\narc: V01S0100 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111010100110001\nword: SLICEC.K1.INIT 0000001100100011\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000001001000001\nword: SLICEB.K0.INIT 1000001001000001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R32C37:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0701 N3_V06S0203\narc: H00L0000 W1_H02E0001\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0601 H02W0601\narc: N3_V06N0003 E1_H01W0000\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0401 H02E0401\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02E0401\narc: V00B0100 V02N0101\narc: V00T0100 V02S0501\narc: W1_H02W0301 V02N0301\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0003 V06S0003\narc: W3_H06W0103 E3_H06W0103\narc: A4 V00T0000\narc: A5 V00T0000\narc: B4 H01E0101\narc: B5 H01E0101\narc: C4 V02N0001\narc: C5 V02S0001\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 H02E0001\narc: E1_H01E0101 Q2\narc: E1_H02E0601 Q6\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: M0 V00T0100\narc: M2 V00B0100\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0203 F4\narc: N3_V06N0303 F5\narc: S1_V02S0201 Q2\narc: V00T0000 Q2\narc: V01S0000 Q0\narc: W1_H02W0001 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1101000011011101\nword: SLICEC.K1.INIT 1011000000001011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R32C38:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0601 V02S0601\narc: E3_H06E0203 N1_V01S0000\narc: H00R0000 H02E0601\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H02W0701\narc: N3_V06N0203 S1_V02N0401\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0601 W1_H02E0601\narc: V00B0000 H02E0601\narc: V00B0100 V02S0301\narc: V00T0100 H02W0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 N3_V06S0303\narc: S1_V02S0301 W3_H06E0003\narc: A1 E1_H01E0001\narc: A2 E1_H01E0001\narc: B1 V00B0000\narc: B2 H00R0000\narc: C1 N1_V01S0100\narc: C2 N1_V01S0100\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D2 V02N0001\narc: E1_H01E0001 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 F1\narc: M0 W1_H02E0601\narc: M1 V01S0100\narc: M2 W1_H02E0601\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q4\narc: W1_H02W0401 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000101011001111\nword: SLICEB.K0.INIT 1000101011001111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R32C39:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 N1_V01S0100\narc: H00L0000 S1_V02N0201\narc: H00L0100 V02N0301\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 V01N0001\narc: S3_V06S0203 N3_V06S0103\narc: V00B0100 H02W0701\narc: V00T0000 H02E0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0701 V02S0701\narc: N3_V06N0303 W3_H06E0303\narc: S1_V02S0101 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: CE0 H00L0100\narc: CE1 S1_V02N0201\narc: CE2 H00R0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q6\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 H02W0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: N1_V02N0201 Q2\narc: S1_V02S0401 Q6\narc: V01S0100 Q2\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R32C3:PLC2\narc: H00L0000 H02E0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 N1_V02S0401\narc: H00R0100 V02S0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 H06W0303\narc: N1_V02N0701 V01N0101\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 E1_H02W0601\narc: V00B0100 V02S0101\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02E0101\narc: W1_H02W0601 V06N0303\narc: A1 V02N0501\narc: A2 V01N0101\narc: A3 V00T0000\narc: A5 V02N0101\narc: A6 V02S0301\narc: B1 H00R0100\narc: B2 H01W0100\narc: B3 H00L0000\narc: B5 H00R0000\narc: B6 H02W0101\narc: C1 H02E0401\narc: C2 V02N0401\narc: C3 H00L0100\narc: C5 H02W0401\narc: C6 H02W0601\narc: C7 V02S0001\narc: D1 S1_V02N0201\narc: D2 V00T0100\narc: D3 V00B0100\narc: D5 H02E0201\narc: D6 V02S0601\narc: D7 S1_V02N0601\narc: E1_H02E0701 F5\narc: E3_H06E0103 F2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F0\narc: M0 V00B0000\narc: N1_V01N0001 F0\narc: N1_V02N0201 F0\narc: V00B0000 F6\narc: V01S0000 F3\narc: V01S0100 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000110000100011\nword: SLICED.K0.INIT 1010001011110011\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0000000010000000\nword: SLICEB.K1.INIT 1001000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R32C40:PLC2\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 V02S0601\narc: H00L0000 H02W0201\narc: H00R0100 V02N0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H02W0701\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0701 E1_H02W0701\narc: V00B0100 H02W0701\narc: V00T0000 V02S0601\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 V06S0203\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0701 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A1 V02S0501\narc: A3 H02W0501\narc: A5 H02W0501\narc: A7 E1_H02W0701\narc: B0 S1_V02N0101\narc: B1 H00R0100\narc: B3 V02S0101\narc: B5 H02E0101\narc: B7 H02E0101\narc: C0 F4\narc: C1 H00L0000\narc: C3 E1_H02W0601\narc: C5 H02W0401\narc: C6 E1_H02W0401\narc: C7 H02E0401\narc: D0 V01S0100\narc: D1 N1_V02S0201\narc: D3 V02N0001\narc: D5 H02W0201\narc: D6 V02S0401\narc: D7 H02W0001\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F2\narc: M2 V00B0100\narc: M4 V00B0100\narc: M6 V00T0000\narc: N1_V01N0001 F6\narc: N3_V06N0003 F0\narc: V01S0100 F1\nword: SLICEA.K0.INIT 0000000000000011\nword: SLICEA.K1.INIT 1100010010000000\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 1010101000001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0110101110110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0110101110110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R32C41:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 N3_V06S0303\narc: E3_H06E0003 N3_V06S0003\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 S1_V02N0501\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 H02W0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02N0301\narc: V00T0000 V02S0401\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 V06S0203\narc: E1_H02E0201 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0103 E3_H06W0003\narc: A1 S1_V02N0501\narc: A4 H02E0501\narc: A5 H02E0701\narc: B0 S1_V02N0301\narc: B1 V02N0101\narc: B4 V00B0100\narc: B5 H02W0101\narc: B6 V02N0701\narc: B7 H02E0301\narc: C0 H00L0100\narc: C1 H02E0401\narc: C2 V02S0601\narc: C3 V02S0601\narc: C4 S1_V02N0201\narc: C5 S1_V02N0201\narc: C6 V02N0201\narc: C7 H02W0401\narc: D0 N1_V01S0000\narc: D1 V00T0100\narc: D2 V01S0100\narc: D3 E1_H02W0001\narc: D4 V00B0000\narc: D5 V00B0000\narc: D6 W1_H02E0201\narc: D7 S1_V02N0601\narc: E1_H01E0101 F2\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 F1\narc: H01W0000 F4\narc: H01W0100 F3\narc: M6 V00T0000\narc: N3_V06N0303 F5\narc: V01S0000 F6\narc: V01S0100 F6\narc: W3_H06W0003 F0\nword: SLICEC.K0.INIT 1100101010101010\nword: SLICEC.K1.INIT 1100101010101010\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 0000000011110011\nword: SLICEA.K1.INIT 1001010001001111\nword: SLICED.K0.INIT 1100111111000000\nword: SLICED.K1.INIT 1100110011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R32C42:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V06S0203\narc: H00L0000 V02S0001\narc: H00L0100 H02W0101\narc: H00R0000 N1_V02S0401\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0301 H02E0301\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 H02E0401\narc: V00B0100 V02S0301\narc: V00T0000 V02N0601\narc: V00T0100 V02S0701\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V06S0203\narc: A1 H00L0100\narc: A2 V00T0000\narc: A3 V02S0501\narc: A4 H02W0501\narc: A5 E1_H02W0701\narc: B0 V00B0000\narc: B1 V02N0101\narc: B2 V02N0301\narc: B3 V02S0101\narc: B4 S1_V02N0701\narc: B5 V02N0501\narc: B6 V02N0701\narc: B7 V02N0701\narc: C0 N1_V01N0001\narc: C1 V02N0401\narc: C2 H00L0000\narc: C3 H02W0601\narc: C4 W1_H02E0601\narc: C5 W1_H02E0601\narc: C6 V02N0201\narc: C7 V02N0201\narc: D0 N1_V01S0000\narc: D1 V00T0100\narc: D2 V01S0100\narc: D3 H00R0000\narc: D4 H02E0001\narc: D5 H02E0001\narc: D6 S1_V02N0401\narc: D7 W1_H02E0201\narc: E1_H01E0001 F6\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: M6 V00B0100\narc: N1_V01N0001 F1\narc: N1_V01N0101 F5\narc: V01S0000 F4\narc: V01S0100 F3\narc: W3_H06W0003 F0\narc: W3_H06W0103 F2\nword: SLICEC.K0.INIT 1010110011001100\nword: SLICEC.K1.INIT 1010110011001100\nword: SLICEB.K0.INIT 0000101000001011\nword: SLICEB.K1.INIT 1100010010000000\nword: SLICEA.K0.INIT 0000000011110011\nword: SLICEA.K1.INIT 1001010001001111\nword: SLICED.K0.INIT 1100111111000000\nword: SLICED.K1.INIT 1111110000001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R32C43:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V06S0003\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0203 N3_V06S0203\narc: H00L0000 E1_H02W0001\narc: H00R0000 H02E0401\narc: H00R0100 H02E0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 H02E0701\narc: V00B0000 S1_V02N0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 N1_V01S0000\narc: A3 V00B0000\narc: A5 H02E0501\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 S1_V02N0301\narc: B3 V02N0101\narc: B5 V02N0501\narc: B6 S1_V02N0701\narc: C0 V02S0601\narc: C1 H02E0601\narc: C2 H00L0100\narc: C3 H00L0000\narc: C5 V02S0001\narc: C6 H02W0401\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 H02E0201\narc: D2 H02W0201\narc: D3 V02S0001\narc: D5 S1_V02N0601\narc: D6 N1_V02S0401\narc: D7 V02N0601\narc: E1_H01E0001 F5\narc: E1_H01E0101 Q6\narc: E3_H06E0003 F0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 F3\narc: H01W0000 F0\narc: M0 E1_H02W0601\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: V01S0000 Q6\narc: V01S0100 Q6\narc: W1_H02W0001 F0\narc: W3_H06W0103 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100010010000000\nword: SLICEB.K0.INIT 0000000011110011\nword: SLICEB.K1.INIT 1001001000101111\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111110000001100\nword: SLICED.K0.INIT 1100000011110011\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R32C44:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0003 N1_V01S0000\narc: H00L0100 E1_H02W0101\narc: H00R0000 W1_H02E0401\narc: H00R0100 H02W0501\narc: N1_V02N0101 H06W0103\narc: N1_V02N0301 H06E0003\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0201 H02W0201\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 E1_H02W0401\narc: V00B0100 N1_V02S0101\narc: V00T0000 S1_V02N0601\narc: V00T0100 H02E0101\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0701 H01E0101\narc: W3_H06W0203 N1_V01S0000\narc: E3_H06E0203 W3_H06E0203\narc: B1 V00T0000\narc: B2 V02N0301\narc: B4 V02S0701\narc: B6 V01S0000\narc: C0 N1_V01N0001\narc: C1 F6\narc: C2 N1_V02S0601\narc: C4 E1_H02W0601\narc: C6 V00B0100\narc: CE0 H00R0000\narc: CE1 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 N1_V02S0001\narc: D1 H02E0201\narc: D2 V02S0001\narc: D3 V02N0201\narc: D4 H00R0100\narc: D5 V00B0000\narc: D6 H00L0100\narc: D7 V02N0401\narc: E3_H06E0103 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q1\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 Q1\narc: N1_V02N0201 Q2\narc: N3_V06N0003 F0\narc: N3_V06N0103 Q2\narc: V01S0000 F4\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 1111110000110000\nword: SLICEB.K0.INIT 1100000011110011\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICEC.K0.INIT 0011000000111111\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1111001100000011\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R32C45:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 W1_H02E0501\narc: H00L0100 V02S0301\narc: H00R0000 H02W0401\narc: H00R0100 S1_V02N0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 V01N0001\narc: N3_V06N0103 E1_H01W0100\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0501 N1_V02S0501\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02W0501\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 V02N0701\narc: E3_H06E0003 W3_H06E0003\narc: B0 H02W0301\narc: B2 V02N0301\narc: B4 V02S0501\narc: B6 H02E0101\narc: C0 H00R0100\narc: C2 E1_H01W0000\narc: C4 F6\narc: C5 H02E0601\narc: C6 E1_H01E0101\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 H00R0000\narc: D2 V00T0100\narc: D3 V02N0201\narc: D4 E1_H02W0201\narc: D5 H02E0201\narc: D6 E1_H01W0100\narc: D7 V02S0401\narc: E1_H01E0101 F0\narc: E3_H06E0203 Q4\narc: E3_H06E0303 F5\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q4\narc: M0 E1_H02W0601\narc: M2 V00B0000\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: N1_V02N0001 F2\nword: SLICEC.K0.INIT 1111110000110000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 0000111100110011\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1100111100000011\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 0011001100001111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R32C46:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0303 N3_V06S0303\narc: H00L0100 V02N0101\narc: H00R0000 N1_V02S0401\narc: H00R0100 N1_V02S0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 N3_V06S0203\narc: V00B0000 V02N0201\narc: V00B0100 V02S0301\narc: V00T0000 H02W0001\narc: V00T0100 H02W0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 S1_V02N0601\narc: E3_H06E0003 W3_H06E0303\narc: A3 V00B0000\narc: A4 H02E0501\narc: B3 V02S0301\narc: B4 V02N0701\narc: B7 V02S0701\narc: C3 N1_V01N0001\narc: C4 E1_H01E0101\narc: C5 V00T0000\narc: C7 N1_V02S0001\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 H00R0000\narc: D4 H02E0201\narc: D5 S1_V02N0401\narc: D7 S1_V02N0601\narc: E1_H01E0101 F5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F1\narc: M0 V00T0100\narc: M1 H00L0100\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: N1_V01N0101 F4\narc: N3_V06N0103 F1\narc: V01S0000 Q1\narc: W1_H02W0101 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 0000100100000000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000110010001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R32C47:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 S1_V02N0601\narc: H00L0100 E1_H02W0301\narc: H00R0000 H02W0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0103 H06W0103\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H02E0201\narc: S1_V02S0401 V01N0001\narc: S1_V02S0701 H06E0203\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N3_V06S0203\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 V06S0103\narc: W1_H02W0601 N1_V02S0601\narc: S1_V02S0501 W3_H06E0303\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: A1 H02W0701\narc: A3 H00L0100\narc: A5 N1_V01N0101\narc: A6 H02E0501\narc: A7 H00R0000\narc: B1 V02S0101\narc: B3 V02N0101\narc: B5 H02E0101\narc: B6 W1_H02E0301\narc: B7 V02S0701\narc: C1 H00R0100\narc: C3 V02N0401\narc: C5 V01N0101\narc: C6 E1_H01E0101\narc: C7 V02N0001\narc: D1 E1_H02W0001\narc: D3 W1_H02E0001\narc: D5 S1_V02N0401\narc: D6 F0\narc: D7 V02N0601\narc: E1_H01E0101 F7\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M0 V00T0100\narc: M4 E1_H02W0401\narc: N1_V01N0101 F6\narc: N3_V06N0203 F4\narc: V00T0100 F3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000010000100001\nword: SLICED.K0.INIT 1001000000000000\nword: SLICED.K1.INIT 1000010000100001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000001001000001\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R32C48:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 W1_H02E0701\narc: H00L0100 N1_V02S0301\narc: H00R0000 H02E0401\narc: H00R0100 N1_V02S0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0203 H06E0203\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 W1_H02E0601\narc: V00B0100 W1_H02E0701\narc: V00T0000 N1_V02S0601\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 N1_V02S0701\narc: N3_V06N0303 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0203 V06S0203\narc: E3_H06E0303 W3_H06E0303\narc: A3 H00L0100\narc: A7 S1_V02N0301\narc: B3 V02S0101\narc: B4 V01S0000\narc: B7 V00B0000\narc: C3 W1_H02E0401\narc: C4 V00T0000\narc: C7 N1_V02S0001\narc: CE0 H00R0000\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: D2 V02S0201\narc: D3 V02N0001\narc: D4 H00R0100\narc: D5 V02N0401\narc: D7 H01W0000\narc: E1_H01E0001 F7\narc: E3_H06E0203 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q4\narc: M0 H02E0601\narc: M1 W1_H02E0001\narc: M2 H02E0601\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q1\narc: N1_V02N0101 F1\narc: N1_V02N0301 Q1\narc: N3_V06N0103 F1\narc: W1_H02W0301 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0010001100000001\nword: SLICEC.K0.INIT 1100000011110011\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1100000011001000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R32C49:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0401 N1_V01S0000\narc: H00L0100 V02S0101\narc: H00R0000 V02N0401\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H02E0601\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0303 E1_H01W0100\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 N1_V01S0000\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00B0100 V02N0301\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02S0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 V06S0203\narc: W1_H02W0701 V02S0701\narc: N1_V02N0701 W3_H06E0203\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: A3 V00T0000\narc: B3 S1_V02N0101\narc: C3 H00L0100\narc: CE0 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 W1_H02E0201\narc: F3 F3_SLICE\narc: M0 V00T0100\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: S1_V02S0001 Q0\narc: V01S0000 Q4\narc: W3_H06W0003 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010110000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R32C4:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0701 V01N0101\narc: H00L0100 V02N0301\narc: H00R0100 S1_V02N0501\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0103 H06W0103\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 E1_H02W0601\narc: V00T0000 V02S0601\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 E1_H02W0601\narc: A1 H02E0701\narc: B1 E1_H01W0100\narc: C1 H00L0100\narc: D1 V00T0100\narc: E1_H02E0301 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 E1_H02W0001\narc: M2 V00T0000\narc: M3 H00R0100\narc: M4 V00T0000\narc: M5 E1_H02W0001\narc: M6 V00T0000\narc: N3_V06N0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R32C50:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0501 V02S0501\narc: E3_H06E0203 V06S0203\narc: H00L0100 H02W0101\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0203 H06W0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 H06W0103\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 V01N0101\narc: S3_V06S0103 N1_V01S0100\narc: V00T0000 E1_H02W0201\narc: V00T0100 S1_V02N0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 N1_V02S0701\narc: N1_V02N0301 W3_H06E0003\narc: A3 H00L0100\narc: B1 E1_H02W0301\narc: B3 S1_V02N0301\narc: B5 H02W0301\narc: B7 V00T0000\narc: C1 E1_H02W0401\narc: C3 H02E0401\narc: C5 S1_V02N0201\narc: C7 V00T0100\narc: D1 H02E0201\narc: D3 V02S0201\narc: D5 H02E0201\narc: D7 H02E0201\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F5\narc: W3_H06W0003 F3\narc: W3_H06W0103 F1\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0101001100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0011001100001111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0011001100001111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011001100001111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R32C51:PLC2\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0203 N3_V06S0203\narc: H00L0000 W1_H02E0001\narc: H00R0000 V02N0601\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 N1_V02S0001\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02S0201\narc: V00T0000 V02S0601\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0601 V06S0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: A0 H00L0000\narc: A2 V02S0501\narc: A3 V00T0000\narc: A4 V00B0000\narc: A5 V02S0101\narc: A6 N1_V01S0100\narc: A7 N1_V02S0101\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q5\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0203 Q7\narc: W1_H02W0101 Q3\narc: W1_H02W0201 Q2\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 1010101010101010\nword: SLICED.K1.INIT 1010101010101010\nword: SLICEC.K0.INIT 1010101010101010\nword: SLICEC.K1.INIT 1010101010101010\nword: SLICEB.K0.INIT 1010101010101010\nword: SLICEB.K1.INIT 1010101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R32C52:PLC2\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 V02S0701\narc: H00L0000 N1_V02S0001\narc: H00R0000 V02N0601\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 E1_H01W0100\narc: N3_V06N0003 H06E0003\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 E1_H02W0701\narc: V00B0000 V02S0001\narc: V00T0000 H02E0201\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 S1_V02N0401\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0003 V01N0001\narc: A0 W1_H02E0501\narc: A1 H02E0701\narc: A2 H02E0501\narc: A3 V00B0000\narc: A4 N1_V01S0100\narc: A5 V00T0000\narc: A6 N1_V02S0301\narc: A7 H00L0000\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q0\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: V01S0000 Q6\narc: V01S0100 Q7\narc: W1_H02W0301 Q1\narc: W1_H02W0701 Q5\nword: SLICED.K0.INIT 1010101010101010\nword: SLICED.K1.INIT 1010101010101010\nword: SLICEC.K0.INIT 1010101010101010\nword: SLICEC.K1.INIT 1010101010101010\nword: SLICEB.K0.INIT 1010101010101010\nword: SLICEB.K1.INIT 1010101010101010\nword: SLICEA.K0.INIT 1010101010101010\nword: SLICEA.K1.INIT 1010101010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R32C53:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0401 V06S0203\narc: E1_H02E0701 V06S0203\narc: H00L0000 S1_V02N0201\narc: H00L0100 N1_V02S0301\narc: H00R0100 V02S0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H02E0401\narc: N1_V02N0701 H06E0203\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 H06W0303\narc: S3_V06S0103 H06W0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02E0501\narc: V00T0000 N1_V02S0601\narc: V00T0100 V02N0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 E1_H02W0701\narc: N1_V02N0301 W3_H06E0003\narc: W3_H06W0103 E1_H02W0101\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: A0 N1_V02S0501\narc: A1 H02E0701\narc: A2 H00L0100\narc: A3 V00B0000\narc: A4 V02S0101\narc: A5 V00T0000\narc: A6 V00T0100\narc: A7 V02S0301\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 H00L0000\narc: B6 N1_V02S0701\narc: B7 V02N0501\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q4\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: N3_V06N0003 Q3\narc: V01S0100 Q5\narc: W1_H02W0101 Q1\narc: W3_H06W0203 Q7\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 1010101010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 1010101010101010\nword: SLICEA.K1.INIT 1010101010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R32C54:PLC2\narc: H00L0000 V02S0001\narc: H00L0100 H02W0301\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 H02E0701\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 H02W0201\narc: S1_V02S0601 H06W0303\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 S1_V02N0701\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0701 E1_H02W0601\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0003 E1_H02W0301\narc: A0 V02S0501\narc: A1 V02S0701\narc: A2 V00B0000\narc: A3 H00L0100\narc: A4 V00T0100\narc: A5 V00T0000\narc: A6 N1_V01S0100\narc: A7 V02S0301\narc: B0 N1_V02S0101\narc: B1 S1_V02N0101\narc: B2 H00R0100\narc: B3 H00L0000\narc: B4 N1_V02S0701\narc: B5 S1_V02N0501\narc: B6 V00B0100\narc: B7 N1_V01S0000\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: E1_H02E0501 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q2\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q6\narc: S1_V02S0501 Q7\narc: V01S0100 Q3\narc: W1_H02W0101 Q1\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R32C55:PLC2\narc: E1_H02E0101 V02N0101\narc: H00L0000 V02S0201\narc: H00L0100 H02W0101\narc: H00R0000 W1_H02E0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0501 H02E0501\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 E1_H02W0601\narc: V00T0000 V02S0401\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0701 E1_H01W0100\narc: N3_V06N0003 W3_H06E0003\narc: W3_H06W0003 E1_H01W0000\narc: A0 V02N0701\narc: A1 S1_V02N0501\narc: A2 N1_V02S0701\narc: A3 H00L0100\narc: A4 V00T0000\narc: A5 N1_V01S0100\narc: A6 S1_V02N0301\narc: A7 V02S0101\narc: B0 H00R0100\narc: B1 V00B0000\narc: B2 H00L0000\narc: B3 V02S0301\narc: B4 V02S0501\narc: B5 V02S0701\narc: B6 N1_V01S0000\narc: B7 V02N0501\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 H00R0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q1\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: W1_H02W0101 Q3\narc: W1_H02W0501 Q5\narc: W1_H02W0601 Q4\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q7\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R32C56:PLC2\narc: H00L0000 V02S0001\narc: H00R0000 V02S0601\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0103 H06E0103\narc: S1_V02S0201 V01N0001\narc: V00B0000 V02S0201\narc: V00T0000 N1_V02S0601\narc: V01S0000 N3_V06S0103\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0401 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: A0 N1_V02S0701\narc: A1 H00R0000\narc: A2 V01N0101\narc: A3 E1_H02W0501\narc: A4 V00T0000\narc: A5 V02N0301\narc: A6 N1_V01S0100\narc: A7 V02S0101\narc: B0 N1_V02S0301\narc: B1 H02W0301\narc: B2 V02S0301\narc: B3 V02N0101\narc: B4 N1_V01S0000\narc: B5 H00L0000\narc: B6 V00B0000\narc: B7 V02S0701\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q3\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W1_H02W0301 Q1\narc: W1_H02W0601 Q6\narc: W1_H02W0701 Q5\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q7\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R32C57:PLC2\narc: H00L0000 V02S0201\narc: H00R0000 V02S0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0301 N3_V06S0003\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N1_V01S0100\narc: V00B0000 V02S0001\narc: V00T0000 N1_V02S0601\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0601 V06S0303\narc: E3_H06E0003 W3_H06E0003\narc: A0 V02S0701\narc: A1 N1_V02S0501\narc: A2 V00B0000\narc: A3 V00T0000\narc: A4 V00T0000\narc: A5 V00T0000\narc: B0 H00R0100\narc: B1 N1_V02S0101\narc: B2 V02S0101\narc: B3 V02S0301\narc: B4 N1_V02S0701\narc: B5 N1_V02S0701\narc: CE0 V02S0201\narc: CE1 H00R0000\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q3\narc: H01W0100 Q1\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R32C58:PLC2\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0501 N3_V06S0303\narc: S3_V06S0003 N3_V06S0303\narc: W1_H02W0501 V02S0501\n\n.tile R32C59:PLC2\narc: W3_H06W0303 E3_H06W0203\n\n.tile R32C5:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 S1_V02N0001\narc: H00R0000 S1_V02N0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 E3_H06W0303\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02S0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 E3_H06W0303\narc: W3_H06W0003 E3_H06W0303\narc: A1 H02E0701\narc: A4 V00T0000\narc: A5 V00T0000\narc: A7 N1_V01N0101\narc: B1 H00R0100\narc: B4 H00R0000\narc: B5 V02S0501\narc: B7 V02N0501\narc: C1 H02W0401\narc: C4 H02W0601\narc: C5 N1_V02S0201\narc: C7 E1_H02W0401\narc: CE1 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D4 V00B0000\narc: D5 H02E0201\narc: D7 V00B0000\narc: E1_H01E0001 F4\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F5\narc: M2 V00B0100\narc: M6 V00T0100\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F6\narc: N1_V01N0101 Q2\narc: V00T0000 Q2\narc: V00T0100 F1\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000010000100001\nword: SLICEC.K0.INIT 1010001011110011\nword: SLICEC.K1.INIT 1100010011110101\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000001001000001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R32C60:PLC2\narc: S3_V06S0103 N3_V06S0003\n\n.tile R32C63:PLC2\narc: S3_V06S0103 N3_V06S0103\narc: E3_H06E0003 W3_H06E0003\n\n.tile R32C65:PLC2\narc: W3_H06W0203 E3_H06W0203\n\n.tile R32C66:PLC2\narc: S3_V06S0203 N3_V06S0103\n\n.tile R32C69:PLC2\narc: E1_H02E0101 V02S0101\narc: S3_V06S0003 W3_H06E0003\n\n.tile R32C6:PLC2\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 V02S0001\narc: H00L0100 V02S0101\narc: H00R0000 H02E0401\narc: N1_V02N0101 H06E0103\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 N1_V02S0501\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0601\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02N0401\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E3_H06W0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0303\narc: A1 V01N0101\narc: A2 S1_V02N0701\narc: A3 V01N0101\narc: A4 V02N0101\narc: A6 E1_H02W0701\narc: A7 N1_V01N0101\narc: B1 V00B0000\narc: B2 H00R0000\narc: B3 H00R0000\narc: B4 H00L0000\narc: B5 V01S0000\narc: B6 V00B0100\narc: B7 H02W0101\narc: C1 E1_H01W0000\narc: C2 E1_H01W0000\narc: C3 E1_H01W0000\narc: C4 S1_V02N0201\narc: C5 H02W0601\narc: C6 E1_H02W0601\narc: C7 E1_H02W0401\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: D2 E1_H02W0201\narc: D3 E1_H02W0201\narc: D4 S1_V02N0401\narc: D5 E1_H02W0201\narc: D6 H00R0100\narc: D7 H00L0100\narc: E1_H01E0101 F7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0100 F7\narc: LSR0 H02E0501\narc: M0 V00T0000\narc: M1 H02E0001\narc: M2 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 F6\narc: S1_V02S0601 Q4\narc: V01S0000 Q4\narc: V01S0100 Q4\narc: W1_H02W0101 F1\nword: SLICEC.K0.INIT 1111111100101010\nword: SLICEC.K1.INIT 1100000011001100\nword: SLICED.K0.INIT 1001000000000000\nword: SLICED.K1.INIT 0000000010000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010111100100011\nword: SLICEB.K0.INIT 1010111100100011\nword: SLICEB.K1.INIT 1010111100100011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R32C70:PLC2\narc: E1_H02E0301 S1_V02N0301\n\n.tile R32C7:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V06S0103\narc: E1_H02E0401 N3_V06S0203\narc: H00L0000 S1_V02N0001\narc: H00R0000 H02E0601\narc: H01W0000 E3_H06W0103\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 N3_V06S0203\narc: S1_V02S0301 E3_H06W0003\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02W0001\narc: V00T0100 H02W0101\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E1_H01W0000\narc: W3_H06W0203 E3_H06W0103\narc: A1 V02N0501\narc: A2 V02N0701\narc: A3 V02N0701\narc: B1 V02N0301\narc: B2 V02N0101\narc: B3 V02N0301\narc: C1 H00L0000\narc: C2 H00L0000\narc: C3 H00L0000\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D2 V02S0001\narc: D3 V02S0001\narc: E1_H01E0101 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 V00T0100\narc: M1 H00R0000\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0103 F1\narc: S1_V02S0401 Q6\narc: V01S0000 Q4\narc: V01S0100 Q6\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111101111111\nword: SLICEB.K0.INIT 1111111101111111\nword: SLICEB.K1.INIT 1111111101111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R32C8:PLC2\narc: E1_H02E0001 H01E0001\narc: H00L0100 S1_V02N0301\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H02E0401\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0401 H01E0001\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 V01N0101\narc: V00B0000 V02S0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02W0301\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0701 H01E0101\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0203\narc: A3 V00B0000\narc: B3 V02S0301\narc: C3 H02W0601\narc: CE2 H02E0101\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: E1_H01E0101 Q6\narc: E1_H02E0601 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q4\narc: M0 V00T0000\narc: M1 H00L0100\narc: M2 V00T0000\narc: M4 H02W0401\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: N3_V06N0103 F1\narc: V01S0000 Q4\narc: V01S0100 Q4\narc: W1_H02W0101 F1\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 0111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R32C9:PLC2\narc: E1_H02E0301 H01E0101\narc: H00R0100 V02S0701\narc: N1_V02N0301 N1_V01S0100\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 H06W0303\narc: V00B0000 V02N0001\narc: V00B0100 H02W0501\narc: V00T0000 W1_H02E0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 E1_H01W0000\narc: A6 H00R0000\narc: B6 V02N0501\narc: C6 V00T0000\narc: C7 E1_H01E0101\narc: CE1 S1_V02N0201\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D6 H02E0001\narc: D7 W1_H02E0001\narc: E1_H01E0101 Q4\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0000 F6\narc: M2 V00B0100\narc: M4 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: N1_V02N0001 Q2\narc: S1_V02S0401 Q4\narc: V01S0000 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1100010011110101\nword: SLICED.K1.INIT 1111000000001111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R33C10:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: N1_V02N0501 H02W0501\narc: W1_H02W0101 V01N0101\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 H01E0001\n\n.tile R33C11:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 E3_H06W0303\narc: H00R0000 V02S0601\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 E1_H02W0701\narc: V00B0000 E1_H02W0401\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 S1_V02N0601\narc: CE0 N1_V02S0201\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: H01W0100 Q0\narc: M0 E1_H02W0601\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R33C12:PLC2\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 N3_V06S0303\narc: H00L0000 S1_V02N0201\narc: H00R0000 N1_V02S0401\narc: H00R0100 H02W0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 N3_V06S0303\narc: V00B0000 H02E0601\narc: V00B0100 H02E0501\narc: V00T0000 V02N0401\narc: V01S0000 N3_V06S0103\narc: A1 E1_H01E0001\narc: A3 E1_H02W0501\narc: A6 V02N0301\narc: A7 W1_H02E0501\narc: B1 H00R0100\narc: B3 H00R0000\narc: B6 S1_V02N0501\narc: B7 E1_H02W0301\narc: C1 F6\narc: C3 H00L0000\narc: C6 V00B0100\narc: C7 E1_H02W0401\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 V01S0100\narc: D3 H02W0201\narc: D6 H02W0001\narc: D7 V00B0000\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q4\narc: E1_H02E0201 F0\narc: E3_H06E0003 F0\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M0 E1_H02W0601\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F3\narc: V01S0100 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000100000\nword: SLICED.K0.INIT 0001010100111111\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R33C13:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V06S0203\narc: H00L0100 V02N0101\narc: H00R0100 V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 V02S0001\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02W0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E3_H06W0203\narc: A1 H00L0000\narc: A7 E1_H01W0000\narc: B1 V00B0000\narc: B7 V02S0701\narc: C1 E1_H02W0401\narc: C7 V00T0100\narc: CE1 H00R0100\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V02S0201\narc: D7 N1_V02S0601\narc: E1_H01E0001 F0\narc: E1_H01E0101 Q4\narc: F0 F5A_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 H02E0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: V00B0100 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R33C14:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 N3_V06S0303\narc: H00L0000 H02W0001\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 H02W0701\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0701 H06W0203\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02N0101\narc: W1_H02W0101 V06S0103\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 H01E0001\narc: A1 H02E0501\narc: A6 S1_V02N0301\narc: A7 H02W0501\narc: B1 H02E0301\narc: B2 V02S0101\narc: B6 H02W0101\narc: B7 V00B0100\narc: C1 V02N0401\narc: C2 N1_V02S0401\narc: C6 W1_H02E0601\narc: C7 S1_V02N0201\narc: CE0 H00L0000\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0201\narc: D2 H00R0000\narc: D3 V01S0100\narc: D6 E1_H02W0001\narc: D7 V00B0000\narc: E1_H01E0101 Q4\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: M2 H02E0601\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q2\narc: N1_V02N0401 F6\narc: N1_V02N0501 F7\narc: V01S0000 F1\narc: V01S0100 F1\narc: W1_H02W0301 Q1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111000001111100\nword: SLICED.K0.INIT 0101001111111111\nword: SLICED.K1.INIT 0000000000100000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R33C15:PLC2\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 N1_V02S0701\narc: H00L0100 N1_V02S0301\narc: H00R0100 V02S0501\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 H01E0001\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02W0501\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0003 E3_H06W0003\narc: A3 E1_H01E0001\narc: B0 H01W0100\narc: B2 H00R0000\narc: B3 V02N0301\narc: B6 V01S0000\narc: C0 H00R0100\narc: C2 E1_H02W0601\narc: C3 V02N0401\narc: C6 V00B0100\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 V00T0100\narc: D2 V01S0100\narc: D3 V02N0201\narc: D6 V00B0000\narc: D7 S1_V02N0601\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q6\narc: E1_H02E0201 Q0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 Q4\narc: H01W0100 Q0\narc: M0 V00T0000\narc: M4 V00T0100\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: S1_V02S0201 F2\narc: V01S0000 Q6\narc: V01S0100 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0011111100000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R33C16:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 V06S0303\narc: H00L0000 H02E0201\narc: H00L0100 N1_V02S0101\narc: H00R0000 H02W0401\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 H06W0103\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H02W0601\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02E0701\narc: V00T0000 H02W0001\narc: V00T0100 H02W0301\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 V06S0303\narc: A5 V00B0000\narc: A6 H00L0000\narc: A7 H02E0501\narc: B5 S1_V02N0701\narc: B6 H01E0101\narc: B7 V00B0100\narc: C5 E1_H02W0601\narc: C6 V00T0100\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CE1 H02W0101\narc: CLK0 G_HPBX0000\narc: D5 E1_H02W0201\narc: D6 H00L0100\narc: D7 V02N0601\narc: E1_H01E0001 F7\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: M0 H02E0601\narc: M2 H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q2\narc: V01S0100 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0101001111111111\nword: SLICED.K1.INIT 1010101010001010\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R33C17:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 E1_H01W0100\narc: H00L0000 V02S0001\narc: H00R0000 V02S0401\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E3_H06W0103\narc: V00B0000 H02W0401\narc: V00B0100 V02S0301\narc: V00T0000 H02E0201\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 E3_H06W0303\narc: W3_H06W0103 N3_V06S0103\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A1 E1_H01E0001\narc: B1 V00B0000\narc: C1 W1_H02E0401\narc: CE2 H00R0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: E1_H01E0001 Q6\narc: E3_H06E0203 Q4\narc: F1 F1_SLICE\narc: H01W0100 Q4\narc: M4 E1_H02W0401\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R33C18:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: H00R0000 S1_V02N0601\narc: H00R0100 V02S0501\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 V01N0001\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0201\narc: V00B0100 S1_V02N0301\narc: V00T0100 H02W0301\narc: W1_H02W0201 V06S0103\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 E3_H06W0303\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0303 E3_H06W0303\narc: A4 V02N0301\narc: A5 V00T0000\narc: B0 V02S0101\narc: B4 H00L0000\narc: B5 V00B0100\narc: B6 V01S0000\narc: C0 E1_H02W0401\narc: C4 V00T0100\narc: C5 W1_H02E0601\narc: C6 E1_H02W0401\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 E1_H02W0201\narc: D4 V02S0601\narc: D5 H02E0001\narc: D6 S1_V02N0401\narc: D7 E1_H02W0201\narc: E1_H01E0101 F5\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q0\narc: H01W0100 F4\narc: M0 V00B0000\narc: M2 E1_H02W0601\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: N1_V02N0201 Q2\narc: V00T0000 Q2\narc: V01S0000 Q6\narc: V01S0100 Q6\narc: W1_H02W0401 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 1010100010101010\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R33C19:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V02S0201\narc: E1_H02E0601 N3_V06S0303\narc: H00L0100 V02N0101\narc: H00R0000 V02S0401\narc: H00R0100 H02W0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0701 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: V00T0000 V02S0601\narc: V00T0100 V02N0501\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 E1_H02W0101\narc: W3_H06W0103 E1_H02W0101\narc: W3_H06W0203 E3_H06W0203\narc: A1 E1_H01E0001\narc: A3 V00T0000\narc: B1 N1_V02S0101\narc: B3 W1_H02E0301\narc: C1 H00R0100\narc: C3 N1_V01N0001\narc: CE2 H00L0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D3 H01E0101\narc: E1_H01E0001 Q4\narc: E3_H06E0303 Q6\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 Q6\narc: M2 V00T0100\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F1\narc: V01S0000 F2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000001000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111011101110011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R33C20:PLC2\narc: E1_H02E0401 V02S0401\narc: H00L0000 E1_H02W0001\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 E1_H01W0100\narc: S1_V02S0101 N3_V06S0103\narc: V00B0000 S1_V02N0001\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02E0201\narc: V00T0100 V02N0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 V02S0001\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 N1_V01S0000\narc: W3_H06W0003 E3_H06W0003\narc: A1 H00L0000\narc: A3 E1_H01E0001\narc: A4 H02W0701\narc: A5 W1_H02E0501\narc: B1 H01W0100\narc: B3 N1_V02S0101\narc: B4 N1_V02S0701\narc: B5 V00B0100\narc: C1 N1_V01N0001\narc: C3 H00R0100\narc: C4 H02E0601\narc: C5 E1_H02W0601\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D3 S1_V02N0001\narc: D4 E1_H02W0001\narc: D5 V00B0000\narc: E1_H01E0001 Q6\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F3\narc: H01W0100 F4\narc: M0 V00T0100\narc: M6 V00T0000\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V02N0001 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000001000000000\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 1010100010101010\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111011101110011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R33C21:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 V02S0601\narc: H00L0000 H02W0201\narc: H00L0100 V02S0101\narc: H00R0000 V02S0601\narc: H01W0000 E3_H06W0103\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 H06W0003\narc: S1_V02S0301 H02W0301\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02W0701\narc: V00T0100 V02S0501\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0701 V02S0701\narc: W3_H06W0003 V06S0003\narc: W3_H06W0203 V06S0203\narc: B0 V00T0000\narc: C0 H00L0100\narc: CE1 H00R0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 E1_H02W0001\narc: E1_H01E0101 Q2\narc: E1_H02E0001 Q0\narc: E1_H02E0201 Q2\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: H01W0100 Q4\narc: M0 V00B0000\narc: M2 V00B0100\narc: M4 H02E0401\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: N3_V06N0203 Q4\narc: N3_V06N0303 Q6\narc: V00T0000 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R33C22:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 E1_H01W0000\narc: E3_H06E0003 V06S0003\narc: H00L0100 H02W0301\narc: H00R0000 H02E0601\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0701 H02W0701\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02S0101\narc: V00T0000 H02E0201\narc: V00T0100 V02S0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V02S0701\narc: A4 V00T0000\narc: A5 V00B0000\narc: B4 H02E0101\narc: B5 H01E0101\narc: C4 V02N0001\narc: C5 V02S0001\narc: CE0 H02W0101\narc: CE1 H00R0000\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D4 H02W0201\narc: D5 H00L0100\narc: E1_H02E0501 F5\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F4\narc: H01W0100 Q0\narc: M0 V00B0100\narc: M2 H02W0601\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: V00B0000 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1010100010101010\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R33C23:PLC2\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V06S0303\narc: E3_H06E0303 V06S0303\narc: H00L0000 W1_H02E0001\narc: H00L0100 H02E0101\narc: H00R0100 H02W0701\narc: N1_V02N0001 E1_H02W0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 N1_V02S0701\narc: V00B0100 H02W0501\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 N1_V02S0701\narc: N1_V02N0401 W3_H06E0203\narc: W3_H06W0103 V06S0103\narc: W3_H06W0303 V06S0303\narc: A2 H00L0100\narc: A3 V00T0000\narc: A5 V02N0301\narc: A7 S1_V02N0101\narc: B2 N1_V02S0301\narc: B3 V01N0001\narc: B5 H00L0000\narc: B7 W1_H02E0301\narc: C2 E1_H02W0401\narc: C3 H02W0601\narc: C5 S1_V02N0001\narc: C7 W1_H02E0401\narc: CE0 N1_V02S0201\narc: CE1 H02W0101\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 H02W0201\narc: D5 H00R0100\narc: D7 H02W0001\narc: E1_H01E0001 F2\narc: E1_H01E0101 F4\narc: E3_H06E0003 Q0\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M0 E1_H02W0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0101 Q0\narc: N3_V06N0103 F2\narc: S1_V02S0201 F2\narc: V00T0000 Q2\narc: V00T0100 F3\narc: V01S0000 F2\narc: W1_H02W0001 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0111000001111100\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R33C24:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V01N0101\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 V06S0303\narc: E3_H06E0303 V06S0303\narc: H00R0100 H02E0501\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 E1_H01W0000\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 H02W0701\narc: V00B0000 N1_V02S0001\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02N0601\narc: V00T0100 H02W0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0003 N3_V06S0003\narc: W3_H06W0303 V06S0303\narc: E3_H06E0103 W3_H06E0003\narc: A6 V00T0100\narc: B5 H01E0101\narc: B6 H01E0101\narc: B7 S1_V02N0701\narc: C5 E1_H02W0401\narc: C6 E1_H01E0101\narc: C7 V00T0000\narc: CE0 H00R0100\narc: CE1 V02S0201\narc: CLK0 G_HPBX0000\narc: D5 H01W0000\narc: D6 E1_H01W0100\narc: D7 W1_H02E0201\narc: E1_H01E0101 F7\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: LSR1 V00B0000\narc: M0 H02W0601\narc: M2 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q2\narc: N3_V06N0303 F6\narc: W1_H02W0501 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100000000000000\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0011111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R33C25:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0701 V06S0203\narc: H00L0100 V02S0301\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0601 H02W0601\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00B0100 H02E0501\narc: V00T0000 N1_V02S0401\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V06S0203\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0203 V06S0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A3 V02N0501\narc: B3 H02E0101\narc: C3 H00L0100\narc: CE0 H02W0101\narc: CE2 V02N0601\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: E1_H01E0001 F2\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: F2 F5B_SLICE\narc: H01W0000 Q4\narc: H01W0100 F2\narc: M0 H02W0601\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q0\narc: N3_V06N0203 Q4\narc: V01S0000 Q0\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R33C26:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 V02S0401\narc: E1_H02E0701 V06S0203\narc: E3_H06E0203 V06N0203\narc: E3_H06E0303 V06N0303\narc: H00L0000 V02S0201\narc: H00L0100 H02E0301\narc: H00R0100 V02S0501\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H02W0401\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 E1_H02W0601\narc: V00B0100 W1_H02E0501\narc: V00T0000 W1_H02E0001\narc: V00T0100 H02W0101\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 V06S0203\narc: W3_H06W0003 E3_H06W0003\narc: A1 E1_H01E0001\narc: B1 E1_H01W0100\narc: C1 H00L0100\narc: CE1 H00R0100\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: E1_H01E0001 Q2\narc: E3_H06E0003 F0\narc: F0 F5A_SLICE\narc: H01W0100 Q4\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00T0000\narc: M2 E1_H02W0601\narc: M4 H02E0401\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q6\narc: N3_V06N0003 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R33C27:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 V02S0001\narc: H00R0000 H02E0401\narc: H00R0100 N1_V02S0701\narc: N1_V02N0101 H02W0101\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 N3_V06S0303\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: V00B0000 H02W0601\narc: V00B0100 H02W0501\narc: V00T0100 E1_H02W0301\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 E3_H06W0303\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0103\narc: A3 V00T0000\narc: B3 H00R0100\narc: C3 H00L0000\narc: CE0 W1_H02E0101\narc: CE2 N1_V02S0601\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: E1_H01E0001 F3\narc: E3_H06E0203 Q4\narc: F3 F3_SLICE\narc: H01W0000 Q6\narc: H01W0100 Q4\narc: M0 V00T0100\narc: M4 V00B0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V00T0000 Q0\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000100000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R33C28:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 H02E0001\narc: H00R0100 V02S0501\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 V02S0101\narc: V00T0000 V02N0401\narc: V00T0100 H02W0301\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 V02S0601\narc: E1_H02E0001 W3_H06E0003\narc: S1_V02S0001 W3_H06E0003\narc: A3 V01N0101\narc: A4 E1_H02W0501\narc: A5 H02E0501\narc: B3 V02N0301\narc: B4 H02W0101\narc: B5 V02N0701\narc: C3 H00L0000\narc: C4 V02N0001\narc: C5 V00T0000\narc: CE0 V02S0201\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 H02E0201\narc: D4 V00B0000\narc: D5 V02N0601\narc: E1_H01E0001 Q0\narc: E1_H02E0101 F3\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 V00T0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 1010101010001010\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R33C29:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 V01N0001\narc: E1_H02E0601 V02S0601\narc: H00L0000 N1_V02S0001\narc: H00R0000 H02W0601\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 S1_V02N0001\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N3_V06S0003\narc: V00B0100 H02E0501\narc: V00T0000 H02W0001\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0301 N1_V01S0100\narc: E1_H02E0501 W3_H06E0303\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: A3 H01E0001\narc: A5 N1_V01N0101\narc: A7 N1_V02S0101\narc: B0 H01W0100\narc: B3 W1_H02E0301\narc: B5 H02E0301\narc: B7 V02N0501\narc: C0 H00L0000\narc: C3 V02N0601\narc: C5 H02E0601\narc: C7 W1_H02E0401\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 N1_V02S0201\narc: D3 H00R0000\narc: D5 W1_H02E0201\narc: D7 E1_H02W0201\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: M0 V00T0000\narc: M2 N1_V01N0001\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q0\narc: N1_V02N0201 F2\narc: N1_V02N0501 F5\narc: N3_V06N0103 F2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R33C2:PLC2\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: V00B0000 V02N0201\narc: V00T0000 S1_V02N0401\narc: B3 N1_V02S0101\narc: B7 E1_H02W0301\narc: C3 V02N0601\narc: C7 V01N0101\narc: CE0 S1_V02N0201\narc: CLK0 G_HPBX0000\narc: D3 H02E0001\narc: D7 H02E0001\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F3\narc: LSR0 V00B0000\narc: M0 V00T0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: S3_V06S0203 F7\narc: V01S0000 Q0\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R33C30:PLC2\narc: H00L0100 H02E0301\narc: H00R0100 H02E0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 N1_V02S0401\narc: V00B0000 V02S0001\narc: V00B0100 N1_V02S0101\narc: V00T0000 W1_H02E0201\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 V02S0001\narc: W1_H02W0501 V02S0501\narc: H01W0100 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: A5 N1_V01N0101\narc: B0 V02N0101\narc: B5 V02S0701\narc: C0 N1_V02S0401\narc: C5 V00T0000\narc: CE1 V02N0201\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 N1_V01S0000\narc: D5 H00R0100\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q2\narc: F0 F5A_SLICE\narc: F4 F5C_SLICE\narc: H01W0000 F4\narc: M0 V00B0000\narc: M2 H02E0601\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: V01S0100 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R33C31:PLC2\narc: E1_H02E0401 V06S0203\narc: H00L0000 V02S0201\narc: H00L0100 V02S0301\narc: H00R0000 V02S0401\narc: H00R0100 H02W0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0601 H06W0303\narc: V00B0100 N1_V02S0301\narc: V00T0000 N1_V02S0601\narc: V00T0100 V02S0701\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0003 N3_V06S0003\narc: W3_H06W0203 N3_V06S0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: A3 E1_H01E0001\narc: A4 V02N0301\narc: B2 H00L0000\narc: B3 V02N0101\narc: B4 H01E0101\narc: B5 V01S0000\narc: C2 H02W0401\narc: C3 W1_H02E0401\narc: C4 V00T0000\narc: C5 H01E0001\narc: CE0 H00L0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 H00R0000\narc: D3 W1_H02E0201\narc: D4 W1_H02E0001\narc: D5 V02S0401\narc: E1_H01E0001 F4\narc: E1_H02E0501 F5\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F3\narc: M0 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0003 F3\narc: N3_V06N0103 F2\narc: V01S0000 Q6\narc: V01S0100 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0011001100001111\nword: SLICEB.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0001010100111111\nword: SLICEC.K1.INIT 0011001100001111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R33C32:PLC2\narc: E1_H02E0301 E3_H06W0003\narc: H00R0000 V02N0601\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 N1_V01S0100\narc: S3_V06S0303 N3_V06S0303\narc: V00B0100 V02S0101\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 E1_H02W0701\narc: N3_V06N0203 W3_H06E0203\narc: N3_V06N0303 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: CE0 V02S0201\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: E1_H02E0401 Q6\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: H01W0100 Q2\narc: M0 E1_H02W0601\narc: M2 V00B0100\narc: M4 H02E0401\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q6\narc: N1_V02N0001 Q0\narc: N1_V02N0601 Q4\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R33C33:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 V06S0303\narc: E3_H06E0103 V06S0103\narc: H00L0000 H02W0001\narc: H00R0000 V02S0601\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0501 N1_V02S0401\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02E0301\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 V02S0401\narc: E1_H02E0601 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: CE1 H00R0000\narc: CE2 H00L0000\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: M2 V00T0100\narc: M4 E1_H02W0401\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: V01S0000 Q4\narc: W3_H06W0103 Q2\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R33C34:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 V06S0003\narc: H00L0100 V02S0301\narc: H00R0000 V02S0401\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0701 N1_V01S0100\narc: V00B0000 V02S0001\narc: V00B0100 V02S0101\narc: V00T0100 V02S0701\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0303 E3_H06W0203\narc: B4 V02S0501\narc: B7 V00T0000\narc: C4 V02N0001\narc: C7 H02W0601\narc: CE0 H00L0100\narc: CE1 H00R0000\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D4 V02N0601\narc: D5 H02E0001\narc: D7 V00B0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F7\narc: E1_H02E0601 Q4\narc: E3_H06E0103 Q2\narc: E3_H06E0203 F4\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: M0 V00B0100\narc: M2 H02E0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N3_V06N0203 Q4\narc: V00T0000 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0011001100001111\nword: SLICEC.K0.INIT 0000001111001111\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R33C35:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 S1_V02N0201\narc: H00L0100 H02W0301\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H01E0101\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 H06E0203\narc: N3_V06N0303 H06E0303\narc: S1_V02S0001 H02E0001\narc: S1_V02S0301 H02W0301\narc: S1_V02S0601 V01N0001\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02S0001\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02N0701\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 E1_H02W0301\narc: E1_H02E0301 W3_H06E0003\narc: A7 H02E0701\narc: B7 V00B0000\narc: C6 V00B0100\narc: C7 V00T0100\narc: CE0 S1_V02N0201\narc: CE1 V02S0201\narc: CE2 H00L0000\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D6 H01W0000\narc: D7 H02W0201\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q7\narc: E1_H02E0201 Q2\narc: E1_H02E0401 F6\narc: E3_H06E0003 Q0\narc: E3_H06E0203 Q4\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: M0 V00T0000\narc: M2 H02W0601\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0501 Q7\narc: S1_V02S0201 Q0\narc: S1_V02S0401 Q4\narc: V00B0100 Q7\narc: V01S0000 Q7\narc: W1_H02W0501 Q7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0000001000110011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R33C36:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0203 H01E0001\narc: H00L0000 H02E0001\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 V01N0101\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 H06E0103\narc: V00B0000 V02N0001\narc: V00B0100 H02E0501\narc: V00T0000 H02E0201\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0601 V02S0601\narc: H01W0000 W3_H06E0103\narc: A5 N1_V01N0101\narc: B5 H01E0101\narc: C5 V00T0000\narc: CE0 H00L0000\narc: CE1 H02W0101\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D5 V02S0401\narc: E1_H02E0001 Q0\narc: E1_H02E0401 Q6\narc: F4 F5C_SLICE\narc: M0 V00B0100\narc: M2 H02E0601\narc: M4 H02W0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q0\narc: N3_V06N0203 F4\narc: V01S0000 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100001101000001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R33C37:PLC2\narc: H00L0000 H02E0001\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 W1_H02E0301\narc: S1_V02S0201 H02E0201\narc: S1_V02S0601 H02E0601\narc: V00B0000 N1_V02S0201\narc: V00T0000 N1_V02S0601\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 E1_H02W0201\narc: E1_H02E0601 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: A1 F5\narc: A4 N1_V01N0101\narc: A6 H00L0000\narc: B1 H00R0100\narc: B4 V02N0501\narc: B5 H00R0000\narc: B6 N1_V01S0000\narc: C1 W1_H02E0401\narc: C4 S1_V02N0001\narc: C5 V02S0201\narc: C6 H02E0601\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D4 W1_H02E0001\narc: D5 H02E0201\narc: D6 V02S0401\narc: D7 V00B0000\narc: E1_H01E0001 F6\narc: F0 F5A_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H00R0100 F7\narc: LSR1 V00T0000\narc: M0 H02W0601\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q4\narc: N3_V06N0003 F0\narc: W1_H02W0401 Q4\nword: SLICED.K0.INIT 1000001001000001\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 1111111100101010\nword: SLICEC.K1.INIT 1100110000001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000001000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R33C38:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 V01N0101\narc: E3_H06E0303 W1_H02E0501\narc: H00L0100 H02W0301\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00T0100 N1_V02S0501\narc: W1_H02W0601 H01E0001\narc: E1_H02E0201 W3_H06E0103\narc: B5 H00R0000\narc: C5 H02W0401\narc: CE0 H00L0100\narc: CE1 V02N0201\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: E3_H06E0103 Q2\narc: F5 F5_SLICE\narc: H00R0000 Q6\narc: M0 V00T0000\narc: M2 H02E0601\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: V00T0000 Q2\narc: W3_H06W0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011001100001111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R33C39:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V06S0303\narc: E1_H02E0701 N1_V01S0100\narc: H00L0000 V02N0201\narc: H00L0100 V02S0301\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 E1_H02W0501\narc: S1_V02S0001 N3_V06S0003\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 V02N0301\narc: V00T0000 H02E0201\narc: V00T0100 V02S0501\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0003 N3_V06S0003\narc: CE0 V02S0201\narc: CE1 H00L0100\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: E1_H02E0201 Q2\narc: E3_H06E0303 Q6\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V00B0000 Q6\narc: V01S0000 Q2\narc: V01S0100 Q4\narc: W1_H02W0201 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R33C3:PLC2\narc: E1_H02E0401 V02N0401\narc: E1_H02E0701 E1_H01W0100\narc: H00L0100 V02S0101\narc: H00R0000 V02S0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 N1_V01S0100\narc: V00B0000 V02S0201\narc: V00B0100 H02W0501\narc: V00T0000 V02S0401\narc: A3 E1_H02W0701\narc: A7 V02N0301\narc: B3 H01W0100\narc: B7 E1_H02W0101\narc: C1 H00R0100\narc: C3 H00L0100\narc: C5 V00B0100\narc: C7 V00T0000\narc: D1 H00R0000\narc: D3 E1_H02W0201\narc: D5 V00B0000\narc: D7 V02S0601\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F5\narc: M2 H02W0601\narc: N1_V01N0101 F2\narc: V01S0000 F1\narc: V01S0100 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000110010101111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0010000100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R33C40:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 N1_V02S0601\narc: H00L0100 H02W0301\narc: H00R0100 H02E0501\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 H01E0101\narc: V00B0000 V02N0001\narc: V00T0000 H02E0001\narc: V00T0100 W1_H02E0101\narc: E1_H02E0701 W3_H06E0203\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: A1 V02S0701\narc: B1 W1_H02E0101\narc: C0 E1_H02W0401\narc: C1 H00L0100\narc: CE1 H00R0100\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 N1_V02S0201\narc: E1_H01E0101 Q2\narc: E3_H06E0103 Q2\narc: F0 F5A_SLICE\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 E1_H01E0101\narc: M6 H02E0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 F0\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011110000\nword: SLICEA.K1.INIT 1010001110100000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\n\n.tile R33C41:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 N1_V02S0601\narc: H00L0100 N1_V02S0301\narc: H00R0000 H02W0401\narc: H00R0100 V02S0701\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0401 N1_V01S0000\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 V02S0301\narc: V00T0000 E1_H02W0001\narc: V00T0100 H02E0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 N1_V02S0501\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: A1 W1_H02E0701\narc: A3 V02S0501\narc: A7 H02W0501\narc: B1 H00R0100\narc: B3 H00R0000\narc: B4 V02S0701\narc: B5 H02E0301\narc: B7 N1_V02S0501\narc: C0 H02W0401\narc: C1 H02E0401\narc: C2 H02W0401\narc: C3 H02E0401\narc: C4 V02N0001\narc: C5 H02W0401\narc: C7 S1_V02N0001\narc: D0 V00T0100\narc: D1 S1_V02N0201\narc: D2 V00T0100\narc: D3 S1_V02N0201\narc: D4 V02S0401\narc: D5 H02W0201\narc: D7 H00L0100\narc: E3_H06E0203 F4\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: M0 V00B0100\narc: M2 H02E0601\narc: M4 V00T0000\narc: N1_V01N0001 F4\narc: N3_V06N0003 F0\narc: N3_V06N0103 F2\narc: N3_V06N0203 F4\narc: S1_V02S0701 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100010010000000\nword: SLICEC.K0.INIT 1100111111000000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 0000000011110000\nword: SLICEB.K1.INIT 1100110000001010\nword: SLICEA.K0.INIT 0000000011110000\nword: SLICEA.K1.INIT 1100110000001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\n\n.tile R33C42:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 H01E0001\narc: H00L0000 H02E0201\narc: H00L0100 V02N0301\narc: H00R0100 H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 V01N0101\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0501 N1_V02S0501\narc: S3_V06S0203 N1_V02S0401\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 V02S0301\narc: V00T0000 S1_V02N0401\narc: V01S0000 N3_V06S0103\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0701 S1_V02N0701\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: A2 H00L0100\narc: A3 V02N0501\narc: B0 E1_H01W0100\narc: B1 V00T0000\narc: B2 H02E0101\narc: B3 H00R0100\narc: B4 V02S0501\narc: B5 H02E0301\narc: C0 S1_V02N0401\narc: C1 H02E0401\narc: C2 H02W0401\narc: C3 H00L0000\narc: C4 V00T0000\narc: C5 V00T0000\narc: C6 H02E0601\narc: C7 H02E0601\narc: D0 V02N0001\narc: D1 V02N0001\narc: D2 V00T0100\narc: D3 V02S0001\narc: D4 V02N0601\narc: D5 V02N0601\narc: D6 H01W0000\narc: D7 F0\narc: E1_H01E0001 F4\narc: E3_H06E0003 F0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: M0 V00B0100\narc: M4 V00B0100\narc: N1_V01N0101 F7\narc: N1_V02N0401 F4\narc: N3_V06N0203 F4\narc: S1_V02S0001 F0\narc: V00T0100 F3\narc: V01S0100 F6\narc: W3_H06W0103 F2\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEB.K0.INIT 0010001000100011\nword: SLICEB.K1.INIT 1100010010000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111000011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R33C43:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0203 H01E0001\narc: H00L0100 H02E0101\narc: H00R0000 H02W0601\narc: H00R0100 V02S0501\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 N3_V06S0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02W0701\narc: V00T0100 H02E0101\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 N3_V06S0203\narc: A5 E1_H02W0501\narc: B2 H00R0100\narc: B5 H02W0301\narc: B6 V02S0701\narc: B7 H02W0101\narc: C1 S1_V02N0401\narc: C2 H02W0401\narc: C5 N1_V02S0201\narc: C6 V00T0100\narc: C7 H02E0401\narc: CE1 S1_V02N0201\narc: CLK0 G_HPBX0000\narc: D1 V01S0100\narc: D2 V00B0100\narc: D3 H00R0000\narc: D5 W1_H02E0001\narc: D6 N1_V02S0401\narc: D7 H00L0100\narc: E3_H06E0103 Q2\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 Q2\narc: M2 E1_H02W0601\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: N1_V01N0101 F1\narc: N3_V06N0303 F5\narc: V01S0100 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100101010101010\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 1100111111000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 1100000011110011\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R33C44:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 V06S0203\narc: H00L0000 H02W0201\narc: H00L0100 N1_V02S0301\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 E3_H06W0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 W1_H02E0401\narc: V00B0100 E1_H02W0701\narc: V00T0000 V02S0601\narc: V00T0100 W1_H02E0101\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 N1_V02S0401\narc: H01W0000 W3_H06E0103\narc: N1_V02N0101 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: B0 E1_H02W0101\narc: B2 E1_H02W0301\narc: B3 V02N0301\narc: B5 H02E0101\narc: B6 V01S0000\narc: B7 V00B0000\narc: C0 H00L0000\narc: C2 W1_H02E0401\narc: C3 W1_H02E0601\narc: C5 E1_H02W0401\narc: C6 W1_H02E0401\narc: C7 V00B0100\narc: CE0 V02S0201\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 W1_H02E0201\narc: D2 V00T0100\narc: D3 V00T0100\narc: D5 H00L0100\narc: D6 W1_H02E0001\narc: D7 W1_H02E0001\narc: E1_H01E0101 F6\narc: E1_H02E0401 F6\narc: E3_H06E0003 Q0\narc: E3_H06E0103 F2\narc: E3_H06E0303 F6\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F2\narc: M0 H02W0601\narc: M2 V00T0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: V01S0000 Q0\narc: V01S0100 F2\narc: W1_H02W0701 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0011000011111100\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1100000011110011\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R33C45:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 E3_H06W0103\narc: E3_H06E0203 V01N0001\narc: H00L0100 H02E0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0303 E1_H01W0100\narc: V00B0000 N1_V02S0201\narc: V00B0100 E1_H02W0501\narc: V00T0000 E1_H02W0001\narc: V00T0100 N1_V02S0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 N1_V02S0601\narc: H01W0100 W3_H06E0303\narc: W1_H02W0501 W3_H06E0303\narc: A3 V02S0501\narc: B3 N1_V02S0101\narc: B4 V01S0000\narc: B7 S1_V02N0501\narc: C3 H00R0100\narc: C4 V00T0000\narc: C7 H02W0601\narc: CE0 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 S1_V02N0201\narc: D4 H02W0001\narc: D5 H01W0000\narc: D7 E1_H01W0100\narc: E1_H01E0001 F7\narc: E1_H01E0101 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: M0 V00B0100\narc: M1 H00L0100\narc: M2 E1_H02W0601\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F4\narc: N1_V02N0301 Q1\narc: N3_V06N0103 F1\narc: V01S0000 Q1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0011000011111100\nword: SLICEC.K0.INIT 0011001100001111\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1100000011100000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R33C46:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 H01E0101\narc: H00L0100 V02N0301\narc: H00R0000 H02W0401\narc: H00R0100 V02S0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H06W0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 W1_H02E0701\narc: V00T0000 H02W0201\narc: V00T0100 H02E0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0701 W3_H06E0203\narc: A3 V00T0000\narc: B3 H00R0100\narc: B5 H02W0101\narc: B6 N1_V02S0501\narc: C3 V02S0401\narc: C5 S1_V02N0201\narc: C6 E1_H02W0601\narc: CE0 V02S0201\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 V00T0100\narc: D5 H00L0100\narc: D6 H00L0100\narc: D7 H01W0000\narc: E1_H01E0001 F5\narc: E1_H01E0101 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q1\narc: H01W0100 F1\narc: M0 H02W0601\narc: M1 H00R0000\narc: M2 H02W0601\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F1\narc: N1_V01N0101 F1\narc: W1_H02W0601 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 0000111100110011\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000100011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R33C47:PLC2\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 W1_H02E0201\narc: H00L0100 V02N0101\narc: H00R0000 N1_V02S0401\narc: H00R0100 V02S0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H02E0701\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S1_V02N0101\narc: N3_V06N0303 E3_H06W0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02N0601\narc: V00T0100 V02S0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 V06S0303\narc: N3_V06N0203 W3_H06E0203\narc: S1_V02S0701 W3_H06E0203\narc: A3 H00L0100\narc: A6 H02W0501\narc: A7 E1_H02W0701\narc: B3 H00R0100\narc: B4 V00B0100\narc: B6 V01S0000\narc: B7 V02N0501\narc: C3 H02E0601\narc: C4 V02N0001\narc: C6 E1_H02W0401\narc: C7 V02N0201\narc: CE0 V02S0201\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 H00R0000\narc: D4 N1_V02S0601\narc: D5 V02S0401\narc: D6 H02W0001\narc: D7 H02E0201\narc: E1_H01E0001 F1\narc: E1_H01E0101 F1\narc: E1_H02E0401 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 F1\narc: M0 V00T0000\narc: M1 H00L0000\narc: M2 V00T0000\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: N1_V01N0001 Q1\narc: N1_V01N0101 F6\narc: N1_V02N0301 Q1\narc: V01S0000 F7\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 1001000000001001\nword: SLICEC.K0.INIT 0000111100110011\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 0000100011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\n\n.tile R33C48:PLC2\narc: E1_H02E0601 N3_V06S0303\narc: H00L0100 V02S0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 H01E0001\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 E1_H02W0701\narc: V00B0000 V02N0201\narc: V00B0100 H02E0701\narc: V00T0000 V02N0401\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V02N0601\narc: H01W0100 W3_H06E0303\narc: N1_V02N0401 W3_H06E0203\narc: S1_V02S0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: A5 V02N0101\narc: B1 H00R0100\narc: B2 W1_H02E0301\narc: B5 V02N0701\narc: C1 H02E0401\narc: C2 V02S0601\narc: C5 H02E0601\narc: CE1 H00L0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0001\narc: D2 V01S0100\narc: D3 V00B0100\narc: D5 H02W0201\narc: E1_H01E0001 F5\narc: E3_H06E0103 Q2\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: M2 V00T0000\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N3_V06N0103 Q2\narc: V01S0100 F1\narc: W1_H02W0201 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000001001000001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0011000011111100\nword: SLICEB.K0.INIT 1100000011110011\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R33C49:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V02S0601\narc: H00R0000 H02E0601\narc: H00R0100 H02W0701\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 N3_V06S0303\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 V02S0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0401 H01E0001\narc: N1_V02N0101 W3_H06E0103\narc: N3_V06N0303 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0203 N3_V06S0203\narc: E3_H06E0103 W3_H06E0103\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E3_H06E0003 Q0\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0001 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R33C4:PLC2\narc: E1_H02E0601 V02S0601\narc: H00R0000 V02S0601\narc: H00R0100 V02N0701\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0501 E1_H01W0100\narc: V00B0000 V02N0001\narc: V00T0000 V02S0601\narc: V00T0100 V02N0701\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 E1_H01W0100\narc: A1 H02E0701\narc: A2 H02E0701\narc: A6 V02N0101\narc: A7 E1_H02W0701\narc: B1 V02N0101\narc: B2 V02N0101\narc: B6 V00B0000\narc: B7 S1_V02N0701\narc: C1 E1_H02W0401\narc: C2 E1_H02W0401\narc: C6 V00T0000\narc: C7 E1_H02W0601\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D6 H00R0100\narc: D7 V02S0401\narc: E1_H01E0001 F7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q4\narc: M0 V00T0100\narc: M1 H02W0001\narc: M2 V00T0100\narc: M4 H02E0401\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: V01S0100 F1\narc: W1_H02W0601 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1000110000100011\nword: SLICED.K1.INIT 1111001101010001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100010011110101\nword: SLICEB.K0.INIT 1100010011110101\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R33C50:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0701 N1_V01S0100\narc: H00R0000 V02S0601\narc: H00R0100 V02S0701\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0401 V01N0001\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0701 N3_V06S0203\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02N0101\narc: V00T0100 V02S0501\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0701 N3_V06S0203\narc: N3_V06N0003 W3_H06E0003\narc: N3_V06N0103 W3_H06E0103\narc: N3_V06N0303 W3_H06E0303\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: H01W0100 Q0\narc: M0 V00T0000\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V00T0000 Q2\narc: V01S0100 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R33C51:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0601 S1_V02N0601\narc: H00L0100 W1_H02E0101\narc: H00R0000 H02W0401\narc: N1_V02N0101 V01N0101\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H02W0701\narc: N3_V06N0003 H06E0003\narc: N3_V06N0103 H06E0103\narc: S1_V02S0301 H01E0101\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 H02E0701\narc: S3_V06S0003 N3_V06S0303\narc: V00B0100 V02N0301\narc: V00T0000 V02N0401\narc: W3_H06W0103 E1_H02W0101\narc: A1 N1_V02S0701\narc: A3 H02W0501\narc: A5 V02S0301\narc: A7 H00R0000\narc: B1 V00T0000\narc: B3 V01N0001\narc: B5 V00B0100\narc: B7 S1_V02N0701\narc: C1 W1_H02E0601\narc: C3 H00L0100\narc: C5 W1_H02E0601\narc: C7 W1_H02E0601\narc: D1 H02W0201\narc: D3 H02W0201\narc: D5 H02W0201\narc: D7 H02W0201\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 F7\narc: N3_V06N0303 F5\narc: W3_H06W0003 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1010110000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010110000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010110000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010110000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R33C52:PLC2\narc: H00L0000 H02W0201\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0103 H06E0103\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 H06E0003\narc: S1_V02S0501 H06E0303\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02N0101\narc: V00T0000 V02S0401\narc: V01S0100 N3_V06S0303\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 N1_V01S0100\narc: A1 H02W0701\narc: A3 V00T0000\narc: A7 V02S0101\narc: B1 V01N0001\narc: B3 S1_V02N0301\narc: B7 V02N0501\narc: C1 E1_H02W0401\narc: C3 H00L0000\narc: C7 E1_H02W0401\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 N1_V02S0201\narc: D3 N1_V02S0201\narc: D7 V00B0000\narc: E1_H02E0601 Q4\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F3\narc: W1_H02W0701 F7\narc: W3_H06W0103 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010110000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010110000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010110000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R33C53:PLC2\narc: E1_H02E0101 V01N0101\narc: H00L0000 V02S0201\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0203 H06E0203\narc: N3_V06N0303 H06E0303\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 E1_H02W0401\narc: S3_V06S0003 N1_V01S0000\narc: V00B0000 V02N0001\narc: V00T0000 V02S0401\narc: W1_H02W0201 V02S0201\narc: W1_H02W0701 N1_V01S0100\narc: W3_H06W0203 E1_H01W0000\narc: A1 E1_H02W0501\narc: A3 H02W0501\narc: A5 V00T0000\narc: A7 V02S0101\narc: B1 V01N0001\narc: B3 V02N0101\narc: B5 V02N0701\narc: B7 V00B0000\narc: C1 H00L0000\narc: C3 H00L0000\narc: C5 V02S0201\narc: C7 V02S0201\narc: D1 E1_H02W0001\narc: D3 E1_H02W0001\narc: D5 E1_H02W0001\narc: D7 E1_H02W0001\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: W1_H02W0101 F1\narc: W1_H02W0501 F7\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1010110000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010110000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010110000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010110000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R33C54:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0601 W1_H02E0601\narc: H00L0000 V02S0201\narc: N1_V02N0201 H02W0201\narc: S1_V02S0501 N1_V02S0401\narc: V00T0000 N1_V02S0601\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 N1_V01S0100\narc: N3_V06N0003 W3_H06E0003\narc: N3_V06N0103 W3_H06E0103\narc: A1 V02S0501\narc: A3 V00T0000\narc: A5 V02S0101\narc: B1 H02E0101\narc: B3 V02N0301\narc: B5 S1_V02N0701\narc: C1 H00L0000\narc: C3 H00L0000\narc: C5 V02S0201\narc: D1 H02W0001\narc: D3 H02W0001\narc: D5 H02W0001\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F3\narc: N3_V06N0303 F5\narc: W3_H06W0103 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1010110000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1010110000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010110000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R33C55:PLC2\narc: E1_H02E0601 E1_H01W0000\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0601\narc: V00B0000 H02E0601\narc: V00B0100 H02W0701\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0501 V02S0501\narc: W1_H02W0401 W3_H06E0203\narc: C6 V00T0000\narc: C7 V00T0000\narc: CE0 H02E0101\narc: CLK0 G_HPBX0000\narc: D6 V00B0000\narc: D7 V00B0000\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: N1_V02N0501 F7\narc: V00T0000 Q0\narc: V01S0100 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R33C56:PLC2\narc: H00L0100 E1_H02W0301\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0601 N3_V06S0303\narc: V00B0000 V02S0201\narc: V01S0000 N3_V06S0103\narc: W1_H02W0701 V06S0203\narc: N3_V06N0003 W3_H06E0003\narc: C0 H02E0601\narc: C1 H02E0601\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02N0001\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: H01W0000 Q4\narc: M4 V00B0000\narc: MUXCLK2 CLK0\narc: N1_V01N0101 F0\narc: N1_V02N0101 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000111111110000\nword: SLICEA.K1.INIT 1111000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R33C57:PLC2\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 N3_V06S0303\n\n.tile R33C58:PLC2\narc: S3_V06S0103 N3_V06S0103\narc: W1_H02W0301 N3_V06S0003\n\n.tile R33C59:PLC2\narc: S3_V06S0203 N3_V06S0203\n\n.tile R33C5:PLC2\narc: E1_H02E0501 V02S0501\narc: H00L0000 N1_V02S0001\narc: H00L0100 V02N0301\narc: H00R0100 V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 V01N0101\narc: S1_V02S0001 H06W0003\narc: V00B0000 H02W0601\narc: V00B0100 V02S0301\narc: V00T0100 E1_H02W0101\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 H01E0001\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0701 N1_V01S0100\narc: A3 V02N0701\narc: A5 V00T0000\narc: A6 E1_H01W0000\narc: A7 S1_V02N0301\narc: B3 H00L0000\narc: B5 E1_H02W0301\narc: B6 E1_H02W0301\narc: B7 V02N0501\narc: C3 F6\narc: C5 V00B0100\narc: C6 V02S0201\narc: C7 H02E0601\narc: CE0 H00L0100\narc: CLK0 G_HPBX0000\narc: D3 V01S0100\narc: D5 H00R0100\narc: D6 H00R0100\narc: D7 V00B0000\narc: E1_H02E0001 Q0\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: M0 V00T0100\narc: M2 N1_V01N0001\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F7\narc: N1_V02N0201 F2\narc: V00T0000 Q0\narc: V01S0100 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000110010101111\nword: SLICED.K0.INIT 1111010100110001\nword: SLICED.K1.INIT 1010111100100011\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1101000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R33C60:PLC2\narc: S1_V02S0201 N3_V06S0103\n\n.tile R33C61:PLC2\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\n\n.tile R33C62:PLC2\narc: S3_V06S0303 N3_V06S0203\n\n.tile R33C63:PLC2\narc: S3_V06S0303 N3_V06S0203\n\n.tile R33C64:PLC2\narc: S3_V06S0303 N3_V06S0303\n\n.tile R33C65:PLC2\narc: S3_V06S0303 N3_V06S0303\n\n.tile R33C66:PLC2\narc: S1_V02S0401 N3_V06S0203\n\n.tile R33C67:PLC2\narc: S3_V06S0103 N3_V06S0103\n\n.tile R33C69:PLC2\narc: E1_H02E0501 N3_V06S0303\n\n.tile R33C6:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 H02E0001\narc: H00L0100 V02S0301\narc: N1_V02N0101 N1_V01S0100\narc: S1_V02S0001 E1_H02W0001\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02E0501\narc: V00T0000 H02E0001\narc: V00T0100 V02S0501\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02N0701\narc: A1 E1_H01E0001\narc: A2 E1_H01E0001\narc: A3 E1_H01E0001\narc: B1 V00T0000\narc: B2 H00L0000\narc: B3 H00L0000\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 V02S0201\narc: D2 V02S0201\narc: D3 V02S0201\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H00R0000 Q6\narc: H01W0000 Q4\narc: H01W0100 Q6\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: N1_V02N0401 Q6\narc: N1_V02N0601 Q4\narc: V01S0000 Q4\narc: V01S0100 Q4\narc: W1_H02W0301 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100111101000101\nword: SLICEB.K0.INIT 1100111101000101\nword: SLICEB.K1.INIT 1100111101000101\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R33C7:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 V02S0401\narc: H00L0100 V02S0301\narc: H00R0000 V02S0401\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0301 N1_V01S0100\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 V02N0601\narc: V00T0100 V02N0501\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 H01E0101\narc: A1 H00R0000\narc: A3 H02W0701\narc: A5 H02W0701\narc: A7 H00L0000\narc: B1 H02W0101\narc: B3 V02S0301\narc: B5 H02W0301\narc: B7 V01S0000\narc: C1 H00L0100\narc: C2 E1_H02W0401\narc: C3 S1_V02N0401\narc: C5 V00B0100\narc: C7 V00T0000\narc: D1 H02E0201\narc: D2 S1_V02N0001\narc: D3 E1_H02W0201\narc: D5 H02W0201\narc: D7 V00B0000\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 F2\narc: M0 E1_H02W0601\narc: M4 V00T0100\narc: M6 N1_V01N0101\narc: N1_V01N0101 F4\narc: N1_V02N0101 F3\narc: N1_V02N0301 F3\narc: N1_V02N0601 F6\narc: V01S0000 F0\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 1011000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100111101000101\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100010011110101\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000010000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R33C8:PLC2\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 E1_H01W0100\narc: H00L0100 V02S0101\narc: H00R0000 E1_H02W0601\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0501 V01N0101\narc: V00B0000 H02E0401\narc: V00B0100 H02W0501\narc: V00T0000 V02S0601\narc: V00T0100 V02S0701\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 V02S0201\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0701 E1_H01W0100\narc: W3_H06W0003 N3_V06S0003\narc: A1 H00R0000\narc: A2 E1_H02W0501\narc: A3 V02N0501\narc: A5 S1_V02N0101\narc: A7 N1_V01S0100\narc: B1 V00B0000\narc: B2 H02E0301\narc: B3 F1\narc: B5 N1_V01S0000\narc: B6 H02W0301\narc: B7 W1_H02E0101\narc: C1 V02S0401\narc: C2 W1_H02E0601\narc: C3 H02W0401\narc: C5 V00B0100\narc: C6 S1_V02N0001\narc: C7 V00T0000\narc: D1 W1_H02E0001\narc: D2 S1_V02N0201\narc: D3 V00T0100\narc: D5 H00L0100\narc: D6 H01W0000\narc: D7 H00L0100\narc: E1_H01E0001 F7\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F3\narc: N1_V01N0001 F6\narc: N1_V01N0101 F5\narc: V01S0100 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111010100110001\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100010011110101\nword: SLICED.K0.INIT 1100000000000000\nword: SLICED.K1.INIT 1100111101000101\nword: SLICEB.K0.INIT 1000010000100001\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R33C9:PLC2\narc: H00L0000 V02S0001\narc: H00R0000 H02E0401\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0501 H02E0501\narc: V00B0100 V02S0301\narc: V00T0000 V02S0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 H01E0001\narc: A1 E1_H01E0001\narc: A2 V00B0000\narc: B1 V00T0000\narc: B2 N1_V02S0301\narc: C1 H00L0000\narc: C2 H00L0000\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q6\narc: M0 E1_H02W0601\narc: M1 V01S0100\narc: M2 E1_H02W0601\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V00B0000 Q6\narc: V01S0100 Q4\narc: W1_H02W0301 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100111101000101\nword: SLICEB.K0.INIT 1100111101000101\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R34C10:PLC2\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0601 H02E0601\n\n.tile R34C11:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0601 N1_V02S0601\narc: N1_V02N0301 N1_V01S0100\n\n.tile R34C12:PLC2\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 H02E0601\narc: V00B0100 V02N0101\narc: CE1 H02E0101\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: H01W0100 Q2\narc: LSR0 V00B0100\narc: M2 E1_H02W0601\narc: M6 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: V01S0100 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R34C13:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 E3_H06W0203\narc: H00L0000 E1_H02W0001\narc: H00L0100 V02S0101\narc: H00R0000 V02S0601\narc: H00R0100 H02W0701\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 H02W0601\narc: S1_V02S0101 E1_H02W0101\narc: V00B0000 V02N0201\narc: V00B0100 V02S0301\narc: V00T0100 V02N0501\narc: A1 V02N0701\narc: A2 H02E0501\narc: A4 E1_H01W0000\narc: A5 N1_V01S0100\narc: B1 V01N0001\narc: B2 E1_H01W0100\narc: B4 F1\narc: B5 V02S0701\narc: B6 V01S0000\narc: C1 V02S0401\narc: C2 H00L0100\narc: C4 V02N0001\narc: C5 H02E0401\narc: C6 H02E0601\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 V00B0100\narc: D4 F2\narc: D5 H02W0001\narc: D6 H00R0100\narc: D7 H01W0000\narc: E1_H01E0001 F4\narc: E1_H01E0101 F5\narc: E3_H06E0203 F4\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F5\narc: H01W0100 Q6\narc: M2 V00T0100\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: V01S0000 Q6\narc: V01S0100 Q5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 0111000001111100\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111111100000000\nword: SLICEB.K0.INIT 0001001101011111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R34C14:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0501 E1_H01W0100\narc: H00L0100 H02E0101\narc: H00R0100 H02E0501\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0701 H01E0101\narc: V00B0000 V02S0201\narc: V00B0100 H02E0701\narc: V00T0100 V02S0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 E1_H02W0601\narc: A7 H00L0000\narc: B0 H01W0100\narc: B4 H00R0000\narc: B7 V01S0000\narc: C0 H00L0100\narc: C4 V00B0100\narc: C7 H02W0401\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 H01E0101\narc: D4 H02W0201\narc: D5 H02E0001\narc: D7 V02N0401\narc: E1_H01E0101 Q4\narc: F0 F5A_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 F7\narc: H01W0100 Q0\narc: M0 V00T0100\narc: M2 W1_H02E0601\narc: M4 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: V01S0000 Q4\narc: V01S0100 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R34C15:PLC2\narc: H00L0000 N1_V02S0001\narc: H00L0100 H02E0101\narc: H00R0000 V02N0401\narc: H00R0100 H02W0501\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 S1_V02N0401\narc: S3_V06S0203 N3_V06S0203\narc: V00B0000 V02S0201\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02S0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 S1_V02N0401\narc: W3_H06W0103 E3_H06W0103\narc: A1 H00R0000\narc: A3 E1_H02W0701\narc: A5 H02E0501\narc: A6 N1_V01N0101\narc: A7 V00T0100\narc: B1 N1_V02S0301\narc: B3 E1_H01W0100\narc: B5 V02S0701\narc: B6 V00B0100\narc: B7 V02N0701\narc: C1 H00L0100\narc: C3 H00R0100\narc: C5 W1_H02E0401\narc: C6 E1_H01E0101\narc: C7 V00T0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: D3 V02S0001\narc: D5 V02S0401\narc: D6 V00B0000\narc: D7 H01W0000\narc: E1_H01E0001 F7\narc: E1_H01E0101 F1\narc: E1_H02E0701 F7\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: H01W0100 Q7\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F3\narc: N1_V02N0501 F7\narc: N3_V06N0303 F6\narc: S1_V02S0501 F7\narc: V00B0100 F5\narc: V01S0000 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0111000001111100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R34C16:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: H00L0100 V02N0101\narc: H00R0100 N1_V02S0701\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0303 N3_V06S0303\narc: V00B0000 V02N0001\narc: V00B0100 H02E0701\narc: V00T0100 H02W0101\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 S1_V02N0601\narc: CE0 H00L0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q0\narc: H01W0100 Q4\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 H01E0001\narc: M2 V00T0100\narc: M4 V00B0100\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: V01S0000 Q6\narc: V01S0100 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R34C17:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0601 E1_H01W0000\narc: H00R0000 N1_V02S0401\narc: H01W0000 E3_H06W0103\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H02E0601\narc: V00B0000 H02E0601\narc: V00B0100 V02S0101\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02W0301\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0701 H01E0101\narc: A6 H00L0000\narc: A7 H02E0701\narc: B0 V02N0301\narc: B4 V01S0000\narc: B6 V01S0000\narc: B7 H02W0101\narc: C0 E1_H02W0601\narc: C4 E1_H02W0601\narc: C6 V02S0001\narc: C7 V02N0001\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 E1_H02W0001\narc: D4 V02N0601\narc: D5 E1_H01W0100\narc: D6 H02E0001\narc: D7 V00B0000\narc: E1_H01E0101 F6\narc: E1_H02E0701 F7\narc: F0 F5A_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0100 Q2\narc: M0 V00B0100\narc: M2 H02W0601\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: S1_V02S0001 Q0\narc: V01S0000 Q4\narc: V01S0100 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0101001111111111\nword: SLICED.K1.INIT 1010101010001010\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R34C18:PLC2\narc: E1_H02E0101 V02N0101\narc: H00L0000 V02S0001\narc: H00L0100 V02S0101\narc: H00R0100 H02E0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 N3_V06S0203\narc: S1_V02S0101 N1_V02S0001\narc: V00B0000 V02N0201\narc: V00B0100 E1_H02W0501\narc: V00T0100 V02N0501\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 V01N0101\narc: W1_H02W0601 V02S0601\narc: A3 V00T0000\narc: A5 V00T0100\narc: A7 H02W0701\narc: B3 V02N0301\narc: B5 H01E0101\narc: B7 H02W0301\narc: C3 W1_H02E0601\narc: C5 E1_H01E0101\narc: C7 H02W0401\narc: CE0 H00L0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D3 H02E0001\narc: D5 H00R0100\narc: D7 V00B0000\narc: E1_H01E0001 F7\narc: E1_H01E0101 F3\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F7\narc: M0 H02E0601\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F7\narc: N1_V02N0601 F4\narc: V00T0000 Q0\narc: V01S0000 F7\narc: V01S0100 F7\narc: W1_H02W0501 Q7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111000001111100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000001000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0111011101110011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R34C19:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V06S0003\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 V02S0701\narc: H00L0000 H02W0201\narc: H00L0100 S1_V02N0101\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0201 V01N0001\narc: S1_V02S0301 E1_H02W0301\narc: V00B0100 H02W0501\narc: V00T0000 N1_V02S0601\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 V02S0701\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0103\narc: A1 H00R0000\narc: A3 V00T0000\narc: B1 E1_H02W0101\narc: B3 H00L0000\narc: C1 E1_H02W0601\narc: C3 N1_V01N0001\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D3 E1_H02W0001\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: H00R0000 Q4\narc: M2 V00B0100\narc: M4 V00T0100\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F1\narc: N1_V02N0001 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000001000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111011101110011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R34C20:PLC2\narc: E1_H02E0601 E3_H06W0303\narc: H00L0000 N1_V02S0001\narc: H00L0100 V02S0101\narc: H01W0100 E3_H06W0303\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0701 N1_V01S0100\narc: V00B0000 E1_H02W0601\narc: V00B0100 H02E0501\narc: V00T0000 E1_H02W0201\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0501 N1_V01S0100\narc: A0 H02W0701\narc: A1 V01N0101\narc: A2 H02W0501\narc: A3 H02E0701\narc: A7 H00R0000\narc: B0 V00B0000\narc: B1 H02W0101\narc: B2 V02N0301\narc: B3 H02E0301\narc: B6 V01S0000\narc: B7 V00T0000\narc: C0 N1_V02S0601\narc: C1 S1_V02N0601\narc: C2 F6\narc: C3 H00L0100\narc: C6 V00T0100\narc: C7 H02W0401\narc: CE1 H00L0000\narc: CE2 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 V02N0001\narc: D2 S1_V02N0001\narc: D3 F2\narc: D6 H00R0100\narc: D7 V02N0601\narc: E1_H01E0001 F1\narc: E1_H01E0101 F3\narc: E1_H02E0101 F3\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H00R0100 F7\narc: M4 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: S1_V02S0101 F3\narc: V01S0000 Q3\narc: W1_H02W0201 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0101001111111111\nword: SLICEA.K1.INIT 1010100010101010\nword: SLICEB.K0.INIT 1000000000000000\nword: SLICEB.K1.INIT 0111000001111100\nword: SLICED.K0.INIT 0011111100000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R34C21:PLC2\narc: H00L0000 W1_H02E0001\narc: H00R0000 H02W0601\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0301 H01E0101\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02S0301\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 E1_H01W0100\narc: W3_H06W0103 E3_H06W0003\narc: A5 V00T0000\narc: B2 H01W0100\narc: B5 H00R0000\narc: C1 H00L0000\narc: C2 H02E0601\narc: C5 S1_V02N0001\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D1 H02W0001\narc: D2 V00B0100\narc: D3 H01E0101\narc: D5 W1_H02E0201\narc: E3_H06E0103 F1\narc: E3_H06E0303 Q6\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q2\narc: M2 V00B0000\narc: M6 H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0301 F1\narc: V00T0000 Q2\narc: V01S0000 Q6\narc: W1_H02W0501 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R34C22:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 E1_H01W0100\narc: E3_H06E0103 V06S0103\narc: H00L0000 H02W0001\narc: H00R0000 H02W0401\narc: H00R0100 V02S0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0601 N3_V06S0303\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02W0701\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02W0101\narc: W1_H02W0001 V02N0001\narc: W1_H02W0401 E1_H01W0000\narc: A0 E1_H02W0501\narc: A1 E1_H01E0001\narc: A4 V02N0101\narc: A5 N1_V01N0101\narc: B0 W1_H02E0101\narc: B1 V00B0000\narc: B4 W1_H02E0101\narc: B5 H00R0000\narc: C0 H00R0100\narc: C1 V02N0601\narc: C4 V00B0100\narc: C5 V02S0001\narc: CE1 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V00T0100\narc: D4 H01W0000\narc: D5 H02W0201\narc: E1_H01E0001 Q0\narc: E1_H02E0201 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F5\narc: H01W0100 Q0\narc: M2 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: V01S0100 F1\narc: W1_H02W0201 Q0\narc: W1_H02W0601 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111110000000\nword: SLICEA.K1.INIT 0000000011001010\nword: SLICEC.K0.INIT 1111111110000000\nword: SLICEC.K1.INIT 0000000011001010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R34C23:PLC2\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0601 N1_V01S0000\narc: H00R0000 V02S0401\narc: H00R0100 V02N0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 N3_V06S0203\narc: S1_V02S0101 H02W0101\narc: S1_V02S0701 H02W0701\narc: V00B0000 V02S0201\narc: V00T0000 V02N0601\narc: V00T0100 H02W0301\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 V02S0701\narc: W3_H06W0103 E3_H06W0103\narc: A7 V02S0101\narc: B4 V02S0501\narc: B7 E1_H02W0301\narc: C4 H02W0601\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D4 H02E0001\narc: D5 V00B0000\narc: D7 E1_H01W0100\narc: E1_H01E0001 F7\narc: E1_H02E0701 Q7\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q0\narc: M0 V00B0000\narc: M2 H02W0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q4\narc: S1_V02S0501 F7\narc: V01S0000 F7\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111000001111100\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R34C24:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 W1_H02E0201\narc: H00R0000 V02N0401\narc: H00R0100 H02E0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H06W0203\narc: N3_V06N0103 H06E0103\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0103 N1_V01S0100\narc: V00B0000 H02W0601\narc: V00B0100 S1_V02N0101\narc: V00T0000 N1_V02S0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 V06S0203\narc: A4 V02N0101\narc: A5 H02E0701\narc: A7 V02N0301\narc: B4 H00R0000\narc: B5 H00L0000\narc: B7 V02S0701\narc: C4 V00T0100\narc: C5 E1_H02W0401\narc: C7 F4\narc: CE0 N1_V02S0201\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 V02S0601\narc: D7 H01W0000\narc: E3_H06E0303 F6\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F5\narc: H01W0100 F6\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 H02E0601\narc: M2 H02E0601\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q2\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0001010100111111\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R34C25:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0103 V06N0103\narc: H00L0100 V02N0301\narc: H00R0000 V02N0601\narc: H00R0100 S1_V02N0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H06W0303\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0701 E1_H02W0701\narc: V00B0000 W1_H02E0401\narc: V00B0100 E1_H02W0701\narc: V00T0000 V02N0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0601 S1_V02N0601\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A4 H02E0701\narc: A5 E1_H02W0501\narc: A7 V02N0301\narc: B0 H01W0100\narc: B2 H00L0000\narc: B4 V02N0501\narc: B5 V00B0100\narc: B7 V01S0000\narc: C0 V02S0601\narc: C2 V02S0601\narc: C4 V02S0201\narc: C5 H02W0601\narc: C7 E1_H01E0101\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H02E0001\narc: D2 V02N0001\narc: D3 H02E0001\narc: D4 H00L0100\narc: D5 H00R0100\narc: D7 S1_V02N0401\narc: E1_H01E0101 F5\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q2\narc: H01W0100 Q0\narc: M0 V00B0000\narc: M2 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F6\narc: V01S0000 F4\narc: V01S0100 Q2\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 1010101010001010\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0111011101110011\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R34C26:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 E1_H01W0000\narc: H00L0100 V02N0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02W0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 N3_V06S0303\narc: V00T0000 V02S0601\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 V01N0001\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A1 E1_H01E0001\narc: A2 V02N0501\narc: A3 V02S0501\narc: A4 V02N0101\narc: A5 V00B0000\narc: B1 H00R0100\narc: B2 E1_H01W0100\narc: B3 W1_H02E0101\narc: B4 E1_H02W0101\narc: B5 W1_H02E0101\narc: C1 H00L0100\narc: C2 V02S0601\narc: C3 V02N0601\narc: C4 V00T0000\narc: C5 V02S0201\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 V01S0100\narc: D3 S1_V02N0201\narc: D4 H01W0000\narc: D5 H02E0201\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q4\narc: E1_H02E0001 Q2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F5\narc: H01W0100 F1\narc: M6 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: V00B0000 Q4\narc: V01S0100 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000100000\nword: SLICEB.K0.INIT 1111111110000000\nword: SLICEB.K1.INIT 0000000011001010\nword: SLICEC.K0.INIT 1111111110000000\nword: SLICEC.K1.INIT 0000000011001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R34C27:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 V06S0203\narc: H00L0000 V02S0001\narc: H00L0100 E1_H02W0301\narc: H00R0100 W1_H02E0501\narc: N1_V02N0101 H06W0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 H01E0101\narc: S3_V06S0303 N1_V02S0601\narc: V00B0000 H02W0601\narc: V00T0000 H02W0201\narc: V00T0100 V02N0701\narc: W1_H02W0701 V06S0203\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0203 V06S0203\narc: W3_H06W0003 E3_H06W0003\narc: A1 H00L0000\narc: A5 V00T0000\narc: A6 H02E0501\narc: A7 W1_H02E0701\narc: B1 H02E0301\narc: B5 H00R0000\narc: B6 H01E0101\narc: B7 V02S0701\narc: C1 H00L0100\narc: C5 H02E0601\narc: C6 V02N0201\narc: C7 H02E0401\narc: CE0 H02E0101\narc: CE1 V02S0201\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D5 H00R0100\narc: D6 H02W0201\narc: D7 V00B0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 F1\narc: E1_H02E0201 Q2\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H01W0000 F7\narc: H01W0100 F1\narc: M2 E1_H02W0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F1\narc: N1_V02N0601 F4\narc: S1_V02S0301 Q1\narc: W1_H02W0301 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0111000001111100\nword: SLICED.K0.INIT 0101001111111111\nword: SLICED.K1.INIT 1010101010001010\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0111011101110011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R34C28:PLC2\narc: H00L0000 H02E0201\narc: H00L0100 V02N0301\narc: H00R0000 H02E0401\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H02E0701\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 H01E0001\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 H02E0601\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 H02E0401\narc: V00B0100 E1_H02W0701\narc: V00T0000 E1_H02W0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 S1_V02N0601\narc: H01W0000 W3_H06E0103\narc: W3_H06W0303 N3_V06S0303\narc: A1 H00L0000\narc: A3 H00L0100\narc: A4 E1_H01W0000\narc: A5 N1_V01N0101\narc: B1 V00B0000\narc: B3 H01W0100\narc: B4 E1_H02W0301\narc: B5 H00R0000\narc: C1 H02W0401\narc: C3 N1_V01N0001\narc: C4 V00T0000\narc: C5 H02W0401\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D3 V00T0100\narc: D4 V01N0001\narc: D5 S1_V02N0601\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 F4\narc: M2 V00B0100\narc: M6 E1_H02W0401\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q6\narc: N1_V02N0201 F2\narc: V00T0100 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000100000\nword: SLICEC.K0.INIT 0101001111111111\nword: SLICEC.K1.INIT 1010101010001010\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111011101110011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R34C29:PLC2\narc: E1_H02E0201 V06S0103\narc: E1_H02E0701 E1_H01W0100\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02N0601\narc: H00R0100 V02S0701\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 N1_V02S0201\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02W0501\narc: V00T0000 S1_V02N0401\narc: V00T0100 W1_H02E0301\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0103 E3_H06W0003\narc: A5 V00T0000\narc: B0 H01W0100\narc: B2 H00L0000\narc: B5 S1_V02N0701\narc: C0 H00L0100\narc: C2 H00L0100\narc: C5 E1_H02W0601\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 N1_V02S0001\narc: D2 H00R0000\narc: D3 N1_V02S0001\narc: D5 H00R0100\narc: E1_H01E0101 Q2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H00L0000 Q2\narc: H01W0000 Q0\narc: H01W0100 Q0\narc: M0 V00B0000\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111111100000000\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R34C2:PLC2\narc: E1_H02E0601 N1_V02S0601\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0203 S1_V02N0701\narc: V00B0100 V02N0101\narc: V00T0100 S1_V02N0701\narc: V01S0100 N3_V06S0303\narc: B1 S1_V02N0301\narc: C1 N1_V01N0001\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: E1_H01E0001 F1\narc: F1 F1_SLICE\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q4\narc: V00B0000 Q6\narc: V01S0000 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100110011110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R34C30:PLC2\narc: E1_H02E0301 N1_V01S0100\narc: H00L0000 H02W0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02E0201\narc: N1_V02N0601 H02W0601\narc: V00T0000 S1_V02N0401\narc: V00T0100 V02S0501\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 V01N0101\narc: W1_H02W0701 V02N0701\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0303 W3_H06E0303\narc: A7 H02E0701\narc: B7 H01E0101\narc: C7 V00T0000\narc: CE0 H00L0000\narc: CLK0 G_HPBX0000\narc: D7 H02W0201\narc: E1_H01E0101 F7\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: M0 V00T0100\narc: MUXCLK0 CLK0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R34C31:PLC2\narc: E1_H02E0601 N3_V06S0303\narc: H00L0100 V02S0301\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N3_V06S0303\narc: V00B0000 E1_H02W0401\narc: V00T0000 V02S0601\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 S1_V02N0601\narc: E1_H01E0001 W3_H06E0003\narc: N3_V06N0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: H01W0100 Q6\narc: M0 V00B0000\narc: M2 E1_H02W0601\narc: M4 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q2\narc: N3_V06N0003 Q0\narc: W3_H06W0003 Q0\narc: W3_H06W0103 Q2\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R34C32:PLC2\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 H02E0601\narc: N3_V06N0303 E3_H06W0303\narc: W3_H06W0303 V06S0303\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\n\n.tile R34C33:PLC2\narc: E1_H02E0601 V06S0303\narc: E3_H06E0003 V06S0003\narc: N1_V02N0401 S1_V02N0101\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N1_V02S0101\narc: S3_V06S0103 N3_V06S0003\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 E1_H02W0601\narc: W3_H06W0003 V06S0003\n\n.tile R34C34:PLC2\narc: E3_H06E0103 N3_V06S0103\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 H06E0303\n\n.tile R34C35:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 W1_H02E0601\narc: E3_H06E0103 N3_V06S0103\narc: H00L0100 V02S0301\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0701 H06E0203\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02S0401\narc: W3_H06W0003 E3_H06W0003\narc: CE0 H02W0101\narc: CE2 V02S0601\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: M0 V00T0000\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W1_H02W0201 Q0\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R34C36:PLC2\narc: E1_H02E0301 V06S0003\narc: E1_H02E0701 H01E0101\narc: H00L0000 V02S0001\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 H06E0003\narc: N1_V02N0601 N3_V06S0303\narc: V00B0000 N1_V02S0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 S1_V02N0601\narc: V00T0100 H02E0301\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 V02S0101\narc: N1_V02N0501 W3_H06E0303\narc: A5 H02E0501\narc: B5 N1_V01S0000\narc: C5 H02E0401\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: E1_H01E0101 Q6\narc: E1_H02E0001 Q0\narc: E1_H02E0201 Q2\narc: E1_H02E0401 F4\narc: F4 F5C_SLICE\narc: H01W0100 Q0\narc: M0 V00B0100\narc: M2 H02E0601\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000001011000011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R34C37:PLC2\narc: E1_H02E0201 V06S0103\narc: H00L0000 H02E0201\narc: H00L0100 N1_V02S0101\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 N3_V06S0203\narc: V00B0100 H02W0701\narc: V00T0000 H02E0001\narc: W3_H06W0003 E3_H06W0003\narc: A0 H02E0701\narc: A1 E1_H01E0001\narc: A2 V01N0101\narc: A3 V01N0101\narc: A5 V00T0000\narc: A6 H00L0000\narc: A7 S1_V02N0101\narc: B0 H02E0301\narc: B1 E1_H02W0301\narc: B2 E1_H01W0100\narc: B3 E1_H01W0100\narc: B5 S1_V02N0701\narc: B6 V00B0100\narc: B7 H01E0101\narc: C0 H02E0401\narc: C1 F6\narc: C2 V02S0601\narc: C3 V02S0601\narc: C5 V02S0201\narc: C6 E1_H01E0101\narc: C7 V02S0201\narc: D0 V01S0100\narc: D1 H00R0000\narc: D2 W1_H02E0001\narc: D3 W1_H02E0001\narc: D5 H00L0100\narc: D6 H01W0000\narc: D7 N1_V02S0401\narc: E1_H01E0001 F2\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H01W0000 F3\narc: M4 E1_H02W0401\narc: N3_V06N0003 F0\narc: V01S0100 F1\nword: SLICED.K0.INIT 1001000000000000\nword: SLICED.K1.INIT 1100010000110001\nword: SLICEA.K0.INIT 1001000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 1010111100100011\nword: SLICEB.K1.INIT 1100010011110101\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100111101000101\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R34C38:PLC2\narc: E1_H02E0301 N1_V02S0301\narc: H00R0000 V02N0401\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 S1_V02N0101\narc: S1_V02S0001 H02W0001\narc: S1_V02S0301 N3_V06S0003\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 H02W0601\narc: V00B0100 S1_V02N0301\narc: V00T0100 H02W0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0701 V06S0203\narc: A2 V00T0000\narc: A3 V00T0000\narc: B2 V01N0001\narc: B3 V01N0001\narc: C2 N1_V02S0601\narc: C3 N1_V02S0601\narc: CE0 V02N0201\narc: CE2 H00R0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D2 H02E0201\narc: D3 H02E0201\narc: E1_H01E0001 F3\narc: E1_H01E0101 F2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0100 Q4\narc: M0 V00T0100\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V00T0000 Q0\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1000110010101111\nword: SLICEB.K1.INIT 1111010100110001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R34C39:PLC2\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 V02S0001\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 N1_V01S0100\narc: V00T0000 N1_V02S0401\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 H01E0001\narc: W1_H02W0001 W3_H06E0003\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: M6 V00T0000\narc: MUXCLK3 CLK0\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R34C3:PLC2\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0601 H02E0601\narc: S3_V06S0203 H01E0001\n\n.tile R34C40:PLC2\narc: E1_H02E0301 N1_V02S0301\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0601 H02E0601\narc: E3_H06E0103 W3_H06E0103\n\n.tile R34C41:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 V06S0303\narc: H00R0100 V02N0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0301 V01N0101\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 H02W0601\narc: V00T0100 V02S0701\narc: V01S0100 N3_V06S0303\narc: H01W0000 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: A1 V02N0501\narc: B0 H00R0100\narc: B1 V02S0101\narc: C0 H00L0100\narc: C1 V02S0401\narc: D0 V00T0100\narc: D1 S1_V02N0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: H00L0100 F1\narc: N3_V06N0003 F0\nword: SLICEA.K0.INIT 0000000011110011\nword: SLICEA.K1.INIT 1001010001001111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R34C42:PLC2\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 V01N0101\narc: E1_H02E0601 V06S0303\narc: H00L0000 V02S0001\narc: H00L0100 V02N0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02N0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 H06E0203\narc: S1_V02S0201 N1_V02S0701\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02E0001\narc: V00T0100 H02E0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0601 N1_V01S0000\narc: A0 V02S0501\narc: A3 H00L0100\narc: A5 V02N0101\narc: B0 V00T0000\narc: B3 H02W0101\narc: B5 H02W0101\narc: C0 H00R0100\narc: C3 H00L0000\narc: C5 V00B0100\narc: D0 H00R0000\narc: D3 H02W0001\narc: D5 H02E0201\narc: E1_H01E0001 F4\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: M0 E1_H02W0601\narc: M2 V00T0100\narc: M4 V00T0100\narc: N1_V01N0101 F2\narc: W3_H06W0003 F0\nword: SLICEA.K0.INIT 0011101101111111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0110101110110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0110101110110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R34C43:PLC2\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0003 V06S0003\narc: H00L0000 S1_V02N0201\narc: H00L0100 V02S0101\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 H02W0701\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02E0601\narc: V00B0100 V02S0301\narc: V00T0000 H02W0201\narc: V00T0100 V02N0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V02S0101\narc: W3_H06W0003 V06S0003\narc: A1 H00L0100\narc: A5 V02S0101\narc: A7 W1_H02E0501\narc: B0 W1_H02E0301\narc: B1 V02N0101\narc: B5 H00L0000\narc: B7 V02S0501\narc: C0 N1_V01N0001\narc: C1 N1_V01S0100\narc: C5 V00B0100\narc: C7 V00T0000\narc: D0 H02E0201\narc: D1 H02W0201\narc: D5 V00B0000\narc: D7 V02S0601\narc: E1_H01E0001 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M4 V00T0100\narc: N1_V01N0001 F1\narc: W1_H02W0201 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100010010000000\nword: SLICEA.K0.INIT 0000000011110011\nword: SLICEA.K1.INIT 1001001000101111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0110110111010000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R34C44:PLC2\narc: E1_H02E0401 N3_V06S0203\narc: E3_H06E0103 N1_V01S0100\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0601 H02E0601\narc: N3_V06N0203 E3_H06W0203\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 N1_V02S0701\narc: W1_H02W0201 V06S0103\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 N3_V06S0203\n\n.tile R34C45:PLC2\narc: E1_H02E0201 V06S0103\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 N1_V01S0100\narc: V01S0000 N3_V06S0103\n\n.tile R34C46:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0401 E1_H01W0000\narc: H00R0000 V02S0401\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0303 E3_H06W0303\narc: S3_V06S0003 N3_V06S0003\narc: V00T0100 V02S0701\narc: E3_H06E0203 W3_H06E0103\narc: A7 H00R0000\narc: B7 N1_V02S0701\narc: C7 V00T0100\narc: D7 V02N0401\narc: F7 F7_SLICE\narc: H01W0000 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000010000100001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R34C47:PLC2\narc: E1_H02E0201 V06N0103\narc: E1_H02E0701 V02S0701\narc: H00R0000 H02W0601\narc: H00R0100 H02W0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0401 N3_V06S0203\narc: S3_V06S0203 N3_V06S0103\narc: V00B0000 H02W0401\narc: V00T0000 W1_H02E0201\narc: V00T0100 N1_V02S0501\narc: W3_H06W0303 N3_V06S0303\narc: A7 N1_V01S0100\narc: B7 H02W0301\narc: C7 V00T0100\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D7 E1_H02W0001\narc: E1_H01E0101 F7\narc: E1_H02E0601 Q4\narc: E3_H06E0003 Q0\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000010000100001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R34C48:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0601 V02S0601\narc: H00R0000 E1_H02W0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 H02E0701\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02S0101\narc: V00T0100 W1_H02E0101\narc: W1_H02W0301 V02S0301\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 V02S0701\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q0\narc: E1_H02E0001 Q2\narc: M0 H02W0601\narc: M2 V00B0000\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W1_H02W0401 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R34C49:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 W1_H02E0601\narc: H00R0000 H02E0601\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 W1_H02E0201\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0601 N3_V06S0303\narc: V00B0000 V02S0001\narc: V00B0100 V02N0301\narc: V00T0000 V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0601 H01E0001\narc: W1_H02W0001 W3_H06E0003\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 V02S0601\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q0\narc: H01W0100 Q6\narc: M0 V00T0100\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0000 Q4\narc: V01S0100 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R34C4:PLC2\narc: E1_H02E0501 V06S0303\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H02W0701\narc: S1_V02S0501 N3_V06S0303\n\n.tile R34C50:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 N1_V01S0100\narc: H00L0000 H02E0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 H02E0401\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 E1_H01W0000\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0401 N3_V06S0203\narc: V00B0000 H02W0601\narc: V00B0100 H02E0701\narc: V00T0000 H02E0201\narc: V01S0100 N3_V06S0303\narc: W1_H02W0401 V02S0401\narc: W1_H02W0101 W3_H06E0103\narc: A0 H00L0000\narc: A2 V00T0000\narc: A3 H00L0100\narc: A4 V00B0000\narc: A5 H02W0501\narc: A6 H02E0501\narc: A7 H00R0000\narc: B2 V01N0001\narc: B3 W1_H02E0101\narc: B4 H01E0101\narc: B5 V00B0100\narc: B6 V02N0701\narc: B7 H02E0101\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F2\narc: N1_V02N0301 F3\narc: N1_V02N0501 F5\narc: N3_V06N0203 F7\narc: W3_H06W0203 F4\narc: W3_H06W0303 F6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R34C51:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0003 V06N0003\narc: E3_H06E0103 V06N0103\narc: H00L0000 N1_V02S0001\narc: H00L0100 H02E0301\narc: H00R0000 H02E0401\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 N3_V06S0203\narc: V00B0000 E1_H02W0401\narc: V00T0000 H02W0201\narc: V00T0100 H02W0301\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 N1_V02S0601\narc: W3_H06W0003 N3_V06S0003\narc: A0 H00L0100\narc: A1 H00L0000\narc: A2 V00B0000\narc: A3 N1_V02S0701\narc: A4 V00T0100\narc: A5 V00T0000\narc: A6 H02W0701\narc: A7 H00R0000\narc: B0 V02N0301\narc: B1 H02E0101\narc: B2 V01N0001\narc: B3 V02N0101\narc: B4 W1_H02E0301\narc: B5 E1_H02W0301\narc: B6 V02N0501\narc: B7 V02S0501\narc: E1_H01E0001 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F0\narc: N1_V01N0001 F7\narc: N1_V01N0101 F5\narc: N1_V02N0301 F3\narc: N1_V02N0401 F4\narc: V01S0000 F2\narc: V01S0100 F6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R34C52:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 V02S0501\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 E1_H02W0001\narc: H00L0100 H02E0101\narc: H00R0000 N1_V02S0601\narc: H00R0100 W1_H02E0501\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H02E0601\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 H02E0401\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0601\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0701 N1_V02S0701\narc: E3_H06E0203 W3_H06E0203\narc: A0 H00L0000\narc: A1 H02W0501\narc: A2 H00L0100\narc: A3 N1_V02S0501\narc: A4 V00B0000\narc: A5 V00T0000\narc: A6 H00R0000\narc: A7 H00R0000\narc: B0 V01N0001\narc: B1 H00R0100\narc: B2 S1_V02N0101\narc: B3 V02N0101\narc: B4 V00B0100\narc: B5 V02N0701\narc: B6 H02E0301\narc: B7 V02N0501\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F1\narc: N1_V01N0001 F5\narc: N1_V02N0001 F2\narc: N3_V06N0003 F3\narc: N3_V06N0203 F7\narc: V01S0000 F4\narc: V01S0100 F0\narc: W3_H06W0303 F6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R34C53:PLC2\narc: H00R0000 H02W0601\narc: H00R0100 H02E0501\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0701 H02E0701\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 V01N0101\narc: V00B0000 H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 V02S0401\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0303 V06N0303\narc: A0 H00R0000\narc: A1 H00R0000\narc: A2 V00B0000\narc: A3 V00B0000\narc: A4 V00B0000\narc: A5 V00B0000\narc: A6 H00R0000\narc: A7 H00R0000\narc: B0 V00T0000\narc: B1 V02S0101\narc: B2 V01N0001\narc: B3 H00R0100\narc: B4 H02E0301\narc: B5 V00B0100\narc: B6 V02N0701\narc: B7 S1_V02N0701\narc: E1_H01E0001 F6\narc: E1_H01E0101 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F7\narc: N1_V02N0001 F2\narc: N1_V02N0101 F3\narc: V01S0000 F1\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R34C54:PLC2\narc: H00R0000 N1_V02S0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0103 H06E0103\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0601 N1_V02S0601\narc: A0 H00R0000\narc: A1 H00R0000\narc: B0 V02N0101\narc: B1 H00R0100\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: N1_V02N0201 F0\narc: V01S0100 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R34C55:PLC2\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 N3_V06S0303\n\n.tile R34C56:PLC2\narc: N1_V02N0001 N1_V01S0000\narc: S1_V02S0101 N3_V06S0103\narc: W3_H06W0103 V06N0103\n\n.tile R34C57:PLC2\narc: E1_H02E0601 V06S0303\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0601 N1_V02S0301\narc: V01S0000 N3_V06S0103\narc: N3_V06N0003 W3_H06E0003\n\n.tile R34C58:PLC2\narc: S1_V02S0001 N3_V06S0003\narc: S3_V06S0203 N3_V06S0203\narc: E3_H06E0303 W3_H06E0203\n\n.tile R34C59:PLC2\narc: S1_V02S0601 W1_H02E0601\n\n.tile R34C5:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0501 N1_V02S0501\narc: H00R0000 H02W0601\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 S1_V02N0601\narc: V00B0000 V02S0001\narc: V00B0100 H02W0501\narc: W1_H02W0701 N3_V06S0203\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: H01W0000 Q4\narc: H01W0100 Q6\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q4\narc: N1_V02N0401 Q6\narc: N1_V02N0601 Q6\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R34C64:PLC2\narc: E3_H06E0003 W3_H06E0303\n\n.tile R34C69:PLC2\narc: S3_V06S0203 N3_V06S0103\n\n.tile R34C6:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 N1_V02S0601\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02W0401\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 N1_V01S0100\narc: V00B0100 H02E0501\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02W0101\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 N3_V06S0303\narc: W3_H06W0003 N1_V01S0000\narc: A3 V02N0501\narc: A6 E1_H01W0000\narc: B3 H00R0100\narc: B6 H02W0301\narc: C1 N1_V01N0001\narc: C3 E1_H02W0401\narc: C6 V00T0000\narc: C7 V02S0001\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D3 V01S0100\narc: D6 H00L0100\narc: D7 V02N0601\narc: E1_H01E0001 F2\narc: E1_H01E0101 Q4\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0000 F1\narc: M2 V00B0000\narc: M4 V00T0100\narc: MUXCLK2 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q4\narc: V00B0000 F6\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011110000\nword: SLICED.K0.INIT 1000010010100101\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000100001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R34C70:PLC2\narc: E1_H02E0501 N3_V06S0303\narc: N1_V02N0301 S1_V02N0201\narc: S3_V06S0103 N3_V06S0003\narc: S3_V06S0303 N3_V06S0303\narc: S3_V06S0003 W3_H06E0003\n\n.tile R34C7:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 V01N0101\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 H01E0101\narc: H00L0100 H02E0301\narc: H00R0000 H02E0401\narc: H00R0100 V02N0501\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 H01E0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 H02W0501\narc: V00B0100 H02W0701\narc: V00T0000 V02N0601\narc: V00T0100 H02W0101\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 N3_V06S0203\narc: A0 S1_V02N0501\narc: A1 S1_V02N0501\narc: A3 E1_H02W0701\narc: A7 E1_H01W0000\narc: B0 V02S0301\narc: B1 V02S0301\narc: B3 V01N0001\narc: B7 E1_H02W0101\narc: C0 H00L0100\narc: C1 H00L0100\narc: C3 V02N0601\narc: C7 V00T0000\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 W1_H02E0001\narc: D3 H00R0000\narc: D7 H00R0100\narc: E1_H01E0101 Q4\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: M0 V00B0100\narc: M2 H02E0601\narc: M4 V00T0100\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: N1_V02N0001 F0\narc: N1_V02N0501 F7\narc: V01S0000 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111010100110001\nword: SLICEA.K0.INIT 0000000001000101\nword: SLICEA.K1.INIT 0000000010001010\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000110000100011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R34C8:PLC2\narc: H00R0000 N1_V02S0601\narc: H00R0100 V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 N1_V01S0100\narc: V00B0000 V02S0001\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02S0501\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0701 N3_V06S0203\narc: A3 H02E0701\narc: A4 V02N0101\narc: A5 V00T0000\narc: A7 V02N0101\narc: B2 F3\narc: B3 H02E0301\narc: B4 H01E0101\narc: B5 V02N0701\narc: B7 V02N0701\narc: C2 N1_V01N0001\narc: C3 W1_H02E0401\narc: C4 H02E0601\narc: C5 V00T0100\narc: C7 H02E0601\narc: CE0 H02E0101\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 H00R0000\narc: D4 V02N0401\narc: D5 V02N0401\narc: D7 H00R0100\narc: E1_H01E0101 Q0\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 F2\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: N1_V01N0001 F7\narc: V00B0100 F5\narc: V01S0000 F4\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1010111100100011\nword: SLICEB.K0.INIT 1100000000000000\nword: SLICEB.K1.INIT 1100001101000001\nword: SLICEC.K0.INIT 1111010100110001\nword: SLICEC.K1.INIT 1000101011001111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R34C9:PLC2\narc: E1_H02E0601 N3_V06S0303\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 N3_V06S0003\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0701 H01E0101\narc: W3_H06W0203 E3_H06W0103\n\n.tile R35C11:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: N1_V02N0601 H02W0601\n\n.tile R35C12:PLC2\narc: E1_H02E0201 V06S0103\narc: E3_H06E0203 N3_V06S0203\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0501 N1_V01S0100\narc: S1_V02S0401 N3_V06S0203\narc: W1_H02W0601 N3_V06S0303\n\n.tile R35C13:PLC2\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0701 N1_V02S0701\narc: H00R0100 H02W0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 H02E0201\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0601 N3_V06S0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02S0101\narc: V00T0100 H02W0101\narc: A4 V00T0000\narc: B4 V00B0100\narc: C4 V00T0100\narc: C5 V00T0000\narc: CE0 H00R0100\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D4 V02N0601\narc: D5 V02N0401\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: M0 V00B0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V02N0501 F5\narc: N1_V02N0601 F4\narc: V00T0000 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1010101010001010\nword: SLICEC.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R35C14:PLC2\narc: E1_H02E0401 V02N0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H02E0401\narc: S1_V02S0501 N3_V06S0303\narc: V00B0100 H02W0701\narc: V00T0100 V02S0701\narc: W1_H02W0101 N3_V06S0103\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0701 V06S0203\narc: A3 V00B0000\narc: B3 H00R0000\narc: C3 V02N0601\narc: CE2 H02W0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 V02N0001\narc: F3 F3_SLICE\narc: H00R0000 Q6\narc: H01W0000 F3\narc: LSR1 V00B0100\narc: M4 V00T0100\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: V00B0000 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R35C15:PLC2\narc: E1_H02E0401 V02N0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 W1_H02E0701\narc: V00B0000 H02W0601\narc: V00B0100 E1_H02W0701\narc: V00T0100 H02W0301\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0303 E3_H06W0203\narc: B4 H00R0000\narc: C4 E1_H02W0401\narc: CE0 H02W0101\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 H00R0100\narc: F4 F5C_SLICE\narc: H00R0000 Q4\narc: M0 V00B0100\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q0\narc: N1_V02N0401 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R35C16:PLC2\narc: E1_H02E0601 V02N0601\narc: H00R0000 V02N0401\narc: H00R0100 E1_H02W0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 N3_V06S0103\narc: V00B0000 V02N0001\narc: V00B0100 E1_H02W0501\narc: V00T0000 V02S0601\narc: V00T0100 N1_V02S0501\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0601 V02N0601\narc: A3 V02S0701\narc: A6 N1_V01N0101\narc: A7 E1_H01W0000\narc: B3 H00R0000\narc: B6 V01S0000\narc: B7 V02S0501\narc: C3 F6\narc: C6 V00T0100\narc: C7 W1_H02E0401\narc: CE0 H00R0100\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D3 V01S0100\narc: D6 V00B0000\narc: D7 N1_V02S0601\narc: E1_H02E0201 F2\narc: E3_H06E0103 F2\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00B0100\narc: M2 H02W0601\narc: M4 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q4\narc: V01S0000 Q0\narc: V01S0100 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0001010100111111\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R35C17:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0601 N3_V06S0303\narc: H00L0000 V02S0001\narc: H00L0100 S1_V02N0301\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0601 H02W0601\narc: S1_V02S0601 N3_V06S0303\narc: V00B0000 H02W0401\narc: V00B0100 V02N0101\narc: W1_H02W0101 V06S0103\narc: W1_H02W0401 V06S0203\narc: W1_H02W0701 V06S0203\narc: A5 V00T0000\narc: A7 E1_H01W0000\narc: B5 H00L0000\narc: B7 N1_V01S0000\narc: C5 W1_H02E0401\narc: C7 V02N0001\narc: CE0 E1_H02W0101\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D5 H02W0001\narc: D7 E1_H02W0201\narc: E1_H01E0101 F7\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: M0 V00B0100\narc: M2 V00B0000\narc: M4 E1_H01E0101\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: V00T0000 Q0\narc: W1_H02W0601 F4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R35C18:PLC2\narc: E1_H02E0601 V02N0601\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 N3_V06S0303\narc: V00B0000 W1_H02E0601\narc: V00B0100 V02S0101\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 E1_H02W0601\narc: E1_H02E0701 W3_H06E0203\narc: E3_H06E0203 W3_H06E0203\narc: B4 H00R0000\narc: C4 V02N0201\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 N1_V02S0401\narc: F4 F5C_SLICE\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: M4 V00B0100\narc: MUXCLK2 CLK0\nword: SLICEC.K0.INIT 1111000011001100\nword: SLICEC.K1.INIT 1111111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R35C19:PLC2\narc: E1_H02E0601 W1_H02E0601\narc: H00R0000 V02N0601\narc: H00R0100 H02W0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0401 N3_V06S0203\narc: S1_V02S0701 H02E0701\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0501 N3_V06S0303\narc: W3_H06W0203 E3_H06W0103\narc: A1 E1_H01E0001\narc: B1 H01W0100\narc: C1 H02E0601\narc: CE2 W1_H02E0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: E1_H01E0001 Q4\narc: E1_H02E0301 F1\narc: F1 F1_SLICE\narc: H01W0100 Q6\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M4 V00B0100\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R35C20:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E3_H06E0303 V06S0303\narc: H00R0100 H02W0701\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0301 H02E0301\narc: N1_V02N0601 H02W0601\narc: S1_V02S0201 N3_V06S0103\narc: V00B0100 V02S0101\narc: V00T0100 V02N0501\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 V06S0303\narc: A3 V00B0000\narc: B3 E1_H01W0100\narc: C3 V02N0401\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: F3 F3_SLICE\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: V00B0000 Q4\narc: V01S0000 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R35C21:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0501 N3_V06S0303\narc: E3_H06E0003 N1_V01S0000\narc: H00L0000 V02S0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H06E0203\narc: V00B0100 V02S0301\narc: W1_H02W0601 N3_V06S0303\narc: W1_H02W0701 V06S0203\narc: W3_H06W0203 E3_H06W0103\narc: CE0 H00L0000\narc: CLK0 G_HPBX0000\narc: H01W0100 Q0\narc: M0 V00B0100\narc: MUXCLK0 CLK0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R35C22:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: H00L0000 V02N0201\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0601 E1_H02W0601\narc: E3_H06E0203 W3_H06E0103\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H02E0601 Q4\narc: M4 H02W0401\narc: MUXCLK2 CLK0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R35C23:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0501 E1_H01W0100\narc: E3_H06E0203 N3_V06S0203\narc: H00R0000 H02W0401\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0101 H02E0101\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N3_V06S0303\narc: V00B0000 H02E0601\narc: V00B0100 V02S0101\narc: V00T0000 V02N0401\narc: V00T0100 V02S0501\narc: V01S0000 N3_V06S0103\narc: W1_H02W0401 E1_H02W0401\narc: A5 V00B0000\narc: B5 V02S0701\narc: C5 V02N0201\narc: CE0 E1_H02W0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D5 V02N0601\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q6\narc: F5 F5_SLICE\narc: LSR0 V00T0000\narc: LSR1 V00B0100\narc: M0 V00T0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000100000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R35C24:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 N3_V06S0303\narc: H00R0000 V02N0601\narc: H00R0100 H02W0501\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0101 N3_V06S0103\narc: V00T0000 V02S0601\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 N3_V06S0303\narc: S1_V02S0401 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: A3 V00B0000\narc: A5 H02E0501\narc: B0 H01W0100\narc: B3 H02W0301\narc: B5 V02S0701\narc: C0 E1_H02W0401\narc: C3 V02N0401\narc: C5 V02N0001\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H02E0201\narc: D3 H02W0201\narc: D5 H02E0001\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q0\narc: M0 V00T0000\narc: M2 N1_V01N0001\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F5\narc: V00B0000 Q6\narc: V01S0100 F2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R35C25:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E1_H02E0301 V01N0101\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 V02N0701\narc: H00R0100 H02W0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H02E0601\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 W1_H02E0201\narc: V00T0100 H02W0301\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E1_H02W0301\narc: W3_H06W0103 N3_V06S0103\narc: A7 H02E0501\narc: B7 V02S0701\narc: C7 V00T0100\narc: CE0 V02N0201\narc: CE1 H00R0100\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: F7 F7_SLICE\narc: H01W0100 Q4\narc: M0 E1_H02W0601\narc: M2 V00B0100\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V02N0201 Q0\narc: V01S0000 F7\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000100000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R35C26:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V02N0401\narc: E1_H02E0701 S1_V02N0701\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 H06E0203\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0401 N3_V06S0203\narc: W1_H02W0701 V06S0203\narc: E1_H02E0501 W3_H06E0303\narc: H01W0100 W3_H06E0303\n\n.tile R35C27:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 V02N0401\narc: E3_H06E0203 N3_V06S0203\narc: H00R0100 H02E0501\narc: N1_V02N0201 H02W0201\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 S1_V02N0301\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 H06E0303\narc: V00B0000 V02N0201\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02W0101\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V06S0303\narc: W3_H06W0103 E3_H06W0103\narc: A3 W1_H02E0701\narc: A6 H00L0000\narc: A7 V02S0301\narc: B3 W1_H02E0301\narc: B6 H02E0301\narc: B7 V00B0000\narc: C3 F6\narc: C6 W1_H02E0601\narc: C7 H02E0401\narc: CE0 H02E0101\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: D6 N1_V02S0601\narc: D7 V02N0601\narc: E3_H06E0103 F2\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0100 Q4\narc: LSR0 H02W0301\narc: LSR1 V00T0100\narc: M0 V00T0000\narc: M2 E1_H02W0601\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: N1_V02N0001 F2\narc: V00B0100 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0001001101011111\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R35C28:PLC2\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0701 W1_H02E0701\narc: H00R0000 V02N0601\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0301 N3_V06S0003\narc: S1_V02S0701 N1_V02S0701\narc: V00B0000 V02S0001\narc: V00B0100 N1_V02S0101\narc: V00T0100 H02E0301\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 E1_H02W0201\narc: W3_H06W0003 N3_V06S0003\narc: E3_H06E0303 W3_H06E0203\narc: A5 V00T0000\narc: A7 H00L0000\narc: B0 H01W0100\narc: B5 H02E0101\narc: B7 V00B0000\narc: C0 N1_V02S0401\narc: C5 H02E0401\narc: C7 V02N0001\narc: CE1 S1_V02N0201\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V02S0201\narc: D5 S1_V02N0401\narc: D7 V02S0601\narc: E1_H01E0001 F4\narc: E1_H01E0101 F7\narc: F0 F5A_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0100 Q0\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 E1_H01E0101\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: V00T0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R35C29:PLC2\narc: H00L0100 H02W0101\narc: H00R0100 H02E0501\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02W0601\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0401 N1_V02S0101\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0701\narc: V00T0000 H02W0201\narc: W1_H02W0601 H01E0001\narc: A1 V02N0501\narc: A7 V02N0101\narc: B1 V02S0101\narc: B7 V00B0000\narc: C1 V02N0601\narc: C7 V00B0100\narc: CE1 V02S0201\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D7 H00L0100\narc: F1 F1_SLICE\narc: F6 F5D_SLICE\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M2 E1_H02W0601\narc: M4 H02W0401\narc: M6 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N3_V06N0303 F6\narc: V00T0100 F1\narc: V01S0000 Q2\narc: V01S0100 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R35C2:PLC2\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 E1_H01W0000\n\n.tile R35C30:PLC2\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0701 H06E0203\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 N3_V06S0303\narc: W1_H02W0601 N3_V06S0303\narc: S1_V02S0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\n\n.tile R35C31:PLC2\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0601 N3_V06S0303\narc: W1_H02W0601 V06S0303\n\n.tile R35C32:PLC2\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0103 N3_V06S0103\narc: S1_V02S0501 N3_V06S0303\narc: S3_V06S0203 N3_V06S0103\n\n.tile R35C33:PLC2\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 H02E0701\narc: W3_H06W0103 N3_V06S0103\narc: E3_H06E0103 W3_H06E0103\n\n.tile R35C34:PLC2\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 N3_V06S0203\narc: H01W0100 W3_H06E0303\n\n.tile R35C35:PLC2\narc: E1_H02E0301 N3_V06S0003\narc: N1_V02N0201 N3_V06S0103\narc: N3_V06N0103 S1_V02N0101\narc: S1_V02S0601 N3_V06S0303\narc: S1_V02S0701 E1_H02W0701\narc: W3_H06W0103 E3_H06W0103\n\n.tile R35C36:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0201 N1_V02S0201\narc: N1_V02N0201 H06E0103\narc: N3_V06N0103 S1_V02N0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0001 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\n\n.tile R35C37:PLC2\narc: E1_H02E0201 V01N0001\narc: E1_H02E0401 V01N0001\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 N3_V06S0203\narc: H00L0000 V02N0001\narc: N1_V02N0001 H02E0001\narc: N3_V06N0203 S1_V02N0701\narc: S1_V02S0401 N3_V06S0203\narc: V00B0100 H02W0701\narc: V00T0000 H02E0201\narc: W1_H02W0701 N3_V06S0203\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: M2 V00T0000\narc: M4 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: V01S0100 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R35C38:PLC2\narc: E1_H02E0301 N3_V06S0003\narc: E3_H06E0003 N3_V06S0003\narc: H00R0000 H02E0401\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 H02E0601\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 H02E0701\narc: V00B0000 V02S0001\narc: W1_H02W0701 N1_V01S0100\narc: E3_H06E0203 W3_H06E0103\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R35C39:PLC2\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 V01N0101\n\n.tile R35C3:PLC2\narc: S3_V06S0103 N3_V06S0103\narc: V00T0100 V02N0701\narc: A1 V02N0501\narc: A5 V02N0301\narc: B1 V01N0001\narc: B5 S1_V02N0501\narc: C1 V02N0401\narc: C4 V00T0100\narc: C5 E1_H01E0101\narc: D1 S1_V02N0201\narc: D4 H00R0100\narc: D5 E1_H01W0100\narc: E1_H01E0101 F1\narc: E1_H02E0601 F4\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0100 F5\narc: H01W0000 F5\narc: N3_V06N0303 F5\narc: S1_V02S0601 F4\narc: V01S0100 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICEC.K0.INIT 1111000011111111\nword: SLICEC.K1.INIT 1110111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\n\n.tile R35C40:PLC2\narc: N1_V02N0101 N3_V06S0103\narc: S1_V02S0601 N3_V06S0303\n\n.tile R35C41:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0701 N3_V06S0203\narc: E3_H06E0203 N3_V06S0203\narc: E3_H06E0303 N3_V06S0303\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 V01N0001\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 H06E0203\narc: W3_H06W0103 E3_H06W0003\n\n.tile R35C42:PLC2\narc: E1_H02E0201 V02S0201\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 H02W0101\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0003 S1_V02N0001\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0501 E1_H02W0501\narc: E1_H02E0101 W3_H06E0103\narc: S1_V02S0101 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\n\n.tile R35C43:PLC2\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0101 H02E0101\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0101 N3_V06S0103\n\n.tile R35C44:PLC2\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 N3_V06S0203\narc: N1_V02N0201 S1_V02N0701\narc: N3_V06N0203 H06E0203\narc: S1_V02S0601 N3_V06S0303\narc: W1_H02W0501 N3_V06S0303\narc: S1_V02S0401 W3_H06E0203\narc: E3_H06E0203 W3_H06E0203\n\n.tile R35C45:PLC2\narc: E1_H02E0401 N3_V06S0203\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 H02E0301\n\n.tile R35C46:PLC2\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H02W0401\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0401 H02E0401\narc: S1_V02S0701 N1_V02S0601\n\n.tile R35C47:PLC2\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0303 N3_V06S0303\narc: H00R0000 H02W0601\narc: H00R0100 H02W0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S1_V02N0101\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S1_V02N0701\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0601 E1_H01W0000\narc: S1_V02S0701 H06E0203\narc: V00T0000 S1_V02N0401\narc: W1_H02W0401 V06S0203\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: CE2 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E3_H06E0203 Q4\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V00B0000 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R35C48:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0401 E1_H01W0000\narc: H00R0100 N1_V02S0701\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 S1_V02N0701\narc: N3_V06N0003 S1_V02N0001\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H02E0601\narc: V00B0100 E1_H02W0501\narc: V01S0100 N3_V06S0303\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0601 N1_V02S0601\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0201 W3_H06E0103\narc: H01W0000 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H02E0601 Q6\narc: M6 V00B0100\narc: MUXCLK3 CLK0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R35C49:PLC2\narc: E1_H02E0401 E1_H01W0000\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 V02N0201\narc: H00R0100 H02W0701\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0201 H02E0201\narc: V00B0000 V02S0001\narc: V00T0000 H02E0001\narc: V01S0000 N3_V06S0103\narc: CE0 H00R0100\narc: CE1 V02N0201\narc: CE2 H00R0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q6\narc: H01W0000 Q4\narc: M0 V00T0000\narc: M2 H02E0601\narc: M4 V00B0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R35C4:PLC2\narc: H00L0000 V02N0001\narc: N1_V02N0701 S1_V02N0601\narc: V00B0100 H02W0501\narc: V00T0100 V02N0501\narc: A3 V01N0101\narc: A6 F7\narc: A7 V00T0100\narc: B3 V01N0001\narc: B6 F3\narc: B7 V02N0701\narc: C3 H00L0000\narc: C6 V00B0100\narc: C7 S1_V02N0201\narc: D3 V02N0201\narc: D6 E1_H01W0100\narc: D7 V02N0401\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000001\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0000000000000001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R35C50:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 N3_V06S0303\narc: H00R0000 N1_V02S0401\narc: H00R0100 H02W0501\narc: N1_V02N0701 H06E0203\narc: N3_V06N0103 S1_V02N0101\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0601 H06E0303\narc: V00B0000 V02S0001\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0701 N1_V02S0701\narc: S1_V02S0701 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CE2 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q4\narc: H01W0000 Q6\narc: M0 V00T0000\narc: M2 V00B0000\narc: M4 H02E0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R35C51:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 H01E0001\narc: E1_H02E0601 N3_V06S0303\narc: H00R0000 V02S0601\narc: H00R0100 V02N0701\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0203 S1_V02N0401\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0101 H06E0103\narc: S1_V02S0701 N3_V06S0203\narc: V00B0000 S1_V02N0201\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0401\narc: V00T0100 N1_V02S0701\narc: V01S0100 N3_V06S0303\narc: W1_H02W0501 N3_V06S0303\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q6\narc: E1_H02E0001 Q0\narc: M0 V00T0000\narc: M2 V00B0100\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R35C52:PLC2\narc: E1_H02E0401 H01E0001\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 H02W0201\narc: H00R0000 H02E0601\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 N1_V01S0000\narc: N1_V02N0701 H06E0203\narc: N3_V06N0103 S1_V02N0201\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02E0001\narc: V00T0100 V02N0701\narc: CE0 H00L0000\narc: CE1 H00R0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: H01W0100 Q4\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q6\narc: V01S0100 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R35C53:PLC2\narc: E3_H06E0003 N3_V06S0003\narc: H00R0000 W1_H02E0601\narc: H00R0100 V02S0501\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0701 H02E0701\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0601 H06E0303\narc: V00B0100 H02E0501\narc: W1_H02W0201 N1_V02S0201\narc: W3_H06W0303 E3_H06W0203\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: H01W0100 Q0\narc: M0 H02E0601\narc: M2 V00B0100\narc: M4 H02E0401\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q2\narc: V01S0100 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R35C54:PLC2\narc: N1_V02N0101 H01E0101\narc: N1_V02N0401 H02W0401\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0601 N3_V06S0303\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0201 W3_H06E0103\narc: H01W0000 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\n\n.tile R35C55:PLC2\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0501 E1_H01W0100\narc: W1_H02W0401 N3_V06S0203\n\n.tile R35C56:PLC2\narc: E1_H02E0401 W1_H02E0101\narc: N1_V02N0301 S1_V02N0201\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 H06E0003\narc: H01W0100 W3_H06E0303\narc: S1_V02S0501 W3_H06E0303\narc: E3_H06E0303 W3_H06E0303\n\n.tile R35C57:PLC2\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 N1_V01S0000\n\n.tile R35C58:PLC2\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 N3_V06S0303\n\n.tile R35C59:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 N3_V06S0103\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0401 V01N0001\narc: S1_V02S0601 H06E0303\narc: S3_V06S0303 N3_V06S0303\narc: W3_H06W0203 E3_H06W0203\n\n.tile R35C5:PLC2\narc: N1_V02N0301 N1_V01S0100\narc: S1_V02S0601 W1_H02E0601\narc: V00B0100 V02N0301\narc: V00T0100 V02N0701\narc: A5 V00T0100\narc: A7 V02N0101\narc: B5 V02N0501\narc: B7 V00B0100\narc: C5 V01N0101\narc: C7 V02N0001\narc: D5 V02N0401\narc: D7 V01N0001\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: W1_H02W0501 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000001\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R35C60:PLC2\narc: E1_H02E0201 N1_V02S0201\narc: S1_V02S0401 W3_H06E0203\narc: E3_H06E0103 W3_H06E0103\n\n.tile R35C61:PLC2\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 H02E0201\n\n.tile R35C62:PLC2\narc: S1_V02S0701 N3_V06S0203\narc: S1_V02S0501 W3_H06E0303\narc: E3_H06E0303 W3_H06E0303\n\n.tile R35C63:PLC2\narc: S1_V02S0201 H06E0103\n\n.tile R35C64:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: S1_V02S0701 H02W0701\n\n.tile R35C65:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E3_H06E0203 N3_V06S0203\narc: E3_H06E0303 N3_V06S0303\narc: S1_V02S0101 H02E0101\narc: S1_V02S0501 H06E0303\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0203 E3_H06W0203\n\n.tile R35C66:PLC2\narc: S1_V02S0101 H02E0101\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0201 W3_H06E0103\n\n.tile R35C68:PLC2\narc: S1_V02S0401 H06E0203\narc: S1_V02S0601 H06E0303\n\n.tile R35C69:PLC2\narc: E1_H02E0101 S1_V02N0101\n\n.tile R35C6:PLC2\narc: E1_H02E0501 N3_V06S0303\narc: E1_H02E0601 V06S0303\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 N3_V06S0303\n\n.tile R35C7:PLC2\narc: H00R0000 V02N0601\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H02E0601\narc: V00B0000 V02S0201\narc: V00T0100 V02S0501\narc: V01S0000 N3_V06S0103\narc: CE0 H00R0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: H01W0100 Q6\narc: M0 V00B0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q0\narc: V01S0100 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R35C8:PLC2\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0701 H01E0101\n\n.tile R35C9:PLC2\narc: N1_V02N0501 E3_H06W0303\n\n.tile R36C10:PLC2\narc: V00T0000 W1_H02E0201\narc: CLK0 G_HPBX0000\narc: E3_H06E0103 F1\narc: E3_H06E0203 Q4\narc: F1 F1_SLICE\narc: LSR1 V00T0000\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: N3_V06N0103 F1\narc: N3_V06N0203 Q4\narc: V00T0100 Q1\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR ENABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE ASYNC\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR ENABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE ASYNC\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R36C12:PLC2\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0701 N3_V06S0203\n\n.tile R36C13:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0601 H06W0303\narc: N3_V06N0103 H06E0103\narc: N3_V06N0203 H06E0203\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 V01N0001\narc: V01S0100 N3_V06S0303\n\n.tile R36C14:PLC2\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 E1_H02W0601\n\n.tile R36C15:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0301 H02W0301\n\n.tile R36C16:PLC2\narc: N1_V02N0001 H06W0003\narc: N1_V02N0401 H06W0203\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0101 H02E0101\narc: W1_H02W0301 V06S0003\narc: W1_H02W0601 E1_H02W0601\narc: N3_V06N0103 W3_H06E0103\narc: N3_V06N0203 W3_H06E0203\narc: W3_H06W0003 V06S0003\narc: W3_H06W0303 N3_V06S0303\narc: E3_H06E0103 W3_H06E0103\n\n.tile R36C17:PLC2\narc: E1_H02E0501 N3_V06S0303\narc: E3_H06E0203 V01N0001\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 N3_V06S0103\narc: S3_V06S0103 N3_V06S0003\narc: V01S0100 N3_V06S0303\n\n.tile R36C18:PLC2\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0701 N3_V06S0203\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0601 E3_H06W0303\narc: V01S0100 N3_V06S0303\narc: W1_H02W0601 E3_H06W0303\n\n.tile R36C19:PLC2\narc: E1_H02E0401 E3_H06W0203\narc: E3_H06E0303 V01N0101\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 H02E0701\narc: W3_H06W0103 N3_V06S0103\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0203\n\n.tile R36C20:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E3_H06E0003 V01N0001\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0501 N3_V06S0303\narc: W1_H02W0201 N3_V06S0103\narc: W3_H06W0003 N3_V06S0003\n\n.tile R36C21:PLC2\narc: N1_V02N0001 H02E0001\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 H02W0601\narc: S1_V02S0201 E3_H06W0103\narc: W3_H06W0203 N3_V06S0203\n\n.tile R36C22:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0301 V02N0301\narc: E1_H02E0601 N3_V06S0303\narc: E1_H02E0701 V02N0701\narc: E3_H06E0303 N3_V06S0303\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0201 H06W0103\narc: S1_V02S0401 V01N0001\narc: W1_H02W0601 N3_V06S0303\narc: E3_H06E0103 W3_H06E0103\n\n.tile R36C23:PLC2\narc: E1_H02E0601 V02N0601\narc: E3_H06E0303 N3_V06S0303\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 H02E0601\narc: E1_H02E0401 W3_H06E0203\narc: W3_H06W0303 N3_V06S0303\n\n.tile R36C24:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0103 V01N0101\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 N3_V06S0203\narc: V01S0000 N3_V06S0103\narc: W3_H06W0303 N3_V06S0303\n\n.tile R36C25:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0701 W1_H02E0601\narc: E3_H06E0303 N3_V06S0303\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 N1_V01S0100\narc: V01S0000 N3_V06S0103\narc: W1_H02W0601 V06S0303\narc: E1_H02E0601 W3_H06E0303\narc: W3_H06W0103 N3_V06S0103\narc: W3_H06W0203 N3_V06S0203\narc: W3_H06W0303 N3_V06S0303\n\n.tile R36C26:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 V01N0001\narc: H00L0000 H02W0001\narc: H00L0100 H02E0101\narc: H00R0000 H02W0601\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0701 N3_V06S0203\narc: V00B0000 V02N0001\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0201 V01N0001\narc: E1_H02E0301 W3_H06E0003\narc: A1 H00L0100\narc: A3 H00L0100\narc: A4 V02N0301\narc: A5 H02W0501\narc: A7 H00L0000\narc: B1 E1_H01W0100\narc: B3 H02W0101\narc: B4 H00R0000\narc: B5 H02W0301\narc: B7 H02W0101\narc: C1 W1_H02E0601\narc: C3 H02E0601\narc: C4 V00B0100\narc: C5 V00T0100\narc: C7 H02E0401\narc: D1 W1_H02E0201\narc: D3 V02N0201\narc: D4 H01W0000\narc: D5 V02N0601\narc: D7 V00B0000\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M6 N1_V01N0101\narc: N1_V01N0101 F1\narc: N3_V06N0203 F4\narc: N3_V06N0303 F6\narc: V00B0100 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0111000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R36C27:PLC2\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 N3_V06S0303\narc: E3_H06E0203 N3_V06S0203\narc: H00L0100 V02S0301\narc: H00R0000 H02E0401\narc: H00R0100 W1_H02E0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0401 N3_V06S0203\narc: N1_V02N0601 E1_H02W0601\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 N3_V06S0003\narc: V00B0000 V02N0201\narc: V00B0100 H02W0501\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02N0701\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 N3_V06S0303\narc: W3_H06W0203 N3_V06S0203\narc: W3_H06W0103 E3_H06W0103\narc: A1 H00L0100\narc: A7 E1_H02W0501\narc: B0 V02N0101\narc: B1 V02S0101\narc: B7 H02E0101\narc: C0 V02N0401\narc: C1 H00R0100\narc: C7 V00T0000\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V00T0100\narc: D7 V00B0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F7 F7_SLICE\narc: M2 V00B0100\narc: MUXCLK1 CLK0\narc: N1_V02N0201 Q2\narc: N3_V06N0003 F0\narc: N3_V06N0203 F7\narc: V01S0100 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0011111100000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R36C28:PLC2\narc: E1_H02E0601 V01N0001\narc: E3_H06E0303 N1_V01S0100\narc: H00L0100 W1_H02E0301\narc: H00R0000 H02E0401\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0601 N3_V06S0303\narc: W1_H02W0501 N1_V02S0501\narc: E3_H06E0203 W3_H06E0103\narc: A1 H00R0000\narc: A5 H02E0501\narc: B1 H02W0301\narc: B5 V02N0701\narc: C1 H00L0100\narc: C5 H02E0601\narc: D1 V02N0001\narc: D5 V02N0601\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: M4 E1_H01E0101\narc: N3_V06N0203 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000011101110111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R36C29:PLC2\narc: E1_H02E0201 V01N0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 N1_V01S0100\narc: V01S0100 N3_V06S0303\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 W3_H06E0303\n\n.tile R36C2:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0701 E1_H02W0701\n\n.tile R36C30:PLC2\narc: N1_V02N0401 H06E0203\narc: S1_V02S0201 N3_V06S0103\narc: E1_H02E0101 W3_H06E0103\n\n.tile R36C31:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 N3_V06S0003\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0401 E1_H02W0101\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0103 E1_H02W0101\n\n.tile R36C32:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 V02N0501\n\n.tile R36C33:PLC2\narc: E3_H06E0303 N3_V06S0303\narc: H00L0100 V02N0301\narc: H00R0000 N1_V02S0401\narc: H01W0100 E3_H06W0303\narc: N1_V02N0501 E3_H06W0303\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0601 N1_V02S0301\narc: V00B0100 H02E0501\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02S0701\narc: W3_H06W0303 E3_H06W0303\narc: A0 E1_H01E0001\narc: A3 E1_H01E0001\narc: A5 N1_V01N0101\narc: A7 N1_V01N0101\narc: B0 H02E0301\narc: B1 S1_V02N0101\narc: B3 H01W0100\narc: B4 V02S0501\narc: B5 H02E0101\narc: B6 V02S0501\narc: B7 H02E0101\narc: C0 H00L0100\narc: C1 V02S0401\narc: C3 V02N0601\narc: C4 H02E0401\narc: C5 V02N0201\narc: C6 V00T0000\narc: C7 V01N0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 H00R0000\narc: D3 V00B0100\narc: D4 H00R0100\narc: D5 H02E0001\narc: D6 H01W0000\narc: D7 W1_H02E0201\narc: E1_H01E0001 Q1\narc: E1_H02E0301 Q1\narc: E3_H06E0103 Q1\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0000 F7\narc: MUXCLK0 CLK0\narc: N1_V01N0101 Q1\narc: N1_V02N0001 F0\narc: N1_V02N0101 F3\narc: N3_V06N0103 Q1\narc: N3_V06N0303 F6\narc: S1_V02S0101 F1\narc: V01S0000 F1\narc: W1_H02W0101 Q1\narc: W3_H06W0103 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0011111100000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0001001101011111\nword: SLICEA.K1.INIT 0000000000110000\nword: SLICED.K0.INIT 0011111100000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R36C34:PLC2\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\n\n.tile R36C35:PLC2\narc: E1_H02E0401 V02N0401\narc: V00B0100 E1_H02W0701\narc: V00T0100 W1_H02E0301\narc: V01S0100 N3_V06S0303\narc: A7 V00T0100\narc: B7 V00B0100\narc: C7 V01N0101\narc: D7 V02N0601\narc: F7 F7_SLICE\narc: N3_V06N0203 F7\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R36C36:PLC2\narc: N1_V02N0601 H06E0303\narc: N3_V06N0103 H06E0103\narc: N3_V06N0303 H06W0303\narc: S1_V02S0001 N3_V06S0003\n\n.tile R36C37:PLC2\narc: E1_H02E0701 N3_V06S0203\narc: H00R0000 W1_H02E0401\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0701 N1_V01S0100\narc: W1_H02W0701 E1_H02W0701\narc: A3 E1_H02W0701\narc: B3 E1_H02W0101\narc: C3 V02N0401\narc: D3 H00R0000\narc: E1_H01E0101 F3\narc: F3 F3_SLICE\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R36C38:PLC2\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0203 N3_V06S0203\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 N3_V06S0003\narc: S1_V02S0601 N1_V02S0301\narc: S1_V02S0701 H02E0701\n\n.tile R36C39:PLC2\narc: E3_H06E0103 V01N0101\narc: H00R0000 H02E0601\narc: H00R0100 V02S0701\narc: N1_V01N0101 N3_V06S0203\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0401 V01N0001\narc: V00T0000 V02S0401\narc: V01S0000 N3_V06S0103\narc: H01W0000 W3_H06E0103\narc: N3_V06N0203 W3_H06E0203\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: A4 H02E0701\narc: B4 H00R0000\narc: B5 S1_V02N0701\narc: C4 V02N0001\narc: C5 V00T0000\narc: CLK0 G_HPBX0000\narc: D4 V02N0401\narc: D5 H00R0100\narc: E1_H01E0101 F4\narc: E3_H06E0303 Q5\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q5\narc: MUXCLK2 CLK0\narc: N3_V06N0303 Q5\narc: S1_V02S0501 F5\narc: W1_H02W0701 Q5\narc: W3_H06W0303 Q5\nword: SLICEC.K0.INIT 0001001101011111\nword: SLICEC.K1.INIT 0000000000001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R36C3:PLC2\narc: E1_H02E0501 N1_V01S0100\narc: N1_V02N0701 H02W0701\narc: V00T0000 V02S0601\narc: A0 H02W0501\narc: A2 H02E0501\narc: A3 E1_H01E0001\narc: A4 V00B0000\narc: A5 Q5\narc: A6 H00R0000\narc: A7 Q7\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q6\narc: H01W0100 Q2\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q7\narc: N1_V02N0301 Q3\narc: N1_V02N0401 Q4\narc: N1_V02N0501 Q5\narc: V00B0000 Q4\narc: V01S0000 Q6\narc: V01S0100 Q2\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R36C40:PLC2\narc: E3_H06E0303 H01E0101\narc: N1_V02N0001 N3_V06S0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\n\n.tile R36C41:PLC2\narc: E1_H02E0401 V02S0401\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0201 N3_V06S0103\narc: S1_V02S0701 H06E0203\narc: V01S0000 N3_V06S0103\n\n.tile R36C42:PLC2\narc: E1_H02E0001 N3_V06S0003\narc: N1_V02N0401 N3_V06S0203\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 H02E0401\n\n.tile R36C43:PLC2\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0301 N1_V01S0100\narc: W1_H02W0301 N3_V06S0003\n\n.tile R36C44:PLC2\narc: E1_H02E0001 V06S0003\narc: E3_H06E0103 N3_V06S0103\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 N1_V02S0201\n\n.tile R36C45:PLC2\narc: S1_V02S0001 H02E0001\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N3_V06S0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\n\n.tile R36C46:PLC2\narc: E1_H02E0501 V02N0501\narc: N1_V02N0101 N3_V06S0103\narc: S1_V02S0001 N3_V06S0003\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\n\n.tile R36C47:PLC2\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0601 N3_V06S0303\narc: S1_V02S0401 N1_V02S0401\n\n.tile R36C48:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0601 N3_V06S0303\n\n.tile R36C49:PLC2\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 N1_V01S0000\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 N1_V02S0601\narc: V00B0000 V02N0001\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02E0001\narc: V00T0100 E1_H02W0301\narc: V01S0000 N3_V06S0103\narc: A7 V00T0100\narc: B6 V00T0000\narc: B7 V00B0100\narc: C6 E1_H02W0601\narc: C7 V02N0201\narc: D6 H00R0100\narc: D7 V00B0000\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: N1_V02N0601 F6\nword: SLICED.K0.INIT 0011111100000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R36C4:PLC2\narc: E1_H02E0701 E1_H01W0100\narc: N3_V06N0203 E3_H06W0203\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0701 E3_H06W0203\narc: A0 H00L0000\narc: A1 E1_H01E0001\narc: A2 V00T0000\narc: A3 H00L0100\narc: A4 V00B0000\narc: A5 Q5\narc: A6 H00R0000\narc: A7 Q7\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00L0100 Q3\narc: H00R0000 Q6\narc: LSR1 H02E0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q3\narc: N1_V01N0101 Q1\narc: N1_V02N0001 Q0\narc: N1_V02N0201 Q2\narc: N1_V02N0401 Q6\narc: N1_V02N0501 Q5\narc: N1_V02N0701 Q7\narc: V00B0000 Q4\narc: V00T0000 Q2\narc: V01S0000 Q4\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 0101101010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R36C50:PLC2\narc: E1_H02E0701 N3_V06S0203\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0001 N3_V06S0003\narc: V01S0100 N3_V06S0303\n\n.tile R36C51:PLC2\narc: N1_V02N0401 H02W0401\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 N1_V02S0701\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0601 V02N0601\narc: W1_H02W0301 W3_H06E0003\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\n\n.tile R36C52:PLC2\narc: E1_H02E0701 V02S0701\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0701 W1_H02E0701\narc: W1_H02W0401 N3_V06S0203\narc: E1_H02E0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\n\n.tile R36C53:PLC2\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0501 N1_V02S0401\narc: V01S0000 N3_V06S0103\narc: V01S0100 N3_V06S0303\n\n.tile R36C54:PLC2\narc: H00L0000 V02N0001\narc: H00R0000 W1_H02E0601\narc: S1_V02S0101 N3_V06S0103\narc: S1_V02S0201 N3_V06S0103\narc: S1_V02S0301 N3_V06S0003\narc: S1_V02S0701 W1_H02E0701\narc: V00B0100 V02N0301\narc: W3_H06W0103 E3_H06W0103\narc: A0 V02N0701\narc: A1 H02W0701\narc: B0 F1\narc: B1 V02S0101\narc: C0 V02N0601\narc: C1 H00L0000\narc: D0 H00R0000\narc: D1 V00B0100\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: N3_V06N0003 F0\nword: SLICEA.K0.INIT 0100110000000000\nword: SLICEA.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R36C55:PLC2\narc: N1_V02N0501 N3_V06S0303\narc: N3_V06N0103 H06W0103\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0301 V01N0101\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0003 E3_H06W0303\n\n.tile R36C56:PLC2\narc: E1_H02E0501 N3_V06S0303\narc: E3_H06E0003 N3_V06S0003\narc: S1_V02S0101 N1_V02S0101\narc: W3_H06W0003 E3_H06W0303\n\n.tile R36C57:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0701 N3_V06S0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 N1_V02S0601\narc: V01S0100 N3_V06S0303\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: E1_H02E0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\n\n.tile R36C58:PLC2\narc: E1_H02E0201 V06S0103\narc: H00L0000 V02N0001\narc: H00R0000 V02N0401\narc: N1_V01N0101 N3_V06S0203\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 H02E0201\narc: S1_V02S0501 N3_V06S0303\narc: S1_V02S0701 H02E0701\narc: V00T0100 V02N0501\narc: W1_H02W0601 V02S0601\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: A1 H02E0501\narc: A3 V02S0501\narc: B1 S1_V02N0301\narc: B3 H00R0000\narc: C1 V02N0601\narc: C3 H00L0000\narc: D1 F2\narc: D3 V00T0100\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: M2 E1_H02W0601\narc: W3_H06W0103 F1\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000011001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000011101110111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R36C59:PLC2\narc: E1_H02E0301 N3_V06S0003\narc: E1_H02E0601 W1_H02E0301\narc: H00L0100 W1_H02E0301\narc: H00R0000 W1_H02E0601\narc: H00R0100 V02N0501\narc: H01W0000 E3_H06W0103\narc: N1_V01N0001 N3_V06S0003\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0301 H06E0003\narc: V00B0000 W1_H02E0601\narc: V00B0100 V02N0101\narc: V00T0000 H02E0201\narc: W1_H02W0001 N3_V06S0003\narc: A3 H00L0100\narc: A4 F5\narc: A5 V00B0000\narc: A6 F7\narc: A7 H00R0000\narc: B3 V02N0301\narc: B4 H02W0101\narc: B5 H02W0301\narc: B6 E1_H02W0101\narc: B7 V00B0100\narc: C3 V02N0601\narc: C4 V02N0001\narc: C5 V00T0000\narc: C6 W1_H02E0401\narc: C7 V00T0000\narc: D3 H02E0201\narc: D4 H00R0100\narc: D5 H01W0000\narc: D6 N1_V02S0601\narc: D7 V02N0401\narc: E1_H01E0001 F3\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N3_V06N0203 F4\narc: N3_V06N0303 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000100010001000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0000100010001000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R36C5:PLC2\narc: N1_V02N0601 N3_V06S0303\narc: V00T0000 V02S0601\narc: A0 H00L0000\narc: A1 H02E0701\narc: A2 E1_H01E0001\narc: A3 H00L0100\narc: A4 V00B0000\narc: A5 Q5\narc: A6 H00R0000\narc: A7 Q7\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00L0100 Q3\narc: H00R0000 Q6\narc: H01W0100 Q1\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q4\narc: N1_V02N0001 Q0\narc: N1_V02N0101 Q1\narc: N1_V02N0301 Q3\narc: N1_V02N0401 Q6\narc: N1_V02N0501 Q7\narc: N1_V02N0701 Q5\narc: V00B0000 Q4\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 0101101010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R36C60:PLC2\narc: H00L0100 E1_H02W0301\narc: H00R0000 V02N0401\narc: H00R0100 H02W0701\narc: S1_V02S0201 H02W0201\narc: V00B0000 H02E0601\narc: V00B0100 H02W0701\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0301 V01N0101\narc: W1_H02W0601 H01E0001\narc: A1 V02N0501\narc: A3 V00B0000\narc: A5 V00B0000\narc: A7 E1_H02W0701\narc: B1 H00R0100\narc: B3 V01N0001\narc: B5 H00R0000\narc: B7 V00B0100\narc: C1 V02N0601\narc: C3 H00L0100\narc: C5 E1_H02W0601\narc: C7 V02N0201\narc: D1 H02W0001\narc: D3 H02W0001\narc: D5 H02W0001\narc: D7 E1_H02W0001\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: M4 E1_H02W0401\narc: M6 V00T0100\narc: N3_V06N0203 F4\narc: N3_V06N0303 F6\narc: V00T0100 F3\narc: W3_H06W0103 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R36C61:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V06S0103\narc: E1_H02E0401 N3_V06S0203\narc: E1_H02E0601 V01N0001\narc: E1_H02E0701 N3_V06S0203\narc: H00L0000 E1_H02W0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 H06E0203\narc: V00B0100 E1_H02W0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 V06S0103\narc: W1_H02W0701 N3_V06S0203\narc: A7 H00L0000\narc: B7 V02N0701\narc: C7 V02N0001\narc: D7 V02N0601\narc: F6 F5D_SLICE\narc: M6 V00B0100\narc: W3_H06W0303 F6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R36C62:PLC2\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 H02W0001\narc: H00R0000 H02E0401\narc: S1_V02S0101 H02E0101\narc: S1_V02S0601 H02W0601\narc: V00B0000 H02E0401\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02W0001\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V02N0001\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E1_H01W0100\narc: A1 H00L0000\narc: A3 V00T0000\narc: A5 V00T0000\narc: A7 H02W0501\narc: B1 V01N0001\narc: B3 V02N0101\narc: B5 V02N0701\narc: B7 E1_H02W0101\narc: C1 V02N0401\narc: C3 H02E0601\narc: C5 V00B0100\narc: C7 E1_H02W0401\narc: D1 H00R0000\narc: D3 H02E0001\narc: D5 V00B0000\narc: D7 V00B0000\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F5\narc: M6 V00T0100\narc: V00T0100 F3\narc: W1_H02W0101 F1\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000011101110111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000011101110111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000011101110111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R36C63:PLC2\narc: H00L0000 V02N0201\narc: H00R0100 W1_H02E0701\narc: V00B0100 W1_H02E0701\narc: V00T0000 E1_H02W0201\narc: W1_H02W0601 V06S0303\narc: H01W0100 W3_H06E0303\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0501 W3_H06E0303\narc: A1 H02E0701\narc: A5 H02E0701\narc: B1 V00T0000\narc: B5 E1_H02W0301\narc: C1 H00L0000\narc: C5 V02N0001\narc: D1 V00B0100\narc: D5 H00R0100\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F1\narc: W1_H02W0701 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R36C64:PLC2\narc: W1_H02W0101 V02N0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V02N0501\narc: E3_H06E0103 W3_H06E0003\n\n.tile R36C65:PLC2\narc: E1_H02E0101 N3_V06S0103\narc: E3_H06E0103 N3_V06S0103\narc: V01S0100 N3_V06S0303\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V01N0101\narc: W3_H06W0103 E1_H02W0201\n\n.tile R36C66:PLC2\narc: S1_V02S0101 H02E0101\n\n.tile R36C67:PLC2\narc: W1_H02W0201 V02N0201\n\n.tile R36C68:PLC2\narc: S1_V02S0201 H06E0103\n\n.tile R36C69:PLC2\narc: S3_V06S0003 N3_V06S0003\n\n.tile R36C6:PLC2\narc: N1_V02N0301 N3_V06S0003\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R36C70:PLC2\narc: E1_H02E0101 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: S3_V06S0103 W3_H06E0103\n\n.tile R36C7:PLC2\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 N1_V01S0000\narc: N3_V06N0203 H06W0203\n\n.tile R36C8:PLC2\narc: E1_H02E0201 S1_V02N0201\n\n.tile R38C14:PLC2\narc: N1_V02N0201 N1_V01S0000\n\n.tile R38C15:PLC2\narc: N1_V02N0501 H02W0501\n\n.tile R38C16:PLC2\narc: W1_H02W0501 N3_V06S0303\n\n.tile R38C18:PLC2\narc: E1_H02E0201 N3_V06S0103\narc: N1_V02N0201 N3_V06S0103\n\n.tile R38C20:PLC2\narc: N1_V02N0201 W1_H02E0201\n\n.tile R38C21:PLC2\narc: E1_H02E0201 N3_V06S0103\n\n.tile R38C22:PLC2\narc: N1_V02N0201 H02E0201\n\n.tile R38C23:PLC2\narc: N1_V02N0101 N3_V06S0103\n\n.tile R38C26:PLC2\narc: E3_H06E0003 N3_V06S0003\narc: N1_V01N0001 N3_V06S0003\n\n.tile R38C28:PLC2\narc: N1_V01N0001 N3_V06S0003\narc: N1_V01N0101 N3_V06S0203\n\n.tile R38C29:PLC2\narc: N1_V02N0001 H06E0003\n\n.tile R38C2:PLC2\narc: S3_V06S0303 N3_V06S0203\n\n.tile R38C30:PLC2\narc: N1_V02N0101 N3_V06S0103\n\n.tile R38C32:PLC2\narc: E1_H02E0701 V06S0203\n\n.tile R38C33:PLC2\narc: N1_V01N0001 N3_V06S0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0701 H02E0701\n\n.tile R38C35:PLC2\narc: N1_V02N0501 N1_V01S0100\n\n.tile R38C39:PLC2\narc: N1_V02N0701 N3_V06S0203\n\n.tile R38C41:PLC2\narc: N1_V02N0701 N3_V06S0203\n\n.tile R38C42:PLC2\narc: N1_V02N0101 V01N0101\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 H02W0701\n\n.tile R38C43:PLC2\narc: W1_H02W0701 E1_H02W0601\n\n.tile R38C44:PLC2\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 N3_V06S0203\n\n.tile R38C45:PLC2\narc: E3_H06E0003 N3_V06S0003\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 N1_V01S0100\narc: V01S0100 N3_V06S0303\narc: W1_H02W0601 N3_V06S0303\n\n.tile R38C46:PLC2\narc: N1_V02N0001 H06W0003\n\n.tile R38C47:PLC2\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 N3_V06S0303\narc: N1_V02N0701 E1_H02W0701\n\n.tile R38C48:PLC2\narc: E1_H02E0501 N3_V06S0303\narc: N1_V02N0001 H06E0003\n\n.tile R38C49:PLC2\narc: N1_V02N0501 H02E0501\narc: W1_H02W0701 N3_V06S0203\narc: W3_H06W0003 N3_V06S0003\n\n.tile R38C50:PLC2\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0401 N1_V01S0000\n\n.tile R38C51:PLC2\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0701 N3_V06S0203\n\n.tile R38C53:PLC2\narc: E1_H02E0501 N3_V06S0303\narc: E3_H06E0203 N1_V01S0000\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0401 N1_V01S0000\n\n.tile R38C54:PLC2\narc: E3_H06E0203 N1_V01S0000\narc: N1_V02N0501 H02E0501\narc: V01S0100 N3_V06S0303\n\n.tile R38C55:PLC2\narc: N1_V02N0201 N3_V06S0103\n\n.tile R38C56:PLC2\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H06E0203\n\n.tile R38C57:PLC2\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0701 H06E0203\narc: W1_H02W0301 N3_V06S0003\n\n.tile R38C58:PLC2\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0501 H02W0501\narc: W1_H02W0101 V02S0101\n\n.tile R38C59:PLC2\narc: W1_H02W0501 V06S0303\n\n.tile R38C60:PLC2\narc: N1_V02N0101 N3_V06S0103\n\n.tile R38C62:PLC2\narc: N1_V02N0201 H02W0201\n\n.tile R38C63:PLC2\narc: E1_H02E0201 N3_V06S0103\narc: N1_V02N0601 N1_V01S0000\narc: W1_H02W0201 N3_V06S0103\n\n.tile R38C65:PLC2\narc: N1_V02N0201 W1_H02E0201\n\n.tile R38C66:PLC2\narc: N1_V02N0701 N3_V06S0203\n\n.tile R38C69:PLC2\narc: S3_V06S0103 N3_V06S0003\n\n.tile R38C70:PLC2\narc: S1_V02S0301 N1_V02S0201\n\n.tile R38C8:PLC2\narc: N1_V02N0201 S3_V06N0103\n\n.tile R39C13:PLC2\narc: N1_V02N0401 N3_V06S0203\n\n.tile R39C14:PLC2\narc: E1_H02E0301 N3_V06S0003\narc: N1_V02N0301 N3_V06S0003\n\n.tile R39C16:PLC2\narc: E1_H02E0301 N3_V06S0003\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 N3_V06S0303\n\n.tile R39C17:PLC2\narc: E1_H02E0201 V06S0103\n\n.tile R39C18:PLC2\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0601 N3_V06S0303\n\n.tile R39C19:PLC2\narc: N1_V02N0201 W1_H02E0201\n\n.tile R39C22:PLC2\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0601 N3_V06S0303\n\n.tile R39C25:PLC2\narc: E1_H02E0601 N3_V06S0303\n\n.tile R39C26:PLC2\narc: E3_H06E0303 N3_V06S0303\n\n.tile R39C27:PLC2\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 W1_H02E0601\n\n.tile R39C28:PLC2\narc: N1_V02N0401 N3_V06S0203\narc: W1_H02W0501 N3_V06S0303\n\n.tile R39C29:PLC2\narc: N1_V02N0601 H06E0303\n\n.tile R39C2:PLC2\narc: S1_V02S0701 N3_V06S0203\n\n.tile R39C32:PLC2\narc: N1_V02N0601 N3_V06S0303\n\n.tile R39C35:PLC2\narc: N1_V02N0401 N3_V06S0203\n\n.tile R39C39:PLC2\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0601 N3_V06S0303\n\n.tile R39C41:PLC2\narc: N1_V02N0601 N3_V06S0303\n\n.tile R39C42:PLC2\narc: N1_V01N0101 N3_V06S0203\narc: N1_V02N0301 H02W0301\narc: N1_V02N0601 N3_V06S0303\n\n.tile R39C43:PLC2\narc: W1_H02W0301 N3_V06S0003\n\n.tile R39C44:PLC2\narc: E3_H06E0303 N3_V06S0303\narc: N1_V02N0701 N3_V06S0203\n\n.tile R39C45:PLC2\narc: N1_V02N0701 N1_V01S0100\n\n.tile R39C49:PLC2\narc: N1_V02N0101 N3_V06S0103\n\n.tile R39C50:PLC2\narc: N1_V02N0601 W3_H06E0303\n\n.tile R39C51:PLC2\narc: N1_V02N0001 N3_V06S0003\n\n.tile R39C53:PLC2\narc: N1_V02N0001 N3_V06S0003\n\n.tile R39C54:PLC2\narc: N1_V02N0301 N1_V01S0100\n\n.tile R39C58:PLC2\narc: N1_V02N0101 V01N0101\n\n.tile R39C59:PLC2\narc: N1_V02N0401 N3_V06S0203\n\n.tile R39C61:PLC2\narc: E1_H02E0701 N3_V06S0203\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0701 N3_V06S0203\n\n.tile R39C62:PLC2\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 H02E0701\n\n.tile R39C63:PLC2\narc: E3_H06E0303 N3_V06S0303\n\n.tile R39C64:PLC2\narc: E3_H06E0303 N3_V06S0303\narc: N1_V02N0601 N3_V06S0303\n\n.tile R39C65:PLC2\narc: N1_V02N0601 N3_V06S0303\n\n.tile R39C66:PLC2\narc: N1_V02N0501 H06E0303\n\n.tile R39C67:PLC2\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0601 H06E0303\n\n.tile R3C10:PLC2\narc: E1_H02E0201 V02N0201\narc: E3_H06E0303 V06N0303\narc: V00B0000 V02N0201\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 S3_V06N0303\narc: W3_H06W0103 S3_V06N0103\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: F5 F5_SLICE\narc: LSR1 V00B0100\narc: M0 H02W0601\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: V00B0100 F5\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R3C11:PLC2\narc: S1_V02S0501 N1_V01S0100\narc: V00B0000 S1_V02N0001\narc: W1_H02W0601 V01N0001\narc: CLK0 G_HPBX0000\narc: D3 H02E0201\narc: D5 H02E0201\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: LSR0 V00T0100\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: S1_V02S0701 F5\narc: V00T0100 F3\narc: V01S0000 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R3C12:PLC2\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 N1_V01S0100\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0201\narc: D5 W1_H02E0201\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: LSR1 V00B0100\narc: M6 H02W0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q6\narc: V00B0100 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R3C13:PLC2\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0501 H01E0101\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 V02S0001\narc: V00T0000 V02N0601\narc: W1_H02W0401 V02N0401\narc: CLK0 G_HPBX0000\narc: D3 V02S0001\narc: D7 V00B0000\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: LSR1 V00B0100\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: S1_V02S0301 F3\narc: V00B0100 F7\narc: V01S0000 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R3C14:PLC2\narc: E1_H02E0401 V01N0001\narc: H00R0000 E1_H02W0401\narc: H00R0100 E1_H02W0701\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0701 S3_V06N0203\narc: V00B0000 V02N0201\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D7 H00R0100\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: LSR1 V00B0100\narc: M2 V00B0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00B0100 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\n\n.tile R3C15:PLC2\narc: S1_V02S0301 H01E0101\narc: S1_V02S0501 S3_V06N0303\narc: S3_V06S0103 H06E0103\narc: V00B0100 H02W0701\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: F1 F1_SLICE\narc: H01W0100 Q6\narc: LSR0 V00T0100\narc: M6 H02E0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00T0100 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R3C16:PLC2\narc: E1_H02E0301 V06N0003\narc: E1_H02E0501 V06N0303\narc: E1_H02E0701 V06N0203\narc: H00R0000 V02N0401\narc: V00B0100 V02N0301\narc: W1_H02W0401 V06N0203\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0701 V06N0203\narc: E3_H06E0003 W3_H06E0303\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: F1 F1_SLICE\narc: LSR0 V00T0100\narc: M6 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00T0100 F1\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R3C17:PLC2\narc: H00R0100 V02S0701\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0501 H02E0501\narc: S1_V02S0701 H02E0701\narc: A6 N1_V01N0101\narc: B1 V02S0101\narc: B2 E1_H01W0100\narc: B5 E1_H02W0101\narc: B6 V01S0000\narc: B7 N1_V01S0000\narc: C1 E1_H01W0000\narc: C2 H00R0100\narc: C3 E1_H02W0401\narc: C5 N1_V02S0201\narc: C6 V00T0000\narc: C7 E1_H02W0601\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D2 S1_V02N0001\narc: D3 S1_V02N0201\narc: D5 S1_V02N0601\narc: D6 H02W0001\narc: D7 S1_V02N0401\narc: E1_H01E0001 Q1\narc: E1_H01E0101 F6\narc: E1_H02E0101 F3\narc: E1_H02E0201 Q2\narc: E1_H02E0501 Q5\narc: E1_H02E0701 Q7\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q7\narc: N1_V01N0101 Q7\narc: N1_V02N0101 Q1\narc: N1_V02N0701 Q5\narc: S3_V06S0303 Q5\narc: V00T0000 Q2\narc: V01S0000 Q1\narc: V01S0100 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 0000000000000001\nword: SLICED.K1.INIT 1100110011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R3C18:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0101 H01E0101\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 H01E0101\narc: V00T0000 H02E0201\narc: W1_H02W0001 E1_H01W0000\narc: S3_V06S0203 W3_H06E0203\narc: A0 H02W0701\narc: A2 H02E0701\narc: A3 H01E0001\narc: A4 E1_H01W0000\narc: A5 V00T0000\narc: A6 H02E0501\narc: E1_H01E0001 F2\narc: E1_H01E0101 F6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: H01W0000 F3\narc: H01W0100 F5\narc: V01S0100 F4\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R3C19:PLC2\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 V01N0001\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 N1_V01S0000\narc: V00B0000 N1_V02S0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02N0401\narc: W1_H02W0101 H01E0101\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 V02N0701\narc: B3 V02N0301\narc: B5 S1_V02N0701\narc: C3 V02S0401\narc: C4 H02E0401\narc: C5 H02E0401\narc: CE1 W1_H02E0101\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: D4 V00B0000\narc: D5 V02S0601\narc: E3_H06E0303 Q5\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0000 F4\narc: H01W0000 Q3\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: W1_H02W0301 Q3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICEC.K0.INIT 1111111111110000\nword: SLICEC.K1.INIT 0000111100001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C20:PLC2\narc: H00L0100 V02N0301\narc: S1_V02S0601 S3_V06N0303\narc: V00B0000 V02S0001\narc: V00B0100 V02N0101\narc: V00T0000 V02S0401\narc: B1 E1_H02W0301\narc: C1 V02S0601\narc: CE0 S1_V02N0201\narc: CE1 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: E1_H02E0301 Q1\narc: F1 F1_SLICE\narc: H01W0000 Q6\narc: H01W0100 Q1\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: M2 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: S1_V02S0201 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100110011110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R3C21:PLC2\narc: H00L0100 V02S0101\narc: H00R0100 S1_V02N0701\narc: N1_V02N0301 H02E0301\narc: V00B0100 H02W0701\narc: V00T0100 V02S0501\narc: B1 E1_H01W0100\narc: B3 H02W0101\narc: B5 V00B0100\narc: B7 E1_H02W0301\narc: C1 N1_V01S0100\narc: C3 H00L0100\narc: C5 V00T0100\narc: C7 V02S0001\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D3 V02N0001\narc: D5 V02N0401\narc: D7 V02N0401\narc: E1_H01E0001 Q1\narc: E1_H01E0101 Q5\narc: E1_H02E0101 Q1\narc: E1_H02E0301 Q3\narc: E1_H02E0501 Q7\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q3\narc: N1_V02N0101 Q1\narc: N1_V02N0501 Q5\narc: N1_V02N0701 Q7\narc: S1_V02S0701 Q7\narc: V01S0000 Q5\narc: V01S0100 Q3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100110011110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R3C22:PLC2\narc: E1_H02E0501 V02N0501\narc: H00R0100 H02E0501\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 H01E0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 V02N0501\narc: E1_H01E0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: A0 E1_H01E0001\narc: B2 H00R0100\narc: B3 H02E0301\narc: B4 H02E0101\narc: B5 H01E0101\narc: B6 W1_H02E0301\narc: E1_H01E0101 F2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: H01W0100 F4\narc: V01S0100 F6\narc: W1_H02W0101 F3\narc: W1_H02W0701 F5\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C23:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0701 V02S0701\narc: E3_H06E0303 S3_V06N0303\narc: H00R0100 V02S0701\narc: N1_V02N0501 N1_V01S0100\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 E1_H01W0100\narc: V00B0100 E1_H02W0701\narc: W1_H02W0301 H01E0101\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H02E0201 Q2\narc: E3_H06E0103 Q2\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M2 H02W0601\narc: M4 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: S1_V02S0201 Q2\narc: V01S0100 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C24:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0701 V01N0101\narc: E3_H06E0303 W1_H02E0501\narc: H00R0000 V02N0601\narc: H00R0100 H02E0701\narc: S1_V02S0401 V01N0001\narc: V00B0000 H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 H02E0001\narc: W1_H02W0601 E1_H02W0601\narc: A2 H02W0501\narc: A3 V02N0501\narc: A7 V02N0101\narc: B2 V02S0101\narc: B3 H00R0000\narc: B7 H02W0101\narc: C2 H00L0100\narc: C3 V02S0401\narc: C7 V00B0100\narc: CE0 H00R0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 V01S0100\narc: D3 V02S0001\narc: D7 V02S0401\narc: E1_H01E0001 Q4\narc: E1_H01E0101 F2\narc: E3_H06E0203 Q4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 F3\narc: H01W0100 Q0\narc: LSR0 W1_H02E0501\narc: LSR1 W1_H02E0501\narc: M0 V00T0000\narc: M4 V00B0000\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q0\narc: S1_V02S0601 Q4\narc: V01S0100 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1001000000000000\nword: SLICEB.K1.INIT 1100010000110001\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000001011000011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R3C25:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: H00R0000 H02E0401\narc: N1_V02N0401 H02E0401\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 E1_H01W0000\narc: V00B0000 V02S0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0501 V01N0101\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: E3_H06E0003 W3_H06E0303\narc: A0 V02N0701\narc: A2 H02E0501\narc: A3 V02S0501\narc: A4 V02N0101\narc: A5 V00B0000\narc: A6 H00R0000\narc: A7 V02N0301\narc: E1_H02E0201 F2\narc: E1_H02E0601 F6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: S1_V02S0401 F4\narc: S1_V02S0701 F7\narc: S3_V06S0303 F5\narc: V01S0100 F3\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R3C26:PLC2\narc: E1_H02E0301 E1_H01W0100\narc: H00L0000 H02E0001\narc: H00R0000 V02S0601\narc: N1_V02N0101 H06E0103\narc: N1_V02N0301 E1_H02W0301\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 N1_V01S0000\narc: V00B0000 H02E0401\narc: V00T0000 W1_H02E0001\narc: V00T0100 H02E0301\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 S1_V02N0601\narc: A0 H00R0000\narc: A1 W1_H02E0701\narc: A2 V00T0000\narc: A3 V02S0501\narc: A4 V00B0000\narc: A5 V00T0100\narc: A6 V02N0101\narc: A7 H00L0000\narc: E1_H01E0001 F6\narc: E1_H02E0401 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: S1_V02S0001 F0\narc: S1_V02S0501 F5\narc: S1_V02S0701 F7\narc: V01S0000 F3\narc: V01S0100 F2\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 0101101010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C27:PLC2\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0701 V02S0701\narc: H00R0100 S1_V02N0501\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0701 H06E0203\narc: S1_V02S0001 H01E0001\narc: S1_V02S0601 W1_H02E0601\narc: V00B0000 H02E0401\narc: V00T0000 W1_H02E0201\narc: W1_H02W0401 V01N0001\narc: A0 W1_H02E0501\narc: A5 N1_V01N0101\narc: A7 N1_V01N0101\narc: B5 H00R0000\narc: B7 H02E0301\narc: C4 V02N0201\narc: C5 V00T0000\narc: C6 V02N0001\narc: C7 V02S0201\narc: CLK0 G_HPBX0000\narc: D4 H00R0100\narc: D5 V00B0000\narc: D6 H00R0100\narc: D7 V02S0601\narc: E1_H01E0101 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q6\narc: H01W0100 Q6\narc: LSR0 H02W0301\narc: LSR1 H02W0501\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q4\narc: S1_V02S0201 F0\narc: S1_V02S0401 Q4\narc: S1_V02S0501 F7\narc: S1_V02S0701 F5\narc: V01S0000 F1\nword: SLICEC.K0.INIT 0000000011110000\nword: SLICEC.K1.INIT 1000010000100001\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 1000010000100001\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 1111000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C28:PLC2\narc: E1_H02E0001 V06N0003\narc: H00L0100 V02S0301\narc: S1_V02S0501 H01E0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0301 V06N0003\narc: W1_H02W0501 V06N0303\narc: E3_H06E0003 W3_H06E0003\narc: A0 V02N0501\narc: A2 H00L0100\narc: A3 H02E0701\narc: A4 V02S0101\narc: A5 H02E0501\narc: A6 N1_V01S0100\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: H01W0100 F3\narc: N1_V01N0001 F5\narc: N1_V02N0001 F2\narc: N1_V02N0601 F6\narc: V01S0100 F4\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C29:PLC2\narc: V00T0000 V02S0601\narc: E3_H06E0303 W3_H06E0303\narc: B7 N1_V01S0000\narc: C6 V00B0100\narc: C7 V00T0000\narc: D6 H02E0001\narc: D7 V02S0401\narc: E1_H01E0101 F6\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V02N0401 F6\narc: S3_V06S0203 F7\narc: V00B0100 F7\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 1111110011111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000001010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C2:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0201 V01N0001\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02N0701\narc: A7 H00R0000\narc: B7 S1_V02N0501\narc: C7 V00T0100\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: E1_H02E0701 F7\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: LSR0 V00B0100\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R3C30:PLC2\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 W1_H02E0001\narc: N1_V02N0101 H01E0101\narc: E3_H06E0303 W3_H06E0303\n\n.tile R3C31:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0201 V01N0001\narc: H00R0100 H02E0701\narc: S1_V02S0201 H02W0201\narc: V00B0000 S1_V02N0001\narc: E3_H06E0103 W3_H06E0003\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: E3_H06E0003 Q0\narc: M0 V00B0000\narc: MUXCLK0 CLK0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C32:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 S1_V02N0401\narc: H00L0100 V02S0101\narc: H00R0100 V02N0501\narc: S1_V02S0401 E1_H02W0401\narc: V00B0100 S1_V02N0301\narc: W1_H02W0201 E1_H02W0201\narc: A0 H00L0100\narc: B0 H02W0101\narc: C0 V02N0601\narc: D0 V00B0100\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 E1_H02W0601\narc: M1 H02E0001\narc: M2 E1_H02W0601\narc: M3 H00R0100\narc: M4 E1_H02W0401\narc: M5 H02E0001\narc: M6 E1_H02W0401\nword: SLICEA.K0.INIT 1000110010101111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R3C33:PLC2\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0601 N1_V01S0000\narc: H00L0100 E1_H02W0101\narc: H00R0000 V02N0401\narc: N1_V02N0001 S1_V02N0501\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0601 H02W0601\narc: V00B0000 H02W0601\narc: V00T0100 H02E0101\narc: W1_H02W0101 E1_H02W0101\narc: A0 H00L0100\narc: B0 V00B0000\narc: C0 S1_V02N0401\narc: D0 W1_H02E0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00R0000\narc: M2 V00T0100\narc: M3 W1_H02E0201\narc: M4 V00T0100\narc: M5 H00R0000\narc: M6 V00T0100\narc: S3_V06S0003 F3\nword: SLICEA.K0.INIT 1000110010101111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R3C34:PLC2\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 S1_V02N0301\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0201 H02E0201\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 S3_V06N0303\narc: S1_V02S0001 H06E0003\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0601 E1_H01W0000\narc: V00B0000 H02W0601\narc: V00T0100 V02N0701\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0601 N1_V01S0000\narc: E3_H06E0003 W3_H06E0003\narc: A1 E1_H01E0001\narc: A2 E1_H01E0001\narc: B1 V00B0000\narc: B2 E1_H02W0301\narc: C1 V02S0601\narc: C2 V02S0601\narc: CE2 S1_V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: D2 V02N0201\narc: E1_H01E0001 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 Q6\narc: M0 H02E0601\narc: M1 V01S0100\narc: M2 H02E0601\narc: M4 V00T0100\narc: M6 W1_H02E0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F1\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000101011001111\nword: SLICEB.K0.INIT 1000101011001111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R3C35:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 V01N0001\narc: E1_H02E0601 V06N0303\narc: H00R0000 V02N0601\narc: H01W0000 E3_H06W0103\narc: N1_V02N0401 S3_V06N0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 E1_H02W0401\narc: V00B0100 N1_V02S0301\narc: V00T0100 H02E0301\narc: W1_H02W0101 E3_H06W0103\narc: E3_H06E0303 W3_H06E0303\narc: A1 E1_H01E0001\narc: A2 E1_H01E0001\narc: B1 W1_H02E0301\narc: B2 W1_H02E0301\narc: C1 H02W0601\narc: C2 H02W0601\narc: CE2 S1_V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D2 V02N0001\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 F1\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q4\narc: W1_H02W0601 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111010100110001\nword: SLICEB.K0.INIT 1111010100110001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R3C36:PLC2\narc: E1_H02E0301 V06N0003\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 E1_H02W0201\narc: H00L0100 H02E0101\narc: H00R0000 V02N0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0501 E1_H01W0100\narc: V00B0100 V02S0301\narc: V00T0000 W1_H02E0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0601 E1_H02W0601\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: A0 H00L0100\narc: B0 V00T0000\narc: C0 H00L0000\narc: D0 H02W0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: M3 H00R0100\narc: M4 V00B0100\narc: M5 H00R0000\narc: M6 V00B0100\narc: S1_V02S0101 F3\narc: V01S0100 F3\nword: SLICEA.K0.INIT 1000110010101111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R3C37:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 V02S0301\narc: E1_H02E0601 V02N0601\narc: H00L0100 H02E0301\narc: H00R0000 S1_V02N0601\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0101 W1_H02E0101\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0401 E1_H02W0101\narc: N1_V02N0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: A1 V02S0701\narc: A2 V02S0701\narc: A3 V02S0701\narc: B1 V02S0101\narc: B2 V02S0101\narc: B3 V02S0101\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: D1 N1_V01S0000\narc: D2 N1_V01S0000\narc: D3 N1_V01S0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F3\narc: M0 V00T0100\narc: M1 H00R0000\narc: M2 V00T0100\narc: M3 W1_H02E0201\narc: M4 V00T0100\narc: M5 H00R0000\narc: M6 V00T0100\narc: S3_V06S0003 F3\nword: SLICEB.K0.INIT 0001000000000000\nword: SLICEB.K1.INIT 0001000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0001000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R3C38:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 W1_H02E0601\narc: H00L0100 V02N0101\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 E1_H01W0100\narc: S1_V02S0401 E1_H02W0401\narc: V00B0100 S1_V02N0301\narc: V00T0100 H02E0301\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0601 S3_V06N0303\narc: A1 E1_H01E0001\narc: A2 V00B0000\narc: B1 H01W0100\narc: B2 H00R0000\narc: C1 H02E0601\narc: C2 H02E0601\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D2 H02W0201\narc: E1_H01E0001 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H00R0000 Q6\narc: H01W0100 Q6\narc: M0 H02W0601\narc: M1 H00L0100\narc: M2 H02W0601\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V00B0000 Q4\narc: V01S0000 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010001011110011\nword: SLICEB.K0.INIT 1010001011110011\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R3C39:PLC2\narc: E1_H02E0601 N1_V01S0000\narc: H00R0000 V02S0401\narc: H00R0100 H02W0701\narc: N1_V02N0201 S1_V02N0201\narc: S1_V02S0401 H02W0401\narc: V00B0000 S1_V02N0201\narc: V00T0000 E1_H02W0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0601 V02S0601\narc: A1 H01E0001\narc: A2 H01E0001\narc: B1 W1_H02E0101\narc: B2 W1_H02E0101\narc: C1 V02N0401\narc: C2 V02N0401\narc: CE2 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V02S0201\narc: D2 V02S0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q4\narc: H01W0100 F1\narc: M0 V00B0000\narc: M1 V01S0100\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 E1_H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111001101010001\nword: SLICEB.K0.INIT 1111001101010001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R3C3:PLC2\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0401 W1_H02E0101\narc: H00L0000 H02E0001\narc: H00L0100 E1_H02W0301\narc: H00R0000 E1_H02W0601\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0501 N1_V01S0100\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 H02W0601\narc: V00B0000 V02S0201\narc: V00B0100 W1_H02E0701\narc: V00T0000 H02W0201\narc: V00T0100 V02N0701\narc: A5 E1_H01W0000\narc: A6 H02E0701\narc: A7 N1_V01N0101\narc: B1 H01W0100\narc: B5 H02W0301\narc: B6 V02S0501\narc: B7 V00B0000\narc: C1 H00L0000\narc: C5 V02N0201\narc: C6 E1_H01E0101\narc: C7 V02N0001\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 H00R0000\narc: D5 V02N0601\narc: D6 H00R0100\narc: D7 V02S0601\narc: E1_H01E0101 F7\narc: E3_H06E0003 Q0\narc: F0 F5A_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: H01W0100 Q2\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00T0100\narc: M2 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q2\narc: V01S0000 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111000011001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R3C40:PLC2\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 V02S0201\narc: H00R0000 W1_H02E0601\narc: H00R0100 V02S0701\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 H02W0201\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0001 E1_H01W0000\narc: S3_V06S0203 E1_H01W0000\narc: V00B0100 W1_H02E0701\narc: V00T0000 V02N0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0701 V02S0701\narc: E3_H06E0103 W3_H06E0003\narc: A1 V02S0501\narc: A2 V00B0000\narc: B1 V02S0301\narc: B2 V02S0301\narc: C1 V02S0401\narc: C2 V02S0401\narc: CE2 H00R0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 V00T0000\narc: M1 W1_H02E0001\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: V00B0000 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010001011110011\nword: SLICEB.K0.INIT 1010001011110011\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R3C41:PLC2\narc: H00R0000 V02S0401\narc: N1_V02N0601 S1_V02N0301\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0401 V02N0401\narc: E3_H06E0003 W3_H06E0303\narc: A3 H01E0001\narc: A5 H02E0701\narc: B3 V02S0101\narc: B5 H01E0101\narc: C3 W1_H02E0601\narc: C5 V02N0201\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: D5 V02N0601\narc: E1_H01E0101 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F1\narc: H01W0100 Q6\narc: M0 H02E0601\narc: M1 E1_H02W0001\narc: M2 H02E0601\narc: M6 H02E0401\narc: MUXCLK3 CLK0\narc: S1_V02S0301 F1\narc: S3_V06S0103 F1\narc: V00B0100 F5\narc: V01S0100 F1\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000010000100001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111111111111111\nword: SLICEB.K1.INIT 0111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R3C42:PLC2\narc: S1_V02S0701 H01E0101\narc: E1_H01E0001 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\n\n.tile R3C43:PLC2\narc: E3_H06E0003 H01E0001\narc: W1_H02W0001 W3_H06E0003\narc: A0 V02N0501\narc: A2 V00T0000\narc: A3 H00L0100\narc: A4 V00B0000\narc: A5 Q5\narc: A6 H00R0000\narc: A7 Q7\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: H00R0000 Q6\narc: LSR1 H02W0301\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q3\narc: N1_V02N0001 Q2\narc: N1_V02N0701 Q5\narc: V00B0000 Q4\narc: V00T0000 Q2\narc: V01S0000 Q4\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C44:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0501 V01N0101\narc: H00R0000 V02S0401\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0601 H01E0001\narc: S1_V02S0001 H06E0003\narc: V00T0100 V02N0501\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 V01N0101\narc: A0 H00L0000\narc: A1 E1_H01E0001\narc: A2 V00T0000\narc: A3 H00L0100\narc: A4 V00B0000\narc: A5 Q5\narc: A6 V02N0301\narc: A7 Q7\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00L0100 Q3\narc: LSR0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q1\narc: N1_V02N0201 Q2\narc: N1_V02N0301 Q3\narc: N1_V02N0401 Q4\narc: N1_V02N0501 Q5\narc: N1_V02N0701 Q7\narc: V00B0000 Q4\narc: V00T0000 Q2\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 0101101010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C45:PLC2\narc: S1_V02S0701 S3_V06N0203\narc: A0 E1_H01E0001\narc: A1 H00L0100\narc: A2 V00T0000\narc: A3 V02S0701\narc: A4 V00B0000\narc: A5 Q5\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0100 Q1\narc: H01W0000 Q1\narc: LSR0 H02E0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q3\narc: N1_V02N0001 Q0\narc: N1_V02N0401 Q4\narc: V00B0000 Q4\narc: V00T0000 Q2\narc: V01S0000 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 0101101010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C46:PLC2\narc: E1_H02E0301 V06N0003\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 S3_V06N0303\narc: V00B0100 E1_H02W0701\narc: E3_H06E0203 W3_H06E0103\narc: CLK0 G_HPBX0000\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C47:PLC2\narc: E3_H06E0103 V06N0103\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 S3_V06N0203\n\n.tile R3C48:PLC2\narc: H00L0000 V02N0201\narc: H00R0000 E1_H02W0401\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0601 E1_H02W0601\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: V00T0000 V02S0601\narc: V00T0100 H02W0301\narc: V01S0000 S3_V06N0103\narc: W1_H02W0501 V06N0303\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0701 W3_H06E0203\narc: W1_H02W0701 W3_H06E0203\narc: CE0 H00R0000\narc: CE1 V02N0201\narc: CE2 H00L0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: LSR0 W1_H02E0301\narc: LSR1 V00T0100\narc: M0 V00B0100\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: S3_V06S0003 Q0\narc: S3_V06S0103 Q2\narc: S3_V06S0203 Q4\narc: S3_V06S0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R3C49:PLC2\narc: E1_H02E0301 H01E0101\narc: V00B0000 V02S0201\narc: V00B0100 H02E0701\narc: W1_H02W0301 W3_H06E0003\narc: CE0 V02N0201\narc: CLK0 G_HPBX0000\narc: LSR0 V00B0100\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: S3_V06S0003 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C4:PLC2\narc: E1_H02E0301 V06N0003\narc: E1_H02E0501 V02N0501\narc: H00L0000 E1_H02W0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02N0701\narc: V00B0000 H02W0401\narc: V00B0100 H02W0701\narc: V00T0000 H02W0201\narc: V00T0100 V02N0501\narc: V01S0000 S3_V06N0103\narc: W1_H02W0201 V06N0103\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0601 S3_V06N0303\narc: A3 V00T0000\narc: B1 V02N0101\narc: B3 N1_V02S0101\narc: B7 V02S0701\narc: C1 H00L0000\narc: C3 E1_H02W0401\narc: C7 V02N0201\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V00B0100\narc: D3 H02E0201\narc: D6 H00L0100\narc: D7 V02N0601\narc: E1_H02E0201 Q0\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q4\narc: H01W0100 F3\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00B0000\narc: M4 H02E0401\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: S1_V02S0601 Q6\narc: S3_V06S0003 Q0\narc: S3_V06S0303 Q6\narc: V01S0100 Q4\narc: W1_H02W0001 Q0\narc: W1_H02W0401 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1111111100000000\nword: SLICED.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R3C50:PLC2\narc: V00B0000 V02N0201\narc: V00B0100 V02S0301\narc: V00T0100 V02S0501\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 S3_V06N0303\narc: CE0 E1_H02W0101\narc: CE1 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: LSR0 H02E0301\narc: LSR1 V00B0000\narc: M0 V00B0100\narc: M2 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: S3_V06S0003 Q0\narc: S3_V06S0103 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R3C51:PLC2\narc: S1_V02S0101 E1_H02W0101\narc: V01S0100 S3_V06N0303\n\n.tile R3C52:PLC2\narc: S1_V02S0001 V01N0001\narc: W1_H02W0101 V01N0101\narc: E3_H06E0303 W3_H06E0203\n\n.tile R3C53:PLC2\narc: W1_H02W0101 W3_H06E0103\n\n.tile R3C58:PLC2\narc: E3_H06E0003 W3_H06E0303\n\n.tile R3C5:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: H00L0000 V02S0201\narc: H00L0100 V02N0101\narc: H00R0000 S1_V02N0601\narc: H00R0100 E1_H02W0701\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H02W0701\narc: V00T0000 V02N0401\narc: V00T0100 S1_V02N0701\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 E1_H02W0601\narc: B3 H00L0000\narc: C3 V02N0601\narc: CE0 E1_H02W0101\narc: CE2 H00L0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 N1_V01S0000\narc: D3 H00R0000\narc: E1_H02E0601 Q4\narc: F2 F5B_SLICE\narc: LSR0 H02E0301\narc: LSR1 H02E0501\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 E1_H02W0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q6\narc: S1_V02S0001 Q2\narc: S1_V02S0201 Q0\narc: V01S0000 Q6\narc: W1_H02W0201 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R3C64:PLC2\narc: E3_H06E0103 W3_H06E0003\n\n.tile R3C6:PLC2\narc: H00L0000 V02S0201\narc: H00R0000 H02E0601\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0201 W1_H02E0201\narc: V00B0000 E1_H02W0601\narc: V00B0100 H02W0501\narc: V00T0000 E1_H02W0201\narc: W1_H02W0001 V06N0003\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0701 N1_V01S0100\narc: A1 V02N0701\narc: A3 V02N0501\narc: A5 N1_V01S0100\narc: A7 H00R0000\narc: B0 V02S0301\narc: B1 E1_H02W0301\narc: B2 V02N0101\narc: B3 E1_H02W0101\narc: B5 H00L0000\narc: B7 V00T0000\narc: C0 E1_H01W0000\narc: C1 H00R0100\narc: C2 N1_V01N0001\narc: C3 V02N0401\narc: C5 E1_H02W0401\narc: C7 V02N0001\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V00B0100\narc: D2 V00T0100\narc: D3 S1_V02N0001\narc: D5 V02S0601\narc: D7 V00B0000\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: LSR0 H02E0301\narc: LSR1 H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F5\narc: V00T0100 F3\narc: V01S0100 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0011111111111111\nword: SLICEB.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 0011111111111111\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R3C70:PLC2\narc: E1_H02E0201 W3_H06E0103\n\n.tile R3C7:PLC2\narc: E1_H02E0601 S1_V02N0601\narc: H00L0100 V02S0301\narc: H00R0000 S1_V02N0601\narc: S1_V02S0101 H06W0103\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02W0701\narc: V00T0000 H02W0001\narc: V00T0100 V02S0501\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 E1_H02W0701\narc: A5 N1_V01S0100\narc: A7 H00L0000\narc: B1 V00T0000\narc: B5 E1_H02W0101\narc: B7 N1_V01S0000\narc: C1 V02N0401\narc: C5 H02W0401\narc: C7 V02S0201\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H00R0000\narc: D5 E1_H02W0001\narc: D7 V02S0601\narc: E1_H01E0001 Q0\narc: F0 F5A_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 F7\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00B0100\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: S1_V02S0201 Q0\narc: V01S0100 Q2\narc: W1_H02W0501 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111000011001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R3C8:PLC2\narc: H00L0100 H02W0101\narc: H00R0000 V02N0601\narc: H00R0100 H02W0701\narc: N1_V02N0401 H01E0001\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 H02W0501\narc: V00B0000 H02E0601\narc: V00B0100 V02S0301\narc: V00T0100 V02N0701\narc: W1_H02W0101 V01N0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 V02N0701\narc: A3 V00T0000\narc: B3 H01W0100\narc: B5 V01S0000\narc: C3 H02W0601\narc: C5 V02N0201\narc: CE0 E1_H02W0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 H00R0000\narc: D4 H00L0100\narc: D5 V00B0000\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: H01W0100 Q6\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M0 V00B0100\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V02N0601 Q4\narc: S3_V06S0203 Q4\narc: V00T0000 Q0\narc: V01S0000 Q6\narc: V01S0100 Q4\narc: W1_H02W0001 Q0\narc: W1_H02W0301 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 1111111100000000\nword: SLICEC.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R3C9:PLC2\narc: V00B0100 V02N0101\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V01N0101\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 S3_V06N0203\narc: S1_V02S0001 W3_H06E0003\narc: S3_V06S0003 W3_H06E0003\narc: CLK0 G_HPBX0000\narc: D3 H02W0201\narc: E3_H06E0203 Q4\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: V00T0100 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R40C3:PLC2\narc: W1_H02W0701 N3_V06S0203\n\n.tile R40C47:PLC2\narc: N1_V02N0401 N3_V06S0203\n\n.tile R40C58:PLC2\narc: N1_V01N0101 N3_V06S0203\n\n.tile R40C69:PLC2\narc: S3_V06S0303 N3_V06S0203\n\n.tile R40C70:PLC2\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0501 N3_V06S0303\narc: S1_V02S0001 N3_V06S0003\narc: S3_V06S0203 N3_V06S0103\n\n.tile R41C2:PLC2\narc: W1_H02W0701 N1_V02S0701\n\n.tile R41C3:PLC2\narc: S3_V06S0103 N3_V06S0103\n\n.tile R41C70:PLC2\narc: E1_H02E0001 V02S0001\n\n.tile R42C69:PLC2\narc: E1_H02E0301 N3_V06S0003\n\n.tile R42C70:PLC2\narc: E1_H02E0201 N3_V06S0103\narc: S1_V02S0101 N3_V06S0103\n\n.tile R43C2:PLC2\narc: E3_H06E0103 S3_V06N0103\n\n.tile R43C69:PLC2\narc: E1_H02E0201 V02N0201\n\n.tile R43C70:PLC2\narc: E1_H02E0701 V06S0203\n\n.tile R43C8:PLC2\narc: S1_V02S0201 W3_H06E0103\n\n.tile R44C2:PLC2\narc: W1_H02W0501 N3_V06S0303\n\n.tile R44C69:PLC2\narc: E1_H02E0501 S1_V02N0501\narc: N1_V02N0201 N3_V06S0103\n\n.tile R44C70:PLC2\narc: E1_H02E0101 N1_V02S0101\n\n.tile R44C8:PLC2\narc: D1 V02S0201\narc: F1 F1_SLICE\narc: N3_V06N0103 F1\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R46C69:PLC2\narc: N1_V02N0501 N3_V06S0303\n\n.tile R47C3:PLC2\narc: S1_V02S0101 N3_V06S0103\n\n.tile R4C10:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0501 V01N0101\narc: E1_H02E0701 H01E0101\narc: H00R0000 H02E0601\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 S1_V02N0101\narc: S1_V02S0301 H06W0003\narc: V00B0000 V02N0201\narc: V00B0100 V02N0301\narc: V00T0000 H02W0201\narc: V00T0100 V02N0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 S3_V06N0303\narc: W3_H06W0303 S3_V06N0303\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q0\narc: E1_H02E0201 Q2\narc: E3_H06E0003 Q0\narc: E3_H06E0203 Q4\narc: H01W0100 Q6\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00B0000\narc: M2 V00B0100\narc: M4 E1_H02W0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: S1_V02S0001 Q2\narc: S1_V02S0201 Q0\narc: S3_V06S0103 Q2\narc: S3_V06S0203 Q4\narc: S3_V06S0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R4C11:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 S1_V02N0701\narc: H00R0000 V02N0401\narc: N1_V02N0601 H02W0601\narc: V00B0000 V02N0201\narc: V00T0000 H02E0201\narc: V00T0100 V02S0701\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0701 S3_V06N0203\narc: W3_H06W0203 S3_V06N0203\narc: A0 V02N0501\narc: A2 W1_H02E0501\narc: A3 H01E0001\narc: A4 V00T0000\narc: A5 V00B0000\narc: A6 H02E0701\narc: A7 H00R0000\narc: B2 H00L0000\narc: B3 V02N0301\narc: B4 V02S0501\narc: B5 H02E0301\narc: B6 N1_V01S0000\narc: B7 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: LSR0 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F5\narc: N1_V02N0401 F4\narc: S3_V06S0003 F3\narc: V01S0000 F6\narc: V01S0100 F7\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R4C12:PLC2\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 V01N0101\narc: E1_H02E0701 V02N0701\narc: H00L0000 W1_H02E0001\narc: H00L0100 H02E0101\narc: H00R0000 N1_V02S0601\narc: S1_V02S0201 V01N0001\narc: S1_V02S0601 H06E0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02N0601\narc: V00T0100 H02E0301\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0401 E1_H01W0000\narc: W3_H06W0003 S3_V06N0003\narc: A0 E1_H02W0501\narc: A1 H02E0501\narc: A2 V00B0000\narc: A3 H00L0100\narc: A4 V02N0301\narc: A5 V00T0000\narc: A6 W1_H02E0501\narc: A7 V00T0100\narc: B0 H01W0100\narc: B1 N1_V02S0101\narc: B2 H00L0000\narc: B3 S1_V02N0301\narc: B4 H00R0000\narc: B5 S1_V02N0501\narc: B6 V00B0100\narc: B7 V02S0501\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR1 H02W0501\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V02N0401 F4\narc: N1_V02N0701 F7\narc: S1_V02S0101 F3\narc: S3_V06S0303 F5\narc: V01S0000 F2\narc: W1_H02W0601 F6\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R4C13:PLC2\narc: H00L0000 V02N0001\narc: H00R0000 H02E0401\narc: H00R0100 E1_H02W0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0401 H01E0001\narc: S1_V02S0001 H06E0003\narc: S1_V02S0701 H02W0701\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02S0301\narc: V00T0000 W1_H02E0201\narc: W1_H02W0101 V01N0101\narc: W1_H02W0501 V02S0501\narc: W3_H06W0303 S3_V06N0303\narc: A0 H02E0701\narc: A1 W1_H02E0701\narc: A2 E1_H02W0701\narc: A3 V00T0000\narc: A4 V02N0301\narc: A5 S1_V02N0101\narc: A6 H00L0000\narc: A7 H02E0501\narc: B0 H01W0100\narc: B1 V02S0101\narc: B2 H00R0000\narc: B3 H00R0100\narc: B4 V02S0701\narc: B5 N1_V02S0701\narc: B6 N1_V01S0000\narc: B7 V00B0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 F4\narc: E1_H02E0501 F5\narc: E1_H02E0701 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR1 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V02N0301 F1\narc: N1_V02N0601 F6\narc: W1_H02W0001 F2\narc: W3_H06W0003 F3\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R4C14:PLC2\narc: E1_H02E0101 V01N0101\narc: H00L0000 E1_H02W0001\narc: H00L0100 S1_V02N0101\narc: H00R0000 V02N0601\narc: H00R0100 V02S0701\narc: N1_V02N0201 H01E0001\narc: N1_V02N0501 H02E0501\narc: S1_V02S0401 E1_H01W0000\narc: V00B0000 V02N0201\narc: V00B0100 V02S0101\narc: V00T0000 S1_V02N0601\narc: W1_H02W0501 E1_H02W0401\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0203 S3_V06N0203\narc: A0 V02N0701\narc: A1 H00L0100\narc: A2 V00B0000\narc: A3 S1_V02N0501\narc: A4 V02N0301\narc: A5 E1_H02W0701\narc: A6 H00R0000\narc: A7 V02N0101\narc: B0 H01W0100\narc: B1 E1_H02W0301\narc: B2 H00R0100\narc: B3 E1_H02W0101\narc: B4 V02S0501\narc: B5 H00L0000\narc: B6 V00B0100\narc: B7 V00T0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 F3\narc: E1_H02E0301 F1\narc: E1_H02E0701 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR0 H02W0301\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F6\narc: N1_V02N0601 F4\narc: S3_V06S0103 F2\narc: W1_H02W0701 F7\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R4C15:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V02N0501\narc: H00L0100 S1_V02N0101\narc: H00R0000 V02N0601\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 E1_H02W0701\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 S1_V02N0701\narc: E3_H06E0303 W3_H06E0203\narc: A0 H00R0000\narc: A1 H00L0100\narc: B0 V00T0000\narc: B1 H02E0101\narc: CLK0 G_HPBX0000\narc: D7 S1_V02N0401\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: LSR1 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: V00B0100 F7\narc: V00T0000 Q0\narc: V01S0000 F2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000001010\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R4C16:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0401 S1_V02N0401\narc: E3_H06E0303 S3_V06N0303\narc: H00R0000 S1_V02N0601\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0601 H02W0601\narc: V00B0100 W1_H02E0701\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0701 V02N0701\narc: W1_H02W0401 W3_H06E0203\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D5 S1_V02N0601\narc: E1_H02E0501 F5\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: LSR1 V00T0100\narc: M2 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00T0100 F1\narc: W1_H02W0001 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R4C17:PLC2\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 H02W0301\narc: H00R0000 N1_V02S0401\narc: H00R0100 H02W0501\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 V01N0101\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0303 H06W0303\narc: V00B0000 H02E0401\narc: V00B0100 W1_H02E0501\narc: V00T0000 W1_H02E0001\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 E1_H02W0601\narc: A0 V02S0701\narc: A1 H02W0501\narc: A2 V00B0000\narc: A3 V00B0000\narc: B0 H00R0100\narc: B1 E1_H01W0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B7 H02W0101\narc: C0 W1_H02E0401\narc: C1 W1_H02E0401\narc: C2 H00L0100\narc: C3 W1_H02E0401\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 V00B0100\narc: D3 H02E0001\narc: D7 N1_V02S0401\narc: E1_H01E0101 F0\narc: E1_H02E0001 F2\narc: E1_H02E0201 F0\narc: E1_H02E0501 F7\narc: E3_H06E0003 F3\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q4\narc: LSR0 H02E0501\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: S1_V02S0101 F1\narc: S1_V02S0701 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001100\nword: SLICEA.K0.INIT 1000000000000000\nword: SLICEA.K1.INIT 1110000000100000\nword: SLICEB.K0.INIT 0000001000000000\nword: SLICEB.K1.INIT 1111111101111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R4C18:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 H01E0101\narc: E1_H02E0301 N1_V01S0100\narc: H00L0100 N1_V02S0301\narc: H00R0100 S1_V02N0501\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0501 E1_H01W0100\narc: W1_H02W0101 V01N0101\narc: A0 V02N0501\narc: A3 E1_H01E0001\narc: A5 N1_V01N0101\narc: A7 Q7\narc: B0 V01N0001\narc: B3 H00R0000\narc: B4 H00R0000\narc: B5 H00L0000\narc: B7 V00B0000\narc: C0 H00L0100\narc: C1 V02N0401\narc: C2 N1_V01N0001\narc: C3 H00L0000\narc: C4 V00T0000\narc: C5 E1_H01E0101\narc: C7 V00T0000\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 F0\narc: D2 Q2\narc: D3 V01S0100\narc: D4 V02N0601\narc: D5 V00B0000\narc: D6 V00B0000\narc: D7 V02N0601\narc: E1_H01E0001 Q7\narc: E1_H01E0101 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q6\narc: H01W0000 F0\narc: H01W0100 F3\narc: LSR0 H02E0501\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q7\narc: S1_V02S0301 F1\narc: V00B0000 Q6\narc: V00T0000 Q2\narc: V01S0000 Q4\narc: V01S0100 Q4\narc: W1_H02W0301 F3\narc: W1_H02W0501 F5\nword: SLICEC.K0.INIT 0011111111000000\nword: SLICEC.K1.INIT 0000001000000000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0110101010101010\nword: SLICEB.K0.INIT 0000111111110000\nword: SLICEB.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0100111111001100\nword: SLICEA.K1.INIT 0000111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R4C19:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 W1_H02E0201\narc: E3_H06E0203 S3_V06N0203\narc: H00R0000 V02N0601\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0501 E1_H02W0501\narc: V00T0100 S1_V02N0701\narc: W1_H02W0601 S3_V06N0303\narc: W3_H06W0103 E3_H06W0003\narc: A1 E1_H01E0001\narc: A7 N1_V01N0101\narc: B1 V00T0000\narc: B4 V02S0501\narc: B7 V00B0100\narc: C1 H02W0401\narc: C4 E1_H01E0101\narc: C5 V02S0201\narc: C7 E1_H01E0101\narc: CE0 H00R0000\narc: CE1 H02E0101\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 Q0\narc: D1 V02N0001\narc: D4 V00B0000\narc: D5 H01W0000\narc: D6 H01W0000\narc: D7 V00B0000\narc: E1_H01E0001 Q1\narc: E1_H01E0101 Q6\narc: E1_H02E0001 Q0\narc: E1_H02E0401 Q4\narc: E1_H02E0501 Q5\narc: E1_H02E0701 Q7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q6\narc: H01W0100 Q7\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M2 H02W0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q5\narc: S1_V02S0301 Q1\narc: S1_V02S0601 Q6\narc: S1_V02S0701 Q5\narc: V00B0000 Q4\narc: V00B0100 Q7\narc: V00T0000 Q0\narc: V01S0000 Q0\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0110101010101010\nword: SLICEC.K0.INIT 0011111111000000\nword: SLICEC.K1.INIT 0000111111110000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0110110011001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\n\n.tile R4C20:PLC2\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 E1_H02W0001\narc: H00R0000 V02N0601\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 H02E0301\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 H02E0401\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0501\narc: V00T0000 H02W0201\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0401 V01N0001\narc: W3_H06W0303 E3_H06W0303\narc: A0 H01E0001\narc: A1 H01E0001\narc: A2 H01E0001\narc: A3 H01E0001\narc: A4 H02E0701\narc: A5 E1_H01W0000\narc: B0 V01N0001\narc: B1 V01N0001\narc: B2 V01N0001\narc: B3 V01N0001\narc: B4 V00B0100\narc: B5 H00L0000\narc: C0 V02N0401\narc: C1 V02N0401\narc: C2 V02N0401\narc: C3 V02N0401\narc: C4 H02E0401\narc: C5 V00T0000\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE3 H02E0101\narc: CLK1 G_HPBX0000\narc: D0 H02E0001\narc: D1 H02E0001\narc: D2 H02E0001\narc: D3 H02E0001\narc: D4 W1_H02E0001\narc: D5 E1_H01W0100\narc: E1_H02E0601 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0000 Q0\narc: LSR1 E1_H02W0301\narc: M6 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: MUXCLK3 CLK1\narc: S1_V02S0101 Q3\narc: S1_V02S0201 Q2\narc: V01S0100 Q1\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R4C21:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0701 V02S0701\narc: H00L0000 W1_H02E0201\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0401 E1_H01W0000\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 H02W0401\narc: V00B0100 H02W0701\narc: V00T0000 E1_H02W0001\narc: W1_H02W0001 V01N0001\narc: W1_H02W0501 E1_H01W0100\narc: E1_H02E0501 W3_H06E0303\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: H01W0000 Q2\narc: H01W0100 Q6\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 H02W0601\narc: M2 E1_H02W0601\narc: M4 V00T0000\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: W1_H02W0201 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R4C22:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 V02S0301\narc: H00R0000 N1_V02S0601\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0701 W1_H02E0701\narc: V00B0000 W1_H02E0601\narc: W1_H02W0001 H01E0001\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0501 W3_H06E0303\narc: A2 H02E0701\narc: B2 H02E0101\narc: B3 H00R0000\narc: C2 V02S0401\narc: C3 H00L0100\narc: CE0 H02W0101\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D2 H02E0001\narc: D3 F2\narc: E1_H01E0001 Q0\narc: E1_H02E0601 Q4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0000 F3\narc: H01W0100 F2\narc: M0 E1_H02W0601\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V00T0000 Q0\narc: V01S0000 Q4\narc: V01S0100 F3\narc: W1_H02W0101 F3\narc: W1_H02W0301 F3\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000001\nword: SLICEB.K1.INIT 0000110011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R4C23:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0401 V02N0401\narc: E3_H06E0103 N1_V01S0100\narc: H00R0000 H02E0401\narc: S1_V02S0101 V01N0101\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 E1_H01W0000\narc: W1_H02W0601 H01E0001\narc: H01W0000 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: M2 H02E0601\narc: M4 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: V00T0000 Q2\narc: W1_H02W0001 Q2\narc: W1_H02W0401 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R4C24:PLC2\narc: E1_H02E0501 V02N0501\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0303 S3_V06N0303\narc: H00R0000 V02N0601\narc: H00R0100 V02N0701\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0101 H02E0101\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 W1_H02E0501\narc: V00B0100 W1_H02E0701\narc: V00T0000 V02N0401\narc: V00T0100 H02E0101\narc: W1_H02W0601 H01E0001\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CE2 H00R0100\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: E1_H02E0401 Q6\narc: H01W0000 Q4\narc: H01W0100 Q0\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 V00T0100\narc: M2 H02W0601\narc: M4 V00T0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q4\narc: N1_V02N0001 Q0\narc: N1_V02N0201 Q2\narc: N1_V02N0401 Q4\narc: V01S0000 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R4C25:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0601 V02S0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0001 V01N0001\narc: S1_V02S0201 N1_V02S0701\narc: V00B0000 W1_H02E0401\narc: V00T0100 V02S0701\narc: W1_H02W0601 E3_H06W0303\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: A3 V00T0000\narc: A5 V00T0000\narc: B1 V02N0301\narc: B3 V02N0101\narc: B5 H00R0000\narc: B7 F3\narc: C0 H02W0401\narc: C1 N1_V01S0100\narc: C2 H00R0100\narc: C3 V02S0401\narc: C4 E1_H02W0601\narc: C5 V00T0100\narc: C7 V02N0001\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 V00B0100\narc: D2 E1_H02W0001\narc: D3 V00T0100\narc: D4 E1_H02W0001\narc: D5 E1_H02W0201\narc: D7 H00L0100\narc: E1_H02E0001 Q0\narc: E1_H02E0201 Q2\narc: E3_H06E0203 Q4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: H01W0100 Q2\narc: LSR0 V00B0000\narc: LSR1 H02E0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q0\narc: V00B0100 F5\narc: V00T0000 Q2\narc: V01S0000 F7\narc: V01S0100 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEC.K0.INIT 0000000011110000\nword: SLICEC.K1.INIT 1100010000110001\nword: SLICEB.K0.INIT 0000000011110000\nword: SLICEB.K1.INIT 1000001011000011\nword: SLICEA.K0.INIT 0000000011110000\nword: SLICEA.K1.INIT 1100001100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R4C26:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0301 V02N0301\narc: E1_H02E0601 V01N0001\narc: H00L0100 E1_H02W0101\narc: H00R0100 V02S0701\narc: N1_V02N0101 H06E0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0701 V01N0101\narc: V00B0100 E1_H02W0701\narc: V00T0100 N1_V02S0701\narc: W1_H02W0401 E1_H01W0000\narc: W3_H06W0303 E3_H06W0303\narc: A1 V02N0701\narc: A3 V00T0000\narc: A5 V00T0000\narc: A7 N1_V01N0101\narc: B1 H01W0100\narc: B3 H00R0000\narc: B5 H00R0000\narc: B7 H02E0101\narc: C0 H00L0100\narc: C1 N1_V01S0100\narc: C2 H02W0401\narc: C3 H02E0401\narc: C4 V00B0100\narc: C5 H02E0601\narc: C6 V02S0201\narc: C7 N1_V02S0001\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 N1_V01S0000\narc: D2 S1_V02N0201\narc: D3 V00T0100\narc: D4 H02W0001\narc: D5 H00R0100\narc: D6 H02W0001\narc: D7 V02S0601\narc: E1_H01E0001 F3\narc: E1_H01E0101 Q4\narc: E1_H02E0001 Q2\narc: E1_H02E0201 Q0\narc: E1_H02E0401 Q6\narc: E1_H02E0701 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0100 Q0\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q6\narc: V00T0000 Q2\narc: V01S0000 F1\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0000000011110000\nword: SLICEC.K1.INIT 1000010000100001\nword: SLICEA.K0.INIT 0000000011110000\nword: SLICEA.K1.INIT 1000010000100001\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 1000010000100001\nword: SLICEB.K0.INIT 0000000011110000\nword: SLICEB.K1.INIT 1000010000100001\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\n\n.tile R4C27:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0301 H01E0101\narc: H00L0000 W1_H02E0001\narc: H00L0100 S1_V02N0101\narc: H00R0000 V02S0401\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S3_V06N0303\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 H02E0701\narc: V00B0000 V02N0201\narc: V00T0000 W1_H02E0201\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 E1_H02W0301\narc: A0 H00L0100\narc: B2 H00R0000\narc: B3 H00L0000\narc: B4 V02N0701\narc: B5 E1_H02W0101\narc: B6 V00B0000\narc: B7 V00T0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: N1_V01N0001 F5\narc: N1_V02N0201 F2\narc: V01S0000 F4\narc: V01S0100 F6\narc: W1_H02W0701 F7\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R4C28:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0501 S1_V02N0501\narc: E3_H06E0103 S3_V06N0103\narc: H00L0000 W1_H02E0201\narc: H00R0000 W1_H02E0401\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0501 H06E0303\narc: N3_V06N0103 S1_V02N0201\narc: V00B0000 W1_H02E0601\narc: V00T0000 W1_H02E0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: B0 V00B0000\narc: B1 V00T0000\narc: B2 H00R0000\narc: B3 H00L0000\narc: B4 V02S0501\narc: B5 W1_H02E0101\narc: B6 W1_H02E0301\narc: B7 H02E0301\narc: E1_H01E0001 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F6\narc: N1_V01N0001 F2\narc: V01S0000 F5\narc: W1_H02W0001 F0\narc: W1_H02W0101 F3\narc: W1_H02W0701 F7\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R4C29:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: N3_V06N0003 S1_V02N0001\narc: S1_V02S0001 V01N0001\narc: V00B0000 E1_H02W0401\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02E0001\narc: V00T0100 V02N0501\narc: W1_H02W0101 V02N0101\narc: W1_H02W0401 H01E0001\narc: E3_H06E0303 W3_H06E0303\narc: B0 W1_H02E0101\narc: B1 V00B0000\narc: CLK0 G_HPBX0000\narc: E1_H02E0401 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: LSR0 V00B0100\narc: LSR1 V00T0000\narc: M4 V00T0100\narc: M6 N1_V01N0101\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q4\narc: W1_H02W0201 F0\narc: W1_H02W0301 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R4C2:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0701 V02N0701\narc: H00R0000 V02N0601\narc: H00R0100 H02E0501\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0701 E3_H06W0203\narc: V00B0000 V02N0201\narc: V00B0100 H02E0701\narc: V00T0000 E1_H02W0201\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q6\narc: E1_H02E0201 Q0\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M0 V00T0000\narc: M2 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R4C30:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E3_H06E0303 W1_H02E0501\narc: S1_V02S0101 V01N0101\narc: V00T0000 W1_H02E0001\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: CLK0 G_HPBX0000\narc: LSR1 V00T0000\narc: M6 H02E0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: S1_V02S0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R4C31:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: H00L0000 W1_H02E0201\narc: H00L0100 V02N0301\narc: H00R0100 V02N0701\narc: S1_V02S0001 N1_V02S0501\narc: V00B0000 V02S0201\narc: V00T0000 V02N0601\narc: N1_V02N0501 W3_H06E0303\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0303 E3_H06W0303\narc: CE0 H00L0100\narc: CE1 H00R0100\narc: CE2 H00L0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: E1_H02E0001 Q0\narc: E1_H02E0401 Q6\narc: M0 V00B0000\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R4C32:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E3_H06E0003 W1_H02E0001\narc: H00L0000 H02E0001\narc: H00L0100 N1_V02S0101\narc: H00R0000 S1_V02N0601\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 S3_V06N0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02W0401\narc: W3_H06W0303 E3_H06W0303\narc: A1 H00L0100\narc: A2 H00L0100\narc: A3 H00L0100\narc: B1 S1_V02N0101\narc: B2 H00R0000\narc: B3 H00R0000\narc: C1 V02S0401\narc: C2 V02S0401\narc: C3 V02S0401\narc: D1 H02E0201\narc: D2 H02E0201\narc: D3 H02E0201\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0000\narc: M1 H02W0001\narc: M2 V00B0000\narc: M3 H00L0000\narc: M4 H02W0401\narc: M5 H02W0001\narc: M6 H02W0401\nword: SLICEB.K0.INIT 0000010000000000\nword: SLICEB.K1.INIT 0000010000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0000010000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R4C33:PLC2\narc: E1_H02E0201 N1_V02S0201\narc: E3_H06E0203 H01E0001\narc: H00L0000 W1_H02E0201\narc: H00L0100 H02E0101\narc: H00R0000 W1_H02E0401\narc: N1_V02N0401 S1_V02N0101\narc: V00T0000 V02S0601\narc: W1_H02W0001 V02N0001\narc: W1_H02W0401 E1_H02W0101\narc: A0 H00L0100\narc: B0 S1_V02N0301\narc: C0 H02W0601\narc: D0 V02N0201\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H00L0000\narc: M2 V00T0000\narc: M3 H00R0000\narc: M4 V00T0000\narc: M5 H00L0000\narc: M6 V00T0000\nword: SLICEA.K0.INIT 1011000010111011\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R4C34:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0501 S1_V02N0501\narc: E3_H06E0203 S3_V06N0203\narc: H00R0000 S1_V02N0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0001 E1_H01W0000\narc: S3_V06S0003 E1_H01W0000\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02N0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0601 V02S0601\narc: E3_H06E0103 W3_H06E0103\narc: D0 S1_V02N0201\narc: D1 V00B0100\narc: D2 V02S0001\narc: D3 H02E0201\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 E1_H02W0601\narc: M1 H00R0000\narc: M2 E1_H02W0601\narc: M3 H00R0100\narc: M4 V00B0000\narc: M5 H00R0000\narc: M6 V00B0000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R4C35:PLC2\narc: E1_H02E0001 V02S0001\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02N0201\narc: H00L0100 V02S0101\narc: H00R0000 E1_H02W0601\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 H06W0003\narc: N1_V02N0301 S3_V06N0003\narc: N3_V06N0303 S3_V06N0303\narc: V00B0000 N1_V02S0201\narc: V00T0000 H02E0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 S3_V06N0103\narc: E3_H06E0003 W3_H06E0303\narc: A0 H00L0100\narc: B0 V02N0101\narc: C0 H00L0000\narc: CE2 S1_V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 F1\narc: M0 V00B0000\narc: M1 E1_H02W0001\narc: M2 V00B0000\narc: M4 V00T0000\narc: M6 N1_V01N0101\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V02N0601 Q6\narc: S3_V06S0103 F1\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1000110010101111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R4C36:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0701 E3_H06W0203\narc: H00L0100 V02N0101\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0701 V01N0101\narc: V00T0000 V02N0601\narc: V01S0000 S3_V06N0103\narc: W1_H02W0601 S1_V02N0601\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: A2 V02S0501\narc: A3 V02S0501\narc: B2 V02S0101\narc: B3 V02S0101\narc: C2 E1_H02W0601\narc: C3 E1_H02W0601\narc: D2 H02E0001\narc: D3 H02E0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H00L0100\narc: M2 V00T0000\narc: M3 H00R0100\narc: M4 V00T0000\narc: M5 H00L0100\narc: M6 V00T0000\narc: S1_V02S0101 F3\nword: SLICEB.K0.INIT 1111111111111110\nword: SLICEB.K1.INIT 1111111111111110\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R4C37:PLC2\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: H00L0100 H02E0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 H02E0701\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S3_V06N0303\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0501 V01N0101\narc: S3_V06S0003 H06E0003\narc: V00B0100 N1_V02S0101\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0601 S1_V02N0601\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0303 E3_H06W0203\narc: A0 N1_V02S0701\narc: B0 V02S0101\narc: C0 H00L0100\narc: D0 V02N0201\narc: E1_H01E0101 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: M3 H00R0100\narc: M4 V00B0100\narc: M5 H00R0000\narc: M6 V00B0100\narc: S1_V02S0301 F3\nword: SLICEA.K0.INIT 1000110010101111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R4C38:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 S3_V06N0203\narc: E3_H06E0003 S3_V06N0003\narc: H00L0100 N1_V02S0101\narc: H00R0000 V02S0401\narc: H00R0100 H02E0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0101 H01E0101\narc: S3_V06S0103 H06E0103\narc: V00T0000 V02S0401\narc: V00T0100 H02W0301\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0601 E1_H02W0301\narc: W3_H06W0003 S3_V06N0003\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0303 E3_H06W0303\narc: A0 H00R0000\narc: A1 H00R0000\narc: A2 V00T0000\narc: B0 V02N0101\narc: B1 V02N0101\narc: B2 V02N0101\narc: C0 H02E0601\narc: C1 H02E0601\narc: C2 H02E0601\narc: D0 V02N0201\narc: D1 V02N0201\narc: D2 V02N0201\narc: E1_H02E0301 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00L0100\narc: M2 V00T0100\narc: M3 H00R0100\narc: M4 V00T0100\narc: M5 H00L0100\narc: M6 V00T0100\nword: SLICEA.K0.INIT 1000101011001111\nword: SLICEA.K1.INIT 1000101011001111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1000101011001111\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R4C39:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0601 W1_H02E0601\narc: H00L0000 H02E0201\narc: H00L0100 H02W0101\narc: H00R0000 W1_H02E0601\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0401 H02E0401\narc: S1_V02S0101 N1_V02S0001\narc: V00B0000 N1_V02S0001\narc: V00B0100 E1_H02W0701\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0301 S1_V02N0301\narc: A1 N1_V02S0701\narc: A2 V00B0000\narc: A3 V00B0000\narc: B1 S1_V02N0301\narc: B2 S1_V02N0301\narc: B3 S1_V02N0301\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00L0000\narc: M2 V00B0100\narc: M3 E1_H02W0201\narc: M4 V00B0100\narc: M5 H00L0000\narc: M6 V00B0100\narc: W1_H02W0101 F3\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0000010000000000\nword: SLICEB.K0.INIT 0000010000000000\nword: SLICEB.K1.INIT 0000010000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R4C3:PLC2\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 S1_V02N0501\narc: H00L0000 H02E0201\narc: H00R0000 V02N0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 H06W0003\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 H02W0601\narc: V00B0100 E1_H02W0501\narc: A1 F5\narc: A3 H01E0001\narc: A5 E1_H01W0000\narc: A7 H00L0000\narc: B0 V02S0301\narc: B1 H02W0101\narc: B2 V02N0301\narc: B3 H00R0000\narc: B5 V02N0501\narc: B7 H02E0301\narc: C0 H00R0100\narc: C1 N1_V01N0001\narc: C2 H00L0100\narc: C3 V02S0601\narc: C5 V00B0100\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 E1_H02W0001\narc: D2 N1_V01S0000\narc: D3 W1_H02E0001\narc: D5 H02W0001\narc: D7 V02S0601\narc: E3_H06E0103 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F7\narc: S3_V06S0003 Q0\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0011111111111111\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0011111111111111\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R4C40:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: H00L0000 V02N0201\narc: H00L0100 V02N0301\narc: H00R0000 H02E0601\narc: N1_V02N0401 W1_H02E0401\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0301 W1_H02E0301\narc: V00B0000 V02S0001\narc: V00T0100 H02E0301\narc: W1_H02W0101 N1_V02S0101\narc: N1_V02N0701 W3_H06E0203\narc: S3_V06S0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: A0 H02W0701\narc: A1 H02W0701\narc: A2 V00B0000\narc: B0 N1_V02S0101\narc: B1 N1_V02S0101\narc: B2 N1_V02S0101\narc: C0 H00L0000\narc: C1 H00L0000\narc: C2 H00L0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H02E0001\narc: M2 V00T0100\narc: M3 H00L0100\narc: M4 V00T0100\narc: M5 H02E0001\narc: M6 V00T0100\narc: W1_H02W0301 F3\nword: SLICEA.K0.INIT 1000110010101111\nword: SLICEA.K1.INIT 1000110010101111\nword: SLICEB.K0.INIT 1000110010101111\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R4C41:PLC2\narc: H00L0000 N1_V02S0201\narc: H00L0100 H02E0101\narc: H00R0000 W1_H02E0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0601 H02W0601\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0701 N1_V01S0100\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02S0301\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0701 N1_V01S0100\narc: E1_H02E0001 W3_H06E0003\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: A1 H00L0000\narc: A2 V00B0000\narc: A3 V00B0000\narc: B1 W1_H02E0301\narc: B2 W1_H02E0301\narc: B3 W1_H02E0301\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00B0100\narc: M1 E1_H02W0001\narc: M2 V00B0100\narc: M3 H00R0100\narc: M4 V00B0100\narc: M5 E1_H02W0001\narc: M6 V00B0100\nword: SLICEB.K0.INIT 0000010000000000\nword: SLICEB.K1.INIT 0000010000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0000010000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R4C42:PLC2\narc: E3_H06E0103 W1_H02E0201\narc: H00R0100 N1_V02S0701\narc: V00B0100 V02N0301\narc: V00T0100 H02W0301\narc: W1_H02W0601 S3_V06N0303\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0301 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: CE0 H00R0100\narc: CE2 V02N0601\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: H01W0000 Q0\narc: M0 V00T0100\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R4C43:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0601 E1_H01W0000\narc: N1_V02N0001 N1_V01S0000\narc: S1_V02S0201 V01N0001\narc: W1_H02W0001 V02N0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 H01E0101\narc: N1_V02N0501 W3_H06E0303\narc: W3_H06W0203 S3_V06N0203\n\n.tile R4C44:PLC2\narc: E1_H02E0401 V01N0001\narc: E3_H06E0103 V06N0103\narc: N1_V02N0301 N1_V01S0100\narc: S1_V02S0201 H06W0103\narc: S3_V06S0003 E1_H01W0000\narc: V00B0000 H02E0601\narc: H01W0000 W3_H06E0103\narc: A1 E1_H02W0701\narc: B1 S1_V02N0301\narc: B6 V00B0000\narc: B7 W1_H02E0301\narc: C1 V02N0401\narc: C6 V02S0001\narc: C7 F6\narc: D1 E1_H02W0201\narc: D6 H02E0001\narc: D7 W1_H02E0201\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V01N0101 F7\narc: N1_V02N0501 F7\narc: N3_V06N0103 F1\narc: S3_V06S0303 F6\narc: W3_H06W0303 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010001110101111\nword: SLICED.K0.INIT 0011111100001100\nword: SLICED.K1.INIT 1111110011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R4C45:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 V02S0701\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0401 E1_H02W0401\narc: V00T0100 V02N0501\narc: CE0 H02W0101\narc: CLK0 G_HPBX0000\narc: H01W0000 Q0\narc: LSR0 H02W0301\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R4C46:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0301 S1_V02N0301\narc: H00L0000 H02E0201\narc: H00L0100 H02W0101\narc: H00R0100 S1_V02N0701\narc: H01W0000 E3_H06W0103\narc: S1_V02S0001 H02E0001\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0103 E3_H06W0103\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0701 N1_V01S0100\narc: W1_H02W0201 W3_H06E0103\narc: A1 H00L0100\narc: A3 E1_H02W0501\narc: A5 E1_H01W0000\narc: A6 H02E0701\narc: A7 F5\narc: B1 H00R0100\narc: B3 H02W0301\narc: B5 H02W0301\narc: B6 H02E0301\narc: B7 S1_V02N0501\narc: C1 V02N0401\narc: C3 H00L0000\narc: C5 W1_H02E0401\narc: C6 V02N0001\narc: C7 E1_H01E0101\narc: D1 V02N0201\narc: D3 N1_V02S0001\narc: D5 V02N0601\narc: D6 H02W0201\narc: D7 H02W0001\narc: E1_H01E0001 F7\narc: E1_H01E0101 F1\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: V01S0000 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0000110010101100\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R4C47:PLC2\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 V02N0701\narc: H00L0000 S1_V02N0201\narc: H00R0000 V02N0601\narc: H00R0100 V02N0701\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 V01N0101\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 V02N0001\narc: V00B0100 E1_H02W0701\narc: V00T0000 H02E0001\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V02N0401\narc: W3_H06W0103 E3_H06W0003\narc: A0 H00L0100\narc: A4 W1_H02E0501\narc: A5 V00B0000\narc: A6 F7\narc: B0 V02N0301\narc: B1 H01W0100\narc: B4 V02N0501\narc: B5 V02S0501\narc: B6 S1_V02N0501\narc: B7 V01S0000\narc: C0 H00L0000\narc: C1 H00R0100\narc: C4 V00T0000\narc: C5 V02N0201\narc: C6 V00B0100\narc: C7 V01N0101\narc: CE1 V02S0201\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 H00R0000\narc: D3 V00T0100\narc: D4 V02S0601\narc: D5 F0\narc: D6 S1_V02N0601\narc: D7 V02N0601\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: E3_H06E0103 F1\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0000 F7\narc: H01W0100 Q3\narc: LSR0 E1_H02W0301\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F5\narc: N1_V01N0101 F6\narc: S1_V02S0301 Q3\narc: S1_V02S0501 F7\narc: S3_V06S0103 F1\narc: S3_V06S0203 F7\narc: V00T0100 Q3\narc: V01S0000 Q3\narc: V01S0100 F1\narc: W1_H02W0101 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 0001001101011111\nword: SLICED.K1.INIT 0000001100000000\nword: SLICEA.K0.INIT 0001001101011111\nword: SLICEA.K1.INIT 0011000000000000\nword: SLICEC.K0.INIT 0000110010101100\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R4C48:PLC2\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0203 H01E0001\narc: H00R0000 E1_H02W0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0201 E1_H02W0201\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 H02E0701\narc: S3_V06S0203 H06W0203\narc: V00B0000 H02E0601\narc: V00B0100 V02S0301\narc: V00T0000 H02W0201\narc: V00T0100 H02W0101\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 H01E0101\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0201 W3_H06E0103\narc: H01W0000 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: CE0 H00R0100\narc: CE1 W1_H02E0101\narc: CE2 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: LSR0 E1_H02W0301\narc: LSR1 V00B0000\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: S3_V06S0003 Q0\narc: S3_V06S0103 Q2\narc: V01S0000 Q4\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R4C49:PLC2\narc: E1_H02E0301 W1_H02E0201\narc: H00R0000 E1_H02W0601\narc: N1_V02N0201 H02W0201\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H02W0601\narc: S3_V06S0203 E1_H01W0000\narc: V00B0100 H02W0501\narc: V00T0000 H02E0201\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 V02N0701\narc: CE0 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: LSR0 V00T0000\narc: LSR1 W1_H02E0501\narc: M0 H02E0601\narc: M4 W1_H02E0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: S1_V02S0001 Q0\narc: S3_V06S0303 Q6\narc: V01S0100 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R4C4:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 E3_H06W0303\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0701 S3_V06N0203\narc: V00B0100 W1_H02E0701\narc: V00T0000 E1_H02W0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 S3_V06N0303\narc: A7 H00L0000\narc: B7 V00B0000\narc: C7 V00T0000\narc: CE0 H02W0101\narc: CE1 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D7 H00R0100\narc: E1_H01E0001 F7\narc: E1_H02E0201 Q0\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0000 Q2\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00B0100\narc: M2 H02W0601\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: V00B0000 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R4C50:PLC2\narc: E1_H02E0201 W1_H02E0201\narc: H00L0100 E1_H02W0301\narc: H00R0000 E1_H02W0601\narc: N1_V02N0201 E1_H02W0201\narc: S1_V02S0101 H06E0103\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 H06E0103\narc: V00B0000 N1_V02S0001\narc: V00T0000 E1_H02W0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 E1_H02W0701\narc: E3_H06E0203 W3_H06E0103\narc: CE0 H00R0000\narc: CE1 E1_H02W0101\narc: CE2 H00R0000\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: H01W0000 Q0\narc: LSR0 W1_H02E0301\narc: LSR1 H02E0301\narc: M0 V00T0000\narc: M2 V00T0100\narc: M4 V00B0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: S1_V02S0401 Q4\narc: V01S0000 Q2\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R4C51:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: H00R0100 H02W0701\narc: S1_V02S0701 H06E0203\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 V02N0001\narc: V00B0100 V02S0101\narc: V00T0000 H02E0201\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0601 E1_H01W0000\narc: CE0 H02W0101\narc: CE2 H00R0100\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: H01W0000 Q6\narc: LSR0 E1_H02W0501\narc: LSR1 V00T0000\narc: M0 V00B0100\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: S3_V06S0003 Q0\narc: W3_H06W0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R4C52:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: V00T0100 H02E0101\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 S1_V02N0201\narc: E3_H06E0003 W3_H06E0303\narc: B1 V00B0000\narc: B3 H00R0000\narc: B4 H00R0000\narc: B5 H00R0000\narc: B7 V02N0701\narc: C0 H00R0100\narc: C1 V02N0401\narc: C3 V02N0401\narc: C4 V02N0201\narc: C5 V02N0201\narc: C6 Q6\narc: C7 V02S0001\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 F0\narc: D3 F0\narc: D4 F0\narc: D5 F0\narc: D6 V02N0401\narc: D7 V02N0601\narc: E1_H01E0001 Q7\narc: E1_H01E0101 F1\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q6\narc: H00R0100 Q7\narc: H01W0000 F4\narc: H01W0100 F3\narc: LSR1 E1_H02W0501\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V01N0101 F3\narc: S1_V02S0301 F3\narc: S1_V02S0401 Q6\narc: S1_V02S0601 F4\narc: S3_V06S0003 F3\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V00B0000 Q6\narc: V01S0000 F3\narc: V01S0100 Q7\narc: W1_H02W0101 F3\narc: W1_H02W0301 F1\narc: W1_H02W0601 F4\narc: W1_H02W0701 F5\narc: W3_H06W0103 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0011000000000000\nword: SLICEC.K0.INIT 0000110000000000\nword: SLICEC.K1.INIT 0000001100000000\nword: SLICED.K0.INIT 0000111111110000\nword: SLICED.K1.INIT 0011110011001100\nword: SLICEA.K0.INIT 0000111100000000\nword: SLICEA.K1.INIT 1100000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R4C53:PLC2\narc: E1_H02E0501 V02N0501\narc: S1_V02S0401 H01E0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0501 E1_H01W0100\narc: E1_H02E0201 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\n\n.tile R4C54:PLC2\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 H02E0201\narc: E1_H02E0701 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: S1_V02S0701 W3_H06E0203\narc: W1_H02W0501 W3_H06E0303\n\n.tile R4C55:PLC2\narc: E1_H02E0501 W1_H02E0501\narc: S1_V02S0401 V01N0001\n\n.tile R4C56:PLC2\narc: S1_V02S0101 H06E0103\narc: S1_V02S0501 H02E0501\narc: S1_V02S0701 W1_H02E0701\narc: E3_H06E0303 W3_H06E0203\n\n.tile R4C57:PLC2\narc: S1_V02S0401 S3_V06N0203\n\n.tile R4C58:PLC2\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\n\n.tile R4C59:PLC2\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0303 E3_H06W0203\n\n.tile R4C5:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0701 E3_H06W0203\narc: H00R0000 V02N0601\narc: N1_V02N0101 H02W0101\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0701 S3_V06N0203\narc: V00B0000 H02E0601\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02N0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 S3_V06N0203\narc: A5 V00T0000\narc: B1 V00T0000\narc: B3 N1_V02S0101\narc: B5 N1_V01S0000\narc: B7 V02S0701\narc: C1 S1_V02N0601\narc: C3 S1_V02N0401\narc: C5 V00B0100\narc: C7 V02N0001\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 H00R0000\narc: D2 H02E0201\narc: D3 H00R0000\narc: D5 V00B0000\narc: D6 E1_H02W0201\narc: D7 V02N0601\narc: E1_H02E0401 Q6\narc: E3_H06E0103 Q2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q0\narc: H01W0100 F5\narc: LSR0 H02E0501\narc: LSR1 H02E0301\narc: M0 V00T0100\narc: M2 V00T0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q6\narc: S1_V02S0601 Q6\narc: V01S0100 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1111111100000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R4C62:PLC2\narc: E3_H06E0303 W3_H06E0303\n\n.tile R4C64:PLC2\narc: E3_H06E0203 W3_H06E0103\n\n.tile R4C65:PLC2\narc: E3_H06E0003 W3_H06E0003\narc: W3_H06W0203 E3_H06W0203\n\n.tile R4C68:PLC2\narc: E1_H02E0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\n\n.tile R4C6:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 S1_V02N0401\narc: H00L0000 E1_H02W0001\narc: H00R0100 H02W0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 V01N0101\narc: V00B0100 E1_H02W0501\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0601 V02N0601\narc: W3_H06W0003 E1_H02W0001\narc: W3_H06W0103 E3_H06W0003\narc: A1 H00R0000\narc: A3 V00B0000\narc: B1 H02W0301\narc: B3 E1_H02W0101\narc: C1 H00R0100\narc: C3 N1_V01N0001\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D3 V00B0100\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: H00R0000 Q4\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M4 V00T0000\narc: M6 H02E0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V02N0101 F1\narc: V00B0000 Q6\narc: V01S0000 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R4C70:PLC2\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0701 W3_H06E0203\n\n.tile R4C7:PLC2\narc: H00L0000 N1_V02S0001\narc: H00L0100 V02S0101\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0301 H02W0301\narc: S1_V02S0701 W1_H02E0701\narc: V00B0000 V02N0201\narc: V00B0100 V02S0101\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02E0301\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 V01N0101\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 E3_H06W0303\narc: W3_H06W0003 E1_H02W0001\narc: W3_H06W0103 V06N0103\narc: W3_H06W0303 E1_H02W0501\narc: A1 H00R0000\narc: A3 V00T0000\narc: B1 V01N0001\narc: B3 V02N0301\narc: B5 H00L0000\narc: C1 E1_H02W0401\narc: C3 H00L0100\narc: C5 S1_V02N0201\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D3 H02E0001\narc: D4 E1_H02W0201\narc: D5 V02N0601\narc: E1_H01E0101 F3\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: H00R0000 Q6\narc: H01W0000 Q4\narc: H01W0100 F1\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q4\narc: W1_H02W0401 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1111111100000000\nword: SLICEC.K1.INIT 1111000011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R4C8:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: H00R0000 V02S0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 H06W0203\narc: S1_V02S0201 H06E0103\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0701 V01N0101\narc: V00B0100 H02W0701\narc: V00T0000 E1_H02W0201\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 H01E0101\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A5 V00B0000\narc: B3 H00L0000\narc: B5 V01S0000\narc: C3 S1_V02N0601\narc: C5 W1_H02E0401\narc: CE0 H00R0000\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D2 E1_H02W0001\narc: D3 V02N0001\narc: D5 H00R0100\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H00L0000 Q0\narc: H01W0000 Q6\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00T0100\narc: M2 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 F5\narc: V00B0000 Q6\narc: V01S0000 Q0\narc: V01S0100 Q2\narc: W1_H02W0201 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R4C9:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H02W0101\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 H02W0201\narc: V00T0100 H02W0301\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 E1_H02W0701\narc: E3_H06E0203 W3_H06E0103\narc: CE0 H00R0100\narc: CE1 H02W0101\narc: CE2 H00R0100\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q6\narc: E3_H06E0303 Q6\narc: H01W0100 Q4\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00B0000\narc: M2 V00B0000\narc: M4 V00T0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q0\narc: S3_V06S0303 Q6\narc: W1_H02W0201 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R5C10:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 V02N0501\narc: H00R0100 H02E0701\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0701 V01N0101\narc: S1_V02S0001 E1_H02W0001\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02N0201\narc: V00B0100 H02W0701\narc: V00T0000 H02W0001\narc: V00T0100 H02W0301\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: CE0 H02E0101\narc: CE1 H00R0100\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: E1_H02E0601 Q6\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q0\narc: S1_V02S0401 Q6\narc: S3_V06S0003 Q0\narc: V01S0100 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R5C11:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 H01E0101\narc: H00R0000 V02N0601\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 H02E0501\narc: S1_V02S0101 H01E0101\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0001\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02E0101\narc: W1_H02W0001 V02N0001\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 S1_V02N0701\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 W1_H02E0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: E1_H02E0401 Q6\narc: E3_H06E0003 Q0\narc: E3_H06E0203 Q4\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00T0000\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q6\narc: S1_V02S0001 Q0\narc: S1_V02S0601 Q6\narc: V01S0000 Q2\narc: V01S0100 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R5C12:PLC2\narc: E1_H02E0701 E3_H06W0203\narc: H00R0000 V02N0601\narc: N1_V02N0301 H02E0301\narc: N1_V02N0601 W1_H02E0601\narc: N1_V02N0701 H01E0101\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 H01E0101\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 H01E0101\narc: V00T0000 S1_V02N0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 S1_V02N0401\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q0\narc: E3_H06E0103 Q2\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 H01E0001\narc: M2 H02W0601\narc: M4 E1_H02W0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q2\narc: S1_V02S0001 Q0\narc: S1_V02S0201 Q2\narc: S1_V02S0601 Q4\narc: S3_V06S0003 Q0\narc: V01S0000 Q4\narc: V01S0100 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R5C13:PLC2\narc: E1_H02E0201 W1_H02E0201\narc: N1_V02N0001 H01E0001\narc: N1_V02N0301 H01E0101\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 H06E0303\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 H06E0103\narc: S3_V06S0203 H06E0203\narc: V00B0000 V02N0001\narc: V00T0100 W1_H02E0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0601 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: F5 F5_SLICE\narc: LSR1 V00B0100\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q6\narc: V00B0100 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R5C14:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: H00R0100 W1_H02E0701\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 H06E0003\narc: S3_V06S0203 H06E0203\narc: V00B0100 W1_H02E0701\narc: V00T0100 H02W0301\narc: W1_H02W0401 S1_V02N0401\narc: B3 V02N0301\narc: B5 V00B0100\narc: C3 H00R0100\narc: C5 V00T0100\narc: C7 V02N0001\narc: CLK0 G_HPBX0000\narc: D3 S1_V02N0201\narc: D5 S1_V02N0601\narc: D7 V02S0401\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q7\narc: S1_V02S0301 Q3\narc: S1_V02S0701 Q5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111110000001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000110000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111100001111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R5C15:PLC2\narc: E1_H02E0601 V01N0001\narc: E1_H02E0701 V01N0101\narc: H00L0000 E1_H02W0001\narc: H00R0100 N1_V02S0501\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0701 H06W0203\narc: S3_V06S0103 H06E0103\narc: V00T0000 H02W0001\narc: V00T0100 V02S0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 S1_V02N0301\narc: H01W0000 W3_H06E0103\narc: S1_V02S0301 W3_H06E0003\narc: W1_H02W0201 W3_H06E0103\narc: A5 V02N0301\narc: B2 V02N0301\narc: B5 V00B0100\narc: C2 H02W0401\narc: C3 H00L0100\narc: C5 H02W0601\narc: CE0 H00R0100\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D2 Q2\narc: D3 H00R0000\narc: D4 V00B0000\narc: D5 V02S0601\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q0\narc: E1_H02E0001 Q2\narc: E1_H02E0101 Q3\narc: E1_H02E0401 Q4\narc: E1_H02E0501 Q5\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0100 Q3\narc: H00R0000 Q4\narc: H01W0100 Q6\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 E1_H02W0601\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q5\narc: S1_V02S0101 Q3\narc: S1_V02S0601 Q4\narc: S3_V06S0303 Q6\narc: V00B0000 Q4\narc: V00B0100 Q5\narc: V01S0000 Q0\narc: V01S0100 Q3\narc: W1_H02W0001 Q0\narc: W1_H02W0601 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0011111111000000\nword: SLICEB.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 0110110011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\n\n.tile R5C16:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: H00L0000 S1_V02N0001\narc: H00R0100 E1_H02W0501\narc: N1_V02N0701 H01E0101\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 H02W0201\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02E0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 V02N0001\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 H01E0001\narc: H01W0000 W3_H06E0103\narc: W3_H06W0203 E3_H06W0203\narc: A0 V02N0701\narc: A1 V02N0501\narc: A2 V02N0701\narc: A3 V02N0501\narc: A4 H02E0501\narc: A5 V00T0100\narc: B0 V02N0101\narc: B1 V01N0001\narc: B2 V01N0001\narc: B3 V02N0301\narc: B4 H02E0101\narc: B5 H00L0000\narc: C0 S1_V02N0401\narc: C1 S1_V02N0401\narc: C2 S1_V02N0601\narc: C3 S1_V02N0601\narc: C4 V00T0000\narc: C5 W1_H02E0401\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CLK1 G_HPBX0000\narc: D0 V00B0100\narc: D1 V00B0100\narc: D2 V00B0100\narc: D3 V00B0100\narc: D4 V00B0000\narc: D5 V02S0601\narc: E1_H01E0001 Q1\narc: E1_H01E0101 Q2\narc: E1_H02E0001 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR1 E1_H02W0301\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: V01S0000 Q3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R5C17:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 E1_H01W0100\narc: H00L0000 H02E0001\narc: H00L0100 V02N0301\narc: H00R0000 H02W0601\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0401 H06W0203\narc: S1_V02S0701 E3_H06W0203\narc: V00B0000 H02W0601\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0103 S3_V06N0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: B0 H02W0101\narc: B1 V00T0000\narc: B2 V02N0101\narc: B3 V02S0301\narc: B5 H02E0101\narc: B6 H01E0101\narc: B7 V01S0000\narc: C0 H00L0000\narc: C1 W1_H02E0601\narc: C2 H00R0100\narc: C3 H00L0100\narc: C5 V02N0001\narc: C6 V02N0201\narc: C7 H01E0001\narc: CE0 V02S0201\narc: CE1 V02S0201\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D5 V00B0000\narc: D6 V00B0000\narc: D7 V00B0000\narc: E1_H01E0101 Q7\narc: E1_H02E0701 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q3\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: V00T0000 Q0\narc: V01S0000 Q6\narc: V01S0100 Q1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 1111000011001100\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R5C18:PLC2\narc: E1_H02E0501 V02S0501\narc: H00L0000 V02N0001\narc: H00L0100 N1_V02S0101\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 N1_V01S0000\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 V02N0201\narc: V00B0100 H02W0701\narc: V00T0000 E1_H02W0001\narc: V00T0100 N1_V02S0701\narc: W1_H02W0101 H01E0101\narc: A7 Q7\narc: B3 V02N0101\narc: B4 H02E0101\narc: B5 V01S0000\narc: B7 N1_V02S0501\narc: C2 V02N0601\narc: C3 H00L0000\narc: C4 Q4\narc: C5 V00T0000\narc: C6 V02S0001\narc: C7 V02S0001\narc: CE2 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 S1_V02N0201\narc: D4 H02E0001\narc: D5 N1_V02S0601\narc: D6 H02W0201\narc: D7 H00L0100\narc: E1_H01E0001 F7\narc: E1_H01E0101 F3\narc: E1_H02E0001 Q2\narc: E1_H02E0201 F2\narc: E1_H02E0401 F4\narc: E1_H02E0701 Q7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H00R0100 F5\narc: H01W0000 F3\narc: H01W0100 Q7\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F4\narc: N1_V01N0101 Q0\narc: N1_V02N0401 F4\narc: S1_V02S0601 Q4\narc: V01S0000 F4\narc: V01S0100 F2\narc: W1_H02W0301 F3\narc: W1_H02W0501 F7\narc: W1_H02W0601 F4\narc: W3_H06W0203 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0011000000000000\nword: SLICEC.K0.INIT 0000000000001100\nword: SLICEC.K1.INIT 1111110011001100\nword: SLICED.K0.INIT 1111111111110000\nword: SLICED.K1.INIT 1100010011110101\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R5C19:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V02N0401\narc: H00L0000 N1_V02S0001\narc: H00L0100 V02S0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02W0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 W1_H02E0701\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02E0701\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02S0501\narc: W1_H02W0201 H01E0001\narc: W1_H02W0501 V06S0303\narc: W1_H02W0701 V06S0203\narc: A0 H00L0100\narc: A1 H00L0100\narc: A2 H00L0100\narc: A3 H00L0100\narc: A4 H02E0501\narc: A5 N1_V01S0100\narc: A6 N1_V02S0101\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 V02S0701\narc: B5 H00L0000\narc: B6 V02S0501\narc: B7 N1_V02S0701\narc: C0 E1_H01W0000\narc: C1 E1_H01W0000\narc: C2 E1_H01W0000\narc: C3 E1_H01W0000\narc: C4 H02W0401\narc: C5 V02S0001\narc: C6 V00T0000\narc: C7 V00T0100\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CLK1 G_HPBX0000\narc: D0 N1_V01S0000\narc: D1 N1_V01S0000\narc: D2 N1_V01S0000\narc: D3 N1_V01S0000\narc: D4 V02S0601\narc: D5 H02W0201\narc: D6 V00B0000\narc: D7 E1_H02W0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q3\narc: LSR1 H02W0501\narc: M6 V00B0100\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: S1_V02S0101 Q1\narc: S3_V06S0003 Q0\narc: S3_V06S0103 Q2\narc: V01S0100 F6\nword: SLICED.K0.INIT 0000000001111111\nword: SLICED.K1.INIT 0011111111111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R5C20:PLC2\narc: E1_H02E0601 V01N0001\narc: H00L0000 W1_H02E0001\narc: H00R0000 N1_V02S0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0601 H02W0601\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0303 H06W0303\narc: V00B0000 H02E0401\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 E1_H02W0501\narc: W3_H06W0203 E1_H02W0401\narc: A1 V02N0701\narc: A2 E1_H01E0001\narc: A4 V00T0100\narc: B1 V00T0000\narc: B2 V02S0301\narc: B4 V01S0000\narc: B5 H02E0301\narc: B6 V00B0100\narc: C0 H00L0000\narc: C1 V02N0601\narc: C2 V02N0401\narc: C3 H00L0100\narc: C4 Q4\narc: C5 V02N0201\narc: C6 Q6\narc: C7 V00B0100\narc: CE0 H02W0101\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0201\narc: D1 H00R0000\narc: D2 V02N0001\narc: D3 E1_H02W0001\narc: D4 E1_H01W0100\narc: D5 E1_H01W0100\narc: D6 H02E0201\narc: D7 H02E0201\narc: E1_H01E0001 Q3\narc: E1_H01E0101 F1\narc: E1_H02E0201 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: H01W0000 Q6\narc: H01W0100 Q3\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q7\narc: N1_V01N0101 Q4\narc: N1_V02N0401 Q6\narc: S1_V02S0301 Q3\narc: S1_V02S0501 Q5\narc: V00B0100 Q7\narc: V00T0000 F0\narc: V00T0100 Q3\narc: V01S0000 Q5\narc: V01S0100 F2\narc: W1_H02W0701 Q7\nword: SLICED.K0.INIT 0011110011110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 0111100000000000\nword: SLICEC.K1.INIT 0011110000000000\nword: SLICEB.K0.INIT 1111010100110001\nword: SLICEB.K1.INIT 0000111100000000\nword: SLICEA.K0.INIT 0000000011110000\nword: SLICEA.K1.INIT 1110110011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\n\n.tile R5C21:PLC2\narc: H00R0000 V02N0601\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 E1_H02W0301\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 V02S0401\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 S1_V02N0401\narc: A6 N1_V01N0101\narc: B0 E1_H02W0101\narc: B5 W1_H02E0101\narc: B6 H02W0301\narc: C0 H02E0601\narc: C1 H00L0000\narc: C5 V00T0100\narc: C6 V00B0100\narc: C7 V02S0001\narc: CE1 V02S0201\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V01S0100\narc: D5 V00B0000\narc: D6 F0\narc: D7 V02N0401\narc: E1_H01E0001 F5\narc: E1_H01E0101 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H00L0100 F1\narc: H01W0000 F7\narc: H01W0100 F5\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M2 H02W0601\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q6\narc: N1_V02N0701 F7\narc: S1_V02S0001 F0\narc: S1_V02S0401 Q6\narc: V01S0000 F6\narc: V01S0100 F6\narc: W1_H02W0601 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000110000000000\nword: SLICEA.K0.INIT 1100000000000000\nword: SLICEA.K1.INIT 1111111111110000\nword: SLICED.K0.INIT 1100111101000101\nword: SLICED.K1.INIT 0000111111110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R5C22:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V02N0501\narc: H00R0000 S1_V02N0601\narc: S1_V02S0101 H02W0101\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 H02W0601\narc: V00B0100 E1_H02W0701\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02S0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 N1_V01S0000\narc: W3_H06W0203 E3_H06W0203\narc: B7 V00T0000\narc: C7 V00B0100\narc: CE0 H00R0000\narc: CE2 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: F7 F7_SLICE\narc: M0 V00T0100\narc: M4 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: S1_V02S0401 Q4\narc: S3_V06S0003 Q0\narc: V01S0100 Q0\narc: W1_H02W0401 Q4\narc: W1_H02W0701 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0011110000110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R5C23:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 V02S0301\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 V06N0203\narc: H00L0000 N1_V02S0001\narc: H00R0100 H02W0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 H02E0401\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 E1_H01W0000\narc: V00B0100 H02W0501\narc: V00T0000 V02S0401\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E1_H02W0301\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0303 E3_H06W0303\narc: A3 V00B0000\narc: A7 E1_H02W0701\narc: B3 N1_V02S0101\narc: B7 V02S0701\narc: C3 V02N0601\narc: C7 V02N0201\narc: CE0 H00L0000\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: D7 H00R0100\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: M0 H02W0601\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q0\narc: S1_V02S0201 Q0\narc: V00B0000 Q4\narc: V01S0100 Q4\narc: W3_H06W0203 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R5C24:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0103 W1_H02E0201\narc: H00L0000 V02N0001\narc: H00R0000 N1_V02S0601\narc: H00R0100 V02N0501\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H02E0701\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 W1_H02E0401\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 H02W0601\narc: V00B0100 V02S0101\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 E1_H01W0100\narc: A1 E1_H01E0001\narc: A3 V00T0000\narc: B1 H02E0301\narc: B3 H00R0000\narc: C1 V02N0601\narc: C3 H00R0100\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D3 V02N0201\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q4\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: H01W0000 F1\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: S3_V06S0003 F3\narc: W1_H02W0401 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R5C25:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V06S0303\narc: E1_H02E0701 E1_H01W0100\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0201 E1_H01W0000\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 S1_V02N0201\narc: V00T0000 H02W0201\narc: V00T0100 N1_V02S0501\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 H01E0101\narc: A3 V00T0000\narc: B2 F1\narc: B3 E1_H02W0101\narc: C1 H02E0601\narc: C2 H00L0100\narc: C3 E1_H02W0601\narc: CE0 H00L0000\narc: CE2 H02E0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 Q0\narc: D1 V01S0100\narc: D2 V02N0001\narc: D3 V00T0100\narc: E1_H02E0101 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H00L0000 F2\narc: H00L0100 F3\narc: H01W0000 Q1\narc: H01W0100 Q0\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M4 V00B0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q1\narc: N1_V01N0101 Q4\narc: N1_V02N0401 Q6\narc: N3_V06N0303 Q6\narc: S1_V02S0001 Q0\narc: S1_V02S0101 Q1\narc: S1_V02S0301 F3\narc: S1_V02S0401 Q6\narc: S1_V02S0601 Q4\narc: S3_V06S0003 F3\narc: V01S0000 Q1\narc: V01S0100 Q0\narc: W1_H02W0201 Q0\narc: W1_H02W0301 F3\narc: W3_H06W0103 Q1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111001100000000\nword: SLICEB.K1.INIT 1001000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000111111110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R5C26:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 V06S0303\narc: E3_H06E0203 W1_H02E0401\narc: H00L0100 H02E0101\narc: H00R0100 N1_V02S0501\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 V01N0001\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V06N0203\narc: A1 H00L0000\narc: A3 V02S0701\narc: A5 V00T0000\narc: B1 V00B0000\narc: B3 H00R0100\narc: B5 H00R0000\narc: C0 N1_V02S0401\narc: C1 V02N0601\narc: C2 E1_H02W0401\narc: C3 H02E0401\narc: C4 V02S0001\narc: C5 V02S0201\narc: C6 H02W0401\narc: C7 E1_H01E0101\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 N1_V02S0001\narc: D2 V00B0100\narc: D3 V02N0001\narc: D4 V02N0401\narc: D5 H02E0201\narc: D6 V02N0401\narc: D7 H00L0100\narc: E1_H01E0001 F7\narc: E1_H01E0101 F3\narc: E1_H02E0001 Q0\narc: E1_H02E0501 F7\narc: E1_H02E0701 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00R0000 Q4\narc: H01W0000 F3\narc: H01W0100 Q6\narc: LSR0 H02E0301\narc: LSR1 W1_H02E0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q2\narc: V00B0000 Q4\narc: V00B0100 F7\narc: V00T0000 Q0\narc: V01S0000 F7\narc: V01S0100 F1\narc: W1_H02W0201 Q2\narc: W3_H06W0003 F3\nword: SLICEB.K0.INIT 0000000011110000\nword: SLICEB.K1.INIT 0110111111111111\nword: SLICEC.K0.INIT 0000000011110000\nword: SLICEC.K1.INIT 1000001001000001\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0000000011110000\nword: SLICEA.K1.INIT 1000010000100001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\n\n.tile R5C27:PLC2\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 S1_V02N0301\narc: E3_H06E0303 W1_H02E0501\narc: H00L0100 V02S0301\narc: H00R0000 H02E0601\narc: H00R0100 V02S0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0501 H02E0501\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0601 H02W0601\narc: S3_V06S0303 H01E0101\narc: V00B0100 H02E0501\narc: W1_H02W0101 V06S0103\narc: W1_H02W0401 N1_V01S0000\narc: A1 E1_H01E0001\narc: A3 V00T0000\narc: A6 H02E0701\narc: B1 H01W0100\narc: B3 H00L0000\narc: B5 V01S0000\narc: B6 N1_V02S0501\narc: B7 V00B0000\narc: C0 H00L0100\narc: C1 W1_H02E0601\narc: C2 N1_V01S0100\narc: C3 N1_V02S0601\narc: C4 V02S0201\narc: C5 N1_V02S0201\narc: C6 E1_H01E0101\narc: C7 V02S0001\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 H00R0000\narc: D2 V00B0100\narc: D3 N1_V02S0001\narc: D4 V02N0601\narc: D5 H00R0100\narc: D6 H01W0000\narc: D7 V02S0601\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H01W0000 F7\narc: H01W0100 Q0\narc: LSR0 E1_H02W0301\narc: LSR1 H02W0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q4\narc: N1_V02N0201 Q2\narc: S1_V02S0101 F3\narc: V00B0000 Q4\narc: V00T0000 Q2\narc: V01S0000 Q4\narc: W1_H02W0601 F6\nword: SLICEC.K0.INIT 0000000011110000\nword: SLICEC.K1.INIT 1100001100000000\nword: SLICEA.K0.INIT 0000000011110000\nword: SLICEA.K1.INIT 1000010000100001\nword: SLICEB.K0.INIT 0000000011110000\nword: SLICEB.K1.INIT 1000010000100001\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 1100001100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R5C28:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0501 W1_H02E0401\narc: N3_V06N0003 S1_V02N0001\narc: S1_V02S0101 V01N0101\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V06S0303\narc: W3_H06W0203 E3_H06W0103\narc: B1 S1_V02N0101\narc: C0 H00L0100\narc: C1 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 S1_V02N0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: H00L0100 F1\narc: LSR0 H02E0301\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V01S0000 Q1\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 1111111111110000\nword: SLICEA.K1.INIT 0000001100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R5C29:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V06S0203\narc: H00R0000 V02N0601\narc: H00R0100 H02E0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0501 V01N0101\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0501 E1_H02W0501\narc: V00B0000 V02S0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02N0401\narc: W1_H02W0301 V02N0301\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0303 E3_H06W0303\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: M0 V00T0000\narc: M2 N1_V01N0001\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0201 Q0\narc: S1_V02S0601 Q4\narc: V01S0000 Q6\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R5C2:PLC2\narc: E1_H02E0601 E3_H06W0303\narc: H00L0100 S1_V02N0301\narc: H01W0100 E3_H06W0303\narc: N1_V02N0201 H06W0103\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0303 S1_V02N0501\narc: V00B0100 E1_H02W0701\narc: V00T0000 H02W0001\narc: V00T0100 S1_V02N0501\narc: CE0 H02E0101\narc: CE1 H00L0100\narc: CE2 H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q6\narc: E1_H02E0201 Q0\narc: H01W0000 Q4\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q0\narc: V01S0000 Q2\narc: V01S0100 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R5C30:PLC2\narc: E3_H06E0103 W1_H02E0201\narc: H00L0100 V02N0301\narc: H00R0000 E1_H02W0401\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0401 H02E0401\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02W0501\narc: V00T0100 H02W0301\narc: E1_H02E0101 W3_H06E0103\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: M2 V00T0100\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: S3_V06S0303 Q6\narc: V01S0000 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R5C31:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V02N0201\narc: H00L0000 W1_H02E0201\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 H06W0003\narc: N1_V02N0301 H02W0301\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0501 S3_V06N0303\narc: V00B0000 V02S0001\narc: V01S0000 S3_V06N0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: CE0 H00L0000\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q0\narc: E3_H06E0103 Q2\narc: M0 V00B0000\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R5C32:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 S1_V02N0201\narc: H00R0000 H02W0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0401 S1_V02N0401\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0501 V01N0101\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02S0401\narc: V00T0100 V02N0501\narc: W1_H02W0301 V06N0003\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0401 W3_H06E0203\narc: A1 H02W0501\narc: A6 N1_V01N0101\narc: A7 H00L0000\narc: B1 H01W0100\narc: B6 H02E0101\narc: B7 V02N0701\narc: C1 S1_V02N0601\narc: C6 V00T0100\narc: C7 V02N0201\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V02S0201\narc: D6 E1_H02W0201\narc: D7 H00R0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 F6\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: M0 V00B0100\narc: M1 H02E0001\narc: M2 V00B0100\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: N1_V02N0301 F1\narc: V01S0000 F1\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1100111101000101\nword: SLICED.K1.INIT 1100111101000101\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R5C33:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: H00L0100 H02W0101\narc: H00R0000 E1_H02W0601\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 S3_V06N0303\narc: V00T0000 H02E0201\narc: V00T0100 V02N0501\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E1_H02W0601\narc: E3_H06E0003 W3_H06E0303\narc: A1 H01E0001\narc: A2 H01E0001\narc: A3 H01E0001\narc: B1 N1_V02S0101\narc: B2 N1_V02S0101\narc: B3 N1_V02S0101\narc: C1 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: CE2 V02N0601\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0201\narc: D2 W1_H02E0201\narc: D3 W1_H02E0201\narc: E1_H01E0001 F1\narc: E1_H02E0401 Q4\narc: E1_H02E0601 Q6\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 Q4\narc: M0 V00T0000\narc: M1 H02W0001\narc: M2 V00T0000\narc: M4 H02W0401\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0103 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1101000011011101\nword: SLICEB.K0.INIT 1101000011011101\nword: SLICEB.K1.INIT 1101000011011101\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R5C34:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0203 W1_H02E0401\narc: H00L0100 E1_H02W0101\narc: H00R0000 H02W0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0601 H02W0601\narc: N3_V06N0003 S1_V02N0301\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 N1_V02S0401\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 H01E0001\narc: V00B0000 H02E0401\narc: V00B0100 V02N0101\narc: V00T0000 S1_V02N0601\narc: V00T0100 H02E0101\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 V06N0203\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0103 E3_H06W0103\narc: A0 W1_H02E0701\narc: A2 V00B0000\narc: A3 W1_H02E0701\narc: B0 W1_H02E0101\narc: B2 W1_H02E0101\narc: B3 W1_H02E0101\narc: C0 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: CE2 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D2 V02S0001\narc: D3 V02S0001\narc: E1_H01E0001 Q4\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 V00B0100\narc: M1 E1_H02W0001\narc: M2 V00B0100\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: V01S0000 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0001001101011111\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0001001101011111\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R5C35:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V02N0701\narc: E3_H06E0203 V06N0203\narc: H00L0000 V02N0201\narc: H00R0000 H02W0601\narc: H00R0100 V02N0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 N1_V02S0101\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02E0701\narc: V00T0100 V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A0 H01E0001\narc: A2 H01E0001\narc: A3 H01E0001\narc: B0 V02N0101\narc: B2 V02N0101\narc: B3 V02N0101\narc: B4 H00R0000\narc: B5 H02E0301\narc: C0 N1_V01S0100\narc: C2 N1_V01S0100\narc: C3 N1_V01S0100\narc: C4 V00T0100\narc: C5 F4\narc: C7 V00B0100\narc: CE2 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D2 H02E0001\narc: D3 H02E0001\narc: D4 E1_H01W0100\narc: D5 H00L0100\narc: D7 H00R0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0100 F7\narc: LSR1 V00B0000\narc: M0 W1_H02E0601\narc: M1 H00L0000\narc: M2 W1_H02E0601\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: S3_V06S0303 Q5\narc: V01S0100 F4\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001111\nword: SLICEC.K0.INIT 0011000011110000\nword: SLICEC.K1.INIT 0000001100110011\nword: SLICEA.K0.INIT 0001001101011111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0001001101011111\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R5C36:PLC2\narc: E1_H02E0501 V02N0501\narc: H00L0000 W1_H02E0201\narc: H00L0100 E1_H02W0101\narc: H00R0000 H02W0601\narc: H00R0100 V02N0501\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0001 H01E0001\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 H01E0101\narc: S1_V02S0501 S3_V06N0303\narc: V00B0100 V02S0301\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02E0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0301 E1_H02W0201\narc: W3_H06W0203 V06N0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A1 H02W0501\narc: A2 V00T0000\narc: A3 V00T0000\narc: B1 V02N0301\narc: B2 V02N0301\narc: B3 V02N0301\narc: B5 V02S0501\narc: C1 H00L0000\narc: C2 H00L0000\narc: C3 H00L0000\narc: C4 V02S0201\narc: C5 V00B0100\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 H00R0100\narc: D5 H02E0001\narc: E1_H01E0001 F5\narc: E1_H01E0101 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 F1\narc: M0 V00T0100\narc: M1 H00L0100\narc: M2 V00T0100\narc: M6 H02W0401\narc: MUXCLK3 CLK0\narc: N1_V01N0101 F4\narc: S1_V02S0601 F4\narc: S1_V02S0701 F5\narc: S3_V06S0103 F1\narc: W1_H02W0101 F1\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000001111\nword: SLICEC.K1.INIT 0000000000000011\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0000010000000000\nword: SLICEB.K0.INIT 0000010000000000\nword: SLICEB.K1.INIT 0000010000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R5C37:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V06S0103\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0003 W1_H02E0301\narc: E3_H06E0303 W1_H02E0601\narc: H00L0100 N1_V02S0101\narc: H00R0000 S1_V02N0601\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 H01E0101\narc: S1_V02S0701 S3_V06N0203\narc: V00T0000 H02W0201\narc: V00T0100 H02W0101\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 V02N0601\narc: H01W0000 W3_H06E0103\narc: A0 H00L0100\narc: B0 V02N0301\narc: C0 V02N0401\narc: D0 V00T0100\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 E1_H02W0001\narc: M2 V00T0000\narc: M3 H00R0000\narc: M4 V00T0000\narc: M5 E1_H02W0001\narc: M6 V00T0000\narc: V01S0000 F3\nword: SLICEA.K0.INIT 1010001011110011\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R5C38:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: H00L0000 V02N0201\narc: H00R0000 S1_V02N0401\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0701 H06E0203\narc: S1_V02S0301 E1_H02W0301\narc: V00B0000 V02N0201\narc: V00T0000 N1_V02S0401\narc: W1_H02W0201 V06S0103\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0201 W3_H06E0103\narc: H01W0000 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: A1 H00L0000\narc: A2 V00B0000\narc: A3 V00B0000\narc: B1 H02W0301\narc: B2 H02W0301\narc: B3 H02W0301\narc: C1 H02E0601\narc: C2 H02E0601\narc: C3 H02E0601\narc: D1 H02E0201\narc: D2 H02E0201\narc: D3 H02E0201\narc: E1_H01E0101 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 H02E0001\narc: M2 V00T0000\narc: M3 H00R0000\narc: M4 V00T0000\narc: M5 H02E0001\narc: M6 V00T0000\narc: S3_V06S0003 F3\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 0000000001000000\nword: SLICEB.K0.INIT 0000000001000000\nword: SLICEB.K1.INIT 0000000001000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R5C39:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 V02N0001\narc: H00L0100 H02E0101\narc: H00R0000 N1_V02S0401\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S3_V06N0103\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 E1_H01W0000\narc: V00B0000 W1_H02E0601\narc: V00B0100 V02S0101\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 V02N0301\narc: S1_V02S0201 W3_H06E0103\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: A0 H00R0000\narc: B0 V00B0000\narc: C0 H00L0100\narc: D0 H02W0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00L0000\narc: M2 V00B0100\narc: M3 E1_H02W0201\narc: M4 V00B0100\narc: M5 H00L0000\narc: M6 V00B0100\narc: S1_V02S0101 F3\nword: SLICEA.K0.INIT 1010111100100011\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R5C3:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 H01E0001\narc: E1_H02E0401 V02S0401\narc: H00R0000 H02W0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0101 V01N0101\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02S0401\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 V02N0101\narc: A7 H00L0000\narc: B3 H00L0000\narc: B7 V00B0000\narc: C3 V02N0601\narc: C7 S1_V02N0001\narc: CE0 H00R0000\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 W1_H02E0001\narc: D3 V00T0100\narc: D7 V02S0601\narc: E3_H06E0103 Q2\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 H02W0601\narc: M2 V00T0000\narc: M4 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: S1_V02S0601 Q4\narc: V00B0000 Q4\narc: V01S0000 F7\narc: W1_H02W0001 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R5C40:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0601 V02N0601\narc: H00L0100 E1_H02W0101\narc: H00R0100 H02E0701\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 H06W0303\narc: S1_V02S0201 W1_H02E0201\narc: V00T0000 H02E0001\narc: W1_H02W0201 V06S0103\narc: S1_V02S0101 W3_H06E0103\narc: S3_V06S0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: A0 E1_H02W0501\narc: A1 E1_H02W0501\narc: B0 V02S0301\narc: B1 V02S0301\narc: C0 H00L0100\narc: C1 H00L0100\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 V02S0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 F1\narc: LSR1 H02E0301\narc: M0 V00T0000\narc: M1 W1_H02E0001\narc: M2 V00T0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: W1_H02W0301 F1\narc: W3_H06W0103 Q1\nword: SLICEA.K0.INIT 1111111111111110\nword: SLICEA.K1.INIT 1111111111111110\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R5C41:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V02N0201\narc: H00R0100 E1_H02W0701\narc: N1_V02N0301 S3_V06N0003\narc: S1_V02S0401 H06E0203\narc: V00T0100 H02E0101\narc: W1_H02W0201 S1_V02N0201\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A0 V02S0701\narc: B0 V02S0301\narc: C0 H02E0601\narc: D0 H02E0201\narc: E1_H01E0101 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00R0100\narc: M2 V00T0100\narc: M3 E1_H02W0201\narc: M4 V00T0100\narc: M5 H00R0100\narc: M6 V00T0100\nword: SLICEA.K0.INIT 1000101011001111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R5C42:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 H02W0001\narc: H00L0100 W1_H02E0101\narc: H00R0000 V02N0601\narc: N1_V02N0301 H02W0301\narc: N1_V02N0601 H02W0601\narc: V00B0100 E1_H02W0701\narc: V00T0100 H02E0101\narc: W1_H02W0501 H01E0101\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: A0 N1_V02S0701\narc: B0 E1_H02W0101\narc: C0 H00L0100\narc: D0 V00B0100\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00R0000\narc: M2 V00T0100\narc: M3 H00L0000\narc: M4 V00T0100\narc: M5 W1_H02E0001\narc: M6 V00T0100\narc: W1_H02W0101 F3\nword: SLICEA.K0.INIT 1011000010111011\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R5C43:PLC2\narc: E1_H02E0101 V02N0101\narc: H00L0000 W1_H02E0201\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E1_H01W0000\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: V00B0000 V02S0201\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0701 E1_H02W0601\narc: H01W0100 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0303 S3_V06N0303\narc: E3_H06E0103 W3_H06E0003\narc: CE0 H00L0000\narc: CE1 H02E0101\narc: CLK0 G_HPBX0000\narc: M0 V00B0000\narc: M2 N1_V01N0001\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: W1_H02W0001 Q0\narc: W1_H02W0201 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R5C44:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0601 S1_V02N0601\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0401 E1_H02W0401\narc: S1_V02S0401 E1_H01W0000\narc: W1_H02W0701 E1_H01W0100\narc: H01W0000 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\n\n.tile R5C45:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 N1_V02S0701\narc: H00L0000 E1_H02W0001\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 H06W0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0701 S3_V06N0203\narc: V00T0000 H02W0201\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H02W0001\narc: E1_H01E0001 W3_H06E0003\narc: H01W0100 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: CE0 V02S0201\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: H01W0000 Q4\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: S3_V06S0003 Q0\narc: S3_V06S0103 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R5C46:PLC2\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 H02E0201\narc: H00L0100 V02N0101\narc: H00R0000 N1_V02S0401\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 H02W0601\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 W1_H02E0601\narc: V00B0000 E1_H02W0401\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 H01E0001\narc: W3_H06W0003 S3_V06N0003\narc: E3_H06E0303 W3_H06E0303\narc: A3 H02W0701\narc: A4 H02E0701\narc: A5 N1_V01N0101\narc: A6 H00R0000\narc: A7 E1_H01W0000\narc: B0 V02N0101\narc: B3 H02W0101\narc: B4 H02E0101\narc: B5 N1_V01S0000\narc: B6 V00B0000\narc: B7 E1_H02W0301\narc: C0 H00L0000\narc: C1 H00L0100\narc: C3 V02N0401\narc: C4 H01E0001\narc: C5 E1_H01E0101\narc: C6 V00T0000\narc: C7 S1_V02N0201\narc: D0 V02S0001\narc: D1 S1_V02N0201\narc: D3 V02S0001\narc: D4 H01W0000\narc: D5 V01N0001\narc: D6 N1_V02S0601\narc: D7 N1_V02S0601\narc: E1_H01E0101 F7\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: M0 H02E0601\narc: N1_V01N0101 F3\narc: N3_V06N0203 F4\narc: S3_V06S0303 F6\narc: V00T0000 F0\nword: SLICEC.K0.INIT 0000110010101100\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 1000101000001010\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000110000111111\nword: SLICEA.K1.INIT 1111000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R5C47:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 N1_V01S0100\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 S3_V06N0203\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02S0301\narc: H00R0000 V02S0601\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0301 H02W0301\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 S3_V06N0303\narc: V00B0000 E1_H02W0601\narc: V00B0100 E1_H02W0501\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 V01N0101\narc: W1_H02W0301 V06N0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 N1_V01S0100\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A0 E1_H01E0001\narc: A2 V02N0701\narc: B0 V02N0101\narc: B1 H00R0100\narc: B2 V01N0001\narc: B3 H00R0100\narc: B5 V01S0000\narc: B6 V00B0100\narc: C0 H02E0601\narc: C1 W1_H02E0401\narc: C2 H02E0401\narc: C3 W1_H02E0401\narc: C4 Q4\narc: C5 E1_H01E0101\narc: C6 V02N0201\narc: C7 V00B0100\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 N1_V01S0000\narc: D2 H00R0000\narc: D3 N1_V01S0000\narc: D4 H00L0100\narc: D5 H00L0100\narc: D6 V00B0000\narc: D7 V02S0401\narc: E1_H01E0001 F1\narc: E1_H01E0101 Q4\narc: E1_H02E0301 F3\narc: E3_H06E0003 F3\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00R0100 Q5\narc: H01W0000 F1\narc: H01W0100 F6\narc: LSR0 E1_H02W0301\narc: M6 E1_H02W0401\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q5\narc: N1_V02N0001 F0\narc: N1_V02N0201 F2\narc: N1_V02N0401 Q4\narc: N1_V02N0601 Q4\narc: N1_V02N0701 Q5\narc: S1_V02S0301 F1\narc: S1_V02S0401 Q4\narc: S1_V02S0701 Q5\narc: S3_V06S0003 F3\narc: S3_V06S0103 F1\narc: V01S0000 Q5\narc: V01S0100 F3\nword: SLICEB.K0.INIT 0001001101011111\nword: SLICEB.K1.INIT 0000000000000011\nword: SLICEA.K0.INIT 0001010100111111\nword: SLICEA.K1.INIT 0000110000000000\nword: SLICEC.K0.INIT 0000111111110000\nword: SLICEC.K1.INIT 0011110011001100\nword: SLICED.K0.INIT 0000001111001111\nword: SLICED.K1.INIT 1111000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R5C48:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V01N0001\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0303 V01N0101\narc: H00L0100 V02N0101\narc: H00R0000 V02S0401\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 V02S0001\narc: V00B0100 H02E0701\narc: V00T0000 V02N0601\narc: V00T0100 H02E0301\narc: W1_H02W0301 V01N0101\narc: W1_H02W0401 V01N0001\narc: W1_H02W0701 S1_V02N0701\narc: S1_V02S0401 W3_H06E0203\narc: W3_H06W0303 V06N0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: A4 V00T0100\narc: A5 W1_H02E0501\narc: A7 S1_V02N0301\narc: B0 V02N0101\narc: B2 V02N0301\narc: B4 V02N0501\narc: B5 E1_H02W0101\narc: B7 V02N0701\narc: C0 N1_V02S0601\narc: C1 H00L0100\narc: C2 H02E0601\narc: C3 H00L0100\narc: C4 S1_V02N0001\narc: C5 S1_V02N0001\narc: C7 V00B0100\narc: D0 S1_V02N0201\narc: D1 V02S0001\narc: D2 H00R0000\narc: D3 V00B0100\narc: D4 V02S0401\narc: D5 F0\narc: D7 V00B0000\narc: E1_H02E0001 F2\narc: E1_H02E0401 F4\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M0 V00T0000\narc: M2 V00T0000\narc: S3_V06S0303 F5\nword: SLICEC.K0.INIT 0001001101011111\nword: SLICEC.K1.INIT 1000000010101010\nword: SLICEA.K0.INIT 0000001111001111\nword: SLICEA.K1.INIT 1111000011111111\nword: SLICEB.K0.INIT 0000110000111111\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R5C49:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0701 V02N0701\narc: H00L0000 H02E0201\narc: H00L0100 H02W0301\narc: H00R0000 E1_H02W0401\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 H06W0103\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N1_V01S0100\narc: V00B0100 H02W0501\narc: V00T0000 E1_H02W0001\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0101 W3_H06E0103\narc: A1 W1_H02E0501\narc: A4 H02E0501\narc: A5 E1_H02W0701\narc: A6 H00R0000\narc: A7 V00T0100\narc: B1 W1_H02E0101\narc: B4 H00L0000\narc: B5 H02E0101\narc: B6 E1_H02W0101\narc: B7 V02S0501\narc: C1 V02N0601\narc: C4 H02W0601\narc: C5 V02N0001\narc: C6 V00T0000\narc: C7 H02E0401\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: D4 H02E0001\narc: D5 H02W0001\narc: D6 H01W0000\narc: D7 W1_H02E0001\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: LSR1 E1_H02W0501\narc: M2 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0101 F5\narc: S3_V06S0203 F4\narc: V00T0100 F1\narc: V01S0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1000000010101010\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000110010101100\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R5C4:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 V02S0701\narc: H00L0000 W1_H02E0201\narc: H00R0000 W1_H02E0601\narc: H00R0100 H02W0701\narc: V00B0100 V02N0301\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 E1_H02W0601\narc: A3 V00B0000\narc: B3 E1_H01W0100\narc: B5 H00L0000\narc: C3 S1_V02N0401\narc: C5 V02N0001\narc: CE0 H00R0000\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D3 V02N0201\narc: D4 H02E0201\narc: D5 H00R0100\narc: E1_H02E0201 Q0\narc: E3_H06E0203 Q4\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: H01W0000 Q0\narc: H01W0100 F3\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 V00T0100\narc: M4 H02E0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V02N0401 Q6\narc: N3_V06N0203 Q4\narc: V00B0000 Q6\narc: V01S0000 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 1111111100000000\nword: SLICEC.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R5C50:PLC2\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0303 W1_H02E0501\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02S0701\narc: N1_V02N0401 H06W0203\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 H06W0003\narc: S3_V06S0203 N1_V01S0000\narc: V00B0100 H02E0701\narc: V00T0000 V02N0401\narc: V00T0100 V02N0501\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 S3_V06N0303\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 E1_H02W0101\narc: CE3 V02S0601\narc: CLK0 G_HPBX0000\narc: H01W0100 Q6\narc: LSR0 V00T0000\narc: LSR1 H02W0301\narc: M0 H02W0601\narc: M2 V00T0100\narc: M4 H02E0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: S1_V02S0401 Q4\narc: S3_V06S0103 Q2\narc: V01S0100 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R5C51:PLC2\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: N1_V02N0001 V01N0001\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0701 H02E0701\narc: S3_V06S0103 E1_H01W0100\narc: V00B0000 V02N0201\narc: V00B0100 V02N0301\narc: V00T0000 H02W0001\narc: V00T0100 V02N0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V01N0001\narc: W1_H02W0701 V02S0701\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: CE0 E1_H02W0101\narc: CE1 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: LSR0 V00B0100\narc: LSR1 H02W0501\narc: M0 V00B0000\narc: M2 E1_H02W0601\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: S1_V02S0001 Q2\narc: S1_V02S0401 Q6\narc: S1_V02S0601 Q4\narc: V01S0100 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R5C52:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 E1_H01W0000\narc: H00L0100 V02S0301\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0601 N1_V01S0000\narc: V00T0000 H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0103 E1_H01W0100\narc: CE0 H00L0100\narc: CE1 H02W0101\narc: CE2 V02S0601\narc: CLK0 G_HPBX0000\narc: H01W0100 Q4\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 H02E0601\narc: M2 H02E0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: S1_V02S0201 Q2\narc: S3_V06S0003 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R5C53:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0501 W1_H02E0501\narc: H00L0000 H02W0001\narc: H00R0000 H02E0601\narc: S1_V02S0301 H02E0301\narc: S1_V02S0601 E3_H06W0303\narc: V00B0000 H02E0601\narc: V00B0100 V02N0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0601 V02N0601\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: S3_V06S0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0303 E3_H06W0303\narc: B1 V00B0000\narc: B3 H00R0000\narc: B4 V01S0000\narc: B5 V01S0000\narc: C0 V02S0401\narc: C1 H02E0401\narc: C3 H02E0401\narc: C4 H02E0401\narc: C5 H02E0401\narc: CE1 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 F0\narc: D2 Q2\narc: D3 F0\narc: D4 F0\narc: D5 F0\narc: E1_H01E0101 F3\narc: E1_H02E0101 F1\narc: E3_H06E0003 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q2\narc: H01W0100 F4\narc: LSR0 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: S1_V02S0101 F1\narc: S1_V02S0701 F5\narc: S3_V06S0103 F1\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V01S0000 Q2\narc: V01S0100 F3\narc: W1_H02W0101 F1\narc: W1_H02W0301 F1\narc: W3_H06W0003 F3\narc: W3_H06W0203 F4\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 1100000000000000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0011000000000000\nword: SLICEC.K0.INIT 0000001100000000\nword: SLICEC.K1.INIT 0000110000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R5C54:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 V02S0701\narc: H00L0000 V02S0001\narc: H00R0000 H02W0601\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 H01E0101\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0701 H01E0101\narc: V00B0000 V02N0201\narc: V00B0100 H02W0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 S1_V02N0001\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: S1_V02S0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: A0 E1_H02W0501\narc: A1 H01E0001\narc: A6 H02E0501\narc: A7 V00T0100\narc: B0 V00B0000\narc: B1 V02N0101\narc: B6 H02W0101\narc: B7 V00B0100\narc: C0 H00L0000\narc: C1 H00L0000\narc: C6 E1_H02W0601\narc: C7 E1_H02W0401\narc: D0 H00R0000\narc: D1 S1_V02N0201\narc: D6 H00R0100\narc: D7 V01N0001\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: S3_V06S0003 F0\narc: V00T0100 F1\nword: SLICEA.K0.INIT 1000000010101010\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000110010101100\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R5C55:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 V01N0001\narc: H00L0000 V02N0201\narc: H00R0000 V02N0401\narc: N1_V01N0001 S3_V06N0003\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0501 H02E0501\narc: V00B0000 S1_V02N0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02E0201\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 H01E0101\narc: E3_H06E0003 W3_H06E0303\narc: A3 V00T0000\narc: A5 H02E0701\narc: B3 V02N0301\narc: B5 H00L0000\narc: B6 V00B0000\narc: C3 S1_V02N0401\narc: C5 V00B0100\narc: C6 V00T0100\narc: C7 S1_V02N0001\narc: D3 H00R0000\narc: D5 H02W0001\narc: D6 H02W0001\narc: D7 V02N0401\narc: E1_H01E0001 F3\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: M6 E1_H02W0401\narc: W1_H02W0601 F6\narc: W1_H02W0701 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0000001111001111\nword: SLICED.K1.INIT 1111000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R5C56:PLC2\narc: H00L0000 S1_V02N0201\narc: H00L0100 H02E0301\narc: H00R0000 S1_V02N0601\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0701 H06E0203\narc: V00B0000 H02W0401\narc: V00T0000 H02E0001\narc: V00T0100 H02W0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 E1_H01W0000\narc: W1_H02W0501 W3_H06E0303\narc: A1 H00L0100\narc: A5 V02S0101\narc: A6 H02W0701\narc: A7 F5\narc: B1 V02N0101\narc: B2 H02E0101\narc: B5 V02S0701\narc: B6 V02S0501\narc: B7 F1\narc: C1 H00L0000\narc: C2 H02E0401\narc: C3 H02E0601\narc: C5 V00T0000\narc: C6 V00T0100\narc: C7 V01N0101\narc: D1 H02E0201\narc: D2 H00R0000\narc: D3 E1_H02W0001\narc: D5 S1_V02N0601\narc: D6 H01W0000\narc: D7 V02N0601\narc: E3_H06E0303 F6\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M2 V00B0000\narc: S1_V02S0001 F2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000110010101100\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000001111001111\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R5C57:PLC2\narc: S1_V02S0401 H02W0401\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 S1_V02N0701\narc: H01W0000 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\n\n.tile R5C58:PLC2\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0401 S3_V06N0203\narc: W3_H06W0003 S3_V06N0003\n\n.tile R5C59:PLC2\narc: S1_V02S0001 W3_H06E0003\narc: W3_H06W0303 E3_H06W0203\n\n.tile R5C5:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0701 V02S0701\narc: H00L0000 H02E0201\narc: H00R0000 V02S0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 V01N0001\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0501 N1_V01S0100\narc: V00B0000 N1_V02S0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 S1_V02N0601\narc: V00T0100 V02S0701\narc: W1_H02W0701 E1_H02W0601\narc: A1 N1_V02S0501\narc: B1 V00B0000\narc: B3 H00L0000\narc: C1 H02E0601\narc: C3 E1_H02W0401\narc: CE2 H00R0100\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 V01S0100\narc: D3 E1_H02W0001\narc: E1_H02E0001 Q2\narc: E1_H02E0301 F1\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 Q6\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V02N0401 Q4\narc: V01S0100 Q6\narc: W3_H06W0103 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R5C60:PLC2\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\n\n.tile R5C61:PLC2\narc: S3_V06S0003 W3_H06E0003\n\n.tile R5C62:PLC2\narc: E3_H06E0003 W3_H06E0303\n\n.tile R5C65:PLC2\narc: W3_H06W0203 E3_H06W0203\n\n.tile R5C66:PLC2\narc: E1_H02E0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\n\n.tile R5C68:PLC2\narc: E1_H02E0301 W1_H02E0201\narc: E3_H06E0003 W3_H06E0003\n\n.tile R5C69:PLC2\narc: E1_H02E0501 S1_V02N0501\narc: S3_V06S0003 H06E0003\n\n.tile R5C6:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 H02W0201\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 H02W0601\narc: S1_V02S0101 H06E0103\narc: V00B0000 H02W0601\narc: V00B0100 H02E0701\narc: V00T0000 H02E0201\narc: W1_H02W0601 S1_V02N0601\narc: A1 H00R0000\narc: A3 E1_H01E0001\narc: B1 H02E0101\narc: B3 E1_H02W0301\narc: B7 V02S0701\narc: C1 H00L0000\narc: C3 V02S0601\narc: C7 V01N0101\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 N1_V02S0201\narc: D3 W1_H02E0001\narc: D6 E1_H02W0201\narc: D7 V00B0000\narc: E1_H01E0001 Q4\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 Q6\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F3\narc: N1_V01N0101 Q4\narc: N1_V02N0401 Q6\narc: V01S0000 F1\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICED.K0.INIT 1111111100000000\nword: SLICED.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R5C70:PLC2\narc: E1_H02E0601 W1_H02E0301\n\n.tile R5C7:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 S1_V02N0501\narc: H00L0000 H02W0001\narc: H00R0000 S1_V02N0401\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 H06E0203\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02S0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: A5 H02E0501\narc: B3 H02W0301\narc: B5 H00L0000\narc: C3 V02N0601\narc: C5 V00T0000\narc: CE0 H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D2 H02E0001\narc: D3 H00R0000\narc: D5 V02N0401\narc: E1_H01E0001 Q6\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q0\narc: H01W0100 Q2\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 E1_H02W0601\narc: M2 V00T0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q6\narc: N1_V02N0201 Q2\narc: S1_V02S0501 F5\narc: V01S0100 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000001\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R5C8:PLC2\narc: E1_H02E0101 V06N0103\narc: E1_H02E0601 W1_H02E0601\narc: H00R0000 E1_H02W0601\narc: N1_V02N0001 S1_V02N0001\narc: S1_V02S0301 N1_V01S0100\narc: V00B0000 E1_H02W0401\narc: V00B0100 V02N0101\narc: V00T0100 H02E0301\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 E1_H01W0100\narc: W3_H06W0303 E1_H02W0601\narc: A5 N1_V01S0100\narc: B1 V00T0000\narc: B5 V02S0501\narc: C1 S1_V02N0401\narc: C5 V02S0201\narc: CE1 H00R0000\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 S1_V02N0201\narc: D5 H02W0001\narc: E1_H01E0001 Q0\narc: F0 F5A_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: LSR1 V00B0100\narc: M0 V00B0000\narc: M2 V00T0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q0\narc: N1_V02N0201 Q2\narc: S1_V02S0701 F5\narc: V00T0000 Q2\narc: V01S0100 Q6\narc: W1_H02W0001 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111000011001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R5C9:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 S1_V02N0001\narc: H00R0000 V02N0601\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 S1_V02N0201\narc: N3_V06N0203 H01E0001\narc: V00B0000 E1_H02W0401\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02W0201\narc: V00T0100 E1_H02W0301\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0601 E1_H02W0301\narc: W3_H06W0203 V06N0203\narc: CE0 H00R0000\narc: CE1 H00L0000\narc: CE2 V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: E1_H02E0201 Q0\narc: E1_H02E0401 Q4\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: H01W0100 Q6\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 H02E0601\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: S1_V02S0601 Q4\narc: S3_V06S0003 Q0\narc: S3_V06S0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R6C10:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 V02S0401\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00R0100 H02W0701\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0701 E3_H06W0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 S3_V06N0303\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 V02S0001\narc: V01S0000 S3_V06N0103\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 V02N0601\narc: CLK0 G_HPBX0000\narc: D5 H00R0100\narc: F5 F5_SLICE\narc: LSR0 V00B0100\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V02N0001 Q0\narc: V00B0100 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R6C11:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 V01N0001\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 N1_V01S0100\narc: E3_H06E0003 N1_V01S0000\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 H02E0201\narc: H00R0000 H02W0601\narc: H00R0100 V02N0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0701 E1_H01W0100\narc: V00B0100 V02N0101\narc: V00T0000 V02S0601\narc: W1_H02W0701 H01E0101\narc: B1 V00T0000\narc: B3 H00R0000\narc: B5 H00L0000\narc: B7 H02E0301\narc: C1 H02W0401\narc: C3 H02W0401\narc: C5 H02W0401\narc: C7 H02W0401\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D3 V02N0001\narc: D5 H00R0100\narc: D7 V02N0601\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q3\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0301 Q1\narc: V01S0000 Q7\narc: V01S0100 Q5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111110000001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111110000001100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110000001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R6C12:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 V02N0001\narc: H00R0000 W1_H02E0401\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H02W0601\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N1_V02S0101\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 N1_V02S0201\narc: V00B0100 V02N0101\narc: V00T0000 V02S0401\narc: V00T0100 V02N0701\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 N1_V02S0601\narc: B1 V00B0000\narc: B3 H00L0000\narc: B5 H00R0000\narc: B7 N1_V01S0000\narc: C1 V02S0401\narc: C3 V02S0401\narc: C5 V00T0000\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D3 V00B0100\narc: D5 H02E0201\narc: D7 V01N0001\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q5\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q1\narc: S1_V02S0101 Q3\narc: V01S0000 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111110000001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111110000001100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110000001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R6C13:PLC2\narc: H00L0000 N1_V02S0001\narc: H00L0100 E1_H02W0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02S0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 H02E0101\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0701 H06W0203\narc: V00B0000 E1_H02W0601\narc: V00B0100 E1_H02W0501\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0601 S1_V02N0601\narc: B1 V00T0000\narc: B3 H00R0100\narc: B5 H02E0301\narc: C0 W1_H02E0401\narc: C1 H00L0000\narc: C2 E1_H02W0401\narc: C3 H00L0100\narc: C4 V02S0201\narc: C5 H02E0601\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 V00B0000\narc: D5 V00B0000\narc: E1_H01E0101 F4\narc: E1_H02E0001 F0\narc: E1_H02E0201 F2\narc: E1_H02E0601 Q6\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: LSR0 H02W0501\narc: M0 V00B0100\narc: M2 V00B0100\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111100001111\nword: SLICEA.K1.INIT 0000111100110011\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 0000111100110011\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 0000111100110011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R6C14:PLC2\narc: E1_H02E0601 S1_V02N0601\narc: H00R0000 W1_H02E0401\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H02E0601\narc: V00B0000 V02S0001\narc: V00B0100 V02N0101\narc: V00T0100 S1_V02N0701\narc: B1 V00B0000\narc: B3 H00R0000\narc: B7 W1_H02E0101\narc: C1 H00R0100\narc: C3 H00R0100\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D3 H01E0101\narc: D5 H02W0001\narc: D7 H02E0201\narc: E1_H02E0501 Q7\narc: E3_H06E0103 Q1\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: V01S0000 Q3\narc: W1_H02W0501 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100000011111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R6C15:PLC2\narc: E1_H02E0401 V02N0401\narc: H00L0000 H02W0201\narc: H00R0000 H02W0601\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0001 H02W0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 H06W0103\narc: V00B0000 V02S0001\narc: V00B0100 V02S0101\narc: V00T0000 N1_V02S0601\narc: V00T0100 H02W0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V02N0601\narc: N1_V02N0501 W3_H06E0303\narc: A0 H02W0701\narc: A1 H02W0701\narc: A2 H02W0701\narc: A3 H02W0701\narc: A4 N1_V02S0301\narc: A5 V00T0100\narc: B0 H02W0301\narc: B1 H02W0301\narc: B2 H02W0301\narc: B3 H02W0301\narc: B4 V00B0100\narc: B5 V02N0701\narc: C0 H00L0000\narc: C1 H00L0000\narc: C2 H00L0000\narc: C3 H00L0000\narc: C4 V00T0000\narc: C5 H02E0601\narc: CE0 V02S0201\narc: CE1 V02S0201\narc: CLK1 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D2 H00R0000\narc: D3 H00R0000\narc: D4 V02S0601\narc: D5 E1_H02W0201\narc: E1_H02E0001 Q0\narc: E1_H02E0301 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR1 V00B0000\narc: MUXCLK0 CLK1\narc: MUXCLK1 CLK1\narc: N1_V01N0001 Q3\narc: N1_V01N0101 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE RAMW\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE DPRAM\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE DPRAM\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.WREMUX WRE\nenum: CLK1.CLKMUX CLK\n\n.tile R6C16:PLC2\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0601 N1_V01S0000\narc: H00L0000 V02S0201\narc: H00R0100 H02W0701\narc: N1_V02N0001 S3_V06N0003\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 H06W0103\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 H06W0203\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 E1_H02W0701\narc: V00T0000 S1_V02N0601\narc: V00T0100 H02W0101\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 V02N0101\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A7 N1_V01N0101\narc: B0 V02S0101\narc: B4 H00R0000\narc: B5 H00R0000\narc: B7 V00B0100\narc: C0 H02W0601\narc: C1 H00L0100\narc: C4 V00T0100\narc: C5 H02E0401\narc: C7 E1_H01E0101\narc: CE0 V02S0201\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 Q0\narc: D1 V01S0100\narc: D4 H00R0100\narc: D5 H00R0100\narc: D6 V00B0000\narc: D7 V02N0401\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q6\narc: E1_H02E0501 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: H00R0000 Q4\narc: H01W0000 Q4\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q1\narc: N1_V01N0101 Q1\narc: N1_V02N0101 Q1\narc: N1_V02N0301 Q1\narc: N1_V02N0401 Q4\narc: N1_V02N0501 Q7\narc: N1_V02N0601 Q4\narc: N1_V02N0701 Q7\narc: N3_V06N0203 Q4\narc: V00B0000 Q6\narc: V00B0100 Q7\narc: V01S0000 Q0\narc: V01S0100 Q6\narc: W1_H02W0201 Q0\narc: W1_H02W0301 Q1\narc: W1_H02W0601 Q6\narc: W1_H02W0701 Q7\narc: W3_H06W0203 Q4\nword: SLICEA.K0.INIT 0011111111000000\nword: SLICEA.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 1111111100001100\nword: SLICEC.K1.INIT 1111111111000000\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0110110011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\n\n.tile R6C17:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 V06S0303\narc: E3_H06E0003 S3_V06N0003\narc: H00L0000 V02N0201\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 W1_H02E0301\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0301 H02E0301\narc: S3_V06S0003 H06W0003\narc: V00B0000 V02N0001\narc: V00B0100 S1_V02N0301\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 N1_V02S0701\narc: A7 H00L0000\narc: B7 V00B0100\narc: C7 V00T0100\narc: CE0 N1_V02S0201\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR0 H02W0301\narc: M0 H02E0601\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V02N0201 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R6C18:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 N1_V01S0100\narc: H00L0000 S1_V02N0001\narc: H00L0100 S1_V02N0101\narc: H00R0000 V02N0401\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 H02E0601\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 W1_H02E0201\narc: V00B0100 V02N0101\narc: V00T0000 H02E0001\narc: V00T0100 W1_H02E0101\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0601 E1_H01W0000\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A5 N1_V01N0101\narc: B5 H00R0000\narc: C5 V00T0000\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D5 H00L0100\narc: E1_H02E0001 Q0\narc: E1_H02E0201 Q2\narc: E1_H02E0401 Q6\narc: F5 F5_SLICE\narc: H01W0100 Q0\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 H02W0601\narc: M2 V00B0100\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q2\narc: V01S0100 Q6\narc: W1_H02W0701 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R6C19:PLC2\narc: E1_H02E0601 E1_H01W0000\narc: H00L0100 H02W0101\narc: H00R0100 H02E0501\narc: N1_V02N0401 H06E0203\narc: N1_V02N0701 H06E0203\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 N1_V02S0201\narc: V00B0000 H02W0401\narc: V00B0100 V02S0101\narc: V00T0000 H02W0201\narc: W1_H02W0601 V02N0601\narc: W3_H06W0103 E3_H06W0003\narc: B0 H02E0301\narc: C0 H00R0100\narc: C1 N1_V01S0100\narc: C3 H00L0100\narc: C5 V00T0000\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0001\narc: D1 S1_V02N0201\narc: D3 H02W0001\narc: D5 E1_H01W0100\narc: D7 E1_H01W0100\narc: E1_H02E0201 Q0\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q3\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: V01S0100 Q5\narc: W3_H06W0203 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 1100000011111111\nword: SLICEA.K1.INIT 0000111111111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R6C20:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 V06N0303\narc: H00L0100 H02W0301\narc: H00R0000 H02W0601\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 S1_V02N0701\narc: V00B0000 E1_H02W0401\narc: V00B0100 E1_H02W0701\narc: V00T0000 V02N0601\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 V02N0401\narc: E3_H06E0203 W3_H06E0103\narc: A1 V02S0701\narc: A2 E1_H01E0001\narc: A3 V02S0501\narc: A4 V02N0301\narc: A7 V02S0301\narc: B1 V01N0001\narc: B2 H00R0100\narc: B3 N1_V02S0301\narc: B4 H00R0000\narc: B7 V00B0000\narc: C0 V02N0401\narc: C1 H00L0000\narc: C2 N1_V01S0100\narc: C3 H00L0100\narc: C4 V00T0000\narc: C5 V02N0201\narc: C7 V02S0001\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 V01S0100\narc: D2 V00B0100\narc: D3 V00T0100\narc: D4 V02S0601\narc: D5 H02W0201\narc: D7 E1_H01W0100\narc: E1_H01E0001 F3\narc: E1_H02E0101 Q1\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H00R0100 F7\narc: H01W0000 F5\narc: H01W0100 F0\narc: LSR1 E1_H02W0301\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0001 F5\narc: S1_V02S0001 F0\narc: S1_V02S0701 F5\narc: V01S0100 F4\narc: W1_H02W0001 F0\narc: W3_H06W0003 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001011\nword: SLICEA.K0.INIT 0000111100000000\nword: SLICEA.K1.INIT 1110110011111111\nword: SLICEC.K0.INIT 0001010100111111\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 1000000000000000\nword: SLICEB.K1.INIT 1000010010100101\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R6C21:PLC2\narc: E1_H02E0601 E1_H01W0000\narc: H00L0000 H02E0001\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 H02E0601\narc: S1_V02S0201 W1_H02E0201\narc: V00B0000 H02E0401\narc: V00T0100 H02E0301\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0601 V01N0001\narc: W3_H06W0003 E3_H06W0003\narc: A0 V02N0701\narc: A2 V01N0101\narc: A3 E1_H02W0501\narc: A4 V00B0000\narc: A5 V00T0100\narc: A6 H02E0501\narc: A7 H00L0000\narc: E1_H01E0001 F2\narc: E1_H01E0101 F4\narc: E1_H02E0501 F7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F6\narc: N1_V01N0001 F5\narc: W1_H02W0301 F3\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R6C22:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 S1_V02N0201\narc: H00L0100 S1_V02N0301\narc: H00R0100 H02E0501\narc: V00B0000 H02E0601\narc: V00B0100 V02S0101\narc: W1_H02W0101 H01E0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 H01E0001\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0601 W3_H06E0303\narc: H01W0000 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0501 W3_H06E0303\narc: S1_V02S0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A0 V02N0701\narc: A1 H00L0100\narc: B5 V01S0000\narc: C5 V00T0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D5 H00R0100\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: LSR0 V00B0000\narc: M6 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00T0100 F1\narc: V01S0000 F0\narc: W1_H02W0701 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000011\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R6C23:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 S1_V02N0501\narc: E3_H06E0003 S3_V06N0003\narc: H00L0100 N1_V02S0101\narc: H00R0100 N1_V02S0501\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0701 N1_V01S0100\narc: V00B0000 V02N0001\narc: V00B0100 H02E0501\narc: V00T0100 S1_V02N0501\narc: W1_H02W0501 H01E0101\narc: W1_H02W0701 V02N0701\narc: E3_H06E0103 W3_H06E0003\narc: A1 H01E0001\narc: A3 H00L0100\narc: A5 S1_V02N0301\narc: A6 H02E0701\narc: B1 V01N0001\narc: B3 V02S0301\narc: B5 S1_V02N0701\narc: B6 H02E0101\narc: B7 V01S0000\narc: C1 H02W0601\narc: C3 S1_V02N0401\narc: C5 V00T0100\narc: C6 H02W0401\narc: C7 E1_H01E0101\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D3 V00B0100\narc: D5 V02N0601\narc: D6 H00R0100\narc: D7 V02S0601\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q7\narc: LSR0 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: S3_V06S0303 F6\narc: V01S0000 F5\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0000000000000001\nword: SLICED.K1.INIT 0011111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R6C24:PLC2\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0303 S3_V06N0303\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02N0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H02W0201\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S1_V02N0301\narc: V00B0000 W1_H02E0601\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02N0601\narc: V00T0100 W1_H02E0301\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: A5 N1_V01N0101\narc: B5 H00L0000\narc: C5 S1_V02N0201\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D5 H00R0100\narc: F4 F5C_SLICE\narc: H00L0000 Q0\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 V00T0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q2\narc: V01S0000 F4\narc: V01S0100 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111010111110011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R6C25:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 V06S0303\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 N1_V02S0001\narc: H00L0100 V02S0301\narc: H00R0000 V02S0601\narc: H00R0100 W1_H02E0501\narc: N1_V02N0301 H06E0003\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 H06E0303\narc: V00B0000 V02S0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02S0401\narc: W1_H02W0201 S1_V02N0201\narc: A0 H00L0000\narc: A3 V00T0000\narc: B0 V00B0000\narc: B3 H00R0000\narc: B5 N1_V01S0000\narc: C0 E1_H01W0000\narc: C3 H00R0100\narc: C5 V02S0001\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D3 S1_V02N0201\narc: D5 H00L0100\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: LSR0 E1_H02W0501\narc: M0 V00B0100\narc: M6 E1_H02W0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V02N0001 F0\narc: S1_V02S0501 F5\narc: V01S0000 Q6\narc: V01S0100 Q6\narc: W3_H06W0003 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0111010111111101\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R6C26:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0303 W1_H02E0601\narc: H00R0000 V02N0601\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 H02E0601\narc: S1_V02S0101 V01N0101\narc: S1_V02S0201 V01N0001\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 E1_H02W0601\narc: W1_H02W0101 V01N0101\narc: H01W0000 W3_H06E0103\narc: W1_H02W0401 W3_H06E0203\narc: A4 V00T0100\narc: B0 H01W0100\narc: B4 H00L0000\narc: B5 H02E0101\narc: B6 V02N0701\narc: C0 H00L0000\narc: C1 H00L0100\narc: C4 Q4\narc: C5 V00T0000\narc: C6 V00B0100\narc: C7 V02S0201\narc: CE0 H02W0101\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D4 V02N0601\narc: D5 V00B0000\narc: D6 V02N0601\narc: D7 H00R0100\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00L0100 Q1\narc: H00R0100 F5\narc: H01W0100 Q1\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0501\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q6\narc: V00B0000 Q4\narc: V00B0100 F5\narc: V00T0000 Q0\narc: V00T0100 Q1\narc: V01S0000 F7\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 1110000111111111\nword: SLICEC.K1.INIT 0000000000000011\nword: SLICEA.K0.INIT 1100001111111111\nword: SLICEA.K1.INIT 0000111111111111\nword: SLICED.K0.INIT 0011110011111111\nword: SLICED.K1.INIT 0000111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R6C27:PLC2\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 E1_H01W0100\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 V02N0001\narc: H00R0000 V02S0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0101 H02W0101\narc: N1_V02N0601 H02E0601\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 V01N0001\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: V00T0100 S1_V02N0501\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 V01N0101\narc: A0 S1_V02N0701\narc: A2 E1_H02W0701\narc: A5 H02W0701\narc: A7 H02E0701\narc: B0 H00R0100\narc: B2 H02E0101\narc: B3 V02N0101\narc: B5 H00L0000\narc: B7 V00B0000\narc: C0 V02N0601\narc: C1 E1_H02W0601\narc: C2 H00L0100\narc: C3 V02N0401\narc: C5 V02N0201\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H01E0101\narc: D2 W1_H02E0001\narc: D3 H02E0001\narc: D5 E1_H02W0201\narc: D7 N1_V02S0401\narc: E1_H02E0101 F3\narc: E1_H02E0201 F2\narc: E3_H06E0003 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H01W0000 F7\narc: LSR1 V00T0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F5\narc: S3_V06S0003 F0\narc: V01S0100 Q5\narc: W1_H02W0101 F1\narc: W3_H06W0003 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0001010100111111\nword: SLICEB.K1.INIT 0011000000000000\nword: SLICEA.K0.INIT 1111001111010001\nword: SLICEA.K1.INIT 0000111111111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R6C28:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0501 W1_H02E0401\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02W0401\narc: N1_V02N0301 W1_H02E0301\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 N1_V01S0000\narc: V00B0100 H02E0501\narc: V00T0000 H02W0001\narc: V00T0100 H02W0101\narc: W1_H02W0701 V02N0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0601 W3_H06E0303\narc: H01W0000 W3_H06E0103\narc: H01W0100 W3_H06E0303\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: N3_V06N0003 W3_H06E0003\narc: N3_V06N0303 W3_H06E0303\narc: S1_V02S0501 W3_H06E0303\narc: S1_V02S0601 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: C1 H02W0401\narc: CE2 H00L0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: F1 F1_SLICE\narc: LSR0 H02W0501\narc: LSR1 V00T0000\narc: M4 V00T0100\narc: M6 H02E0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q4\narc: S1_V02S0301 F1\narc: V01S0100 Q4\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R6C29:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 H02E0201\narc: H00R0100 E1_H02W0701\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0601 H01E0001\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02E0001\narc: V00T0100 V02S0501\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 N1_V01S0100\narc: N1_V02N0001 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: A2 E1_H01E0001\narc: A3 E1_H01E0001\narc: B2 V02N0101\narc: B3 H00R0100\narc: C2 H00L0000\narc: C3 E1_H02W0601\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 H02W0001\narc: E1_H01E0001 Q4\narc: E3_H06E0303 Q6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR0 V00B0000\narc: LSR1 V00T0000\narc: M4 V00T0100\narc: M6 H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q2\narc: S3_V06S0003 F3\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1110001011000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R6C2:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0601 E3_H06W0303\narc: H00R0000 H02E0401\narc: H00R0100 E1_H02W0701\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0001 E1_H01W0000\narc: V00B0000 H02E0601\narc: V00T0100 H02W0301\narc: A5 V00T0000\narc: B5 N1_V01S0000\narc: C5 S1_V02N0001\narc: CE0 E1_H02W0101\narc: CE1 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: E1_H01E0001 Q6\narc: E1_H02E0001 Q2\narc: E1_H02E0201 Q0\narc: E3_H06E0303 F5\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: M0 V00T0100\narc: M2 V00T0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR1\narc: V00T0000 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R6C30:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 H02W0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02N0401\narc: N1_V02N0301 S1_V02N0201\narc: S1_V02S0301 H02E0301\narc: S3_V06S0003 H06E0003\narc: V00B0000 W1_H02E0401\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02N0401\narc: V00T0100 V02N0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0401 S1_V02N0401\narc: N1_V02N0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0103\narc: A1 E1_H01E0001\narc: A4 V02N0101\narc: A6 N1_V01N0101\narc: B1 N1_V02S0101\narc: B4 H00L0000\narc: B6 N1_V01S0000\narc: C0 V02N0401\narc: C1 H02W0601\narc: C3 N1_V02S0601\narc: C4 H02E0401\narc: C5 V00T0000\narc: C6 H02E0401\narc: C7 V00T0000\narc: CE0 H02E0101\narc: CE2 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00B0100\narc: D3 H00R0000\narc: D4 V02N0601\narc: D5 H02W0201\narc: D6 H00L0100\narc: D7 V02S0401\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F3\narc: LSR0 W1_H02E0301\narc: LSR1 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q7\narc: S1_V02S0101 F3\narc: S1_V02S0401 F6\narc: S3_V06S0103 F1\narc: S3_V06S0203 F4\narc: V01S0100 Q5\nword: SLICEA.K0.INIT 0000111100000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0001001101011111\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 0001001101011111\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R6C31:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0601 V02N0601\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 H01E0101\narc: H00L0000 H02E0001\narc: H00R0000 S1_V02N0601\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 S1_V02N0201\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 H02W0301\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 V02N0201\narc: V00B0100 S1_V02N0101\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0701 E3_H06W0203\narc: W1_H02W0601 W3_H06E0303\narc: CE0 H00L0000\narc: CE1 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q6\narc: E1_H02E0401 Q6\narc: E3_H06E0003 Q0\narc: M0 V00B0000\narc: M2 V00B0100\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: V01S0000 Q2\narc: V01S0100 Q2\narc: W1_H02W0001 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R6C32:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0201 V01N0001\narc: E1_H02E0701 N1_V01S0100\narc: H00L0000 V02S0201\narc: H00L0100 H02W0301\narc: H00R0100 S1_V02N0501\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 N1_V01S0100\narc: S3_V06S0003 H01E0001\narc: V00B0000 H02E0601\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: A1 H01E0001\narc: A2 H01E0001\narc: B1 V02N0101\narc: B2 V02N0101\narc: C1 H00L0000\narc: C2 H00L0000\narc: CE2 E1_H02W0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D2 H02E0001\narc: E1_H01E0101 Q4\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 F1\narc: M0 E1_H02W0601\narc: M1 H00R0100\narc: M2 E1_H02W0601\narc: M4 V00B0000\narc: M6 V00B0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: S1_V02S0401 Q6\narc: V01S0000 Q6\narc: V01S0100 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010111100100011\nword: SLICEB.K0.INIT 1010111100100011\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R6C33:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 H01E0101\narc: H00L0100 S1_V02N0101\narc: H00R0100 V02N0701\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0201 H02W0201\narc: S1_V02S0701 V01N0101\narc: V00B0100 V02N0301\narc: V00T0000 V02N0601\narc: V01S0100 S3_V06N0303\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 S1_V02N0301\narc: E3_H06E0303 W3_H06E0303\narc: A1 E1_H02W0701\narc: B1 H00R0100\narc: C1 E1_H01W0000\narc: D1 V00B0100\narc: E1_H01E0001 F3\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: H01W0100 F3\narc: M0 V00T0000\narc: M1 H00L0100\narc: M2 V00T0000\narc: M3 W1_H02E0201\narc: M4 V00T0000\narc: M5 H00L0100\narc: M6 V00T0000\narc: N1_V02N0101 F3\narc: N1_V02N0301 F3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R6C34:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0501 S1_V02N0501\narc: H00L0000 H02W0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02E0401\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0401 H02E0401\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 W1_H02E0701\narc: V00B0100 S1_V02N0301\narc: V00T0000 S1_V02N0401\narc: V00T0100 V02S0501\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 S3_V06N0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A0 H01E0001\narc: A4 H02E0701\narc: A5 V00T0000\narc: A7 H02E0501\narc: B0 V02S0301\narc: B4 H00R0000\narc: B5 V02N0501\narc: B7 V02N0701\narc: C0 H00L0000\narc: C4 S1_V02N0001\narc: C5 S1_V02N0201\narc: C7 V00B0100\narc: D0 W1_H02E0001\narc: D4 H00L0100\narc: D5 W1_H02E0201\narc: D7 H00R0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 F4\narc: E1_H02E0401 F6\narc: E1_H02E0601 F6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00R0100 F5\narc: H01W0000 F5\narc: M0 V00T0100\narc: M1 E1_H02W0001\narc: M2 V00T0100\narc: M6 N1_V01N0101\narc: N1_V01N0101 F4\narc: N1_V02N0101 F1\narc: S3_V06S0103 F1\narc: V01S0000 F1\nword: SLICEC.K0.INIT 1010111100100011\nword: SLICEC.K1.INIT 1111010100110001\nword: SLICEA.K0.INIT 1101000011011101\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1101000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R6C35:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0601 W1_H02E0301\narc: H00L0100 V02S0301\narc: H00R0000 V02S0401\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 H01E0001\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0501 H06E0303\narc: V00B0000 V02N0001\narc: V00B0100 V02S0301\narc: W1_H02W0201 V06S0103\narc: W1_H02W0701 H01E0101\narc: W3_H06W0003 S3_V06N0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A0 V02N0701\narc: A1 V02N0701\narc: A2 V02N0701\narc: A3 V02N0701\narc: A4 V02N0301\narc: A6 V02N0101\narc: A7 V02N0301\narc: B0 V01N0001\narc: B1 V01N0001\narc: B2 V01N0001\narc: B3 V01N0001\narc: B4 S1_V02N0501\narc: B6 S1_V02N0501\narc: B7 S1_V02N0501\narc: C0 H02E0401\narc: C1 H02E0601\narc: C2 H02E0601\narc: C3 H02E0401\narc: C4 H02E0401\narc: C6 H02E0401\narc: C7 H02E0601\narc: D0 V00B0100\narc: D1 V00B0100\narc: D2 V00B0100\narc: D3 V00B0100\narc: D4 H00L0100\narc: D6 H00L0100\narc: D7 H00L0100\narc: E3_H06E0003 F3\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00B0000\narc: M1 W1_H02E0001\narc: M2 V00B0000\narc: M3 H00R0000\narc: M4 V00B0000\narc: M5 W1_H02E0001\narc: M6 V00B0000\narc: S1_V02S0301 F3\narc: S3_V06S0003 F3\nword: SLICEA.K0.INIT 1111111101111111\nword: SLICEA.K1.INIT 1111111101111111\nword: SLICEB.K0.INIT 1111111101111111\nword: SLICEB.K1.INIT 1111111101111111\nword: SLICEC.K0.INIT 1111111101111111\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111111101111111\nword: SLICED.K1.INIT 1111111101111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R6C36:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 V02S0601\narc: H00L0000 N1_V02S0001\narc: H00L0100 E1_H02W0301\narc: H00R0000 N1_V02S0401\narc: H00R0100 V02S0701\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 S1_V02N0301\narc: N3_V06N0003 H06E0003\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0601 E1_H01W0000\narc: V00B0000 H02W0601\narc: V00B0100 W1_H02E0501\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02S0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: A0 H00L0000\narc: A1 H00L0000\narc: A4 V02S0101\narc: A5 V02S0301\narc: B0 V00B0000\narc: B1 V00B0000\narc: B4 H02E0101\narc: B5 H02E0101\narc: B6 N1_V02S0701\narc: C0 H02E0601\narc: C1 H02E0601\narc: C4 V02S0001\narc: C5 V02S0001\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: CE0 S1_V02N0201\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D4 H00L0100\narc: D5 H00L0100\narc: D6 H00R0100\narc: D7 H02W0001\narc: E1_H01E0101 F7\narc: E1_H02E0301 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 V00T0000\narc: M1 H02E0001\narc: M2 V00T0000\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR3 LSR0\narc: S1_V02S0401 F4\narc: S3_V06S0103 Q1\narc: S3_V06S0303 Q6\narc: V01S0000 F1\narc: W3_H06W0103 Q1\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000001100110011\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEC.K0.INIT 0000000011101010\nword: SLICEC.K1.INIT 0000000000010101\nword: SLICEA.K0.INIT 1111111111111110\nword: SLICEA.K1.INIT 1111111111111110\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R6C37:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 V01N0001\narc: H00L0000 V02S0201\narc: H00L0100 N1_V02S0101\narc: H00R0000 H02W0401\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 V01N0101\narc: V00B0000 S1_V02N0201\narc: V00B0100 N1_V02S0301\narc: V00T0100 H02E0301\narc: W1_H02W0001 V06S0003\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 H01E0001\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 V01N0101\narc: B0 W1_H02E0301\narc: B7 N1_V01S0000\narc: C0 V02S0401\narc: C2 V02N0401\narc: C3 H00L0000\narc: C7 V00B0100\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D2 V00T0100\narc: D3 V00T0100\narc: D7 H00L0100\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: M0 H02E0601\narc: M1 H02E0001\narc: M2 H02E0601\narc: M4 V00B0000\narc: MUXCLK2 CLK0\narc: V01S0000 Q4\narc: V01S0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000011\nword: SLICEB.K0.INIT 1111111100001111\nword: SLICEB.K1.INIT 1111111100001111\nword: SLICEA.K0.INIT 0011111100010101\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R6C38:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 W1_H02E0501\narc: H00L0000 H02E0201\narc: H00L0100 H02E0101\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0601 S3_V06N0303\narc: S1_V02S0601 H02E0601\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0101\narc: W1_H02W0401 S1_V02N0401\narc: W3_H06W0103 E1_H01W0100\narc: W3_H06W0003 E3_H06W0003\narc: A2 V00B0000\narc: A3 V00B0000\narc: B2 N1_V02S0101\narc: B3 N1_V02S0101\narc: C2 H00L0100\narc: C3 H00L0100\narc: D2 E1_H02W0201\narc: D3 E1_H02W0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00L0000\narc: M2 V00B0100\narc: M3 H00R0100\narc: M4 V00B0100\narc: M5 H00L0000\narc: M6 V00B0100\narc: W1_H02W0301 F3\nword: SLICEB.K0.INIT 1111111111111110\nword: SLICEB.K1.INIT 1111111111111110\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R6C39:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0601 W1_H02E0301\narc: H00R0100 H02E0501\narc: H01W0100 E3_H06W0303\narc: N1_V02N0101 S1_V02N0001\narc: S1_V02S0201 E1_H01W0000\narc: V00B0000 H02E0401\narc: W1_H02W0601 E1_H02W0301\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0001 W3_H06E0003\narc: N1_V02N0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: A2 V02S0501\narc: A3 V02S0501\narc: B2 V02S0101\narc: B3 V02S0101\narc: C2 E1_H01W0000\narc: C3 E1_H01W0000\narc: D2 V02N0201\narc: D3 V02N0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0000\narc: M1 H02E0001\narc: M2 V00B0000\narc: M3 H00R0100\narc: M4 H02E0401\narc: M5 H02E0001\narc: M6 H02E0401\narc: S1_V02S0301 F3\narc: V01S0000 F3\narc: V01S0100 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111111111111110\nword: SLICEB.K1.INIT 1111111111111110\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R6C3:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 S1_V02N0201\narc: H00R0000 S1_V02N0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 H06W0303\narc: S1_V02S0301 V01N0101\narc: V00B0000 E1_H02W0401\narc: V00B0100 V02N0301\narc: V00T0000 V02S0601\narc: V00T0100 V02N0701\narc: W1_H02W0301 V02N0301\narc: A1 H01E0001\narc: B1 H02E0101\narc: B3 W1_H02E0101\narc: B7 V00T0000\narc: C1 H00L0000\narc: C3 H00R0100\narc: C7 H02E0601\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V02N0201\narc: D2 H02E0201\narc: D3 V00T0100\narc: D6 H02E0001\narc: D7 V02N0401\narc: E1_H02E0301 F1\narc: E3_H06E0103 Q2\narc: E3_H06E0303 Q6\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q2\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q4\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 1111111100000000\nword: SLICED.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R6C40:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: H00L0000 W1_H02E0201\narc: H00L0100 H02E0301\narc: H00R0000 H02E0601\narc: N1_V02N0001 H01E0001\narc: N1_V02N0601 H01E0001\narc: S1_V02S0301 H02E0301\narc: S1_V02S0601 H02E0601\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 S1_V02N0201\narc: V01S0000 S3_V06N0103\narc: W1_H02W0201 E1_H01W0000\narc: E1_H02E0101 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: A0 H00L0000\narc: B0 H02W0101\narc: C0 H00L0100\narc: D0 V02S0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00B0000\narc: M1 H00R0000\narc: M2 V00B0000\narc: M3 H02W0201\narc: M4 V00B0000\narc: M5 H00R0000\narc: M6 V00B0000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1000110010101111\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R6C41:PLC2\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 V02S0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 W1_H02E0601\narc: H00L0000 S1_V02N0201\narc: H00R0000 W1_H02E0601\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: V00B0000 W1_H02E0601\narc: V00T0100 W1_H02E0301\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V01N0001\narc: S1_V02S0001 W3_H06E0003\narc: S3_V06S0003 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: A0 N1_V02S0701\narc: A1 N1_V02S0701\narc: A2 N1_V02S0701\narc: B0 V00B0000\narc: B1 V00B0000\narc: B2 H00R0000\narc: C0 V02S0401\narc: C1 V02S0401\narc: C2 V02S0401\narc: D0 H02E0201\narc: D1 H02E0201\narc: D2 H02E0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00T0100\narc: M1 H00L0000\narc: M2 V00T0100\narc: M3 W1_H02E0201\narc: M4 V00T0100\narc: M5 H00L0000\narc: M6 V00T0100\narc: W1_H02W0301 F3\nword: SLICEA.K0.INIT 1010111100100011\nword: SLICEA.K1.INIT 1010111100100011\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1010111100100011\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R6C42:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0103 W1_H02E0101\narc: H00L0000 H02E0201\narc: H00L0100 H02E0301\narc: H00R0100 H02E0701\narc: N1_V02N0601 H02E0601\narc: S1_V02S0301 E3_H06W0003\narc: V00B0000 H02E0601\narc: V00T0000 H02E0201\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0001 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: A0 H00L0000\narc: A1 H00L0000\narc: A2 V00T0000\narc: B0 H00R0100\narc: B1 H00R0100\narc: B2 H00R0100\narc: C0 H02E0401\narc: C1 H02E0401\narc: C2 H02E0401\narc: D0 W1_H02E0201\narc: D1 W1_H02E0201\narc: D2 W1_H02E0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 H02E0601\narc: M1 H00L0100\narc: M2 H02E0601\narc: M3 H02W0201\narc: M4 V00B0000\narc: M5 H00L0100\narc: M6 V00B0000\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 1010111100100011\nword: SLICEA.K1.INIT 1010111100100011\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1010111100100011\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R6C43:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 E3_H06W0103\narc: H00R0100 H02E0701\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 S3_V06N0003\narc: S1_V02S0301 H06E0003\narc: V00B0100 W1_H02E0501\narc: V00T0000 E1_H02W0001\narc: V00T0100 H02E0101\narc: W1_H02W0201 E1_H02W0701\narc: E1_H02E0501 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: W3_H06W0303 S3_V06N0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: C1 E1_H02W0601\narc: C3 E1_H02W0601\narc: C7 V00T0000\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D3 V02S0001\narc: D7 H02W0201\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR1\narc: W3_H06W0003 Q3\narc: W3_H06W0103 Q1\narc: W3_H06W0203 Q7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R6C44:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0601 V06N0303\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 W1_H02E0401\narc: H00L0000 H02W0001\narc: H00R0100 H02E0501\narc: N1_V02N0301 H06E0003\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0101 E3_H06W0103\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 H01E0001\narc: V00B0100 E1_H02W0701\narc: V00T0000 H02E0201\narc: V00T0100 W1_H02E0101\narc: W1_H02W0201 N1_V02S0201\narc: C3 H00L0000\narc: CE0 H02E0101\narc: CE1 H00R0100\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D3 V02N0001\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: LSR1 E1_H02W0301\narc: M0 V00B0100\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: S1_V02S0401 Q4\narc: V01S0000 Q0\narc: W3_H06W0003 Q3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R6C45:PLC2\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0501 S1_V02N0501\narc: H00L0000 V02S0001\narc: H00L0100 V02N0101\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H02W0601\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 H06E0103\narc: S1_V02S0701 E3_H06W0203\narc: V00T0000 V02S0401\narc: V00T0100 H02E0101\narc: W1_H02W0701 V02S0701\narc: E1_H02E0301 W3_H06E0003\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0303 S3_V06N0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: CE0 H00L0100\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: H01W0100 Q2\narc: LSR0 V00T0100\narc: LSR1 H02W0301\narc: M0 E1_H02W0601\narc: M2 E1_H02W0601\narc: M4 E1_H02W0401\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: S1_V02S0401 Q4\narc: V01S0000 Q0\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R6C46:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 E1_H01W0100\narc: H00L0100 S1_V02N0101\narc: H00R0000 N1_V02S0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 V01N0101\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 E3_H06W0203\narc: V00B0000 W1_H02E0401\narc: V00B0100 V02N0101\narc: V00T0100 E1_H02W0101\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0101 W3_H06E0103\narc: H01W0000 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: N3_V06N0003 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A0 V02N0501\narc: A1 H02W0701\narc: A6 S1_V02N0301\narc: A7 H02W0501\narc: B0 E1_H02W0301\narc: B1 H00R0100\narc: B2 E1_H02W0101\narc: B4 E1_H02W0101\narc: B6 E1_H02W0301\narc: B7 H02W0301\narc: C0 N1_V02S0601\narc: C1 W1_H02E0601\narc: C2 H00L0100\narc: C3 V02N0601\narc: C4 V02N0001\narc: C5 V00T0100\narc: C6 V00B0100\narc: C7 V02S0201\narc: D0 S1_V02N0201\narc: D1 H00R0000\narc: D2 W1_H02E0001\narc: D3 V02S0001\narc: D4 V02S0601\narc: D5 S1_V02N0401\narc: D6 F2\narc: D7 N1_V02S0401\narc: E1_H01E0001 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M2 V00B0000\narc: M4 E1_H01E0101\narc: N1_V01N0001 F7\narc: V01S0000 F4\narc: V01S0100 F6\narc: W3_H06W0003 F0\nword: SLICEA.K0.INIT 1000000010101010\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 1000000010101010\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000001111001111\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICEC.K0.INIT 0000110000111111\nword: SLICEC.K1.INIT 1111000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R6C47:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V02S0401\narc: H00L0100 N1_V02S0301\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0103 S1_V02N0101\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 H02E0501\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: V00T0000 V02S0401\narc: V00T0100 W1_H02E0301\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 V02N0201\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 S1_V02N0601\narc: E1_H01E0101 W3_H06E0203\narc: S1_V02S0101 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A0 H02E0701\narc: A4 F5\narc: A6 W1_H02E0501\narc: A7 H00L0000\narc: B0 V02S0301\narc: B1 N1_V02S0101\narc: B2 H02W0101\narc: B4 N1_V02S0501\narc: B5 V02S0701\narc: B6 E1_H02W0301\narc: B7 V01S0000\narc: C0 V02N0601\narc: C1 V02S0401\narc: C2 V02N0601\narc: C3 H00R0100\narc: C4 H02W0601\narc: C5 V00T0000\narc: C6 V00T0100\narc: C7 H02W0401\narc: D0 N1_V02S0001\narc: D1 V02S0001\narc: D2 V00B0100\narc: D3 N1_V02S0001\narc: D4 V00B0000\narc: D5 H00L0100\narc: D6 H02W0001\narc: D7 E1_H02W0001\narc: E1_H01E0001 F7\narc: E1_H02E0201 F2\narc: E1_H02E0501 F5\narc: E3_H06E0103 F1\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F0\narc: H01W0100 F1\narc: M2 H02E0601\narc: N1_V01N0001 F5\narc: N1_V01N0101 F5\narc: N1_V02N0101 F1\narc: N1_V02N0301 F1\narc: S3_V06S0103 F1\narc: S3_V06S0303 F5\narc: V01S0000 F4\narc: V01S0100 F1\narc: W1_H02W0701 F5\nword: SLICEC.K0.INIT 0001010100111111\nword: SLICEC.K1.INIT 1100000000000000\nword: SLICEA.K0.INIT 0001001101011111\nword: SLICEA.K1.INIT 0011000000000000\nword: SLICED.K0.INIT 0000110010101100\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000110000111111\nword: SLICEB.K1.INIT 1111000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R6C48:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 E1_H02W0201\narc: H00R0100 H02W0501\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 W1_H02E0601\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 H02W0601\narc: V00B0000 V02S0201\narc: V00B0100 W1_H02E0501\narc: V00T0000 N1_V02S0601\narc: V00T0100 V02N0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0601 V06N0303\narc: S1_V02S0001 W3_H06E0003\narc: W3_H06W0303 S3_V06N0303\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0303\narc: A0 S1_V02N0701\narc: A4 F5\narc: A6 F7\narc: B0 F1\narc: B4 H02E0101\narc: B5 N1_V02S0701\narc: B6 V02N0501\narc: B7 N1_V02S0701\narc: C0 H00L0000\narc: C1 H00R0100\narc: C4 S1_V02N0201\narc: C5 H02E0401\narc: C6 V00T0000\narc: C7 H02E0401\narc: CE1 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 V00B0100\narc: D4 E1_H02W0201\narc: D5 V00B0000\narc: D6 H02E0001\narc: D7 V00B0000\narc: E1_H01E0001 F4\narc: E1_H02E0101 F1\narc: E1_H02E0501 F5\narc: E1_H02E0701 F7\narc: E3_H06E0103 F1\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR1 H02E0301\narc: M2 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F1\narc: N1_V01N0101 F5\narc: N1_V02N0701 F7\narc: S1_V02S0301 F1\narc: S1_V02S0701 F5\narc: S3_V06S0103 F1\narc: S3_V06S0203 F7\narc: S3_V06S0303 F5\narc: V01S0100 Q2\narc: W1_H02W0301 F1\narc: W1_H02W0401 F6\narc: W1_H02W0501 F5\narc: W1_H02W0701 F7\narc: W3_H06W0003 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0001010100111111\nword: SLICEC.K1.INIT 0000001100000000\nword: SLICEA.K0.INIT 1000000010101010\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0001010100111111\nword: SLICED.K1.INIT 0000000000001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R6C49:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0303 W1_H02E0501\narc: H00R0000 V02N0401\narc: H00R0100 H02E0501\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 V02N0301\narc: V00T0000 V02S0601\narc: V00T0100 E1_H02W0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 S3_V06N0303\narc: S1_V02S0701 W3_H06E0203\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0103 E1_H02W0101\narc: E3_H06E0203 W3_H06E0103\narc: A0 V02N0501\narc: A1 W1_H02E0501\narc: A5 H02E0701\narc: B0 H02E0101\narc: B1 H00R0100\narc: B5 H02W0101\narc: B6 H02E0301\narc: C0 V02N0401\narc: C1 S1_V02N0601\narc: C5 V00T0000\narc: C6 V00T0000\narc: C7 V00B0100\narc: CE1 V02S0201\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 H00R0000\narc: D5 N1_V02S0601\narc: D6 H02E0001\narc: D7 N1_V02S0601\narc: E1_H02E0301 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: LSR0 H02W0301\narc: M2 V00T0100\narc: M6 H02W0401\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F5\narc: S1_V02S0201 Q2\narc: W3_H06W0003 F0\narc: W3_H06W0303 F6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1000000010101010\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000001111001111\nword: SLICED.K1.INIT 1111000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R6C4:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0501 V06S0303\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 H02W0001\narc: H00L0100 E1_H02W0301\narc: H00R0000 V02N0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0003\narc: S1_V02S0001 H06W0003\narc: S1_V02S0101 V01N0101\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 S3_V06N0303\narc: V00B0000 H02W0401\narc: V00B0100 V02N0301\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02N0501\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 V02N0101\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0701 E1_H02W0701\narc: A7 N1_V01N0101\narc: B1 H02E0101\narc: B7 V00T0000\narc: C1 E1_H01W0000\narc: C7 S1_V02N0201\narc: CE1 H00L0000\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 H00R0000\narc: D7 V02N0401\narc: E1_H01E0101 Q2\narc: E3_H06E0003 Q0\narc: F0 F5A_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q0\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 V00B0000\narc: M2 H02E0601\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q4\narc: S1_V02S0201 Q0\narc: V01S0000 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111000011001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R6C50:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 E1_H01W0000\narc: H00L0000 H02W0201\narc: H00L0100 H02E0301\narc: H00R0100 H02W0701\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0501 S1_V02N0401\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H06E0203\narc: S3_V06S0103 N1_V01S0100\narc: V00B0000 H02E0401\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02W0001\narc: V00T0100 H02E0101\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 V06N0303\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0701 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: W3_H06W0103 S3_V06N0103\narc: W3_H06W0203 E1_H02W0401\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A1 W1_H02E0701\narc: A3 V02N0501\narc: A6 H02W0501\narc: A7 N1_V01N0101\narc: B1 H00R0100\narc: B3 N1_V02S0101\narc: B6 V02S0701\narc: B7 F1\narc: C1 V02N0601\narc: C3 S1_V02N0601\narc: C6 V00T0000\narc: C7 V00T0100\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0201\narc: D3 V02N0201\narc: D6 V02N0401\narc: D7 H00L0100\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR1 V00B0000\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 F3\narc: S3_V06S0303 F6\narc: V01S0000 F7\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0000110010101100\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R6C51:PLC2\narc: E1_H02E0501 H01E0101\narc: H00L0100 V02S0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 E1_H02W0701\narc: H01W0000 E3_H06W0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0301 V01N0101\narc: S1_V02S0501 H01E0101\narc: S1_V02S0701 H02W0701\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 W1_H02E0401\narc: V00B0100 H02E0501\narc: V00T0000 V02N0601\narc: V00T0100 V02S0701\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 N1_V02S0701\narc: H01W0100 W3_H06E0303\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0003\narc: C3 H02E0601\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 E1_H02W0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: E1_H01E0001 F3\narc: F3 F3_SLICE\narc: LSR0 E1_H02W0301\narc: LSR1 V00B0000\narc: M0 E1_H02W0601\narc: M4 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F3\narc: N1_V02N0101 F3\narc: S1_V02S0201 Q0\narc: V01S0100 Q6\narc: W1_H02W0101 F3\narc: W1_H02W0301 Q3\narc: W3_H06W0203 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R6C52:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 W1_H02E0701\narc: H00R0000 V02S0601\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0501 S1_V02N0501\narc: S1_V02S0101 W1_H02E0101\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 W1_H02E0401\narc: V00B0100 V02N0301\narc: V00T0100 V02N0701\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 V01N0101\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: S1_V02S0001 W3_H06E0003\narc: S1_V02S0301 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0203\narc: CE1 H00R0000\narc: CE2 V02S0601\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: H01W0000 Q4\narc: LSR0 V00B0000\narc: LSR1 H02E0501\narc: M2 V00B0100\narc: M4 V00T0100\narc: M6 H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: S3_V06S0303 Q6\narc: V01S0100 Q2\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R6C53:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 E1_H01W0100\narc: H00R0000 H02E0601\narc: H00R0100 V02N0501\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0101 V01N0101\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 H02E0701\narc: V00B0000 S1_V02N0001\narc: V00B0100 E1_H02W0501\narc: V00T0100 H02E0301\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02S0701\narc: E1_H02E0201 W3_H06E0103\narc: H01W0000 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 V00B0100\narc: M2 V00T0100\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: S3_V06S0003 Q0\narc: S3_V06S0103 Q2\narc: S3_V06S0203 Q4\narc: S3_V06S0303 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R6C54:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0201 V06N0103\narc: E1_H02E0401 V06N0203\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 V02N0601\narc: E3_H06E0103 W1_H02E0201\narc: N1_V02N0101 E1_H01W0100\narc: S1_V02S0101 V01N0101\narc: S1_V02S0401 W1_H02E0401\narc: V00B0000 V02S0201\narc: V00T0100 H02W0101\narc: W1_H02W0501 E1_H02W0401\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0701 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: N1_V02N0201 W3_H06E0103\narc: S1_V02S0301 W3_H06E0003\narc: S3_V06S0103 W3_H06E0103\narc: S3_V06S0203 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: A5 V00B0000\narc: B5 V02S0501\narc: C5 V02S0001\narc: CE0 H02E0101\narc: CLK0 G_HPBX0000\narc: D5 V02S0401\narc: F5 F5_SLICE\narc: LSR0 H02E0301\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F5\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R6C55:PLC2\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 H01E0101\narc: H00L0000 V02S0001\narc: H00L0100 V02S0301\narc: H00R0000 H02E0401\narc: H00R0100 V02S0501\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 S1_V02N0401\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 H01E0101\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 H06W0203\narc: V00B0000 V02N0201\narc: V00B0100 V02N0101\narc: V00T0000 H02E0201\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0501 S1_V02N0501\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: A0 V02N0701\narc: A1 H02E0701\narc: A2 V02N0701\narc: A3 V02S0501\narc: B0 H02E0101\narc: B1 H00R0100\narc: B2 H02E0101\narc: B3 H02W0101\narc: B4 V01S0000\narc: C0 F4\narc: C1 H00L0000\narc: C2 H02E0401\narc: C3 V02N0601\narc: C4 V00B0100\narc: C5 V02N0001\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 V00T0100\narc: D2 E1_H02W0001\narc: D3 H00R0000\narc: D4 H00L0100\narc: D5 V00B0000\narc: E1_H01E0001 F1\narc: E1_H02E0301 F3\narc: E1_H02E0401 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: M4 E1_H02W0401\narc: M6 V00T0000\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q6\narc: S1_V02S0401 Q6\narc: S3_V06S0003 F0\narc: S3_V06S0103 F2\narc: S3_V06S0303 Q6\narc: V01S0000 Q6\narc: V01S0100 Q6\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1000000010101010\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 1000101000001010\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000110000111111\nword: SLICEC.K1.INIT 1111000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R6C56:PLC2\narc: H00L0100 H02E0301\narc: N1_V02N0101 H06E0103\narc: N1_V02N0601 H01E0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0501 H02E0501\narc: V00B0100 E1_H02W0701\narc: V00T0000 E1_H02W0001\narc: V00T0100 H02W0101\narc: W1_H02W0101 N1_V02S0101\narc: E1_H02E0101 W3_H06E0103\narc: S1_V02S0701 W3_H06E0203\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: A0 V02N0701\narc: A1 W1_H02E0501\narc: A2 V02N0701\narc: A3 H02E0501\narc: A5 H02E0501\narc: A6 H02W0701\narc: A7 F5\narc: B0 W1_H02E0101\narc: B1 V02S0101\narc: B2 W1_H02E0101\narc: B3 V02S0101\narc: B5 V02S0701\narc: B6 H01E0101\narc: B7 F1\narc: C0 V02S0401\narc: C1 V02N0401\narc: C2 N1_V01S0100\narc: C3 W1_H02E0601\narc: C5 V00T0000\narc: C6 V00T0100\narc: C7 E1_H02W0401\narc: D0 V00B0100\narc: D1 W1_H02E0001\narc: D2 V02S0001\narc: D3 S1_V02N0001\narc: D5 E1_H02W0201\narc: D6 H01W0000\narc: D7 H00L0100\narc: E3_H06E0103 F2\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: N1_V01N0101 F3\narc: S3_V06S0003 F0\nword: SLICEB.K0.INIT 1000000010101010\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000110010101100\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 1000000010101010\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R6C57:PLC2\narc: H00L0100 V02N0101\narc: H00R0000 V02N0601\narc: H00R0100 V02N0501\narc: N1_V02N0401 E1_H01W0000\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0203 H06E0203\narc: V00B0000 W1_H02E0401\narc: V00B0100 S1_V02N0301\narc: V00T0100 H02W0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0701 V02N0701\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A3 W1_H02E0701\narc: B0 V02N0301\narc: B3 H00R0100\narc: B6 V00B0000\narc: C0 N1_V02S0401\narc: C1 W1_H02E0401\narc: C3 V02S0401\narc: C6 W1_H02E0601\narc: C7 W1_H02E0401\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 S1_V02N0001\narc: D3 H00R0000\narc: D6 V02S0401\narc: D7 V02N0601\narc: E1_H01E0001 F3\narc: E1_H01E0101 F6\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: LSR1 V00T0100\narc: M0 E1_H02W0601\narc: M4 V00B0100\narc: M6 E1_H02W0401\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: V01S0100 Q4\narc: W1_H02W0001 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000001111001111\nword: SLICED.K1.INIT 1111000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0000110000111111\nword: SLICEA.K1.INIT 1111000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R6C58:PLC2\narc: S1_V02S0101 W1_H02E0101\narc: V00T0100 V02N0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 H01E0001\narc: W1_H02W0701 H01E0101\narc: H01W0100 W3_H06E0303\narc: S1_V02S0701 W3_H06E0203\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q4\narc: H01W0000 Q4\narc: M4 V00T0100\narc: MUXCLK2 CLK0\narc: S3_V06S0203 Q4\narc: V01S0100 Q4\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R6C59:PLC2\narc: S1_V02S0401 H06E0203\narc: S3_V06S0103 H06E0103\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 H01E0001\narc: E3_H06E0003 W3_H06E0003\n\n.tile R6C5:PLC2\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V02S0501\narc: H00L0100 V02S0101\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0101 H01E0101\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 H06E0303\narc: V00B0000 E1_H02W0601\narc: V00T0000 N1_V02S0601\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 E1_H02W0701\narc: A0 E1_H02W0501\narc: A2 V00B0000\narc: A3 H00L0100\narc: A4 V00T0000\narc: A5 W1_H02E0701\narc: A6 H02E0501\narc: A7 H02W0501\narc: E1_H01E0101 F2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: H01W0100 F6\narc: N1_V01N0001 F4\narc: N1_V02N0301 F3\narc: V01S0000 F7\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 1001011010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R6C60:PLC2\narc: S1_V02S0101 V01N0101\narc: S1_V02S0301 W3_H06E0003\n\n.tile R6C62:PLC2\narc: S1_V02S0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0303\n\n.tile R6C63:PLC2\narc: W3_H06W0003 E3_H06W0303\n\n.tile R6C64:PLC2\narc: E3_H06E0103 W3_H06E0103\n\n.tile R6C65:PLC2\narc: E3_H06E0003 W3_H06E0003\n\n.tile R6C68:PLC2\narc: E3_H06E0103 W3_H06E0003\n\n.tile R6C69:PLC2\narc: W3_H06W0303 E1_H02W0601\n\n.tile R6C6:PLC2\narc: H00L0000 N1_V02S0201\narc: H00R0000 H02E0401\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 S1_V02N0101\narc: S1_V02S0001 N1_V01S0000\narc: S3_V06S0103 H01E0101\narc: V00T0000 W1_H02E0001\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 E1_H02W0701\narc: A0 H00R0000\narc: A1 H00L0000\narc: A2 V02N0501\narc: A3 V00T0000\narc: A4 N1_V01S0100\narc: A5 V02S0101\narc: A6 H02E0501\narc: A7 V02N0101\narc: E1_H01E0001 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: N1_V01N0101 F4\narc: N3_V06N0003 F3\narc: S1_V02S0201 F2\narc: S1_V02S0501 F7\narc: V01S0000 F0\narc: W3_H06W0303 F5\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 0101101010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R6C70:PLC2\narc: E1_H02E0101 W3_H06E0103\n\n.tile R6C7:PLC2\narc: H00L0000 V02S0201\narc: H00L0100 E1_H02W0101\narc: H00R0000 V02S0401\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 S3_V06N0303\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 E1_H02W0201\narc: V00B0000 V02S0001\narc: V00T0000 E1_H02W0201\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0203 E1_H02W0401\narc: W3_H06W0303 E1_H02W0501\narc: A0 H00L0100\narc: A1 H00L0000\narc: A2 V02N0701\narc: A3 V00B0000\narc: A4 N1_V01S0100\narc: A5 V00T0000\narc: A6 H00R0000\narc: A7 H02W0501\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: N1_V01N0001 F3\narc: N1_V02N0101 F1\narc: N1_V02N0601 F4\narc: V01S0000 F2\narc: V01S0100 F7\narc: W1_H02W0701 F5\narc: W3_H06W0003 F0\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 0101101010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R6C8:PLC2\narc: E1_H02E0701 V06S0203\narc: H00L0000 N1_V02S0201\narc: H00L0100 H02W0301\narc: H00R0000 V02N0601\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0501 H02W0501\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0101 E1_H02W0101\narc: V00B0000 H02W0601\narc: V00T0000 H02W0001\narc: W1_H02W0001 V02N0001\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 E1_H02W0601\narc: A0 H00L0100\narc: A1 N1_V02S0701\narc: A2 V02N0701\narc: A3 V00T0000\narc: A4 V02S0301\narc: A5 V00B0000\narc: A6 H00L0000\narc: A7 H00R0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F6\narc: N1_V02N0601 F4\narc: S1_V02S0201 F2\narc: S1_V02S0701 F7\narc: S3_V06S0003 F0\narc: V01S0000 F1\narc: W3_H06W0003 F3\narc: W3_H06W0303 F5\nword: SLICED.K0.INIT 0101101010101010\nword: SLICED.K1.INIT 0101101010101010\nword: SLICEB.K0.INIT 0101101010101010\nword: SLICEB.K1.INIT 0101101010101010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nword: SLICEC.K0.INIT 0101101010101010\nword: SLICEC.K1.INIT 0101101010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R6C9:PLC2\narc: H00R0000 V02N0401\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0601\narc: V00B0000 H02W0401\narc: V00T0100 H02W0301\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0201 W3_H06E0103\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0303 V06N0303\narc: A0 H00R0000\narc: A1 H02E0701\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: E3_H06E0303 Q6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: H01W0100 F1\narc: LSR1 V00B0100\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: V00B0100 F5\narc: W3_H06W0003 F0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 0101101010101010\nword: SLICEA.K1.INIT 0101101010101010\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R7C10:PLC2\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0701 V06S0203\narc: H00R0000 H02E0601\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 S1_V02N0601\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 H06W0103\narc: V00B0000 V02S0201\narc: V00B0100 V02N0101\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 N1_V01S0000\narc: H01W0000 W3_H06E0103\narc: A0 V02S0501\narc: A2 V02N0701\narc: A3 V00B0000\narc: A4 V02S0101\narc: A5 V02N0301\narc: A6 H02E0501\narc: A7 H00R0000\narc: B2 V01N0001\narc: B3 H02W0101\narc: B4 S1_V02N0501\narc: B5 V00B0100\narc: B6 V02S0701\narc: B7 V02N0501\narc: E1_H01E0001 F6\narc: E1_H01E0101 F3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: S1_V02S0401 F4\narc: S1_V02S0501 F7\narc: S1_V02S0701 F5\narc: V01S0100 F2\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R7C11:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0701 V01N0101\narc: H00L0000 V02N0201\narc: H00R0000 V02N0401\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 H06W0203\narc: S1_V02S0601 V01N0001\narc: V00B0000 H02E0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 N1_V02S0601\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0401 V06N0203\narc: E3_H06E0103 W3_H06E0103\narc: A0 H02E0701\narc: A1 H00R0000\narc: A2 V01N0101\narc: A3 V00T0000\narc: A4 N1_V02S0101\narc: A5 V00B0000\narc: A6 V02N0301\narc: A7 H00L0000\narc: B0 V02N0101\narc: B1 S1_V02N0301\narc: B2 H00R0100\narc: B3 V02S0301\narc: B4 S1_V02N0501\narc: B5 V02S0701\narc: B6 N1_V01S0000\narc: B7 V00B0100\narc: E1_H01E0101 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V01N0001 F5\narc: N1_V02N0101 F3\narc: N1_V02N0601 F6\narc: S1_V02S0001 F2\narc: S1_V02S0301 F1\narc: S1_V02S0701 F7\narc: V01S0000 F0\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R7C12:PLC2\narc: H00L0000 N1_V02S0201\narc: H00L0100 V02N0101\narc: H00R0000 N1_V02S0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 H02W0201\narc: N1_V02N0401 E3_H06W0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0701 H01E0101\narc: V00B0000 N1_V02S0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02E0001\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 N1_V02S0701\narc: A1 H00L0100\narc: A2 V02N0701\narc: A3 V00T0000\narc: A4 V00B0000\narc: A5 V02S0301\narc: A6 H00R0000\narc: A7 H00L0000\narc: B0 H00R0100\narc: B1 S1_V02N0101\narc: B2 V02N0301\narc: B3 V02S0101\narc: B4 V02N0501\narc: B5 N1_V02S0501\narc: B6 N1_V01S0000\narc: B7 V00B0100\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: N1_V01N0001 F6\narc: N1_V02N0101 F3\narc: N1_V02N0701 F5\narc: S1_V02S0101 F1\narc: S1_V02S0501 F7\narc: S1_V02S0601 F4\narc: V01S0000 F2\narc: V01S0100 F0\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R7C13:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 E1_H01W0100\narc: H00L0000 V02N0001\narc: H00R0000 N1_V02S0601\narc: H00R0100 S1_V02N0701\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0601 E3_H06W0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02W0701\narc: V00T0000 W1_H02E0201\narc: V00T0100 E1_H02W0301\narc: W1_H02W0201 E3_H06W0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0303\narc: A0 H00R0000\narc: A1 H00L0000\narc: A2 V00T0000\narc: A3 V02S0501\narc: A4 V00T0100\narc: A5 V00B0000\narc: A6 V02N0101\narc: A7 E1_H02W0501\narc: B0 H00R0100\narc: B1 S1_V02N0101\narc: B2 V02N0301\narc: B3 H02W0301\narc: B4 V00B0100\narc: B5 S1_V02N0501\narc: B6 V02N0501\narc: B7 H02W0101\narc: E1_H01E0001 F3\narc: E1_H01E0101 F2\narc: E1_H02E0601 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: S1_V02S0001 F0\narc: S1_V02S0101 F1\narc: S1_V02S0401 F6\narc: S1_V02S0501 F5\narc: V01S0000 F7\nword: SLICED.K0.INIT 0110011010101010\nword: SLICED.K1.INIT 0110011010101010\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 0110011010101010\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0110011010101010\nword: SLICEC.K1.INIT 0110011010101010\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R7C14:PLC2\narc: E1_H02E0401 N1_V01S0000\narc: H00L0100 H02E0101\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0601 H02E0601\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0501 H01E0101\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 H02W0701\narc: W1_H02W0101 V01N0101\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 H00L0100\narc: A1 V02N0501\narc: B0 V01N0001\narc: B1 V02N0101\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D7 H02E0201\narc: E3_H06E0103 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR0 H02E0501\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: S1_V02S0001 F0\narc: V01S0000 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111100001111\nword: SLICEA.K0.INIT 0110011010101010\nword: SLICEA.K1.INIT 0110011010101010\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000001010\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R7C15:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 S1_V02N0201\narc: N1_V02N0101 V01N0101\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H06W0203\narc: S1_V02S0601 E1_H02W0601\narc: V00B0100 H02W0501\narc: V00T0000 N1_V02S0401\narc: W1_H02W0201 V02S0201\narc: W1_H02W0501 V01N0101\narc: W1_H02W0701 N1_V02S0701\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: C1 H00L0000\narc: C3 V02S0601\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D3 V02S0001\narc: E3_H06E0103 F1\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: M6 V00T0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V02N0401 Q6\narc: S1_V02S0301 F1\narc: S3_V06S0103 F1\narc: V00T0100 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111111100001111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R7C16:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0303 V06N0303\narc: H00L0000 V02S0201\narc: H00R0000 S1_V02N0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 H06W0103\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H06W0303\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 S3_V06N0303\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 H06W0203\narc: V00B0000 V02S0001\narc: V00B0100 H02W0701\narc: V00T0000 V02N0401\narc: V00T0100 V02S0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0501 S3_V06N0303\narc: A0 E1_H01E0001\narc: A2 H00L0100\narc: A4 N1_V01N0101\narc: A7 E1_H01W0000\narc: B0 H00R0100\narc: B1 E1_H01W0100\narc: B2 H00R0000\narc: B3 V02S0301\narc: B4 S1_V02N0501\narc: B5 E1_H02W0301\narc: B7 H02W0101\narc: C0 V02S0601\narc: C1 H00L0000\narc: C2 V02S0401\narc: C3 N1_V01N0001\narc: C4 W1_H02E0401\narc: C5 V01N0101\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 V00T0100\narc: D2 E1_H02W0201\narc: D3 V00B0100\narc: D4 H02E0201\narc: D5 V00B0000\narc: D7 H02W0001\narc: E1_H01E0001 Q1\narc: E1_H01E0101 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q3\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q5\narc: S1_V02S0001 F2\narc: V01S0100 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 0011111111111111\nword: SLICEA.K0.INIT 0000000000000001\nword: SLICEA.K1.INIT 0011111111111111\nword: SLICEB.K0.INIT 0000000000000001\nword: SLICEB.K1.INIT 0011111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R7C17:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 V02N0201\narc: H00R0000 V02N0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0401 H06W0203\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0101 H01E0101\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 H02W0601\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 H02E0101\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 N1_V02S0701\narc: W1_H02W0201 W3_H06E0103\narc: A1 E1_H01E0001\narc: B1 V00T0000\narc: C1 H00R0100\narc: CE1 H00R0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: E1_H01E0001 Q6\narc: F1 F1_SLICE\narc: H01W0000 Q4\narc: H01W0100 F1\narc: LSR0 V00T0100\narc: LSR1 V00B0100\narc: M2 H02W0601\narc: M4 V00B0000\narc: M6 H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V02N0201 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R7C18:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 N1_V02S0601\narc: E3_H06E0203 S3_V06N0203\narc: H00L0100 V02N0301\narc: H00R0000 V02N0401\narc: H01W0000 E3_H06W0103\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 W1_H02E0301\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: V00T0100 E1_H02W0301\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0203 E3_H06W0103\narc: CE0 H00R0000\narc: CE1 H00L0100\narc: CE2 H00L0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: H01W0100 Q0\narc: LSR0 V00B0100\narc: LSR1 V00B0000\narc: M0 V00T0000\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V02N0401 Q6\narc: V00T0000 Q2\narc: W1_H02W0601 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R7C19:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0100 V02N0301\narc: H00R0000 H02W0601\narc: H00R0100 W1_H02E0501\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 N1_V01S0100\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02W0401\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02W0001\narc: V00T0100 V02N0701\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 E3_H06W0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A1 V01N0101\narc: A5 W1_H02E0701\narc: A6 V02S0301\narc: B1 H02E0301\narc: B2 H00L0000\narc: B5 W1_H02E0101\narc: B6 H02W0101\narc: B7 S1_V02N0701\narc: C1 H00L0100\narc: C2 V02N0601\narc: C3 H02E0601\narc: C5 V00T0100\narc: C6 V00T0000\narc: C7 S1_V02N0201\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 S1_V02N0001\narc: D3 H02W0201\narc: D5 H00R0100\narc: D6 E1_H01W0100\narc: D7 V02N0401\narc: E1_H01E0001 F3\narc: E1_H01E0101 F7\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H01W0000 F1\narc: H01W0100 F5\narc: LSR0 V00B0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N3_V06N0003 F3\narc: N3_V06N0103 Q2\narc: V01S0000 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0011110011001100\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 0001001100000000\nword: SLICED.K1.INIT 1100000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\n\n.tile R7C20:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0601 V02N0601\narc: H00L0000 H02W0201\narc: H00L0100 E1_H02W0101\narc: H00R0100 V02S0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 E3_H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02W0701\narc: V00T0000 H02W0001\narc: V00T0100 H02W0101\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 H01E0001\narc: W1_H02W0201 W3_H06E0103\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0103\narc: A1 V01N0101\narc: A3 S1_V02N0501\narc: A7 H00L0000\narc: B0 F1\narc: B1 V02N0301\narc: B2 F3\narc: B3 V01N0001\narc: B5 V02N0501\narc: B7 E1_H02W0301\narc: C0 W1_H02E0401\narc: C1 H02W0401\narc: C2 H00L0100\narc: C3 H02W0401\narc: C5 S1_V02N0201\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 S1_V02N0001\narc: D2 N1_V02S0201\narc: D3 S1_V02N0001\narc: D5 V00B0000\narc: D7 H00R0100\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F5\narc: S3_V06S0103 Q2\narc: W3_H06W0003 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100000000000000\nword: SLICEA.K0.INIT 0011111111111111\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0011111111111111\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R7C21:PLC2\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0203 W1_H02E0401\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0103 N1_V02S0201\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02N0101\narc: V00T0000 N1_V02S0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 E1_H02W0701\narc: H01W0000 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: A3 E1_H01E0001\narc: B3 E1_H02W0301\narc: C3 V02N0601\narc: C5 V00T0000\narc: C6 V02N0001\narc: C7 F6\narc: CE0 V02N0201\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: D4 N1_V02S0401\narc: D5 H02E0201\narc: D6 N1_V02S0401\narc: D7 V00B0000\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F5\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0100 Q6\narc: LSR0 H02W0501\narc: LSR1 V00T0100\narc: M0 H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q0\narc: S1_V02S0101 F3\narc: S3_V06S0303 Q6\narc: V01S0000 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000011111111\nword: SLICEC.K1.INIT 0000000000001111\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 1111111111110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R7C22:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V02S0501\narc: E1_H02E0701 V02S0701\narc: H00L0000 V02N0001\narc: H00R0100 V02N0701\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 V01N0101\narc: S1_V02S0501 V01N0101\narc: S3_V06S0103 H06W0103\narc: V00B0100 S1_V02N0101\narc: V00T0000 S1_V02N0401\narc: V00T0100 V02S0701\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V02S0501\narc: N1_V02N0501 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: A3 V00B0000\narc: B3 H02W0101\narc: C3 H00R0100\narc: CE0 H00L0000\narc: CE2 H00L0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: F3 F3_SLICE\narc: H01W0000 Q4\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 H02E0601\narc: M4 V00T0000\narc: M6 N1_V01N0101\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q4\narc: V00B0000 Q6\narc: W1_H02W0101 F3\narc: W1_H02W0201 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R7C23:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 V01N0101\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 S3_V06N0303\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0201 V01N0001\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02E0701\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02S0701\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0701 E1_H02W0701\narc: N1_V02N0701 W3_H06E0203\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H00R0100\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: E1_H02E0001 Q0\narc: E1_H02E0201 Q2\narc: E1_H02E0601 Q6\narc: LSR0 H02E0501\narc: LSR1 V00B0100\narc: M0 V00B0000\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R7C24:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 E3_H06W0103\narc: H00R0000 S1_V02N0601\narc: H00R0100 H02W0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0401 S1_V02N0401\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0601 N1_V02S0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 V01N0101\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0103\narc: A0 H00L0100\narc: A2 E1_H01E0001\narc: A3 H02E0501\narc: A4 N1_V01N0101\narc: A7 H02E0501\narc: B0 H01W0100\narc: B1 H01W0100\narc: B2 F3\narc: B3 V02N0101\narc: B4 V01S0000\narc: B7 V01S0000\narc: C0 N1_V01S0100\narc: C1 H00L0100\narc: C2 N1_V01N0001\narc: C3 E1_H01W0000\narc: C4 H02E0601\narc: C5 E1_H01E0101\narc: C7 V00B0100\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 S1_V02N0601\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 V00T0100\narc: D2 N1_V01S0000\narc: D3 H02W0001\narc: D4 H02E0201\narc: D5 V01N0001\narc: D7 V01N0001\narc: E1_H01E0001 Q7\narc: E1_H01E0101 Q5\narc: E3_H06E0103 Q2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 Q1\narc: H01W0100 Q5\narc: LSR0 W1_H02E0501\narc: LSR1 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F0\narc: N1_V01N0101 Q5\narc: N1_V02N0601 F4\narc: N1_V02N0701 Q5\narc: S1_V02S0001 Q2\narc: V00B0100 Q7\narc: V01S0000 Q1\narc: V01S0100 Q1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111111100001\nword: SLICEC.K0.INIT 0011101101111111\nword: SLICEC.K1.INIT 1111111100001111\nword: SLICEA.K0.INIT 1010111010111111\nword: SLICEA.K1.INIT 1111111111000011\nword: SLICEB.K0.INIT 0010101001111111\nword: SLICEB.K1.INIT 0011101101111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R7C25:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V02S0601\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 H02E0201\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E3_H06W0303\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0001 N1_V02S0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 N1_V02S0201\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0601 N1_V02S0301\narc: V00B0100 V02S0301\narc: V00T0000 V02S0601\narc: V00T0100 V02N0501\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0501 V02S0501\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A5 V00B0000\narc: B5 V02N0501\narc: C5 V02N0001\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D5 V02N0601\narc: F5 F5_SLICE\narc: H01W0000 Q0\narc: LSR0 V00T0000\narc: LSR1 V00B0100\narc: M0 V00T0100\narc: M2 H02W0601\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: N1_V02N0401 Q6\narc: V00B0000 Q6\narc: W1_H02W0001 Q2\narc: W1_H02W0701 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R7C26:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0601 N1_V01S0000\narc: H00L0100 H02E0301\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 E3_H06W0003\narc: S1_V02S0401 H01E0001\narc: S1_V02S0601 E1_H01W0000\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: A2 V02S0501\narc: A4 V00T0100\narc: B0 V02S0101\narc: B2 H02E0301\narc: B3 E1_H02W0101\narc: B4 V00B0100\narc: B5 H02E0301\narc: C0 H00L0100\narc: C1 H00R0100\narc: C2 V02N0601\narc: C3 E1_H02W0601\narc: C4 V02S0201\narc: C5 E1_H01E0101\narc: C6 V00B0100\narc: C7 V00B0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 H00R0000\narc: D2 S1_V02N0001\narc: D3 H02W0001\narc: D4 H02E0001\narc: D5 E1_H01W0100\narc: D6 V00B0000\narc: D7 V00B0000\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: E1_H02E0401 F4\narc: E1_H02E0701 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F2\narc: H00R0000 Q6\narc: H00R0100 Q7\narc: H01W0100 F3\narc: LSR0 H02W0501\narc: LSR1 H02W0301\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q3\narc: S1_V02S0001 F0\narc: S1_V02S0501 Q7\narc: S3_V06S0203 F4\narc: V00B0000 Q6\narc: V00B0100 Q7\narc: V00T0100 Q3\narc: V01S0000 F1\narc: V01S0100 F1\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 1111000000001111\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0000000000101111\nword: SLICEB.K1.INIT 0011000000000000\nword: SLICEA.K0.INIT 0000110000000000\nword: SLICEA.K1.INIT 0000000011110000\nword: SLICEC.K0.INIT 1100001111001011\nword: SLICEC.K1.INIT 0000001100110011\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\n\n.tile R7C27:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 N1_V01S0100\narc: H00R0000 W1_H02E0601\narc: H00R0100 W1_H02E0501\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0601 H02E0601\narc: S1_V02S0201 W1_H02E0201\narc: V00B0000 V02S0001\narc: V00B0100 H02E0701\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 V06N0303\narc: E3_H06E0303 W3_H06E0203\narc: A3 H02W0501\narc: B0 H02W0101\narc: B3 H00L0000\narc: B4 S1_V02N0701\narc: B5 V01S0000\narc: B6 H02W0101\narc: C0 N1_V01N0001\narc: C1 H00R0100\narc: C3 N1_V01N0001\narc: C4 V02N0201\narc: C5 H01E0001\narc: C6 V00T0000\narc: C7 E1_H01E0101\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 Q0\narc: D1 H00R0000\narc: D2 Q2\narc: D3 V00B0100\narc: D4 V02N0401\narc: D5 V00B0000\narc: D6 H02W0001\narc: D7 V02S0601\narc: E1_H01E0001 Q0\narc: E1_H01E0101 Q7\narc: E1_H02E0201 Q2\narc: E1_H02E0401 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q0\narc: H00L0100 F3\narc: H01W0000 F4\narc: H01W0100 F4\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 F5\narc: N1_V02N0001 Q0\narc: N1_V02N0201 Q2\narc: N1_V02N0301 F1\narc: V00T0000 Q2\narc: V00T0100 F1\narc: V01S0000 F4\narc: V01S0100 F6\narc: W1_H02W0001 Q2\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 1111111011111111\nword: SLICED.K0.INIT 1111111100110000\nword: SLICED.K1.INIT 0000111111110000\nword: SLICEC.K0.INIT 0000001100000000\nword: SLICEC.K1.INIT 1111111111000000\nword: SLICEA.K0.INIT 0011111111000000\nword: SLICEA.K1.INIT 1111111111110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R7C28:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0501 V02S0501\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02W0601\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H01E0101\narc: S1_V02S0501 N1_V01S0100\narc: S3_V06S0003 H06W0003\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02N0301\narc: V00T0000 V02S0601\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 H01E0001\narc: E3_H06E0003 W3_H06E0003\narc: A0 E1_H01E0001\narc: A1 H02E0701\narc: A2 H02E0701\narc: A4 H02E0501\narc: A5 V02S0101\narc: B0 N1_V02S0101\narc: B1 H00R0100\narc: B2 H02E0301\narc: B3 H00L0000\narc: B4 E1_H02W0301\narc: B5 V01S0000\narc: C0 S1_V02N0601\narc: C1 H00L0100\narc: C2 H02E0401\narc: C3 S1_V02N0401\narc: C4 V00T0100\narc: C5 V02N0201\narc: C6 V02S0201\narc: C7 W1_H02E0401\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 S1_V02N0201\narc: D2 H00R0000\narc: D3 H02W0001\narc: D4 V02N0601\narc: D5 V00B0000\narc: D6 H00R0100\narc: D7 W1_H02E0201\narc: E1_H01E0001 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0100 F7\narc: H01W0100 Q5\narc: LSR0 V00T0000\narc: LSR1 H02W0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V02N0001 F0\narc: N3_V06N0003 F3\narc: N3_V06N0203 F4\narc: S3_V06S0303 F6\narc: V01S0000 F7\nword: SLICEC.K0.INIT 1010001110101111\nword: SLICEC.K1.INIT 0111000001110111\nword: SLICEA.K0.INIT 1010001110101111\nword: SLICEA.K1.INIT 0111000001110111\nword: SLICEB.K0.INIT 1010000011101100\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0000111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R7C29:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 V02N0501\narc: H00L0000 V02S0001\narc: H00R0000 H02W0601\narc: H00R0100 H02E0701\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 H06W0003\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 N1_V02S0601\narc: S3_V06S0003 H06W0003\narc: S3_V06S0103 N1_V01S0100\narc: S3_V06S0203 H06W0203\narc: V00B0000 V02N0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02S0601\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0301 V02S0301\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: A6 H00L0000\narc: A7 N1_V01N0101\narc: B1 V00B0000\narc: B6 V00B0000\narc: B7 H02E0301\narc: C1 E1_H02W0601\narc: C6 S1_V02N0001\narc: C7 V02S0201\narc: CE1 H00R0100\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D6 W1_H02E0001\narc: D7 H02E0001\narc: E1_H01E0101 Q4\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F6\narc: LSR0 V00T0000\narc: LSR1 H02E0501\narc: M2 V00B0100\narc: M4 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q2\narc: N3_V06N0103 F1\narc: S1_V02S0401 Q4\narc: V01S0000 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111110000001100\nword: SLICED.K0.INIT 0001010100111111\nword: SLICED.K1.INIT 0100000011000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R7C2:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 E1_H01W0000\narc: H00R0000 V02N0601\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 E3_H06W0303\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0001\narc: V00B0100 H02W0501\narc: A5 V00T0000\narc: B5 V01S0000\narc: C5 E1_H02W0601\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D5 V02N0401\narc: E1_H02E0701 F5\narc: F5 F5_SLICE\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: M0 V00B0100\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: V00T0000 Q2\narc: V01S0000 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R7C30:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0501 E1_H01W0100\narc: E3_H06E0103 V01N0101\narc: H00L0000 V02N0201\narc: H00R0100 H02W0701\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 H02W0201\narc: S1_V02S0701 H06W0203\narc: V00B0100 V02S0301\narc: V00T0100 V02N0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 H01E0101\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: CE1 H00R0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: E3_H06E0303 Q6\narc: H01W0000 Q2\narc: H01W0100 Q6\narc: M2 V00B0100\narc: M6 V00T0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0001 Q2\narc: S3_V06S0103 Q2\narc: V01S0000 Q2\narc: W3_H06W0103 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R7C31:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 N1_V01S0100\narc: E3_H06E0003 W1_H02E0301\narc: H00L0000 H02W0201\narc: H00R0000 V02N0401\narc: H00R0100 V02N0501\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0301 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 V02S0301\narc: V00T0100 N1_V02S0501\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0401 H01E0001\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0601 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A1 V02N0701\narc: A2 V00B0000\narc: B1 V01N0001\narc: B2 V01N0001\narc: C1 H00L0000\narc: C2 H00L0000\narc: CE2 H00R0100\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H02W0001\narc: D2 H02W0001\narc: E1_H01E0001 F1\narc: E3_H06E0303 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 Q6\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: M4 V00T0100\narc: M6 H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V00B0000 Q4\narc: V01S0100 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010001011110011\nword: SLICEB.K0.INIT 1010001011110011\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R7C32:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0501 V01N0101\narc: E1_H02E0601 V01N0001\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0103 W1_H02E0101\narc: H00L0100 E1_H02W0101\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 S1_V02N0501\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0501 E3_H06W0303\narc: V00B0000 V02N0001\narc: V00B0100 V02N0301\narc: V00T0000 H02E0001\narc: V00T0100 V02S0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0303\narc: A1 H00R0000\narc: A2 N1_V02S0501\narc: A3 N1_V02S0501\narc: A5 W1_H02E0501\narc: B1 V00T0000\narc: B2 H02E0301\narc: B3 H02E0301\narc: B5 V02N0701\narc: C1 V02S0601\narc: C2 V02S0601\narc: C3 V02S0601\narc: C5 V02N0201\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D2 S1_V02N0001\narc: D3 S1_V02N0001\narc: D5 V00B0000\narc: E1_H01E0101 Q6\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: M0 V00T0100\narc: M1 H00L0100\narc: M2 V00T0100\narc: M4 V00B0100\narc: M6 H02W0401\narc: MUXCLK3 CLK0\narc: N1_V02N0301 F1\narc: N1_V02N0601 F4\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010001011110011\nword: SLICEB.K0.INIT 1010001011110011\nword: SLICEB.K1.INIT 1010001011110011\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1010001001010001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R7C33:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 H01E0101\narc: H00R0000 H02E0401\narc: H00R0100 H02W0701\narc: H01W0000 E3_H06W0103\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 H01E0101\narc: N3_V06N0203 S1_V02N0401\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 V01N0101\narc: V00B0000 V02N0001\narc: V00T0000 V02N0601\narc: V00T0100 V02N0701\narc: V01S0100 S3_V06N0303\narc: W1_H02W0401 V06N0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0203 E3_H06W0203\narc: A1 H00R0000\narc: A5 V00T0100\narc: A6 H02E0701\narc: A7 H00L0000\narc: B1 V00B0000\narc: B5 H02E0301\narc: B6 W1_H02E0101\narc: B7 V02N0501\narc: C1 V02N0401\narc: C5 V02N0201\narc: C6 S1_V02N0201\narc: C7 V02S0201\narc: CE1 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D5 H02E0201\narc: D6 W1_H02E0201\narc: D7 H02E0001\narc: E1_H01E0101 F1\narc: E1_H02E0201 Q2\narc: E3_H06E0203 F4\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: M2 V00T0000\narc: M4 E1_H01E0101\narc: MUXCLK1 CLK0\narc: N1_V01N0001 F4\narc: N1_V01N0101 Q2\narc: N1_V02N0601 F6\narc: N1_V02N0701 F7\narc: S1_V02S0001 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000101011001111\nword: SLICED.K0.INIT 1100010011110101\nword: SLICED.K1.INIT 1100111101000101\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1101000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R7C34:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 E1_H01W0100\narc: H00L0100 V02N0101\narc: H00R0000 W1_H02E0601\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 N1_V01S0000\narc: V00B0000 V02N0001\narc: V00B0100 V02S0101\narc: V00T0000 V02S0601\narc: V00T0100 H02E0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 V02N0101\narc: W1_H02W0701 V02N0701\narc: E3_H06E0003 W3_H06E0003\narc: A1 H02E0501\narc: A2 H02E0501\narc: A3 H02E0501\narc: A4 H02W0701\narc: A5 H02W0501\narc: A7 V00T0100\narc: B1 W1_H02E0101\narc: B2 W1_H02E0101\narc: B3 W1_H02E0101\narc: B4 S1_V02N0701\narc: B5 H02E0101\narc: B7 V02S0701\narc: C1 N1_V01S0100\narc: C2 N1_V01S0100\narc: C3 N1_V01S0100\narc: C4 E1_H01E0101\narc: C5 V00T0000\narc: C7 V00T0000\narc: D1 V02N0001\narc: D2 V02N0001\narc: D3 V02N0001\narc: D4 H01W0000\narc: D5 V00B0000\narc: D7 H00L0100\narc: E1_H01E0001 F4\narc: E1_H01E0101 F5\narc: E1_H02E0101 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: M6 H02E0401\narc: V01S0000 F4\nword: SLICEC.K0.INIT 1001000000000000\nword: SLICEC.K1.INIT 1111001101010001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010111100100011\nword: SLICEB.K0.INIT 1010111100100011\nword: SLICEB.K1.INIT 1010111100100011\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000110000100011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R7C35:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0701 S3_V06N0203\narc: H00L0100 N1_V02S0101\narc: H00R0100 H02W0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 V01N0101\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 V01N0101\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 W1_H02E0201\narc: V00B0100 S1_V02N0301\narc: V00T0100 H02E0101\narc: W1_H02W0501 V02S0501\narc: W1_H02W0701 E1_H02W0601\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: A0 H02E0701\narc: A2 H02E0701\narc: A3 H02E0701\narc: A4 H02E0501\narc: A7 V02N0101\narc: B0 H00R0100\narc: B2 H00R0100\narc: B3 H00R0100\narc: B4 V02N0701\narc: B7 H02W0101\narc: C0 H00L0100\narc: C2 H00L0100\narc: C3 H00L0100\narc: C4 V00B0100\narc: C5 H02E0401\narc: C7 E1_H01E0101\narc: D0 H02W0201\narc: D2 H02W0201\narc: D3 H02W0201\narc: D4 E1_H02W0001\narc: D5 H02E0201\narc: D7 H01W0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 F5\narc: E1_H02E0301 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F4\narc: M0 H02W0601\narc: M1 H02E0001\narc: M2 H02W0601\narc: M6 V00T0100\narc: N1_V01N0001 F6\narc: V01S0100 F6\nword: SLICEC.K0.INIT 1010001011110011\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000101100000000\nword: SLICEA.K0.INIT 0001001101011111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0001001101011111\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R7C36:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0201 N1_V01S0000\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 H01E0001\narc: E1_H02E0601 V02S0601\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 H02E0201\narc: H00L0100 H02W0301\narc: H00R0000 V02S0401\narc: H00R0100 V02N0501\narc: N1_V02N0601 V01N0001\narc: N3_V06N0003 S1_V02N0001\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 H06E0203\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0203 E1_H01W0000\narc: V00B0100 V02S0101\narc: V00T0000 E1_H02W0001\narc: V00T0100 H02W0101\narc: W1_H02W0101 V06N0103\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 E1_H02W0601\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A1 H00R0000\narc: A6 H00L0000\narc: B1 V00B0000\narc: B6 W1_H02E0301\narc: C1 H02W0401\narc: C6 V02S0201\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D6 E1_H02W0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 H00L0100\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: N1_V02N0401 Q4\narc: S1_V02S0101 F1\narc: V00B0000 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0101011101110111\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R7C37:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 N1_V02S0201\narc: H00L0100 H02W0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 N1_V02S0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0601 N1_V01S0000\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 V01N0001\narc: S1_V02S0701 W1_H02E0701\narc: V00B0000 H02E0401\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A0 V02S0701\narc: B0 H01W0100\narc: B4 H00R0000\narc: B5 E1_H02W0301\narc: B6 H02E0301\narc: C0 H02E0401\narc: C2 H00L0000\narc: C3 H00L0000\narc: C4 V00B0100\narc: C5 W1_H02E0401\narc: C6 H02E0601\narc: C7 W1_H02E0401\narc: CE2 W1_H02E0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D2 H02E0201\narc: D3 H02E0201\narc: D4 V00B0000\narc: D5 H00R0100\narc: D6 H02W0201\narc: D7 V02S0601\narc: E1_H01E0001 F7\narc: E1_H02E0501 F5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F5\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 E1_H02W0601\narc: M1 H00L0100\narc: M2 E1_H02W0601\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: S3_V06S0203 Q4\narc: S3_V06S0303 Q6\narc: V00B0100 F5\narc: V01S0000 F6\narc: W1_H02W0101 F1\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000001100110011\nword: SLICEC.K1.INIT 0011000011110000\nword: SLICED.K0.INIT 0000001100110011\nword: SLICED.K1.INIT 0000000011110000\nword: SLICEA.K0.INIT 0010101000111111\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111000011111111\nword: SLICEB.K1.INIT 1111000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R7C38:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 N1_V02S0301\narc: H00L0000 W1_H02E0001\narc: H00R0000 V02N0401\narc: H00R0100 H02E0501\narc: N1_V02N0301 S1_V02N0301\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0401 E1_H02W0401\narc: V00B0000 E1_H02W0601\narc: V00B0100 N1_V02S0301\narc: V00T0000 H02E0001\narc: V01S0000 S3_V06N0103\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 S1_V02N0601\narc: E3_H06E0103 W3_H06E0103\narc: W3_H06W0303 E3_H06W0303\narc: A2 V00T0000\narc: B2 H00R0100\narc: C0 V02S0601\narc: C1 V02S0601\narc: C2 H02E0601\narc: C3 V02S0601\narc: CE2 H00L0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 V00B0100\narc: D2 V00B0100\narc: D3 V00B0100\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 F1\narc: M0 H02W0601\narc: M1 V01S0100\narc: M2 H02W0601\narc: M4 V00B0000\narc: M6 H02E0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V02N0401 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111000011111111\nword: SLICEA.K1.INIT 1111000011111111\nword: SLICEB.K0.INIT 1000000011000000\nword: SLICEB.K1.INIT 1111000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R7C39:PLC2\narc: H00L0000 W1_H02E0001\narc: H00L0100 H02E0301\narc: H00R0100 V02N0701\narc: N1_V02N0201 E1_H01W0000\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0601 E1_H01W0000\narc: V00B0100 V02S0301\narc: V00T0000 W1_H02E0001\narc: V00T0100 H02W0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 V01N0001\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A3 V00T0000\narc: A7 H00L0000\narc: B2 W1_H02E0301\narc: B3 V02S0301\narc: B4 W1_H02E0301\narc: B5 W1_H02E0301\narc: B7 N1_V01S0000\narc: C2 N1_V01S0100\narc: C3 N1_V02S0601\narc: C4 V00B0100\narc: C5 V00B0100\narc: C7 N1_V02S0001\narc: D2 N1_V02S0001\narc: D3 H02W0001\narc: D4 H00L0100\narc: D5 H00L0100\narc: D7 V02N0601\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0100\narc: M1 E1_H02W0001\narc: M2 V00T0100\narc: M3 H00R0100\narc: M4 V00T0100\narc: M5 E1_H02W0001\narc: M6 V00T0100\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000111100000011\nword: SLICEB.K1.INIT 0000000000110001\nword: SLICEC.K0.INIT 0000111100000011\nword: SLICEC.K1.INIT 0000111100000011\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0011000100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R7C3:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0003 V06S0003\narc: H00L0100 V02N0301\narc: H00R0000 S1_V02N0401\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 H06W0003\narc: S3_V06S0303 H06W0303\narc: V00B0100 E1_H02W0501\narc: V00T0000 H02W0201\narc: V00T0100 V02N0501\narc: W1_H02W0501 N1_V01S0100\narc: A3 V00B0000\narc: B3 N1_V02S0101\narc: C3 H00L0100\narc: CE0 H02W0101\narc: CE2 H02E0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: E1_H01E0101 F3\narc: E1_H02E0201 Q0\narc: F3 F3_SLICE\narc: H01W0000 Q6\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 V00B0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q0\narc: V00B0000 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R7C40:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 N1_V01S0000\narc: H00L0000 N1_V02S0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 V02S0601\narc: S1_V02S0001 E1_H02W0001\narc: S3_V06S0003 E3_H06W0003\narc: V00B0100 V02S0301\narc: V00T0000 V02S0601\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 N1_V01S0000\narc: E3_H06E0103 W3_H06E0003\narc: A0 S1_V02N0701\narc: A1 S1_V02N0701\narc: A2 S1_V02N0701\narc: B0 V00T0000\narc: B1 V00T0000\narc: B2 H00R0000\narc: C0 H02W0401\narc: C1 H00L0000\narc: C2 H00L0000\narc: D0 V02N0201\narc: D1 V02N0201\narc: D2 V02N0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F3\narc: M0 V00B0100\narc: M1 W1_H02E0001\narc: M2 V00B0100\narc: M3 H00L0100\narc: M4 V00B0100\narc: M5 W1_H02E0001\narc: M6 V00B0100\nword: SLICEA.K0.INIT 1010111100100011\nword: SLICEA.K1.INIT 1010111100100011\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1010111100100011\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R7C41:PLC2\narc: H00R0000 H02W0601\narc: H00R0100 V02N0701\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 V02N0001\narc: W1_H02W0401 N1_V02S0401\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: CE0 H00R0100\narc: CE1 H02E0101\narc: CE2 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: M0 H02E0601\narc: M2 V00T0100\narc: M4 H02E0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V02N0201 Q0\narc: W1_H02W0201 Q2\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R7C42:PLC2\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0601 V02N0601\narc: H00R0000 S1_V02N0601\narc: H00R0100 V02N0701\narc: V00T0000 V02N0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 V01N0001\narc: W1_H02W0601 S1_V02N0601\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: CE0 H00R0000\narc: CE1 W1_H02E0101\narc: CE2 H00R0100\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: M0 V00T0000\narc: M2 V00T0000\narc: M4 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0001 Q2\narc: S1_V02S0601 Q4\narc: V01S0000 Q0\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R7C43:PLC2\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 S3_V06N0303\narc: E3_H06E0003 S3_V06N0003\narc: H00R0000 E1_H02W0601\narc: S1_V02S0001 V01N0001\narc: S3_V06S0103 E1_H01W0100\narc: V00B0000 V02N0001\narc: V00B0100 V02N0101\narc: E1_H02E0201 W3_H06E0103\narc: CE0 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: M0 H02E0601\narc: M4 V00B0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R7C44:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V02N0701\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02S0001\narc: H00R0000 H02W0601\narc: H00R0100 V02S0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0601 H06W0303\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 H02W0701\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 V02S0301\narc: V01S0000 S3_V06N0103\narc: E1_H02E0101 W3_H06E0103\narc: W3_H06W0003 E1_H02W0301\narc: E3_H06E0103 W3_H06E0103\narc: A1 E1_H01E0001\narc: A3 V01N0101\narc: B0 H02W0301\narc: B1 H00R0100\narc: B3 V02N0101\narc: C0 V02S0601\narc: C1 V02N0601\narc: C3 S1_V02N0601\narc: CE0 H00L0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 W1_H02E0201\narc: D2 V00T0100\narc: D3 H02E0201\narc: E1_H01E0001 Q0\narc: E1_H01E0101 F2\narc: E3_H06E0003 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0100 Q0\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N3_V06N0103 F2\narc: S3_V06S0003 Q0\narc: S3_V06S0103 F1\narc: V00T0100 Q3\narc: W3_H06W0303 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 1010110010100000\nword: SLICEA.K0.INIT 1111000011001100\nword: SLICEA.K1.INIT 1111101111110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R7C45:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V02N0601\narc: E3_H06E0103 H01E0101\narc: H00L0000 N1_V02S0001\narc: H00R0000 S1_V02N0401\narc: N1_V02N0101 H02W0101\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 H02W0701\narc: V00B0000 V02S0201\narc: V00T0000 H02E0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 V02N0001\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0701 V02S0701\narc: W1_H02W0601 W3_H06E0303\narc: C1 H02E0601\narc: C3 H02E0601\narc: CE0 H02E0101\narc: CE1 H02E0101\narc: CE2 H02W0101\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: D3 H00R0000\narc: E1_H01E0101 Q6\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: H01W0100 Q4\narc: LSR0 W1_H02E0301\narc: LSR1 V00B0000\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: W3_H06W0003 Q3\narc: W3_H06W0103 Q1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111100000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R7C46:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0501 V02N0501\narc: E3_H06E0003 N1_V01S0000\narc: H00L0100 V02S0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 W1_H02E0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 H01E0101\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 H02E0601\narc: V00B0000 H02W0601\narc: V00B0100 W1_H02E0701\narc: V00T0000 V02N0601\narc: V00T0100 V02S0701\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0701 N1_V01S0100\narc: E1_H02E0101 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: A2 V02S0501\narc: A3 S1_V02N0501\narc: A4 H02E0501\narc: A5 V02S0101\narc: A6 V02N0301\narc: A7 V02S0101\narc: B0 V00B0000\narc: B2 H02W0301\narc: B3 E1_H02W0301\narc: B4 E1_H02W0301\narc: B5 H02W0301\narc: B6 E1_H02W0301\narc: B7 H02W0301\narc: C0 H00R0100\narc: C1 H02W0601\narc: C2 N1_V01N0001\narc: C3 N1_V01N0001\narc: C4 V00T0000\narc: C5 V00T0000\narc: C6 S1_V02N0201\narc: C7 S1_V02N0201\narc: D0 V00B0100\narc: D1 H00R0000\narc: D2 V02N0001\narc: D3 H02W0001\narc: D4 E1_H01W0100\narc: D5 S1_V02N0601\narc: D6 V02S0601\narc: D7 H00L0100\narc: E1_H02E0701 F7\narc: E3_H06E0103 F2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: M0 V00T0100\narc: N1_V01N0101 F5\narc: V01S0000 F0\narc: W1_H02W0601 F6\narc: W3_H06W0003 F3\narc: W3_H06W0203 F4\nword: SLICEB.K0.INIT 0001001101011111\nword: SLICEB.K1.INIT 1000000010101010\nword: SLICED.K0.INIT 1000000010101010\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1000000010101010\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000110000111111\nword: SLICEA.K1.INIT 1111000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R7C47:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 V02S0201\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 V06S0203\narc: E1_H02E0501 N1_V02S0501\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0103 V06S0103\narc: E3_H06E0203 V06S0203\narc: E3_H06E0303 N1_V01S0100\narc: H00L0100 H02W0101\narc: H00R0000 H02W0401\narc: H00R0100 E1_H02W0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 V01N0001\narc: N1_V02N0601 H06E0303\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 V01N0101\narc: S1_V02S0701 N1_V01S0100\narc: V00B0100 H02E0501\narc: V00T0000 V02S0401\narc: V00T0100 V02S0501\narc: W1_H02W0301 N1_V02S0301\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 S3_V06N0203\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0303 S3_V06N0303\narc: B2 H00R0100\narc: B4 V02N0501\narc: C2 H00L0100\narc: C3 H00R0100\narc: C4 E1_H02W0401\narc: C5 E1_H02W0601\narc: CE0 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 W1_H02E0001\narc: D3 H02E0201\narc: D4 N1_V02S0601\narc: D5 S1_V02N0401\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: H01W0100 F4\narc: M0 V00B0100\narc: M2 V00T0100\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: S1_V02S0601 Q6\narc: S3_V06S0003 Q0\narc: S3_V06S0303 Q6\narc: V01S0100 Q6\narc: W1_H02W0001 F2\narc: W1_H02W0201 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000001111001111\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICEC.K0.INIT 0000001111001111\nword: SLICEC.K1.INIT 1111000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R7C48:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 V01N0001\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 W1_H02E0701\narc: H00L0000 V02S0001\narc: H00L0100 V02S0101\narc: H00R0000 V02S0401\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 V01N0101\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 H01E0001\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 N1_V02S0601\narc: V00B0000 E1_H02W0601\narc: V00T0100 V02N0501\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 N1_V02S0401\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A1 E1_H01E0001\narc: A4 S1_V02N0101\narc: A5 V00B0000\narc: A7 N1_V01N0101\narc: B1 W1_H02E0101\narc: B4 H02E0101\narc: B5 H02E0101\narc: B6 S1_V02N0501\narc: B7 H02E0101\narc: C1 S1_V02N0401\narc: C4 V02N0001\narc: C5 V02N0001\narc: C6 V02S0201\narc: C7 V02N0001\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D4 H01W0000\narc: D5 H01W0000\narc: D6 V02N0601\narc: D7 H02W0001\narc: E1_H01E0101 F1\narc: E3_H06E0303 F5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: M0 V00T0100\narc: M1 H00L0100\narc: M2 V00T0100\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: S3_V06S0203 F7\narc: S3_V06S0303 Q6\narc: V01S0000 F4\narc: V01S0100 Q6\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111101111110000\nword: SLICEC.K0.INIT 1111101111110000\nword: SLICEC.K1.INIT 1111101111110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R7C49:PLC2\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 V02S0701\narc: E3_H06E0303 H01E0101\narc: H00L0000 V02S0201\narc: H00L0100 E1_H02W0101\narc: H00R0000 V02S0401\narc: H00R0100 S1_V02N0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 H02E0601\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0301 H02W0301\narc: S1_V02S0501 N1_V02S0501\narc: V00B0000 W1_H02E0401\narc: V00B0100 H02E0701\narc: V00T0000 H02E0201\narc: V00T0100 H02W0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 V02S0601\narc: E1_H01E0001 W3_H06E0003\narc: W3_H06W0303 S3_V06N0303\narc: A1 W1_H02E0701\narc: A4 E1_H02W0701\narc: A5 N1_V01N0101\narc: A7 V00T0100\narc: B1 V00B0000\narc: B2 H00R0000\narc: B3 H00L0000\narc: B4 H02E0101\narc: B5 V00B0100\narc: B7 V00B0000\narc: C1 H02W0401\narc: C2 H02E0401\narc: C3 H00L0100\narc: C4 V00T0000\narc: C5 N1_V02S0001\narc: C7 V02N0201\narc: D1 V02S0001\narc: D2 V02N0001\narc: D3 V02N0001\narc: D4 H01W0000\narc: D5 H00R0100\narc: D7 V02N0401\narc: E3_H06E0003 F3\narc: E3_H06E0203 F4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: N1_V01N0101 F1\narc: S1_V02S0701 F7\narc: S3_V06S0103 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 0000110010101100\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R7C4:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 H01E0101\narc: H00L0000 W1_H02E0201\narc: H00R0000 H02W0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H06W0203\narc: S3_V06S0203 H06W0203\narc: V00B0000 S1_V02N0201\narc: V00B0100 H02W0501\narc: V00T0000 V02N0401\narc: V00T0100 V02S0501\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 V02S0201\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 S1_V02N0601\narc: B1 H01W0100\narc: B3 H00L0000\narc: C1 E1_H02W0401\narc: C3 V02S0401\narc: CE2 W1_H02E0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 H00R0000\narc: D2 V02N0001\narc: D3 H00R0000\narc: E1_H01E0001 Q0\narc: E1_H02E0001 Q2\narc: E3_H06E0103 Q2\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q6\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 V00T0000\narc: M2 V00T0000\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q0\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R7C50:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0401 V01N0001\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 V02N0701\narc: H00L0000 W1_H02E0001\narc: H00L0100 H02E0301\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H02E0601\narc: S1_V02S0301 N1_V02S0301\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 H02W0601\narc: V00B0100 H02E0701\narc: V00T0000 H02W0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 N1_V01S0100\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0201 W3_H06E0103\narc: S1_V02S0001 W3_H06E0003\narc: S3_V06S0003 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: A1 E1_H02W0701\narc: A4 V02N0301\narc: A5 V00B0000\narc: A7 H02E0501\narc: B1 W1_H02E0301\narc: B4 V02S0701\narc: B5 H02E0301\narc: B6 V02N0501\narc: B7 V02S0701\narc: C1 S1_V02N0401\narc: C4 V02N0001\narc: C5 V02N0001\narc: C6 V00T0000\narc: C7 V02N0001\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D4 H01W0000\narc: D5 H01W0000\narc: D6 V02S0601\narc: D7 H01W0000\narc: E3_H06E0203 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q6\narc: M0 E1_H02W0601\narc: M1 H00L0100\narc: M2 E1_H02W0601\narc: MUXCLK3 CLK0\narc: S3_V06S0203 F7\narc: S3_V06S0303 Q6\narc: V01S0100 Q6\narc: W1_H02W0601 Q6\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 1111101111110000\nword: SLICEC.K1.INIT 1111101111110000\nword: SLICED.K0.INIT 1111000011001100\nword: SLICED.K1.INIT 1111101111110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0100000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R7C51:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 E3_H06W0203\narc: H00L0000 H02E0001\narc: H00R0100 V02N0701\narc: N1_V02N0101 H06E0103\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 N1_V02S0001\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 N1_V02S0601\narc: V00B0100 H02E0701\narc: V00T0100 V02S0501\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 S1_V02N0701\narc: E3_H06E0103 W3_H06E0103\narc: A3 V02N0501\narc: B2 V02S0101\narc: B3 W1_H02E0301\narc: C2 H00L0000\narc: C3 V02N0401\narc: CE0 V02N0201\narc: CE2 V02N0601\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 V02N0001\narc: D3 E1_H02W0001\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H01W0100 Q6\narc: LSR0 H02W0301\narc: LSR1 V00T0100\narc: M0 V00B0100\narc: M4 E1_H02W0401\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q0\narc: S3_V06S0003 F3\narc: S3_V06S0103 F2\narc: V01S0100 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1111101111110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R7C52:PLC2\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 V06S0203\narc: E3_H06E0303 W1_H02E0601\narc: H00R0100 V02N0701\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H01E0101\narc: N1_V02N0701 H02W0701\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 N1_V02S0201\narc: V00B0000 V02S0001\narc: V00B0100 V02S0101\narc: V00T0000 E1_H02W0001\narc: V00T0100 H02E0301\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 W3_H06E0203\narc: CE0 V02N0201\narc: CE1 H00R0100\narc: CE2 N1_V02S0601\narc: CE3 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: LSR0 V00B0100\narc: LSR1 V00B0000\narc: M0 V00T0100\narc: M2 E1_H02W0601\narc: M4 V00T0000\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q4\narc: S3_V06S0303 Q6\narc: V01S0000 Q2\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R7C53:PLC2\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 W1_H02E0401\narc: H00L0100 S1_V02N0301\narc: H00R0100 N1_V02S0701\narc: N1_V02N0501 H02E0501\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0103 H06W0103\narc: V00B0000 W1_H02E0401\narc: V00B0100 S1_V02N0101\narc: V00T0000 H02W0001\narc: V00T0100 V02S0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0601 N1_V02S0601\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0101 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0003\narc: C5 V00B0100\narc: C7 V00B0100\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0100\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D5 V01N0001\narc: D7 H00L0100\narc: E1_H02E0501 F5\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q2\narc: LSR0 H02E0301\narc: LSR1 V00T0100\narc: M0 V00T0000\narc: M2 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q5\narc: N1_V01N0101 Q7\narc: S1_V02S0001 Q0\narc: S1_V02S0501 F5\narc: V01S0000 F5\narc: V01S0100 F7\narc: W1_H02W0701 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R7C54:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 N1_V02S0301\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 N1_V01S0100\narc: S1_V02S0701 N1_V02S0701\narc: V00B0000 H02E0401\narc: V00B0100 E1_H02W0701\narc: V00T0000 V02N0401\narc: W1_H02W0001 V02N0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: E1_H01E0101 W3_H06E0203\narc: S3_V06S0303 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: CE0 V02N0201\narc: CE1 V02N0201\narc: CE2 H00R0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: H01W0100 Q6\narc: LSR0 H02E0301\narc: LSR1 V00B0100\narc: M0 V00B0000\narc: M2 W1_H02E0601\narc: M4 V00T0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q0\narc: S3_V06S0203 Q4\narc: V01S0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R7C55:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V01N0001\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 N1_V02S0201\narc: H00L0100 N1_V02S0101\narc: H00R0000 H02W0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 H06W0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 N1_V01S0100\narc: V00B0000 V02S0201\narc: V00B0100 W1_H02E0501\narc: V00T0000 V02S0601\narc: V00T0100 V02S0701\narc: W1_H02W0101 V02N0101\narc: S3_V06S0003 W3_H06E0003\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0003 N1_V01S0000\narc: E3_H06E0203 W3_H06E0203\narc: A3 V00B0000\narc: B0 V02S0301\narc: B3 H00L0000\narc: C0 H00R0100\narc: C1 N1_V01S0100\narc: C3 H00R0100\narc: CE2 H00L0100\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 H00R0000\narc: D3 H00R0000\narc: E1_H01E0001 F3\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: H01W0000 F0\narc: LSR0 H02E0301\narc: LSR1 V00T0000\narc: M0 V00T0100\narc: M4 H02E0401\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: V01S0000 Q4\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000110000111111\nword: SLICEA.K1.INIT 1111000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R7C56:PLC2\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0601 V02N0601\narc: H00L0000 H02W0001\narc: H00R0100 E1_H02W0501\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0001 V01N0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 H06E0203\narc: V00B0000 H02E0401\narc: V00B0100 V02N0301\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0601 V06N0303\narc: W1_H02W0701 V02S0701\narc: E1_H01E0101 W3_H06E0203\narc: A0 H02E0701\narc: A1 V02S0501\narc: A2 E1_H02W0701\narc: A3 H02E0501\narc: A5 V00B0000\narc: A6 W1_H02E0701\narc: A7 V00T0100\narc: B0 V02S0101\narc: B1 N1_V02S0101\narc: B2 V02S0101\narc: B3 V02N0101\narc: B5 W1_H02E0101\narc: B6 H02E0101\narc: B7 V01S0000\narc: C0 H00L0000\narc: C1 V02N0401\narc: C2 W1_H02E0601\narc: C3 H00R0100\narc: C5 V02N0201\narc: C6 S1_V02N0201\narc: C7 H01E0001\narc: D0 H02W0201\narc: D1 H02E0001\narc: D2 V00B0100\narc: D3 V00B0100\narc: D5 S1_V02N0601\narc: D6 H01W0000\narc: D7 H00L0100\narc: E3_H06E0003 F0\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H01W0000 F7\narc: V00T0100 F1\narc: V01S0000 F5\narc: W3_H06W0103 F2\nword: SLICEB.K0.INIT 1000101000001010\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 1000000010101010\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000110010101100\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R7C57:PLC2\narc: E3_H06E0303 W1_H02E0601\narc: H00L0100 H02E0301\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 H06W0103\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0501 E1_H01W0100\narc: S3_V06S0103 H01E0101\narc: V00B0000 V02S0201\narc: V00B0100 S1_V02N0301\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02S0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 V06N0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S3_V06N0303\narc: E3_H06E0203 W3_H06E0103\narc: C7 S1_V02N0201\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D7 E1_H02W0001\narc: E1_H01E0001 F7\narc: E1_H01E0101 F7\narc: F7 F7_SLICE\narc: LSR0 V00T0100\narc: LSR1 V00B0000\narc: M0 H02E0601\narc: M2 V00B0100\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q2\narc: S1_V02S0201 Q0\narc: S1_V02S0701 Q7\narc: S3_V06S0203 Q4\narc: V01S0100 F7\narc: W3_H06W0203 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R7C58:PLC2\narc: E1_H02E0101 H01E0101\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 V02S0701\narc: H00L0100 V02N0301\narc: N1_V02N0201 E1_H02W0201\narc: V00B0000 V02N0201\narc: V00B0100 V02S0101\narc: V00T0000 V02N0401\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S3_V06N0303\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: S1_V02S0401 W3_H06E0203\narc: W3_H06W0103 S3_V06N0103\narc: E3_H06E0303 W3_H06E0203\narc: CE0 E1_H02W0101\narc: CE2 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: E3_H06E0003 Q0\narc: H01W0000 Q6\narc: H01W0100 Q4\narc: LSR0 V00B0100\narc: LSR1 E1_H02W0301\narc: M0 W1_H02E0601\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R7C59:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V02S0401\narc: S1_V02S0001 N1_V02S0001\narc: S3_V06S0003 H06E0003\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0501 W3_H06E0303\narc: W3_H06W0003 E3_H06W0303\n\n.tile R7C5:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 H01E0001\narc: H00L0000 H02E0201\narc: H00L0100 W1_H02E0101\narc: H00R0000 V02S0601\narc: H00R0100 W1_H02E0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 H06W0303\narc: S1_V02S0101 H02W0101\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0303 H06W0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 E1_H02W0701\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 E1_H02W0601\narc: A1 H00L0100\narc: A3 H02E0701\narc: A7 V02N0101\narc: B1 V02S0101\narc: B2 H00L0000\narc: B3 V02S0301\narc: B7 H02E0301\narc: C1 V02N0601\narc: C2 H02E0401\narc: C3 V02S0401\narc: C7 V02N0201\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 V00T0100\narc: D3 H00R0000\narc: D7 H00R0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: E3_H06E0103 Q2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00B0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: V00T0100 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 0011111111111111\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R7C60:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0501 W1_H02E0401\narc: H00L0000 H02E0001\narc: H00L0100 V02N0301\narc: H00R0000 W1_H02E0401\narc: S1_V02S0401 W1_H02E0401\narc: V00B0000 H02E0401\narc: V00B0100 W1_H02E0701\narc: V00T0000 H02E0201\narc: V00T0100 W1_H02E0101\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 V02S0301\narc: W3_H06W0103 S3_V06N0103\narc: E3_H06E0103 W3_H06E0003\narc: CE0 H00R0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: E3_H06E0303 Q6\narc: LSR0 V00B0000\narc: LSR1 V00B0100\narc: M0 W1_H02E0601\narc: M2 H02W0601\narc: M4 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q4\narc: S1_V02S0201 Q2\narc: V01S0100 Q0\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R7C61:PLC2\narc: H00R0100 H02E0501\narc: S1_V02S0601 H06E0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02W0701\narc: V00T0000 W1_H02E0201\narc: V00T0100 V02N0701\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: CE0 H00R0100\narc: CE1 H02E0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: E3_H06E0103 Q2\narc: LSR0 V00B0100\narc: LSR1 E1_H02W0501\narc: M0 V00B0000\narc: M2 V00T0000\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: V01S0100 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R7C62:PLC2\narc: S1_V02S0101 H01E0101\narc: W1_H02W0701 V02S0701\narc: E3_H06E0303 W3_H06E0303\n\n.tile R7C63:PLC2\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\n\n.tile R7C64:PLC2\narc: S1_V02S0101 H06E0103\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0301 W3_H06E0003\n\n.tile R7C65:PLC2\narc: W3_H06W0303 E3_H06W0203\n\n.tile R7C66:PLC2\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\n\n.tile R7C67:PLC2\narc: E3_H06E0003 W3_H06E0303\n\n.tile R7C68:PLC2\narc: E3_H06E0003 W3_H06E0303\n\n.tile R7C69:PLC2\narc: S3_V06S0103 H06E0103\narc: E1_H01E0101 W3_H06E0203\narc: N1_V02N0501 W3_H06E0303\narc: S3_V06S0303 W3_H06E0303\n\n.tile R7C6:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: H00L0000 E1_H02W0201\narc: H00L0100 W1_H02E0101\narc: H00R0000 E1_H02W0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0101 H02E0101\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 E3_H06W0303\narc: S1_V02S0301 H01E0101\narc: S1_V02S0601 H01E0001\narc: S3_V06S0103 E1_H01W0100\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0001\narc: V00B0100 N1_V02S0101\narc: V00T0000 E1_H02W0001\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 E3_H06W0303\narc: W3_H06W0303 E1_H01W0100\narc: W3_H06W0003 E3_H06W0303\narc: A1 H02E0501\narc: A3 V00T0000\narc: A5 H02W0501\narc: A7 H00L0000\narc: B1 H02E0101\narc: B2 H01W0100\narc: B3 H00R0000\narc: B5 V02N0501\narc: B7 E1_H02W0101\narc: C1 W1_H02E0601\narc: C2 N1_V01N0001\narc: C3 H00R0100\narc: C5 H02E0601\narc: C7 V02N0201\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 S1_V02N0001\narc: D3 H02E0001\narc: D5 H02W0001\narc: D7 H00L0100\narc: E1_H02E0301 F1\narc: E1_H02E0401 F4\narc: E3_H06E0103 Q2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR1 H02E0301\narc: M4 V00B0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICEB.K0.INIT 0011111111111111\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R7C70:PLC2\narc: S1_V02S0101 H01E0101\narc: S3_V06S0003 H06E0003\n\n.tile R7C7:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 E3_H06W0303\narc: H00L0100 H02E0101\narc: H00R0000 S1_V02N0601\narc: H00R0100 H02W0701\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 W1_H02E0401\narc: V00B0100 N1_V02S0301\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 V02S0001\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0501 V01N0101\narc: W1_H02W0701 V02N0701\narc: W3_H06W0203 E3_H06W0103\narc: A1 E1_H02W0701\narc: A5 V00T0000\narc: A6 V00T0100\narc: A7 F5\narc: B1 V02N0301\narc: B3 V01N0001\narc: B5 H00R0000\narc: B6 F1\narc: B7 H02E0301\narc: C1 H00L0100\narc: C3 N1_V01S0100\narc: C5 V02S0201\narc: C6 H02E0401\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0201\narc: D2 V02N0001\narc: D3 V01S0100\narc: D5 E1_H02W0201\narc: D6 H01W0000\narc: D7 H00R0100\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q2\narc: E1_H02E0001 Q2\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M2 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: N1_V02N0401 F6\narc: N1_V02N0601 F6\narc: S1_V02S0401 F6\narc: S3_V06S0303 Q6\narc: V00T0000 Q2\narc: V01S0000 F6\narc: V01S0100 F6\narc: W1_H02W0401 F6\narc: W1_H02W0601 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 0111111111111111\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R7C8:PLC2\narc: E1_H02E0201 E3_H06W0103\narc: H00L0100 V02N0101\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 V01N0101\narc: S1_V02S0001 H01E0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 H02W0301\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 H02E0601\narc: V00B0100 V02S0101\narc: V00T0000 H02E0001\narc: V00T0100 V02S0701\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 N1_V02S0701\narc: W3_H06W0003 V06N0003\narc: W3_H06W0303 E3_H06W0203\narc: B5 H00R0000\narc: C5 V00T0100\narc: CE0 V02N0201\narc: CE1 H00L0100\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D4 H01W0000\narc: D5 V02N0401\narc: E1_H01E0101 Q4\narc: F4 F5C_SLICE\narc: H00R0000 Q6\narc: H01W0000 Q0\narc: H01W0100 Q4\narc: LSR1 V00B0100\narc: M0 H02E0601\narc: M2 V00T0000\narc: M4 H02E0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V02N0601 Q4\narc: W1_H02W0001 Q0\narc: W1_H02W0201 Q2\narc: W1_H02W0601 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111100000000\nword: SLICEC.K1.INIT 1111000011001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R7C9:PLC2\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 H02W0001\narc: H00R0000 S1_V02N0601\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0201 H02W0201\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 V01N0101\narc: S3_V06S0303 H06W0303\narc: V00B0000 W1_H02E0601\narc: V00B0100 V02N0301\narc: V00T0000 H02W0201\narc: V00T0100 V02N0701\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V02N0301\narc: W1_H02W0701 H01E0101\narc: E3_H06E0103 W3_H06E0003\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00L0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H02E0201 Q2\narc: E3_H06E0003 Q0\narc: H01W0000 Q6\narc: H01W0100 Q4\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: V01S0000 Q4\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R8C10:PLC2\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 V06S0003\narc: H00R0000 E1_H02W0401\narc: H00R0100 V02S0501\narc: N1_V02N0301 H02E0301\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0601 E1_H02W0601\narc: V00B0100 H02E0701\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02S0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 H01E0101\narc: W3_H06W0103 E3_H06W0103\narc: B1 V02N0101\narc: B3 H02E0301\narc: B5 V00B0100\narc: B7 V00T0000\narc: C1 N1_V01S0100\narc: C3 E1_H02W0401\narc: C5 E1_H02W0401\narc: C7 E1_H02W0401\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D3 V00T0100\narc: D5 H00R0100\narc: D7 V02S0401\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q1\narc: N1_V02N0101 Q3\narc: N1_V02N0501 Q5\narc: V01S0100 Q7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110000001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111110000001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R8C11:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 W1_H02E0001\narc: H00R0000 W1_H02E0601\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0701 H06W0203\narc: S1_V02S0601 N1_V01S0000\narc: S1_V02S0701 H06W0203\narc: S3_V06S0103 H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0100 S1_V02N0301\narc: V00T0100 E1_H02W0301\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0701 S1_V02N0701\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: H01W0000 Q0\narc: H01W0100 Q6\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 E1_H02W0601\narc: M2 H02W0601\narc: M4 V00T0100\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q2\narc: N1_V02N0001 Q2\narc: N1_V02N0201 Q0\narc: N1_V02N0401 Q6\narc: N1_V02N0601 Q4\narc: V01S0000 Q2\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET SET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET SET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R8C12:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 S1_V02N0201\narc: H00R0000 H02W0401\narc: H00R0100 H02W0701\narc: H01W0000 E3_H06W0103\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0701 H06W0203\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 H02W0401\narc: S1_V02S0701 H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0100 H02E0701\narc: V00T0000 N1_V02S0401\narc: W1_H02W0201 V02S0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 E1_H02W0601\narc: W1_H02W0701 S1_V02N0701\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: B5 H00R0000\narc: C0 H00L0100\narc: C1 H00L0000\narc: C4 V02S0001\narc: C5 V02S0201\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 S1_V02N0001\narc: D4 V02N0601\narc: D5 V02N0601\narc: D7 H00R0100\narc: E1_H01E0101 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0100 F7\narc: LSR1 H02E0501\narc: M2 V00T0000\narc: M4 E1_H02W0401\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V02N0001 F0\narc: N1_V02N0201 Q2\narc: S3_V06S0103 F1\narc: W1_H02W0001 F0\narc: W3_H06W0003 F0\narc: W3_H06W0103 F1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 0000111100110011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R8C13:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V02S0301\narc: H00R0000 V02N0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 H06W0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H02E0101\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0701 H06W0203\narc: S3_V06S0303 H01E0101\narc: V00B0000 H02W0401\narc: V00T0000 S1_V02N0601\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 N1_V02S0701\narc: B1 H02E0301\narc: B7 V02S0701\narc: C0 E1_H02W0401\narc: C1 W1_H02E0401\narc: C6 V02S0201\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H00R0000\narc: D5 H00R0100\narc: D6 V02N0601\narc: D7 V02N0601\narc: E1_H01E0101 F6\narc: F0 F5A_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 Q2\narc: LSR1 V00B0100\narc: M0 V00B0000\narc: M2 H02E0601\narc: M6 H02W0401\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00B0100 F5\narc: V01S0000 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 0000111100110011\nword: SLICEA.K0.INIT 1111111100001111\nword: SLICEA.K1.INIT 0000111100110011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R8C14:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0401 V02S0401\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 H01E0101\narc: H00R0000 H02W0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 H02W0001\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0201 H02E0201\narc: S1_V02S0501 H06E0303\narc: S1_V02S0701 H06E0203\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E3_H06W0303\narc: W3_H06W0003 S3_V06N0003\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0203\narc: B1 E1_H01W0100\narc: B3 H00R0000\narc: B5 V00B0100\narc: B7 H02E0101\narc: C1 W1_H02E0401\narc: C3 W1_H02E0401\narc: C5 W1_H02E0401\narc: C7 W1_H02E0401\narc: CLK0 G_HPBX0000\narc: D1 N1_V01S0000\narc: D3 H02E0001\narc: D5 H00R0100\narc: D7 V00B0000\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q5\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q7\narc: N1_V01N0101 Q3\narc: N1_V02N0101 Q1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111110000001100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110000001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111110000001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R8C15:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 V02N0501\narc: E1_H02E0701 V02N0701\narc: E3_H06E0303 V06S0303\narc: H00L0100 V02N0101\narc: H00R0000 V02N0601\narc: H00R0100 E1_H02W0501\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0201 E3_H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 N1_V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 V02S0601\narc: V00T0100 W1_H02E0301\narc: S3_V06S0103 W3_H06E0103\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: C6 V00B0100\narc: C7 E1_H02W0401\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CE2 V02N0601\narc: CLK0 G_HPBX0000\narc: D6 H01W0000\narc: D7 H00L0100\narc: E1_H01E0001 Q2\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q2\narc: LSR0 H02W0301\narc: LSR1 V00B0000\narc: M0 V00T0100\narc: M2 V00T0100\narc: M4 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q4\narc: N1_V02N0001 Q2\narc: S1_V02S0501 F7\narc: V01S0000 F7\narc: V01S0100 Q0\narc: W1_H02W0001 Q0\narc: W1_H02W0401 Q4\narc: W3_H06W0303 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0000000011110000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R8C16:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0501 S1_V02N0501\narc: H00L0100 S1_V02N0101\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0001 H06W0003\narc: S1_V02S0201 H06W0103\narc: V00T0000 V02S0601\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 H01E0001\narc: W1_H02W0301 S1_V02N0301\narc: W3_H06W0103 E3_H06W0103\narc: A3 V00B0000\narc: B3 V02S0101\narc: C3 H00L0100\narc: C6 V00B0100\narc: C7 V00T0000\narc: CE0 H00R0000\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D3 W1_H02E0001\narc: D6 W1_H02E0201\narc: D7 V01N0001\narc: E1_H01E0101 F6\narc: E1_H02E0701 F7\narc: E3_H06E0203 F7\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F6\narc: H01W0000 Q0\narc: H01W0100 F6\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 W1_H02E0601\narc: M4 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0101 F3\narc: V00B0000 Q4\narc: V00B0100 F7\narc: V01S0000 F7\narc: W1_H02W0701 F7\narc: W3_H06W0203 F7\narc: W3_H06W0303 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0000111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R8C17:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 W1_H02E0701\narc: H00L0000 W1_H02E0001\narc: H00R0000 V02S0401\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0001 V01N0001\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0501 V01N0101\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 S1_V02N0001\narc: V00B0100 H02E0501\narc: V00T0000 H02E0001\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 E3_H06W0103\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 H01E0101\narc: W3_H06W0203 E3_H06W0203\narc: A0 W1_H02E0501\narc: A1 V02N0701\narc: A4 V00T0000\narc: A5 V02N0101\narc: B0 H02E0301\narc: B1 H00R0100\narc: B3 H00L0000\narc: B4 V02S0501\narc: B5 V01S0000\narc: C0 H00L0100\narc: C1 E1_H01W0000\narc: C3 V02N0401\narc: C4 E1_H01E0101\narc: C5 E1_H02W0601\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 H00R0000\narc: D3 H02E0201\narc: D4 V00B0000\narc: D5 V02S0401\narc: D7 V02N0601\narc: E1_H01E0101 F5\narc: E1_H02E0301 Q3\narc: E3_H06E0003 F0\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H00R0100 F7\narc: LSR1 H02W0501\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V01S0000 F7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100000011111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 1010001010101010\nword: SLICEA.K1.INIT 0010001000001010\nword: SLICEC.K0.INIT 1100010011001100\nword: SLICEC.K1.INIT 0010001010100000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R8C18:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E3_H06E0103 V01N0101\narc: H00L0100 E1_H02W0301\narc: H00R0000 S1_V02N0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H02W0401\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02N0201\narc: V00B0100 S1_V02N0301\narc: V00T0000 H02W0001\narc: V00T0100 H02W0101\narc: V01S0100 N3_V06S0303\narc: W1_H02W0301 N3_V06S0003\narc: W1_H02W0501 V02N0501\narc: S1_V02S0001 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A0 V01N0101\narc: A1 V01N0101\narc: A4 H02W0501\narc: A5 H02W0501\narc: B0 H02E0101\narc: B1 H02E0101\narc: B4 H00R0000\narc: B5 H00R0000\narc: C0 V02N0601\narc: C1 V02N0601\narc: C4 V02N0001\narc: C5 V02N0001\narc: CE1 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 V02N0201\narc: D4 V00B0000\narc: D5 V00B0000\narc: E1_H01E0001 F0\narc: E1_H02E0601 Q6\narc: F0 F5A_SLICE\narc: F4 F5C_SLICE\narc: H01W0000 F4\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00T0100\narc: M2 H02E0601\narc: M4 V00B0100\narc: M6 N1_V01N0101\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q2\narc: V01S0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0101101011111011\nword: SLICEC.K1.INIT 0010100001000100\nword: SLICEA.K0.INIT 1011101011101110\nword: SLICEA.K1.INIT 1010111111111101\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R8C19:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 H02W0001\narc: H00R0000 V02N0601\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 H06W0003\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 N3_V06S0303\narc: N1_V02N0701 H06W0203\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0701 H06E0203\narc: V00B0000 V02S0001\narc: V00T0000 S1_V02N0601\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 H01E0001\narc: W3_H06W0003 V06S0003\narc: W3_H06W0103 V06S0103\narc: A7 H00R0000\narc: B7 V02N0501\narc: C7 V00T0000\narc: CE0 H00L0000\narc: CE1 E1_H02W0101\narc: CE2 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D7 H02E0201\narc: E1_H01E0101 Q0\narc: E3_H06E0003 Q0\narc: E3_H06E0203 Q4\narc: F7 F7_SLICE\narc: LSR0 V00T0100\narc: LSR1 H02E0501\narc: M0 V00B0000\narc: M2 H02E0601\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q2\narc: S1_V02S0501 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1101011100001110\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R8C20:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0401 E3_H06W0203\narc: H00L0100 H02W0301\narc: H00R0100 V02N0701\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0401 H06W0203\narc: S3_V06S0103 N3_V06S0103\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 E1_H02W0401\narc: V00B0100 V02N0301\narc: V00T0000 H02E0001\narc: W1_H02W0301 V06S0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: C2 V02N0401\narc: C3 H00R0100\narc: CE0 H00L0100\narc: CE2 H00L0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D2 H02W0201\narc: D3 N1_V02S0001\narc: E1_H01E0101 F2\narc: E1_H02E0101 F3\narc: E1_H02E0201 F2\narc: E3_H06E0003 F3\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H00L0000 F2\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 V00T0000\narc: M4 V00B0100\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q0\narc: N1_V02N0401 Q6\narc: S3_V06S0003 F3\narc: V01S0000 F3\narc: V01S0100 Q6\narc: W1_H02W0001 F2\narc: W1_H02W0101 F3\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0000111100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R8C21:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 V02S0401\narc: E1_H02E0701 H01E0101\narc: H00L0100 V02S0101\narc: H00R0100 S1_V02N0701\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0001 H06W0003\narc: S1_V02S0401 H02E0401\narc: S1_V02S0501 E3_H06W0303\narc: S3_V06S0303 E3_H06W0303\narc: V00T0000 H02W0001\narc: V00T0100 V02N0501\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H02W0201\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A4 N1_V01N0101\narc: A5 F7\narc: A7 S1_V02N0101\narc: B1 H02W0101\narc: B4 W1_H02E0301\narc: B5 E1_H02W0101\narc: B7 H02W0301\narc: C1 V02S0601\narc: C4 N1_V02S0201\narc: C5 E1_H02W0401\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D4 V02N0401\narc: D5 H00L0100\narc: D7 H00R0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 F4\narc: E1_H02E0101 F1\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q5\narc: S1_V02S0301 F1\narc: W1_H02W0101 F1\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 0111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R8C22:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 W1_H02E0001\narc: H00R0100 H02E0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 H01E0101\narc: S1_V02S0401 H06E0203\narc: S1_V02S0701 V01N0101\narc: V00B0000 V02N0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0401\narc: V00T0100 S1_V02N0501\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 S1_V02N0401\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0401 W3_H06E0203\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0203 E1_H01W0000\narc: W3_H06W0103 E3_H06W0003\narc: CE0 H00R0100\narc: CE2 H00L0000\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q6\narc: LSR0 V00B0100\narc: LSR1 V00B0100\narc: M0 V00T0100\narc: M4 V00B0000\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q0\narc: V01S0000 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R8C23:PLC2\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 V01N0001\narc: H00L0100 H02W0301\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 N3_V06S0203\narc: S1_V02S0101 S3_V06N0103\narc: V00B0000 V02N0201\narc: V00T0100 H02E0101\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0601 E1_H01W0000\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: A3 V00T0000\narc: B3 H00L0000\narc: B7 V00B0000\narc: C2 H00L0100\narc: C3 H02W0401\narc: C4 E1_H02W0601\narc: C5 S1_V02N0201\narc: C6 H02E0601\narc: C7 W1_H02E0401\narc: CE0 V02S0201\narc: CLK0 G_HPBX0000\narc: D2 V00B0100\narc: D3 H02W0201\narc: D4 H00R0100\narc: D5 H02E0001\narc: D6 H00R0100\narc: D7 W1_H02E0201\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q2\narc: E1_H02E0001 Q0\narc: E1_H02E0101 F3\narc: E1_H02E0701 F5\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0100 F5\narc: H01W0000 F7\narc: H01W0100 F7\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 H02W0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F2\narc: N1_V01N0101 F4\narc: N1_V02N0501 F7\narc: N3_V06N0203 F4\narc: N3_V06N0303 F6\narc: S1_V02S0201 F2\narc: S1_V02S0701 F5\narc: S3_V06S0203 F7\narc: V00B0100 F5\narc: V00T0000 Q0\narc: V01S0000 F7\narc: V01S0100 F2\narc: W1_H02W0201 F2\narc: W1_H02W0701 F5\narc: W3_H06W0103 F2\narc: W3_H06W0203 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0000000000000111\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000000011110000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0011000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R8C24:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 W1_H02E0401\narc: E1_H02E0601 V06S0303\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 H02E0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 H02E0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 N1_V01S0100\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0601 S1_V02N0301\narc: V00T0000 H02E0001\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 V06S0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 V06S0203\narc: W1_H02W0601 E1_H02W0601\narc: E1_H02E0201 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0203 E3_H06W0203\narc: A1 H02W0501\narc: A6 H00L0000\narc: B0 V00T0000\narc: B1 V02S0301\narc: B3 V02N0101\narc: B6 H01E0101\narc: C0 H00L0100\narc: C1 H00R0100\narc: C2 H02W0601\narc: C3 H02E0401\narc: C6 V02N0201\narc: C7 F6\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 W1_H02E0201\narc: D2 S1_V02N0201\narc: D3 V02S0201\narc: D6 V02S0601\narc: D7 H02W0001\narc: E1_H01E0001 F3\narc: E1_H01E0101 Q4\narc: E3_H06E0003 F3\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 F0\narc: M4 E1_H02W0401\narc: MUXCLK2 CLK0\narc: N1_V01N0001 F6\narc: N1_V01N0101 F6\narc: N1_V02N0301 F3\narc: N1_V02N0401 F6\narc: V00T0100 F1\narc: V01S0000 F7\narc: V01S0100 F6\narc: W3_H06W0003 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0000110000000000\nword: SLICED.K0.INIT 0000000000001000\nword: SLICED.K1.INIT 1111111111110000\nword: SLICEA.K0.INIT 0011111100000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R8C25:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 V02N0101\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0701 W1_H02E0701\narc: V00B0000 H02W0601\narc: V00B0100 W1_H02E0701\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02N0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0501 V01N0101\narc: W1_H02W0601 H01E0001\narc: E1_H02E0501 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: A4 N1_V01N0101\narc: A5 N1_V01N0101\narc: B1 V02S0101\narc: B4 W1_H02E0101\narc: B5 H00R0000\narc: C0 E1_H02W0601\narc: C1 H02E0601\narc: C3 H00R0100\narc: C4 V00T0100\narc: C5 V02S0001\narc: CE0 H00L0000\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0001\narc: D1 V02S0201\narc: D3 V00B0100\narc: D4 S1_V02N0401\narc: D5 V02S0601\narc: E3_H06E0103 Q1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0000 F0\narc: H00L0100 F3\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q6\narc: S3_V06S0303 Q5\narc: W1_H02W0401 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0001001101011111\nword: SLICEC.K1.INIT 0101011101110111\nword: SLICEA.K0.INIT 1111111100001111\nword: SLICEA.K1.INIT 0000000000001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R8C26:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 E3_H06W0303\narc: E3_H06E0203 W1_H02E0401\narc: H00L0000 V02N0201\narc: H00R0100 H02E0501\narc: N1_V02N0601 N1_V01S0000\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0103 N3_V06S0003\narc: V00B0000 V02N0201\narc: V00B0100 V02N0101\narc: V00T0000 W1_H02E0201\narc: V00T0100 W1_H02E0101\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 E3_H06W0303\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0001 W3_H06E0003\narc: S1_V02S0001 W3_H06E0003\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0203\narc: A1 H00L0000\narc: A2 V00B0000\narc: A3 V00B0000\narc: A4 V00B0000\narc: A5 V00B0000\narc: A7 H00R0000\narc: B1 W1_H02E0301\narc: B2 S1_V02N0301\narc: B3 S1_V02N0301\narc: B4 H02W0301\narc: B5 H02W0301\narc: B7 V02S0501\narc: C1 H00R0100\narc: C2 H02E0601\narc: C3 H02E0601\narc: C4 H02E0601\narc: C5 H02E0601\narc: C7 N1_V02S0201\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D2 V00T0100\narc: D3 V00T0100\narc: D4 W1_H02E0201\narc: D5 W1_H02E0201\narc: D6 N1_V02S0601\narc: D7 V02S0601\narc: E1_H01E0001 F2\narc: E3_H06E0003 F0\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q6\narc: LSR1 E1_H02W0301\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: V01S0000 F7\narc: V01S0100 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0101001100000000\nword: SLICEB.K0.INIT 1001100111111011\nword: SLICEB.K1.INIT 1110111111001110\nword: SLICEC.K0.INIT 1111111111101100\nword: SLICEC.K1.INIT 0101101100010011\nword: SLICED.K0.INIT 0000000011111111\nword: SLICED.K1.INIT 0100000101110001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\n\n.tile R8C27:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 W1_H02E0301\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 H06E0003\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0701 V01N0101\narc: V00B0000 V02S0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 V06S0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: B5 W1_H02E0101\narc: B7 E1_H02W0301\narc: C4 V00B0100\narc: C5 W1_H02E0401\narc: C7 H01E0001\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 H00R0100\narc: D5 H02E0001\narc: D7 V02N0601\narc: E1_H01E0001 Q0\narc: E1_H02E0701 F5\narc: E3_H06E0203 F7\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0000 F4\narc: H01W0000 Q0\narc: M0 V00B0000\narc: M2 H02E0601\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: S1_V02S0201 Q2\narc: S1_V02S0701 F5\narc: V00B0100 F5\narc: W1_H02W0701 F5\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000001100\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000110000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R8C28:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0203 V01N0001\narc: H00L0000 H02W0201\narc: H00L0100 V02N0301\narc: H00R0000 S1_V02N0601\narc: H00R0100 H02E0701\narc: N1_V02N0201 H02E0201\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0601 S1_V02N0301\narc: S1_V02S0501 V01N0101\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E1_H01W0000\narc: V00B0100 H02E0501\narc: V00T0000 H02W0001\narc: V00T0100 V02N0501\narc: W1_H02W0301 N1_V02S0301\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: A3 H01E0001\narc: B2 H00L0000\narc: B3 S1_V02N0101\narc: B7 V02S0501\narc: C1 H02E0601\narc: C2 W1_H02E0401\narc: C3 H00R0100\narc: C7 H02E0601\narc: CE2 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 V00T0100\narc: D3 H00R0000\narc: D7 H01W0000\narc: E1_H01E0001 Q4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: N1_V02N0101 F1\narc: N3_V06N0103 F2\narc: S1_V02S0101 F1\narc: V01S0000 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0011111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R8C29:PLC2\narc: E1_H02E0201 V02S0201\narc: E1_H02E0501 E3_H06W0303\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 H02W0201\narc: H00L0100 N1_V02S0101\narc: H00R0100 V02N0501\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H06W0203\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0501 N1_V02S0501\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 H06W0203\narc: V00B0000 V02S0001\narc: V00B0100 N1_V02S0101\narc: V00T0000 V02N0601\narc: V00T0100 V02N0501\narc: W1_H02W0001 V06N0003\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 S1_V02N0301\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: A0 H02E0701\narc: A2 E1_H01E0001\narc: A4 H02W0701\narc: A7 N1_V01N0101\narc: B0 V02S0101\narc: B2 V02S0301\narc: B4 H00L0000\narc: B7 V02S0701\narc: C0 V02N0401\narc: C1 E1_H02W0601\narc: C2 V02N0401\narc: C3 H00R0100\narc: C4 V00T0000\narc: C5 V00T0100\narc: C6 V00T0100\narc: C7 V00B0100\narc: CE0 H02W0101\narc: CE1 H02W0101\narc: CE2 H02W0101\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 E1_H02W0001\narc: D2 H02W0001\narc: D3 S1_V02N0001\narc: D4 H00L0100\narc: D5 E1_H02W0201\narc: D6 V00B0000\narc: D7 H02W0001\narc: E1_H01E0001 Q3\narc: E1_H01E0101 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 Q1\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q6\narc: S3_V06S0003 F0\narc: S3_V06S0203 F7\narc: V01S0100 F2\nword: SLICEA.K0.INIT 0001001101011111\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEC.K0.INIT 0001010100111111\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0001001101011111\nword: SLICEB.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 0000111100000000\nword: SLICED.K1.INIT 0001001101011111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\n\n.tile R8C2:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0101 V01N0101\narc: E1_H02E0301 V02N0301\narc: E1_H02E0601 S1_V02N0601\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 S1_V02N0301\narc: V00B0100 V02N0301\narc: CE1 H02W0101\narc: CLK0 G_HPBX0000\narc: E1_H02E0001 Q2\narc: LSR0 V00B0100\narc: M2 H02E0601\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R8C30:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 W1_H02E0201\narc: E3_H06E0203 W1_H02E0401\narc: H00R0000 H02E0601\narc: H00R0100 V02N0701\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0701 H02W0701\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0401 N1_V02S0401\narc: S1_V02S0701 H02E0701\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 V02S0201\narc: V00B0100 H02W0701\narc: V00T0000 H02E0201\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0701 H01E0101\narc: E1_H02E0701 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: S1_V02S0001 W3_H06E0003\narc: W1_H02W0001 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0203 E3_H06W0203\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CE2 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E3_H06E0003 Q0\narc: E3_H06E0103 Q2\narc: H01W0100 Q6\narc: M0 V00B0100\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: S1_V02S0601 Q4\narc: V01S0000 Q6\narc: V01S0100 Q2\narc: W1_H02W0201 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R8C31:PLC2\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0501 V06N0303\narc: E1_H02E0701 N1_V01S0100\narc: H00L0100 E1_H02W0301\narc: H00R0000 V02N0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 H06W0303\narc: S1_V02S0401 H02W0401\narc: V00B0000 H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 H02W0201\narc: V00T0100 N1_V02S0701\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 S1_V02N0701\narc: E3_H06E0103 W3_H06E0103\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 H02W0101\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q2\narc: E1_H02E0001 Q2\narc: E1_H02E0601 Q6\narc: E3_H06E0003 Q0\narc: E3_H06E0203 Q4\narc: H01W0100 Q6\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q4\narc: N1_V02N0401 Q6\narc: V01S0100 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R8C32:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 N1_V01S0000\narc: E3_H06E0003 W1_H02E0301\narc: H00L0000 V02S0201\narc: H00R0000 H02E0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H02E0601\narc: N1_V02N0701 H01E0101\narc: N3_V06N0003 H06W0003\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 H06W0003\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 H06W0303\narc: S3_V06S0203 H06W0203\narc: V00B0000 V02S0001\narc: V00B0100 H02E0501\narc: V00T0000 H02E0001\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 E3_H06W0203\narc: W1_H02W0601 S3_V06N0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0203\narc: A1 H01E0001\narc: A2 V00T0000\narc: B1 W1_H02E0101\narc: B2 H00R0000\narc: C1 H00L0000\narc: C2 H00L0000\narc: CE2 E1_H02W0101\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D2 S1_V02N0201\narc: E1_H01E0001 Q4\narc: E1_H01E0101 Q6\narc: E1_H02E0601 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 F1\narc: M0 V00B0000\narc: M1 H00R0100\narc: M2 V00B0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V01N0101 Q4\narc: V01S0100 Q6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1010111100100011\nword: SLICEB.K0.INIT 1010111100100011\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R8C33:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 V02S0601\narc: H00L0000 H02W0001\narc: H00L0100 H02E0101\narc: H00R0100 H02W0501\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0301 E1_H02W0301\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0203 E1_H01W0000\narc: V00B0000 V02S0001\narc: V00T0100 W1_H02E0301\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 E1_H02W0301\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A1 N1_V02S0701\narc: A2 V00B0000\narc: A3 V00B0000\narc: A4 N1_V01N0101\narc: A7 Q7\narc: B1 E1_H01W0100\narc: B2 E1_H01W0100\narc: B3 E1_H01W0100\narc: B4 H02E0301\narc: B5 H00R0000\narc: B7 V02N0501\narc: C1 H00L0000\narc: C2 H00L0000\narc: C3 H00L0000\narc: C4 V00T0100\narc: C5 V02N0001\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D2 H02W0201\narc: D3 H02W0201\narc: D4 H00R0100\narc: D5 H00L0100\narc: D7 E1_H02W0001\narc: E1_H02E0701 F5\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: H01W0100 Q7\narc: LSR0 E1_H02W0501\narc: LSR1 E1_H02W0501\narc: M0 H01E0001\narc: M1 H02E0001\narc: M2 H02E0601\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q7\narc: N1_V01N0101 Q4\narc: N1_V02N0101 F1\narc: V01S0100 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111100101010\nword: SLICEC.K0.INIT 1111111100101010\nword: SLICEC.K1.INIT 1100110000001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000110010101111\nword: SLICEB.K0.INIT 1000110010101111\nword: SLICEB.K1.INIT 1000110010101111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R8C34:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0101 V01N0101\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 N1_V01S0100\narc: H00L0000 H02E0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 N1_V02S0401\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0701 E1_H01W0100\narc: N3_V06N0203 E3_H06W0203\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0201 H02E0201\narc: S1_V02S0401 E3_H06W0203\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 V02N0001\narc: V00B0100 H02E0501\narc: V00T0000 H02E0001\narc: V00T0100 E1_H02W0301\narc: V01S0000 S3_V06N0103\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0501 E1_H01W0100\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A1 H00L0000\narc: A2 V00T0000\narc: A3 V00T0000\narc: B1 V00B0000\narc: B2 H00R0000\narc: B3 H00R0000\narc: B7 H02E0301\narc: C1 N1_V01N0001\narc: C2 N1_V01N0001\narc: C3 N1_V01N0001\narc: C6 V00T0100\narc: C7 H02E0601\narc: CE2 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D1 N1_V02S0001\narc: D2 N1_V02S0001\narc: D3 N1_V02S0001\narc: D6 H01W0000\narc: D7 W1_H02E0201\narc: E1_H01E0001 F7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q4\narc: M0 V00B0100\narc: M1 H00L0100\narc: M2 V00B0100\narc: M4 H02E0401\narc: MUXCLK2 CLK0\narc: N1_V01N0101 F6\narc: N1_V02N0301 F1\narc: N1_V02N0401 Q4\narc: N1_V02N0501 F7\narc: S3_V06S0203 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000001111\nword: SLICED.K1.INIT 0000000000110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100010011110101\nword: SLICEB.K0.INIT 1100010011110101\nword: SLICEB.K1.INIT 1100010011110101\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R8C35:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0401 S1_V02N0401\narc: E3_H06E0003 H01E0001\narc: H00L0000 V02S0201\narc: H00L0100 N1_V02S0301\narc: H00R0000 E1_H02W0401\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 H02W0501\narc: V00B0100 E1_H02W0701\narc: V00T0000 S1_V02N0601\narc: V00T0100 S1_V02N0501\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0501 V02N0501\narc: W1_H02W0701 E3_H06W0203\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A5 H02W0701\narc: A6 S1_V02N0101\narc: A7 H00L0000\narc: B5 W1_H02E0101\narc: B6 V01S0000\narc: B7 V00B0100\narc: C5 S1_V02N0001\narc: C6 H02E0401\narc: C7 V02N0201\narc: D0 V02N0001\narc: D1 V00T0100\narc: D2 H00R0000\narc: D3 H02W0001\narc: D5 V02N0401\narc: D6 H00R0100\narc: D7 H02E0001\narc: E1_H01E0101 F4\narc: E3_H06E0203 F4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F4\narc: M0 E1_H02W0601\narc: M1 H00L0100\narc: M2 E1_H02W0601\narc: M4 V00T0000\narc: N1_V01N0101 F6\narc: N3_V06N0203 F4\narc: S3_V06S0103 F1\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 1001000000000000\nword: SLICED.K1.INIT 1000101011001111\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0010000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R8C36:PLC2\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 V01N0001\narc: E1_H02E0701 S3_V06N0203\narc: H00L0000 V02N0201\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02S0401\narc: H00R0100 V02S0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 S1_V02N0301\narc: S3_V06S0103 H06W0103\narc: V00B0100 W1_H02E0701\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02N0701\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 V02N0701\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0401 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A1 V02S0701\narc: A5 V00T0100\narc: B0 H00R0100\narc: B1 S1_V02N0101\narc: B2 H00R0100\narc: B3 H00R0100\narc: B5 S1_V02N0501\narc: B7 H02E0101\narc: C0 S1_V02N0601\narc: C1 H00L0000\narc: C2 S1_V02N0601\narc: C3 S1_V02N0601\narc: C5 H02E0401\narc: C6 V00T0000\narc: C7 E1_H02W0401\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 H02W0201\narc: D2 H02W0201\narc: D3 H02W0201\narc: D5 V02N0401\narc: D6 H02E0001\narc: D7 H02W0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 F4\narc: E3_H06E0103 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F4\narc: LSR1 H02W0301\narc: M0 W1_H02E0601\narc: M1 H00R0000\narc: M2 W1_H02E0601\narc: M4 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F4\narc: N1_V02N0301 F1\narc: N3_V06N0203 F4\narc: S1_V02S0501 F7\narc: S1_V02S0601 F6\narc: S3_V06S0203 F4\narc: V01S0000 F4\narc: V01S0100 F7\narc: W1_H02W0501 Q7\narc: W3_H06W0103 F1\narc: W3_H06W0203 Q7\nword: SLICED.K0.INIT 0000000000001111\nword: SLICED.K1.INIT 0000111111001100\nword: SLICEB.K0.INIT 1111111100111111\nword: SLICEB.K1.INIT 1111111100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 1111111100111111\nword: SLICEA.K1.INIT 1111000001110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\n\n.tile R8C37:PLC2\narc: E1_H01E0001 E3_H06W0003\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 H01E0101\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 S1_V02N0501\narc: E3_H06E0103 H01E0101\narc: H00R0000 V02S0401\narc: H00R0100 H02E0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 N3_V06S0103\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 S1_V02N0401\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 V01N0101\narc: S3_V06S0003 N1_V01S0000\narc: V00B0000 H02E0601\narc: V00B0100 H02E0701\narc: V00T0000 H02W0201\narc: V00T0100 H02E0301\narc: V01S0000 S3_V06N0103\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 N3_V06S0103\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: A1 H00R0000\narc: B1 V00B0000\narc: C1 V02N0401\narc: CE2 H00R0100\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: E1_H01E0101 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 F1\narc: M0 V00T0100\narc: M1 V01S0100\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q6\narc: N1_V02N0301 F1\narc: N3_V06N0103 F1\narc: W3_H06W0103 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R8C38:PLC2\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 S1_V02N0301\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0203 W1_H02E0401\narc: H00R0000 H02W0401\narc: H00R0100 W1_H02E0501\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 H06E0203\narc: N3_V06N0203 S3_V06N0203\narc: S1_V02S0001 H06E0003\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 H06W0303\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 H02E0501\narc: V00T0000 H02E0001\narc: V01S0000 N3_V06S0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 E1_H02W0101\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0101 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: CE0 H00R0100\narc: CE1 H02E0101\narc: CE2 H00R0000\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: H01W0000 Q6\narc: H01W0100 Q2\narc: M0 V00B0100\narc: M2 V00T0000\narc: M4 H02E0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: W1_H02W0001 Q0\narc: W3_H06W0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R8C39:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 V06N0003\narc: E1_H02E0401 V06N0203\narc: E1_H02E0501 V02N0501\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 H01E0001\narc: H00L0000 S1_V02N0001\narc: H00L0100 E1_H02W0301\narc: H00R0100 H02W0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0101 H06E0103\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0501 V01N0101\narc: V00B0000 V02N0001\narc: V00B0100 V02S0101\narc: V00T0100 E1_H02W0301\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 E1_H01W0000\narc: W3_H06W0303 E1_H02W0501\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: B1 V00T0000\narc: B5 V00B0100\narc: C0 H00R0100\narc: C1 H02W0601\narc: C3 H00L0000\narc: C4 H02W0401\narc: C5 N1_V02S0201\narc: CE0 V02N0201\narc: CLK0 G_HPBX0000\narc: D0 V00T0100\narc: D1 H02W0201\narc: D3 V00T0100\narc: D4 H00L0100\narc: D5 V02S0601\narc: E1_H02E0001 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F5\narc: H01W0100 F4\narc: LSR0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F3\narc: V00T0000 F0\narc: W3_H06W0103 Q1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001111\nword: SLICEC.K0.INIT 0000000000001111\nword: SLICEC.K1.INIT 0000000000000011\nword: SLICEA.K0.INIT 0000000000001111\nword: SLICEA.K1.INIT 0000001100110011\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R8C3:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0401 E3_H06W0203\narc: E1_H02E0601 V02S0601\narc: H00L0000 H02W0001\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 E3_H06W0303\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0301 E3_H06W0003\narc: S1_V02S0501 E3_H06W0303\narc: S3_V06S0103 H06W0103\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 E1_H02W0401\narc: V00B0100 H02W0701\narc: V00T0000 H02E0001\narc: V00T0100 V02S0701\narc: W1_H02W0101 H01E0101\narc: A1 H00R0000\narc: A5 V00T0000\narc: B1 N1_V02S0301\narc: B3 V01N0001\narc: B5 H02E0101\narc: C1 H02E0601\narc: C3 H00L0000\narc: C5 V02N0001\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D1 H02W0201\narc: D2 V00B0100\narc: D3 V00T0100\narc: D5 E1_H02W0001\narc: E1_H01E0001 Q2\narc: E1_H02E0301 F1\narc: E1_H02E0501 F5\narc: E3_H06E0103 Q2\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H00R0000 Q6\narc: LSR0 H02W0501\narc: LSR1 H02E0301\narc: M2 V00B0000\narc: M6 N1_V01N0101\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R8C40:PLC2\narc: E1_H02E0101 V06N0103\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 S3_V06N0303\narc: E3_H06E0003 W1_H02E0301\narc: H00R0100 S1_V02N0501\narc: N1_V02N0201 N3_V06S0103\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0301 H02E0301\narc: S1_V02S0601 S3_V06N0303\narc: V00T0000 E1_H02W0201\narc: V00T0100 H02W0301\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 N1_V01S0100\narc: E1_H01E0101 W3_H06E0203\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: A7 V02N0301\narc: B6 V00B0100\narc: B7 H02E0101\narc: C6 V00T0100\narc: C7 V02N0001\narc: CE2 H02W0101\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 V02N0201\narc: D2 V01S0100\narc: D3 V02S0001\narc: D6 H02E0201\narc: D7 V02N0601\narc: E3_H06E0203 F7\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: M0 V00T0000\narc: M1 H02W0001\narc: M2 V00T0000\narc: M4 H02E0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 F6\narc: S3_V06S0203 F7\narc: V00B0100 Q7\narc: V01S0100 Q4\narc: W1_H02W0601 F6\narc: W3_H06W0203 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0011000011110000\nword: SLICED.K1.INIT 0000000010111000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R8C41:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0103 H01E0101\narc: H00L0000 N1_V02S0001\narc: H00R0000 H02W0601\narc: H00R0100 H02W0501\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 N3_V06S0103\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0501 S1_V02N0401\narc: N3_V06N0003 S3_V06N0003\narc: S1_V02S0601 H02E0601\narc: S3_V06S0203 N3_V06S0203\narc: S3_V06S0303 N3_V06S0203\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02W0201\narc: V00T0100 H02E0101\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 V01N0001\narc: W1_H02W0501 S1_V02N0501\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0401 W3_H06E0203\narc: S1_V02S0701 W3_H06E0203\narc: W1_H02W0301 W3_H06E0003\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0203 E3_H06W0103\narc: CE2 V02N0601\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 E1_H02W0201\narc: D2 H00R0000\narc: D3 V01S0100\narc: E1_H01E0001 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 F1\narc: M0 V00T0000\narc: M1 H00L0000\narc: M2 V00T0000\narc: M4 V00B0100\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0100 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\n\n.tile R8C42:PLC2\narc: E1_H02E0001 S3_V06N0003\narc: E1_H02E0301 E3_H06W0003\narc: E1_H02E0601 E3_H06W0303\narc: H00L0000 V02N0001\narc: H00R0000 V02S0601\narc: H00R0100 H02E0701\narc: N1_V02N0401 H02W0401\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 H01E0101\narc: S1_V02S0001 H06E0003\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 N1_V02S0301\narc: S3_V06S0003 E3_H06W0003\narc: V00B0100 V02N0301\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 H01E0001\narc: W1_H02W0501 H01E0101\narc: E1_H02E0101 W3_H06E0103\narc: H01W0000 W3_H06E0103\narc: S1_V02S0101 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: CE2 H00R0100\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 N1_V01S0000\narc: D1 V02N0201\narc: D2 V02S0001\narc: D3 H00R0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0100 F1\narc: M0 H02E0601\narc: M1 H00L0000\narc: M2 H02E0601\narc: M4 H02E0401\narc: M6 V00B0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R8C43:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: E3_H06E0103 W1_H02E0201\narc: H00L0000 V02N0001\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S3_V06N0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0401 H06E0203\narc: V00B0100 S1_V02N0101\narc: V00T0100 H02E0101\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 V06N0103\narc: W1_H02W0401 V06N0203\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0003 E1_H02W0301\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: CE2 E1_H02W0101\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 V02S0001\narc: D1 V00B0100\narc: D2 V01S0100\narc: D3 V02N0201\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 V00T0100\narc: M1 H00L0000\narc: M2 V00T0100\narc: M4 H02W0401\narc: M6 H02W0401\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: V01S0100 Q4\narc: W3_H06W0103 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R8C44:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 N3_V06S0203\narc: H00L0100 V02N0101\narc: H00R0000 V02N0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 H06W0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 V01N0101\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 V01N0001\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02N0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 W1_H02E0301\narc: W1_H02W0401 V02N0401\narc: E1_H01E0101 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A3 V02N0701\narc: B0 V02S0101\narc: B1 S1_V02N0301\narc: B2 H01W0100\narc: B3 S1_V02N0101\narc: B4 V02S0501\narc: B5 V02S0701\narc: B6 N1_V02S0501\narc: B7 V00T0000\narc: C0 H00R0100\narc: C1 H00L0100\narc: C2 H02W0601\narc: C3 H02E0401\narc: C4 H02E0601\narc: C5 N1_V02S0201\narc: C6 V02N0001\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 V00T0100\narc: D2 H00R0000\narc: D3 H02E0201\narc: D4 V00B0000\narc: D5 E1_H02W0201\narc: D6 E1_H02W0201\narc: D7 E1_H02W0201\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q3\narc: LSR0 H02E0501\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 Q3\narc: S1_V02S0301 F1\narc: S1_V02S0501 F5\narc: S3_V06S0203 F7\narc: S3_V06S0303 F6\narc: V01S0000 F0\narc: V01S0100 F4\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 0000110000000000\nword: SLICEB.K1.INIT 1111111111111110\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R8C45:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 V02N0601\narc: H00L0000 V02S0201\narc: H00L0100 H02W0301\narc: H00R0000 H02W0401\narc: H00R0100 H02W0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 V01N0101\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 H02W0701\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0501 N1_V02S0401\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 E1_H01W0000\narc: V00T0000 S1_V02N0601\narc: V00T0100 E1_H02W0101\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 V01N0001\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0103 S3_V06N0103\narc: E3_H06E0303 W3_H06E0203\narc: A7 H02E0501\narc: B4 H00L0000\narc: B5 V02S0501\narc: B6 V02N0701\narc: B7 H01E0101\narc: C4 V02N0001\narc: C5 S1_V02N0001\narc: C6 V02N0201\narc: C7 V00T0100\narc: CE0 H00R0100\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 H02W0201\narc: D5 H02W0201\narc: D6 H00L0100\narc: D7 V00B0000\narc: E1_H01E0101 F6\narc: E3_H06E0003 Q0\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR1 V00B0100\narc: M0 V00T0000\narc: M2 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V00B0000 F6\narc: V00B0100 F7\narc: V01S0000 Q2\narc: V01S0100 Q0\narc: W3_H06W0003 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 0011000000000000\nword: SLICED.K1.INIT 1100111111001110\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R8C46:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0701 V01N0101\narc: H00R0000 H02E0401\narc: H00R0100 V02S0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 V01N0101\narc: N1_V02N0401 S1_V02N0101\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 E3_H06W0203\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 V01N0101\narc: V00B0000 H02E0601\narc: V00B0100 W1_H02E0701\narc: V00T0000 S1_V02N0401\narc: V00T0100 W1_H02E0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 E3_H06W0203\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0003 E3_H06W0003\narc: A2 V00B0000\narc: B0 H02E0101\narc: B1 V02S0101\narc: B2 H00R0000\narc: B6 H02E0301\narc: B7 E1_H02W0101\narc: C0 V02N0401\narc: C1 H02W0401\narc: C2 H00R0100\narc: C6 H02W0401\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 E1_H02W0201\narc: D2 V02N0001\narc: D6 E1_H02W0201\narc: D7 E1_H02W0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: LSR0 V00B0100\narc: M2 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: S3_V06S0003 F0\narc: S3_V06S0103 F1\narc: S3_V06S0203 F7\narc: S3_V06S0303 F6\narc: W3_H06W0103 Q2\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 1111111111101100\nword: SLICEB.K1.INIT 1111111111111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R8C47:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 V06S0103\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0601 E3_H06W0303\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 E1_H02W0201\narc: H00L0100 V02N0101\narc: H00R0100 H02W0501\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02W0601\narc: S1_V02S0101 H02E0101\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0701 H02W0701\narc: V00B0000 V02S0001\narc: V00T0000 W1_H02E0001\narc: V01S0100 S3_V06N0303\narc: W1_H02W0101 V01N0101\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0401 S3_V06N0203\narc: S1_V02S0001 W3_H06E0003\narc: W3_H06W0103 E3_H06W0103\narc: B0 H01W0100\narc: B2 V02S0301\narc: B4 V00B0100\narc: B6 V01S0000\narc: C0 H00R0100\narc: C1 H00L0100\narc: C2 E1_H02W0601\narc: C3 H00L0100\narc: C4 V00T0000\narc: C5 V02N0001\narc: C6 V02S0201\narc: C7 V02N0001\narc: CE0 H00L0000\narc: CE1 H00L0000\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0001\narc: D1 V02N0201\narc: D2 E1_H02W0001\narc: D3 H02E0001\narc: D4 E1_H02W0001\narc: D5 V00B0000\narc: D6 E1_H02W0001\narc: D7 H02W0001\narc: E1_H01E0001 F5\narc: E1_H02E0701 F5\narc: E3_H06E0003 F3\narc: E3_H06E0103 F1\narc: E3_H06E0203 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q1\narc: LSR0 W1_H02E0501\narc: LSR1 W1_H02E0501\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q3\narc: N1_V02N0101 F1\narc: N3_V06N0003 F3\narc: S1_V02S0501 F5\narc: S3_V06S0003 F0\narc: S3_V06S0103 F2\narc: S3_V06S0203 F4\narc: S3_V06S0303 F6\narc: V00B0100 Q5\narc: V01S0000 Q7\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R8C48:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 N1_V02S0701\narc: E3_H06E0203 N1_V01S0000\narc: E3_H06E0303 N1_V01S0100\narc: H00L0000 H02E0001\narc: H00L0100 H02W0301\narc: H00R0000 H02E0601\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 W1_H02E0701\narc: N3_V06N0003 S3_V06N0303\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0601 H06W0303\narc: S3_V06S0303 E1_H01W0100\narc: V00B0000 V02S0201\narc: V00T0100 V02N0701\narc: W1_H02W0001 N3_V06S0003\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 S1_V02N0701\narc: E1_H01E0101 W3_H06E0203\narc: W3_H06W0003 E1_H02W0001\narc: W3_H06W0303 V06S0303\narc: B0 V02N0301\narc: B1 V02S0301\narc: B2 S1_V02N0301\narc: B3 V02S0101\narc: B4 V00B0100\narc: C0 V02S0601\narc: C1 N1_V02S0601\narc: C2 H00L0100\narc: C3 H00L0000\narc: C4 V00T0100\narc: C5 V02N0201\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 E1_H02W0201\narc: D1 E1_H02W0201\narc: D2 E1_H02W0201\narc: D3 E1_H02W0001\narc: D4 E1_H02W0201\narc: D5 V00B0000\narc: E3_H06E0003 F3\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: LSR1 E1_H02W0501\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 F5\narc: N3_V06N0303 F5\narc: S3_V06S0003 F0\narc: S3_V06S0103 F2\narc: V00B0100 Q5\narc: W1_H02W0401 F4\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R8C49:PLC2\narc: E1_H02E0301 W1_H02E0201\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 W1_H02E0701\narc: H00L0000 V02N0001\narc: H00R0100 V02S0501\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 H01E0101\narc: N1_V02N0401 H02E0401\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 H06E0303\narc: S1_V02S0701 H02E0701\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0101\narc: V00T0000 W1_H02E0001\narc: V00T0100 H02E0301\narc: W1_H02W0001 E1_H01W0000\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 V02N0601\narc: E3_H06E0303 W3_H06E0203\narc: B0 H00R0100\narc: B1 V00B0000\narc: B2 V02S0301\narc: B3 N1_V02S0301\narc: B4 S1_V02N0501\narc: B5 S1_V02N0701\narc: B6 E1_H02W0101\narc: B7 V00B0100\narc: C0 H02W0401\narc: C1 H00L0000\narc: C2 E1_H02W0601\narc: C3 H02W0601\narc: C4 V00T0100\narc: C5 S1_V02N0001\narc: C6 V02N0201\narc: C7 V00T0000\narc: D0 E1_H02W0201\narc: D1 H02W0201\narc: D2 H02W0001\narc: D3 H02W0001\narc: D4 E1_H01W0100\narc: D5 E1_H01W0100\narc: D6 E1_H01W0100\narc: D7 E1_H01W0100\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F1\narc: S1_V02S0501 F7\narc: S3_V06S0003 F3\narc: S3_V06S0103 F2\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V01S0000 F6\narc: V01S0100 F0\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1100110011110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R8C4:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 S1_V02N0601\narc: H00L0100 E1_H02W0301\narc: H00R0000 H02E0401\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 H01E0001\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0103 E3_H06W0103\narc: V00B0100 N1_V02S0101\narc: V00T0100 N1_V02S0501\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0701 S1_V02N0701\narc: A5 V00B0000\narc: B5 S1_V02N0701\narc: C5 S1_V02N0001\narc: CE0 H00R0000\narc: CE1 H00L0100\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D5 H02E0201\narc: E1_H01E0101 Q0\narc: E1_H02E0001 Q2\narc: E1_H02E0701 F5\narc: F5 F5_SLICE\narc: H01W0100 Q0\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 H02E0601\narc: M2 H02E0601\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: V00B0000 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R8C50:PLC2\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0103 V01N0101\narc: H00L0000 V02N0201\narc: H00L0100 V02N0301\narc: H00R0000 N1_V02S0401\narc: H00R0100 E1_H02W0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 V01N0001\narc: N1_V02N0701 H06E0203\narc: N3_V06N0003 H06E0003\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 N1_V01S0100\narc: S1_V02S0401 N3_V06S0203\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 N3_V06S0203\narc: S3_V06S0003 E1_H01W0000\narc: S3_V06S0103 E1_H01W0100\narc: V00B0000 E1_H02W0401\narc: V00B0100 V02N0101\narc: V00T0000 V02S0401\narc: W1_H02W0301 V06S0003\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0401 W3_H06E0203\narc: E1_H02E0501 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: A3 V00B0000\narc: B0 V02S0301\narc: B1 S1_V02N0301\narc: B3 H00R0100\narc: B4 H00R0000\narc: B5 E1_H02W0101\narc: B6 V02S0701\narc: B7 V02S0501\narc: C0 H00L0000\narc: C1 S1_V02N0601\narc: C3 H00L0100\narc: C4 W1_H02E0601\narc: C5 S1_V02N0201\narc: C6 V00T0000\narc: C7 N1_V02S0001\narc: D0 F2\narc: D1 F2\narc: D3 E1_H02W0001\narc: D4 F2\narc: D5 F2\narc: D6 F2\narc: D7 F2\narc: E1_H01E0001 F2\narc: E1_H02E0001 F2\narc: E1_H02E0701 F7\narc: E3_H06E0303 F6\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: H01W0100 F2\narc: M2 V00B0100\narc: N1_V02N0001 F2\narc: S1_V02S0201 F2\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V01S0100 F2\narc: W1_H02W0001 F2\narc: W1_H02W0201 F2\narc: W3_H06W0003 F0\narc: W3_H06W0103 F1\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000110000001000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R8C51:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0601 V02S0601\narc: H00L0000 S1_V02N0001\narc: H00L0100 W1_H02E0301\narc: H00R0000 V02S0401\narc: H00R0100 V02S0701\narc: N1_V02N0001 H01E0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0201 H01E0001\narc: S1_V02S0301 N1_V02S0201\narc: S1_V02S0401 H01E0001\narc: S3_V06S0003 H06E0003\narc: V00B0100 V02S0101\narc: V00T0000 S1_V02N0401\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 V06N0003\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 E1_H02W0601\narc: E1_H01E0001 W3_H06E0003\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0303 W3_H06E0303\narc: B0 H00R0100\narc: B1 V02S0301\narc: B2 N1_V02S0301\narc: B3 H00R0000\narc: B4 N1_V02S0701\narc: B5 V02S0501\narc: B6 V00B0100\narc: B7 H02W0301\narc: C0 E1_H02W0401\narc: C1 H00L0100\narc: C2 H02E0601\narc: C3 H00L0000\narc: C4 V00T0000\narc: C5 H02W0601\narc: C6 V02N0001\narc: C7 S1_V02N0201\narc: D0 H02E0001\narc: D1 H02E0001\narc: D2 H02E0001\narc: D3 H02E0001\narc: D4 H02E0001\narc: D5 H02E0001\narc: D6 H02E0001\narc: D7 H02E0001\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F0\narc: H01W0100 F3\narc: S1_V02S0601 F4\narc: S3_V06S0103 F2\narc: S3_V06S0203 F7\narc: S3_V06S0303 F5\narc: W1_H02W0401 F6\narc: W3_H06W0103 F1\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1100110011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R8C52:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 V02S0101\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V02N0401\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 V06N0303\narc: E3_H06E0003 W1_H02E0001\narc: E3_H06E0103 W1_H02E0201\narc: H00L0100 V02N0101\narc: H00R0000 H02W0601\narc: H00R0100 V02N0501\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 H06E0203\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0301 W1_H02E0301\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 W1_H02E0401\narc: V00B0100 V02N0101\narc: V00T0000 S1_V02N0401\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 V02N0601\narc: N1_V02N0601 W3_H06E0303\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0701 W3_H06E0203\narc: B6 V01S0000\narc: C3 H00L0100\narc: C5 V00B0100\narc: C6 V02N0201\narc: C7 H02E0601\narc: CE0 H00R0000\narc: CE1 V02S0201\narc: CE2 H00R0000\narc: CE3 H02W0101\narc: CLK0 G_HPBX0000\narc: D3 V02N0001\narc: D5 H00R0100\narc: D6 H02E0201\narc: D7 H00L0100\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q5\narc: E1_H02E0701 F5\narc: E3_H06E0303 F5\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F6\narc: LSR0 V00B0000\narc: LSR1 V00T0000\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V02N0501 F7\narc: N3_V06N0203 F7\narc: S1_V02S0501 F5\narc: V01S0000 Q7\narc: V01S0100 Q0\narc: W3_H06W0003 Q3\narc: W3_H06W0203 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R8C53:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0201 V06S0103\narc: E1_H02E0501 V02S0501\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0203 V06S0203\narc: H00L0000 H02E0201\narc: H00R0000 N1_V02S0601\narc: H00R0100 V02S0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0601 H01E0001\narc: S1_V02S0101 S3_V06N0103\narc: S1_V02S0201 H02W0201\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 S3_V06N0203\narc: S3_V06S0003 N3_V06S0303\narc: S3_V06S0203 E1_H01W0000\narc: S3_V06S0303 H06E0303\narc: V00B0000 V02S0001\narc: V00B0100 E1_H02W0501\narc: V00T0100 W1_H02E0301\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 V06S0103\narc: W1_H02W0401 V06N0203\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V06S0203\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0301 W3_H06E0003\narc: W3_H06W0303 V06S0303\narc: W3_H06W0103 E3_H06W0003\narc: B0 V00B0000\narc: B1 N1_V02S0101\narc: B2 H02E0101\narc: B3 H00R0000\narc: B4 H02E0301\narc: B5 H01E0101\narc: C0 S1_V02N0401\narc: C1 H00L0000\narc: C2 V02N0601\narc: C3 H02E0601\narc: C4 V00T0100\narc: C5 E1_H02W0401\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D0 W1_H02E0001\narc: D1 W1_H02E0001\narc: D2 W1_H02E0001\narc: D3 W1_H02E0001\narc: D4 W1_H02E0001\narc: D5 W1_H02E0001\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: LSR1 H02W0301\narc: M6 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: S1_V02S0001 F0\narc: S1_V02S0401 F4\narc: S1_V02S0501 F5\narc: S3_V06S0103 F1\narc: V01S0000 F3\narc: V01S0100 F2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R8C54:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 W1_H02E0501\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0303 W1_H02E0501\narc: H00L0000 H02E0201\narc: H00L0100 S1_V02N0101\narc: H00R0100 V02S0701\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 E1_H01W0000\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 H02W0201\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 N1_V02S0401\narc: V00B0000 E1_H02W0601\narc: V00B0100 W1_H02E0701\narc: V00T0100 E1_H02W0101\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 E1_H02W0301\narc: H01W0000 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: B2 N1_V02S0101\narc: B3 H00R0000\narc: B4 V02S0501\narc: B5 N1_V01S0000\narc: C1 W1_H02E0401\narc: C2 V02S0401\narc: C3 H00L0100\narc: C4 S1_V02N0001\narc: C5 V02N0201\narc: CE0 H00R0100\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 W1_H02E0001\narc: D2 V00T0100\narc: D3 V00T0100\narc: D4 V00B0000\narc: D5 V00B0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 F1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0000 Q6\narc: LSR0 W1_H02E0501\narc: LSR1 E1_H02W0301\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR3 LSR1\narc: S3_V06S0003 F3\narc: S3_V06S0103 F2\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V01S0000 Q1\narc: W1_H02W0101 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R8C55:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 H01E0001\narc: H00L0100 V02N0101\narc: H00R0000 V02S0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 H01E0101\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0701 H02E0701\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 S3_V06N0103\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 V01N0001\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0003 H06E0003\narc: V00B0000 H02W0601\narc: V00B0100 W1_H02E0501\narc: V00T0000 H02W0201\narc: V00T0100 H02W0101\narc: W1_H02W0201 V02S0201\narc: W1_H02W0401 E1_H02W0401\narc: S1_V02S0101 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: B2 H01W0100\narc: B4 V01S0000\narc: B5 N1_V01S0000\narc: B6 V02S0501\narc: C2 H02E0601\narc: C3 H00L0100\narc: C4 V02N0001\narc: C5 V00T0000\narc: C6 S1_V02N0001\narc: C7 V02N0201\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 H02W0001\narc: D4 V00B0000\narc: D5 V00B0000\narc: D6 V00B0000\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: E3_H06E0203 F7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F3\narc: H01W0100 Q3\narc: LSR0 E1_H02W0501\narc: LSR1 H02W0301\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q7\narc: N1_V02N0501 F7\narc: S3_V06S0103 F2\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V01S0000 Q0\narc: V01S0100 F6\narc: W1_H02W0501 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R8C56:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 H01E0001\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0501 W1_H02E0501\narc: H00R0000 V02S0401\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0301 H02W0301\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0601 H01E0001\narc: S1_V02S0101 N1_V02S0101\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 H02E0501\narc: V00B0000 H02E0401\narc: V00B0100 V02S0301\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02N0501\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: A3 V02S0701\narc: B0 V00B0000\narc: B3 V02S0101\narc: B4 V02N0501\narc: B6 V02N0501\narc: C0 S1_V02N0401\narc: C1 H02E0401\narc: C3 S1_V02N0401\narc: C4 V02N0001\narc: C5 H02E0401\narc: C6 V00T0000\narc: C7 V00T0100\narc: D0 S1_V02N0201\narc: D1 H00R0000\narc: D3 S1_V02N0201\narc: D4 V02S0601\narc: D5 V02N0401\narc: D6 V02N0601\narc: D7 H00R0100\narc: E1_H01E0001 F6\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F4\narc: M0 V00B0100\narc: M4 V00B0100\narc: M6 V00B0100\narc: N1_V01N0001 F3\narc: S1_V02S0201 F0\nword: SLICEC.K0.INIT 0000110000111111\nword: SLICEC.K1.INIT 1111000011111111\nword: SLICEA.K0.INIT 0000001111001111\nword: SLICEA.K1.INIT 1111000011111111\nword: SLICED.K0.INIT 0000001111001111\nword: SLICED.K1.INIT 1111000011111111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001001101011111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R8C57:PLC2\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 W1_H02E0601\narc: H00L0000 V02S0201\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 N1_V01S0100\narc: S1_V02S0101 H02E0101\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 S3_V06N0303\narc: S1_V02S0701 H06W0203\narc: V00B0000 V02S0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02N0401\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V06N0003\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 W3_H06E0303\narc: B0 V02S0101\narc: B1 W1_H02E0301\narc: B2 E1_H01W0100\narc: B3 N1_V02S0301\narc: B4 H00L0000\narc: B5 V02S0501\narc: B6 V00B0000\narc: B7 E1_H02W0101\narc: C0 N1_V02S0601\narc: C1 H02W0601\narc: C2 V02N0601\narc: C3 H02E0401\narc: C4 E1_H02W0401\narc: C5 H02W0401\narc: C6 V00B0100\narc: C7 V00T0000\narc: D0 E1_H02W0201\narc: D1 E1_H02W0201\narc: D2 E1_H02W0201\narc: D3 E1_H02W0201\narc: D4 E1_H02W0201\narc: D5 E1_H02W0201\narc: D6 E1_H02W0201\narc: D7 E1_H02W0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: S1_V02S0001 F0\narc: S1_V02S0201 F2\narc: S1_V02S0501 F7\narc: S3_V06S0003 F3\narc: S3_V06S0103 F1\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V01S0100 F6\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R8C58:PLC2\narc: E1_H02E0401 V02N0401\narc: H00R0000 V02S0401\narc: N1_V02N0001 H02W0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H06E0203\narc: S1_V02S0101 H06E0103\narc: V00B0000 H02E0601\narc: V00T0000 W1_H02E0201\narc: V00T0100 W1_H02E0301\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V02N0601\narc: E1_H02E0601 W3_H06E0303\narc: W1_H02W0001 W3_H06E0003\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: CE0 S1_V02N0201\narc: CE1 S1_V02N0201\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: E3_H06E0203 Q4\narc: E3_H06E0303 Q6\narc: H01W0100 Q0\narc: LSR0 W1_H02E0501\narc: LSR1 H02W0501\narc: M0 H02E0601\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R8C59:PLC2\narc: E1_H02E0401 W1_H02E0101\narc: H00L0000 V02S0001\narc: S3_V06S0003 N3_V06S0003\narc: V00B0000 V02N0201\narc: V00B0100 V02N0101\narc: V00T0000 S1_V02N0401\narc: V00T0100 H02W0301\narc: W1_H02W0001 V01N0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 E1_H02W0401\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0701 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: W3_H06W0003 E3_H06W0303\narc: B4 H00R0000\narc: B5 V01S0000\narc: C4 V00B0100\narc: C5 W1_H02E0401\narc: CE0 H00L0000\narc: CE1 H02W0101\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 V00B0000\narc: E3_H06E0103 Q2\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0000 Q6\narc: LSR0 V00T0000\narc: LSR1 H02W0501\narc: M0 H02E0601\narc: M2 W1_H02E0601\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR1\narc: S3_V06S0203 F4\narc: S3_V06S0303 F5\narc: V01S0000 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R8C5:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 W1_H02E0301\narc: H00L0000 H02E0001\narc: H00R0000 V02S0601\narc: H00R0100 H02W0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0101 E1_H02W0101\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02S0101\narc: V00T0000 S1_V02N0401\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0401 S1_V02N0401\narc: A7 H00L0000\narc: B1 W1_H02E0101\narc: B3 H02E0301\narc: B7 H01E0101\narc: C1 V02S0401\narc: C3 H00R0100\narc: C7 V00B0100\narc: CE2 H02W0101\narc: CLK0 G_HPBX0000\narc: D0 H02E0001\narc: D1 H00R0000\narc: D2 V02N0201\narc: D3 H00R0000\narc: D7 E1_H02W0201\narc: E1_H01E0001 F7\narc: E1_H01E0101 Q0\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00B0000\narc: LSR1 V00B0000\narc: M0 V00T0000\narc: M2 V00T0000\narc: M4 E1_H01E0101\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q2\narc: S1_V02S0201 Q2\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111000011001100\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R8C60:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0601 S1_V02N0601\narc: H00L0000 V02S0201\narc: H00R0000 V02S0401\narc: H00R0100 H02E0701\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 H01E0101\narc: V00B0000 W1_H02E0601\narc: V00T0000 S1_V02N0401\narc: W1_H02W0101 H01E0101\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: E1_H02E0501 W3_H06E0303\narc: S3_V06S0203 W3_H06E0203\narc: W3_H06W0203 E1_H01W0000\narc: B2 H00L0000\narc: B3 N1_V02S0101\narc: C2 V02N0601\narc: C3 W1_H02E0401\narc: CE0 H00R0100\narc: CE2 H00R0000\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 V02N0201\narc: D3 V02N0201\narc: E1_H02E0401 Q4\narc: E3_H06E0003 Q0\narc: E3_H06E0303 Q6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR0 V00T0000\narc: LSR1 E1_H02W0501\narc: M0 W1_H02E0601\narc: M4 V00B0000\narc: M6 H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: S3_V06S0003 F3\narc: S3_V06S0103 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R8C61:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0401 E1_H01W0000\narc: E3_H06E0003 V06S0003\narc: H00R0000 V02S0601\narc: H00R0100 W1_H02E0701\narc: V00B0000 V02N0001\narc: V00B0100 H02W0701\narc: V00T0100 W1_H02E0101\narc: W1_H02W0401 S1_V02N0401\narc: E1_H01E0101 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE2 V02S0601\narc: CE3 H00R0100\narc: CLK0 G_HPBX0000\narc: E1_H02E0001 Q0\narc: E1_H02E0601 Q6\narc: H01W0100 Q4\narc: LSR0 H02W0301\narc: LSR1 H02E0501\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 W1_H02E0401\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: V01S0100 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R8C62:PLC2\narc: H00L0000 H02W0201\narc: H00L0100 S1_V02N0301\narc: H00R0000 W1_H02E0401\narc: H00R0100 H02W0501\narc: V00B0000 V02N0201\narc: V00B0100 E1_H02W0701\narc: V00T0000 H02E0001\narc: W1_H02W0301 V02N0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0701 H01E0101\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0201 W3_H06E0103\narc: E1_H02E0401 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: B0 H02W0301\narc: B1 H02E0101\narc: B2 V02S0101\narc: B3 H00R0000\narc: B4 W1_H02E0301\narc: B5 W1_H02E0101\narc: B6 V00B0100\narc: B7 V00T0000\narc: C0 H00L0100\narc: C1 H00R0100\narc: C2 V02N0401\narc: C3 H00L0000\narc: C4 H02E0401\narc: C5 H02W0601\narc: C6 W1_H02E0601\narc: C7 H02W0401\narc: D0 V02N0201\narc: D1 V02N0201\narc: D2 V02N0201\narc: D3 V02N0201\narc: D4 V00B0000\narc: D5 V00B0000\narc: D6 V00B0000\narc: D7 V00B0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: S1_V02S0201 F0\narc: S1_V02S0701 F5\narc: S3_V06S0003 F3\narc: S3_V06S0103 F1\narc: S3_V06S0203 F4\narc: S3_V06S0303 F6\narc: V01S0000 F7\narc: V01S0100 F2\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R8C63:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 W1_H02E0601\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 V02N0601\n\n.tile R8C64:PLC2\narc: H00L0000 W1_H02E0201\narc: H00R0000 V02S0601\narc: H00R0100 E1_H02W0501\narc: V00B0100 H02E0701\narc: H01W0100 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: B0 V02S0301\narc: B1 V02S0101\narc: B2 H00R0000\narc: B3 H00R0100\narc: B4 V02N0501\narc: B5 E1_H02W0301\narc: B6 H02W0101\narc: B7 V00B0100\narc: C0 H02E0601\narc: C1 V02N0401\narc: C2 H00L0000\narc: C3 V02N0601\narc: C4 V02N0201\narc: C5 S1_V02N0201\narc: C6 H02W0401\narc: C7 W1_H02E0401\narc: D0 H02E0201\narc: D1 H02E0201\narc: D2 H02E0201\narc: D3 H02E0201\narc: D4 H02E0201\narc: D5 H02E0201\narc: D6 H02E0201\narc: D7 H02E0201\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: S1_V02S0001 F2\narc: S1_V02S0501 F5\narc: S3_V06S0003 F3\narc: S3_V06S0103 F1\narc: S3_V06S0203 F7\narc: S3_V06S0303 F6\narc: V01S0000 F0\narc: V01S0100 F4\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1100110011110000\nword: SLICEC.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 1100110011110000\nword: SLICED.K1.INIT 1100110011110000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R8C65:PLC2\narc: W1_H02W0401 V02N0401\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0303 E3_H06W0203\n\n.tile R8C66:PLC2\narc: W1_H02W0301 W3_H06E0003\narc: W1_H02W0501 W3_H06E0303\n\n.tile R8C67:PLC2\narc: E1_H02E0001 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\n\n.tile R8C68:PLC2\narc: E3_H06E0003 W3_H06E0003\n\n.tile R8C69:PLC2\narc: E1_H02E0101 W1_H02E0001\n\n.tile R8C6:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 V02N0201\narc: H00R0000 H02E0601\narc: H00R0100 E1_H02W0701\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 E3_H06W0003\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 E1_H02W0701\narc: N3_V06N0003 E3_H06W0003\narc: N3_V06N0103 E3_H06W0103\narc: S1_V02S0201 N1_V02S0201\narc: S3_V06S0103 H06W0103\narc: V00B0000 W1_H02E0601\narc: V00B0100 W1_H02E0501\narc: V00T0100 S1_V02N0501\narc: W1_H02W0101 E1_H02W0101\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0501 N1_V02S0501\narc: W1_H02W0601 E1_H02W0301\narc: W3_H06W0103 E3_H06W0103\narc: A1 E1_H02W0501\narc: A3 W1_H02E0701\narc: A5 E1_H01W0000\narc: A6 F5\narc: A7 V02N0101\narc: B1 V02N0301\narc: B2 H00R0000\narc: B3 V02S0301\narc: B5 H00L0000\narc: B6 H02E0101\narc: B7 W1_H02E0301\narc: C1 E1_H02W0401\narc: C2 V02S0601\narc: C3 V02N0601\narc: C5 V00T0100\narc: C6 H01E0001\narc: C7 S1_V02N0001\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D2 V01S0100\narc: D3 H02E0001\narc: D5 H00R0100\narc: D6 H00L0100\narc: D7 V00B0000\narc: E3_H06E0103 Q2\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0100 F7\narc: LSR1 H02E0301\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V01S0000 F6\narc: V01S0100 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0011111111111111\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R8C70:PLC2\narc: E1_H02E0101 V02S0101\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0701 V02N0701\narc: S3_V06S0303 H06E0303\n\n.tile R8C7:PLC2\narc: E1_H02E0401 N1_V01S0000\narc: H00R0000 E1_H02W0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0201 E1_H02W0201\narc: V00B0000 H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 V02S0601\narc: V00T0100 V02S0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0501 S1_V02N0501\narc: B5 V01S0000\narc: C5 V02N0201\narc: CE0 H02W0101\narc: CE1 E1_H02W0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 V00B0000\narc: D5 V02S0401\narc: E1_H01E0001 Q6\narc: E1_H01E0101 Q2\narc: E1_H02E0601 Q4\narc: F4 F5C_SLICE\narc: H01W0000 Q0\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M0 V00T0100\narc: M2 V00T0000\narc: M4 W1_H02E0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q4\narc: N1_V02N0601 Q4\narc: V01S0000 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111100000000\nword: SLICEC.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R8C8:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0601 E3_H06W0303\narc: H00L0000 N1_V02S0201\narc: H00R0100 H02W0701\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0401 H02E0401\narc: N3_V06N0103 S1_V02N0101\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0501 E3_H06W0303\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E1_H01W0100\narc: V00B0100 V02S0301\narc: V00T0100 S1_V02N0701\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0301 E3_H06W0003\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0501 H01E0101\narc: W1_H02W0701 E1_H01W0100\narc: W3_H06W0203 E1_H01W0000\narc: B1 E1_H02W0301\narc: C1 H00L0000\narc: C5 H01E0001\narc: CE1 V02N0201\narc: CE3 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 V02S0001\narc: D5 H00R0100\narc: F0 F5A_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q0\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: M0 V00T0100\narc: M2 H02E0601\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q0\narc: S1_V02S0401 Q6\narc: S1_V02S0701 F5\narc: V01S0000 Q2\narc: W1_H02W0601 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 1111111100000000\nword: SLICEA.K1.INIT 1111000011001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R8C9:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0301 V06S0003\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 E3_H06W0303\narc: E1_H02E0701 V06S0203\narc: H00L0100 S1_V02N0101\narc: N1_V02N0301 H01E0101\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0001 E3_H06W0003\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 N1_V01S0100\narc: S3_V06S0103 H06W0103\narc: V00B0000 V02S0201\narc: V00B0100 E1_H02W0701\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 S1_V02N0301\narc: N1_V02N0101 W3_H06E0103\narc: C0 V02N0401\narc: C1 S1_V02N0401\narc: C4 V00B0100\narc: C5 S1_V02N0001\narc: C6 V00B0100\narc: C7 S1_V02N0001\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 H02W0201\narc: D4 H02W0001\narc: D5 E1_H02W0201\narc: D6 H00R0100\narc: D7 H02E0201\narc: E1_H01E0001 F5\narc: E1_H01E0101 Q2\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F7\narc: H01W0000 F6\narc: H01W0100 F1\narc: LSR0 V00B0000\narc: M2 H02E0601\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F7\narc: N1_V01N0101 Q2\narc: N1_V02N0001 F0\narc: N1_V02N0401 F6\narc: N1_V02N0501 F7\narc: N3_V06N0003 F0\narc: N3_V06N0103 F1\narc: N3_V06N0203 F4\narc: N3_V06N0303 F5\narc: S1_V02S0101 F1\narc: S3_V06S0203 F7\narc: S3_V06S0303 F5\narc: V01S0000 F1\narc: V01S0100 F6\narc: W1_H02W0201 F0\narc: W1_H02W0501 F7\narc: W1_H02W0601 F4\narc: W1_H02W0701 F5\narc: W3_H06W0003 F0\narc: W3_H06W0103 F1\narc: W3_H06W0203 F4\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0000111100000000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R9C10:PLC2\narc: E1_H02E0301 V02S0301\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0501 N1_V01S0100\narc: S1_V02S0401 V01N0001\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0203 E3_H06W0203\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 V02N0501\narc: W3_H06W0203 E3_H06W0203\narc: C0 H00L0100\narc: C1 H02E0401\narc: C4 V02N0201\narc: C5 H02E0401\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 V02N0001\narc: D4 H00R0100\narc: D5 H02E0001\narc: D7 V02S0401\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H00R0100 F5\narc: H01W0000 F5\narc: H01W0100 F4\narc: LSR1 V00B0100\narc: M2 H02W0601\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V02N0001 F0\narc: N1_V02N0201 Q2\narc: N1_V02N0601 F4\narc: N3_V06N0103 F1\narc: N3_V06N0303 F5\narc: S3_V06S0303 F5\narc: V00B0100 F7\narc: W1_H02W0001 F0\narc: W1_H02W0101 F1\narc: W3_H06W0003 F0\narc: W3_H06W0103 F1\narc: W3_H06W0303 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000111100000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R9C11:PLC2\narc: E1_H02E0301 N1_V01S0100\narc: H00R0000 V02N0401\narc: N1_V02N0501 E1_H01W0100\narc: V00B0000 N1_V02S0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 N1_V02S0601\narc: V00T0100 N1_V02S0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0601 V01N0001\narc: B1 V00T0000\narc: B3 H02E0301\narc: B5 H00R0000\narc: B7 N1_V01S0000\narc: C1 H02W0401\narc: C3 H02W0401\narc: C5 H02W0401\narc: C7 H02W0401\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D3 V00B0100\narc: D5 V02S0601\narc: D7 V00B0000\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q5\narc: N1_V02N0101 Q1\narc: N1_V02N0301 Q3\narc: N1_V02N0701 Q7\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111110000001100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110000001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111110000001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000001100\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R9C12:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: H00L0100 V02S0301\narc: H00R0000 V02S0401\narc: H00R0100 N1_V02S0701\narc: N1_V02N0601 E1_H02W0601\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0601 N1_V02S0601\narc: S3_V06S0203 H06W0203\narc: V00B0100 N1_V02S0101\narc: V00T0000 S1_V02N0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 E3_H06W0303\narc: W1_H02W0701 E3_H06W0203\narc: B1 H02E0301\narc: B3 N1_V02S0301\narc: B5 H00R0000\narc: B7 S1_V02N0501\narc: C1 S1_V02N0401\narc: C3 S1_V02N0401\narc: C5 V00T0000\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: D3 V00T0100\narc: D5 H00R0100\narc: D7 H00L0100\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q5\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0101 Q1\narc: N1_V02N0301 Q3\narc: N1_V02N0501 Q7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000001100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110000001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111110000001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111110000001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R9C13:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0301 E1_H01W0100\narc: H00L0000 V02S0001\narc: H00R0000 N1_V02S0401\narc: H00R0100 N1_V02S0501\narc: N1_V02N0601 H02W0601\narc: S1_V02S0201 H06E0103\narc: S3_V06S0103 H06E0103\narc: V00B0000 N1_V02S0001\narc: V00B0100 N1_V02S0101\narc: B1 V02S0101\narc: B3 H00L0000\narc: B5 S1_V02N0501\narc: B7 V02S0501\narc: C1 H02E0401\narc: C3 H02E0401\narc: C5 H02E0401\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D3 V00B0100\narc: D5 V00B0000\narc: D7 H00R0100\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q1\narc: N1_V02N0101 Q3\narc: N1_V02N0501 Q7\narc: N1_V02N0701 Q5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111110000001100\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111110000001100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111110000001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R9C14:PLC2\narc: H00L0000 E1_H02W0001\narc: H00R0000 V02N0401\narc: N1_V02N0401 E1_H02W0401\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 E1_H01W0000\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 H06W0303\narc: V00B0000 V02N0201\narc: V00B0100 E1_H02W0701\narc: V00T0000 S1_V02N0401\narc: V00T0100 V02S0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0401 V01N0001\narc: W1_H02W0601 E1_H02W0301\narc: E3_H06E0103 W3_H06E0003\narc: B1 V00T0000\narc: B7 V02S0501\narc: C0 H00L0000\narc: C1 H00L0000\narc: C6 V02S0001\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D0 V02S0201\narc: D1 H00R0000\narc: D3 N1_V02S0201\narc: D6 E1_H02W0001\narc: D7 E1_H02W0001\narc: E1_H01E0001 F6\narc: E1_H02E0201 F0\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F6 F5D_SLICE\narc: H01W0100 F3\narc: LSR0 H02E0301\narc: M0 V00B0100\narc: M4 V00B0000\narc: M6 E1_H02W0401\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N3_V06N0203 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000011111111\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 0011001100001111\nword: SLICEA.K0.INIT 1111000011111111\nword: SLICEA.K1.INIT 0000001111110011\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R9C15:PLC2\narc: E1_H02E0001 H01E0001\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0601 S3_V06N0303\narc: E1_H02E0701 S1_V02N0701\narc: H00L0100 H02W0301\narc: H00R0000 V02N0601\narc: H00R0100 V02S0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0301 H02W0301\narc: N1_V02N0501 S3_V06N0303\narc: S1_V02S0401 S3_V06N0203\narc: V00B0100 S1_V02N0101\narc: V00T0000 H02W0201\narc: V00T0100 E1_H02W0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 E1_H02W0101\narc: N1_V02N0401 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: B5 V00B0100\narc: C0 N1_V01N0001\narc: C1 H00L0100\narc: C5 V00T0000\narc: C6 E1_H01E0101\narc: C7 V02N0001\narc: CLK0 G_HPBX0000\narc: D0 N1_V01S0000\narc: D1 H00R0000\narc: D5 W1_H02E0001\narc: D6 H00R0100\narc: D7 V02N0601\narc: E1_H01E0001 Q5\narc: E1_H01E0101 F7\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: LSR1 V00T0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 F1\narc: N1_V02N0601 F6\narc: N1_V02N0701 F7\narc: N3_V06N0303 F6\narc: V01S0100 F1\narc: W3_H06W0003 F0\narc: W3_H06W0303 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100000011111111\nword: SLICED.K0.INIT 1111000000000000\nword: SLICED.K1.INIT 0000000000001111\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R9C16:PLC2\narc: E1_H02E0101 E3_H06W0103\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 N1_V01S0000\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 H01E0101\narc: H00L0100 H02W0301\narc: H00R0000 V02N0601\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 H01E0001\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0501 N1_V02S0501\narc: S3_V06S0303 H06W0303\narc: V00B0100 H02E0701\narc: W1_H02W0001 S3_V06N0003\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0701 S3_V06N0203\narc: W3_H06W0203 E3_H06W0203\narc: A1 E1_H01E0001\narc: B1 E1_H01W0100\narc: B2 H00R0000\narc: C1 H00L0100\narc: C2 H02E0401\narc: C3 E1_H02W0401\narc: C5 V02S0201\narc: C7 V02S0001\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: D2 S1_V02N0001\narc: D3 H02W0001\narc: D5 H02W0001\narc: D7 H02W0001\narc: E1_H01E0001 Q3\narc: E1_H02E0001 F2\narc: E3_H06E0003 F0\narc: E3_H06E0103 F2\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V02N0501 Q7\narc: V00T0000 F2\narc: W3_H06W0303 Q5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 1111110011111111\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R9C17:PLC2\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 V02N0501\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 S1_V02N0201\narc: H00R0000 V02S0401\narc: H00R0100 S1_V02N0501\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 V01N0101\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 H02W0601\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02W0201\narc: V00T0100 V02N0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V06S0003\narc: W1_H02W0301 N1_V02S0301\narc: W3_H06W0203 S3_V06N0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\narc: A1 V02S0501\narc: A4 S1_V02N0301\narc: A5 E1_H02W0501\narc: B0 V00B0000\narc: B1 H02E0101\narc: B2 W1_H02E0301\narc: B3 H00R0100\narc: B4 V00B0100\narc: B5 V02N0501\narc: C0 H02E0601\narc: C1 V02N0601\narc: C2 H02E0601\narc: C3 H00L0000\narc: C4 V02S0001\narc: C5 V00T0000\narc: CLK0 G_HPBX0000\narc: D0 H02E0201\narc: D1 V00T0100\narc: D2 W1_H02E0001\narc: D3 H00R0000\narc: D4 H02W0001\narc: D5 E1_H02W0001\narc: E1_H01E0001 F1\narc: E1_H01E0101 F3\narc: E1_H02E0601 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q2\narc: LSR0 H02W0301\narc: LSR1 H02W0301\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F5\narc: N1_V01N0101 Q0\narc: W1_H02W0101 F3\nword: SLICEA.K0.INIT 1100000011111111\nword: SLICEA.K1.INIT 0001000000000000\nword: SLICEB.K0.INIT 1100000011111111\nword: SLICEB.K1.INIT 1100111111111111\nword: SLICEC.K0.INIT 0100110000000000\nword: SLICEC.K1.INIT 0000100100000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R9C18:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 E3_H06W0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 N3_V06S0203\narc: E3_H06E0103 V01N0101\narc: E3_H06E0203 H01E0001\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 E3_H06W0103\narc: N1_V02N0301 N1_V01S0100\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 E1_H01W0000\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0101 H02E0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0501 E3_H06W0303\narc: S1_V02S0601 H06E0303\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0001\narc: V00B0100 H02E0501\narc: V00T0100 S1_V02N0701\narc: W1_H02W0001 V02S0001\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 S1_V02N0401\narc: W1_H02W0601 V02S0601\narc: W3_H06W0203 E3_H06W0203\narc: W3_H06W0303 E3_H06W0303\narc: A6 H00R0000\narc: A7 H00R0000\narc: B6 V00B0100\narc: B7 V00B0100\narc: C6 H02W0401\narc: C7 H02W0401\narc: CLK0 G_HPBX0000\narc: D6 H01W0000\narc: D7 H01W0000\narc: E1_H01E0101 Q0\narc: E1_H02E0601 Q4\narc: E3_H06E0003 Q0\narc: F6 F5D_SLICE\narc: H00R0000 Q4\narc: H01W0100 Q0\narc: M0 V00B0000\narc: M4 V00T0100\narc: M6 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: N1_V01N0101 Q4\narc: S1_V02S0401 F6\narc: V00T0000 Q0\narc: V01S0000 Q0\narc: V01S0100 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1011101010101010\nword: SLICED.K1.INIT 1010101110111000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R9C19:PLC2\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0701 V02S0701\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 S3_V06N0203\narc: E3_H06E0303 W1_H02E0601\narc: H00L0100 W1_H02E0301\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 N3_V06S0003\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0301 V01N0101\narc: S1_V02S0401 H06E0203\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 H02E0601\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02N0601\narc: V00T0100 V02S0501\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0501 H01E0101\narc: W3_H06W0303 E3_H06W0203\narc: A1 E1_H01E0001\narc: A2 H02W0501\narc: A7 V02N0301\narc: B1 V00B0000\narc: B2 S1_V02N0101\narc: B7 H02E0301\narc: C1 H00L0100\narc: C2 H02E0401\narc: C7 V00T0100\narc: CLK0 G_HPBX0000\narc: D1 H02E0201\narc: D2 H00R0000\narc: D7 H00R0100\narc: E1_H01E0001 Q4\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F6 F5D_SLICE\narc: H00R0000 F6\narc: H01W0000 Q4\narc: H01W0100 F0\narc: M0 V00T0000\narc: M2 V00B0100\narc: M4 W1_H02E0401\narc: M6 H02W0401\narc: MUXCLK2 CLK0\narc: N1_V02N0601 Q4\narc: S3_V06S0103 F2\narc: V01S0000 Q4\narc: W1_H02W0401 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111111111111111\nword: SLICEA.K1.INIT 1010111111110111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1111111100110111\nword: SLICEB.K0.INIT 0000000000000001\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R9C20:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0601 W1_H02E0601\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0701 H06E0203\narc: S1_V02S0001 H02W0001\narc: S1_V02S0701 H02W0701\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 N1_V02S0201\narc: V00B0100 H02E0701\narc: V00T0000 H02E0201\narc: V00T0100 E1_H02W0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 E1_H02W0501\narc: S3_V06S0103 W3_H06E0103\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: B4 H02E0301\narc: C4 V00B0100\narc: C5 H02E0401\narc: CE0 H00R0000\narc: CE1 W1_H02E0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 H00R0100\narc: D5 W1_H02E0001\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00R0000 F4\narc: H00R0100 F5\narc: H01W0100 Q6\narc: LSR0 V00T0100\narc: M0 V00T0000\narc: M2 V00B0000\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q0\narc: N3_V06N0303 F5\narc: S3_V06S0003 Q0\narc: S3_V06S0303 Q6\narc: V01S0100 Q2\narc: W1_H02W0701 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100000000000000\nword: SLICEC.K1.INIT 0000000011110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET SET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R9C21:PLC2\narc: E1_H02E0601 V02N0601\narc: H00L0100 V02S0301\narc: N1_V02N0001 H02W0001\narc: N1_V02N0501 E1_H02W0501\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0501 E1_H02W0501\narc: S3_V06S0103 E3_H06W0103\narc: V00B0000 S1_V02N0001\narc: V00B0100 E1_H02W0701\narc: V00T0100 H02W0101\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0401 V02S0401\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0203 E3_H06W0203\narc: CE1 H00L0100\narc: CE2 H02E0101\narc: CLK0 G_HPBX0000\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M2 V00B0100\narc: M4 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: V01S0000 Q4\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R9C22:PLC2\narc: E3_H06E0003 S3_V06N0003\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 E1_H02W0201\narc: H00R0000 V02S0401\narc: H00R0100 H02E0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 E1_H01W0000\narc: V00B0000 V02N0001\narc: V00B0100 V02S0101\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02N0701\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V02N0001\narc: W1_H02W0101 V02N0101\narc: W1_H02W0501 E3_H06W0303\narc: E1_H02E0601 W3_H06E0303\narc: N1_V02N0201 W3_H06E0103\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0203 E3_H06W0203\narc: A1 H00L0000\narc: A3 N1_V02S0501\narc: A4 V02S0301\narc: A5 V00T0100\narc: A6 V02N0301\narc: A7 V02N0301\narc: B1 E1_H02W0301\narc: B2 E1_H01W0100\narc: B3 H00R0000\narc: B4 V02S0701\narc: B5 F1\narc: B6 E1_H02W0301\narc: B7 E1_H02W0301\narc: C1 V02N0601\narc: C2 H00L0100\narc: C3 H02W0401\narc: C4 H02W0601\narc: C5 F6\narc: C6 W1_H02E0601\narc: C7 W1_H02E0601\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 V02S0001\narc: D3 V00B0100\narc: D4 W1_H02E0201\narc: D5 H00R0100\narc: D6 V02N0601\narc: D7 V02N0601\narc: E1_H01E0101 F4\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00L0100 F3\narc: LSR0 V00B0000\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0101 F5\narc: W3_H06W0103 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001000000000\nword: SLICEC.K0.INIT 1101000011110000\nword: SLICEC.K1.INIT 1100110000001110\nword: SLICEB.K0.INIT 0011111111111111\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0101100100001001\nword: SLICED.K1.INIT 0011101011010111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R9C23:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0103 H01E0101\narc: E3_H06E0203 N1_V01S0000\narc: H00R0000 H02W0401\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0501 N1_V01S0100\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0201 E1_H02W0201\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02N0101\narc: V00T0100 V02S0701\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0401 W3_H06E0203\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0003 E1_H01W0000\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A5 V00T0000\narc: B5 H00R0000\narc: C3 E1_H02W0601\narc: C5 V02N0001\narc: CE0 V02S0201\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D5 V00B0000\narc: E1_H02E0301 F3\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F3\narc: H01W0100 F5\narc: LSR0 V00B0100\narc: M0 W1_H02E0601\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F3\narc: N3_V06N0003 F3\narc: V00T0000 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R9C24:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0301 V02N0301\narc: H00L0100 H02E0301\narc: H00R0000 W1_H02E0601\narc: H00R0100 H02E0701\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 N1_V01S0000\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 H02E0401\narc: V00B0100 H02E0701\narc: V00T0000 V02N0601\narc: V00T0100 H02E0101\narc: W1_H02W0001 E1_H01W0000\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0301 W3_H06E0003\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0203 E3_H06W0103\narc: B1 H02E0101\narc: B5 H02E0101\narc: C0 H02E0601\narc: C1 H00R0100\narc: C4 E1_H01E0101\narc: C5 V00B0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D1 H00R0000\narc: D4 V02N0401\narc: D5 V00B0000\narc: E1_H01E0101 F5\narc: E1_H02E0101 F1\narc: E1_H02E0201 Q2\narc: E1_H02E0501 F5\narc: E1_H02E0601 Q6\narc: E1_H02E0701 F5\narc: E3_H06E0003 F0\narc: E3_H06E0103 F1\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F1\narc: H01W0100 F1\narc: M2 V00T0100\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0401 F4\narc: N1_V02N0701 F5\narc: S1_V02S0501 F5\narc: S3_V06S0103 F1\narc: S3_V06S0303 F5\narc: V01S0000 F4\narc: W1_H02W0101 F1\narc: W1_H02W0201 Q2\narc: W1_H02W0401 Q6\narc: W3_H06W0103 Q2\narc: W3_H06W0303 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1111000000000000\nword: SLICEA.K1.INIT 0000110000000000\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000110000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R9C25:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0103 S3_V06N0103\narc: H00R0000 S1_V02N0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0001 V01N0001\narc: S1_V02S0501 S3_V06N0303\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 V02N0201\narc: V00B0100 H02W0701\narc: V00T0100 V02S0701\narc: V01S0100 S3_V06N0303\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0601 V02N0601\narc: E1_H02E0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0203 E3_H06W0103\narc: B5 V00B0100\narc: C3 H00R0100\narc: C5 V00T0000\narc: CE0 H00L0100\narc: CE2 H00R0000\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0000\narc: D3 V00T0100\narc: D5 H02E0001\narc: E3_H06E0303 Q6\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H00L0100 F3\narc: H01W0000 Q5\narc: LSR0 V00B0000\narc: M0 H02W0601\narc: M6 H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0101 Q0\narc: N1_V02N0401 Q6\narc: S1_V02S0601 Q6\narc: S3_V06S0303 Q6\narc: V00T0000 Q0\narc: W1_H02W0701 Q5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111110000001100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R9C26:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 V06N0203\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0303 W1_H02E0501\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0501 W1_H02E0501\narc: V00B0000 E1_H02W0401\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 S3_V06N0203\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: A0 S1_V02N0701\narc: A5 V00T0100\narc: B0 V01N0001\narc: B5 V00B0100\narc: B6 V00B0100\narc: C0 V02N0401\narc: C3 H00R0100\narc: C5 E1_H01E0101\narc: C6 V00T0100\narc: CE1 H02E0101\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V02N0201\narc: D3 V00T0100\narc: D5 H02W0001\narc: D6 H02W0001\narc: D7 H00R0100\narc: E1_H01E0101 Q5\narc: E1_H02E0501 Q5\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00R0100 Q7\narc: H01W0100 Q5\narc: LSR0 V00T0000\narc: LSR1 V00T0000\narc: M0 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: S1_V02S0701 Q5\narc: V00B0100 Q7\narc: V00T0000 F0\narc: V00T0100 Q3\narc: V01S0000 F6\nword: SLICED.K0.INIT 1111110000000011\nword: SLICED.K1.INIT 0000000011111111\nword: SLICEA.K0.INIT 1111111111111110\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111000011110100\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1111000000001111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R9C27:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 E3_H06W0303\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 W1_H02E0701\narc: E3_H06E0303 W1_H02E0601\narc: H00R0000 H02E0401\narc: H00R0100 H02E0701\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0201 H02E0201\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 V01N0001\narc: S3_V06S0003 H06E0003\narc: V00B0100 H02W0501\narc: V00T0000 V02N0401\narc: W1_H02W0001 V02N0001\narc: W1_H02W0701 V02S0701\narc: H01W0100 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: E3_H06E0003 W3_H06E0303\narc: W3_H06W0203 E3_H06W0103\narc: A5 H02E0501\narc: B5 S1_V02N0501\narc: B7 V01S0000\narc: C1 H02W0401\narc: C2 V02N0401\narc: C3 H00L0000\narc: C5 V02N0201\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 V02N0201\narc: D3 H02W0201\narc: D5 H02E0001\narc: D6 H00R0100\narc: D7 E1_H01W0100\narc: E1_H01E0001 F3\narc: E1_H01E0101 Q7\narc: E1_H02E0601 F6\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 F2\narc: LSR1 V00T0100\narc: M4 V00T0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 F2\narc: N3_V06N0103 F2\narc: S1_V02S0001 F2\narc: S1_V02S0401 F4\narc: S3_V06S0103 F2\narc: S3_V06S0203 Q7\narc: V00T0100 F1\narc: V01S0000 Q7\narc: V01S0100 F4\narc: W3_H06W0103 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111111111110000\nword: SLICEB.K0.INIT 1111000000001111\nword: SLICEB.K1.INIT 1111111100001111\nword: SLICED.K0.INIT 1111111100001111\nword: SLICED.K1.INIT 1100111111001100\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000010000000111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R9C28:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 N1_V01S0000\narc: E1_H02E0601 V02N0601\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 H01E0001\narc: H00L0100 V02S0101\narc: H00R0000 H02E0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 V01N0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H06E0303\narc: N1_V02N0701 S1_V02N0701\narc: S1_V02S0001 H01E0001\narc: S1_V02S0501 H06W0303\narc: S1_V02S0601 H06E0303\narc: S3_V06S0003 H01E0001\narc: S3_V06S0303 H06E0303\narc: V00B0000 H02W0401\narc: V00T0000 S1_V02N0601\narc: V00T0100 V02N0501\narc: W1_H02W0201 V02N0201\narc: W1_H02W0401 V02N0401\narc: S3_V06S0103 W3_H06E0103\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0203 E3_H06W0203\narc: A7 S1_V02N0101\narc: B5 V00B0100\narc: B7 V00B0000\narc: C4 Q4\narc: C5 H02E0401\narc: C7 W1_H02E0601\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 H00R0100\narc: D5 H00R0100\narc: D7 V02N0601\narc: E1_H01E0001 Q2\narc: E1_H02E0701 F7\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q4\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M0 H02W0601\narc: M2 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0001 Q0\narc: N1_V01N0101 Q2\narc: S1_V02S0201 Q0\narc: V00B0100 Q5\narc: W1_H02W0501 Q5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111100001111\nword: SLICEC.K1.INIT 1111111111000011\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R9C29:PLC2\narc: E1_H02E0301 V06S0003\narc: E1_H02E0601 E1_H01W0000\narc: E3_H06E0303 V06S0303\narc: H00R0000 H02E0601\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H06E0303\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0601 H06E0303\narc: S3_V06S0003 H06W0003\narc: V00B0000 E1_H02W0601\narc: V00B0100 H02W0701\narc: V00T0000 H02W0001\narc: V00T0100 H02W0101\narc: W1_H02W0401 N1_V02S0401\narc: W1_H02W0601 N1_V02S0601\narc: E1_H02E0001 W3_H06E0003\narc: E1_H02E0701 W3_H06E0203\narc: N1_V02N0401 W3_H06E0203\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0303 E3_H06W0203\narc: A0 W1_H02E0501\narc: A2 V02N0501\narc: A3 H01E0001\narc: A4 H02E0701\narc: A5 S1_V02N0301\narc: A6 S1_V02N0101\narc: A7 N1_V01N0101\narc: B0 V00T0000\narc: B1 V02N0101\narc: B2 H00R0000\narc: B3 E1_H02W0301\narc: B4 V02N0701\narc: B5 V02S0501\narc: B6 S1_V02N0501\narc: B7 V00B0100\narc: C0 H00L0100\narc: C1 N1_V01S0100\narc: C2 N1_V01N0001\narc: C3 V02N0401\narc: C4 E1_H01E0101\narc: C5 V00T0000\narc: C6 V00T0100\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D0 S1_V02N0201\narc: D1 S1_V02N0001\narc: D2 V02S0001\narc: D3 W1_H02E0001\narc: D4 H02W0201\narc: D5 V02S0601\narc: D6 W1_H02E0001\narc: D7 E1_H01W0100\narc: E1_H01E0101 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F1\narc: H01W0100 Q2\narc: LSR0 W1_H02E0301\narc: LSR1 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F3\narc: N1_V01N0101 F6\narc: S3_V06S0203 Q4\narc: W3_H06W0003 Q0\narc: W3_H06W0203 Q7\nword: SLICED.K0.INIT 0001001101011111\nword: SLICED.K1.INIT 0111111111111111\nword: SLICEA.K0.INIT 1000111111111111\nword: SLICEA.K1.INIT 1100000000000000\nword: SLICEB.K0.INIT 1000111111111111\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0111111111111111\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R9C2:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0601 E1_H01W0000\narc: H00L0000 E1_H02W0001\narc: N1_V02N0301 E1_H02W0301\narc: V00B0000 H02E0601\narc: V00T0100 S1_V02N0501\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q4\narc: LSR0 V00T0100\narc: M4 V00B0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R9C30:PLC2\narc: E3_H06E0103 W1_H02E0201\narc: E3_H06E0203 N1_V01S0000\narc: H00L0000 V02S0001\narc: H00L0100 H02E0301\narc: H00R0000 H02E0601\narc: H00R0100 H02E0701\narc: N1_V02N0101 E1_H01W0100\narc: S1_V02S0701 E1_H01W0100\narc: S3_V06S0203 H06W0203\narc: V00B0000 V02S0001\narc: V00B0100 H02W0501\narc: V00T0000 V02N0601\narc: V00T0100 V02N0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0201 V06S0103\narc: W1_H02W0701 V06S0203\narc: E1_H02E0401 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0001 W3_H06E0003\narc: S1_V02S0101 W3_H06E0103\narc: S1_V02S0201 W3_H06E0103\narc: S3_V06S0003 W3_H06E0003\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: A1 V02S0701\narc: A4 V02N0101\narc: A5 H02W0701\narc: A7 N1_V01S0100\narc: B1 V00T0000\narc: B4 H00R0000\narc: B5 N1_V02S0701\narc: B6 V01S0000\narc: B7 S1_V02N0501\narc: C0 V02N0601\narc: C1 H00L0000\narc: C4 E1_H01E0101\narc: C5 E1_H02W0601\narc: C6 V01N0101\narc: C7 E1_H02W0601\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 N1_V02S0001\narc: D4 V02S0401\narc: D5 H00R0100\narc: D6 H00L0100\narc: D7 V00B0000\narc: E1_H01E0101 F5\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F1\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: V01S0000 F7\narc: W3_H06W0203 Q4\narc: W3_H06W0303 Q6\nword: SLICEA.K0.INIT 1111111111110000\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 1000111111111111\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICED.K0.INIT 0011111111111111\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\n\n.tile R9C31:PLC2\narc: E1_H02E0701 E1_H01W0100\narc: E3_H06E0003 W1_H02E0001\narc: H00L0100 V02N0101\narc: H00R0100 E1_H02W0501\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 H02E0401\narc: S1_V02S0201 H06W0103\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0001\narc: V00B0100 H02W0501\narc: V00T0000 V02S0401\narc: W1_H02W0101 V06S0103\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 N1_V01S0100\narc: H01W0100 W3_H06E0303\narc: N1_V02N0501 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: N1_V02N0701 W3_H06E0203\narc: S1_V02S0001 W3_H06E0003\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0203\narc: CE0 H00R0100\narc: CE1 H00L0100\narc: CE3 H00L0100\narc: CLK0 G_HPBX0000\narc: E1_H02E0001 Q0\narc: E1_H02E0601 Q6\narc: E3_H06E0103 Q2\narc: M0 V00B0000\narc: M2 V00T0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: S3_V06S0103 Q2\narc: W3_H06W0303 Q6\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R9C32:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 V02N0601\narc: H00L0000 H02E0001\narc: H00L0100 V02S0301\narc: H00R0000 V02S0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 S3_V06N0103\narc: N1_V02N0401 H02W0401\narc: N1_V02N0501 S1_V02N0501\narc: S1_V02S0001 V01N0001\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0303 E3_H06W0303\narc: V00B0000 V02N0001\narc: V00B0100 E1_H02W0501\narc: V01S0000 S3_V06N0103\narc: W1_H02W0501 N1_V02S0501\narc: N1_V02N0601 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0203 W3_H06E0103\narc: W3_H06W0003 E3_H06W0003\narc: W3_H06W0103 E3_H06W0103\narc: W3_H06W0203 E3_H06W0203\narc: B3 H00L0000\narc: C2 N1_V01N0001\narc: C3 H00R0100\narc: CE0 H00L0100\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 V02S0201\narc: D3 V02S0201\narc: E1_H01E0101 Q0\narc: F2 F5B_SLICE\narc: H01W0100 Q6\narc: M0 V00B0100\narc: M2 H02W0601\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q6\narc: S1_V02S0201 F2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000111111111111\nword: SLICEB.K1.INIT 0000111100110011\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R9C33:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 H01E0101\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 W1_H02E0701\narc: E3_H06E0303 W1_H02E0601\narc: H00L0100 V02N0101\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H01E0101\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0301 E1_H01W0100\narc: V00B0000 V02N0201\narc: V00B0100 V02N0101\narc: V00T0000 H02W0001\narc: W1_H02W0201 E3_H06W0103\narc: W1_H02W0301 S3_V06N0003\narc: W1_H02W0401 V01N0001\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 E1_H02W0301\narc: E1_H02E0501 W3_H06E0303\narc: W3_H06W0203 E1_H02W0401\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0303 E3_H06W0203\narc: A0 N1_V02S0701\narc: A1 N1_V02S0701\narc: A6 N1_V01S0100\narc: A7 N1_V01S0100\narc: B0 H02E0101\narc: B1 H02E0301\narc: B6 H02E0301\narc: B7 H02E0101\narc: C0 H00L0100\narc: C1 H00L0100\narc: C6 V00B0100\narc: C7 V00B0100\narc: D0 V02N0201\narc: D1 V02N0201\narc: D6 V00B0000\narc: D7 V00B0000\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00T0000\narc: M1 E1_H02W0001\narc: M2 V00T0000\narc: M3 E1_H02W0201\narc: M4 V00T0000\narc: M5 E1_H02W0001\narc: M6 V00T0000\narc: N1_V02N0301 F3\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000101000000010\nword: SLICEA.K1.INIT 1010000000100000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000101000000010\nword: SLICED.K1.INIT 1010000000100000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R9C34:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V06S0103\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0701 V02S0701\narc: E3_H06E0303 S3_V06N0303\narc: H00R0000 E1_H02W0401\narc: H00R0100 V02S0701\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0701 N1_V01S0100\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 H02W0001\narc: V00B0000 V02S0201\narc: V00B0100 S1_V02N0301\narc: V00T0000 E1_H02W0201\narc: V00T0100 V02N0701\narc: E1_H02E0301 W3_H06E0003\narc: N1_V02N0601 W3_H06E0303\narc: W3_H06W0103 E1_H01W0100\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A5 H02E0701\narc: A6 V02N0101\narc: B5 S1_V02N0501\narc: B6 H02E0301\narc: B7 V00B0100\narc: C5 N1_V02S0201\narc: C6 V00T0000\narc: C7 S1_V02N0001\narc: CE0 H00R0000\narc: CE1 H00R0100\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D5 V01N0001\narc: D6 V00B0000\narc: D7 E1_H02W0001\narc: E1_H01E0101 F6\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q0\narc: M0 V00T0100\narc: M2 W1_H02E0601\narc: M4 E1_H01E0101\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: S3_V06S0203 Q7\narc: V01S0000 F7\narc: V01S0100 Q7\narc: W1_H02W0001 Q2\narc: W1_H02W0501 F7\narc: W1_H02W0601 F4\narc: W3_H06W0203 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0001010100111111\nword: SLICED.K1.INIT 0000111111001111\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R9C35:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 V01N0101\narc: E1_H02E0201 N3_V06S0103\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0501 W1_H02E0501\narc: E3_H06E0003 W1_H02E0001\narc: H00R0000 W1_H02E0601\narc: H00R0100 H02E0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 V01N0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0203 S3_V06N0203\narc: N3_V06N0303 V01N0101\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 V01N0001\narc: S1_V02S0701 H06W0203\narc: S3_V06S0103 H06W0103\narc: V00B0000 H02W0601\narc: V00B0100 E1_H02W0501\narc: V00T0000 V02N0601\narc: V00T0100 W1_H02E0101\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0301 V06S0003\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0303\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A1 H02W0501\narc: A5 V00B0000\narc: B1 S1_V02N0101\narc: B5 H00R0000\narc: C1 S1_V02N0601\narc: C5 V02N0201\narc: CE1 H00R0100\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D5 V02S0401\narc: E1_H01E0001 F1\narc: E1_H01E0101 F4\narc: E1_H02E0601 F4\narc: F1 F1_SLICE\narc: F4 F5C_SLICE\narc: H01W0000 Q6\narc: H01W0100 F4\narc: M2 V00T0100\narc: M4 V00T0000\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: N1_V02N0601 F4\narc: S3_V06S0203 F4\narc: V01S0100 Q2\narc: W1_H02W0201 Q2\narc: W1_H02W0401 F4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0100000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R9C36:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0201 W1_H02E0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 W1_H02E0401\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0303 H01E0101\narc: H00L0000 V02N0201\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02S0601\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 H02E0401\narc: N1_V02N0701 S1_V02N0601\narc: N3_V06N0303 S1_V02N0501\narc: S1_V02S0001 H02E0001\narc: S1_V02S0201 H01E0001\narc: S1_V02S0401 N1_V02S0101\narc: S1_V02S0701 E1_H02W0701\narc: S3_V06S0003 H06W0003\narc: V00B0100 H02W0701\narc: V00T0100 V02S0501\narc: W1_H02W0001 V01N0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 E3_H06W0303\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0101 W3_H06E0103\narc: W3_H06W0003 E1_H01W0000\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\narc: A3 H00L0100\narc: A7 S1_V02N0301\narc: B2 S1_V02N0301\narc: B3 E1_H01W0100\narc: B4 H00L0000\narc: B5 H00L0000\narc: B7 E1_H02W0101\narc: C2 N1_V01S0100\narc: C3 N1_V01S0100\narc: C4 V00T0100\narc: C5 V00T0100\narc: C7 V00T0100\narc: D2 E1_H02W0001\narc: D3 E1_H02W0001\narc: D4 E1_H02W0001\narc: D5 E1_H02W0001\narc: D7 E1_H02W0001\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F3 FXB_SLICE\narc: F4 F5C_SLICE\narc: F5 FXC_SLICE\narc: F6 F5D_SLICE\narc: M0 V00B0100\narc: M1 H00R0000\narc: M2 V00B0100\narc: M3 H02W0201\narc: M4 V00B0100\narc: M5 H00R0000\narc: M6 V00B0100\narc: S1_V02S0301 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000011000011\nword: SLICEC.K1.INIT 0000000011000011\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000010000100\nword: SLICEB.K0.INIT 0000000011000011\nword: SLICEB.K1.INIT 0000000000100001\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\n\n.tile R9C37:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 V06N0103\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 E3_H06W0203\narc: E3_H06E0203 S3_V06N0203\narc: H00L0100 V02N0101\narc: H00R0100 H02W0501\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 V01N0101\narc: V00B0000 S1_V02N0201\narc: V00T0000 V02N0601\narc: V00T0100 V02S0701\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0501 V02N0501\narc: E1_H02E0301 W3_H06E0003\narc: E1_H02E0401 W3_H06E0203\narc: W3_H06W0203 E1_H01W0000\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0303 E3_H06W0303\narc: A2 E1_H02W0701\narc: A5 N1_V02S0301\narc: A6 V02N0301\narc: B0 V00T0000\narc: B1 V02S0301\narc: B2 S1_V02N0101\narc: B3 H00R0100\narc: B5 V02S0501\narc: B6 N1_V02S0701\narc: B7 S1_V02N0501\narc: C0 N1_V01N0001\narc: C1 H00L0100\narc: C2 V02S0601\narc: C3 H02W0601\narc: C5 V02N0201\narc: C6 E1_H02W0401\narc: C7 V02S0001\narc: CE0 W1_H02E0101\narc: CE1 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 V00T0100\narc: D2 V02N0001\narc: D3 V02N0001\narc: D5 H02E0201\narc: D6 V01N0001\narc: D7 E1_H02W0201\narc: E1_H01E0001 F6\narc: E1_H01E0101 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 F1\narc: LSR1 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F1\narc: N1_V01N0101 F5\narc: S1_V02S0201 F2\narc: S1_V02S0301 F3\narc: S3_V06S0003 Q0\narc: V00B0100 F7\narc: V01S0000 F2\narc: V01S0100 Q3\narc: W1_H02W0701 F7\narc: W3_H06W0003 Q3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 1100000001000100\nword: SLICED.K1.INIT 0011000011110000\nword: SLICEA.K0.INIT 0000001100110011\nword: SLICEA.K1.INIT 0011111100000000\nword: SLICEB.K0.INIT 1100000001000100\nword: SLICEB.K1.INIT 0000111111001100\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R9C38:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 W1_H02E0301\narc: E3_H06E0103 W1_H02E0101\narc: E3_H06E0203 W1_H02E0401\narc: E3_H06E0303 W1_H02E0601\narc: H00L0000 S1_V02N0201\narc: H00L0100 S1_V02N0301\narc: H00R0100 H02W0701\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0601 S1_V02N0601\narc: N3_V06N0003 S3_V06N0303\narc: N3_V06N0103 S3_V06N0003\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 V01N0001\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 H02W0401\narc: S1_V02S0601 E1_H02W0601\narc: S3_V06S0003 E3_H06W0003\narc: V00B0000 N1_V02S0201\narc: V00T0000 S1_V02N0401\narc: V00T0100 H02E0301\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 H01E0101\narc: W1_H02W0501 S3_V06N0303\narc: W1_H02W0601 V02S0601\narc: W1_H02W0701 S1_V02N0701\narc: E1_H01E0101 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0303 E3_H06W0203\narc: A3 V00B0000\narc: A6 V00T0100\narc: A7 V02N0101\narc: B1 H00R0100\narc: B3 V02S0301\narc: B4 V02S0501\narc: B6 V00B0100\narc: B7 H02W0101\narc: C1 H02E0601\narc: C3 N1_V01N0001\narc: C4 H02W0601\narc: C5 V02S0001\narc: C6 V01N0101\narc: C7 E1_H02W0401\narc: CE0 S1_V02N0201\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D3 V02S0201\narc: D4 V02S0401\narc: D5 H00L0100\narc: D6 N1_V02S0401\narc: D7 H02E0001\narc: E1_H01E0001 F5\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M2 V00T0000\narc: MUXCLK0 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0001 F5\narc: S1_V02S0201 F2\narc: V00B0100 F7\narc: V01S0000 F6\narc: V01S0100 F4\narc: W3_H06W0103 Q1\narc: W3_H06W0203 Q4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000111111001100\nword: SLICEC.K0.INIT 0000001100110011\nword: SLICEC.K1.INIT 0000000011110000\nword: SLICED.K0.INIT 0000000000001101\nword: SLICED.K1.INIT 1111110100000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0101011101110111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R9C39:PLC2\narc: E1_H02E0301 S3_V06N0003\narc: E1_H02E0401 S1_V02N0401\narc: E3_H06E0103 W1_H02E0201\narc: H00L0000 H02E0001\narc: H00L0100 N1_V02S0301\narc: H00R0100 W1_H02E0701\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 S1_V02N0101\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 S1_V02N0401\narc: V00B0000 S1_V02N0001\narc: V00T0100 V02S0501\narc: W1_H02W0101 H01E0101\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 H01E0001\narc: W1_H02W0701 V02N0701\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\narc: W3_H06W0103 E3_H06W0003\narc: W3_H06W0203 E3_H06W0103\narc: A5 E1_H02W0701\narc: B0 V00T0000\narc: B1 H00R0100\narc: B3 V02N0101\narc: B5 E1_H02W0101\narc: C0 N1_V01N0001\narc: C1 H02E0601\narc: C2 H02E0401\narc: C3 H00L0000\narc: C5 V02S0201\narc: CE0 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 V01S0100\narc: D1 V00T0100\narc: D2 H02E0001\narc: D3 N1_V02S0201\narc: D5 H00L0100\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: LSR0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F3\narc: N1_V01N0101 F5\narc: S1_V02S0001 F2\narc: S1_V02S0301 F3\narc: V00T0000 F2\narc: V01S0100 F1\narc: W1_H02W0001 F0\narc: W3_H06W0003 Q0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000000000001111\nword: SLICEB.K1.INIT 0011000011110000\nword: SLICEA.K0.INIT 0000001100110011\nword: SLICEA.K1.INIT 0011111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R9C3:PLC2\narc: E1_H02E0301 V02S0301\narc: E1_H02E0501 V02S0501\narc: E1_H02E0601 N1_V02S0601\narc: H00L0000 H02E0001\narc: H00R0000 H02E0601\narc: H00R0100 V02N0701\narc: H01W0000 E3_H06W0103\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0401 E3_H06W0203\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0701 E1_H01W0100\narc: V00B0000 W1_H02E0601\narc: V00B0100 V02N0101\narc: V00T0100 N1_V02S0701\narc: A5 V00T0000\narc: B3 H01W0100\narc: B5 V01S0000\narc: C3 H00L0000\narc: C5 V00B0100\narc: CE0 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D2 H01E0101\narc: D3 V00T0100\narc: D5 E1_H01W0100\narc: E1_H01E0001 Q2\narc: E3_H06E0103 Q2\narc: E3_H06E0303 F5\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: LSR0 H02E0501\narc: LSR1 H02E0501\narc: M0 W1_H02E0601\narc: M2 H02W0601\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR3 LSR0\narc: N1_V01N0001 Q0\narc: V00T0000 Q0\narc: V01S0000 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 1111111100000000\nword: SLICEB.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R9C40:PLC2\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 V02N0301\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0003 W1_H02E0301\narc: H00R0000 H02W0601\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 H02W0201\narc: N1_V02N0301 H02E0301\narc: N1_V02N0601 S1_V02N0601\narc: N1_V02N0701 N3_V06S0203\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 H02W0001\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0601 E3_H06W0303\narc: V00B0000 V02N0201\narc: V00B0100 V02S0101\narc: V00T0100 H02W0301\narc: W1_H02W0301 V02S0301\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 E1_H02W0301\narc: E1_H02E0501 W3_H06E0303\narc: E1_H02E0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: CE2 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V00T0100\narc: D2 V02S0201\narc: D3 E1_H02W0201\narc: E1_H01E0101 Q4\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: H01W0000 F1\narc: M0 V00B0100\narc: M1 H02W0001\narc: M2 V00B0100\narc: M4 V00B0000\narc: MUXCLK2 CLK0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R9C41:PLC2\narc: E1_H02E0001 V06S0003\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0201 V06N0103\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0401 V02S0401\narc: E1_H02E0701 V02N0701\narc: H00R0000 H02W0601\narc: H00R0100 V02S0701\narc: N1_V02N0401 W1_H02E0401\narc: N1_V02N0501 E1_H02W0501\narc: N1_V02N0601 H02W0601\narc: N3_V06N0003 S3_V06N0003\narc: N3_V06N0103 S3_V06N0103\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0601 H02W0601\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 E1_H02W0401\narc: V00T0100 H02E0301\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V02N0101\narc: W1_H02W0201 E1_H02W0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0701 H01E0101\narc: E1_H01E0101 W3_H06E0203\narc: H01W0000 W3_H06E0103\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0103 W3_H06E0003\narc: W3_H06W0003 E3_H06W0303\narc: W3_H06W0103 E3_H06W0003\narc: CE0 H00R0100\narc: CE1 H00R0100\narc: CE2 H00R0000\narc: CE3 H02E0101\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 Q0\narc: M0 V00B0000\narc: M2 V00T0100\narc: M4 E1_H02W0401\narc: M6 E1_H02W0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: V01S0100 Q2\narc: W1_H02W0601 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R9C42:PLC2\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0101 H01E0101\narc: E1_H02E0201 V02N0201\narc: E1_H02E0301 W1_H02E0201\narc: E1_H02E0501 S1_V02N0501\narc: E1_H02E0701 W1_H02E0701\narc: H00R0000 H02E0401\narc: N1_V02N0001 H02E0001\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 H02W0501\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 W1_H02E0601\narc: S1_V02S0701 E1_H02W0701\narc: V00B0100 V02S0101\narc: V00T0100 V02N0701\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0201 H01E0001\narc: E1_H01E0001 W3_H06E0003\narc: E1_H02E0601 W3_H06E0303\narc: H01W0100 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: W3_H06W0303 E1_H02W0601\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: CE2 W1_H02E0101\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02W0001\narc: D1 H02E0201\narc: D2 V02N0001\narc: D3 V01S0100\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: M0 V00B0100\narc: M1 H02E0001\narc: M2 V00B0100\narc: M4 V00T0100\narc: M6 V00T0100\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: V01S0000 Q4\narc: V01S0100 Q6\narc: W1_H02W0301 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000011111111\nword: SLICEA.K1.INIT 0000000011111111\nword: SLICEB.K0.INIT 0000000011111111\nword: SLICEB.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\n\n.tile R9C43:PLC2\narc: E1_H02E0001 E3_H06W0003\narc: E1_H02E0101 S3_V06N0103\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 V06N0203\narc: E1_H02E0501 V02N0501\narc: E1_H02E0601 H01E0001\narc: E1_H02E0701 S1_V02N0701\narc: E3_H06E0303 S3_V06N0303\narc: H00R0000 W1_H02E0401\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H02E0601\narc: S1_V02S0101 H02W0101\narc: V00B0100 S1_V02N0101\narc: V00T0100 V02N0701\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 S1_V02N0501\narc: E1_H01E0001 W3_H06E0003\narc: E1_H01E0101 W3_H06E0203\narc: S1_V02S0601 W3_H06E0303\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0103 W3_H06E0003\narc: E3_H06E0203 W3_H06E0103\narc: CE0 W1_H02E0101\narc: CE1 H00R0000\narc: CE2 W1_H02E0101\narc: CE3 W1_H02E0101\narc: CLK0 G_HPBX0000\narc: M0 V00T0100\narc: M2 H02W0601\narc: M4 H02W0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0001 Q6\narc: N1_V02N0201 Q2\narc: W1_H02W0001 Q0\narc: W3_H06W0203 Q4\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R9C44:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 W1_H02E0001\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0601 H01E0001\narc: E3_H06E0003 H01E0001\narc: H00L0000 V02S0001\narc: H00L0100 H02W0101\narc: H00R0000 H02E0401\narc: H00R0100 W1_H02E0501\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S1_V02N0501\narc: N1_V02N0601 H01E0001\narc: N3_V06N0303 S3_V06N0203\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 V02S0201\narc: V00B0100 W1_H02E0701\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02S0701\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0401 V06N0203\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 V02S0701\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0701 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A1 H02E0701\narc: A6 E1_H02W0501\narc: A7 H02E0701\narc: B0 V00B0000\narc: B1 H00R0100\narc: B2 H01W0100\narc: B3 W1_H02E0101\narc: B4 V02N0701\narc: B5 W1_H02E0301\narc: B6 V00T0000\narc: B7 H02E0301\narc: C0 H00L0000\narc: C1 V02N0601\narc: C2 H00L0000\narc: C3 N1_V02S0601\narc: C4 V02S0001\narc: C5 H02E0601\narc: C6 V00B0100\narc: C7 F6\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 W1_H02E0201\narc: D2 V02N0201\narc: D3 H01E0101\narc: D4 H00L0100\narc: D5 H01W0000\narc: D6 H02E0201\narc: D7 V02S0601\narc: E1_H02E0501 Q5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q3\narc: LSR1 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V01N0001 Q1\narc: S1_V02S0301 Q1\narc: S3_V06S0103 F2\narc: V01S0000 Q3\narc: V01S0100 Q5\narc: W3_H06W0003 F0\narc: W3_H06W0103 Q1\narc: W3_H06W0203 F4\narc: W3_H06W0303 Q5\nword: SLICEC.K0.INIT 1100111111000000\nword: SLICEC.K1.INIT 0000110011111111\nword: SLICEA.K0.INIT 1100111111000000\nword: SLICEA.K1.INIT 1111111111111000\nword: SLICEB.K0.INIT 1100111111000000\nword: SLICEB.K1.INIT 1111110011111111\nword: SLICED.K0.INIT 1000000010101010\nword: SLICED.K1.INIT 0000000000000111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET SET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET SET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R9C45:PLC2\narc: E1_H02E0101 V06N0103\narc: E1_H02E0201 E1_H01W0000\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0601 N1_V01S0000\narc: E1_H02E0701 N1_V01S0100\narc: H00L0100 E1_H02W0301\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 S1_V02N0301\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0201 N1_V02S0701\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 N1_V02S0601\narc: V00B0000 H02E0401\narc: V00B0100 V02N0101\narc: V00T0000 H02E0001\narc: V00T0100 E1_H02W0101\narc: W1_H02W0101 N1_V02S0101\narc: W1_H02W0701 S1_V02N0701\narc: E1_H02E0401 W3_H06E0203\narc: N1_V02N0201 W3_H06E0103\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0103 W3_H06E0103\narc: A4 V00B0000\narc: A5 V00T0000\narc: B4 V02N0701\narc: B5 H02W0301\narc: B7 V02S0501\narc: C1 H02E0601\narc: C3 H02E0601\narc: C4 H02W0401\narc: C5 H02E0601\narc: C7 V02N0201\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0001\narc: D3 V00T0100\narc: D4 V02N0401\narc: D5 W1_H02E0001\narc: D7 V02S0601\narc: E3_H06E0203 Q4\narc: E3_H06E0303 F5\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: LSR0 W1_H02E0501\narc: LSR1 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q4\narc: N1_V01N0101 Q4\narc: N3_V06N0203 Q4\narc: S3_V06S0203 F7\narc: W3_H06W0003 Q3\narc: W3_H06W0103 Q1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100110011110000\nword: SLICEC.K0.INIT 1111111111111110\nword: SLICEC.K1.INIT 0000110010101100\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R9C46:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0401 N1_V02S0401\narc: E1_H02E0501 E1_H01W0100\narc: E3_H06E0103 W1_H02E0201\narc: H00L0000 W1_H02E0201\narc: H00L0100 S1_V02N0101\narc: H00R0000 H02W0601\narc: H00R0100 H02W0501\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0601 S3_V06N0303\narc: N3_V06N0303 S3_V06N0203\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0301 E1_H02W0301\narc: V00B0000 V02N0201\narc: V00B0100 N1_V02S0301\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0301 V02S0301\narc: W1_H02W0501 S1_V02N0501\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0301 W3_H06E0003\narc: W1_H02W0401 W3_H06E0203\narc: W3_H06W0103 V06N0103\narc: A0 V02S0701\narc: A1 S1_V02N0501\narc: A6 N1_V01N0101\narc: B0 E1_H02W0101\narc: B1 W1_H02E0101\narc: B3 H00L0000\narc: B4 H00R0000\narc: B6 E1_H02W0101\narc: B7 V00B0000\narc: C0 H00L0100\narc: C1 E1_H01W0000\narc: C2 H00R0100\narc: C3 H02E0601\narc: C4 V00B0100\narc: C5 H02W0601\narc: C6 F4\narc: C7 H02E0401\narc: CLK0 G_HPBX0000\narc: D0 N1_V02S0001\narc: D1 V02S0201\narc: D2 V01S0100\narc: D3 V02N0001\narc: D4 V02S0601\narc: D5 H02W0201\narc: D6 E1_H02W0201\narc: D7 N1_V02S0601\narc: E1_H01E0101 F3\narc: E1_H02E0201 F2\narc: E1_H02E0701 Q7\narc: E3_H06E0203 Q7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q7\narc: LSR0 E1_H02W0501\narc: M4 H02W0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F2\narc: N1_V01N0101 Q7\narc: N1_V02N0001 F0\narc: N1_V02N0501 Q7\narc: N3_V06N0203 Q7\narc: S1_V02S0701 Q7\narc: V01S0000 F1\narc: V01S0100 F3\narc: W3_H06W0303 F6\nword: SLICED.K0.INIT 1000101000001010\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEA.K0.INIT 1000000010101010\nword: SLICEA.K1.INIT 1000000010101010\nword: SLICEB.K0.INIT 1111000000000000\nword: SLICEB.K1.INIT 0000110000000000\nword: SLICEC.K0.INIT 0000110000111111\nword: SLICEC.K1.INIT 1111000011111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R9C47:PLC2\narc: E1_H02E0001 V06N0003\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 V02S0501\narc: E3_H06E0103 V06S0103\narc: E3_H06E0303 V06S0303\narc: H00R0000 H02W0601\narc: H00R0100 H02W0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 V01N0001\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 S3_V06N0303\narc: N3_V06N0103 H01E0101\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 H02W0101\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0601 N1_V02S0601\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0303 H06W0303\narc: V00B0000 W1_H02E0601\narc: V00B0100 S1_V02N0101\narc: V00T0000 V02N0601\narc: V00T0100 H02E0301\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 N1_V01S0100\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0401 E1_H02W0401\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E1_H02W0601\narc: H01W0000 W3_H06E0103\narc: W1_H02W0301 W3_H06E0003\narc: A2 W1_H02E0701\narc: A3 V00B0000\narc: A6 V02S0101\narc: B2 W1_H02E0101\narc: B3 H00R0000\narc: B6 V02S0701\narc: C2 H00L0100\narc: C3 V02N0401\narc: C6 E1_H01E0101\narc: C7 V00B0100\narc: CE2 H00R0100\narc: CLK0 G_HPBX0000\narc: D2 V00T0100\narc: D3 H02E0201\narc: D6 H02W0001\narc: D7 W1_H02E0201\narc: E1_H01E0001 F7\narc: E1_H01E0101 F2\narc: E3_H06E0003 F3\narc: E3_H06E0203 F7\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0100 F3\narc: H01W0100 Q4\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: N1_V01N0101 F3\narc: V01S0000 Q4\narc: W3_H06W0003 F3\narc: W3_H06W0203 Q4\narc: W3_H06W0303 F6\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 1100000011000100\nword: SLICEB.K1.INIT 0000001100010011\nword: SLICED.K0.INIT 0000111100001110\nword: SLICED.K1.INIT 0000111100000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\n\n.tile R9C48:PLC2\narc: E1_H02E0001 V01N0001\narc: E1_H02E0101 W1_H02E0101\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 H01E0001\narc: E3_H06E0103 W1_H02E0101\narc: H00L0000 E1_H02W0201\narc: H00L0100 V02S0301\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 H02E0001\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0301 N3_V06S0003\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 W1_H02E0501\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 S3_V06N0203\narc: N3_V06N0103 S3_V06N0103\narc: N3_V06N0303 S1_V02N0601\narc: S1_V02S0001 N1_V02S0501\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 H02W0401\narc: S1_V02S0501 H02W0501\narc: S1_V02S0601 H02W0601\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0203 N3_V06S0103\narc: S3_V06S0303 N3_V06S0203\narc: V00B0000 H02W0601\narc: V00B0100 H02W0701\narc: V00T0000 V02N0401\narc: V01S0100 N3_V06S0303\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0501 E1_H02W0501\narc: W1_H02W0701 S1_V02N0701\narc: E1_H01E0101 W3_H06E0203\narc: E3_H06E0203 W3_H06E0103\narc: A4 N1_V01N0101\narc: A7 N1_V01N0101\narc: B0 V00B0000\narc: B2 H01W0100\narc: B4 H02E0301\narc: B7 H02E0301\narc: C0 S1_V02N0401\narc: C1 H02W0601\narc: C2 H00L0000\narc: C3 E1_H01W0000\narc: C4 V02S0201\narc: C5 H02E0401\narc: C6 V02N0201\narc: C7 V02S0201\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D0 H02W0201\narc: D1 W1_H02E0001\narc: D2 V02S0001\narc: D3 V02N0001\narc: D4 H00R0100\narc: D5 H00L0100\narc: D6 H01W0000\narc: D7 H00R0100\narc: E1_H01E0001 F3\narc: E1_H02E0201 F0\narc: E3_H06E0003 F3\narc: E3_H06E0303 F6\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q3\narc: LSR0 E1_H02W0501\narc: LSR1 V00T0000\narc: M0 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q5\narc: N3_V06N0003 F3\narc: S3_V06S0103 F2\narc: W1_H02W0601 F4\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1111000000000000\nword: SLICEC.K0.INIT 1010000010001000\nword: SLICEC.K1.INIT 1111111111110000\nword: SLICED.K0.INIT 0000000011110000\nword: SLICED.K1.INIT 0000101000100010\nword: SLICEA.K0.INIT 0000110000111111\nword: SLICEA.K1.INIT 1111000011111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R9C49:PLC2\narc: E1_H01E0101 E3_H06W0203\narc: E1_H02E0001 W1_H02E0501\narc: E1_H02E0401 H01E0001\narc: E1_H02E0601 V02S0601\narc: E1_H02E0701 V06N0203\narc: H00L0100 S1_V02N0301\narc: H00R0000 V02N0401\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 S3_V06N0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0401 H06E0203\narc: N1_V02N0601 V01N0001\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0201 H02E0201\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 H02E0501\narc: S1_V02S0601 H06W0303\narc: S1_V02S0701 H06W0203\narc: S3_V06S0003 N3_V06S0003\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N1_V01S0100\narc: V00B0000 E1_H02W0401\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 V02S0201\narc: W1_H02W0401 V06S0203\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 V06S0303\narc: W1_H02W0701 V06S0203\narc: E1_H02E0101 W3_H06E0103\narc: E1_H02E0501 W3_H06E0303\narc: H01W0000 W3_H06E0103\narc: W1_H02W0101 W3_H06E0103\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0303 W3_H06E0203\narc: W3_H06W0003 E3_H06W0303\narc: A3 E1_H02W0701\narc: A4 V00B0000\narc: A5 N1_V01N0101\narc: A7 E1_H02W0701\narc: B3 V02S0101\narc: B4 H01E0101\narc: B5 N1_V02S0701\narc: B7 V02S0701\narc: C3 H00L0100\narc: C4 H02E0401\narc: C5 V01N0101\narc: C7 V02S0201\narc: D3 H00R0000\narc: D4 H00R0100\narc: D5 H02E0001\narc: D7 S1_V02N0401\narc: E3_H06E0203 F4\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00R0100 F5\narc: N1_V01N0101 F3\narc: N1_V02N0501 F7\nword: SLICEC.K0.INIT 0000110010101100\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R9C4:PLC2\narc: H00L0000 V02S0201\narc: H00L0100 H02E0301\narc: H00R0000 V02N0401\narc: H00R0100 V02N0501\narc: H01W0000 E3_H06W0103\narc: H01W0100 E3_H06W0303\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 E3_H06W0103\narc: N1_V02N0201 H01E0001\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 H02W0601\narc: N3_V06N0103 E3_H06W0103\narc: N3_V06N0303 E3_H06W0303\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0601 E3_H06W0303\narc: S3_V06S0103 E3_H06W0103\narc: S3_V06S0203 E3_H06W0203\narc: V00B0000 H02E0601\narc: V00B0100 H02E0501\narc: V00T0000 V02S0601\narc: W1_H02W0001 E3_H06W0003\narc: W1_H02W0301 V06N0003\narc: W1_H02W0601 E1_H02W0301\narc: A1 E1_H01E0001\narc: B1 V02S0101\narc: C1 H00L0000\narc: CE1 H00L0100\narc: CE2 H00R0100\narc: CE3 H00R0000\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: E1_H01E0001 Q4\narc: F1 F1_SLICE\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M2 E1_H02W0601\narc: M4 V00T0000\narc: M6 V00B0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q6\narc: S1_V02S0301 F1\narc: V01S0100 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R9C50:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0601 V06N0303\narc: E1_H02E0701 N1_V01S0100\narc: E3_H06E0103 N1_V01S0100\narc: E3_H06E0303 W1_H02E0501\narc: H00L0100 W1_H02E0101\narc: H00R0100 H02E0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V01N0101 S3_V06N0203\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 H06E0203\narc: N3_V06N0303 S3_V06N0303\narc: S1_V02S0001 N3_V06S0003\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0301 H01E0101\narc: S1_V02S0401 H06E0203\narc: S1_V02S0501 H02E0501\narc: S3_V06S0003 E3_H06W0003\narc: S3_V06S0103 N1_V01S0100\narc: V00B0100 V02N0101\narc: V00T0100 H02W0301\narc: V01S0000 N3_V06S0103\narc: W1_H02W0001 V06N0003\narc: W1_H02W0201 V06N0103\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V02S0601\narc: E1_H02E0401 W3_H06E0203\narc: H01W0100 W3_H06E0303\narc: N1_V02N0601 W3_H06E0303\narc: A1 H00L0100\narc: A5 V02S0101\narc: A6 V00T0100\narc: A7 V02S0301\narc: B1 H01W0100\narc: B5 V00B0100\narc: B6 V00B0100\narc: B7 V00B0100\narc: C1 W1_H02E0601\narc: C5 V02S0201\narc: C6 V02S0201\narc: C7 V02S0201\narc: D1 V02N0001\narc: D5 H01W0000\narc: D6 H01W0000\narc: D7 H01W0000\narc: E1_H01E0101 F1\narc: F0 F5A_SLICE\narc: F1 FXA_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: M0 H02E0601\narc: M1 H00R0100\narc: M2 H02E0601\narc: S3_V06S0203 F7\narc: S3_V06S0303 F6\narc: W3_H06W0303 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111101111110000\nword: SLICED.K0.INIT 1111101111110000\nword: SLICED.K1.INIT 1111101111110000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R9C51:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0401 W1_H02E0101\narc: E1_H02E0701 V02N0701\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 S3_V06N0303\narc: H00L0000 H02E0001\narc: H00L0100 V02N0301\narc: H00R0000 V02S0401\narc: H00R0100 V02N0501\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0301 H06E0003\narc: N1_V02N0601 H02E0601\narc: N3_V06N0303 H06E0303\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 S3_V06N0003\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 V01N0101\narc: S1_V02S0701 E3_H06W0203\narc: V00B0000 H02E0401\narc: V00T0000 W1_H02E0001\narc: V00T0100 V02N0701\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0701 E1_H02W0601\narc: E1_H01E0001 W3_H06E0003\narc: N1_V02N0401 W3_H06E0203\narc: N1_V02N0701 W3_H06E0203\narc: S3_V06S0303 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0401 W3_H06E0203\narc: E3_H06E0203 W3_H06E0203\narc: A1 H00L0000\narc: B0 V02S0301\narc: B1 H02E0101\narc: B2 E1_H02W0301\narc: B3 V02S0101\narc: C0 H02E0601\narc: C1 V02S0401\narc: C2 H00L0100\narc: C3 H02W0601\narc: CE2 H00R0100\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 H01E0101\narc: D2 H00R0000\narc: D3 H00R0000\narc: E1_H02E0301 F1\narc: E3_H06E0003 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: LSR1 V00B0000\narc: M4 W1_H02E0401\narc: M6 V00T0000\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: S1_V02S0601 Q6\narc: S3_V06S0003 F3\narc: S3_V06S0103 F2\narc: S3_V06S0203 Q4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 1100110011110000\nword: SLICEA.K1.INIT 1111101111110000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R9C52:PLC2\narc: E1_H02E0001 E1_H01W0000\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 W1_H02E0701\narc: E1_H02E0301 V02S0301\narc: E1_H02E0401 V06S0203\narc: E1_H02E0601 V06N0303\narc: E3_H06E0003 H01E0001\narc: H00L0100 V02N0301\narc: N1_V02N0001 H02W0001\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 S3_V06N0203\narc: S1_V02S0001 S3_V06N0003\narc: S1_V02S0101 H06W0103\narc: S1_V02S0201 E1_H02W0201\narc: S1_V02S0401 E1_H02W0401\narc: V00B0000 N1_V02S0001\narc: V00B0100 H02E0701\narc: V00T0000 V02N0401\narc: V00T0100 V02S0501\narc: W1_H02W0601 V06N0303\narc: E1_H01E0101 W3_H06E0203\narc: E1_H02E0701 W3_H06E0203\narc: W3_H06W0203 V06S0203\narc: W3_H06W0303 E1_H01W0100\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: E3_H06E0303 W3_H06E0203\narc: CE0 H00L0100\narc: CE1 H00L0100\narc: CE2 V02N0601\narc: CE3 V02N0601\narc: CLK0 G_HPBX0000\narc: H01W0000 Q0\narc: LSR0 V00B0100\narc: LSR1 V00T0000\narc: M0 V00T0100\narc: M2 V00B0000\narc: M4 V00T0100\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR0\narc: S3_V06S0203 Q4\narc: S3_V06S0303 Q6\narc: V01S0000 Q2\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R9C53:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: E1_H02E0101 V02N0101\narc: E1_H02E0201 S3_V06N0103\narc: E1_H02E0301 S1_V02N0301\narc: E1_H02E0601 S1_V02N0601\narc: E1_H02E0701 H01E0101\narc: E3_H06E0003 W1_H02E0301\narc: H00L0000 W1_H02E0201\narc: H00R0000 V02S0601\narc: H00R0100 S1_V02N0501\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0601 H02W0601\narc: S1_V02S0401 H02W0401\narc: S3_V06S0003 N1_V02S0301\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N1_V01S0100\narc: V00B0100 E1_H02W0501\narc: V00T0000 S1_V02N0601\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 V06N0003\narc: W1_H02W0301 V06S0003\narc: W1_H02W0501 S3_V06N0303\narc: E1_H02E0501 W3_H06E0303\narc: W1_H02W0601 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0103\narc: E3_H06E0303 W3_H06E0303\narc: A6 H02E0701\narc: A7 H02W0701\narc: B2 H02E0101\narc: B3 V02N0301\narc: B4 V00B0100\narc: B6 H02W0101\narc: B7 E1_H02W0301\narc: C1 W1_H02E0401\narc: C2 H02E0601\narc: C3 H00L0000\narc: C4 V00T0000\narc: C5 V00B0100\narc: C6 V02N0001\narc: C7 N1_V02S0201\narc: CE0 H00R0100\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D2 H02E0201\narc: D3 H02E0201\narc: D4 H02W0001\narc: D5 V02N0601\narc: D6 V00B0000\narc: D7 W1_H02E0001\narc: E1_H01E0001 F1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F6\narc: LSR1 H02W0301\narc: M4 H02E0401\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: S1_V02S0101 F3\narc: S3_V06S0103 F2\narc: V00B0000 F4\narc: V01S0100 Q1\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nword: SLICEB.K0.INIT 1100110011110000\nword: SLICEB.K1.INIT 1100110011110000\nword: SLICED.K0.INIT 1000000010101010\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEC.K0.INIT 0000110000111111\nword: SLICEC.K1.INIT 1111000011111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\n\n.tile R9C54:PLC2\narc: E1_H02E0101 V06S0103\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 V06S0203\narc: E3_H06E0003 H01E0001\narc: H00L0100 V02N0301\narc: H00R0100 H02W0501\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S3_V06N0003\narc: N1_V02N0101 H06E0103\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0401 H01E0001\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H06E0203\narc: N3_V06N0203 S3_V06N0103\narc: S1_V02S0401 H06W0203\narc: S1_V02S0601 V01N0001\narc: S1_V02S0701 W1_H02E0701\narc: S3_V06S0003 H06E0003\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 W1_H02E0401\narc: V00T0100 H02W0101\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 N1_V02S0001\narc: W1_H02W0101 V06S0103\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 S3_V06N0203\narc: W1_H02W0601 V06N0303\narc: W1_H02W0701 V06S0203\narc: N1_V02N0501 W3_H06E0303\narc: N3_V06N0103 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\narc: A2 W1_H02E0701\narc: A3 V02S0501\narc: A4 H02W0701\narc: A5 N1_V01N0101\narc: A7 N1_V02S0301\narc: B0 H00R0100\narc: B2 E1_H02W0101\narc: B3 H02E0301\narc: B4 W1_H02E0301\narc: B5 V00B0100\narc: B7 H02E0101\narc: C0 H02W0401\narc: C1 H00R0100\narc: C2 H00L0100\narc: C3 H02E0601\narc: C4 V00T0100\narc: C5 H02W0601\narc: C7 E1_H02W0601\narc: D0 N1_V02S0201\narc: D1 V02S0001\narc: D2 E1_H02W0201\narc: D3 V01S0100\narc: D4 H02W0201\narc: D5 W1_H02E0001\narc: D7 H02E0201\narc: E1_H01E0001 F5\narc: E1_H01E0101 F4\narc: E1_H02E0001 F0\narc: F0 F5A_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: M0 V00B0000\narc: N1_V01N0101 F3\narc: S1_V02S0201 F2\narc: V00B0100 F7\nword: SLICEC.K0.INIT 0000110010101100\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 1000000010101010\nword: SLICEB.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000110000111111\nword: SLICEA.K1.INIT 1111000011111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R9C55:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0301 V02N0301\narc: E1_H02E0501 V06S0303\narc: E1_H02E0601 V06S0303\narc: E3_H06E0103 S3_V06N0103\narc: E3_H06E0303 H01E0101\narc: H00L0000 W1_H02E0001\narc: H00L0100 E1_H02W0101\narc: H00R0000 V02N0401\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0301 S3_V06N0003\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0601 S3_V06N0303\narc: N1_V02N0701 H06E0203\narc: S1_V02S0001 H02E0001\narc: S1_V02S0301 E1_H01W0100\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0701 H06E0203\narc: S3_V06S0103 N1_V01S0100\narc: V00B0000 V02N0201\narc: V00B0100 H02W0701\narc: V00T0100 V02S0701\narc: W1_H02W0201 H01E0001\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0401 V02S0401\narc: W1_H02W0501 V06S0303\narc: W1_H02W0601 E1_H02W0301\narc: W1_H02W0701 E1_H02W0701\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0101 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: N1_V02N0501 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\narc: W3_H06W0103 V06S0103\narc: E3_H06E0203 W3_H06E0203\narc: A1 V02N0701\narc: A2 W1_H02E0701\narc: A3 H02W0501\narc: A4 W1_H02E0701\narc: A5 W1_H02E0501\narc: A6 F5\narc: A7 H02E0701\narc: B1 V02S0101\narc: B2 V02N0101\narc: B3 H00R0000\narc: B4 H02E0101\narc: B5 H00L0000\narc: B6 F1\narc: B7 V00B0000\narc: C1 S1_V02N0601\narc: C2 H02E0401\narc: C3 H00L0100\narc: C4 E1_H02W0601\narc: C5 E1_H02W0601\narc: C6 E1_H01E0101\narc: C7 H02W0401\narc: D1 V00B0100\narc: D2 V00T0100\narc: D3 S1_V02N0201\narc: D4 E1_H02W0001\narc: D5 N1_V02S0601\narc: D6 V02N0601\narc: D7 H02W0001\narc: E1_H01E0101 F3\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F2\narc: V01S0000 F7\narc: W3_H06W0203 F4\narc: W3_H06W0303 F6\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEB.K0.INIT 1000000010101010\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 1000000010101010\nword: SLICEC.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001001101011111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R9C56:PLC2\narc: E1_H02E0001 V02N0001\narc: E1_H02E0301 N1_V02S0301\narc: E1_H02E0401 V06N0203\narc: H00L0000 H02E0001\narc: H00R0000 H02E0601\narc: H00R0100 W1_H02E0701\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 S3_V06N0303\narc: S1_V02S0101 H06E0103\narc: S1_V02S0301 H02E0301\narc: S1_V02S0401 N1_V01S0000\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 H06E0203\narc: S3_V06S0003 H06E0003\narc: V00B0000 S1_V02N0001\narc: V00B0100 S1_V02N0101\narc: V00T0000 H02E0201\narc: V00T0100 V02N0701\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 V02S0401\narc: W1_H02W0601 V02N0601\narc: W1_H02W0701 S3_V06N0203\narc: H01W0100 W3_H06E0303\narc: S1_V02S0501 W3_H06E0303\narc: S3_V06S0103 W3_H06E0103\narc: W1_H02W0501 W3_H06E0303\narc: E3_H06E0103 W3_H06E0103\narc: A0 E1_H02W0501\narc: A1 H00L0000\narc: A4 H02W0701\narc: A5 N1_V01N0101\narc: A7 E1_H02W0701\narc: B0 W1_H02E0101\narc: B1 H00R0100\narc: B2 H00R0000\narc: B4 V02S0501\narc: B5 V01S0000\narc: B7 E1_H02W0101\narc: C0 H02W0401\narc: C1 H02W0401\narc: C2 N1_V01N0001\narc: C3 H02E0601\narc: C4 V00T0000\narc: C5 N1_V02S0001\narc: C7 V00B0100\narc: D0 V02S0201\narc: D1 S1_V02N0201\narc: D2 H02W0201\narc: D3 E1_H02W0001\narc: D4 H01W0000\narc: D5 V01N0001\narc: D7 V00B0000\narc: E1_H01E0001 F2\narc: E3_H06E0203 F4\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F5\narc: M2 V00T0100\narc: N1_V01N0101 F1\narc: V01S0000 F7\narc: W3_H06W0003 F0\nword: SLICEC.K0.INIT 0000110010101100\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 1000000010101010\nword: SLICEA.K1.INIT 0001001101011111\nword: SLICEB.K0.INIT 0000001111001111\nword: SLICEB.K1.INIT 1111000011111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R9C57:PLC2\narc: E1_H02E0201 V02N0201\narc: E1_H02E0401 S3_V06N0203\narc: E1_H02E0501 V01N0101\narc: E1_H02E0701 V06S0203\narc: H00R0000 E1_H02W0601\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0301 H06E0003\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0501 S3_V06N0303\narc: N1_V02N0601 H02W0601\narc: S1_V02S0401 S3_V06N0203\narc: S1_V02S0501 W1_H02E0501\narc: S1_V02S0601 W1_H02E0601\narc: S3_V06S0203 N1_V02S0701\narc: S3_V06S0303 N1_V01S0100\narc: V00B0100 W1_H02E0501\narc: V00T0000 W1_H02E0201\narc: V00T0100 H02E0301\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 S3_V06N0103\narc: W1_H02W0201 S3_V06N0103\narc: W1_H02W0301 E1_H02W0301\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 S1_V02N0501\narc: E1_H02E0101 W3_H06E0103\narc: N1_V02N0701 W3_H06E0203\narc: W1_H02W0601 W3_H06E0303\narc: W1_H02W0701 W3_H06E0203\narc: W3_H06W0203 S3_V06N0203\narc: A1 E1_H02W0501\narc: A3 V02S0701\narc: A4 E1_H01W0000\narc: A5 N1_V01N0101\narc: B1 E1_H02W0101\narc: B3 V02N0101\narc: B4 H02W0301\narc: B5 F3\narc: B6 V00B0100\narc: C1 H02W0401\narc: C3 H02E0401\narc: C4 V00T0000\narc: C5 E1_H02W0401\narc: C6 V02N0001\narc: C7 W1_H02E0601\narc: D1 E1_H02W0001\narc: D3 H00R0000\narc: D4 H00R0100\narc: D5 H02E0001\narc: D6 V02N0401\narc: D7 E1_H02W0201\narc: E3_H06E0203 F4\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H00R0100 F5\narc: H01W0000 F6\narc: M6 V00T0100\narc: N1_V01N0101 F1\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nword: SLICED.K0.INIT 0000001111001111\nword: SLICED.K1.INIT 1111000011111111\nword: SLICEC.K0.INIT 0000110010101100\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R9C58:PLC2\narc: E1_H02E0601 S3_V06N0303\narc: H00R0100 H02E0501\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 S3_V06N0203\narc: N1_V02N0501 S1_V02N0401\narc: N1_V02N0601 S3_V06N0303\narc: S1_V02S0401 H02E0401\narc: V01S0000 S3_V06N0103\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 V02S0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0601 V06N0303\narc: W1_H02W0701 E1_H01W0100\narc: H01W0000 W3_H06E0103\narc: N1_V02N0701 W3_H06E0203\narc: W1_H02W0301 W3_H06E0003\narc: W1_H02W0501 W3_H06E0303\narc: A1 H02E0701\narc: A7 H02W0501\narc: B1 V02N0101\narc: B7 V02N0701\narc: C1 V02N0601\narc: C7 E1_H02W0601\narc: D1 H02E0201\narc: D7 H00R0100\narc: E1_H01E0001 F1\narc: E1_H01E0101 F7\narc: F1 F1_SLICE\narc: F7 F7_SLICE\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001001101011111\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0001010100111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R9C59:PLC2\narc: N1_V01N0001 S3_V06N0003\narc: N1_V02N0001 S1_V02N0501\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 S1_V02N0401\narc: V01S0000 S3_V06N0103\narc: V01S0100 S3_V06N0303\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 H01E0101\narc: W1_H02W0401 H01E0001\narc: W1_H02W0601 S3_V06N0303\narc: H01W0100 W3_H06E0303\narc: W1_H02W0101 W3_H06E0103\narc: W1_H02W0501 W3_H06E0303\n\n.tile R9C5:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0401 V02N0401\narc: E1_H02E0601 N1_V02S0601\narc: E1_H02E0701 E1_H01W0100\narc: H00L0000 V02N0001\narc: H00L0100 W1_H02E0301\narc: H00R0000 V02N0601\narc: N1_V02N0001 S1_V02N0001\narc: N1_V02N0301 S1_V02N0301\narc: N1_V02N0501 E1_H01W0100\narc: V00B0000 V02S0201\narc: V00B0100 V02S0101\narc: V00T0100 V02N0501\narc: W1_H02W0501 V02N0501\narc: W1_H02W0601 V02N0601\narc: C1 N1_V01N0001\narc: CE1 H00L0100\narc: CE2 H00L0000\narc: CE3 H00L0000\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q4\narc: E1_H02E0301 F1\narc: F1 F1_SLICE\narc: LSR0 V00T0100\narc: LSR1 V00T0100\narc: M2 W1_H02E0601\narc: M4 V00B0000\narc: M6 V00B0100\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V02N0201 Q2\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1111000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\n\n.tile R9C60:PLC2\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0601 W1_H02E0601\narc: W1_H02W0601 S1_V02N0601\narc: E1_H02E0001 W3_H06E0003\narc: N1_V02N0301 W3_H06E0003\narc: E3_H06E0303 W3_H06E0203\n\n.tile R9C61:PLC2\narc: E1_H02E0301 V02N0301\narc: E1_H02E0401 S1_V02N0401\narc: E3_H06E0303 N1_V01S0100\narc: N1_V02N0001 H02E0001\narc: E3_H06E0003 W3_H06E0303\narc: E3_H06E0203 W3_H06E0203\n\n.tile R9C62:PLC2\narc: N1_V02N0301 H02E0301\narc: N1_V02N0401 H02E0401\narc: S3_V06S0003 N1_V01S0000\narc: S3_V06S0303 N1_V01S0100\narc: E1_H02E0201 W3_H06E0103\narc: N1_V02N0201 W3_H06E0103\narc: W1_H02W0201 W3_H06E0103\narc: E3_H06E0203 W3_H06E0203\n\n.tile R9C63:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0601 S1_V02N0601\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 S1_V02N0401\narc: N1_V02N0601 S1_V02N0601\narc: E3_H06E0303 W3_H06E0203\n\n.tile R9C64:PLC2\narc: N1_V02N0201 S1_V02N0701\narc: N1_V02N0401 H02E0401\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H02E0601\narc: S3_V06S0203 N1_V01S0000\narc: S3_V06S0303 N1_V01S0100\n\n.tile R9C65:PLC2\narc: N1_V02N0401 S1_V02N0401\n\n.tile R9C66:PLC2\narc: E3_H06E0003 W3_H06E0303\n\n.tile R9C67:PLC2\narc: E3_H06E0003 W3_H06E0003\narc: E3_H06E0203 W3_H06E0203\n\n.tile R9C68:PLC2\narc: E3_H06E0303 W3_H06E0203\n\n.tile R9C69:PLC2\narc: S3_V06S0003 H06E0003\narc: S3_V06S0303 W3_H06E0303\n\n.tile R9C6:PLC2\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 E1_H01W0100\narc: H00R0000 E1_H02W0601\narc: H00R0100 V02N0701\narc: N1_V02N0001 N1_V01S0000\narc: N1_V02N0101 H02E0101\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H01E0101\narc: N1_V02N0601 H06E0303\narc: V00B0000 H02E0601\narc: V00B0100 H02E0701\narc: V00T0100 H02E0301\narc: W1_H02W0301 V02N0301\narc: W1_H02W0601 V02N0601\narc: A6 H00L0000\narc: B5 H02W0301\narc: B6 V00T0000\narc: C5 V02S0201\narc: C6 E1_H02W0401\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CLK0 G_HPBX0000\narc: D4 E1_H02W0201\narc: D5 V00B0000\narc: D6 H00R0100\narc: E1_H02E0401 F6\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q0\narc: H01W0100 Q4\narc: LSR0 H02W0501\narc: LSR1 H02W0501\narc: M0 H02W0601\narc: M2 V00B0100\narc: M4 H02E0401\narc: M6 V00T0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXLSR0 LSR0\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: N1_V02N0401 Q4\narc: V00T0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1111111100000000\nword: SLICEC.K1.INIT 1111000011001100\nword: SLICED.K0.INIT 0001010100111111\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R9C70:PLC2\narc: N1_V02N0701 H06E0203\narc: S3_V06S0003 H06E0003\n\n.tile R9C7:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0501 V01N0101\narc: E1_H02E0701 V02N0701\narc: H00L0000 V02S0201\narc: N1_V02N0201 H02E0201\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0301 E1_H02W0301\narc: S3_V06S0203 H06W0203\narc: S3_V06S0303 H06W0303\narc: V00B0100 H02W0501\narc: V00T0100 S1_V02N0701\narc: W1_H02W0301 V01N0101\narc: W1_H02W0501 V06N0303\narc: B7 V01S0000\narc: C7 N1_V02S0201\narc: CE0 E1_H02W0101\narc: CE1 H02W0101\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D6 H01W0000\narc: D7 N1_V02S0401\narc: E1_H01E0001 Q4\narc: E1_H02E0601 Q4\narc: F6 F5D_SLICE\narc: H01W0000 Q2\narc: H01W0100 Q2\narc: LSR0 E1_H02W0301\narc: LSR1 E1_H02W0301\narc: M0 V00T0100\narc: M2 V00B0100\narc: M4 V00T0100\narc: M6 W1_H02E0401\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: MUXLSR0 LSR1\narc: MUXLSR1 LSR0\narc: MUXLSR2 LSR0\narc: MUXLSR3 LSR1\narc: N1_V02N0601 Q6\narc: V01S0000 Q0\narc: V01S0100 Q0\narc: W1_H02W0601 Q6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 1111111100000000\nword: SLICED.K1.INIT 1111000011001100\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R9C8:PLC2\narc: E1_H02E0001 N1_V02S0001\narc: E1_H02E0501 W1_H02E0401\narc: H00L0100 E1_H02W0101\narc: H00R0100 E1_H02W0501\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 V01N0001\narc: N1_V02N0501 H02W0501\narc: N1_V02N0601 E1_H01W0000\narc: V00B0100 V02S0101\narc: V00T0000 V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0101 E1_H02W0001\narc: W1_H02W0201 H01E0001\narc: W1_H02W0401 V02N0401\narc: W1_H02W0501 V02S0501\narc: W1_H02W0601 V01N0001\narc: W3_H06W0003 V06S0003\narc: A1 V02S0501\narc: A3 V00T0000\narc: A4 H02E0701\narc: A6 N1_V01N0101\narc: A7 H02E0501\narc: B1 V02N0301\narc: B3 W1_H02E0301\narc: B4 V02N0701\narc: B6 N1_V01S0000\narc: B7 V01S0000\narc: C0 V02N0601\narc: C1 H00R0100\narc: C3 H00L0100\narc: C4 H02W0401\narc: C6 V02N0001\narc: C7 E1_H02W0401\narc: CE0 H02E0101\narc: CLK0 G_HPBX0000\narc: D0 N1_V02S0001\narc: D1 V02N0201\narc: D3 V00B0100\narc: D4 S1_V02N0601\narc: D6 H00R0100\narc: D7 H01W0000\narc: E1_H01E0101 F3\narc: E1_H02E0701 F7\narc: E3_H06E0003 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F4 F5C_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F1\narc: LSR1 H02W0301\narc: M4 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0101 Q0\narc: V01S0000 F6\narc: V01S0100 F0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0001010100111111\nword: SLICEA.K0.INIT 0000000011110000\nword: SLICEA.K1.INIT 1110110011001100\nword: SLICED.K0.INIT 0001010100111111\nword: SLICED.K1.INIT 0100110000000000\nword: SLICEC.K0.INIT 0001001101011111\nword: SLICEC.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R9C9:PLC2\narc: E1_H02E0001 V02S0001\narc: E1_H02E0401 V02N0401\narc: E3_H06E0203 S3_V06N0203\narc: H00L0000 V02S0201\narc: H00L0100 E1_H02W0101\narc: H00R0000 V02N0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 E3_H06W0003\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0301 E1_H01W0100\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 E3_H06W0303\narc: N1_V02N0601 E3_H06W0303\narc: N1_V02N0701 N1_V01S0100\narc: S1_V02S0701 N1_V02S0701\narc: S3_V06S0203 N1_V01S0000\narc: V00B0000 W1_H02E0601\narc: V00B0100 V02S0101\narc: V00T0000 H02E0001\narc: W1_H02W0001 N1_V01S0000\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 V02N0301\narc: W1_H02W0401 E1_H01W0000\narc: N1_V02N0201 W3_H06E0103\narc: W3_H06W0103 E1_H01W0100\narc: A1 H00L0100\narc: A2 V01N0101\narc: A3 H02E0501\narc: A7 V02S0301\narc: B1 V00T0000\narc: B2 H00R0000\narc: B3 H01W0100\narc: B7 V00B0000\narc: C1 H00R0100\narc: C2 H00L0000\narc: C3 N1_V01N0001\narc: C4 V02N0201\narc: C5 V02N0001\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: D2 H01E0101\narc: D3 S1_V02N0201\narc: D4 H02W0201\narc: D5 E1_H02W0001\narc: D7 N1_V02S0601\narc: E1_H01E0001 F5\narc: E3_H06E0103 Q1\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: H01W0100 F7\narc: LSR0 E1_H02W0301\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F2\narc: N3_V06N0203 F4\narc: N3_V06N0303 F5\narc: S1_V02S0501 F5\narc: S3_V06S0303 F5\narc: V00T0100 F3\narc: V01S0100 F4\narc: W1_H02W0501 F5\narc: W3_H06W0203 F4\narc: W3_H06W0303 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000111111111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0001010100111111\nword: SLICEC.K0.INIT 1111000000000000\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0111111100000000\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile TAP_R10C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R10C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R10C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R10C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R11C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R11C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R11C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R11C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R12C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R12C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R12C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R12C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R13C60:TAP_DRIVE_CIB\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R14C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R14C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R14C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R14C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R15C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R15C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R15C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R15C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R16C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R16C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R16C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R16C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R17C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R17C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R17C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R17C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R18C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R18C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R18C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R18C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R19C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R19C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R19C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R19C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R1C60:TAP_DRIVE_CIB\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R20C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R20C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R20C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R20C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R21C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R21C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R21C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R21C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R22C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R22C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R22C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R22C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R23C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R23C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R23C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R23C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R24C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R24C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R24C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R24C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R25C22:TAP_DRIVE_CIB\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R25C42:TAP_DRIVE_CIB\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R25C4:TAP_DRIVE_CIB\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R25C60:TAP_DRIVE_CIB\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R26C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R26C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R26C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R26C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R27C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R27C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R27C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R27C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R28C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R28C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R28C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R28C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R29C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R29C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R29C4:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R29C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R2C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R2C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R2C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R2C60:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R30C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R30C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R30C4:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R30C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R31C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R31C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R31C4:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R31C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R32C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R32C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R32C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R32C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R33C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R33C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R33C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R33C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R34C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R34C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R34C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R35C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R35C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R35C4:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R35C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R36C22:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R36C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R36C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R37C22:TAP_DRIVE_CIB\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R37C42:TAP_DRIVE_CIB\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R37C60:TAP_DRIVE_CIB\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R3C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R3C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R3C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R40C60:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R41C60:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R43C60:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R44C60:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R4C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R4C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R4C4:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R4C60:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R5C22:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: R_HPBX0000 G_VPTX0000\n\n.tile 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018\n01b 019 0d0 19b 008 01d 108 048\n15c 0c8 158 000 199 000 199 059\n1c8 01d 05c 159 000 01b 000 19a\n01d 008 01c 1db 11a 04f 15c 00f\n118 00f 15b 017 1d8 0d9 1d8 01d\n1db 05c 0d9 108 198 1d8 15d 000\n1d8 0d9 159 19a 1da 118 0d9 000\n1d8 0d9 1dc 158 119 0dc 000 1db\n118 118 0d9 0c8 1db 017 0db 15c\n108 119 000 1db 11c 118 00f 05b\n09a 017 1d8 0d9 05c 000 1db 159\n04f 19c 05c 00f 15c 19b 14f 000\n1d8 0d9 15c 19b 188 15d 000 1db\n159 000 11c 159 01e 159 000 1db\n11c 000 11c 159 01e 158 000 1db\n05c 000 05c 119 0dc 05c 000 1db\n11a 000 11a 118 0d9 01c 019 1db\n118 000 118 119 0dc 05c 000 058\n1d8 000 11b 1dc 114 11c 000 05c\n1d8 000 11b 1dc 154 118 194 000\n1d8 000 1d8 000 05c 15d 000 11c\n091 000 14c 008 008 008 1c8 008\n1c8 1d7 14c 000 14c 008 1c8 008\n00a 1d7 01f 1d7 14c 000 14c 008\n00b 1d7 1c8 148 00f 0c6 002 14c\n008 1d7 1cb 1d7 1d7 10b 0c6 002\n14c 088 11b 15b 05a 05d 00b 05c\n0c8 09b 000 058 01b 1da 088 14c\n00c 09b 10b 11a 002 058 01b 1da\n088 14d 14c 10b 09c 000 1d2 158\n01d 188 048 00c 008 0cd 08c 000\n1da 1c8 0c8 08c 198 14d 000 11a\n1c8 0c8 08c 14d 18c 000 14f 14f\n14f 14f 0c6 1d4 016 14f 14f 14f\n14f 14f 002 09e 198 19a 000 14c\n0d5 09b 0c9 148 092 000 014 153\n000 14c 0d4 09b 0c9 159 01d 109\n090 000 14c 0d4 09b 109 11a 118\n000 14c 0d3 09b 109 090 000 14c\n150 14c 142 09a 000 14c 0c6 04e\n0d9 002 14c 054 016 042 052 109\n11a 148 1d5 000 153 000 115 019\n000 14f 14f 14f 056 05b 118 118\n0db 01b 14f 14f 14f 002 1db 048\n05d 09a 1da 059 119 000 14f 14f\n14f 14f 056 1db 016 14f 14f 14f\n14f 14f 002 088 01d 059 188 11b\n000 14f 14f 14f 00f 14c 0db 0d9\n01b 14f 14f 14f 14f 002 08e 11b\n019 14c 000 01c 15b 019 01d 19d\n000 002 11a 19a 114 013 0c8 1dd\n019 11b 19b 000 11a 19a 114 013\n008 1d9 019 11b 19b 000 11a 05b\n1db 091 008 009 18b 000 051 023\n051 1e3 1e4 155 0e6 1e7 153 1e9\n0ea 1eb 0ec 1ed 0ee 1ef 0f0 1f1\n0f2 1f3 0f4 1f5 0f6 1f7 0f8 1f9\n0fa 1fb 0fc 1fd 0fe 1ff 1c1 084\n106 000 015 0d5 000 10e 1df 000\n14e 000 000 000 000 000 000 000\n000 000 000 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EBR0.DP16KD.DATA_WIDTH_B 9\nenum: EBR0.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR0.REGMODE_A NOREG\nenum: EBR0.REGMODE_B NOREG\nenum: EBR0.RESETMODE SYNC\nenum: EBR0.ASYNC_RESET_RELEASE SYNC\nenum: EBR0.GSR DISABLED\nenum: EBR0.CLKAMUX CLKA\nenum: EBR0.CLKBMUX CLKB\nenum: EBR0.RSTAMUX INV\nenum: EBR0.RSTBMUX INV\nenum: EBR0.WEAMUX WEA\nenum: EBR0.WEBMUX INV\nenum: EBR0.CEAMUX CEA\nenum: EBR0.CEBMUX CEB\nenum: EBR0.OCEAMUX OCEA\nenum: EBR0.OCEBMUX OCEB\n\n.tile_group MIB_R37C13:MIB_EBR0 MIB_R37C14:MIB_EBR1\nword: EBR0.WID 011101000\nword: EBR0.CSDECODE_A 111\nword: EBR0.CSDECODE_B 111\nenum: EBR0.MODE DP16KD\nenum: EBR0.DP16KD.DATA_WIDTH_A 9\nenum: EBR0.DP16KD.DATA_WIDTH_B 9\nenum: EBR0.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR0.REGMODE_A NOREG\nenum: EBR0.REGMODE_B NOREG\nenum: EBR0.RESETMODE SYNC\nenum: EBR0.ASYNC_RESET_RELEASE SYNC\nenum: EBR0.GSR DISABLED\nenum: EBR0.CLKAMUX INV\nenum: EBR0.CLKBMUX CLKB\nenum: EBR0.RSTAMUX INV\nenum: EBR0.RSTBMUX INV\nenum: EBR0.WEAMUX INV\nenum: EBR0.WEBMUX INV\nenum: EBR0.CEAMUX CEA\nenum: EBR0.CEBMUX CEB\nenum: EBR0.OCEAMUX OCEA\nenum: EBR0.OCEBMUX OCEB\n\n.tile_group MIB_R37C17:MIB_EBR4 MIB_R37C18:MIB_EBR5 MIB_R37C19:MIB_EBR6\nword: EBR2.WID 101101000\nword: EBR2.CSDECODE_A 111\nword: EBR2.CSDECODE_B 111\nenum: EBR2.MODE DP16KD\nenum: EBR2.DP16KD.DATA_WIDTH_A 9\nenum: EBR2.DP16KD.DATA_WIDTH_B 9\nenum: EBR2.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR2.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR2.REGMODE_A NOREG\nenum: EBR2.REGMODE_B NOREG\nenum: EBR2.RESETMODE SYNC\nenum: EBR2.ASYNC_RESET_RELEASE SYNC\nenum: EBR2.GSR DISABLED\nenum: EBR2.CLKAMUX INV\nenum: EBR2.CLKBMUX CLKB\nenum: EBR2.RSTAMUX INV\nenum: EBR2.RSTBMUX INV\nenum: EBR2.WEAMUX INV\nenum: EBR2.WEBMUX INV\nenum: EBR2.CEAMUX CEA\nenum: EBR2.CEBMUX CEB\nenum: EBR2.OCEAMUX OCEA\nenum: EBR2.OCEBMUX OCEB\n\n.tile_group MIB_R37C22:MIB_EBR0 MIB_R37C23:MIB_EBR1\nword: EBR0.WID 001101000\nword: EBR0.CSDECODE_A 111\nword: EBR0.CSDECODE_B 111\nenum: EBR0.MODE DP16KD\nenum: EBR0.DP16KD.DATA_WIDTH_A 9\nenum: EBR0.DP16KD.DATA_WIDTH_B 9\nenum: EBR0.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR0.REGMODE_A NOREG\nenum: EBR0.REGMODE_B NOREG\nenum: EBR0.RESETMODE SYNC\nenum: EBR0.ASYNC_RESET_RELEASE SYNC\nenum: EBR0.GSR DISABLED\nenum: EBR0.CLKAMUX INV\nenum: EBR0.CLKBMUX CLKB\nenum: EBR0.RSTAMUX INV\nenum: EBR0.RSTBMUX INV\nenum: EBR0.WEAMUX INV\nenum: EBR0.WEBMUX INV\nenum: EBR0.CEAMUX CEA\nenum: EBR0.CEBMUX CEB\nenum: EBR0.OCEAMUX OCEA\nenum: EBR0.OCEBMUX OCEB\n\n.tile_group MIB_R37C15:MIB_EBR2 MIB_R37C16:MIB_EBR3 MIB_R37C17:MIB_EBR4\nword: EBR1.WID 010101000\nword: EBR1.CSDECODE_A 111\nword: EBR1.CSDECODE_B 111\nenum: EBR1.MODE DP16KD\nenum: EBR1.DP16KD.DATA_WIDTH_A 9\nenum: EBR1.DP16KD.DATA_WIDTH_B 9\nenum: EBR1.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR1.REGMODE_A NOREG\nenum: EBR1.REGMODE_B NOREG\nenum: EBR1.RESETMODE SYNC\nenum: EBR1.ASYNC_RESET_RELEASE SYNC\nenum: EBR1.GSR DISABLED\nenum: EBR1.CLKAMUX INV\nenum: EBR1.CLKBMUX CLKB\nenum: EBR1.RSTAMUX INV\nenum: EBR1.RSTBMUX INV\nenum: EBR1.WEAMUX INV\nenum: EBR1.WEBMUX INV\nenum: EBR1.CEAMUX CEA\nenum: EBR1.CEBMUX CEB\nenum: EBR1.OCEAMUX OCEA\nenum: EBR1.OCEBMUX OCEB\n\n.tile_group MIB_R37C26:MIB_EBR4 MIB_R37C27:MIB_EBR5 MIB_R37C28:MIB_EBR6\nword: EBR2.WID 000101000\nword: EBR2.CSDECODE_A 111\nword: EBR2.CSDECODE_B 111\nenum: EBR2.MODE DP16KD\nenum: EBR2.DP16KD.DATA_WIDTH_A 9\nenum: EBR2.DP16KD.DATA_WIDTH_B 9\nenum: EBR2.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR2.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR2.REGMODE_A NOREG\nenum: EBR2.REGMODE_B NOREG\nenum: EBR2.RESETMODE SYNC\nenum: EBR2.ASYNC_RESET_RELEASE SYNC\nenum: EBR2.GSR DISABLED\nenum: EBR2.CLKAMUX INV\nenum: EBR2.CLKBMUX CLKB\nenum: EBR2.RSTAMUX INV\nenum: EBR2.RSTBMUX INV\nenum: EBR2.WEAMUX INV\nenum: EBR2.WEBMUX INV\nenum: EBR2.CEAMUX CEA\nenum: EBR2.CEBMUX CEB\nenum: EBR2.OCEAMUX OCEA\nenum: EBR2.OCEBMUX OCEB\n\n.tile_group MIB_R37C33:EBR_CMUX_LR_25K MIB_R37C34:MIB_EBR1\nword: EBR0.WID 011001000\nword: EBR0.CSDECODE_A 111\nword: EBR0.CSDECODE_B 111\nenum: EBR0.MODE DP16KD\nenum: EBR0.DP16KD.DATA_WIDTH_A 9\nenum: EBR0.DP16KD.DATA_WIDTH_B 9\nenum: EBR0.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR0.REGMODE_A NOREG\nenum: EBR0.REGMODE_B NOREG\nenum: EBR0.RESETMODE SYNC\nenum: EBR0.ASYNC_RESET_RELEASE SYNC\nenum: EBR0.GSR DISABLED\nenum: EBR0.CLKAMUX INV\nenum: EBR0.CLKBMUX CLKB\nenum: EBR0.RSTAMUX INV\nenum: EBR0.RSTBMUX INV\nenum: EBR0.WEAMUX INV\nenum: EBR0.WEBMUX INV\nenum: EBR0.CEAMUX CEA\nenum: EBR0.CEBMUX CEB\nenum: EBR0.OCEAMUX OCEA\nenum: EBR0.OCEBMUX OCEB\n\n.tile_group MIB_R25C22:MIB_EBR0 MIB_R25C23:MIB_EBR1\nword: EBR0.WID 101001000\nword: EBR0.CSDECODE_A 111\nword: EBR0.CSDECODE_B 111\nenum: EBR0.MODE DP16KD\nenum: EBR0.DP16KD.DATA_WIDTH_A 9\nenum: EBR0.DP16KD.DATA_WIDTH_B 9\nenum: EBR0.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR0.REGMODE_A NOREG\nenum: EBR0.REGMODE_B NOREG\nenum: EBR0.RESETMODE SYNC\nenum: EBR0.ASYNC_RESET_RELEASE SYNC\nenum: EBR0.GSR DISABLED\nenum: EBR0.CLKAMUX INV\nenum: EBR0.CLKBMUX CLKB\nenum: EBR0.RSTAMUX INV\nenum: EBR0.RSTBMUX INV\nenum: EBR0.WEAMUX INV\nenum: EBR0.WEBMUX INV\nenum: EBR0.CEAMUX CEA\nenum: EBR0.CEBMUX CEB\nenum: EBR0.OCEAMUX OCEA\nenum: EBR0.OCEBMUX OCEB\n\n.tile_group MIB_R37C39:MIB_EBR6 MIB_R37C40:MIB_EBR7 MIB_R37C41:EBR_SPINE_LR0\nword: EBR3.WID 001001000\nword: EBR3.CSDECODE_A 111\nword: EBR3.CSDECODE_B 111\nenum: EBR3.MODE DP16KD\nenum: EBR3.DP16KD.DATA_WIDTH_A 9\nenum: EBR3.DP16KD.DATA_WIDTH_B 9\nenum: EBR3.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR3.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR3.REGMODE_A NOREG\nenum: EBR3.REGMODE_B NOREG\nenum: EBR3.RESETMODE SYNC\nenum: EBR3.ASYNC_RESET_RELEASE SYNC\nenum: EBR3.GSR DISABLED\nenum: EBR3.CLKAMUX INV\nenum: EBR3.CLKBMUX CLKB\nenum: EBR3.RSTAMUX INV\nenum: EBR3.RSTBMUX INV\nenum: EBR3.WEAMUX INV\nenum: EBR3.WEBMUX INV\nenum: EBR3.CEAMUX CEA\nenum: EBR3.CEBMUX CEB\nenum: EBR3.OCEAMUX OCEA\nenum: EBR3.OCEBMUX OCEB\n\n.tile_group MIB_R37C64:MIB_EBR4 MIB_R37C65:MIB_EBR5 MIB_R37C66:MIB_EBR6\nword: EBR2.WID 110001000\nword: EBR2.CSDECODE_A 111\nword: EBR2.CSDECODE_B 111\nenum: EBR2.MODE DP16KD\nenum: EBR2.DP16KD.DATA_WIDTH_A 9\nenum: EBR2.DP16KD.DATA_WIDTH_B 9\nenum: EBR2.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR2.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR2.REGMODE_A NOREG\nenum: EBR2.REGMODE_B NOREG\nenum: EBR2.RESETMODE SYNC\nenum: EBR2.ASYNC_RESET_RELEASE SYNC\nenum: EBR2.GSR DISABLED\nenum: EBR2.CLKAMUX INV\nenum: EBR2.CLKBMUX CLKB\nenum: EBR2.RSTAMUX INV\nenum: EBR2.RSTBMUX INV\nenum: EBR2.WEAMUX INV\nenum: EBR2.WEBMUX INV\nenum: EBR2.CEAMUX CEA\nenum: EBR2.CEBMUX CEB\nenum: EBR2.OCEAMUX OCEA\nenum: EBR2.OCEBMUX OCEB\n\n.tile_group MIB_R37C62:MIB_EBR2 MIB_R37C63:MIB_EBR3 MIB_R37C64:MIB_EBR4\nword: EBR1.WID 010001000\nword: EBR1.CSDECODE_A 111\nword: EBR1.CSDECODE_B 111\nenum: EBR1.MODE DP16KD\nenum: EBR1.DP16KD.DATA_WIDTH_A 9\nenum: EBR1.DP16KD.DATA_WIDTH_B 9\nenum: EBR1.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR1.REGMODE_A NOREG\nenum: EBR1.REGMODE_B NOREG\nenum: EBR1.RESETMODE SYNC\nenum: EBR1.ASYNC_RESET_RELEASE SYNC\nenum: EBR1.GSR DISABLED\nenum: EBR1.CLKAMUX INV\nenum: EBR1.CLKBMUX CLKB\nenum: EBR1.RSTAMUX INV\nenum: EBR1.RSTBMUX INV\nenum: EBR1.WEAMUX INV\nenum: EBR1.WEBMUX INV\nenum: EBR1.CEAMUX CEA\nenum: EBR1.CEBMUX CEB\nenum: EBR1.OCEAMUX OCEA\nenum: EBR1.OCEBMUX OCEB\n\n.tile_group MIB_R25C17:MIB_EBR4 MIB_R25C18:MIB_EBR5 MIB_R25C19:MIB_EBR6\nword: EBR2.WID 011110000\nword: EBR2.CSDECODE_A 111\nword: EBR2.CSDECODE_B 111\nenum: EBR2.MODE DP16KD\nenum: EBR2.DP16KD.DATA_WIDTH_A 9\nenum: EBR2.DP16KD.DATA_WIDTH_B 9\nenum: EBR2.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR2.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR2.REGMODE_A NOREG\nenum: EBR2.REGMODE_B NOREG\nenum: EBR2.RESETMODE SYNC\nenum: EBR2.ASYNC_RESET_RELEASE SYNC\nenum: EBR2.GSR DISABLED\nenum: EBR2.CLKAMUX INV\nenum: EBR2.CLKBMUX CLKB\nenum: EBR2.RSTAMUX INV\nenum: EBR2.RSTBMUX INV\nenum: EBR2.WEAMUX INV\nenum: EBR2.WEBMUX INV\nenum: EBR2.CEAMUX CEA\nenum: EBR2.CEBMUX CEB\nenum: EBR2.OCEAMUX OCEA\nenum: EBR2.OCEBMUX OCEB\n\n.tile_group MIB_R25C13:MIB_EBR0 MIB_R25C14:MIB_EBR1\nword: EBR0.WID 110011000\nword: EBR0.CSDECODE_A 111\nword: EBR0.CSDECODE_B 111\nenum: EBR0.MODE PDPW16KD\nenum: EBR0.PDPW16KD.DATA_WIDTH_R 36\nenum: EBR0.REGMODE_A NOREG\nenum: EBR0.REGMODE_B NOREG\nenum: EBR0.RESETMODE SYNC\nenum: EBR0.ASYNC_RESET_RELEASE SYNC\nenum: EBR0.GSR DISABLED\nenum: EBR0.CLKAMUX CLKA\nenum: EBR0.CLKBMUX CLKB\nenum: EBR0.RSTAMUX INV\nenum: EBR0.RSTBMUX INV\nenum: EBR0.CEAMUX CEA\nenum: EBR0.CEBMUX CEB\nenum: EBR0.OCEAMUX OCEA\nenum: EBR0.OCEBMUX OCEB\n\n.tile_group MIB_R25C35:MIB_EBR2 MIB_R25C36:MIB_EBR3 MIB_R25C37:MIB_EBR4\nword: EBR1.WID 010100000\nword: EBR1.CSDECODE_A 111\nword: EBR1.CSDECODE_B 111\nenum: EBR1.MODE PDPW16KD\nenum: EBR1.PDPW16KD.DATA_WIDTH_R 36\nenum: EBR1.REGMODE_A NOREG\nenum: EBR1.REGMODE_B NOREG\nenum: EBR1.RESETMODE SYNC\nenum: EBR1.ASYNC_RESET_RELEASE SYNC\nenum: EBR1.GSR DISABLED\nenum: EBR1.CLKAMUX CLKA\nenum: EBR1.CLKBMUX CLKB\nenum: EBR1.RSTAMUX INV\nenum: EBR1.RSTBMUX INV\nenum: EBR1.CEAMUX CEA\nenum: EBR1.CEBMUX CEB\nenum: EBR1.OCEAMUX OCEA\nenum: EBR1.OCEBMUX OCEB\n\n.tile_group MIB_R25C33:MIB_EBR0 MIB_R25C34:MIB_EBR1\nword: EBR0.WID 011000000\nword: EBR0.CSDECODE_A 111\nword: EBR0.CSDECODE_B 111\nenum: EBR0.MODE DP16KD\nenum: EBR0.DP16KD.DATA_WIDTH_A 9\nenum: EBR0.DP16KD.DATA_WIDTH_B 9\nenum: EBR0.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR0.REGMODE_A NOREG\nenum: EBR0.REGMODE_B NOREG\nenum: EBR0.RESETMODE SYNC\nenum: EBR0.ASYNC_RESET_RELEASE SYNC\nenum: EBR0.GSR DISABLED\nenum: EBR0.CLKAMUX CLKA\nenum: EBR0.CLKBMUX CLKB\nenum: EBR0.RSTAMUX INV\nenum: EBR0.RSTBMUX INV\nenum: EBR0.WEAMUX WEA\nenum: EBR0.WEBMUX INV\nenum: EBR0.CEAMUX CEA\nenum: EBR0.CEBMUX CEB\nenum: EBR0.OCEAMUX OCEA\nenum: EBR0.OCEBMUX OCEB\n\n.tile_group MIB_R25C10:MIB_EBR6 MIB_R25C11:MIB_EBR7 MIB_R25C12:MIB_EBR8\nword: EBR3.WID 101000000\nword: EBR3.CSDECODE_A 111\nword: EBR3.CSDECODE_B 111\nenum: EBR3.MODE PDPW16KD\nenum: EBR3.PDPW16KD.DATA_WIDTH_R 36\nenum: EBR3.REGMODE_A NOREG\nenum: EBR3.REGMODE_B NOREG\nenum: EBR3.RESETMODE SYNC\nenum: EBR3.ASYNC_RESET_RELEASE SYNC\nenum: EBR3.GSR DISABLED\nenum: EBR3.CLKAMUX CLKA\nenum: EBR3.CLKBMUX CLKB\nenum: EBR3.RSTAMUX INV\nenum: EBR3.RSTBMUX INV\nenum: EBR3.CEAMUX CEA\nenum: EBR3.CEBMUX CEB\nenum: EBR3.OCEAMUX OCEA\nenum: EBR3.OCEBMUX OCEB\n\n.tile_group MIB_R25C26:MIB_EBR4 MIB_R25C27:MIB_EBR5 MIB_R25C28:MIB_EBR6\nword: EBR2.WID 001000000\nword: EBR2.CSDECODE_A 111\nword: EBR2.CSDECODE_B 111\nenum: EBR2.MODE DP16KD\nenum: EBR2.DP16KD.DATA_WIDTH_A 18\nenum: EBR2.DP16KD.DATA_WIDTH_B 18\nenum: EBR2.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR2.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR2.REGMODE_A NOREG\nenum: EBR2.REGMODE_B NOREG\nenum: EBR2.RESETMODE SYNC\nenum: EBR2.ASYNC_RESET_RELEASE SYNC\nenum: EBR2.GSR DISABLED\nenum: EBR2.CLKAMUX CLKA\nenum: EBR2.CLKBMUX CLKB\nenum: EBR2.RSTAMUX INV\nenum: EBR2.RSTBMUX INV\nenum: EBR2.WEAMUX WEA\nenum: EBR2.WEBMUX INV\nenum: EBR2.CEAMUX CEA\nenum: EBR2.CEBMUX CEB\nenum: EBR2.OCEAMUX OCEA\nenum: EBR2.OCEBMUX OCEB\n\n.tile_group MIB_R37C19:MIB_EBR6 MIB_R37C20:MIB_EBR7 MIB_R37C21:EBR_SPINE_LL0\nword: EBR3.WID 110101000\nword: EBR3.CSDECODE_A 111\nword: EBR3.CSDECODE_B 111\nenum: EBR3.MODE DP16KD\nenum: EBR3.DP16KD.DATA_WIDTH_A 9\nenum: EBR3.DP16KD.DATA_WIDTH_B 9\nenum: EBR3.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR3.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR3.REGMODE_A NOREG\nenum: EBR3.REGMODE_B NOREG\nenum: EBR3.RESETMODE SYNC\nenum: EBR3.ASYNC_RESET_RELEASE SYNC\nenum: EBR3.GSR DISABLED\nenum: EBR3.CLKAMUX INV\nenum: EBR3.CLKBMUX CLKB\nenum: EBR3.RSTAMUX INV\nenum: EBR3.RSTBMUX INV\nenum: EBR3.WEAMUX INV\nenum: EBR3.WEBMUX INV\nenum: EBR3.CEAMUX CEA\nenum: EBR3.CEBMUX CEB\nenum: EBR3.OCEAMUX OCEA\nenum: EBR3.OCEBMUX OCEB\n\n.tile_group MIB_R25C53:MIB_EBR2 MIB_R25C54:MIB_EBR3 MIB_R25C55:MIB_EBR4\nword: EBR1.WID 011100000\nword: EBR1.CSDECODE_A 111\nword: EBR1.CSDECODE_B 111\nenum: EBR1.MODE DP16KD\nenum: EBR1.DP16KD.DATA_WIDTH_A 9\nenum: EBR1.DP16KD.DATA_WIDTH_B 9\nenum: EBR1.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR1.REGMODE_A NOREG\nenum: EBR1.REGMODE_B NOREG\nenum: EBR1.RESETMODE SYNC\nenum: EBR1.ASYNC_RESET_RELEASE SYNC\nenum: EBR1.GSR DISABLED\nenum: EBR1.CLKAMUX CLKA\nenum: EBR1.CLKBMUX CLKB\nenum: EBR1.RSTAMUX INV\nenum: EBR1.RSTBMUX INV\nenum: EBR1.WEAMUX WEA\nenum: EBR1.WEBMUX INV\nenum: EBR1.CEAMUX CEA\nenum: EBR1.CEBMUX CEB\nenum: EBR1.OCEAMUX OCEA\nenum: EBR1.OCEBMUX OCEB\n\n.tile_group MIB_R37C28:MIB_EBR6 MIB_R37C29:MIB_EBR7 MIB_R37C30:EBR_CMUX_LL_25K\nword: EBR3.WID 111001000\nword: EBR3.CSDECODE_A 111\nword: EBR3.CSDECODE_B 111\nenum: EBR3.MODE DP16KD\nenum: EBR3.DP16KD.DATA_WIDTH_A 9\nenum: EBR3.DP16KD.DATA_WIDTH_B 9\nenum: EBR3.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR3.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR3.REGMODE_A NOREG\nenum: EBR3.REGMODE_B NOREG\nenum: EBR3.RESETMODE SYNC\nenum: EBR3.ASYNC_RESET_RELEASE SYNC\nenum: EBR3.GSR DISABLED\nenum: EBR3.CLKAMUX INV\nenum: EBR3.CLKBMUX CLKB\nenum: EBR3.RSTAMUX INV\nenum: EBR3.RSTBMUX INV\nenum: EBR3.WEAMUX INV\nenum: EBR3.WEBMUX INV\nenum: EBR3.CEAMUX CEA\nenum: EBR3.CEBMUX CEB\nenum: EBR3.OCEAMUX OCEA\nenum: EBR3.OCEBMUX OCEB\n\n.tile_group MIB_R25C42:MIB_EBR0 MIB_R25C43:MIB_EBR1\nword: EBR0.WID 100100000\nword: EBR0.CSDECODE_A 111\nword: EBR0.CSDECODE_B 111\nenum: EBR0.MODE DP16KD\nenum: EBR0.DP16KD.DATA_WIDTH_A 9\nenum: EBR0.DP16KD.DATA_WIDTH_B 9\nenum: EBR0.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR0.REGMODE_A NOREG\nenum: EBR0.REGMODE_B NOREG\nenum: EBR0.RESETMODE SYNC\nenum: EBR0.ASYNC_RESET_RELEASE SYNC\nenum: EBR0.GSR DISABLED\nenum: EBR0.CLKAMUX CLKA\nenum: EBR0.CLKBMUX CLKB\nenum: EBR0.RSTAMUX INV\nenum: EBR0.RSTBMUX INV\nenum: EBR0.WEAMUX WEA\nenum: EBR0.WEBMUX INV\nenum: EBR0.CEAMUX CEA\nenum: EBR0.CEBMUX CEB\nenum: EBR0.OCEAMUX OCEA\nenum: EBR0.OCEBMUX OCEB\n\n.tile_group MIB_R37C66:MIB_EBR6 MIB_R37C67:MIB_EBR7 MIB_R37C68:MIB_EBR8\nword: EBR3.WID 100001000\nword: EBR3.CSDECODE_A 111\nword: EBR3.CSDECODE_B 111\nenum: EBR3.MODE DP16KD\nenum: EBR3.DP16KD.DATA_WIDTH_A 9\nenum: EBR3.DP16KD.DATA_WIDTH_B 9\nenum: EBR3.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR3.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR3.REGMODE_A NOREG\nenum: EBR3.REGMODE_B NOREG\nenum: EBR3.RESETMODE SYNC\nenum: EBR3.ASYNC_RESET_RELEASE SYNC\nenum: EBR3.GSR DISABLED\nenum: EBR3.CLKAMUX INV\nenum: EBR3.CLKBMUX CLKB\nenum: EBR3.RSTAMUX INV\nenum: EBR3.RSTBMUX INV\nenum: EBR3.WEAMUX INV\nenum: EBR3.WEBMUX INV\nenum: EBR3.CEAMUX CEA\nenum: EBR3.CEBMUX CEB\nenum: EBR3.OCEAMUX OCEA\nenum: EBR3.OCEBMUX OCEB\n\n.tile_group MIB_R25C66:MIB_EBR6 MIB_R25C67:MIB_EBR7 MIB_R25C68:MIB_EBR8\nword: EBR3.WID 000011000\nword: EBR3.CSDECODE_A 111\nword: EBR3.CSDECODE_B 111\nenum: EBR3.MODE DP16KD\nenum: EBR3.DP16KD.DATA_WIDTH_A 9\nenum: EBR3.DP16KD.DATA_WIDTH_B 9\nenum: EBR3.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR3.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR3.REGMODE_A NOREG\nenum: EBR3.REGMODE_B NOREG\nenum: EBR3.RESETMODE SYNC\nenum: EBR3.ASYNC_RESET_RELEASE SYNC\nenum: EBR3.GSR DISABLED\nenum: EBR3.CLKAMUX CLKA\nenum: EBR3.CLKBMUX CLKB\nenum: EBR3.RSTAMUX INV\nenum: EBR3.RSTBMUX INV\nenum: EBR3.WEAMUX WEA\nenum: EBR3.WEBMUX INV\nenum: EBR3.CEAMUX CEA\nenum: EBR3.CEBMUX CEB\nenum: EBR3.OCEAMUX OCEA\nenum: EBR3.OCEBMUX OCEB\n\n.tile_group MIB_R25C60:MIB_EBR0 MIB_R25C61:MIB_EBR1\nword: EBR0.WID 010010000\nword: EBR0.CSDECODE_A 111\nword: EBR0.CSDECODE_B 111\nenum: EBR0.MODE DP16KD\nenum: EBR0.DP16KD.DATA_WIDTH_A 9\nenum: EBR0.DP16KD.DATA_WIDTH_B 9\nenum: EBR0.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR0.REGMODE_A NOREG\nenum: EBR0.REGMODE_B NOREG\nenum: EBR0.RESETMODE SYNC\nenum: EBR0.ASYNC_RESET_RELEASE SYNC\nenum: EBR0.GSR DISABLED\nenum: EBR0.CLKAMUX CLKA\nenum: EBR0.CLKBMUX CLKB\nenum: EBR0.RSTAMUX INV\nenum: EBR0.RSTBMUX INV\nenum: EBR0.WEAMUX WEA\nenum: EBR0.WEBMUX INV\nenum: EBR0.CEAMUX CEA\nenum: EBR0.CEBMUX CEB\nenum: EBR0.OCEAMUX OCEA\nenum: EBR0.OCEBMUX OCEB\n\n.tile_group MIB_R25C64:MIB_EBR4 MIB_R25C65:MIB_EBR5 MIB_R25C66:MIB_EBR6\nword: EBR2.WID 010110000\nword: EBR2.CSDECODE_A 111\nword: EBR2.CSDECODE_B 111\nenum: EBR2.MODE DP16KD\nenum: EBR2.DP16KD.DATA_WIDTH_A 9\nenum: EBR2.DP16KD.DATA_WIDTH_B 9\nenum: EBR2.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR2.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR2.REGMODE_A NOREG\nenum: EBR2.REGMODE_B NOREG\nenum: EBR2.RESETMODE SYNC\nenum: EBR2.ASYNC_RESET_RELEASE SYNC\nenum: EBR2.GSR DISABLED\nenum: EBR2.CLKAMUX CLKA\nenum: EBR2.CLKBMUX CLKB\nenum: EBR2.RSTAMUX INV\nenum: EBR2.RSTBMUX INV\nenum: EBR2.WEAMUX WEA\nenum: EBR2.WEBMUX INV\nenum: EBR2.CEAMUX CEA\nenum: EBR2.CEBMUX CEB\nenum: EBR2.OCEAMUX OCEA\nenum: EBR2.OCEBMUX OCEB\n\n.tile_group MIB_R13C55:MIB_DSP4 MIB_R13C55:MIB2_DSP4 MIB_R13C56:MIB_DSP5 MIB_R13C56:MIB2_DSP5 MIB_R13C57:MIB_DSP6 MIB_R13C57:MIB2_DSP6 MIB_R13C58:MIB_DSP7 MIB_R13C58:MIB2_DSP7 MIB_R13C59:DSP_SPINE_UR1 MIB_R13C59:MIB2_DSP8\nenum: MULT18_4.REG_INPUTA_CLK NONE\nenum: MULT18_4.REG_INPUTA_CE CE0\nenum: MULT18_4.REG_INPUTA_RST RST0\nenum: MULT18_4.REG_INPUTB_CLK NONE\nenum: MULT18_4.REG_INPUTB_CE CE0\nenum: MULT18_4.REG_INPUTB_RST RST0\nenum: MULT18_4.REG_INPUTC_CLK NONE\nenum: MULT18_4.REG_PIPELINE_CLK NONE\nenum: MULT18_4.REG_PIPELINE_CE CE0\nenum: MULT18_4.REG_PIPELINE_RST RST0\nenum: MULT18_4.REG_OUTPUT_CLK NONE\nenum: MULT18_4.REG_OUTPUT_RST RST0\nenum: MULT18_4.CLK0_DIV ENABLED\nenum: MULT18_4.CLK1_DIV ENABLED\nenum: MULT18_4.CLK2_DIV ENABLED\nenum: MULT18_4.CLK3_DIV ENABLED\nenum: MULT18_4.GSR ENABLED\nenum: MULT18_4.SOURCEB_MODE B_SHIFT\nenum: MULT18_4.RESETMODE SYNC\nenum: MULT18_4.MODE MULT18X18D\nenum: MULT18_4.CIBOUT_BYP ON\nenum: DSP_RIGHT.CIBOUT ON\nenum: MULT18_4.CLK0MUX CLK0\nenum: MULT18_4.CLK1MUX CLK1\nenum: MULT18_4.CLK2MUX CLK2\nenum: MULT18_4.CLK3MUX CLK3\nenum: MULT18_4.CE0MUX CE0\nenum: MULT18_4.CE1MUX CE1\nenum: MULT18_4.CE2MUX CE2\nenum: MULT18_4.CE3MUX CE3\nenum: MULT18_4.RST0MUX RST0\nenum: MULT18_4.RST1MUX RST1\nenum: MULT18_4.RST2MUX RST2\nenum: MULT18_4.RST3MUX RST3\n\n.tile_group MIB_R37C44:MIB_EBR2 MIB_R37C45:MIB_EBR3 MIB_R37C46:MIB_EBR4\nword: EBR1.WID 100010000\nword: EBR1.CSDECODE_A 111\nword: EBR1.CSDECODE_B 111\nenum: EBR1.MODE DP16KD\nenum: EBR1.DP16KD.DATA_WIDTH_A 9\nenum: EBR1.DP16KD.DATA_WIDTH_B 9\nenum: EBR1.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR1.REGMODE_A NOREG\nenum: EBR1.REGMODE_B NOREG\nenum: EBR1.RESETMODE SYNC\nenum: EBR1.ASYNC_RESET_RELEASE SYNC\nenum: EBR1.GSR DISABLED\nenum: EBR1.CLKAMUX CLKA\nenum: EBR1.CLKBMUX CLKB\nenum: EBR1.RSTAMUX INV\nenum: EBR1.RSTBMUX INV\nenum: EBR1.WEAMUX WEA\nenum: EBR1.WEBMUX INV\nenum: EBR1.CEAMUX CEA\nenum: EBR1.CEBMUX CEB\nenum: EBR1.OCEAMUX OCEA\nenum: EBR1.OCEBMUX OCEB\n\n.tile_group MIB_R37C51:MIB_EBR0 MIB_R37C52:MIB_EBR1\nword: EBR0.WID 001010000\nword: EBR0.CSDECODE_A 111\nword: EBR0.CSDECODE_B 111\nenum: EBR0.MODE DP16KD\nenum: EBR0.DP16KD.DATA_WIDTH_A 9\nenum: EBR0.DP16KD.DATA_WIDTH_B 9\nenum: EBR0.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR0.REGMODE_A NOREG\nenum: EBR0.REGMODE_B NOREG\nenum: EBR0.RESETMODE SYNC\nenum: EBR0.ASYNC_RESET_RELEASE SYNC\nenum: EBR0.GSR DISABLED\nenum: EBR0.CLKAMUX CLKA\nenum: EBR0.CLKBMUX CLKB\nenum: EBR0.RSTAMUX INV\nenum: EBR0.RSTBMUX INV\nenum: EBR0.WEAMUX WEA\nenum: EBR0.WEBMUX INV\nenum: EBR0.CEAMUX CEA\nenum: EBR0.CEBMUX CEB\nenum: EBR0.OCEAMUX OCEA\nenum: EBR0.OCEBMUX OCEB\n\n.tile_group MIB_R25C62:MIB_EBR2 MIB_R25C63:MIB_EBR3 MIB_R25C64:MIB_EBR4\nword: EBR1.WID 011010000\nword: EBR1.CSDECODE_A 111\nword: EBR1.CSDECODE_B 111\nenum: EBR1.MODE DP16KD\nenum: EBR1.DP16KD.DATA_WIDTH_A 9\nenum: EBR1.DP16KD.DATA_WIDTH_B 9\nenum: EBR1.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR1.REGMODE_A NOREG\nenum: EBR1.REGMODE_B NOREG\nenum: EBR1.RESETMODE SYNC\nenum: EBR1.ASYNC_RESET_RELEASE SYNC\nenum: EBR1.GSR DISABLED\nenum: EBR1.CLKAMUX CLKA\nenum: EBR1.CLKBMUX CLKB\nenum: EBR1.RSTAMUX INV\nenum: EBR1.RSTBMUX INV\nenum: EBR1.WEAMUX WEA\nenum: EBR1.WEBMUX INV\nenum: EBR1.CEAMUX CEA\nenum: EBR1.CEBMUX CEB\nenum: EBR1.OCEAMUX OCEA\nenum: EBR1.OCEBMUX OCEB\n\n.tile_group MIB_R50C2:PLL0_LL MIB_R50C3:BANKREF8\nword: CLKI_DIV 0000000\nword: CLKFB_DIV 0001111\nword: CLKOP_DIV 0000111\nword: CLKOP_CPHASE 0000111\nword: CLKOP_FPHASE 000\nword: CLKOS_DIV 0000111\nword: CLKOS_CPHASE 0001001\nword: CLKOS_FPHASE 000\nword: CLKOS2_DIV 0000111\nword: CLKOS2_CPHASE 0000000\nword: CLKOS2_FPHASE 000\nword: CLKOS3_DIV 0000000\nword: CLKOS3_CPHASE 0010111\nword: CLKOS3_FPHASE 000\nword: PLL_LOCK_MODE 000\nword: KVCO 000\nword: LPF_CAPACITOR 00\nword: LPF_RESISTOR 0010000\nword: ICP_CURRENT 00110\nword: FREQ_LOCK_ACCURACY 00\nword: MFG_GMC_GAIN 000\nword: MFG_GMC_TEST 1110\nword: MFG1_TEST 000\nword: MFG2_TEST 000\nword: MFG_FORCE_VFILTER 0\nword: MFG_ICP_TEST 0\nword: MFG_EN_UP 0\nword: MFG_FLOAT_ICP 0\nword: MFG_GMC_PRESET 0\nword: MFG_LF_PRESET 0\nword: MFG_GMC_RESET 0\nword: MFG_LF_RESET 0\nword: MFG_LF_RESGRND 0\nword: MFG_GMCREF_SEL 10\nword: MFG_ENABLE_FILTEROPAMP 1\nenum: MODE EHXPLLL\nenum: CLKOP_ENABLE ENABLED\nenum: CLKOS_ENABLE ENABLED\nenum: CLKOS2_ENABLE ENABLED\nenum: CLKOS3_ENABLE ENABLED\nenum: FEEDBK_PATH INT_OS3\nenum: CLKOP_TRIM_POL RISING\nenum: CLKOP_TRIM_DELAY 0\nenum: CLKOS_TRIM_POL RISING\nenum: CLKOS_TRIM_DELAY 0\nenum: OUTDIVIDER_MUXA DIVA\nenum: OUTDIVIDER_MUXB DIVB\nenum: OUTDIVIDER_MUXC DIVC\nenum: OUTDIVIDER_MUXD DIVD\nenum: STDBY_ENABLE DISABLED\nenum: REFIN_RESET DISABLED\nenum: SYNC_ENABLE DISABLED\nenum: INT_LOCK_STICKY ENABLED\nenum: DPHASE_SOURCE DISABLED\nenum: PLLRST_ENA DISABLED\nenum: INTFB_WAKE DISABLED\n\n.tile_group MIB_R25C46:MIB_EBR4 MIB_R25C47:MIB_EBR5 MIB_R25C48:MIB_EBR6\nword: EBR2.WID 110100000\nword: EBR2.CSDECODE_A 111\nword: EBR2.CSDECODE_B 111\nenum: EBR2.MODE DP16KD\nenum: EBR2.DP16KD.DATA_WIDTH_A 9\nenum: EBR2.DP16KD.DATA_WIDTH_B 9\nenum: EBR2.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR2.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR2.REGMODE_A NOREG\nenum: EBR2.REGMODE_B NOREG\nenum: EBR2.RESETMODE SYNC\nenum: EBR2.ASYNC_RESET_RELEASE SYNC\nenum: EBR2.GSR DISABLED\nenum: EBR2.CLKAMUX CLKA\nenum: EBR2.CLKBMUX CLKB\nenum: EBR2.RSTAMUX INV\nenum: EBR2.RSTBMUX INV\nenum: EBR2.WEAMUX WEA\nenum: EBR2.WEBMUX INV\nenum: EBR2.CEAMUX CEA\nenum: EBR2.CEBMUX CEB\nenum: EBR2.OCEAMUX OCEA\nenum: EBR2.OCEBMUX OCEB\n\n.tile_group MIB_R25C15:MIB_EBR2 MIB_R25C16:MIB_EBR3 MIB_R25C17:MIB_EBR4\nword: EBR1.WID 110110000\nword: EBR1.CSDECODE_A 111\nword: EBR1.CSDECODE_B 111\nenum: EBR1.MODE DP16KD\nenum: EBR1.DP16KD.DATA_WIDTH_A 9\nenum: EBR1.DP16KD.DATA_WIDTH_B 9\nenum: EBR1.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR1.REGMODE_A NOREG\nenum: EBR1.REGMODE_B NOREG\nenum: EBR1.RESETMODE SYNC\nenum: EBR1.ASYNC_RESET_RELEASE SYNC\nenum: EBR1.GSR DISABLED\nenum: EBR1.CLKAMUX INV\nenum: EBR1.CLKBMUX CLKB\nenum: EBR1.RSTAMUX INV\nenum: EBR1.RSTBMUX INV\nenum: EBR1.WEAMUX INV\nenum: EBR1.WEBMUX INV\nenum: EBR1.CEAMUX CEA\nenum: EBR1.CEBMUX CEB\nenum: EBR1.OCEAMUX OCEA\nenum: EBR1.OCEBMUX OCEB\n\n.tile_group MIB_R37C37:MIB_EBR4 MIB_R37C38:MIB_EBR5 MIB_R37C39:MIB_EBR6\nword: EBR2.WID 001110000\nword: EBR2.CSDECODE_A 111\nword: EBR2.CSDECODE_B 111\nenum: EBR2.MODE DP16KD\nenum: EBR2.DP16KD.DATA_WIDTH_A 9\nenum: EBR2.DP16KD.DATA_WIDTH_B 9\nenum: EBR2.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR2.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR2.REGMODE_A NOREG\nenum: EBR2.REGMODE_B NOREG\nenum: EBR2.RESETMODE SYNC\nenum: EBR2.ASYNC_RESET_RELEASE SYNC\nenum: EBR2.GSR DISABLED\nenum: EBR2.CLKAMUX INV\nenum: EBR2.CLKBMUX CLKB\nenum: EBR2.RSTAMUX INV\nenum: EBR2.RSTBMUX INV\nenum: EBR2.WEAMUX INV\nenum: EBR2.WEBMUX INV\nenum: EBR2.CEAMUX CEA\nenum: EBR2.CEBMUX CEB\nenum: EBR2.OCEAMUX OCEA\nenum: EBR2.OCEBMUX OCEB\n\n.tile_group MIB_R37C35:MIB_EBR2 MIB_R37C36:MIB_EBR3 MIB_R37C37:MIB_EBR4\nword: EBR1.WID 101110000\nword: EBR1.CSDECODE_A 111\nword: EBR1.CSDECODE_B 111\nenum: EBR1.MODE DP16KD\nenum: EBR1.DP16KD.DATA_WIDTH_A 9\nenum: EBR1.DP16KD.DATA_WIDTH_B 9\nenum: EBR1.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR1.REGMODE_A NOREG\nenum: EBR1.REGMODE_B NOREG\nenum: EBR1.RESETMODE SYNC\nenum: EBR1.ASYNC_RESET_RELEASE SYNC\nenum: EBR1.GSR DISABLED\nenum: EBR1.CLKAMUX INV\nenum: EBR1.CLKBMUX CLKB\nenum: EBR1.RSTAMUX INV\nenum: EBR1.RSTBMUX INV\nenum: EBR1.WEAMUX INV\nenum: EBR1.WEBMUX INV\nenum: EBR1.CEAMUX CEA\nenum: EBR1.CEBMUX CEB\nenum: EBR1.OCEAMUX OCEA\nenum: EBR1.OCEBMUX OCEB\n\n.tile_group MIB_R25C19:MIB_EBR6 MIB_R25C20:MIB_EBR7 MIB_R25C21:MIB_EBR8\nword: EBR3.WID 111110000\nword: EBR3.CSDECODE_A 111\nword: EBR3.CSDECODE_B 111\nenum: EBR3.MODE DP16KD\nenum: EBR3.DP16KD.DATA_WIDTH_A 9\nenum: EBR3.DP16KD.DATA_WIDTH_B 9\nenum: EBR3.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR3.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR3.REGMODE_A NOREG\nenum: EBR3.REGMODE_B NOREG\nenum: EBR3.RESETMODE SYNC\nenum: EBR3.ASYNC_RESET_RELEASE SYNC\nenum: EBR3.GSR DISABLED\nenum: EBR3.CLKAMUX INV\nenum: EBR3.CLKBMUX CLKB\nenum: EBR3.RSTAMUX INV\nenum: EBR3.RSTBMUX INV\nenum: EBR3.WEAMUX INV\nenum: EBR3.WEBMUX INV\nenum: EBR3.CEAMUX CEA\nenum: EBR3.CEBMUX CEB\nenum: EBR3.OCEAMUX OCEA\nenum: EBR3.OCEBMUX OCEB\n\n.tile_group MIB_R37C60:MIB_EBR0 MIB_R37C61:MIB_EBR1\nword: EBR0.WID 000001000\nword: EBR0.CSDECODE_A 111\nword: EBR0.CSDECODE_B 111\nenum: EBR0.MODE DP16KD\nenum: EBR0.DP16KD.DATA_WIDTH_A 9\nenum: EBR0.DP16KD.DATA_WIDTH_B 9\nenum: EBR0.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR0.REGMODE_A NOREG\nenum: EBR0.REGMODE_B NOREG\nenum: EBR0.RESETMODE SYNC\nenum: EBR0.ASYNC_RESET_RELEASE SYNC\nenum: EBR0.GSR DISABLED\nenum: EBR0.CLKAMUX INV\nenum: EBR0.CLKBMUX CLKB\nenum: EBR0.RSTAMUX INV\nenum: EBR0.RSTBMUX INV\nenum: EBR0.WEAMUX INV\nenum: EBR0.WEBMUX INV\nenum: EBR0.CEAMUX CEA\nenum: EBR0.CEBMUX CEB\nenum: EBR0.OCEAMUX OCEA\nenum: EBR0.OCEBMUX OCEB\n\n.tile_group MIB_R37C46:MIB_EBR4 MIB_R37C47:MIB_EBR5 MIB_R37C48:MIB_EBR6\nword: EBR2.WID 101100000\nword: EBR2.CSDECODE_A 111\nword: EBR2.CSDECODE_B 111\nenum: EBR2.MODE DP16KD\nenum: EBR2.DP16KD.DATA_WIDTH_A 9\nenum: EBR2.DP16KD.DATA_WIDTH_B 9\nenum: EBR2.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR2.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR2.REGMODE_A NOREG\nenum: EBR2.REGMODE_B NOREG\nenum: EBR2.RESETMODE SYNC\nenum: EBR2.ASYNC_RESET_RELEASE SYNC\nenum: EBR2.GSR DISABLED\nenum: EBR2.CLKAMUX CLKA\nenum: EBR2.CLKBMUX CLKB\nenum: EBR2.RSTAMUX INV\nenum: EBR2.RSTBMUX INV\nenum: EBR2.WEAMUX WEA\nenum: EBR2.WEBMUX INV\nenum: EBR2.CEAMUX CEA\nenum: EBR2.CEBMUX CEB\nenum: EBR2.OCEAMUX OCEA\nenum: EBR2.OCEBMUX OCEB\n\n.tile_group MIB_R37C24:MIB_EBR2 MIB_R37C25:MIB_EBR3 MIB_R37C26:MIB_EBR4\nword: EBR1.WID 100101000\nword: EBR1.CSDECODE_A 111\nword: EBR1.CSDECODE_B 111\nenum: EBR1.MODE DP16KD\nenum: EBR1.DP16KD.DATA_WIDTH_A 9\nenum: EBR1.DP16KD.DATA_WIDTH_B 9\nenum: EBR1.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR1.REGMODE_A NOREG\nenum: EBR1.REGMODE_B NOREG\nenum: EBR1.RESETMODE SYNC\nenum: EBR1.ASYNC_RESET_RELEASE SYNC\nenum: EBR1.GSR DISABLED\nenum: EBR1.CLKAMUX INV\nenum: EBR1.CLKBMUX CLKB\nenum: EBR1.RSTAMUX INV\nenum: EBR1.RSTBMUX INV\nenum: EBR1.WEAMUX INV\nenum: EBR1.WEBMUX INV\nenum: EBR1.CEAMUX CEA\nenum: EBR1.CEBMUX CEB\nenum: EBR1.OCEAMUX OCEA\nenum: EBR1.OCEBMUX OCEB\n\n.tile_group MIB_R13C51:MIB_DSP0 MIB_R13C51:MIB2_DSP0 MIB_R13C52:MIB_DSP1 MIB_R13C52:MIB2_DSP1 MIB_R13C53:MIB_DSP2 MIB_R13C53:MIB2_DSP2 MIB_R13C54:MIB_DSP3 MIB_R13C54:MIB2_DSP3 MIB_R13C55:MIB_DSP4 MIB_R13C55:MIB2_DSP4\nenum: MULT18_1.REG_INPUTA_CLK NONE\nenum: MULT18_1.REG_INPUTA_CE CE0\nenum: MULT18_1.REG_INPUTA_RST RST0\nenum: MULT18_1.REG_INPUTB_CLK NONE\nenum: MULT18_1.REG_INPUTB_CE CE0\nenum: MULT18_1.REG_INPUTB_RST RST0\nenum: MULT18_1.REG_INPUTC_CLK NONE\nenum: MULT18_1.REG_PIPELINE_CLK NONE\nenum: MULT18_1.REG_PIPELINE_CE CE0\nenum: MULT18_1.REG_PIPELINE_RST RST0\nenum: MULT18_1.REG_OUTPUT_CLK NONE\nenum: MULT18_1.CLK0_DIV ENABLED\nenum: MULT18_1.CLK1_DIV ENABLED\nenum: MULT18_1.CLK2_DIV ENABLED\nenum: MULT18_1.CLK3_DIV ENABLED\nenum: MULT18_1.GSR ENABLED\nenum: MULT18_1.SOURCEB_MODE B_SHIFT\nenum: MULT18_1.RESETMODE SYNC\nenum: MULT18_1.MODE MULT18X18D\nenum: MULT18_1.CIBOUT_BYP ON\nenum: DSP_LEFT.CIBOUT ON\nenum: MULT18_1.CLK0MUX CLK0\nenum: MULT18_1.CLK1MUX CLK1\nenum: MULT18_1.CLK2MUX CLK2\nenum: MULT18_1.CLK3MUX CLK3\nenum: MULT18_1.CE0MUX CE0\nenum: MULT18_1.CE1MUX CE1\nenum: MULT18_1.CE2MUX CE2\nenum: MULT18_1.CE3MUX CE3\nenum: MULT18_1.RST0MUX RST0\nenum: MULT18_1.RST1MUX RST1\nenum: MULT18_1.RST2MUX RST2\nenum: MULT18_1.RST3MUX RST3\n\n.tile_group MIB_R25C24:MIB_EBR2 MIB_R25C25:MIB_EBR3 MIB_R25C26:MIB_EBR4\nword: EBR1.WID 111101000\nword: EBR1.CSDECODE_A 111\nword: EBR1.CSDECODE_B 111\nenum: EBR1.MODE DP16KD\nenum: EBR1.DP16KD.DATA_WIDTH_A 9\nenum: EBR1.DP16KD.DATA_WIDTH_B 9\nenum: EBR1.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR1.REGMODE_A NOREG\nenum: EBR1.REGMODE_B NOREG\nenum: EBR1.RESETMODE SYNC\nenum: EBR1.ASYNC_RESET_RELEASE SYNC\nenum: EBR1.GSR DISABLED\nenum: EBR1.CLKAMUX CLKA\nenum: EBR1.CLKBMUX CLKB\nenum: EBR1.RSTAMUX INV\nenum: EBR1.RSTBMUX INV\nenum: EBR1.WEAMUX WEA\nenum: EBR1.WEBMUX INV\nenum: EBR1.CEAMUX CEA\nenum: EBR1.CEBMUX CEB\nenum: EBR1.OCEAMUX OCEA\nenum: EBR1.OCEBMUX OCEB\n\n.tile_group MIB_R25C37:MIB_EBR4 MIB_R25C38:MIB_EBR5 MIB_R25C39:MIB_EBR6\nword: EBR2.WID 111000000\nword: EBR2.CSDECODE_A 111\nword: EBR2.CSDECODE_B 111\nenum: EBR2.MODE DP16KD\nenum: EBR2.DP16KD.DATA_WIDTH_A 9\nenum: EBR2.DP16KD.DATA_WIDTH_B 9\nenum: EBR2.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR2.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR2.REGMODE_A NOREG\nenum: EBR2.REGMODE_B NOREG\nenum: EBR2.RESETMODE SYNC\nenum: EBR2.ASYNC_RESET_RELEASE SYNC\nenum: EBR2.GSR DISABLED\nenum: EBR2.CLKAMUX CLKA\nenum: EBR2.CLKBMUX CLKB\nenum: EBR2.RSTAMUX INV\nenum: EBR2.RSTBMUX INV\nenum: EBR2.WEAMUX WEA\nenum: EBR2.WEBMUX INV\nenum: EBR2.CEAMUX CEA\nenum: EBR2.CEBMUX CEB\nenum: EBR2.OCEAMUX OCEA\nenum: EBR2.OCEBMUX OCEB\n\n.tile_group MIB_R25C39:MIB_EBR6 MIB_R25C40:MIB_EBR7 MIB_R25C41:MIB_EBR8\nword: EBR3.WID 000100000\nword: EBR3.CSDECODE_A 111\nword: EBR3.CSDECODE_B 111\nenum: EBR3.MODE DP16KD\nenum: EBR3.DP16KD.DATA_WIDTH_A 9\nenum: EBR3.DP16KD.DATA_WIDTH_B 9\nenum: EBR3.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR3.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR3.REGMODE_A NOREG\nenum: EBR3.REGMODE_B NOREG\nenum: EBR3.RESETMODE SYNC\nenum: EBR3.ASYNC_RESET_RELEASE SYNC\nenum: EBR3.GSR DISABLED\nenum: EBR3.CLKAMUX CLKA\nenum: EBR3.CLKBMUX CLKB\nenum: EBR3.RSTAMUX INV\nenum: EBR3.RSTBMUX INV\nenum: EBR3.WEAMUX WEA\nenum: EBR3.WEBMUX INV\nenum: EBR3.CEAMUX CEA\nenum: EBR3.CEBMUX CEB\nenum: EBR3.OCEAMUX OCEA\nenum: EBR3.OCEBMUX OCEB\n\n.tile_group MIB_R13C46:MIB_DSP4 MIB_R13C46:MIB2_DSP4 MIB_R13C47:MIB_DSP5 MIB_R13C47:MIB2_DSP5 MIB_R13C48:MIB_DSP6 MIB_R13C48:MIB2_DSP6 MIB_R13C49:MIB_DSP7 MIB_R13C49:MIB2_DSP7 MIB_R13C50:MIB_DSP8 MIB_R13C50:MIB2_DSP8\nenum: MULT18_5.REG_INPUTA_CLK NONE\nenum: MULT18_5.REG_INPUTA_CE CE0\nenum: MULT18_5.REG_INPUTA_RST RST0\nenum: MULT18_5.REG_INPUTB_CLK NONE\nenum: MULT18_5.REG_INPUTB_CE CE0\nenum: MULT18_5.REG_INPUTB_RST RST0\nenum: MULT18_5.REG_INPUTC_CLK NONE\nenum: MULT18_5.REG_PIPELINE_CLK NONE\nenum: MULT18_5.REG_PIPELINE_CE CE0\nenum: MULT18_5.REG_PIPELINE_RST RST0\nenum: MULT18_5.REG_OUTPUT_CLK NONE\nenum: MULT18_5.CLK0_DIV ENABLED\nenum: MULT18_5.CLK1_DIV ENABLED\nenum: MULT18_5.CLK2_DIV ENABLED\nenum: MULT18_5.CLK3_DIV ENABLED\nenum: MULT18_5.GSR ENABLED\nenum: MULT18_5.SOURCEB_MODE B_SHIFT\nenum: MULT18_5.RESETMODE SYNC\nenum: MULT18_5.MODE MULT18X18D\nenum: MULT18_5.CIBOUT_BYP ON\nenum: DSP_RIGHT.CIBOUT ON\nenum: MULT18_5.CLK0MUX CLK0\nenum: MULT18_5.CLK1MUX CLK1\nenum: MULT18_5.CLK2MUX CLK2\nenum: MULT18_5.CLK3MUX CLK3\nenum: MULT18_5.CE0MUX CE0\nenum: MULT18_5.CE1MUX CE1\nenum: MULT18_5.CE2MUX CE2\nenum: MULT18_5.CE3MUX CE3\nenum: MULT18_5.RST0MUX RST0\nenum: MULT18_5.RST1MUX RST1\nenum: MULT18_5.RST2MUX RST2\nenum: MULT18_5.RST3MUX RST3\n\n.tile_group MIB_R13C51:MIB_DSP0 MIB_R13C51:MIB2_DSP0 MIB_R13C52:MIB_DSP1 MIB_R13C52:MIB2_DSP1 MIB_R13C53:MIB_DSP2 MIB_R13C53:MIB2_DSP2 MIB_R13C54:MIB_DSP3 MIB_R13C54:MIB2_DSP3 MIB_R13C55:MIB_DSP4 MIB_R13C55:MIB2_DSP4\nenum: MULT18_0.REG_INPUTA_CLK NONE\nenum: MULT18_0.REG_INPUTA_CE CE0\nenum: MULT18_0.REG_INPUTA_RST RST0\nenum: MULT18_0.REG_INPUTB_CLK NONE\nenum: MULT18_0.REG_INPUTB_CE CE0\nenum: MULT18_0.REG_INPUTB_RST RST0\nenum: MULT18_0.REG_INPUTC_CLK NONE\nenum: MULT18_0.REG_PIPELINE_CLK NONE\nenum: MULT18_0.REG_PIPELINE_CE CE0\nenum: MULT18_0.REG_PIPELINE_RST RST0\nenum: MULT18_0.REG_OUTPUT_CLK NONE\nenum: MULT18_0.REG_OUTPUT_RST RST0\nenum: MULT18_0.CLK0_DIV ENABLED\nenum: MULT18_0.CLK1_DIV ENABLED\nenum: MULT18_0.CLK2_DIV ENABLED\nenum: MULT18_0.CLK3_DIV ENABLED\nenum: MULT18_0.GSR ENABLED\nenum: MULT18_0.SOURCEB_MODE B_SHIFT\nenum: MULT18_0.RESETMODE SYNC\nenum: MULT18_0.MODE MULT18X18D\nenum: MULT18_0.CIBOUT_BYP ON\nenum: DSP_LEFT.CIBOUT ON\nenum: MULT18_0.CLK0MUX CLK0\nenum: MULT18_0.CLK1MUX CLK1\nenum: MULT18_0.CLK2MUX CLK2\nenum: MULT18_0.CLK3MUX CLK3\nenum: MULT18_0.CE0MUX CE0\nenum: MULT18_0.CE1MUX CE1\nenum: MULT18_0.CE2MUX CE2\nenum: MULT18_0.CE3MUX CE3\nenum: MULT18_0.RST0MUX RST0\nenum: MULT18_0.RST1MUX RST1\nenum: MULT18_0.RST2MUX RST2\nenum: MULT18_0.RST3MUX RST3\n\n.tile_group MIB_R25C51:MIB_EBR0 MIB_R25C52:MIB_EBR1\nword: EBR0.WID 001100000\nword: EBR0.CSDECODE_A 111\nword: EBR0.CSDECODE_B 111\nenum: EBR0.MODE DP16KD\nenum: EBR0.DP16KD.DATA_WIDTH_A 9\nenum: EBR0.DP16KD.DATA_WIDTH_B 9\nenum: EBR0.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR0.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR0.REGMODE_A NOREG\nenum: EBR0.REGMODE_B NOREG\nenum: EBR0.RESETMODE SYNC\nenum: EBR0.ASYNC_RESET_RELEASE SYNC\nenum: EBR0.GSR DISABLED\nenum: EBR0.CLKAMUX CLKA\nenum: EBR0.CLKBMUX CLKB\nenum: EBR0.RSTAMUX INV\nenum: EBR0.RSTBMUX INV\nenum: EBR0.WEAMUX WEA\nenum: EBR0.WEBMUX INV\nenum: EBR0.CEAMUX CEA\nenum: EBR0.CEBMUX CEB\nenum: EBR0.OCEAMUX OCEA\nenum: EBR0.OCEBMUX OCEB\n\n.tile_group MIB_R25C48:MIB_EBR6 MIB_R25C49:MIB_EBR7 MIB_R25C50:MIB_EBR8\nword: EBR3.WID 111100000\nword: EBR3.CSDECODE_A 111\nword: EBR3.CSDECODE_B 111\nenum: EBR3.MODE DP16KD\nenum: EBR3.DP16KD.DATA_WIDTH_A 9\nenum: EBR3.DP16KD.DATA_WIDTH_B 9\nenum: EBR3.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR3.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR3.REGMODE_A NOREG\nenum: EBR3.REGMODE_B NOREG\nenum: EBR3.RESETMODE SYNC\nenum: EBR3.ASYNC_RESET_RELEASE SYNC\nenum: EBR3.GSR DISABLED\nenum: EBR3.CLKAMUX CLKA\nenum: EBR3.CLKBMUX CLKB\nenum: EBR3.RSTAMUX INV\nenum: EBR3.RSTBMUX INV\nenum: EBR3.WEAMUX WEA\nenum: EBR3.WEBMUX INV\nenum: EBR3.CEAMUX CEA\nenum: EBR3.CEBMUX CEB\nenum: EBR3.OCEAMUX OCEA\nenum: EBR3.OCEBMUX OCEB\n\n.tile_group MIB_R25C55:MIB_EBR4 MIB_R25C56:MIB_EBR5 MIB_R25C57:MIB_EBR6\nword: EBR2.WID 000010000\nword: EBR2.CSDECODE_A 111\nword: EBR2.CSDECODE_B 111\nenum: EBR2.MODE DP16KD\nenum: EBR2.DP16KD.DATA_WIDTH_A 9\nenum: EBR2.DP16KD.DATA_WIDTH_B 9\nenum: EBR2.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR2.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR2.REGMODE_A NOREG\nenum: EBR2.REGMODE_B NOREG\nenum: EBR2.RESETMODE SYNC\nenum: EBR2.ASYNC_RESET_RELEASE SYNC\nenum: EBR2.GSR DISABLED\nenum: EBR2.CLKAMUX CLKA\nenum: EBR2.CLKBMUX CLKB\nenum: EBR2.RSTAMUX INV\nenum: EBR2.RSTBMUX INV\nenum: EBR2.WEAMUX WEA\nenum: EBR2.WEBMUX INV\nenum: EBR2.CEAMUX CEA\nenum: EBR2.CEBMUX CEB\nenum: EBR2.OCEAMUX OCEA\nenum: EBR2.OCEBMUX OCEB\n\n.tile_group MIB_R37C55:MIB_EBR4 MIB_R37C56:MIB_EBR5 MIB_R37C57:MIB_EBR6\nword: EBR2.WID 110010000\nword: EBR2.CSDECODE_A 111\nword: EBR2.CSDECODE_B 111\nenum: EBR2.MODE DP16KD\nenum: EBR2.DP16KD.DATA_WIDTH_A 9\nenum: EBR2.DP16KD.DATA_WIDTH_B 9\nenum: EBR2.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR2.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR2.REGMODE_A NOREG\nenum: EBR2.REGMODE_B NOREG\nenum: EBR2.RESETMODE SYNC\nenum: EBR2.ASYNC_RESET_RELEASE SYNC\nenum: EBR2.GSR DISABLED\nenum: EBR2.CLKAMUX CLKA\nenum: EBR2.CLKBMUX CLKB\nenum: EBR2.RSTAMUX INV\nenum: EBR2.RSTBMUX INV\nenum: EBR2.WEAMUX WEA\nenum: EBR2.WEBMUX INV\nenum: EBR2.CEAMUX CEA\nenum: EBR2.CEBMUX CEB\nenum: EBR2.OCEAMUX OCEA\nenum: EBR2.OCEBMUX OCEB\n\n.tile_group MIB_R37C48:MIB_EBR6 MIB_R37C49:MIB_EBR7 MIB_R37C50:MIB_EBR8\nword: EBR3.WID 101010000\nword: EBR3.CSDECODE_A 111\nword: EBR3.CSDECODE_B 111\nenum: EBR3.MODE DP16KD\nenum: EBR3.DP16KD.DATA_WIDTH_A 9\nenum: EBR3.DP16KD.DATA_WIDTH_B 9\nenum: EBR3.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR3.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR3.REGMODE_A NOREG\nenum: EBR3.REGMODE_B NOREG\nenum: EBR3.RESETMODE SYNC\nenum: EBR3.ASYNC_RESET_RELEASE SYNC\nenum: EBR3.GSR DISABLED\nenum: EBR3.CLKAMUX CLKA\nenum: EBR3.CLKBMUX CLKB\nenum: EBR3.RSTAMUX INV\nenum: EBR3.RSTBMUX INV\nenum: EBR3.WEAMUX WEA\nenum: EBR3.WEBMUX INV\nenum: EBR3.CEAMUX CEA\nenum: EBR3.CEBMUX CEB\nenum: EBR3.OCEAMUX OCEA\nenum: EBR3.OCEBMUX OCEB\n\n.tile_group MIB_R25C44:MIB_EBR2 MIB_R25C45:MIB_EBR3 MIB_R25C46:MIB_EBR4\nword: EBR1.WID 111010000\nword: EBR1.CSDECODE_A 111\nword: EBR1.CSDECODE_B 111\nenum: EBR1.MODE DP16KD\nenum: EBR1.DP16KD.DATA_WIDTH_A 9\nenum: EBR1.DP16KD.DATA_WIDTH_B 9\nenum: EBR1.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR1.REGMODE_A NOREG\nenum: EBR1.REGMODE_B NOREG\nenum: EBR1.RESETMODE SYNC\nenum: EBR1.ASYNC_RESET_RELEASE SYNC\nenum: EBR1.GSR DISABLED\nenum: EBR1.CLKAMUX CLKA\nenum: EBR1.CLKBMUX CLKB\nenum: EBR1.RSTAMUX INV\nenum: EBR1.RSTBMUX INV\nenum: EBR1.WEAMUX WEA\nenum: EBR1.WEBMUX INV\nenum: EBR1.CEAMUX CEA\nenum: EBR1.CEBMUX CEB\nenum: EBR1.OCEAMUX OCEA\nenum: EBR1.OCEBMUX OCEB\n\n.tile_group MIB_R25C57:MIB_EBR6 MIB_R25C58:MIB_EBR7 MIB_R25C59:MIB_EBR8\nword: EBR3.WID 000110000\nword: EBR3.CSDECODE_A 111\nword: EBR3.CSDECODE_B 111\nenum: EBR3.MODE DP16KD\nenum: EBR3.DP16KD.DATA_WIDTH_A 9\nenum: EBR3.DP16KD.DATA_WIDTH_B 9\nenum: EBR3.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR3.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR3.REGMODE_A NOREG\nenum: EBR3.REGMODE_B NOREG\nenum: EBR3.RESETMODE SYNC\nenum: EBR3.ASYNC_RESET_RELEASE SYNC\nenum: EBR3.GSR DISABLED\nenum: EBR3.CLKAMUX CLKA\nenum: EBR3.CLKBMUX CLKB\nenum: EBR3.RSTAMUX INV\nenum: EBR3.RSTBMUX INV\nenum: EBR3.WEAMUX WEA\nenum: EBR3.WEBMUX INV\nenum: EBR3.CEAMUX CEA\nenum: EBR3.CEBMUX CEB\nenum: EBR3.OCEAMUX OCEA\nenum: EBR3.OCEBMUX OCEB\n\n.tile_group MIB_R37C53:MIB_EBR2 MIB_R37C54:MIB_EBR3 MIB_R37C55:MIB_EBR4\nword: EBR1.WID 100110000\nword: EBR1.CSDECODE_A 111\nword: EBR1.CSDECODE_B 111\nenum: EBR1.MODE DP16KD\nenum: EBR1.DP16KD.DATA_WIDTH_A 9\nenum: EBR1.DP16KD.DATA_WIDTH_B 9\nenum: EBR1.DP16KD.WRITEMODE_A WRITETHROUGH\nenum: EBR1.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR1.REGMODE_A NOREG\nenum: EBR1.REGMODE_B NOREG\nenum: EBR1.RESETMODE SYNC\nenum: EBR1.ASYNC_RESET_RELEASE SYNC\nenum: EBR1.GSR DISABLED\nenum: EBR1.CLKAMUX CLKA\nenum: EBR1.CLKBMUX CLKB\nenum: EBR1.RSTAMUX INV\nenum: EBR1.RSTBMUX INV\nenum: EBR1.WEAMUX WEA\nenum: EBR1.WEBMUX INV\nenum: EBR1.CEAMUX CEA\nenum: EBR1.CEBMUX CEB\nenum: EBR1.OCEAMUX OCEA\nenum: EBR1.OCEBMUX OCEB\n\n.tile_group MIB_R25C28:MIB_EBR6 MIB_R25C29:MIB_EBR7 MIB_R25C30:MIB_EBR8\nword: EBR3.WID 110000000\nword: EBR3.CSDECODE_A 111\nword: EBR3.CSDECODE_B 111\nenum: EBR3.MODE DP16KD\nenum: EBR3.DP16KD.DATA_WIDTH_A 18\nenum: EBR3.DP16KD.DATA_WIDTH_B 18\nenum: EBR3.DP16KD.WRITEMODE_A READBEFOREWRITE\nenum: EBR3.DP16KD.WRITEMODE_B READBEFOREWRITE\nenum: EBR3.REGMODE_A NOREG\nenum: EBR3.REGMODE_B NOREG\nenum: EBR3.RESETMODE SYNC\nenum: EBR3.ASYNC_RESET_RELEASE SYNC\nenum: EBR3.GSR DISABLED\nenum: EBR3.CLKAMUX CLKA\nenum: EBR3.CLKBMUX CLKB\nenum: EBR3.RSTAMUX INV\nenum: EBR3.RSTBMUX INV\nenum: EBR3.WEAMUX WEA\nenum: EBR3.WEBMUX INV\nenum: EBR3.CEAMUX CEA\nenum: EBR3.CEBMUX CEB\nenum: EBR3.OCEAMUX OCEA\nenum: EBR3.OCEBMUX OCEB\n\n"
  },
  {
    "path": "src/litex_linux/top.rpt",
    "content": "\n /----------------------------------------------------------------------------\\\n |                                                                            |\n |  yosys -- Yosys Open SYnthesis Suite                                       |\n |                                                                            |\n |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |\n |                                                                            |\n |  Permission to use, copy, modify, and/or distribute this software for any  |\n |  purpose with or without fee is hereby granted, provided that the above    |\n |  copyright notice and this permission notice appear in all copies.         |\n |                                                                            |\n |  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |\n |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |\n |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |\n |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |\n |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |\n |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |\n |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |\n |                                                                            |\n \\----------------------------------------------------------------------------/\n\n Yosys 0.9+3672 (git sha1 924f1713, gcc 8.3.0-6+rpi1 -fPIC -Os)\n\n\n-- Executing script file `top.ys' --\n\n1. Executing Verilog-2005 frontend: /home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v\nParsing Verilog input from `/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v' to AST representation.\nStoring AST representation for module `$abstract\\InstructionCache'.\nStoring AST representation for module `$abstract\\DataCache'.\nStoring AST representation for module `$abstract\\VexRiscv'.\nSuccessfully finished Verilog frontend.\n\n2. Executing Verilog-2005 frontend: /home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v\nParsing Verilog input from `/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v' to AST representation.\nStoring AST representation for module `$abstract\\top'.\nSuccessfully finished Verilog frontend.\n\n3. Executing ATTRMAP pass (move or copy attributes).\n\n4. Executing SYNTH_ECP5 pass.\n\n4.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_sim.v\nParsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_sim.v' to AST representation.\nGenerating RTLIL representation for module `\\LUT4'.\nGenerating RTLIL representation for module `\\$__ABC9_LUT5'.\nGenerating RTLIL representation for module `\\$__ABC9_LUT6'.\nGenerating RTLIL representation for module `\\$__ABC9_LUT7'.\nGenerating RTLIL representation for module `\\L6MUX21'.\nGenerating RTLIL representation for module `\\CCU2C'.\nGenerating RTLIL representation for module `\\TRELLIS_RAM16X2'.\nGenerating RTLIL representation for module `\\PFUMX'.\nGenerating RTLIL representation for module `\\TRELLIS_DPR16X4'.\nGenerating RTLIL representation for module `\\DPR16X4C'.\nGenerating RTLIL representation for module `\\LUT2'.\nGenerating RTLIL representation for module `\\TRELLIS_FF'.\nGenerating RTLIL representation for module `\\TRELLIS_IO'.\nGenerating RTLIL representation for module `\\INV'.\nGenerating RTLIL representation for module `\\TRELLIS_SLICE'.\nGenerating RTLIL representation for module `\\DP16KD'.\nGenerating RTLIL representation for module `\\FD1P3AX'.\nGenerating RTLIL representation for module `\\FD1P3AY'.\nGenerating RTLIL representation for module `\\FD1P3BX'.\nGenerating RTLIL representation for module `\\FD1P3DX'.\nGenerating RTLIL representation for module `\\FD1P3IX'.\nGenerating RTLIL representation for module `\\FD1P3JX'.\nGenerating RTLIL representation for module `\\FD1S3AX'.\nGenerating RTLIL representation for module `\\FD1S3AY'.\nGenerating RTLIL representation for module `\\FD1S3BX'.\nGenerating RTLIL representation for module `\\FD1S3DX'.\nGenerating RTLIL representation for module `\\FD1S3IX'.\nGenerating RTLIL representation for module `\\FD1S3JX'.\nGenerating RTLIL representation for module `\\IFS1P3BX'.\nGenerating RTLIL representation for module `\\IFS1P3DX'.\nGenerating RTLIL representation for module `\\IFS1P3IX'.\nGenerating RTLIL representation for module `\\IFS1P3JX'.\nGenerating RTLIL representation for module `\\OFS1P3BX'.\nGenerating RTLIL representation for module `\\OFS1P3DX'.\nGenerating RTLIL representation for module `\\OFS1P3IX'.\nGenerating RTLIL representation for module `\\OFS1P3JX'.\nGenerating RTLIL representation for module `\\IB'.\nGenerating RTLIL representation for module `\\IBPU'.\nGenerating RTLIL representation for module `\\IBPD'.\nGenerating RTLIL representation for module `\\OB'.\nGenerating RTLIL representation for module `\\OBZ'.\nGenerating RTLIL representation for module `\\OBZPU'.\nGenerating RTLIL representation for module `\\OBZPD'.\nGenerating RTLIL representation for module `\\OBCO'.\nGenerating RTLIL representation for module `\\BB'.\nGenerating RTLIL representation for module `\\BBPU'.\nGenerating RTLIL representation for module `\\BBPD'.\nGenerating RTLIL representation for module `\\ILVDS'.\nGenerating RTLIL representation for module `\\OLVDS'.\nSuccessfully finished Verilog frontend.\n\n4.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_bb.v\nParsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_bb.v' to AST representation.\nGenerating RTLIL representation for module `\\MULT18X18D'.\nGenerating RTLIL representation for module `\\ALU54B'.\nGenerating RTLIL representation for module `\\EHXPLLL'.\nGenerating RTLIL representation for module `\\DTR'.\nGenerating RTLIL representation for module `\\OSCG'.\nGenerating RTLIL representation for module `\\USRMCLK'.\nGenerating RTLIL representation for module `\\JTAGG'.\nGenerating RTLIL representation for module `\\DELAYF'.\nGenerating RTLIL representation for module `\\DELAYG'.\nGenerating RTLIL representation for module `\\IDDRX1F'.\nGenerating RTLIL representation for module `\\IDDRX2F'.\nGenerating RTLIL representation for module `\\IDDR71B'.\nGenerating RTLIL representation for module `\\IDDRX2DQA'.\nGenerating RTLIL representation for module `\\ODDRX1F'.\nGenerating RTLIL representation for module `\\ODDRX2F'.\nGenerating RTLIL representation for module `\\ODDR71B'.\nGenerating RTLIL representation for module `\\OSHX2A'.\nGenerating RTLIL representation for module `\\ODDRX2DQA'.\nGenerating RTLIL representation for module `\\ODDRX2DQSB'.\nGenerating RTLIL representation for module `\\TSHX2DQA'.\nGenerating RTLIL representation for module `\\TSHX2DQSA'.\nGenerating RTLIL representation for module `\\DQSBUFM'.\nGenerating RTLIL representation for module `\\DDRDLLA'.\nGenerating RTLIL representation for module `\\CLKDIVF'.\nGenerating RTLIL representation for module `\\ECLKSYNCB'.\nGenerating RTLIL representation for module `\\ECLKBRIDGECS'.\nGenerating RTLIL representation for module `\\DCCA'.\nGenerating RTLIL representation for module `\\DCUA'.\nGenerating RTLIL representation for module `\\EXTREFB'.\nGenerating RTLIL representation for module `\\PCSCLKDIV'.\nGenerating RTLIL representation for module `\\PUR'.\nGenerating RTLIL representation for module `\\GSR'.\nGenerating RTLIL representation for module `\\SGSR'.\nGenerating RTLIL representation for module `\\PDPW16KD'.\nSuccessfully finished Verilog frontend.\n\n4.3. Executing HIERARCHY pass (managing design hierarchy).\n\n4.4. Executing AST frontend in derive mode using pre-parsed AST for module `\\top'.\nGenerating RTLIL representation for module `\\top'.\n\n4.4.1. Analyzing design hierarchy..\nTop module:  \\top\n\n4.4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\\VexRiscv'.\nGenerating RTLIL representation for module `\\VexRiscv'.\n\n4.4.3. Analyzing design hierarchy..\nTop module:  \\top\nUsed module:     \\VexRiscv\n\n4.4.4. Executing AST frontend in derive mode using pre-parsed AST for module `\\DataCache'.\nGenerating RTLIL representation for module `\\DataCache'.\n/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:0: Warning: System task `$display' outside initial block is unsupported.\n\n4.4.5. Executing AST frontend in derive mode using pre-parsed AST for module `\\InstructionCache'.\nGenerating RTLIL representation for module `\\InstructionCache'.\n\n4.4.6. Analyzing design hierarchy..\nTop module:  \\top\nUsed module:     \\VexRiscv\nUsed module:         \\DataCache\nUsed module:         \\InstructionCache\n\n4.4.7. Analyzing design hierarchy..\nTop module:  \\top\nUsed module:     \\VexRiscv\nUsed module:         \\DataCache\nUsed module:         \\InstructionCache\nRemoving unused module `$abstract\\top'.\nRemoving unused module `$abstract\\VexRiscv'.\nRemoving unused module `$abstract\\DataCache'.\nRemoving unused module `$abstract\\InstructionCache'.\nRemoved 4 unused modules.\n\n4.5. Executing PROC pass (convert processes to netlists).\n\n4.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nFound and cleaned up 1 empty switch in `\\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$146'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$2494'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$2493'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$2492'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5884$1844'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5870$1837'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5856$1830'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5842$1823'.\nFound and cleaned up 15 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3962$1500'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3954$1499'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3938$1484'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3930$1483'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3914$1468'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3906$1467'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3890$1452'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3882$1451'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450'.\nFound and cleaned up 2 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nFound and cleaned up 6 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331'.\nCleaned up 38 empty switches.\n\n4.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nMarked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$226 in module TRELLIS_FF.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:271$3882 in module InstructionCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:226$3860 in module InstructionCache.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:210$3855 in module InstructionCache.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:201$3853 in module InstructionCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:193$3852 in module InstructionCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:186$3851 in module InstructionCache.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1125$3815 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1052$3797 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1042$3794 in module DataCache.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1030$3792 in module DataCache.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1017$3789 in module DataCache.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1002$3788 in module DataCache.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:987$3787 in module DataCache.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:972$3786 in module DataCache.\nMarked 11 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:936$3783 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:924$3762 in module DataCache.\nMarked 6 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:905$3759 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:885$3754 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:873$3747 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:866$3746 in module DataCache.\nMarked 11 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:832$3742 in module DataCache.\nMarked 5 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:816$3739 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:806$3736 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:782$3717 in module DataCache.\nMarked 4 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:768$3715 in module DataCache.\nMarked 4 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:754$3713 in module DataCache.\nMarked 4 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:740$3711 in module DataCache.\nMarked 4 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:726$3709 in module DataCache.\nMarked 9 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:699$3706 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:692$3705 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:685$3703 in module DataCache.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:675$3702 in module DataCache.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:665$3701 in module DataCache.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:655$3700 in module DataCache.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:642$3699 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:635$3698 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:628$3697 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:621$3696 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:614$3695 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:599$3689 in module DataCache.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:592$3687 in module DataCache.\nMarked 6 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6677$3408 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6670$3407 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6591$3338 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6582$3335 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6573$3334 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6547$3325 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6533$3324 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6519$3319 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6505$3318 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6381$3305 in module VexRiscv.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6360$3304 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6350$3303 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6341$3299 in module VexRiscv.\nMarked 15 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6219$3294 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6211$3292 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6194$3282 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6180$3281 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6173$3280 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6166$3279 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6155$3272 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6140$3270 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6130$3269 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6120$3268 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6110$3267 in module VexRiscv.\nMarked 13 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6039$3240 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6023$3232 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5963$3222 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5928$3220 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5912$3215 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5832$3211 in module VexRiscv.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5820$3204 in module VexRiscv.\nMarked 10 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5782$3194 in module VexRiscv.\nMarked 10 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5754$3192 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5670$3184 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5652$3183 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5586$3180 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5570$3177 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5556$3173 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5547$3171 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5474$3133 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5454$3132 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5432$3119 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5424$3108 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5416$3107 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5408$3106 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5400$3103 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5392$3101 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5382$3093 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5375$3091 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5363$3088 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5335$3058 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5327$3047 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5319$3046 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5311$3045 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5303$3042 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5295$3040 in module VexRiscv.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5283$3029 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5276$3027 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5264$3024 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5231$2993 in module VexRiscv.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5220$2991 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5206$2990 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5139$2983 in module VexRiscv.\nMarked 4 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5124$2981 in module VexRiscv.\nMarked 5 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5105$2980 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5095$2979 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5086$2976 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5078$2973 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5071$2972 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5061$2970 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5049$2969 in module VexRiscv.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5037$2968 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5027$2966 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5018$2965 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5004$2964 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4995$2963 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4986$2962 in module VexRiscv.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4975$2960 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4928$2947 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4918$2946 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4908$2943 in module VexRiscv.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4895$2942 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4827$2924 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4782$2917 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4743$2910 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4723$2899 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4712$2895 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4701$2891 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4686$2887 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4679$2886 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4672$2885 in module VexRiscv.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4642$2879 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4632$2878 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4625$2876 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4615$2873 in module VexRiscv.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4602$2871 in module VexRiscv.\nMarked 4 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4582$2870 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4575$2869 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4565$2868 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4557$2867 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4547$2866 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4536$2865 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4526$2864 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4519$2863 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4508$2862 in module VexRiscv.\nMarked 6 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4487$2856 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4477$2855 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4466$2854 in module VexRiscv.\nMarked 4 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4450$2843 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4443$2840 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4430$2839 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4423$2838 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4414$2837 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4407$2836 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4400$2835 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4393$2834 in module VexRiscv.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4360$2831 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4348$2829 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4340$2828 in module VexRiscv.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4303$2827 in module VexRiscv.\nMarked 11 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4272$2825 in module VexRiscv.\nMarked 11 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4242$2823 in module VexRiscv.\nMarked 2 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4226$2822 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820 in module VexRiscv.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3313$2819 in module VexRiscv.\nMarked 75 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4177$1559 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4160$1552 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4143$1545 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4126$1538 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4109$1531 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4092$1524 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4058$1522 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4047$1521 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4036$1520 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4025$1519 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4014$1518 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4003$1517 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3992$1516 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3857$1449 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3840$1448 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3823$1447 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3806$1446 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3789$1445 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3772$1444 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3755$1443 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3721$1441 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3704$1440 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3687$1439 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3670$1438 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3653$1437 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3636$1436 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3619$1435 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3602$1434 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3568$1432 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3013$838 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821 in module top.\nMarked 3 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634 in module top.\nMarked 5 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2388$438 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425 in module top.\nMarked 5 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2237$408 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395 in module top.\nMarked 5 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2086$378 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365 in module top.\nMarked 5 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1935$348 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1798$318 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1676$305 in module top.\nMarked 1 switch rules as full_case in process $proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1646$294 in module top.\nRemoved a total of 0 dead cases.\n\n4.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 114 redundant assignments.\nPromoted 1154 assignments to connections.\n\n4.5.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$230'.\n  Set init value: \\Q = 1'0\nFound init rule in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2485$3615'.\n  Set init value: \\CsrPlugin_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000\nFound init rule in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2484$3614'.\n  Set init value: \\CsrPlugin_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1534$2487'.\n  Set init value: \\builder_inferedsdrtristate11_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1530$2486'.\n  Set init value: \\builder_inferedsdrtristate10_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1526$2485'.\n  Set init value: \\builder_inferedsdrtristate9_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1522$2484'.\n  Set init value: \\builder_inferedsdrtristate8_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1518$2483'.\n  Set init value: \\builder_inferedsdrtristate7_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1514$2482'.\n  Set init value: \\builder_inferedsdrtristate6_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1510$2481'.\n  Set init value: \\builder_inferedsdrtristate5_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1506$2480'.\n  Set init value: \\builder_inferedsdrtristate4_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1502$2479'.\n  Set init value: \\builder_inferedsdrtristate3_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1498$2478'.\n  Set init value: \\builder_inferedsdrtristate2_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1494$2477'.\n  Set init value: \\builder_inferedsdrtristate1_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1490$2476'.\n  Set init value: \\builder_inferedsdrtristate0_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1485$2475'.\n  Set init value: \\builder_regs1 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1484$2474'.\n  Set init value: \\builder_regs0 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1483$2473'.\n  Set init value: \\builder_sync_f_array_muxed = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1482$2472'.\n  Set init value: \\builder_sync_rhs_array_muxed6 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1481$2471'.\n  Set init value: \\builder_sync_rhs_array_muxed5 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1480$2470'.\n  Set init value: \\builder_sync_rhs_array_muxed4 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1479$2469'.\n  Set init value: \\builder_sync_rhs_array_muxed3 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1478$2468'.\n  Set init value: \\builder_sync_rhs_array_muxed2 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1477$2467'.\n  Set init value: \\builder_sync_rhs_array_muxed1 = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1476$2466'.\n  Set init value: \\builder_sync_rhs_array_muxed0 = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1475$2465'.\n  Set init value: \\builder_comb_rhs_array_muxed31 = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1474$2464'.\n  Set init value: \\builder_comb_rhs_array_muxed30 = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1473$2463'.\n  Set init value: \\builder_comb_rhs_array_muxed29 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1472$2462'.\n  Set init value: \\builder_comb_rhs_array_muxed28 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1471$2461'.\n  Set init value: \\builder_comb_rhs_array_muxed27 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1470$2460'.\n  Set init value: \\builder_comb_rhs_array_muxed26 = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1469$2459'.\n  Set init value: \\builder_comb_rhs_array_muxed25 = 0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1468$2458'.\n  Set init value: \\builder_comb_rhs_array_muxed24 = 30'000000000000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1467$2457'.\n  Set init value: \\builder_comb_rhs_array_muxed23 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1466$2456'.\n  Set init value: \\builder_comb_rhs_array_muxed22 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1465$2455'.\n  Set init value: \\builder_comb_rhs_array_muxed21 = 22'0000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1464$2454'.\n  Set init value: \\builder_comb_rhs_array_muxed20 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1463$2453'.\n  Set init value: \\builder_comb_rhs_array_muxed19 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1462$2452'.\n  Set init value: \\builder_comb_rhs_array_muxed18 = 22'0000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1461$2451'.\n  Set init value: \\builder_comb_rhs_array_muxed17 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1460$2450'.\n  Set init value: \\builder_comb_rhs_array_muxed16 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1459$2449'.\n  Set init value: \\builder_comb_rhs_array_muxed15 = 22'0000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1458$2448'.\n  Set init value: \\builder_comb_rhs_array_muxed14 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1457$2447'.\n  Set init value: \\builder_comb_rhs_array_muxed13 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1456$2446'.\n  Set init value: \\builder_comb_rhs_array_muxed12 = 22'0000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1455$2445'.\n  Set init value: \\builder_comb_t_array_muxed5 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1454$2444'.\n  Set init value: \\builder_comb_t_array_muxed4 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1453$2443'.\n  Set init value: \\builder_comb_t_array_muxed3 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1452$2442'.\n  Set init value: \\builder_comb_rhs_array_muxed11 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1451$2441'.\n  Set init value: \\builder_comb_rhs_array_muxed10 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1450$2440'.\n  Set init value: \\builder_comb_rhs_array_muxed9 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1449$2439'.\n  Set init value: \\builder_comb_rhs_array_muxed8 = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1448$2438'.\n  Set init value: \\builder_comb_rhs_array_muxed7 = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1447$2437'.\n  Set init value: \\builder_comb_rhs_array_muxed6 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1446$2436'.\n  Set init value: \\builder_comb_t_array_muxed2 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1445$2435'.\n  Set init value: \\builder_comb_t_array_muxed1 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1444$2434'.\n  Set init value: \\builder_comb_t_array_muxed0 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1443$2433'.\n  Set init value: \\builder_comb_rhs_array_muxed5 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1442$2432'.\n  Set init value: \\builder_comb_rhs_array_muxed4 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1441$2431'.\n  Set init value: \\builder_comb_rhs_array_muxed3 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1440$2430'.\n  Set init value: \\builder_comb_rhs_array_muxed2 = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1439$2429'.\n  Set init value: \\builder_comb_rhs_array_muxed1 = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1438$2428'.\n  Set init value: \\builder_comb_rhs_array_muxed0 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1437$2427'.\n  Set init value: \\builder_soclinux_we_next_value_ce2 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1436$2426'.\n  Set init value: \\builder_soclinux_we_next_value2 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1435$2425'.\n  Set init value: \\builder_soclinux_adr_next_value_ce1 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1434$2424'.\n  Set init value: \\builder_soclinux_adr_next_value1 = 14'00000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1433$2423'.\n  Set init value: \\builder_soclinux_dat_w_next_value_ce0 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1432$2422'.\n  Set init value: \\builder_soclinux_dat_w_next_value0 = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1431$2421'.\n  Set init value: \\builder_next_state = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1430$2420'.\n  Set init value: \\builder_state = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1408$2419'.\n  Set init value: \\builder_csr_bankarray_interface7_bank_bus_dat_r = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1383$2418'.\n  Set init value: \\builder_csr_bankarray_interface6_bank_bus_dat_r = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1318$2417'.\n  Set init value: \\builder_csr_bankarray_interface5_bank_bus_dat_r = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1277$2416'.\n  Set init value: \\builder_csr_bankarray_interface4_bank_bus_dat_r = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1236$2415'.\n  Set init value: \\builder_csr_bankarray_interface3_bank_bus_dat_r = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1227$2414'.\n  Set init value: \\builder_csr_bankarray_interface2_bank_bus_dat_r = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1223$2413'.\n  Set init value: \\builder_csr_bankarray_sel_r = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1219$2412'.\n  Set init value: \\builder_csr_bankarray_sram_bus_dat_r = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1178$2411'.\n  Set init value: \\builder_csr_bankarray_interface1_bank_bus_dat_r = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1109$2410'.\n  Set init value: \\builder_csr_bankarray_interface0_bank_bus_dat_r = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1105$2409'.\n  Set init value: \\builder_count = 20'11110100001001000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1102$2408'.\n  Set init value: \\builder_error = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1101$2407'.\n  Set init value: \\builder_slave_sel_r = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1100$2406'.\n  Set init value: \\builder_slave_sel = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1099$2405'.\n  Set init value: \\builder_grant = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1093$2404'.\n  Set init value: \\builder_shared_ack = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1089$2403'.\n  Set init value: \\builder_shared_dat_r = 0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1082$2401'.\n  Set init value: \\builder_soclinux_wishbone_ack = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1078$2400'.\n  Set init value: \\builder_soclinux_wishbone_dat_r = 0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1074$2399'.\n  Set init value: \\builder_soclinux_dat_w = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1073$2398'.\n  Set init value: \\builder_soclinux_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1072$2397'.\n  Set init value: \\builder_soclinux_adr = 14'00000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1071$2396'.\n  Set init value: \\soclinux_count_spimaster_next_value_ce = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1070$2395'.\n  Set init value: \\soclinux_count_spimaster_next_value = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1069$2394'.\n  Set init value: \\builder_spimaster_next_state = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1068$2393'.\n  Set init value: \\builder_spimaster_state = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1067$2392'.\n  Set init value: \\main_wishbone_bridge_count_litedramwishbone2native_next_value_ce = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1066$2391'.\n  Set init value: \\main_wishbone_bridge_count_litedramwishbone2native_next_value = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1065$2390'.\n  Set init value: \\builder_litedramwishbone2native_next_state = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1064$2389'.\n  Set init value: \\builder_litedramwishbone2native_state = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1063$2388'.\n  Set init value: \\builder_fullmemorywe_next_state = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1062$2387'.\n  Set init value: \\builder_fullmemorywe_state = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1061$2386'.\n  Set init value: \\builder_new_master_rdata_valid3 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1060$2385'.\n  Set init value: \\builder_new_master_rdata_valid2 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1059$2384'.\n  Set init value: \\builder_new_master_rdata_valid1 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1058$2383'.\n  Set init value: \\builder_new_master_rdata_valid0 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1057$2382'.\n  Set init value: \\builder_new_master_wdata_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1040$2377'.\n  Set init value: \\builder_multiplexer_next_state = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1039$2376'.\n  Set init value: \\builder_multiplexer_state = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1038$2375'.\n  Set init value: \\builder_bankmachine3_next_state = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1037$2374'.\n  Set init value: \\builder_bankmachine3_state = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1036$2373'.\n  Set init value: \\builder_bankmachine2_next_state = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1035$2372'.\n  Set init value: \\builder_bankmachine2_state = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1034$2371'.\n  Set init value: \\builder_bankmachine1_next_state = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1033$2370'.\n  Set init value: \\builder_bankmachine1_state = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1032$2369'.\n  Set init value: \\builder_bankmachine0_next_state = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1031$2368'.\n  Set init value: \\builder_bankmachine0_state = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1030$2367'.\n  Set init value: \\builder_refresher_next_state = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1029$2366'.\n  Set init value: \\builder_refresher_state = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1028$2365'.\n  Set init value: \\soclinux_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1027$2364'.\n  Set init value: \\soclinux_storage = 16'0000000001111101\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1026$2363'.\n  Set init value: \\soclinux_miso_data = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1025$2362'.\n  Set init value: \\soclinux_mosi_sel = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1024$2361'.\n  Set init value: \\soclinux_mosi_data = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1021$2360'.\n  Set init value: \\soclinux_clk_divider1 = 16'0000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1020$2359'.\n  Set init value: \\soclinux_miso_latch = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1019$2358'.\n  Set init value: \\soclinux_mosi_latch = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1018$2357'.\n  Set init value: \\soclinux_count = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1017$2356'.\n  Set init value: \\soclinux_cs_enable = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1016$2355'.\n  Set init value: \\soclinux_clk_enable = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1015$2354'.\n  Set init value: \\soclinux_loopback_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1014$2353'.\n  Set init value: \\soclinux_loopback_storage = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1013$2352'.\n  Set init value: \\soclinux_cs_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1012$2351'.\n  Set init value: \\soclinux_cs_storage = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1007$2350'.\n  Set init value: \\soclinux_mosi_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1006$2349'.\n  Set init value: \\soclinux_mosi_storage = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1001$2348'.\n  Set init value: \\soclinux_control_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1000$2347'.\n  Set init value: \\soclinux_control_storage = 16'0000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:998$2346'.\n  Set init value: \\soclinux_start1 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:994$2345'.\n  Set init value: \\soclinux_miso = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:992$2344'.\n  Set init value: \\soclinux_irq = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:991$2343'.\n  Set init value: \\soclinux_done0 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:988$2342'.\n  Set init value: \\main_count = 22'1011111010111100001000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:985$2341'.\n  Set init value: \\main_mode = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:984$2340'.\n  Set init value: \\main_chaser = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:983$2339'.\n  Set init value: \\main_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:982$2338'.\n  Set init value: \\main_storage = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:978$2337'.\n  Set init value: \\main_wishbone_bridge_wdata_consumed = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:977$2336'.\n  Set init value: \\main_wishbone_bridge_cmd_consumed = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:971$2335'.\n  Set init value: \\main_wishbone_bridge_rdata_converter_converter_strobe_all = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:969$2334'.\n  Set init value: \\main_wishbone_bridge_rdata_converter_converter_demux = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:968$2333'.\n  Set init value: \\main_wishbone_bridge_rdata_converter_converter_source_payload_valid_token_count = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:967$2332'.\n  Set init value: \\main_wishbone_bridge_rdata_converter_converter_source_payload_data = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:966$2331'.\n  Set init value: \\main_wishbone_bridge_rdata_converter_converter_source_last = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:965$2330'.\n  Set init value: \\main_wishbone_bridge_rdata_converter_converter_source_first = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:957$2329'.\n  Set init value: \\main_wishbone_bridge_rdata_converter_source_payload_data = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:940$2328'.\n  Set init value: \\main_wishbone_bridge_wdata_converter_converter_mux = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:938$2327'.\n  Set init value: \\main_wishbone_bridge_wdata_converter_converter_source_payload_data = 18'000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:933$2326'.\n  Set init value: \\main_wishbone_bridge_wdata_converter_converter_sink_payload_data = 144'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:916$2325'.\n  Set init value: \\main_wishbone_bridge_count = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:901$2322'.\n  Set init value: \\main_wishbone_bridge_cmd_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:898$2321'.\n  Set init value: \\main_word_inc = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:897$2320'.\n  Set init value: \\main_word_clr = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:896$2319'.\n  Set init value: \\main_tag_di_dirty = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:891$2318'.\n  Set init value: \\main_tag_port_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:888$2317'.\n  Set init value: \\main_adr_offset_r = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:887$2316'.\n  Set init value: \\main_write_from_slave = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:886$2315'.\n  Set init value: \\main_data_port_dat_w = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:885$2314'.\n  Set init value: \\main_data_port_we = 16'0000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:882$2313'.\n  Set init value: \\main_interface_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:880$2312'.\n  Set init value: \\main_interface_stb = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:879$2311'.\n  Set init value: \\main_interface_cyc = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:870$2309'.\n  Set init value: \\main_wb_sdram_ack = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:866$2308'.\n  Set init value: \\main_wb_sdram_dat_r = 0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:852$2305'.\n  Set init value: \\main_port_cmd_payload_addr = 24'000000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:851$2304'.\n  Set init value: \\main_port_cmd_payload_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:849$2303'.\n  Set init value: \\main_port_cmd_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:847$2302'.\n  Set init value: \\main_sdram_time1 = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:845$2301'.\n  Set init value: \\main_sdram_en1 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:844$2300'.\n  Set init value: \\main_sdram_time0 = 5'00000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:842$2299'.\n  Set init value: \\main_sdram_en0 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:839$2298'.\n  Set init value: \\main_sdram_twtrcon_count = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:838$2297'.\n  Set init value: \\main_sdram_twtrcon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:836$2296'.\n  Set init value: \\main_sdram_tccdcon_count = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:835$2295'.\n  Set init value: \\main_sdram_tccdcon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:831$2293'.\n  Set init value: \\main_sdram_trrdcon_count = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:830$2292'.\n  Set init value: \\main_sdram_trrdcon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:826$2289'.\n  Set init value: \\main_sdram_steerer_sel = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:822$2286'.\n  Set init value: \\main_sdram_choose_req_grant = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:820$2285'.\n  Set init value: \\main_sdram_choose_req_valids = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:816$2284'.\n  Set init value: \\main_sdram_choose_req_cmd_payload_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:815$2283'.\n  Set init value: \\main_sdram_choose_req_cmd_payload_ras = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:814$2282'.\n  Set init value: \\main_sdram_choose_req_cmd_payload_cas = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:811$2281'.\n  Set init value: \\main_sdram_choose_req_cmd_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:809$2280'.\n  Set init value: \\main_sdram_choose_req_want_activates = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:807$2279'.\n  Set init value: \\main_sdram_choose_req_want_writes = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:806$2278'.\n  Set init value: \\main_sdram_choose_req_want_reads = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:804$2277'.\n  Set init value: \\main_sdram_choose_cmd_grant = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:802$2276'.\n  Set init value: \\main_sdram_choose_cmd_valids = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:798$2275'.\n  Set init value: \\main_sdram_choose_cmd_cmd_payload_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:797$2274'.\n  Set init value: \\main_sdram_choose_cmd_cmd_payload_ras = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:796$2273'.\n  Set init value: \\main_sdram_choose_cmd_cmd_payload_cas = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:785$2267'.\n  Set init value: \\main_sdram_bankmachine3_trascon_count = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:784$2266'.\n  Set init value: \\main_sdram_bankmachine3_trascon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:782$2265'.\n  Set init value: \\main_sdram_bankmachine3_trccon_count = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:781$2264'.\n  Set init value: \\main_sdram_bankmachine3_trccon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:779$2263'.\n  Set init value: \\main_sdram_bankmachine3_twtpcon_count = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:778$2262'.\n  Set init value: \\main_sdram_bankmachine3_twtpcon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:776$2261'.\n  Set init value: \\main_sdram_bankmachine3_row_col_n_addr_sel = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:775$2260'.\n  Set init value: \\main_sdram_bankmachine3_row_close = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:774$2259'.\n  Set init value: \\main_sdram_bankmachine3_row_open = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:772$2258'.\n  Set init value: \\main_sdram_bankmachine3_row_opened = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:771$2257'.\n  Set init value: \\main_sdram_bankmachine3_row = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:770$2256'.\n  Set init value: \\main_sdram_bankmachine3_cmd_buffer_source_payload_addr = 22'0000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:769$2255'.\n  Set init value: \\main_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:768$2254'.\n  Set init value: \\main_sdram_bankmachine3_cmd_buffer_source_last = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:767$2253'.\n  Set init value: \\main_sdram_bankmachine3_cmd_buffer_source_first = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:765$2252'.\n  Set init value: \\main_sdram_bankmachine3_cmd_buffer_source_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:744$2251'.\n  Set init value: \\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:743$2250'.\n  Set init value: \\main_sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:742$2249'.\n  Set init value: \\main_sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:740$2247'.\n  Set init value: \\main_sdram_bankmachine3_cmd_buffer_lookahead_level = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:721$2244'.\n  Set init value: \\main_sdram_bankmachine3_auto_precharge = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:720$2243'.\n  Set init value: \\main_sdram_bankmachine3_cmd_payload_is_write = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:719$2242'.\n  Set init value: \\main_sdram_bankmachine3_cmd_payload_is_read = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:718$2241'.\n  Set init value: \\main_sdram_bankmachine3_cmd_payload_is_cmd = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:717$2240'.\n  Set init value: \\main_sdram_bankmachine3_cmd_payload_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:716$2239'.\n  Set init value: \\main_sdram_bankmachine3_cmd_payload_ras = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:715$2238'.\n  Set init value: \\main_sdram_bankmachine3_cmd_payload_cas = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:713$2237'.\n  Set init value: \\main_sdram_bankmachine3_cmd_payload_a = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:712$2236'.\n  Set init value: \\main_sdram_bankmachine3_cmd_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:711$2235'.\n  Set init value: \\main_sdram_bankmachine3_cmd_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:710$2234'.\n  Set init value: \\main_sdram_bankmachine3_refresh_gnt = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:708$2233'.\n  Set init value: \\main_sdram_bankmachine3_req_rdata_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:707$2232'.\n  Set init value: \\main_sdram_bankmachine3_req_wdata_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:701$2231'.\n  Set init value: \\main_sdram_bankmachine2_trascon_count = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:700$2230'.\n  Set init value: \\main_sdram_bankmachine2_trascon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:698$2229'.\n  Set init value: \\main_sdram_bankmachine2_trccon_count = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:697$2228'.\n  Set init value: \\main_sdram_bankmachine2_trccon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:695$2227'.\n  Set init value: \\main_sdram_bankmachine2_twtpcon_count = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:694$2226'.\n  Set init value: \\main_sdram_bankmachine2_twtpcon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:692$2225'.\n  Set init value: \\main_sdram_bankmachine2_row_col_n_addr_sel = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:691$2224'.\n  Set init value: \\main_sdram_bankmachine2_row_close = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:690$2223'.\n  Set init value: \\main_sdram_bankmachine2_row_open = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:688$2222'.\n  Set init value: \\main_sdram_bankmachine2_row_opened = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:687$2221'.\n  Set init value: \\main_sdram_bankmachine2_row = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:686$2220'.\n  Set init value: \\main_sdram_bankmachine2_cmd_buffer_source_payload_addr = 22'0000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:685$2219'.\n  Set init value: \\main_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:684$2218'.\n  Set init value: \\main_sdram_bankmachine2_cmd_buffer_source_last = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:683$2217'.\n  Set init value: \\main_sdram_bankmachine2_cmd_buffer_source_first = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:681$2216'.\n  Set init value: \\main_sdram_bankmachine2_cmd_buffer_source_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:660$2215'.\n  Set init value: \\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:659$2214'.\n  Set init value: \\main_sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:658$2213'.\n  Set init value: \\main_sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:656$2211'.\n  Set init value: \\main_sdram_bankmachine2_cmd_buffer_lookahead_level = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:637$2208'.\n  Set init value: \\main_sdram_bankmachine2_auto_precharge = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:636$2207'.\n  Set init value: \\main_sdram_bankmachine2_cmd_payload_is_write = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:635$2206'.\n  Set init value: \\main_sdram_bankmachine2_cmd_payload_is_read = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:634$2205'.\n  Set init value: \\main_sdram_bankmachine2_cmd_payload_is_cmd = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:633$2204'.\n  Set init value: \\main_sdram_bankmachine2_cmd_payload_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:632$2203'.\n  Set init value: \\main_sdram_bankmachine2_cmd_payload_ras = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:631$2202'.\n  Set init value: \\main_sdram_bankmachine2_cmd_payload_cas = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:629$2201'.\n  Set init value: \\main_sdram_bankmachine2_cmd_payload_a = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:628$2200'.\n  Set init value: \\main_sdram_bankmachine2_cmd_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:627$2199'.\n  Set init value: \\main_sdram_bankmachine2_cmd_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:626$2198'.\n  Set init value: \\main_sdram_bankmachine2_refresh_gnt = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:624$2197'.\n  Set init value: \\main_sdram_bankmachine2_req_rdata_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:623$2196'.\n  Set init value: \\main_sdram_bankmachine2_req_wdata_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:617$2195'.\n  Set init value: \\main_sdram_bankmachine1_trascon_count = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:616$2194'.\n  Set init value: \\main_sdram_bankmachine1_trascon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:614$2193'.\n  Set init value: \\main_sdram_bankmachine1_trccon_count = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:613$2192'.\n  Set init value: \\main_sdram_bankmachine1_trccon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:611$2191'.\n  Set init value: \\main_sdram_bankmachine1_twtpcon_count = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:610$2190'.\n  Set init value: \\main_sdram_bankmachine1_twtpcon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:608$2189'.\n  Set init value: \\main_sdram_bankmachine1_row_col_n_addr_sel = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:607$2188'.\n  Set init value: \\main_sdram_bankmachine1_row_close = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:606$2187'.\n  Set init value: \\main_sdram_bankmachine1_row_open = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:604$2186'.\n  Set init value: \\main_sdram_bankmachine1_row_opened = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:603$2185'.\n  Set init value: \\main_sdram_bankmachine1_row = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:602$2184'.\n  Set init value: \\main_sdram_bankmachine1_cmd_buffer_source_payload_addr = 22'0000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:601$2183'.\n  Set init value: \\main_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:600$2182'.\n  Set init value: \\main_sdram_bankmachine1_cmd_buffer_source_last = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:599$2181'.\n  Set init value: \\main_sdram_bankmachine1_cmd_buffer_source_first = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:597$2180'.\n  Set init value: \\main_sdram_bankmachine1_cmd_buffer_source_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:576$2179'.\n  Set init value: \\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:575$2178'.\n  Set init value: \\main_sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:574$2177'.\n  Set init value: \\main_sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:572$2175'.\n  Set init value: \\main_sdram_bankmachine1_cmd_buffer_lookahead_level = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:553$2172'.\n  Set init value: \\main_sdram_bankmachine1_auto_precharge = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:552$2171'.\n  Set init value: \\main_sdram_bankmachine1_cmd_payload_is_write = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:551$2170'.\n  Set init value: \\main_sdram_bankmachine1_cmd_payload_is_read = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:550$2169'.\n  Set init value: \\main_sdram_bankmachine1_cmd_payload_is_cmd = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:549$2168'.\n  Set init value: \\main_sdram_bankmachine1_cmd_payload_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:548$2167'.\n  Set init value: \\main_sdram_bankmachine1_cmd_payload_ras = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:547$2166'.\n  Set init value: \\main_sdram_bankmachine1_cmd_payload_cas = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:545$2165'.\n  Set init value: \\main_sdram_bankmachine1_cmd_payload_a = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:544$2164'.\n  Set init value: \\main_sdram_bankmachine1_cmd_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:543$2163'.\n  Set init value: \\main_sdram_bankmachine1_cmd_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:542$2162'.\n  Set init value: \\main_sdram_bankmachine1_refresh_gnt = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:540$2161'.\n  Set init value: \\main_sdram_bankmachine1_req_rdata_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:539$2160'.\n  Set init value: \\main_sdram_bankmachine1_req_wdata_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:533$2159'.\n  Set init value: \\main_sdram_bankmachine0_trascon_count = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:532$2158'.\n  Set init value: \\main_sdram_bankmachine0_trascon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:530$2157'.\n  Set init value: \\main_sdram_bankmachine0_trccon_count = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:529$2156'.\n  Set init value: \\main_sdram_bankmachine0_trccon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:527$2155'.\n  Set init value: \\main_sdram_bankmachine0_twtpcon_count = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:526$2154'.\n  Set init value: \\main_sdram_bankmachine0_twtpcon_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:524$2153'.\n  Set init value: \\main_sdram_bankmachine0_row_col_n_addr_sel = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:523$2152'.\n  Set init value: \\main_sdram_bankmachine0_row_close = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:522$2151'.\n  Set init value: \\main_sdram_bankmachine0_row_open = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:520$2150'.\n  Set init value: \\main_sdram_bankmachine0_row_opened = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:519$2149'.\n  Set init value: \\main_sdram_bankmachine0_row = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:518$2148'.\n  Set init value: \\main_sdram_bankmachine0_cmd_buffer_source_payload_addr = 22'0000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:517$2147'.\n  Set init value: \\main_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:516$2146'.\n  Set init value: \\main_sdram_bankmachine0_cmd_buffer_source_last = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:515$2145'.\n  Set init value: \\main_sdram_bankmachine0_cmd_buffer_source_first = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:513$2144'.\n  Set init value: \\main_sdram_bankmachine0_cmd_buffer_source_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:492$2143'.\n  Set init value: \\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:491$2142'.\n  Set init value: \\main_sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:490$2141'.\n  Set init value: \\main_sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:488$2139'.\n  Set init value: \\main_sdram_bankmachine0_cmd_buffer_lookahead_level = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:469$2136'.\n  Set init value: \\main_sdram_bankmachine0_auto_precharge = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:468$2135'.\n  Set init value: \\main_sdram_bankmachine0_cmd_payload_is_write = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:467$2134'.\n  Set init value: \\main_sdram_bankmachine0_cmd_payload_is_read = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:466$2133'.\n  Set init value: \\main_sdram_bankmachine0_cmd_payload_is_cmd = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:465$2132'.\n  Set init value: \\main_sdram_bankmachine0_cmd_payload_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:464$2131'.\n  Set init value: \\main_sdram_bankmachine0_cmd_payload_ras = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:463$2130'.\n  Set init value: \\main_sdram_bankmachine0_cmd_payload_cas = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:461$2129'.\n  Set init value: \\main_sdram_bankmachine0_cmd_payload_a = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:460$2128'.\n  Set init value: \\main_sdram_bankmachine0_cmd_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:459$2127'.\n  Set init value: \\main_sdram_bankmachine0_cmd_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:458$2126'.\n  Set init value: \\main_sdram_bankmachine0_refresh_gnt = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:456$2125'.\n  Set init value: \\main_sdram_bankmachine0_req_rdata_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:455$2124'.\n  Set init value: \\main_sdram_bankmachine0_req_wdata_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:449$2123'.\n  Set init value: \\main_sdram_sequencer_count = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:448$2122'.\n  Set init value: \\main_sdram_sequencer_counter = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:447$2121'.\n  Set init value: \\main_sdram_sequencer_done1 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:444$2120'.\n  Set init value: \\main_sdram_sequencer_start0 = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:443$2119'.\n  Set init value: \\main_sdram_postponer_count = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:442$2118'.\n  Set init value: \\main_sdram_postponer_req_o = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:440$2117'.\n  Set init value: \\main_sdram_timer_count1 = 9'110000110\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:432$2114'.\n  Set init value: \\main_sdram_cmd_payload_we = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:431$2113'.\n  Set init value: \\main_sdram_cmd_payload_ras = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:430$2112'.\n  Set init value: \\main_sdram_cmd_payload_cas = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:429$2111'.\n  Set init value: \\main_sdram_cmd_payload_ba = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:428$2110'.\n  Set init value: \\main_sdram_cmd_payload_a = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:427$2109'.\n  Set init value: \\main_sdram_cmd_last = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:426$2108'.\n  Set init value: \\main_sdram_cmd_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:425$2107'.\n  Set init value: \\main_sdram_cmd_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:422$2106'.\n  Set init value: \\main_sdram_dfi_p0_rddata_en = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:420$2105'.\n  Set init value: \\main_sdram_dfi_p0_wrdata_en = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:414$2103'.\n  Set init value: \\main_sdram_dfi_p0_we_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:413$2102'.\n  Set init value: \\main_sdram_dfi_p0_ras_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:412$2101'.\n  Set init value: \\main_sdram_dfi_p0_cs_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:411$2100'.\n  Set init value: \\main_sdram_dfi_p0_cas_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:410$2099'.\n  Set init value: \\main_sdram_dfi_p0_bank = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:409$2098'.\n  Set init value: \\main_sdram_dfi_p0_address = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:407$2097'.\n  Set init value: \\main_sdram_interface_wdata_we = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:406$2096'.\n  Set init value: \\main_sdram_interface_wdata = 16'0000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:375$2095'.\n  Set init value: \\main_sdram_rddata_status = 16'0000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:374$2094'.\n  Set init value: \\main_sdram_wrdata_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:373$2093'.\n  Set init value: \\main_sdram_wrdata_storage = 16'0000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:372$2092'.\n  Set init value: \\main_sdram_baddress_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:371$2091'.\n  Set init value: \\main_sdram_baddress_storage = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:370$2090'.\n  Set init value: \\main_sdram_address_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:369$2089'.\n  Set init value: \\main_sdram_address_storage = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:364$2087'.\n  Set init value: \\main_sdram_command_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:363$2086'.\n  Set init value: \\main_sdram_command_storage = 6'000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:362$2085'.\n  Set init value: \\main_sdram_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:361$2084'.\n  Set init value: \\main_sdram_storage = 4'0001\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:354$2083'.\n  Set init value: \\main_sdram_master_p0_rddata_en = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:353$2082'.\n  Set init value: \\main_sdram_master_p0_wrdata_mask = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:352$2081'.\n  Set init value: \\main_sdram_master_p0_wrdata_en = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:351$2080'.\n  Set init value: \\main_sdram_master_p0_wrdata = 16'0000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:350$2079'.\n  Set init value: \\main_sdram_master_p0_act_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:349$2078'.\n  Set init value: \\main_sdram_master_p0_reset_n = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:348$2077'.\n  Set init value: \\main_sdram_master_p0_odt = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:347$2076'.\n  Set init value: \\main_sdram_master_p0_cke = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:346$2075'.\n  Set init value: \\main_sdram_master_p0_we_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:345$2074'.\n  Set init value: \\main_sdram_master_p0_ras_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:344$2073'.\n  Set init value: \\main_sdram_master_p0_cs_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:343$2072'.\n  Set init value: \\main_sdram_master_p0_cas_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:342$2071'.\n  Set init value: \\main_sdram_master_p0_bank = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:341$2070'.\n  Set init value: \\main_sdram_master_p0_address = 13'0000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:340$2069'.\n  Set init value: \\main_sdram_slave_p0_rddata_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:339$2068'.\n  Set init value: \\main_sdram_slave_p0_rddata = 16'0000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:324$2067'.\n  Set init value: \\main_sdram_inti_p0_rddata_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:323$2066'.\n  Set init value: \\main_sdram_inti_p0_rddata = 16'0000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:314$2064'.\n  Set init value: \\main_sdram_inti_p0_we_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:313$2063'.\n  Set init value: \\main_sdram_inti_p0_ras_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:312$2062'.\n  Set init value: \\main_sdram_inti_p0_cs_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:311$2061'.\n  Set init value: \\main_sdram_inti_p0_cas_n = 1'1\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:308$2060'.\n  Set init value: \\main_rddata_en = 3'000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:307$2059'.\n  Set init value: \\main_dfi_p0_rddata_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:282$2058'.\n  Set init value: \\main_soclinux_timer_value = 0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:281$2057'.\n  Set init value: \\main_soclinux_timer_eventmanager_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:280$2056'.\n  Set init value: \\main_soclinux_timer_eventmanager_storage = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:271$2055'.\n  Set init value: \\main_soclinux_timer_zero_old_trigger = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:270$2054'.\n  Set init value: \\main_soclinux_timer_zero_clear = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:268$2053'.\n  Set init value: \\main_soclinux_timer_zero_pending = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:263$2052'.\n  Set init value: \\main_soclinux_timer_value_status = 0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:262$2051'.\n  Set init value: \\main_soclinux_timer_update_value_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:261$2050'.\n  Set init value: \\main_soclinux_timer_update_value_storage = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:260$2049'.\n  Set init value: \\main_soclinux_timer_en_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:259$2048'.\n  Set init value: \\main_soclinux_timer_en_storage = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:258$2047'.\n  Set init value: \\main_soclinux_timer_reload_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:257$2046'.\n  Set init value: \\main_soclinux_timer_reload_storage = 0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:256$2045'.\n  Set init value: \\main_soclinux_timer_load_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:255$2044'.\n  Set init value: \\main_soclinux_timer_load_storage = 0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:239$2042'.\n  Set init value: \\main_soclinux_uart_rx_fifo_wrport_adr = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:238$2041'.\n  Set init value: \\main_soclinux_uart_rx_fifo_consume = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:237$2040'.\n  Set init value: \\main_soclinux_uart_rx_fifo_produce = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:235$2038'.\n  Set init value: \\main_soclinux_uart_rx_fifo_level0 = 5'00000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:228$2037'.\n  Set init value: \\main_soclinux_uart_rx_fifo_readable = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:202$2036'.\n  Set init value: \\main_soclinux_uart_tx_fifo_wrport_adr = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:201$2035'.\n  Set init value: \\main_soclinux_uart_tx_fifo_consume = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:200$2034'.\n  Set init value: \\main_soclinux_uart_tx_fifo_produce = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:198$2032'.\n  Set init value: \\main_soclinux_uart_tx_fifo_level0 = 5'00000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:191$2031'.\n  Set init value: \\main_soclinux_uart_tx_fifo_readable = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:163$2028'.\n  Set init value: \\main_soclinux_uart_eventmanager_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:162$2027'.\n  Set init value: \\main_soclinux_uart_eventmanager_storage = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:161$2026'.\n  Set init value: \\main_soclinux_uart_eventmanager_pending_w = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:157$2025'.\n  Set init value: \\main_soclinux_uart_eventmanager_status_w = 2'00\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:153$2024'.\n  Set init value: \\main_soclinux_uart_rx_old_trigger = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:152$2023'.\n  Set init value: \\main_soclinux_uart_rx_clear = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:150$2022'.\n  Set init value: \\main_soclinux_uart_rx_pending = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:148$2021'.\n  Set init value: \\main_soclinux_uart_tx_old_trigger = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:147$2020'.\n  Set init value: \\main_soclinux_uart_tx_clear = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:145$2019'.\n  Set init value: \\main_soclinux_uart_tx_pending = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:132$2018'.\n  Set init value: \\main_soclinux_rx_busy = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:131$2017'.\n  Set init value: \\main_soclinux_rx_bitcount = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:130$2016'.\n  Set init value: \\main_soclinux_rx_reg = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:129$2015'.\n  Set init value: \\main_soclinux_rx_r = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:127$2014'.\n  Set init value: \\main_soclinux_rx_clkphase = 0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:126$2013'.\n  Set init value: \\main_soclinux_rx_clken = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:125$2012'.\n  Set init value: \\main_soclinux_source_payload_data = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:121$2009'.\n  Set init value: \\main_soclinux_source_valid = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:120$2008'.\n  Set init value: \\main_soclinux_tx_busy = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:119$2007'.\n  Set init value: \\main_soclinux_tx_bitcount = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:118$2006'.\n  Set init value: \\main_soclinux_tx_reg = 8'00000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:117$2005'.\n  Set init value: \\main_soclinux_tx_clkphase = 0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:116$2004'.\n  Set init value: \\main_soclinux_tx_clken = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:112$2003'.\n  Set init value: \\main_soclinux_sink_ready = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:110$2002'.\n  Set init value: \\main_soclinux_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:109$2001'.\n  Set init value: \\main_soclinux_storage = 85899345\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:107$2000'.\n  Set init value: \\main_soclinux_ram_we = 4'0000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:100$1998'.\n  Set init value: \\main_soclinux_ram_bus_ram_bus_ack = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:87$1996'.\n  Set init value: \\main_soclinux_soclinux_ram_bus_ack = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:79$1994'.\n  Set init value: \\main_soclinux_cpu_time_cmp = 64'1111111111111111111111111111111111111111111111111111111111111111\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:78$1993'.\n  Set init value: \\main_soclinux_cpu_time = 64'0000000000000000000000000000000000000000000000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:76$1992'.\n  Set init value: \\main_soclinux_cpu_time_cmp_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:75$1991'.\n  Set init value: \\main_soclinux_cpu_time_cmp_storage = 64'1111111111111111111111111111111111111111111111111111111111111111\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:72$1990'.\n  Set init value: \\main_soclinux_cpu_time_status = 64'0000000000000000000000000000000000000000000000000000000000000000\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:45$1988'.\n  Set init value: \\main_soclinux_cpu_interrupt0 = 0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:43$1987'.\n  Set init value: \\main_soclinux_soccontroller_bus_errors = 0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:37$1986'.\n  Set init value: \\main_soclinux_soccontroller_scratch_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:36$1985'.\n  Set init value: \\main_soclinux_soccontroller_scratch_storage = 305419896\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:35$1984'.\n  Set init value: \\main_soclinux_soccontroller_reset_re = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:34$1983'.\n  Set init value: \\main_soclinux_soccontroller_reset_storage = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1550$2491'.\n  Set init value: \\builder_inferedsdrtristate15_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1546$2490'.\n  Set init value: \\builder_inferedsdrtristate14_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1542$2489'.\n  Set init value: \\builder_inferedsdrtristate13_oe = 1'0\nFound init rule in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1538$2488'.\n  Set init value: \\builder_inferedsdrtristate12_oe = 1'0\n\n4.5.5. Executing PROC_ARST pass (detect async resets in processes).\n\n4.5.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$230'.\nCreating decoders for process `\\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$226'.\n     1/1: $0\\Q[0:0]\nCreating decoders for process `\\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$223'.\nCreating decoders for process `\\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$202'.\n     1/3: $0$memwr$\\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$201_EN[3:0]$205\n     2/3: $0$memwr$\\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$201_DATA[3:0]$204\n     3/3: $0$memwr$\\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$201_ADDR[3:0]$203\nCreating decoders for process `\\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$169'.\nCreating decoders for process `\\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$147'.\n     1/3: $0$memwr$\\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$145_EN[3:0]$150\n     2/3: $0$memwr$\\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$145_DATA[3:0]$149\n     3/3: $0$memwr$\\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$145_ADDR[3:0]$148\nCreating decoders for process `\\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$146'.\nCreating decoders for process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n     1/12: $0\\decodeStage_hit_error[0:0]\n     2/12: $0\\decodeStage_hit_valid[0:0]\n     3/12: $0\\decodeStage_mmuRsp_refilling[0:0]\n     4/12: $0\\decodeStage_mmuRsp_exception[0:0]\n     5/12: $0\\decodeStage_mmuRsp_allowExecute[0:0]\n     6/12: $0\\decodeStage_mmuRsp_allowWrite[0:0]\n     7/12: $0\\decodeStage_mmuRsp_allowRead[0:0]\n     8/12: $0\\decodeStage_mmuRsp_isIoAccess[0:0]\n     9/12: $0\\decodeStage_mmuRsp_physicalAddress[31:0]\n    10/12: $0\\io_cpu_fetch_data_regNextWhen[31:0]\n    11/12: $0\\lineLoader_flushCounter[7:0]\n    12/12: $0\\lineLoader_address[31:0]\nCreating decoders for process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:271$3882'.\n     1/5: $0\\lineLoader_wordIndex[2:0]\n     2/5: $0\\lineLoader_cmdSent[0:0]\n     3/5: $0\\lineLoader_flushPending[0:0]\n     4/5: $0\\lineLoader_hadError[0:0]\n     5/5: $0\\lineLoader_valid[0:0]\nCreating decoders for process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:226$3860'.\n     1/1: $1\\lineLoader_wayToAllocate_willIncrement[0:0]\nCreating decoders for process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:210$3855'.\n     1/3: $3\\io_cpu_prefetch_haltIt[0:0]\n     2/3: $2\\io_cpu_prefetch_haltIt[0:0]\n     3/3: $1\\io_cpu_prefetch_haltIt[0:0]\nCreating decoders for process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:201$3853'.\n     1/2: $2\\lineLoader_fire[0:0]\n     2/2: $1\\lineLoader_fire[0:0]\nCreating decoders for process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:193$3852'.\n     1/1: $1\\_zz_2_[0:0]\nCreating decoders for process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:186$3851'.\n     1/1: $1\\_zz_1_[0:0]\nCreating decoders for process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:180$3849'.\n     1/1: $0\\_zz_11_[31:0]\nCreating decoders for process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:174$3845'.\n     1/3: $0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848\n     2/3: $0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_DATA[31:0]$3847\n     3/3: $0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_ADDR[9:0]$3846\nCreating decoders for process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:168$3843'.\n     1/1: $0\\_zz_10_[21:0]\nCreating decoders for process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:162$3839'.\n     1/3: $0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842\n     2/3: $0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_DATA[21:0]$3841\n     3/3: $0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_ADDR[6:0]$3840\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1125$3815'.\n     1/10: $0\\stageB_mmuRsp_physicalAddress[31:0] [31:12]\n     2/10: $0\\stageB_mmuRsp_physicalAddress[31:0] [11:5]\n     3/10: $0\\stageB_mmuRsp_physicalAddress[31:0] [4:0]\n     4/10: $0\\loader_error[0:0]\n     5/10: $0\\loader_waysAllocator[0:0]\n     6/10: $0\\loader_valid[0:0]\n     7/10: $0\\stageB_memCmdSent[0:0]\n     8/10: $0\\stageB_lrsc_reserved[0:0]\n     9/10: $0\\stageB_flusher_valid[0:0]\n    10/10: $0\\loader_counter_value[2:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n     1/30: $0\\stageB_amo_resultRegValid[0:0]\n     2/30: $0\\stageB_colisions[0:0]\n     3/30: $0\\stageB_mask[3:0]\n     4/30: $0\\stageB_waysHits[0:0]\n     5/30: $0\\stageB_dataReadRsp_0[31:0]\n     6/30: $0\\stageB_tagsReadRsp_0_address[19:0]\n     7/30: $0\\stageB_tagsReadRsp_0_error[0:0]\n     8/30: $0\\stageB_tagsReadRsp_0_valid[0:0]\n     9/30: $0\\stageB_mmuRsp_refilling[0:0]\n    10/30: $0\\stageB_mmuRsp_exception[0:0]\n    11/30: $0\\stageB_mmuRsp_allowExecute[0:0]\n    12/30: $0\\stageB_mmuRsp_allowWrite[0:0]\n    13/30: $0\\stageB_mmuRsp_allowRead[0:0]\n    14/30: $0\\stageB_mmuRsp_isIoAccess[0:0]\n    15/30: $0\\stageB_request_amoCtrl_alu[2:0]\n    16/30: $0\\stageB_request_amoCtrl_swap[0:0]\n    17/30: $0\\stageB_isAmo[0:0]\n    18/30: $0\\stageB_request_isLrsc[0:0]\n    19/30: $0\\stageB_request_size[1:0]\n    20/30: $0\\stageB_request_data[31:0]\n    21/30: $0\\stageB_request_wr[0:0]\n    22/30: $0\\stage0_colisions_regNextWhen[0:0]\n    23/30: $0\\stageA_mask[3:0]\n    24/30: $0\\stageA_request_amoCtrl_alu[2:0]\n    25/30: $0\\stageA_request_amoCtrl_swap[0:0]\n    26/30: $0\\stageA_request_isAmo[0:0]\n    27/30: $0\\stageA_request_isLrsc[0:0]\n    28/30: $0\\stageA_request_size[1:0]\n    29/30: $0\\stageA_request_data[31:0]\n    30/30: $0\\stageA_request_wr[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1052$3797'.\n     1/1: $1\\loader_counter_valueNext[2:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1042$3794'.\n     1/1: $1\\loader_counter_willIncrement[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1030$3792'.\n     1/2: $2\\io_cpu_writeBack_data[31:0]\n     2/2: $1\\io_cpu_writeBack_data[31:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1017$3789'.\n     1/3: $3\\io_mem_cmd_payload_wr[0:0]\n     2/3: $2\\io_mem_cmd_payload_wr[0:0]\n     3/3: $1\\io_mem_cmd_payload_wr[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1002$3788'.\n     1/3: $3\\io_mem_cmd_payload_last[0:0]\n     2/3: $2\\io_mem_cmd_payload_last[0:0]\n     3/3: $1\\io_mem_cmd_payload_last[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:987$3787'.\n     1/3: $3\\io_mem_cmd_payload_length[2:0]\n     2/3: $2\\io_mem_cmd_payload_length[2:0]\n     3/3: $1\\io_mem_cmd_payload_length[2:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:972$3786'.\n     1/3: $3\\io_mem_cmd_payload_address[31:0]\n     2/3: $2\\io_mem_cmd_payload_address[31:0]\n     3/3: $1\\io_mem_cmd_payload_address[31:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:936$3783'.\n     1/11: $11\\io_mem_cmd_valid[0:0]\n     2/11: $10\\io_mem_cmd_valid[0:0]\n     3/11: $9\\io_mem_cmd_valid[0:0]\n     4/11: $8\\io_mem_cmd_valid[0:0]\n     5/11: $7\\io_mem_cmd_valid[0:0]\n     6/11: $6\\io_mem_cmd_valid[0:0]\n     7/11: $5\\io_mem_cmd_valid[0:0]\n     8/11: $4\\io_mem_cmd_valid[0:0]\n     9/11: $3\\io_mem_cmd_valid[0:0]\n    10/11: $2\\io_mem_cmd_valid[0:0]\n    11/11: $1\\io_mem_cmd_valid[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:924$3762'.\n     1/1: $1\\io_cpu_writeBack_accessError[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:905$3759'.\n     1/6: $6\\io_cpu_redo[0:0]\n     2/6: $5\\io_cpu_redo[0:0]\n     3/6: $4\\io_cpu_redo[0:0]\n     4/6: $3\\io_cpu_redo[0:0]\n     5/6: $2\\io_cpu_redo[0:0]\n     6/6: $1\\io_cpu_redo[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:885$3754'.\n     1/1: $1\\stageB_amo_result[31:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:873$3747'.\n     1/1: $1\\stageB_requestDataBypass[31:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:866$3746'.\n     1/1: $1\\io_cpu_flush_ready[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:832$3742'.\n     1/11: $11\\io_cpu_writeBack_haltIt[0:0]\n     2/11: $10\\io_cpu_writeBack_haltIt[0:0]\n     3/11: $9\\io_cpu_writeBack_haltIt[0:0]\n     4/11: $8\\io_cpu_writeBack_haltIt[0:0]\n     5/11: $7\\io_cpu_writeBack_haltIt[0:0]\n     6/11: $6\\io_cpu_writeBack_haltIt[0:0]\n     7/11: $5\\io_cpu_writeBack_haltIt[0:0]\n     8/11: $4\\io_cpu_writeBack_haltIt[0:0]\n     9/11: $3\\io_cpu_writeBack_haltIt[0:0]\n    10/11: $2\\io_cpu_writeBack_haltIt[0:0]\n    11/11: $1\\io_cpu_writeBack_haltIt[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:816$3739'.\n     1/5: $5\\stageB_loaderValid[0:0]\n     2/5: $4\\stageB_loaderValid[0:0]\n     3/5: $3\\stageB_loaderValid[0:0]\n     4/5: $2\\stageB_loaderValid[0:0]\n     5/5: $1\\stageB_loaderValid[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:806$3736'.\n     1/1: $1\\stageB_mmuRspFreeze[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:782$3717'.\n     1/1: $1\\_zz_6_[3:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:768$3715'.\n     1/4: $4\\dataWriteCmd_payload_mask[3:0]\n     2/4: $3\\dataWriteCmd_payload_mask[3:0]\n     3/4: $2\\dataWriteCmd_payload_mask[3:0]\n     4/4: $1\\dataWriteCmd_payload_mask[3:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:754$3713'.\n     1/4: $4\\dataWriteCmd_payload_data[31:0]\n     2/4: $3\\dataWriteCmd_payload_data[31:0]\n     3/4: $2\\dataWriteCmd_payload_data[31:0]\n     4/4: $1\\dataWriteCmd_payload_data[31:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:740$3711'.\n     1/4: $4\\dataWriteCmd_payload_address[9:0]\n     2/4: $3\\dataWriteCmd_payload_address[9:0]\n     3/4: $2\\dataWriteCmd_payload_address[9:0]\n     4/4: $1\\dataWriteCmd_payload_address[9:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:726$3709'.\n     1/4: $4\\dataWriteCmd_payload_way[0:0]\n     2/4: $3\\dataWriteCmd_payload_way[0:0]\n     3/4: $2\\dataWriteCmd_payload_way[0:0]\n     4/4: $1\\dataWriteCmd_payload_way[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:699$3706'.\n     1/9: $9\\dataWriteCmd_valid[0:0]\n     2/9: $8\\dataWriteCmd_valid[0:0]\n     3/9: $7\\dataWriteCmd_valid[0:0]\n     4/9: $6\\dataWriteCmd_valid[0:0]\n     5/9: $5\\dataWriteCmd_valid[0:0]\n     6/9: $4\\dataWriteCmd_valid[0:0]\n     7/9: $3\\dataWriteCmd_valid[0:0]\n     8/9: $2\\dataWriteCmd_valid[0:0]\n     9/9: $1\\dataWriteCmd_valid[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:692$3705'.\n     1/1: $1\\tagsWriteCmd_payload_data_address[19:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:685$3703'.\n     1/1: $1\\tagsWriteCmd_payload_data_error[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:675$3702'.\n     1/2: $2\\tagsWriteCmd_payload_data_valid[0:0]\n     2/2: $1\\tagsWriteCmd_payload_data_valid[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:665$3701'.\n     1/2: $2\\tagsWriteCmd_payload_address[6:0]\n     2/2: $1\\tagsWriteCmd_payload_address[6:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:655$3700'.\n     1/2: $2\\tagsWriteCmd_payload_way[0:0]\n     2/2: $1\\tagsWriteCmd_payload_way[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:642$3699'.\n     1/3: $3\\tagsWriteCmd_valid[0:0]\n     2/3: $2\\tagsWriteCmd_valid[0:0]\n     3/3: $1\\tagsWriteCmd_valid[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:635$3698'.\n     1/1: $1\\dataReadCmd_payload[9:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:628$3697'.\n     1/1: $1\\dataReadCmd_valid[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:621$3696'.\n     1/1: $1\\tagsReadCmd_payload[6:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:614$3695'.\n     1/1: $1\\tagsReadCmd_valid[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:599$3689'.\n     1/1: $1\\_zz_2_[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:592$3687'.\n     1/1: $1\\_zz_1_[0:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:583$3682'.\n     1/4: $0\\_zz_41_[7:0]\n     2/4: $0\\_zz_40_[7:0]\n     3/4: $0\\_zz_39_[7:0]\n     4/4: $0\\_zz_38_[7:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n     1/12: $0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN[7:0]$3668\n     2/12: $0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_DATA[7:0]$3667\n     3/12: $0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_ADDR[9:0]$3666\n     4/12: $0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN[7:0]$3671\n     5/12: $0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_DATA[7:0]$3670\n     6/12: $0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_ADDR[9:0]$3669\n     7/12: $0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN[7:0]$3674\n     8/12: $0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_DATA[7:0]$3673\n     9/12: $0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_ADDR[9:0]$3672\n    10/12: $0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN[7:0]$3677\n    11/12: $0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_DATA[7:0]$3676\n    12/12: $0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_ADDR[9:0]$3675\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:565$3664'.\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:559$3662'.\n     1/1: $0\\_zz_10_[21:0]\nCreating decoders for process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:553$3658'.\n     1/3: $0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661\n     2/3: $0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_DATA[21:0]$3660\n     3/3: $0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_ADDR[6:0]$3659\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2485$3615'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2484$3614'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n     1/204: $0\\memory_DivPlugin_rs1[32:0] [32]\n     2/204: $0\\memory_DivPlugin_accumulator[64:0] [31:0]\n     3/204: $0\\memory_DivPlugin_accumulator[64:0] [64:32]\n     4/204: $0\\decode_to_execute_IS_RS1_SIGNED[0:0]\n     5/204: $0\\decode_to_execute_RS1[31:0]\n     6/204: $0\\decode_to_execute_BYPASSABLE_EXECUTE_STAGE[0:0]\n     7/204: $0\\memory_to_writeBack_IS_MUL[0:0]\n     8/204: $0\\execute_to_memory_IS_MUL[0:0]\n     9/204: $0\\decode_to_execute_IS_MUL[0:0]\n    10/204: $0\\execute_to_memory_IS_DIV[0:0]\n    11/204: $0\\decode_to_execute_IS_DIV[0:0]\n    12/204: $0\\memory_to_writeBack_FORMAL_PC_NEXT[31:0]\n    13/204: $0\\execute_to_memory_FORMAL_PC_NEXT[31:0]\n    14/204: $0\\decode_to_execute_FORMAL_PC_NEXT[31:0]\n    15/204: $0\\decode_to_execute_BRANCH_CTRL[1:0]\n    16/204: $0\\decode_to_execute_CSR_WRITE_OPCODE[0:0]\n    17/204: $0\\memory_to_writeBack_MEMORY_ENABLE[0:0]\n    18/204: $0\\execute_to_memory_MEMORY_ENABLE[0:0]\n    19/204: $0\\decode_to_execute_MEMORY_ENABLE[0:0]\n    20/204: $0\\decode_to_execute_MEMORY_LRSC[0:0]\n    21/204: $0\\execute_to_memory_MUL_LH[33:0]\n    22/204: $0\\memory_to_writeBack_MEMORY_WR[0:0]\n    23/204: $0\\execute_to_memory_MEMORY_WR[0:0]\n    24/204: $0\\decode_to_execute_MEMORY_WR[0:0]\n    25/204: $0\\memory_to_writeBack_PC[31:0]\n    26/204: $0\\execute_to_memory_PC[31:0]\n    27/204: $0\\decode_to_execute_PC[31:0]\n    28/204: $0\\execute_to_memory_SHIFT_CTRL[1:0]\n    29/204: $0\\decode_to_execute_SHIFT_CTRL[1:0]\n    30/204: $0\\decode_to_execute_ALU_CTRL[1:0]\n    31/204: $0\\decode_to_execute_CSR_READ_OPCODE[0:0]\n    32/204: $0\\execute_to_memory_BRANCH_DO[0:0]\n    33/204: $0\\decode_to_execute_PREDICTION_HAD_BRANCHED2[0:0]\n    34/204: $0\\memory_to_writeBack_IS_SFENCE_VMA[0:0]\n    35/204: $0\\execute_to_memory_IS_SFENCE_VMA[0:0]\n    36/204: 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$0\\_zz_137_[2:0]\n   198/204: $0\\_zz_136_[3:0]\n   199/204: $0\\_zz_135_[31:0]\n   200/204: $0\\_zz_134_[31:0]\n   201/204: $0\\_zz_133_[0:0]\n   202/204: $0\\IBusCachedPlugin_s2_tightlyCoupledHit[0:0]\n   203/204: $0\\IBusCachedPlugin_s1_tightlyCoupledHit[0:0]\n   204/204: $0\\_zz_119_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n     1/85: $0\\_zz_238_[0:0]\n     2/85: $0\\_zz_231_[0:0]\n     3/85: $0\\memory_DivPlugin_div_counter_value[5:0]\n     4/85: $0\\execute_CsrPlugin_wfiWake[0:0]\n     5/85: $0\\CsrPlugin_hadException[0:0]\n     6/85: $0\\CsrPlugin_lastStageWasWfi[0:0]\n     7/85: $0\\CsrPlugin_interrupt_valid[0:0]\n     8/85: $0\\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack[0:0]\n     9/85: $0\\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory[0:0]\n    10/85: $0\\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute[0:0]\n    11/85: $0\\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode[0:0]\n    12/85: $0\\_zz_185_[0:0]\n    13/85: $0\\_zz_172_[0:0]\n    14/85: $0\\MmuPlugin_ports_1_entryToReplace_value[1:0]\n    15/85: $0\\MmuPlugin_ports_0_entryToReplace_value[1:0]\n    16/85: $0\\IBusCachedPlugin_fetchPc_booted[0:0]\n    17/85: $0\\_zz_232_[2:0]\n    18/85: $0\\_zz_230_[2:0]\n    19/85: $0\\memory_to_writeBack_IS_DBUS_SHARING[0:0]\n    20/85: $0\\execute_to_memory_IS_DBUS_SHARING[0:0]\n    21/85: $0\\memory_to_writeBack_INSTRUCTION[31:0]\n    22/85: $0\\memory_to_writeBack_REGFILE_WRITE_DATA[31:0]\n    23/85: $0\\_zz_228_[31:0]\n    24/85: $0\\_zz_226_[31:0]\n    25/85: $0\\CsrPlugin_sie_SSIE[0:0]\n    26/85: $0\\CsrPlugin_sie_STIE[0:0]\n    27/85: $0\\CsrPlugin_sie_SEIE[0:0]\n    28/85: $0\\CsrPlugin_sip_SSIP[0:0]\n    29/85: $0\\CsrPlugin_sip_STIP[0:0]\n    30/85: $0\\CsrPlugin_sip_SEIP_SOFT[0:0]\n    31/85: $0\\CsrPlugin_sstatus_SPP[0:0]\n    32/85: $0\\CsrPlugin_sstatus_SPIE[0:0]\n    33/85: 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 57/85: $0\\MmuPlugin_ports_1_cache_3_valid[0:0]\n    58/85: $0\\MmuPlugin_ports_1_cache_2_valid[0:0]\n    59/85: $0\\MmuPlugin_ports_1_cache_1_valid[0:0]\n    60/85: $0\\MmuPlugin_ports_1_cache_0_valid[0:0]\n    61/85: $0\\MmuPlugin_ports_0_cache_3_valid[0:0]\n    62/85: $0\\MmuPlugin_ports_0_cache_2_valid[0:0]\n    63/85: $0\\MmuPlugin_ports_0_cache_1_valid[0:0]\n    64/85: $0\\MmuPlugin_ports_0_cache_0_valid[0:0]\n    65/85: $0\\MmuPlugin_satp_mode[0:0]\n    66/85: $0\\MmuPlugin_status_mprv[0:0]\n    67/85: $0\\MmuPlugin_status_mxr[0:0]\n    68/85: $0\\MmuPlugin_status_sum[0:0]\n    69/85: $0\\DBusCachedPlugin_rspCounter[31:0]\n    70/85: $0\\_zz_139_[0:0]\n    71/85: $0\\_zz_132_[0:0]\n    72/85: $0\\IBusCachedPlugin_rspCounter[31:0]\n    73/85: $0\\IBusCachedPlugin_injector_decodeRemoved[0:0]\n    74/85: $0\\IBusCachedPlugin_injector_nextPcCalc_valids_4[0:0]\n    75/85: $0\\IBusCachedPlugin_injector_nextPcCalc_valids_3[0:0]\n    76/85: $0\\IBusCachedPlugin_injector_nextPcCalc_valids_2[0:0]\n    77/85: $0\\IBusCachedPlugin_injector_nextPcCalc_valids_1[0:0]\n    78/85: $0\\IBusCachedPlugin_injector_nextPcCalc_valids_0[0:0]\n    79/85: $0\\_zz_118_[0:0]\n    80/85: $0\\_zz_116_[0:0]\n    81/85: $0\\IBusCachedPlugin_fetchPc_inc[0:0]\n    82/85: $0\\IBusCachedPlugin_fetchPc_pcReg[31:0]\n    83/85: $0\\writeBack_arbitration_isValid[0:0]\n    84/85: $0\\memory_arbitration_isValid[0:0]\n    85/85: $0\\execute_arbitration_isValid[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6677$3408'.\n     1/1: $1\\iBusWishbone_STB[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6670$3407'.\n     1/1: $1\\iBusWishbone_CYC[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6608$3346'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6591$3338'.\n     1/2: $2\\memory_DivPlugin_div_counter_valueNext[5:0]\n     2/2: $1\\memory_DivPlugin_div_counter_valueNext[5:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6582$3335'.\n     1/1: $1\\memory_DivPlugin_div_counter_willClear[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6573$3334'.\n     1/2: $2\\memory_DivPlugin_div_counter_willIncrement[0:0]\n     2/2: $1\\memory_DivPlugin_div_counter_willIncrement[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6547$3325'.\n     1/1: $1\\execute_MulPlugin_bSigned[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6533$3324'.\n     1/1: $1\\execute_MulPlugin_aSigned[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6519$3319'.\n     1/1: $1\\execute_CsrPlugin_writeData[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6505$3318'.\n     1/1: $1\\execute_CsrPlugin_readToWriteData[9:9]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6381$3305'.\n     1/20: $1\\execute_CsrPlugin_readData[31:0] [31]\n     2/20: $1\\execute_CsrPlugin_readData[31:0] [25:20]\n     3/20: $1\\execute_CsrPlugin_readData[31:0] [11]\n     4/20: $1\\execute_CsrPlugin_readData[31:0] [7]\n     5/20: $1\\execute_CsrPlugin_readData[31:0] [16:13]\n     6/20: $1\\execute_CsrPlugin_readData[31:0] [0]\n     7/20: $1\\execute_CsrPlugin_readData[31:0] [4]\n     8/20: $1\\execute_CsrPlugin_readData[31:0] [9]\n     9/20: $1\\execute_CsrPlugin_readData[31:0] [8]\n    10/20: $1\\execute_CsrPlugin_readData[31:0] [2]\n    11/20: $1\\execute_CsrPlugin_readData[31:0] [12]\n    12/20: $1\\execute_CsrPlugin_readData[31:0] [3]\n    13/20: $1\\execute_CsrPlugin_readData[31:0] [6]\n    14/20: $1\\execute_CsrPlugin_readData[31:0] [17]\n    15/20: $1\\execute_CsrPlugin_readData[31:0] [1]\n    16/20: $1\\execute_CsrPlugin_readData[31:0] [10]\n    17/20: $1\\execute_CsrPlugin_readData[31:0] [19]\n    18/20: $1\\execute_CsrPlugin_readData[31:0] [5]\n    19/20: $1\\execute_CsrPlugin_readData[31:0] [18]\n    20/20: $1\\execute_CsrPlugin_readData[31:0] [30:26]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6360$3304'.\n     1/3: $3\\CsrPlugin_selfException_payload_code[3:0]\n     2/3: $2\\CsrPlugin_selfException_payload_code[3:0]\n     3/3: $1\\CsrPlugin_selfException_payload_code[3:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6350$3303'.\n     1/2: $2\\CsrPlugin_selfException_valid[0:0]\n     2/2: $1\\CsrPlugin_selfException_valid[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6341$3299'.\n     1/2: $2\\execute_CsrPlugin_illegalInstruction[0:0]\n     2/2: $1\\execute_CsrPlugin_illegalInstruction[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6219$3294'.\n     1/15: $15\\execute_CsrPlugin_illegalAccess[0:0]\n     2/15: $14\\execute_CsrPlugin_illegalAccess[0:0]\n     3/15: $13\\execute_CsrPlugin_illegalAccess[0:0]\n     4/15: $12\\execute_CsrPlugin_illegalAccess[0:0]\n     5/15: $11\\execute_CsrPlugin_illegalAccess[0:0]\n     6/15: $10\\execute_CsrPlugin_illegalAccess[0:0]\n     7/15: $9\\execute_CsrPlugin_illegalAccess[0:0]\n     8/15: $8\\execute_CsrPlugin_illegalAccess[0:0]\n     9/15: $7\\execute_CsrPlugin_illegalAccess[0:0]\n    10/15: $6\\execute_CsrPlugin_illegalAccess[0:0]\n    11/15: $5\\execute_CsrPlugin_illegalAccess[0:0]\n    12/15: $4\\execute_CsrPlugin_illegalAccess[0:0]\n    13/15: $3\\execute_CsrPlugin_illegalAccess[0:0]\n    14/15: $2\\execute_CsrPlugin_illegalAccess[0:0]\n    15/15: $1\\execute_CsrPlugin_illegalAccess[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6211$3292'.\n     1/1: $1\\execute_CsrPlugin_inWfi[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6194$3282'.\n     1/1: $1\\CsrPlugin_xtvec_base[29:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6180$3281'.\n     1/1: $1\\CsrPlugin_xtvec_mode[1:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6173$3280'.\n     1/1: $1\\CsrPlugin_trapCause[3:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6166$3279'.\n     1/1: $1\\CsrPlugin_targetPrivilege[1:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6155$3272'.\n     1/2: $2\\CsrPlugin_pipelineLiberator_done[0:0]\n     2/2: $1\\CsrPlugin_pipelineLiberator_done[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6140$3270'.\n     1/2: $2\\CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack[0:0]\n     2/2: $1\\CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6130$3269'.\n     1/2: $2\\CsrPlugin_exceptionPortCtrl_exceptionValids_memory[0:0]\n     2/2: $1\\CsrPlugin_exceptionPortCtrl_exceptionValids_memory[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6120$3268'.\n     1/2: $2\\CsrPlugin_exceptionPortCtrl_exceptionValids_execute[0:0]\n     2/2: $1\\CsrPlugin_exceptionPortCtrl_exceptionValids_execute[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6110$3267'.\n     1/2: $2\\CsrPlugin_exceptionPortCtrl_exceptionValids_decode[0:0]\n     2/2: $1\\CsrPlugin_exceptionPortCtrl_exceptionValids_decode[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6039$3240'.\n     1/13: $13\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n     2/13: $12\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n     3/13: $11\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n     4/13: $10\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n     5/13: $9\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n     6/13: $8\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n     7/13: $7\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n     8/13: $6\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n     9/13: $5\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n    10/13: $4\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n    11/13: $3\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n    12/13: $2\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n    13/13: $1\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6023$3232'.\n     1/1: $1\\CsrPlugin_privilege[1:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5993$3226'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5978$3225'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5963$3222'.\n     1/2: $2\\execute_BranchPlugin_branch_src2[31:0]\n     2/2: $1\\execute_BranchPlugin_branch_src2[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5940$3221'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5928$3220'.\n     1/1: $1\\execute_BranchPlugin_branch_src1[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5912$3215'.\n     1/1: $1\\_zz_203_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5890$3214'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5875$3213'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5851$3212'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5832$3211'.\n     1/1: $1\\_zz_196_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5820$3204'.\n     1/3: $3\\_zz_195_[0:0]\n     2/3: $2\\_zz_195_[0:0]\n     3/3: $1\\_zz_195_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5782$3194'.\n     1/10: $10\\_zz_183_[0:0]\n     2/10: $9\\_zz_183_[0:0]\n     3/10: $8\\_zz_183_[0:0]\n     4/10: $7\\_zz_183_[0:0]\n     5/10: $6\\_zz_183_[0:0]\n     6/10: $5\\_zz_183_[0:0]\n     7/10: $4\\_zz_183_[0:0]\n     8/10: $3\\_zz_183_[0:0]\n     9/10: $2\\_zz_183_[0:0]\n    10/10: $1\\_zz_183_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5754$3192'.\n     1/10: $10\\_zz_182_[0:0]\n     2/10: $9\\_zz_182_[0:0]\n     3/10: $8\\_zz_182_[0:0]\n     4/10: $7\\_zz_182_[0:0]\n     5/10: $6\\_zz_182_[0:0]\n     6/10: $5\\_zz_182_[0:0]\n     7/10: $4\\_zz_182_[0:0]\n     8/10: $3\\_zz_182_[0:0]\n     9/10: $2\\_zz_182_[0:0]\n    10/10: $1\\_zz_182_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5719$3191'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5682$3188'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5670$3184'.\n     1/1: $1\\execute_SrcPlugin_addSub[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5652$3183'.\n     1/1: $1\\_zz_179_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5629$3182'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5605$3181'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5586$3180'.\n     1/1: $1\\_zz_174_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5570$3177'.\n     1/1: $1\\_zz_173_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5556$3173'.\n     1/1: $1\\execute_IntAluPlugin_bitwise[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5547$3171'.\n     1/1: $1\\lastStageRegFileWrite_valid[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5474$3133'.\n     1/1: $1\\MmuPlugin_dBusAccess_cmd_payload_address[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5454$3132'.\n     1/1: $1\\MmuPlugin_dBusAccess_cmd_valid[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5432$3119'.\n     1/1: $1\\IBusCachedPlugin_mmuBus_rsp_refilling[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5424$3108'.\n     1/1: $1\\IBusCachedPlugin_mmuBus_rsp_exception[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5416$3107'.\n     1/1: $1\\IBusCachedPlugin_mmuBus_rsp_allowExecute[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5408$3106'.\n     1/1: $1\\IBusCachedPlugin_mmuBus_rsp_allowWrite[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5400$3103'.\n     1/1: $1\\IBusCachedPlugin_mmuBus_rsp_allowRead[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5392$3101'.\n     1/1: $1\\IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5382$3093'.\n     1/2: $2\\MmuPlugin_ports_1_requireMmuLockup[0:0]\n     2/2: $1\\MmuPlugin_ports_1_requireMmuLockup[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5375$3091'.\n     1/1: $1\\MmuPlugin_ports_1_entryToReplace_valueNext[1:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5363$3088'.\n     1/2: $2\\MmuPlugin_ports_1_entryToReplace_willIncrement[0:0]\n     2/2: $1\\MmuPlugin_ports_1_entryToReplace_willIncrement[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5335$3058'.\n     1/1: $1\\DBusCachedPlugin_mmuBus_rsp_refilling[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5327$3047'.\n     1/1: $1\\DBusCachedPlugin_mmuBus_rsp_exception[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5319$3046'.\n     1/1: $1\\DBusCachedPlugin_mmuBus_rsp_allowExecute[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5311$3045'.\n     1/1: $1\\DBusCachedPlugin_mmuBus_rsp_allowWrite[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5303$3042'.\n     1/1: $1\\DBusCachedPlugin_mmuBus_rsp_allowRead[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5295$3040'.\n     1/1: $1\\DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5283$3029'.\n     1/3: $3\\MmuPlugin_ports_0_requireMmuLockup[0:0]\n     2/3: $2\\MmuPlugin_ports_0_requireMmuLockup[0:0]\n     3/3: $1\\MmuPlugin_ports_0_requireMmuLockup[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5276$3027'.\n     1/1: $1\\MmuPlugin_ports_0_entryToReplace_valueNext[1:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5264$3024'.\n     1/2: $2\\MmuPlugin_ports_0_entryToReplace_willIncrement[0:0]\n     2/2: $1\\MmuPlugin_ports_0_entryToReplace_willIncrement[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5231$2993'.\n     1/2: $2\\DBusCachedPlugin_forceDatapath[0:0]\n     2/2: $1\\DBusCachedPlugin_forceDatapath[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5220$2991'.\n     1/3: $3\\MmuPlugin_dBusAccess_cmd_ready[0:0]\n     2/3: $2\\MmuPlugin_dBusAccess_cmd_ready[0:0]\n     3/3: $1\\MmuPlugin_dBusAccess_cmd_ready[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5206$2990'.\n     1/1: $1\\writeBack_DBusCachedPlugin_rspFormated[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5186$2989'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5157$2986'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5139$2983'.\n     1/2: $1\\writeBack_DBusCachedPlugin_rspShifted[15:0] [15:8]\n     2/2: $1\\writeBack_DBusCachedPlugin_rspShifted[15:0] [7:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5124$2981'.\n     1/4: $4\\DBusCachedPlugin_exceptionBus_payload_code[3:0]\n     2/4: $3\\DBusCachedPlugin_exceptionBus_payload_code[3:0]\n     3/4: $2\\DBusCachedPlugin_exceptionBus_payload_code[3:0]\n     4/4: $1\\DBusCachedPlugin_exceptionBus_payload_code[3:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5105$2980'.\n     1/5: $5\\DBusCachedPlugin_exceptionBus_valid[0:0]\n     2/5: $4\\DBusCachedPlugin_exceptionBus_valid[0:0]\n     3/5: $3\\DBusCachedPlugin_exceptionBus_valid[0:0]\n     4/5: $2\\DBusCachedPlugin_exceptionBus_valid[0:0]\n     5/5: $1\\DBusCachedPlugin_exceptionBus_valid[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5095$2979'.\n     1/2: $2\\DBusCachedPlugin_redoBranch_valid[0:0]\n     2/2: $1\\DBusCachedPlugin_redoBranch_valid[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5086$2976'.\n     1/1: $1\\_zz_260_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5078$2973'.\n     1/1: $1\\_zz_259_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5071$2972'.\n     1/1: $1\\DBusCachedPlugin_mmuBus_cmd_bypassTranslation[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5061$2970'.\n     1/1: $1\\_zz_257_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5049$2969'.\n     1/2: $2\\_zz_254_[0:0]\n     2/2: $1\\_zz_254_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5037$2968'.\n     1/3: $3\\_zz_253_[0:0]\n     2/3: $2\\_zz_253_[0:0]\n     3/3: $1\\_zz_253_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5027$2966'.\n     1/2: $2\\_zz_252_[1:0]\n     2/2: $1\\_zz_252_[1:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5018$2965'.\n     1/2: $2\\_zz_251_[31:0]\n     2/2: $1\\_zz_251_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5004$2964'.\n     1/1: $1\\_zz_147_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4995$2963'.\n     1/2: $2\\_zz_250_[0:0]\n     2/2: $1\\_zz_250_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4986$2962'.\n     1/2: $2\\_zz_249_[31:0]\n     2/2: $1\\_zz_249_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4975$2960'.\n     1/3: $3\\_zz_248_[0:0]\n     2/3: $2\\_zz_248_[0:0]\n     3/3: $1\\_zz_248_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4928$2947'.\n     1/2: $2\\IBusCachedPlugin_decodeExceptionPort_payload_code[3:0]\n     2/2: $1\\IBusCachedPlugin_decodeExceptionPort_payload_code[3:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4918$2946'.\n     1/2: $2\\IBusCachedPlugin_decodeExceptionPort_valid[0:0]\n     2/2: $1\\IBusCachedPlugin_decodeExceptionPort_valid[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4908$2943'.\n     1/2: $2\\_zz_247_[0:0]\n     2/2: $1\\_zz_247_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4895$2942'.\n     1/3: $3\\IBusCachedPlugin_rsp_redoFetch[0:0]\n     2/3: $2\\IBusCachedPlugin_rsp_redoFetch[0:0]\n     3/3: $1\\IBusCachedPlugin_rsp_redoFetch[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4879$2931'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4855$2927'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4840$2926'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4827$2924'.\n     1/1: $1\\_zz_126_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4805$2923'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4790$2922'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4782$2917'.\n     1/1: $1\\IBusCachedPlugin_decodePrediction_cmd_hadBranch[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4760$2916'.\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4743$2910'.\n     1/1: $1\\IBusCachedPlugin_iBusRsp_readyForError[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4723$2899'.\n     1/1: $1\\IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4712$2895'.\n     1/1: $1\\IBusCachedPlugin_iBusRsp_stages_1_halt[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4701$2891'.\n     1/1: $1\\IBusCachedPlugin_iBusRsp_stages_0_halt[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4686$2887'.\n     1/1: $1\\IBusCachedPlugin_fetchPc_pc[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4679$2886'.\n     1/1: $1\\IBusCachedPlugin_fetchPc_pcRegPropagate[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4672$2885'.\n     1/1: $1\\IBusCachedPlugin_fetchPc_corrected[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4642$2879'.\n     1/3: $3\\CsrPlugin_jumpInterface_payload[31:0]\n     2/3: $2\\CsrPlugin_jumpInterface_payload[31:0]\n     3/3: $1\\CsrPlugin_jumpInterface_payload[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4632$2878'.\n     1/2: $2\\CsrPlugin_jumpInterface_valid[0:0]\n     2/2: $1\\CsrPlugin_jumpInterface_valid[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4625$2876'.\n     1/1: $1\\IBusCachedPlugin_incomingInstruction[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4615$2873'.\n     1/2: $2\\IBusCachedPlugin_fetcherflushIt[0:0]\n     2/2: $1\\IBusCachedPlugin_fetcherflushIt[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4602$2871'.\n     1/3: $3\\IBusCachedPlugin_fetcherHalt[0:0]\n     2/3: $2\\IBusCachedPlugin_fetcherHalt[0:0]\n     3/3: $1\\IBusCachedPlugin_fetcherHalt[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4582$2870'.\n     1/4: $4\\writeBack_arbitration_flushNext[0:0]\n     2/4: $3\\writeBack_arbitration_flushNext[0:0]\n     3/4: $2\\writeBack_arbitration_flushNext[0:0]\n     4/4: $1\\writeBack_arbitration_flushNext[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4575$2869'.\n     1/1: $1\\writeBack_arbitration_flushIt[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4565$2868'.\n     1/2: $2\\writeBack_arbitration_removeIt[0:0]\n     2/2: $1\\writeBack_arbitration_removeIt[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4557$2867'.\n     1/1: $1\\writeBack_arbitration_haltItself[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4547$2866'.\n     1/2: $2\\memory_arbitration_flushNext[0:0]\n     2/2: $1\\memory_arbitration_flushNext[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4536$2865'.\n     1/2: $2\\memory_arbitration_removeIt[0:0]\n     2/2: $1\\memory_arbitration_removeIt[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4526$2864'.\n     1/2: $2\\memory_arbitration_haltItself[0:0]\n     2/2: $1\\memory_arbitration_haltItself[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4519$2863'.\n     1/1: $1\\execute_arbitration_flushNext[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4508$2862'.\n     1/2: $2\\execute_arbitration_removeIt[0:0]\n     2/2: $1\\execute_arbitration_removeIt[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4487$2856'.\n     1/6: $6\\execute_arbitration_haltItself[0:0]\n     2/6: $5\\execute_arbitration_haltItself[0:0]\n     3/6: $4\\execute_arbitration_haltItself[0:0]\n     4/6: $3\\execute_arbitration_haltItself[0:0]\n     5/6: $2\\execute_arbitration_haltItself[0:0]\n     6/6: $1\\execute_arbitration_haltItself[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4477$2855'.\n     1/2: $2\\decode_arbitration_flushNext[0:0]\n     2/2: $1\\decode_arbitration_flushNext[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4466$2854'.\n     1/2: $2\\decode_arbitration_removeIt[0:0]\n     2/2: $1\\decode_arbitration_removeIt[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4450$2843'.\n     1/4: $4\\decode_arbitration_haltByOther[0:0]\n     2/4: $3\\decode_arbitration_haltByOther[0:0]\n     3/4: $2\\decode_arbitration_haltByOther[0:0]\n     4/4: $1\\decode_arbitration_haltByOther[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4443$2840'.\n     1/1: $1\\decode_arbitration_haltItself[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4430$2839'.\n     1/2: $2\\_zz_101_[31:0]\n     2/2: $1\\_zz_101_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4423$2838'.\n     1/1: $1\\_zz_100_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4414$2837'.\n     1/1: $1\\_zz_97_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4407$2836'.\n     1/1: $1\\_zz_96_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4400$2835'.\n     1/1: $1\\_zz_95_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4393$2834'.\n     1/1: $1\\IBusCachedPlugin_rsp_issueDetected[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4360$2831'.\n     1/3: $3\\_zz_93_[31:0]\n     2/3: $2\\_zz_93_[31:0]\n     3/3: $1\\_zz_93_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4348$2829'.\n     1/1: $1\\decode_REGFILE_WRITE_VALID[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4340$2828'.\n     1/1: $1\\_zz_61_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4303$2827'.\n     1/3: $3\\_zz_43_[31:0]\n     2/3: $2\\_zz_43_[31:0]\n     3/3: $1\\_zz_43_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4272$2825'.\n     1/11: $11\\decode_RS1[31:0]\n     2/11: $10\\decode_RS1[31:0]\n     3/11: $9\\decode_RS1[31:0]\n     4/11: $8\\decode_RS1[31:0]\n     5/11: $7\\decode_RS1[31:0]\n     6/11: $6\\decode_RS1[31:0]\n     7/11: $5\\decode_RS1[31:0]\n     8/11: $4\\decode_RS1[31:0]\n     9/11: $3\\decode_RS1[31:0]\n    10/11: $2\\decode_RS1[31:0]\n    11/11: $1\\decode_RS1[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4242$2823'.\n     1/11: $11\\decode_RS2[31:0]\n     2/11: $10\\decode_RS2[31:0]\n     3/11: $9\\decode_RS2[31:0]\n     4/11: $8\\decode_RS2[31:0]\n     5/11: $7\\decode_RS2[31:0]\n     6/11: $6\\decode_RS2[31:0]\n     7/11: $5\\decode_RS2[31:0]\n     8/11: $4\\decode_RS2[31:0]\n     9/11: $3\\decode_RS2[31:0]\n    10/11: $2\\decode_RS2[31:0]\n    11/11: $1\\decode_RS2[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4226$2822'.\n     1/2: $2\\_zz_42_[31:0]\n     2/2: $1\\_zz_42_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\n     1/11: $1\\_zz_289_[0:0]\n     2/11: $1\\_zz_288_[0:0]\n     3/11: $1\\_zz_287_[0:0]\n     4/11: $1\\_zz_286_[0:0]\n     5/11: $1\\_zz_285_[9:0]\n     6/11: $1\\_zz_284_[9:0]\n     7/11: $1\\_zz_283_[9:0]\n     8/11: $1\\_zz_282_[9:0]\n     9/11: $1\\_zz_281_[0:0]\n    10/11: $1\\_zz_280_[0:0]\n    11/11: $1\\_zz_279_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\n     1/11: $1\\_zz_278_[0:0]\n     2/11: $1\\_zz_277_[0:0]\n     3/11: $1\\_zz_276_[0:0]\n     4/11: $1\\_zz_275_[0:0]\n     5/11: $1\\_zz_274_[9:0]\n     6/11: $1\\_zz_273_[9:0]\n     7/11: $1\\_zz_272_[9:0]\n     8/11: $1\\_zz_271_[9:0]\n     9/11: $1\\_zz_270_[0:0]\n    10/11: $1\\_zz_269_[0:0]\n    11/11: $1\\_zz_268_[0:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3313$2819'.\n     1/1: $1\\_zz_267_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3204$2817'.\n     1/1: $0\\_zz_266_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3198$2815'.\n     1/1: $0\\_zz_265_[31:0]\nCreating decoders for process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3192$2811'.\n     1/3: $0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814\n     2/3: $0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_DATA[31:0]$2813\n     3/3: $0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_ADDR[4:0]$2812\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1534$2487'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1530$2486'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1526$2485'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1522$2484'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1518$2483'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1514$2482'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1510$2481'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1506$2480'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1502$2479'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1498$2478'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1494$2477'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1490$2476'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1485$2475'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1484$2474'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1483$2473'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1482$2472'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1481$2471'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1480$2470'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1479$2469'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1478$2468'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1477$2467'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1476$2466'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1475$2465'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1474$2464'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1473$2463'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1472$2462'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1471$2461'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1470$2460'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1469$2459'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1468$2458'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1467$2457'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1466$2456'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1465$2455'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1464$2454'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1463$2453'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1462$2452'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1461$2451'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1460$2450'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1459$2449'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1458$2448'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1457$2447'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1456$2446'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1455$2445'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1454$2444'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1453$2443'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1452$2442'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1451$2441'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1450$2440'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1449$2439'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1448$2438'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1447$2437'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1446$2436'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1445$2435'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1444$2434'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1443$2433'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1442$2432'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1441$2431'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1440$2430'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1439$2429'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1438$2428'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1437$2427'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1436$2426'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1435$2425'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1434$2424'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1433$2423'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1432$2422'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1431$2421'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1430$2420'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1408$2419'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1383$2418'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1318$2417'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1277$2416'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1236$2415'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1227$2414'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1223$2413'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1219$2412'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1178$2411'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1109$2410'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1105$2409'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1102$2408'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1101$2407'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1100$2406'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1099$2405'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1093$2404'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1089$2403'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1086$2402'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1082$2401'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1078$2400'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1074$2399'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1073$2398'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1072$2397'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1071$2396'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1070$2395'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1069$2394'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1068$2393'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1067$2392'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1066$2391'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1065$2390'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1064$2389'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1063$2388'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1062$2387'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1061$2386'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1060$2385'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1059$2384'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1058$2383'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1057$2382'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1056$2381'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1055$2380'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1054$2379'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1053$2378'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1040$2377'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1039$2376'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1038$2375'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1037$2374'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1036$2373'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1035$2372'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1034$2371'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1033$2370'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1032$2369'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1031$2368'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1030$2367'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1029$2366'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1028$2365'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1027$2364'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1026$2363'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1025$2362'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1024$2361'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1021$2360'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1020$2359'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1019$2358'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1018$2357'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1017$2356'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1016$2355'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1015$2354'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1014$2353'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1013$2352'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1012$2351'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1007$2350'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1006$2349'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1001$2348'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1000$2347'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:998$2346'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:994$2345'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:992$2344'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:991$2343'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:988$2342'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:985$2341'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:984$2340'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:983$2339'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:982$2338'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:978$2337'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:977$2336'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:971$2335'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:969$2334'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:968$2333'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:967$2332'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:966$2331'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:965$2330'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:957$2329'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:940$2328'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:938$2327'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:933$2326'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:916$2325'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:908$2324'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:907$2323'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:901$2322'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:898$2321'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:897$2320'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:896$2319'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:891$2318'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:888$2317'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:887$2316'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:886$2315'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:885$2314'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:882$2313'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:880$2312'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:879$2311'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:874$2310'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:870$2309'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:866$2308'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:862$2307'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:861$2306'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:852$2305'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:851$2304'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:849$2303'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:847$2302'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:845$2301'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:844$2300'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:842$2299'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:839$2298'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:838$2297'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:836$2296'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:835$2295'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:833$2294'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:831$2293'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:830$2292'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:828$2291'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:827$2290'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:826$2289'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:825$2288'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:824$2287'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:822$2286'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:820$2285'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:816$2284'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:815$2283'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:814$2282'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:811$2281'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:809$2280'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:807$2279'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:806$2278'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:804$2277'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:802$2276'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:798$2275'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:797$2274'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:796$2273'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:793$2272'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:791$2271'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:790$2270'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:789$2269'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:788$2268'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:785$2267'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:784$2266'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:782$2265'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:781$2264'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:779$2263'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:778$2262'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:776$2261'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:775$2260'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:774$2259'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:772$2258'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:771$2257'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:770$2256'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:769$2255'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:768$2254'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:767$2253'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:765$2252'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:744$2251'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:743$2250'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:742$2249'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:741$2248'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:740$2247'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:725$2246'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:724$2245'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:721$2244'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:720$2243'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:719$2242'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:718$2241'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:717$2240'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:716$2239'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:715$2238'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:713$2237'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:712$2236'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:711$2235'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:710$2234'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:708$2233'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:707$2232'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:701$2231'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:700$2230'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:698$2229'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:697$2228'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:695$2227'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:694$2226'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:692$2225'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:691$2224'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:690$2223'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:688$2222'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:687$2221'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:686$2220'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:685$2219'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:684$2218'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:683$2217'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:681$2216'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:660$2215'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:659$2214'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:658$2213'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:657$2212'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:656$2211'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:641$2210'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:640$2209'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:637$2208'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:636$2207'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:635$2206'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:634$2205'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:633$2204'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:632$2203'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:631$2202'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:629$2201'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:628$2200'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:627$2199'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:626$2198'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:624$2197'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:623$2196'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:617$2195'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:616$2194'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:614$2193'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:613$2192'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:611$2191'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:610$2190'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:608$2189'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:607$2188'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:606$2187'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:604$2186'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:603$2185'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:602$2184'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:601$2183'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:600$2182'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:599$2181'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:597$2180'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:576$2179'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:575$2178'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:574$2177'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:573$2176'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:572$2175'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:557$2174'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:556$2173'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:553$2172'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:552$2171'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:551$2170'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:550$2169'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:549$2168'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:548$2167'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:547$2166'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:545$2165'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:544$2164'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:543$2163'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:542$2162'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:540$2161'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:539$2160'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:533$2159'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:532$2158'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:530$2157'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:529$2156'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:527$2155'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:526$2154'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:524$2153'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:523$2152'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:522$2151'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:520$2150'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:519$2149'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:518$2148'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:517$2147'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:516$2146'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:515$2145'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:513$2144'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:492$2143'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:491$2142'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:490$2141'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:489$2140'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:488$2139'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:473$2138'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:472$2137'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:469$2136'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:468$2135'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:467$2134'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:466$2133'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:465$2132'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:464$2131'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:463$2130'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:461$2129'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:460$2128'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:459$2127'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:458$2126'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:456$2125'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:455$2124'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:449$2123'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:448$2122'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:447$2121'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:444$2120'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:443$2119'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:442$2118'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:440$2117'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:434$2116'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:433$2115'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:432$2114'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:431$2113'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:430$2112'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:429$2111'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:428$2110'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:427$2109'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:426$2108'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:425$2107'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:422$2106'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:420$2105'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:418$2104'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:414$2103'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:413$2102'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:412$2101'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:411$2100'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:410$2099'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:409$2098'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:407$2097'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:406$2096'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:375$2095'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:374$2094'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:373$2093'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:372$2092'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:371$2091'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:370$2090'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:369$2089'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:368$2088'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:364$2087'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:363$2086'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:362$2085'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:361$2084'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:354$2083'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:353$2082'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:352$2081'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:351$2080'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:350$2079'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:349$2078'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:348$2077'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:347$2076'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:346$2075'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:345$2074'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:344$2073'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:343$2072'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:342$2071'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:341$2070'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:340$2069'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:339$2068'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:324$2067'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:323$2066'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:318$2065'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:314$2064'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:313$2063'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:312$2062'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:311$2061'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:308$2060'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:307$2059'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:282$2058'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:281$2057'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:280$2056'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:271$2055'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:270$2054'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:268$2053'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:263$2052'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:262$2051'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:261$2050'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:260$2049'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:259$2048'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:258$2047'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:257$2046'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:256$2045'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:255$2044'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:254$2043'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:239$2042'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:238$2041'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:237$2040'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:236$2039'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:235$2038'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:228$2037'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:202$2036'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:201$2035'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:200$2034'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:199$2033'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:198$2032'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:191$2031'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:183$2030'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:182$2029'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:163$2028'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:162$2027'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:161$2026'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:157$2025'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:153$2024'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:152$2023'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:150$2022'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:148$2021'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:147$2020'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:145$2019'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:132$2018'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:131$2017'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:130$2016'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:129$2015'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:127$2014'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:126$2013'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:125$2012'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:124$2011'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:123$2010'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:121$2009'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:120$2008'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:119$2007'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:118$2006'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:117$2005'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:116$2004'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:112$2003'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:110$2002'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:109$2001'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:107$2000'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:104$1999'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:100$1998'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:91$1997'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:87$1996'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:80$1995'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:79$1994'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:78$1993'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:76$1992'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:75$1991'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:72$1990'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:71$1989'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:45$1988'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:43$1987'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:37$1986'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:36$1985'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:35$1984'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:34$1983'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6107$1927'.\n     1/3: $0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN[7:0]$1930\n     2/3: $0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_DATA[7:0]$1929\n     3/3: $0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_ADDR[8:0]$1928\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6097$1922'.\n     1/3: $0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN[7:0]$1925\n     2/3: $0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_DATA[7:0]$1924\n     3/3: $0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_ADDR[8:0]$1923\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6087$1917'.\n     1/3: $0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN[7:0]$1920\n     2/3: $0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_DATA[7:0]$1919\n     3/3: $0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_ADDR[8:0]$1918\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6077$1912'.\n     1/3: $0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN[7:0]$1915\n     2/3: $0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_DATA[7:0]$1914\n     3/3: $0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_ADDR[8:0]$1913\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6067$1907'.\n     1/3: $0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN[7:0]$1910\n     2/3: $0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_DATA[7:0]$1909\n     3/3: $0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_ADDR[8:0]$1908\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6057$1902'.\n     1/3: $0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN[7:0]$1905\n     2/3: $0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_DATA[7:0]$1904\n     3/3: $0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_ADDR[8:0]$1903\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6047$1897'.\n     1/3: $0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN[7:0]$1900\n     2/3: $0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_DATA[7:0]$1899\n     3/3: $0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_ADDR[8:0]$1898\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6037$1892'.\n     1/3: $0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN[7:0]$1895\n     2/3: $0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_DATA[7:0]$1894\n     3/3: $0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_ADDR[8:0]$1893\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6027$1887'.\n     1/3: $0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN[7:0]$1890\n     2/3: $0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_DATA[7:0]$1889\n     3/3: $0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_ADDR[8:0]$1888\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6017$1882'.\n     1/3: $0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN[7:0]$1885\n     2/3: $0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_DATA[7:0]$1884\n     3/3: $0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_ADDR[8:0]$1883\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6007$1877'.\n     1/3: $0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN[7:0]$1880\n     2/3: $0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_DATA[7:0]$1879\n     3/3: $0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_ADDR[8:0]$1878\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5997$1872'.\n     1/3: $0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN[7:0]$1875\n     2/3: $0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_DATA[7:0]$1874\n     3/3: $0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_ADDR[8:0]$1873\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5987$1867'.\n     1/3: $0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN[7:0]$1870\n     2/3: $0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_DATA[7:0]$1869\n     3/3: $0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_ADDR[8:0]$1868\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5977$1862'.\n     1/3: $0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN[7:0]$1865\n     2/3: $0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_DATA[7:0]$1864\n     3/3: $0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_ADDR[8:0]$1863\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5967$1857'.\n     1/3: $0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN[7:0]$1860\n     2/3: $0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_DATA[7:0]$1859\n     3/3: $0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_ADDR[8:0]$1858\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5957$1852'.\n     1/3: $0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN[7:0]$1855\n     2/3: $0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_DATA[7:0]$1854\n     3/3: $0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_ADDR[8:0]$1853\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5892$1846'.\n     1/3: $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849\n     2/3: $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_DATA[23:0]$1848\n     3/3: $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_ADDR[8:0]$1847\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1550$2491'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5878$1839'.\n     1/3: $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842\n     2/3: $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_DATA[24:0]$1841\n     3/3: $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_ADDR[2:0]$1840\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1546$2490'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5864$1832'.\n     1/3: $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835\n     2/3: $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_DATA[24:0]$1834\n     3/3: $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_ADDR[2:0]$1833\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1542$2489'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5850$1825'.\n     1/3: $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828\n     2/3: $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_DATA[24:0]$1827\n     3/3: $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_ADDR[2:0]$1826\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1538$2488'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5836$1818'.\n     1/3: $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821\n     2/3: $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_DATA[24:0]$1820\n     3/3: $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_ADDR[2:0]$1819\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5826$1816'.\n     1/1: $0\\memdat_4[9:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5820$1811'.\n     1/3: $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814\n     2/3: $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_DATA[9:0]$1813\n     3/3: $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_ADDR[3:0]$1812\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5809$1809'.\n     1/1: $0\\memdat_2[9:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5803$1804'.\n     1/3: $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807\n     2/3: $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_DATA[9:0]$1806\n     3/3: $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_ADDR[3:0]$1805\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5790$1802'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n     1/12: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN[31:0]$1791\n     2/12: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_DATA[31:0]$1790\n     3/12: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_ADDR[10:0]$1789\n     4/12: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN[31:0]$1794\n     5/12: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_DATA[31:0]$1793\n     6/12: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_ADDR[10:0]$1792\n     7/12: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797\n     8/12: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_DATA[31:0]$1796\n     9/12: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_ADDR[10:0]$1795\n    10/12: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN[31:0]$1800\n    11/12: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_DATA[31:0]$1799\n    12/12: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_ADDR[10:0]$1798\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5758$1786'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n     1/257: $0\\soclinux_storage[15:0] [15:8]\n     2/257: $0\\main_soclinux_rx_clkphase[31:0]\n     3/257: $0\\main_soclinux_tx_clkphase[31:0]\n     4/257: $0\\main_soclinux_cpu_time_cmp_storage[63:0] [63:56]\n     5/257: $0\\main_soclinux_storage[31:0] [15:8]\n     6/257: $0\\main_soclinux_storage[31:0] [23:16]\n     7/257: $0\\main_soclinux_timer_load_storage[31:0] [31:24]\n     8/257: $0\\main_soclinux_timer_reload_storage[31:0] [15:8]\n     9/257: $0\\main_soclinux_timer_reload_storage[31:0] [23:16]\n    10/257: $0\\main_soclinux_rx_clken[0:0]\n    11/257: $0\\main_soclinux_timer_load_storage[31:0] [15:8]\n    12/257: $0\\main_soclinux_timer_load_storage[31:0] [23:16]\n    13/257: $0\\soclinux_control_storage[15:0] [15:8]\n    14/257: $0\\main_wishbone_bridge_rdata_converter_converter_source_payload_data[127:0] [127:112]\n    15/257: $0\\main_sdram_wrdata_storage[15:0] [7:0]\n    16/257: $0\\main_sdram_address_storage[12:0] [7:0]\n    17/257: $0\\main_soclinux_storage[31:0] [7:0]\n    18/257: $0\\main_soclinux_soccontroller_scratch_storage[31:0] [15:8]\n    19/257: $0\\main_soclinux_soccontroller_scratch_storage[31:0] [23:16]\n    20/257: $0\\main_soclinux_soccontroller_scratch_storage[31:0] [31:24]\n    21/257: $0\\main_soclinux_cpu_time_cmp_storage[63:0] [15:8]\n    22/257: $0\\main_soclinux_cpu_time_cmp_storage[63:0] [23:16]\n    23/257: $0\\main_soclinux_cpu_time_cmp_storage[63:0] [31:24]\n    24/257: $0\\main_soclinux_cpu_time_cmp_storage[63:0] [39:32]\n    25/257: $0\\main_soclinux_cpu_time_cmp_storage[63:0] [47:40]\n    26/257: $0\\main_soclinux_cpu_time_cmp_storage[63:0] [55:48]\n    27/257: $0\\main_wishbone_bridge_rdata_converter_converter_source_payload_data[127:0] [95:80]\n    28/257: $0\\main_wishbone_bridge_rdata_converter_converter_source_payload_data[127:0] [79:64]\n    29/257: $0\\main_wishbone_bridge_rdata_converter_converter_source_payload_data[127:0] [63:48]\n    30/257: $0\\main_wishbone_bridge_rdata_converter_converter_source_payload_data[127:0] [47:32]\n    31/257: $0\\main_wishbone_bridge_rdata_converter_converter_source_payload_data[127:0] [31:16]\n    32/257: $0\\main_wishbone_bridge_rdata_converter_converter_source_payload_data[127:0] [15:0]\n    33/257: $0\\main_soclinux_timer_reload_storage[31:0] [31:24]\n    34/257: $0\\main_soclinux_timer_value[31:0]\n    35/257: $0\\main_soclinux_tx_clken[0:0]\n    36/257: $0\\main_soclinux_storage[31:0] [31:24]\n    37/257: $0\\main_soclinux_re[0:0]\n    38/257: $0\\builder_csr_bankarray_interface7_bank_bus_dat_r[7:0]\n    39/257: $0\\main_soclinux_uart_eventmanager_re[0:0]\n    40/257: $0\\builder_csr_bankarray_interface6_bank_bus_dat_r[7:0]\n    41/257: $0\\main_soclinux_timer_eventmanager_re[0:0]\n    42/257: $0\\main_soclinux_timer_update_value_re[0:0]\n    43/257: $0\\main_soclinux_timer_en_re[0:0]\n    44/257: $0\\main_soclinux_timer_reload_re[0:0]\n    45/257: $0\\main_soclinux_timer_load_re[0:0]\n    46/257: $0\\builder_csr_bankarray_interface5_bank_bus_dat_r[7:0]\n    47/257: $0\\soclinux_re[0:0]\n    48/257: $0\\soclinux_loopback_re[0:0]\n    49/257: $0\\soclinux_cs_re[0:0]\n    50/257: $0\\soclinux_mosi_re[0:0]\n    51/257: $0\\soclinux_control_re[0:0]\n    52/257: $0\\builder_csr_bankarray_interface4_bank_bus_dat_r[7:0]\n    53/257: $0\\main_sdram_wrdata_re[0:0]\n    54/257: $0\\main_sdram_baddress_re[0:0]\n    55/257: $0\\main_sdram_address_re[0:0]\n    56/257: $0\\main_sdram_command_re[0:0]\n    57/257: $0\\main_sdram_re[0:0]\n    58/257: $0\\builder_csr_bankarray_interface3_bank_bus_dat_r[7:0]\n    59/257: $0\\main_re[0:0]\n    60/257: $0\\builder_csr_bankarray_interface2_bank_bus_dat_r[7:0]\n    61/257: $0\\builder_csr_bankarray_sel_r[0:0]\n    62/257: $0\\main_soclinux_soccontroller_scratch_re[0:0]\n    63/257: $0\\main_soclinux_soccontroller_reset_re[0:0]\n    64/257: $0\\builder_csr_bankarray_interface1_bank_bus_dat_r[7:0]\n    65/257: $0\\main_soclinux_cpu_time_cmp_re[0:0]\n    66/257: $0\\builder_csr_bankarray_interface0_bank_bus_dat_r[7:0]\n    67/257: $0\\builder_slave_sel_r[3:0]\n    68/257: $0\\builder_state[1:0]\n    69/257: $0\\builder_spimaster_state[1:0]\n    70/257: $0\\spisdcard_cs_n[0:0]\n    71/257: $0\\soclinux_clk_divider1[15:0]\n    72/257: $0\\builder_litedramwishbone2native_state[0:0]\n    73/257: $0\\builder_fullmemorywe_state[1:0]\n    74/257: $0\\builder_new_master_rdata_valid3[0:0]\n    75/257: $0\\builder_new_master_rdata_valid2[0:0]\n    76/257: $0\\builder_new_master_rdata_valid1[0:0]\n    77/257: $0\\builder_new_master_rdata_valid0[0:0]\n    78/257: $0\\builder_new_master_wdata_ready[0:0]\n    79/257: $0\\builder_multiplexer_state[2:0]\n    80/257: $0\\main_sdram_dfi_p0_wrdata_en[0:0]\n    81/257: $0\\main_sdram_dfi_p0_rddata_en[0:0]\n    82/257: $0\\main_sdram_dfi_p0_we_n[0:0]\n    83/257: $0\\main_sdram_dfi_p0_ras_n[0:0]\n    84/257: $0\\main_sdram_dfi_p0_cas_n[0:0]\n    85/257: $0\\main_sdram_dfi_p0_address[12:0]\n    86/257: $0\\main_sdram_dfi_p0_bank[1:0]\n    87/257: $0\\main_sdram_dfi_p0_cs_n[0:0]\n    88/257: $0\\builder_bankmachine3_state[2:0]\n    89/257: $0\\builder_bankmachine2_state[2:0]\n    90/257: $0\\builder_bankmachine1_state[2:0]\n    91/257: $0\\builder_bankmachine0_state[2:0]\n    92/257: $0\\builder_refresher_state[1:0]\n    93/257: $0\\main_sdram_sequencer_done1[0:0]\n    94/257: $0\\main_sdram_cmd_payload_we[0:0]\n    95/257: $0\\main_sdram_cmd_payload_ras[0:0]\n    96/257: $0\\main_sdram_cmd_payload_cas[0:0]\n    97/257: $0\\main_sdram_cmd_payload_ba[1:0]\n    98/257: $0\\main_sdram_cmd_payload_a[12:0]\n    99/257: $0\\main_sdram_postponer_req_o[0:0]\n   100/257: $0\\main_dfi_p0_rddata_valid[0:0]\n   101/257: $0\\main_rddata_en[2:0]\n   102/257: $0\\main_soclinux_timer_zero_old_trigger[0:0]\n   103/257: $0\\main_soclinux_uart_rx_old_trigger[0:0]\n   104/257: $0\\main_soclinux_uart_tx_old_trigger[0:0]\n   105/257: $0\\main_soclinux_rx_r[0:0]\n   106/257: $0\\main_soclinux_source_valid[0:0]\n   107/257: $0\\main_soclinux_sink_ready[0:0]\n   108/257: $0\\main_soclinux_ram_bus_ram_bus_ack[0:0]\n   109/257: $0\\main_soclinux_soclinux_ram_bus_ack[0:0]\n   110/257: $0\\main_soclinux_cpu_time[63:0]\n   111/257: $0\\builder_count[19:0]\n   112/257: $0\\builder_grant[0:0]\n   113/257: $0\\builder_soclinux_dat_w[7:0]\n   114/257: $0\\builder_soclinux_we[0:0]\n   115/257: $0\\builder_soclinux_adr[13:0]\n   116/257: $0\\soclinux_control_storage[15:0] [7:0]\n   117/257: $0\\soclinux_miso_data[7:0]\n   118/257: $0\\soclinux_mosi_sel[2:0]\n   119/257: $0\\soclinux_mosi_data[7:0]\n   120/257: $0\\soclinux_count[2:0]\n   121/257: $0\\soclinux_loopback_storage[0:0]\n   122/257: $0\\soclinux_cs_storage[0:0]\n   123/257: $0\\soclinux_mosi_storage[7:0]\n   124/257: $0\\main_sdram_wrdata_storage[15:0] [15:8]\n   125/257: $0\\soclinux_miso[7:0]\n   126/257: $0\\main_count[21:0]\n   127/257: $0\\main_mode[0:0]\n   128/257: $0\\main_chaser[7:0]\n   129/257: $0\\main_storage[7:0]\n   130/257: $0\\main_wishbone_bridge_wdata_consumed[0:0]\n   131/257: $0\\main_wishbone_bridge_cmd_consumed[0:0]\n   132/257: $0\\main_wishbone_bridge_rdata_converter_converter_strobe_all[0:0]\n   133/257: $0\\main_wishbone_bridge_rdata_converter_converter_demux[2:0]\n   134/257: $0\\main_wishbone_bridge_rdata_converter_converter_source_payload_valid_token_count[3:0]\n   135/257: $0\\main_sdram_timer_count1[8:0]\n   136/257: $0\\main_wishbone_bridge_rdata_converter_converter_source_last[0:0]\n   137/257: $0\\main_wishbone_bridge_rdata_converter_converter_source_first[0:0]\n   138/257: $0\\main_wishbone_bridge_wdata_converter_converter_mux[2:0]\n   139/257: $0\\main_wishbone_bridge_count[2:0]\n   140/257: $0\\main_sdram_time1[3:0]\n   141/257: $0\\main_sdram_time0[4:0]\n   142/257: $0\\main_sdram_twtrcon_count[2:0]\n   143/257: $0\\main_sdram_twtrcon_ready[0:0]\n   144/257: $0\\main_sdram_tccdcon_count[0:0]\n   145/257: $0\\main_sdram_tccdcon_ready[0:0]\n   146/257: $0\\main_sdram_trrdcon_count[0:0]\n   147/257: $0\\main_sdram_trrdcon_ready[0:0]\n   148/257: $0\\main_sdram_choose_req_grant[1:0]\n   149/257: $0\\main_sdram_choose_cmd_grant[1:0]\n   150/257: $0\\main_sdram_bankmachine3_trascon_count[1:0]\n   151/257: $0\\main_sdram_bankmachine3_trascon_ready[0:0]\n   152/257: $0\\main_sdram_bankmachine3_trccon_count[1:0]\n   153/257: $0\\main_sdram_bankmachine3_trccon_ready[0:0]\n   154/257: $0\\main_sdram_bankmachine3_twtpcon_count[1:0]\n   155/257: $0\\main_sdram_bankmachine3_twtpcon_ready[0:0]\n   156/257: $0\\main_sdram_bankmachine3_row_opened[0:0]\n   157/257: $0\\main_sdram_bankmachine3_row[12:0]\n   158/257: $0\\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]\n   159/257: $0\\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0]\n   160/257: $0\\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]\n   161/257: $0\\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]\n   162/257: $0\\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0]\n   163/257: $0\\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]\n   164/257: $0\\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0]\n   165/257: $0\\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0]\n   166/257: $0\\main_sdram_bankmachine2_trascon_count[1:0]\n   167/257: $0\\main_sdram_bankmachine2_trascon_ready[0:0]\n   168/257: $0\\main_sdram_bankmachine2_trccon_count[1:0]\n   169/257: $0\\main_sdram_bankmachine2_trccon_ready[0:0]\n   170/257: $0\\main_sdram_bankmachine2_twtpcon_count[1:0]\n   171/257: $0\\main_sdram_bankmachine2_twtpcon_ready[0:0]\n   172/257: $0\\main_sdram_bankmachine2_row_opened[0:0]\n   173/257: $0\\main_sdram_bankmachine2_row[12:0]\n   174/257: $0\\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]\n   175/257: $0\\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]\n   176/257: $0\\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]\n   177/257: $0\\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]\n   178/257: $0\\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]\n   179/257: $0\\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]\n   180/257: $0\\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]\n   181/257: $0\\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]\n   182/257: $0\\main_sdram_bankmachine1_trascon_count[1:0]\n   183/257: $0\\main_sdram_bankmachine1_trascon_ready[0:0]\n   184/257: $0\\main_sdram_bankmachine1_trccon_count[1:0]\n   185/257: $0\\main_sdram_bankmachine1_trccon_ready[0:0]\n   186/257: $0\\main_sdram_bankmachine1_twtpcon_count[1:0]\n   187/257: $0\\main_sdram_bankmachine1_twtpcon_ready[0:0]\n   188/257: $0\\main_sdram_bankmachine1_row_opened[0:0]\n   189/257: $0\\main_sdram_bankmachine1_row[12:0]\n   190/257: $0\\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0]\n   191/257: $0\\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0]\n   192/257: $0\\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]\n   193/257: $0\\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]\n   194/257: $0\\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0]\n   195/257: $0\\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]\n   196/257: $0\\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]\n   197/257: $0\\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]\n   198/257: $0\\main_sdram_bankmachine0_trascon_count[1:0]\n   199/257: $0\\main_sdram_bankmachine0_trascon_ready[0:0]\n   200/257: $0\\main_sdram_bankmachine0_trccon_count[1:0]\n   201/257: $0\\main_sdram_bankmachine0_trccon_ready[0:0]\n   202/257: $0\\main_sdram_bankmachine0_twtpcon_count[1:0]\n   203/257: $0\\main_sdram_bankmachine0_twtpcon_ready[0:0]\n   204/257: $0\\main_sdram_bankmachine0_row_opened[0:0]\n   205/257: $0\\main_sdram_bankmachine0_row[12:0]\n   206/257: $0\\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]\n   207/257: $0\\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]\n   208/257: $0\\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]\n   209/257: $0\\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]\n   210/257: $0\\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]\n   211/257: $0\\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]\n   212/257: $0\\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]\n   213/257: $0\\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]\n   214/257: $0\\main_sdram_sequencer_count[0:0]\n   215/257: $0\\main_sdram_sequencer_counter[2:0]\n   216/257: $0\\main_sdram_postponer_count[0:0]\n   217/257: $0\\main_sdram_rddata_status[15:0]\n   218/257: $0\\main_sdram_address_storage[12:0] [12:8]\n   219/257: $0\\main_sdram_baddress_storage[1:0]\n   220/257: $0\\main_soclinux_soccontroller_scratch_storage[31:0] [7:0]\n   221/257: $0\\main_sdram_command_storage[5:0]\n   222/257: $0\\main_sdram_storage[3:0]\n   223/257: $0\\main_soclinux_timer_eventmanager_storage[0:0]\n   224/257: $0\\main_soclinux_timer_zero_pending[0:0]\n   225/257: $0\\main_soclinux_timer_value_status[31:0]\n   226/257: $0\\main_soclinux_timer_update_value_storage[0:0]\n   227/257: $0\\main_soclinux_timer_en_storage[0:0]\n   228/257: $0\\main_soclinux_timer_load_storage[31:0] [7:0]\n   229/257: $0\\soclinux_storage[15:0] [7:0]\n   230/257: $0\\main_soclinux_uart_rx_fifo_consume[3:0]\n   231/257: $0\\main_soclinux_uart_rx_fifo_produce[3:0]\n   232/257: $0\\main_soclinux_uart_rx_fifo_level0[4:0]\n   233/257: $0\\main_soclinux_uart_rx_fifo_readable[0:0]\n   234/257: $0\\main_soclinux_uart_tx_fifo_consume[3:0]\n   235/257: $0\\main_soclinux_uart_tx_fifo_produce[3:0]\n   236/257: $0\\main_soclinux_uart_tx_fifo_level0[4:0]\n   237/257: $0\\main_soclinux_uart_tx_fifo_readable[0:0]\n   238/257: $0\\main_soclinux_uart_eventmanager_storage[1:0]\n   239/257: $0\\main_soclinux_uart_rx_pending[0:0]\n   240/257: $0\\main_soclinux_uart_tx_pending[0:0]\n   241/257: $0\\main_soclinux_rx_busy[0:0]\n   242/257: $0\\main_soclinux_rx_bitcount[3:0]\n   243/257: $0\\main_soclinux_rx_reg[7:0]\n   244/257: $0\\main_soclinux_source_payload_data[7:0]\n   245/257: $0\\main_soclinux_tx_busy[0:0]\n   246/257: $0\\main_soclinux_tx_bitcount[3:0]\n   247/257: $0\\main_soclinux_tx_reg[7:0]\n   248/257: $0\\main_soclinux_timer_reload_storage[31:0] [7:0]\n   249/257: $0\\main_soclinux_cpu_time_cmp[63:0]\n   250/257: $0\\main_wishbone_bridge_rdata_converter_converter_source_payload_data[127:0] [111:96]\n   251/257: $0\\main_soclinux_cpu_time_status[63:0]\n   252/257: $0\\main_soclinux_soccontroller_bus_errors[31:0]\n   253/257: $0\\main_soclinux_cpu_time_cmp_storage[63:0] [7:0]\n   254/257: $0\\main_soclinux_soccontroller_reset_storage[0:0]\n   255/257: $0\\spisdcard_mosi[0:0]\n   256/257: $0\\spisdcard_clk[0:0]\n   257/257: $0\\serial_tx[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4177$1559'.\n     1/1: $0\\builder_sync_f_array_muxed[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4160$1552'.\n     1/1: $0\\builder_sync_rhs_array_muxed6[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4143$1545'.\n     1/1: $0\\builder_sync_rhs_array_muxed5[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4126$1538'.\n     1/1: $0\\builder_sync_rhs_array_muxed4[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4109$1531'.\n     1/1: $0\\builder_sync_rhs_array_muxed3[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4092$1524'.\n     1/1: $0\\builder_sync_rhs_array_muxed2[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523'.\n     1/1: $0\\builder_sync_rhs_array_muxed1[12:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4058$1522'.\n     1/1: $0\\builder_sync_rhs_array_muxed0[1:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4047$1521'.\n     1/1: $0\\builder_comb_rhs_array_muxed31[1:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4036$1520'.\n     1/1: $0\\builder_comb_rhs_array_muxed30[2:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4025$1519'.\n     1/1: $0\\builder_comb_rhs_array_muxed29[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4014$1518'.\n     1/1: $0\\builder_comb_rhs_array_muxed28[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4003$1517'.\n     1/1: $0\\builder_comb_rhs_array_muxed27[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3992$1516'.\n     1/1: $0\\builder_comb_rhs_array_muxed26[3:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515'.\n     1/1: $0\\builder_comb_rhs_array_muxed25[31:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514'.\n     1/1: $0\\builder_comb_rhs_array_muxed24[29:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3962$1500'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3954$1499'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3938$1484'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3930$1483'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3914$1468'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3906$1467'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3890$1452'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3882$1451'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3857$1449'.\n     1/1: $0\\builder_comb_t_array_muxed5[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3840$1448'.\n     1/1: $0\\builder_comb_t_array_muxed4[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3823$1447'.\n     1/1: $0\\builder_comb_t_array_muxed3[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3806$1446'.\n     1/1: $0\\builder_comb_rhs_array_muxed11[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3789$1445'.\n     1/1: $0\\builder_comb_rhs_array_muxed10[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3772$1444'.\n     1/1: $0\\builder_comb_rhs_array_muxed9[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3755$1443'.\n     1/1: $0\\builder_comb_rhs_array_muxed8[1:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442'.\n     1/1: $0\\builder_comb_rhs_array_muxed7[12:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3721$1441'.\n     1/1: $0\\builder_comb_rhs_array_muxed6[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3704$1440'.\n     1/1: $0\\builder_comb_t_array_muxed2[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3687$1439'.\n     1/1: $0\\builder_comb_t_array_muxed1[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3670$1438'.\n     1/1: $0\\builder_comb_t_array_muxed0[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3653$1437'.\n     1/1: $0\\builder_comb_rhs_array_muxed5[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3636$1436'.\n     1/1: $0\\builder_comb_rhs_array_muxed4[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3619$1435'.\n     1/1: $0\\builder_comb_rhs_array_muxed3[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3602$1434'.\n     1/1: $0\\builder_comb_rhs_array_muxed2[1:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433'.\n     1/1: $0\\builder_comb_rhs_array_muxed1[12:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3568$1432'.\n     1/1: $0\\builder_comb_rhs_array_muxed0[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3390$1217'.\n     1/1: $0\\soclinux_start1[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3304$1073'.\n     1/1: $0\\builder_csr_bankarray_sram_bus_dat_r[7:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876'.\n     1/3: $0\\builder_shared_dat_r[31:0]\n     2/3: $0\\builder_shared_ack[0:0]\n     3/3: $0\\builder_error[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3140$861'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849'.\n     1/9: $0\\builder_next_state[1:0]\n     2/9: $0\\builder_soclinux_we_next_value_ce2[0:0]\n     3/9: $0\\builder_soclinux_we_next_value2[0:0]\n     4/9: $0\\builder_soclinux_adr_next_value_ce1[0:0]\n     5/9: $0\\builder_soclinux_wishbone_ack[0:0]\n     6/9: $0\\builder_soclinux_adr_next_value1[13:0]\n     7/9: $0\\builder_soclinux_wishbone_dat_r[31:0]\n     8/9: $0\\builder_soclinux_dat_w_next_value_ce0[0:0]\n     9/9: $0\\builder_soclinux_dat_w_next_value0[7:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845'.\n     1/9: $0\\builder_spimaster_next_state[1:0]\n     2/9: $0\\soclinux_miso_latch[0:0]\n     3/9: $0\\soclinux_mosi_latch[0:0]\n     4/9: $0\\soclinux_done0[0:0]\n     5/9: $0\\soclinux_cs_enable[0:0]\n     6/9: $0\\soclinux_clk_enable[0:0]\n     7/9: $0\\soclinux_count_spimaster_next_value_ce[0:0]\n     8/9: $0\\soclinux_count_spimaster_next_value[2:0]\n     9/9: $0\\soclinux_irq[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3013$838'.\n     1/1: { $0\\user_led7[0:0] $0\\user_led6[0:0] $0\\user_led5[0:0] $0\\user_led4[0:0] $0\\user_led3[0:0] $0\\user_led2[0:0] $0\\user_led1[0:0] $0\\user_led0[0:0] }\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832'.\n     1/1: $0\\main_wishbone_bridge_wdata_converter_converter_source_payload_data[17:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821'.\n     1/7: $0\\builder_litedramwishbone2native_next_state[0:0]\n     2/7: $0\\main_wishbone_bridge_count_litedramwishbone2native_next_value_ce[0:0]\n     3/7: $0\\main_port_cmd_valid[0:0]\n     4/7: $0\\main_wishbone_bridge_count_litedramwishbone2native_next_value[2:0]\n     5/7: $0\\main_port_cmd_payload_addr[23:0]\n     6/7: $0\\main_port_cmd_payload_we[0:0]\n     7/7: $0\\main_wishbone_bridge_cmd_ready[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\n     1/10: $0\\builder_fullmemorywe_next_state[1:0]\n     2/10: $0\\main_tag_di_dirty[0:0]\n     3/10: $0\\main_wb_sdram_ack[0:0]\n     4/10: $0\\main_interface_we[0:0]\n     5/10: $0\\main_tag_port_we[0:0]\n     6/10: $0\\main_interface_stb[0:0]\n     7/10: $0\\main_interface_cyc[0:0]\n     8/10: $0\\main_write_from_slave[0:0]\n     9/10: $0\\main_word_inc[0:0]\n    10/10: $0\\main_word_clr[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794'.\n     1/1: $0\\main_wb_sdram_dat_r[31:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782'.\n     1/2: $0\\main_data_port_dat_w[127:0]\n     2/2: $0\\main_data_port_we[15:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781'.\n     1/2: $0\\main_sdram_interface_wdata_we[1:0]\n     2/2: $0\\main_sdram_interface_wdata[15:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\n     1/8: $0\\builder_multiplexer_next_state[2:0]\n     2/8: $0\\main_sdram_cmd_ready[0:0]\n     3/8: $0\\main_sdram_choose_req_want_writes[0:0]\n     4/8: $0\\main_sdram_choose_req_want_reads[0:0]\n     5/8: $0\\main_sdram_en0[0:0]\n     6/8: $0\\main_sdram_en1[0:0]\n     7/8: $0\\main_sdram_steerer_sel[1:0]\n     8/8: $0\\main_sdram_choose_req_cmd_ready[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2603$625'.\n     1/1: $0\\main_sdram_bankmachine3_cmd_ready[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2594$618'.\n     1/1: $0\\main_sdram_bankmachine2_cmd_ready[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2585$611'.\n     1/1: $0\\main_sdram_bankmachine1_cmd_ready[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2576$604'.\n     1/1: $0\\main_sdram_bankmachine0_cmd_ready[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2570$603'.\n     1/1: $0\\main_sdram_choose_req_cmd_payload_we[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2564$602'.\n     1/1: $0\\main_sdram_choose_req_cmd_payload_ras[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2558$601'.\n     1/1: $0\\main_sdram_choose_req_cmd_payload_cas[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2544$548'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2537$545'.\n     1/1: $0\\main_sdram_choose_cmd_cmd_payload_we[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2531$544'.\n     1/1: $0\\main_sdram_choose_cmd_cmd_payload_ras[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2525$543'.\n     1/1: $0\\main_sdram_choose_cmd_cmd_payload_cas[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2511$490'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\n     1/14: $0\\builder_bankmachine3_next_state[2:0]\n     2/14: $0\\main_sdram_bankmachine3_cmd_payload_is_write[0:0]\n     3/14: $0\\main_sdram_bankmachine3_cmd_payload_is_read[0:0]\n     4/14: $0\\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0]\n     5/14: $0\\main_sdram_bankmachine3_cmd_payload_we[0:0]\n     6/14: $0\\main_sdram_bankmachine3_cmd_payload_ras[0:0]\n     7/14: $0\\main_sdram_bankmachine3_cmd_payload_cas[0:0]\n     8/14: $0\\main_sdram_bankmachine3_row_col_n_addr_sel[0:0]\n     9/14: $0\\main_sdram_bankmachine3_row_close[0:0]\n    10/14: $0\\main_sdram_bankmachine3_row_open[0:0]\n    11/14: $0\\main_sdram_bankmachine3_cmd_valid[0:0]\n    12/14: $0\\main_sdram_bankmachine3_refresh_gnt[0:0]\n    13/14: $0\\main_sdram_bankmachine3_req_rdata_valid[0:0]\n    14/14: $0\\main_sdram_bankmachine3_req_wdata_ready[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2388$438'.\n     1/1: $0\\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2366$434'.\n     1/1: $0\\main_sdram_bankmachine3_auto_precharge[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425'.\n     1/1: $0\\main_sdram_bankmachine3_cmd_payload_a[12:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\n     1/14: $0\\builder_bankmachine2_next_state[2:0]\n     2/14: $0\\main_sdram_bankmachine2_cmd_payload_is_write[0:0]\n     3/14: $0\\main_sdram_bankmachine2_cmd_payload_is_read[0:0]\n     4/14: $0\\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]\n     5/14: $0\\main_sdram_bankmachine2_cmd_payload_we[0:0]\n     6/14: $0\\main_sdram_bankmachine2_cmd_payload_ras[0:0]\n     7/14: $0\\main_sdram_bankmachine2_cmd_payload_cas[0:0]\n     8/14: $0\\main_sdram_bankmachine2_row_close[0:0]\n     9/14: $0\\main_sdram_bankmachine2_row_open[0:0]\n    10/14: $0\\main_sdram_bankmachine2_row_col_n_addr_sel[0:0]\n    11/14: $0\\main_sdram_bankmachine2_cmd_valid[0:0]\n    12/14: $0\\main_sdram_bankmachine2_refresh_gnt[0:0]\n    13/14: $0\\main_sdram_bankmachine2_req_rdata_valid[0:0]\n    14/14: $0\\main_sdram_bankmachine2_req_wdata_ready[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2237$408'.\n     1/1: $0\\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2215$404'.\n     1/1: $0\\main_sdram_bankmachine2_auto_precharge[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395'.\n     1/1: $0\\main_sdram_bankmachine2_cmd_payload_a[12:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\n     1/14: $0\\builder_bankmachine1_next_state[2:0]\n     2/14: $0\\main_sdram_bankmachine1_cmd_payload_is_write[0:0]\n     3/14: $0\\main_sdram_bankmachine1_cmd_payload_is_read[0:0]\n     4/14: $0\\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]\n     5/14: $0\\main_sdram_bankmachine1_cmd_payload_we[0:0]\n     6/14: $0\\main_sdram_bankmachine1_cmd_payload_ras[0:0]\n     7/14: $0\\main_sdram_bankmachine1_cmd_payload_cas[0:0]\n     8/14: $0\\main_sdram_bankmachine1_row_close[0:0]\n     9/14: $0\\main_sdram_bankmachine1_row_open[0:0]\n    10/14: $0\\main_sdram_bankmachine1_cmd_valid[0:0]\n    11/14: $0\\main_sdram_bankmachine1_refresh_gnt[0:0]\n    12/14: $0\\main_sdram_bankmachine1_req_rdata_valid[0:0]\n    13/14: $0\\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]\n    14/14: $0\\main_sdram_bankmachine1_req_wdata_ready[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2086$378'.\n     1/1: $0\\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2064$374'.\n     1/1: $0\\main_sdram_bankmachine1_auto_precharge[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365'.\n     1/1: $0\\main_sdram_bankmachine1_cmd_payload_a[12:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\n     1/14: $0\\builder_bankmachine0_next_state[2:0]\n     2/14: $0\\main_sdram_bankmachine0_cmd_payload_is_write[0:0]\n     3/14: $0\\main_sdram_bankmachine0_cmd_payload_is_read[0:0]\n     4/14: $0\\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]\n     5/14: $0\\main_sdram_bankmachine0_cmd_payload_we[0:0]\n     6/14: $0\\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]\n     7/14: $0\\main_sdram_bankmachine0_cmd_payload_ras[0:0]\n     8/14: $0\\main_sdram_bankmachine0_cmd_payload_cas[0:0]\n     9/14: $0\\main_sdram_bankmachine0_row_close[0:0]\n    10/14: $0\\main_sdram_bankmachine0_row_open[0:0]\n    11/14: $0\\main_sdram_bankmachine0_cmd_valid[0:0]\n    12/14: $0\\main_sdram_bankmachine0_refresh_gnt[0:0]\n    13/14: $0\\main_sdram_bankmachine0_req_rdata_valid[0:0]\n    14/14: $0\\main_sdram_bankmachine0_req_wdata_ready[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1935$348'.\n     1/1: $0\\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1913$344'.\n     1/1: $0\\main_sdram_bankmachine0_auto_precharge[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335'.\n     1/1: $0\\main_sdram_bankmachine0_cmd_payload_a[12:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331'.\n     1/4: $0\\builder_refresher_next_state[1:0]\n     2/4: $0\\main_sdram_cmd_valid[0:0]\n     3/4: $0\\main_sdram_sequencer_start0[0:0]\n     4/4: $0\\main_sdram_cmd_last[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1798$318'.\n     1/4: $0\\main_sdram_inti_p0_ras_n[0:0]\n     2/4: $0\\main_sdram_inti_p0_cas_n[0:0]\n     3/4: $0\\main_sdram_inti_p0_we_n[0:0]\n     4/4: $0\\main_sdram_inti_p0_cs_n[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\n     1/18: $0\\main_sdram_master_p0_rddata_en[0:0]\n     2/18: $0\\main_sdram_master_p0_wrdata_mask[1:0]\n     3/18: $0\\main_sdram_master_p0_wrdata_en[0:0]\n     4/18: $0\\main_sdram_master_p0_wrdata[15:0]\n     5/18: $0\\main_sdram_master_p0_act_n[0:0]\n     6/18: $0\\main_sdram_master_p0_reset_n[0:0]\n     7/18: $0\\main_sdram_master_p0_odt[0:0]\n     8/18: $0\\main_sdram_master_p0_cke[0:0]\n     9/18: $0\\main_sdram_master_p0_we_n[0:0]\n    10/18: $0\\main_sdram_master_p0_ras_n[0:0]\n    11/18: $0\\main_sdram_master_p0_cs_n[0:0]\n    12/18: $0\\main_sdram_master_p0_cas_n[0:0]\n    13/18: $0\\main_sdram_master_p0_bank[1:0]\n    14/18: $0\\main_sdram_master_p0_address[12:0]\n    15/18: $0\\main_sdram_inti_p0_rddata_valid[0:0]\n    16/18: $0\\main_sdram_inti_p0_rddata[15:0]\n    17/18: $0\\main_sdram_slave_p0_rddata_valid[0:0]\n    18/18: $0\\main_sdram_slave_p0_rddata[15:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1694$313'.\n     1/1: $0\\main_soclinux_timer_zero_clear[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1676$305'.\n     1/1: $0\\main_soclinux_uart_rx_fifo_wrport_adr[3:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1646$294'.\n     1/1: $0\\main_soclinux_uart_tx_fifo_wrport_adr[3:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1624$286'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1618$284'.\n     1/1: $0\\main_soclinux_uart_rx_clear[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1613$283'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1607$281'.\n     1/1: $0\\main_soclinux_uart_tx_clear[0:0]\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1567$260'.\nCreating decoders for process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258'.\n\n4.5.7. Executing PROC_DLATCH pass (convert process syncs to latches).\nNo latch inferred for signal `\\InstructionCache.\\lineLoader_wayToAllocate_willIncrement' from process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:226$3860'.\nNo latch inferred for signal `\\InstructionCache.\\io_cpu_prefetch_haltIt' from process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:210$3855'.\nNo latch inferred for signal `\\InstructionCache.\\lineLoader_fire' from process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:201$3853'.\nNo latch inferred for signal `\\InstructionCache.\\_zz_2_' from process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:193$3852'.\nNo latch inferred for signal `\\InstructionCache.\\_zz_1_' from process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:186$3851'.\nNo latch inferred for signal `\\DataCache.\\loader_counter_valueNext' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1052$3797'.\nNo latch inferred for signal `\\DataCache.\\loader_counter_willIncrement' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1042$3794'.\nNo latch inferred for signal `\\DataCache.\\io_cpu_writeBack_data' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1030$3792'.\nNo latch inferred for signal `\\DataCache.\\io_mem_cmd_payload_wr' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1017$3789'.\nNo latch inferred for signal `\\DataCache.\\io_mem_cmd_payload_last' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1002$3788'.\nNo latch inferred for signal `\\DataCache.\\io_mem_cmd_payload_length' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:987$3787'.\nNo latch inferred for signal `\\DataCache.\\io_mem_cmd_payload_address' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:972$3786'.\nNo latch inferred for signal `\\DataCache.\\io_mem_cmd_valid' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:936$3783'.\nNo latch inferred for signal `\\DataCache.\\io_cpu_writeBack_accessError' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:924$3762'.\nNo latch inferred for signal `\\DataCache.\\io_cpu_redo' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:905$3759'.\nNo latch inferred for signal `\\DataCache.\\stageB_amo_result' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:885$3754'.\nNo latch inferred for signal `\\DataCache.\\stageB_requestDataBypass' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:873$3747'.\nNo latch inferred for signal `\\DataCache.\\io_cpu_flush_ready' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:866$3746'.\nNo latch inferred for signal `\\DataCache.\\io_cpu_writeBack_haltIt' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:832$3742'.\nNo latch inferred for signal `\\DataCache.\\stageB_loaderValid' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:816$3739'.\nNo latch inferred for signal `\\DataCache.\\stageB_mmuRspFreeze' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:806$3736'.\nNo latch inferred for signal `\\DataCache.\\_zz_6_' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:782$3717'.\nNo latch inferred for signal `\\DataCache.\\dataWriteCmd_payload_mask' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:768$3715'.\nNo latch inferred for signal `\\DataCache.\\dataWriteCmd_payload_data' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:754$3713'.\nNo latch inferred for signal `\\DataCache.\\dataWriteCmd_payload_address' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:740$3711'.\nNo latch inferred for signal `\\DataCache.\\dataWriteCmd_payload_way' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:726$3709'.\nNo latch inferred for signal `\\DataCache.\\dataWriteCmd_valid' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:699$3706'.\nNo latch inferred for signal `\\DataCache.\\tagsWriteCmd_payload_data_address' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:692$3705'.\nNo latch inferred for signal `\\DataCache.\\tagsWriteCmd_payload_data_error' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:685$3703'.\nNo latch inferred for signal `\\DataCache.\\tagsWriteCmd_payload_data_valid' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:675$3702'.\nNo latch inferred for signal `\\DataCache.\\tagsWriteCmd_payload_address' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:665$3701'.\nNo latch inferred for signal `\\DataCache.\\tagsWriteCmd_payload_way' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:655$3700'.\nNo latch inferred for signal `\\DataCache.\\tagsWriteCmd_valid' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:642$3699'.\nNo latch inferred for signal `\\DataCache.\\dataReadCmd_payload' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:635$3698'.\nNo latch inferred for signal `\\DataCache.\\dataReadCmd_valid' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:628$3697'.\nNo latch inferred for signal `\\DataCache.\\tagsReadCmd_payload' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:621$3696'.\nNo latch inferred for signal `\\DataCache.\\tagsReadCmd_valid' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:614$3695'.\nNo latch inferred for signal `\\DataCache.\\_zz_2_' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:599$3689'.\nNo latch inferred for signal `\\DataCache.\\_zz_1_' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:592$3687'.\nNo latch inferred for signal `\\DataCache.\\_zz_11_' from process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:565$3664'.\nNo latch inferred for signal `\\VexRiscv.\\iBusWishbone_STB' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6677$3408'.\nNo latch inferred for signal `\\VexRiscv.\\iBusWishbone_CYC' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6670$3407'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_225_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6608$3346'.\nNo latch inferred for signal `\\VexRiscv.\\memory_DivPlugin_div_counter_valueNext' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6591$3338'.\nNo latch inferred for signal `\\VexRiscv.\\memory_DivPlugin_div_counter_willClear' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6582$3335'.\nNo latch inferred for signal `\\VexRiscv.\\memory_DivPlugin_div_counter_willIncrement' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6573$3334'.\nNo latch inferred for signal `\\VexRiscv.\\execute_MulPlugin_bSigned' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6547$3325'.\nNo latch inferred for signal `\\VexRiscv.\\execute_MulPlugin_aSigned' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6533$3324'.\nNo latch inferred for signal `\\VexRiscv.\\execute_CsrPlugin_writeData' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6519$3319'.\nNo latch inferred for signal `\\VexRiscv.\\execute_CsrPlugin_readToWriteData' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6505$3318'.\nNo latch inferred for signal `\\VexRiscv.\\execute_CsrPlugin_readData' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6381$3305'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_selfException_payload_code' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6360$3304'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_selfException_valid' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6350$3303'.\nNo latch inferred for signal `\\VexRiscv.\\execute_CsrPlugin_illegalInstruction' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6341$3299'.\nNo latch inferred for signal `\\VexRiscv.\\execute_CsrPlugin_illegalAccess' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6219$3294'.\nNo latch inferred for signal `\\VexRiscv.\\execute_CsrPlugin_inWfi' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6211$3292'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_xtvec_base' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6194$3282'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_xtvec_mode' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6180$3281'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_trapCause' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6173$3280'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_targetPrivilege' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6166$3279'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_pipelineLiberator_done' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6155$3272'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6140$3270'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_exceptionPortCtrl_exceptionValids_memory' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6130$3269'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_exceptionPortCtrl_exceptionValids_execute' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6120$3268'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_exceptionPortCtrl_exceptionValids_decode' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6110$3267'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6039$3240'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_privilege' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6023$3232'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_209_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5993$3226'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_207_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5978$3225'.\nNo latch inferred for signal `\\VexRiscv.\\execute_BranchPlugin_branch_src2' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5963$3222'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_205_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5940$3221'.\nNo latch inferred for signal `\\VexRiscv.\\execute_BranchPlugin_branch_src1' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5928$3220'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_203_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5912$3215'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_202_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5890$3214'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_200_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5875$3213'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_198_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5851$3212'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_196_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5832$3211'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_195_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5820$3204'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_183_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5782$3194'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_182_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5754$3192'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_181_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5719$3191'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_180_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5682$3188'.\nNo latch inferred for signal `\\VexRiscv.\\execute_SrcPlugin_addSub' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5670$3184'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_179_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5652$3183'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_178_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5629$3182'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_176_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5605$3181'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_174_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5586$3180'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_173_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5570$3177'.\nNo latch inferred for signal `\\VexRiscv.\\execute_IntAluPlugin_bitwise' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5556$3173'.\nNo latch inferred for signal `\\VexRiscv.\\lastStageRegFileWrite_valid' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5547$3171'.\nNo latch inferred for signal `\\VexRiscv.\\MmuPlugin_dBusAccess_cmd_payload_address' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5474$3133'.\nNo latch inferred for signal `\\VexRiscv.\\MmuPlugin_dBusAccess_cmd_valid' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5454$3132'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_mmuBus_rsp_refilling' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5432$3119'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_mmuBus_rsp_exception' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5424$3108'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_mmuBus_rsp_allowExecute' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5416$3107'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_mmuBus_rsp_allowWrite' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5408$3106'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_mmuBus_rsp_allowRead' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5400$3103'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_mmuBus_rsp_physicalAddress' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5392$3101'.\nNo latch inferred for signal `\\VexRiscv.\\MmuPlugin_ports_1_requireMmuLockup' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5382$3093'.\nNo latch inferred for signal `\\VexRiscv.\\MmuPlugin_ports_1_entryToReplace_valueNext' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5375$3091'.\nNo latch inferred for signal `\\VexRiscv.\\MmuPlugin_ports_1_entryToReplace_willIncrement' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5363$3088'.\nNo latch inferred for signal `\\VexRiscv.\\DBusCachedPlugin_mmuBus_rsp_refilling' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5335$3058'.\nNo latch inferred for signal `\\VexRiscv.\\DBusCachedPlugin_mmuBus_rsp_exception' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5327$3047'.\nNo latch inferred for signal `\\VexRiscv.\\DBusCachedPlugin_mmuBus_rsp_allowExecute' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5319$3046'.\nNo latch inferred for signal `\\VexRiscv.\\DBusCachedPlugin_mmuBus_rsp_allowWrite' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5311$3045'.\nNo latch inferred for signal `\\VexRiscv.\\DBusCachedPlugin_mmuBus_rsp_allowRead' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5303$3042'.\nNo latch inferred for signal `\\VexRiscv.\\DBusCachedPlugin_mmuBus_rsp_physicalAddress' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5295$3040'.\nNo latch inferred for signal `\\VexRiscv.\\MmuPlugin_ports_0_requireMmuLockup' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5283$3029'.\nNo latch inferred for signal `\\VexRiscv.\\MmuPlugin_ports_0_entryToReplace_valueNext' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5276$3027'.\nNo latch inferred for signal `\\VexRiscv.\\MmuPlugin_ports_0_entryToReplace_willIncrement' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5264$3024'.\nNo latch inferred for signal `\\VexRiscv.\\DBusCachedPlugin_forceDatapath' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5231$2993'.\nNo latch inferred for signal `\\VexRiscv.\\MmuPlugin_dBusAccess_cmd_ready' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5220$2991'.\nNo latch inferred for signal `\\VexRiscv.\\writeBack_DBusCachedPlugin_rspFormated' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5206$2990'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_151_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5186$2989'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_149_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5157$2986'.\nNo latch inferred for signal `\\VexRiscv.\\writeBack_DBusCachedPlugin_rspShifted' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5139$2983'.\nNo latch inferred for signal `\\VexRiscv.\\DBusCachedPlugin_exceptionBus_payload_code' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5124$2981'.\nNo latch inferred for signal `\\VexRiscv.\\DBusCachedPlugin_exceptionBus_valid' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5105$2980'.\nNo latch inferred for signal `\\VexRiscv.\\DBusCachedPlugin_redoBranch_valid' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5095$2979'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_260_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5086$2976'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_259_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5078$2973'.\nNo latch inferred for signal `\\VexRiscv.\\DBusCachedPlugin_mmuBus_cmd_bypassTranslation' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5071$2972'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_257_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5061$2970'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_254_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5049$2969'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_253_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5037$2968'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_252_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5027$2966'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_251_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5018$2965'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_147_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5004$2964'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_250_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4995$2963'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_249_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4986$2962'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_248_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4975$2960'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_decodeExceptionPort_payload_code' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4928$2947'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_decodeExceptionPort_valid' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4918$2946'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_247_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4908$2943'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_rsp_redoFetch' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4895$2942'.\nNo latch inferred for signal `\\VexRiscv.\\iBus_cmd_payload_address' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4879$2931'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_130_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4855$2927'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_128_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4840$2926'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_126_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4827$2924'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_125_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4805$2923'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_123_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4790$2922'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_decodePrediction_cmd_hadBranch' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4782$2917'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_121_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4760$2916'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_iBusRsp_readyForError' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4743$2910'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4723$2899'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_iBusRsp_stages_1_halt' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4712$2895'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_iBusRsp_stages_0_halt' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4701$2891'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_fetchPc_pc' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4686$2887'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_fetchPc_pcRegPropagate' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4679$2886'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_fetchPc_corrected' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4672$2885'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_jumpInterface_payload' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4642$2879'.\nNo latch inferred for signal `\\VexRiscv.\\CsrPlugin_jumpInterface_valid' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4632$2878'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_incomingInstruction' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4625$2876'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_fetcherflushIt' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4615$2873'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_fetcherHalt' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4602$2871'.\nNo latch inferred for signal `\\VexRiscv.\\writeBack_arbitration_flushNext' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4582$2870'.\nNo latch inferred for signal `\\VexRiscv.\\writeBack_arbitration_flushIt' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4575$2869'.\nNo latch inferred for signal `\\VexRiscv.\\writeBack_arbitration_removeIt' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4565$2868'.\nNo latch inferred for signal `\\VexRiscv.\\writeBack_arbitration_haltItself' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4557$2867'.\nNo latch inferred for signal `\\VexRiscv.\\memory_arbitration_flushNext' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4547$2866'.\nNo latch inferred for signal `\\VexRiscv.\\memory_arbitration_removeIt' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4536$2865'.\nNo latch inferred for signal `\\VexRiscv.\\memory_arbitration_haltItself' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4526$2864'.\nNo latch inferred for signal `\\VexRiscv.\\execute_arbitration_flushNext' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4519$2863'.\nNo latch inferred for signal `\\VexRiscv.\\execute_arbitration_removeIt' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4508$2862'.\nNo latch inferred for signal `\\VexRiscv.\\execute_arbitration_haltItself' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4487$2856'.\nNo latch inferred for signal `\\VexRiscv.\\decode_arbitration_flushNext' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4477$2855'.\nNo latch inferred for signal `\\VexRiscv.\\decode_arbitration_removeIt' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4466$2854'.\nNo latch inferred for signal `\\VexRiscv.\\decode_arbitration_haltByOther' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4450$2843'.\nNo latch inferred for signal `\\VexRiscv.\\decode_arbitration_haltItself' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4443$2840'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_101_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4430$2839'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_100_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4423$2838'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_97_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4414$2837'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_96_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4407$2836'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_95_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4400$2835'.\nNo latch inferred for signal `\\VexRiscv.\\IBusCachedPlugin_rsp_issueDetected' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4393$2834'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_93_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4360$2831'.\nNo latch inferred for signal `\\VexRiscv.\\decode_REGFILE_WRITE_VALID' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4348$2829'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_61_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4340$2828'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_43_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4303$2827'.\nNo latch inferred for signal `\\VexRiscv.\\decode_RS1' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4272$2825'.\nNo latch inferred for signal `\\VexRiscv.\\decode_RS2' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4242$2823'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_42_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4226$2822'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_279_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_280_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_281_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_282_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_283_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_284_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_285_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_286_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_287_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_288_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_289_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_268_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_269_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_270_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_271_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_272_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_273_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_274_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_275_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_276_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_277_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_278_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nNo latch inferred for signal `\\VexRiscv.\\_zz_267_' from process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3313$2819'.\nNo latch inferred for signal `\\top.\\builder_soclinux_wishbone_err' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1086$2402'.\nNo latch inferred for signal `\\top.\\builder_locked3' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1056$2381'.\nNo latch inferred for signal `\\top.\\builder_locked2' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1055$2380'.\nNo latch inferred for signal `\\top.\\builder_locked1' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1054$2379'.\nNo latch inferred for signal `\\top.\\builder_locked0' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1053$2378'.\nNo latch inferred for signal `\\top.\\main_wishbone_bridge_wdata_last' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:908$2324'.\nNo latch inferred for signal `\\top.\\main_wishbone_bridge_wdata_first' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:907$2323'.\nNo latch inferred for signal `\\top.\\main_wb_sdram_err' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:874$2310'.\nNo latch inferred for signal `\\top.\\main_port_rdata_last' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:862$2307'.\nNo latch inferred for signal `\\top.\\main_port_rdata_first' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:861$2306'.\nNo latch inferred for signal `\\top.\\main_sdram_tfawcon_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:833$2294'.\nNo latch inferred for signal `\\top.\\main_sdram_steerer1' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:828$2291'.\nNo latch inferred for signal `\\top.\\main_sdram_steerer0' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:827$2290'.\nNo latch inferred for signal `\\top.\\main_sdram_nop_ba' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:825$2288'.\nNo latch inferred for signal `\\top.\\main_sdram_nop_a' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:824$2287'.\nNo latch inferred for signal `\\top.\\main_sdram_choose_cmd_cmd_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:793$2272'.\nNo latch inferred for signal `\\top.\\main_sdram_choose_cmd_want_activates' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:791$2271'.\nNo latch inferred for signal `\\top.\\main_sdram_choose_cmd_want_cmds' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:790$2270'.\nNo latch inferred for signal `\\top.\\main_sdram_choose_cmd_want_writes' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:789$2269'.\nNo latch inferred for signal `\\top.\\main_sdram_choose_cmd_want_reads' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:788$2268'.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_buffer_lookahead_replace' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:741$2248'.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:725$2246'.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:724$2245'.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_buffer_lookahead_replace' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:657$2212'.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:641$2210'.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:640$2209'.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_buffer_lookahead_replace' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:573$2176'.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:557$2174'.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:556$2173'.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_buffer_lookahead_replace' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:489$2140'.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:473$2138'.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:472$2137'.\nNo latch inferred for signal `\\top.\\main_sdram_cmd_payload_is_write' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:434$2116'.\nNo latch inferred for signal `\\top.\\main_sdram_cmd_payload_is_read' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:433$2115'.\nNo latch inferred for signal `\\top.\\main_sdram_dfi_p0_act_n' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:418$2104'.\nNo latch inferred for signal `\\top.\\main_sdram_command_issue_w' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:368$2088'.\nNo latch inferred for signal `\\top.\\main_sdram_inti_p0_act_n' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:318$2065'.\nNo latch inferred for signal `\\top.\\main_soclinux_uart_reset' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:254$2043'.\nNo latch inferred for signal `\\top.\\main_soclinux_uart_rx_fifo_replace' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:236$2039'.\nNo latch inferred for signal `\\top.\\main_soclinux_uart_tx_fifo_replace' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:199$2033'.\nNo latch inferred for signal `\\top.\\main_soclinux_uart_tx_fifo_sink_last' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:183$2030'.\nNo latch inferred for signal `\\top.\\main_soclinux_uart_tx_fifo_sink_first' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:182$2029'.\nNo latch inferred for signal `\\top.\\main_soclinux_source_last' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:124$2011'.\nNo latch inferred for signal `\\top.\\main_soclinux_source_first' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:123$2010'.\nNo latch inferred for signal `\\top.\\main_soclinux_ram_bus_ram_bus_err' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:104$1999'.\nNo latch inferred for signal `\\top.\\main_soclinux_soclinux_ram_bus_err' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:91$1997'.\nNo latch inferred for signal `\\top.\\main_soclinux_vexriscv' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:80$1995'.\nNo latch inferred for signal `\\top.\\main_soclinux_cpu_latch_w' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:71$1989'.\nNo latch inferred for signal `\\top.\\builder_sync_f_array_muxed' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4177$1559'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_f_array_muxed` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4177$1559`.\nNo latch inferred for signal `\\top.\\builder_sync_rhs_array_muxed6' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4160$1552'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed6` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4160$1552`.\nNo latch inferred for signal `\\top.\\builder_sync_rhs_array_muxed5' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4143$1545'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed5` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4143$1545`.\nNo latch inferred for signal `\\top.\\builder_sync_rhs_array_muxed4' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4126$1538'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed4` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4126$1538`.\nNo latch inferred for signal `\\top.\\builder_sync_rhs_array_muxed3' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4109$1531'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed3` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4109$1531`.\nNo latch inferred for signal `\\top.\\builder_sync_rhs_array_muxed2' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4092$1524'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed2` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4092$1524`.\nNo latch inferred for signal `\\top.\\builder_sync_rhs_array_muxed1' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed1 [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523`.\nNo latch inferred for signal `\\top.\\builder_sync_rhs_array_muxed0' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4058$1522'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed0 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4058$1522`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_sync_rhs_array_muxed0 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4058$1522`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed31' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4047$1521'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed31 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4047$1521`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed31 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4047$1521`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed30' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4036$1520'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed30 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4036$1520`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed30 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4036$1520`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed30 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4036$1520`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed29' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4025$1519'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed29` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4025$1519`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed28' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4014$1518'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed28` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4014$1518`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed27' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4003$1517'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed27` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4003$1517`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed26' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3992$1516'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed26 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3992$1516`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed26 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3992$1516`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed26 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3992$1516`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed26 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3992$1516`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed25' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [22]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [23]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [24]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [25]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [26]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [27]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [28]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [29]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [30]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed25 [31]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed24' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [22]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [23]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [24]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [25]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [26]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [27]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [28]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed24 [29]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed23' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3962$1500'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed23` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3962$1500`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed22' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3954$1499'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed22` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3954$1499`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed21' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed21 [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed20' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3938$1484'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed20` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3938$1484`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed19' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3930$1483'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed19` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3930$1483`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed18' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed18 [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed17' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3914$1468'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed17` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3914$1468`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed16' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3906$1467'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed16` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3906$1467`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed15' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed15 [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed14' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3890$1452'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed14` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3890$1452`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed13' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3882$1451'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed13` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3882$1451`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed12' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed12 [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450`.\nNo latch inferred for signal `\\top.\\builder_comb_t_array_muxed5' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3857$1449'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_t_array_muxed5` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3857$1449`.\nNo latch inferred for signal `\\top.\\builder_comb_t_array_muxed4' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3840$1448'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_t_array_muxed4` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3840$1448`.\nNo latch inferred for signal `\\top.\\builder_comb_t_array_muxed3' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3823$1447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_t_array_muxed3` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3823$1447`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed11' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3806$1446'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed11` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3806$1446`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed10' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3789$1445'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed10` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3789$1445`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed9' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3772$1444'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed9` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3772$1444`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed8' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3755$1443'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed8 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3755$1443`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed8 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3755$1443`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed7' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed7 [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed6' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3721$1441'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed6` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3721$1441`.\nNo latch inferred for signal `\\top.\\builder_comb_t_array_muxed2' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3704$1440'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_t_array_muxed2` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3704$1440`.\nNo latch inferred for signal `\\top.\\builder_comb_t_array_muxed1' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3687$1439'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_t_array_muxed1` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3687$1439`.\nNo latch inferred for signal `\\top.\\builder_comb_t_array_muxed0' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3670$1438'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_t_array_muxed0` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3670$1438`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed5' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3653$1437'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed5` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3653$1437`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed4' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3636$1436'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed4` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3636$1436`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed3' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3619$1435'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed3` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3619$1435`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed2' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3602$1434'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed2 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3602$1434`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed2 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3602$1434`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed1' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed1 [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433`.\nNo latch inferred for signal `\\top.\\builder_comb_rhs_array_muxed0' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3568$1432'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_comb_rhs_array_muxed0` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3568$1432`.\nNo latch inferred for signal `\\top.\\soclinux_start1' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3390$1217'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\soclinux_start1` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3390$1217`.\nNo latch inferred for signal `\\top.\\builder_csr_bankarray_sram_bus_dat_r' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3304$1073'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_csr_bankarray_sram_bus_dat_r [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3304$1073`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_csr_bankarray_sram_bus_dat_r [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3304$1073`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_csr_bankarray_sram_bus_dat_r [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3304$1073`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_csr_bankarray_sram_bus_dat_r [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3304$1073`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_csr_bankarray_sram_bus_dat_r [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3304$1073`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_csr_bankarray_sram_bus_dat_r [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3304$1073`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_csr_bankarray_sram_bus_dat_r [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3304$1073`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_csr_bankarray_sram_bus_dat_r [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3304$1073`.\nNo latch inferred for signal `\\top.\\builder_shared_dat_r' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [22]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [23]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [24]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [25]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [26]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [27]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [28]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [29]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [30]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_dat_r [31]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nNo latch inferred for signal `\\top.\\builder_shared_ack' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_shared_ack` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nNo latch inferred for signal `\\top.\\builder_error' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_error` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876`.\nNo latch inferred for signal `\\top.\\builder_slave_sel' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3140$861'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_slave_sel [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3140$861`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_slave_sel [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3140$861`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_slave_sel [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3140$861`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_slave_sel [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3140$861`.\nNo latch inferred for signal `\\top.\\builder_soclinux_wishbone_dat_r' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [22]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [23]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [24]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [25]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [26]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [27]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [28]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [29]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [30]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_dat_r [31]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nNo latch inferred for signal `\\top.\\builder_soclinux_wishbone_ack' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_wishbone_ack` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nNo latch inferred for signal `\\top.\\builder_next_state' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_next_state [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_next_state [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nNo latch inferred for signal `\\top.\\builder_soclinux_dat_w_next_value0' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_dat_w_next_value0 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_dat_w_next_value0 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_dat_w_next_value0 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_dat_w_next_value0 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_dat_w_next_value0 [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_dat_w_next_value0 [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_dat_w_next_value0 [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_dat_w_next_value0 [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nNo latch inferred for signal `\\top.\\builder_soclinux_dat_w_next_value_ce0' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_dat_w_next_value_ce0` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nNo latch inferred for signal `\\top.\\builder_soclinux_adr_next_value1' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value1 [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nNo latch inferred for signal `\\top.\\builder_soclinux_adr_next_value_ce1' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_adr_next_value_ce1` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nNo latch inferred for signal `\\top.\\builder_soclinux_we_next_value2' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_we_next_value2` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nNo latch inferred for signal `\\top.\\builder_soclinux_we_next_value_ce2' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_soclinux_we_next_value_ce2` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849`.\nNo latch inferred for signal `\\top.\\soclinux_done0' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\soclinux_done0` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845`.\nNo latch inferred for signal `\\top.\\soclinux_irq' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\soclinux_irq` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845`.\nNo latch inferred for signal `\\top.\\soclinux_clk_enable' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\soclinux_clk_enable` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845`.\nNo latch inferred for signal `\\top.\\soclinux_cs_enable' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\soclinux_cs_enable` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845`.\nNo latch inferred for signal `\\top.\\soclinux_mosi_latch' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\soclinux_mosi_latch` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845`.\nNo latch inferred for signal `\\top.\\soclinux_miso_latch' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\soclinux_miso_latch` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845`.\nNo latch inferred for signal `\\top.\\builder_spimaster_next_state' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_spimaster_next_state [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_spimaster_next_state [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845`.\nNo latch inferred for signal `\\top.\\soclinux_count_spimaster_next_value' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\soclinux_count_spimaster_next_value [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\soclinux_count_spimaster_next_value [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\soclinux_count_spimaster_next_value [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845`.\nNo latch inferred for signal `\\top.\\soclinux_count_spimaster_next_value_ce' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\soclinux_count_spimaster_next_value_ce` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845`.\nNo latch inferred for signal `\\top.\\user_led0' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3013$838'.\nNo latch inferred for signal `\\top.\\user_led1' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3013$838'.\nNo latch inferred for signal `\\top.\\user_led2' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3013$838'.\nNo latch inferred for signal `\\top.\\user_led3' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3013$838'.\nNo latch inferred for signal `\\top.\\user_led4' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3013$838'.\nNo latch inferred for signal `\\top.\\user_led5' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3013$838'.\nNo latch inferred for signal `\\top.\\user_led6' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3013$838'.\nNo latch inferred for signal `\\top.\\user_led7' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3013$838'.\nNo latch inferred for signal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [22]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [23]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [24]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [25]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [26]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [27]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [28]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [29]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [30]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [31]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [32]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [33]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [34]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [35]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [36]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [37]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [38]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [39]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [40]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [41]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [42]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [43]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [44]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [45]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [46]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [47]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [48]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [49]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [50]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [51]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [52]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [53]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [54]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [55]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [56]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [57]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [58]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [59]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [60]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [61]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [62]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [63]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [64]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [65]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [66]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [67]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [68]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [69]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [70]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [71]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [72]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [73]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [74]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [75]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [76]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [77]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [78]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [79]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [80]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [81]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [82]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [83]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [84]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [85]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [86]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [87]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [88]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [89]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [90]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [91]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [92]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [93]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [94]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [95]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [96]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [97]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [98]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [99]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [100]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [101]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [102]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [103]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [104]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [105]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [106]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [107]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [108]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [109]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [110]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [111]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [112]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [113]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [114]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [115]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [116]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [117]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [118]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [119]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [120]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [121]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [122]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [123]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [124]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [125]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [126]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_rdata_converter_source_payload_data [127]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833`.\nNo latch inferred for signal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_source_payload_data [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832`.\nNo latch inferred for signal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [22]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [23]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [24]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [25]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [26]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [27]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [28]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [29]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [30]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [31]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [32]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [33]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [34]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [35]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [36]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [37]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [38]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [39]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [40]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [41]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [42]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [43]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [44]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [45]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [46]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [47]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [48]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [49]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [50]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [51]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [52]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [53]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [54]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [55]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [56]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [57]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [58]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [59]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [60]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [61]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [62]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [63]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [64]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [65]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [66]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [67]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [68]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [69]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [70]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [71]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [72]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [73]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [74]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [75]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [76]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [77]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [78]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [79]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [80]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [81]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [82]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [83]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [84]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [85]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [86]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [87]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [88]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [89]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [90]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [91]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [92]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [93]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [94]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [95]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [96]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [97]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [98]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [99]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [100]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [101]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [102]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [103]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [104]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [105]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [106]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [107]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [108]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [109]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [110]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [111]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [112]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [113]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [114]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [115]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [116]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [117]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [118]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [119]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [120]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [121]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [122]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [123]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [124]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [125]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [126]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [127]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [128]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [129]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [130]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [131]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [132]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [133]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [134]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [135]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [136]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [137]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [138]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [139]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [140]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [141]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [142]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_wdata_converter_converter_sink_payload_data [143]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826`.\nNo latch inferred for signal `\\top.\\main_port_cmd_valid' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_valid` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nNo latch inferred for signal `\\top.\\main_port_cmd_payload_we' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_we` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nNo latch inferred for signal `\\top.\\main_port_cmd_payload_addr' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [22]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_port_cmd_payload_addr [23]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nNo latch inferred for signal `\\top.\\main_wishbone_bridge_cmd_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_cmd_ready` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nNo latch inferred for signal `\\top.\\builder_litedramwishbone2native_next_state' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_litedramwishbone2native_next_state` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nNo latch inferred for signal `\\top.\\main_wishbone_bridge_count_litedramwishbone2native_next_value' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_count_litedramwishbone2native_next_value [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_count_litedramwishbone2native_next_value [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_count_litedramwishbone2native_next_value [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nNo latch inferred for signal `\\top.\\main_wishbone_bridge_count_litedramwishbone2native_next_value_ce' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wishbone_bridge_count_litedramwishbone2native_next_value_ce` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821`.\nNo latch inferred for signal `\\top.\\main_wb_sdram_ack' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_ack` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795`.\nNo latch inferred for signal `\\top.\\main_interface_cyc' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_interface_cyc` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795`.\nNo latch inferred for signal `\\top.\\main_interface_stb' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_interface_stb` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795`.\nNo latch inferred for signal `\\top.\\main_interface_we' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_interface_we` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795`.\nNo latch inferred for signal `\\top.\\main_write_from_slave' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_write_from_slave` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795`.\nNo latch inferred for signal `\\top.\\main_tag_port_we' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_tag_port_we` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795`.\nNo latch inferred for signal `\\top.\\main_tag_di_dirty' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_tag_di_dirty` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795`.\nNo latch inferred for signal `\\top.\\main_word_clr' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_word_clr` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795`.\nNo latch inferred for signal `\\top.\\main_word_inc' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_word_inc` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795`.\nNo latch inferred for signal `\\top.\\builder_fullmemorywe_next_state' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_fullmemorywe_next_state [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_fullmemorywe_next_state [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795`.\nNo latch inferred for signal `\\top.\\main_wb_sdram_dat_r' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [22]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [23]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [24]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [25]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [26]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [27]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [28]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [29]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [30]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_wb_sdram_dat_r [31]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794`.\nNo latch inferred for signal `\\top.\\main_data_port_we' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_we [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nNo latch inferred for signal `\\top.\\main_data_port_dat_w' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [22]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [23]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [24]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [25]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [26]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [27]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [28]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [29]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [30]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [31]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [32]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [33]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [34]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [35]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [36]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [37]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [38]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [39]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [40]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [41]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [42]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [43]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [44]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [45]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [46]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [47]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [48]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [49]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [50]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [51]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [52]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [53]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [54]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [55]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [56]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [57]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [58]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [59]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [60]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [61]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [62]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [63]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [64]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [65]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [66]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [67]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [68]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [69]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [70]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [71]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [72]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [73]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [74]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [75]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [76]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [77]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [78]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [79]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [80]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [81]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [82]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [83]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [84]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [85]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [86]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [87]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [88]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [89]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [90]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [91]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [92]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [93]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [94]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [95]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [96]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [97]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [98]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [99]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [100]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [101]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [102]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [103]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [104]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [105]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [106]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [107]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [108]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [109]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [110]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [111]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [112]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [113]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [114]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [115]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [116]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [117]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [118]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [119]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [120]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [121]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [122]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [123]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [124]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [125]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [126]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_data_port_dat_w [127]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782`.\nNo latch inferred for signal `\\top.\\main_sdram_interface_wdata' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nNo latch inferred for signal `\\top.\\main_sdram_interface_wdata_we' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata_we [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_interface_wdata_we [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781`.\nNo latch inferred for signal `\\top.\\main_sdram_cmd_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_cmd_ready` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634`.\nNo latch inferred for signal `\\top.\\main_sdram_choose_req_want_reads' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_req_want_reads` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634`.\nNo latch inferred for signal `\\top.\\main_sdram_choose_req_want_writes' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_req_want_writes` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634`.\nNo latch inferred for signal `\\top.\\main_sdram_choose_req_want_activates' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_req_want_activates` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634`.\nNo latch inferred for signal `\\top.\\main_sdram_choose_req_cmd_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_req_cmd_ready` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634`.\nNo latch inferred for signal `\\top.\\main_sdram_steerer_sel' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_steerer_sel [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_steerer_sel [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634`.\nNo latch inferred for signal `\\top.\\main_sdram_en0' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_en0` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634`.\nNo latch inferred for signal `\\top.\\main_sdram_en1' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_en1` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634`.\nNo latch inferred for signal `\\top.\\builder_multiplexer_next_state' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_multiplexer_next_state [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_multiplexer_next_state [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_multiplexer_next_state [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2603$625'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_ready` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2603$625`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2594$618'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_ready` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2594$618`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2585$611'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_ready` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2585$611`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2576$604'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_ready` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2576$604`.\nNo latch inferred for signal `\\top.\\main_sdram_choose_req_cmd_payload_we' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2570$603'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_req_cmd_payload_we` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2570$603`.\nNo latch inferred for signal `\\top.\\main_sdram_choose_req_cmd_payload_ras' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2564$602'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_req_cmd_payload_ras` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2564$602`.\nNo latch inferred for signal `\\top.\\main_sdram_choose_req_cmd_payload_cas' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2558$601'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_req_cmd_payload_cas` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2558$601`.\nNo latch inferred for signal `\\top.\\main_sdram_choose_req_valids' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2544$548'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_req_valids [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2544$548`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_req_valids [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2544$548`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_req_valids [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2544$548`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_req_valids [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2544$548`.\nNo latch inferred for signal `\\top.\\main_sdram_choose_cmd_cmd_payload_we' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2537$545'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_cmd_cmd_payload_we` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2537$545`.\nNo latch inferred for signal `\\top.\\main_sdram_choose_cmd_cmd_payload_ras' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2531$544'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_cmd_cmd_payload_ras` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2531$544`.\nNo latch inferred for signal `\\top.\\main_sdram_choose_cmd_cmd_payload_cas' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2525$543'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_cmd_cmd_payload_cas` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2525$543`.\nNo latch inferred for signal `\\top.\\main_sdram_choose_cmd_valids' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2511$490'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_cmd_valids [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2511$490`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_cmd_valids [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2511$490`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_cmd_valids [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2511$490`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_choose_cmd_valids [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2511$490`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_req_wdata_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_req_wdata_ready` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_req_rdata_valid' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_req_rdata_valid` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_refresh_gnt' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_refresh_gnt` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_valid' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_valid` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_payload_cas' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_cas` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_payload_ras' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_ras` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_payload_we' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_we` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_payload_is_cmd' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_is_cmd` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_payload_is_read' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_is_read` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_payload_is_write' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_is_write` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_row_open' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_row_open` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_row_close' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_row_close` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_row_col_n_addr_sel' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_row_col_n_addr_sel` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\builder_bankmachine3_next_state' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_bankmachine3_next_state [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_bankmachine3_next_state [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_bankmachine3_next_state [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2388$438'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2388$438`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2388$438`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2388$438`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_auto_precharge' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2366$434'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_auto_precharge` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2366$434`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine3_cmd_payload_a' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine3_cmd_payload_a [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_req_wdata_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_req_wdata_ready` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_req_rdata_valid' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_req_rdata_valid` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_refresh_gnt' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_refresh_gnt` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_valid' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_valid` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_payload_cas' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_cas` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_payload_ras' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_ras` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_payload_we' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_we` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_payload_is_cmd' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_is_cmd` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_payload_is_read' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_is_read` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_payload_is_write' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_is_write` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_row_open' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_row_open` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_row_close' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_row_close` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_row_col_n_addr_sel' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_row_col_n_addr_sel` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\builder_bankmachine2_next_state' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_bankmachine2_next_state [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_bankmachine2_next_state [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_bankmachine2_next_state [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2237$408'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2237$408`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2237$408`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2237$408`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_auto_precharge' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2215$404'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_auto_precharge` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2215$404`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine2_cmd_payload_a' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine2_cmd_payload_a [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_req_wdata_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_req_wdata_ready` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_req_rdata_valid' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_req_rdata_valid` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_refresh_gnt' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_refresh_gnt` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_valid' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_valid` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_payload_cas' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_cas` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_payload_ras' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_ras` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_payload_we' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_we` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_payload_is_cmd' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_is_cmd` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_payload_is_read' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_is_read` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_payload_is_write' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_is_write` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_row_open' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_row_open` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_row_close' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_row_close` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_row_col_n_addr_sel' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_row_col_n_addr_sel` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\builder_bankmachine1_next_state' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_bankmachine1_next_state [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_bankmachine1_next_state [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_bankmachine1_next_state [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2086$378'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2086$378`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2086$378`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2086$378`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_auto_precharge' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2064$374'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_auto_precharge` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2064$374`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine1_cmd_payload_a' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine1_cmd_payload_a [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_req_wdata_ready' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_req_wdata_ready` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_req_rdata_valid' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_req_rdata_valid` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_refresh_gnt' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_refresh_gnt` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_valid' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_valid` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_payload_cas' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_cas` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_payload_ras' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_ras` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_payload_we' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_we` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_payload_is_cmd' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_is_cmd` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_payload_is_read' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_is_read` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_payload_is_write' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_is_write` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_row_open' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_row_open` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_row_close' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_row_close` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_row_col_n_addr_sel' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_row_col_n_addr_sel` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\builder_bankmachine0_next_state' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_bankmachine0_next_state [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_bankmachine0_next_state [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_bankmachine0_next_state [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1935$348'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1935$348`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1935$348`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1935$348`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_auto_precharge' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1913$344'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_auto_precharge` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1913$344`.\nNo latch inferred for signal `\\top.\\main_sdram_bankmachine0_cmd_payload_a' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_bankmachine0_cmd_payload_a [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335`.\nNo latch inferred for signal `\\top.\\main_sdram_cmd_valid' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_cmd_valid` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331`.\nNo latch inferred for signal `\\top.\\main_sdram_cmd_last' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_cmd_last` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331`.\nNo latch inferred for signal `\\top.\\main_sdram_sequencer_start0' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_sequencer_start0` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331`.\nNo latch inferred for signal `\\top.\\builder_refresher_next_state' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_refresher_next_state [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\builder_refresher_next_state [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331`.\nNo latch inferred for signal `\\top.\\main_sdram_inti_p0_cas_n' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1798$318'.\nRemoving init bit 1'1 for non-memory siginal `\\top.\\main_sdram_inti_p0_cas_n` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1798$318`.\nNo latch inferred for signal `\\top.\\main_sdram_inti_p0_cs_n' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1798$318'.\nRemoving init bit 1'1 for non-memory siginal `\\top.\\main_sdram_inti_p0_cs_n` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1798$318`.\nNo latch inferred for signal `\\top.\\main_sdram_inti_p0_ras_n' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1798$318'.\nRemoving init bit 1'1 for non-memory siginal `\\top.\\main_sdram_inti_p0_ras_n` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1798$318`.\nNo latch inferred for signal `\\top.\\main_sdram_inti_p0_we_n' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1798$318'.\nRemoving init bit 1'1 for non-memory siginal `\\top.\\main_sdram_inti_p0_we_n` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1798$318`.\nNo latch inferred for signal `\\top.\\main_sdram_inti_p0_rddata' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_inti_p0_rddata_valid' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_inti_p0_rddata_valid` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_slave_p0_rddata' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_slave_p0_rddata_valid' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_slave_p0_rddata_valid` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_address' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_address [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_bank' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_bank [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_bank [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_cas_n' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'1 for non-memory siginal `\\top.\\main_sdram_master_p0_cas_n` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_cs_n' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'1 for non-memory siginal `\\top.\\main_sdram_master_p0_cs_n` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_ras_n' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'1 for non-memory siginal `\\top.\\main_sdram_master_p0_ras_n` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_we_n' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'1 for non-memory siginal `\\top.\\main_sdram_master_p0_we_n` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_cke' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_cke` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_odt' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_odt` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_reset_n' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_reset_n` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_act_n' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'1 for non-memory siginal `\\top.\\main_sdram_master_p0_act_n` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_wrdata' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_wrdata_en' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata_en` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_wrdata_mask' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata_mask [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_wrdata_mask [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_sdram_master_p0_rddata_en' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_sdram_master_p0_rddata_en` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317`.\nNo latch inferred for signal `\\top.\\main_soclinux_timer_zero_clear' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1694$313'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_timer_zero_clear` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1694$313`.\nNo latch inferred for signal `\\top.\\main_soclinux_uart_rx_fifo_wrport_adr' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1676$305'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_rx_fifo_wrport_adr [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1676$305`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_rx_fifo_wrport_adr [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1676$305`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_rx_fifo_wrport_adr [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1676$305`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_rx_fifo_wrport_adr [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1676$305`.\nNo latch inferred for signal `\\top.\\main_soclinux_uart_tx_fifo_wrport_adr' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1646$294'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_tx_fifo_wrport_adr [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1646$294`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_tx_fifo_wrport_adr [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1646$294`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_tx_fifo_wrport_adr [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1646$294`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_tx_fifo_wrport_adr [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1646$294`.\nNo latch inferred for signal `\\top.\\main_soclinux_uart_eventmanager_pending_w' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1624$286'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_eventmanager_pending_w [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1624$286`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_eventmanager_pending_w [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1624$286`.\nNo latch inferred for signal `\\top.\\main_soclinux_uart_rx_clear' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1618$284'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_rx_clear` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1618$284`.\nNo latch inferred for signal `\\top.\\main_soclinux_uart_eventmanager_status_w' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1613$283'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_eventmanager_status_w [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1613$283`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_eventmanager_status_w [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1613$283`.\nNo latch inferred for signal `\\top.\\main_soclinux_uart_tx_clear' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1607$281'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_uart_tx_clear` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1607$281`.\nNo latch inferred for signal `\\top.\\main_soclinux_ram_we' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1567$260'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_ram_we [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1567$260`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_ram_we [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1567$260`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_ram_we [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1567$260`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_ram_we [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1567$260`.\nNo latch inferred for signal `\\top.\\main_soclinux_cpu_interrupt0' from process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258'.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [0]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [1]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [2]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [3]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [4]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [5]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [6]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [7]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [8]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [9]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [10]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [11]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [12]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [13]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [14]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [15]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [16]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [17]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [18]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [19]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [20]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [21]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [22]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [23]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [24]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [25]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [26]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [27]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [28]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [29]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [30]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\nRemoving init bit 1'0 for non-memory siginal `\\top.\\main_soclinux_cpu_interrupt0 [31]` in process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258`.\n\n4.5.8. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\TRELLIS_FF.\\Q' using process `\\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$226'.\n  created $dff cell `$procdff$11602' with positive edge clock.\nCreating register for signal `\\DPR16X4C.\\i' using process `\\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$223'.\n  created direct connection (no actual register cell created).\nCreating register for signal `\\DPR16X4C.$memwr$\\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$201_ADDR' using process `\\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$202'.\n  created $dff cell `$procdff$11603' with positive edge clock.\nCreating register for signal `\\DPR16X4C.$memwr$\\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$201_DATA' using process `\\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$202'.\n  created $dff cell `$procdff$11604' with positive edge clock.\nCreating register for signal `\\DPR16X4C.$memwr$\\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$201_EN' using process `\\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$202'.\n  created $dff cell `$procdff$11605' with positive edge clock.\nCreating register for signal `\\TRELLIS_DPR16X4.\\i' using process `\\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$169'.\n  created direct connection (no actual register cell created).\nCreating register for signal `\\TRELLIS_DPR16X4.$memwr$\\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$145_ADDR' using process `\\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$147'.\n  created $dff cell `$procdff$11606' with positive edge clock.\nCreating register for signal `\\TRELLIS_DPR16X4.$memwr$\\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$145_DATA' using process `\\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$147'.\n  created $dff cell `$procdff$11607' with positive edge clock.\nCreating register for signal `\\TRELLIS_DPR16X4.$memwr$\\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$145_EN' using process `\\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$147'.\n  created $dff cell `$procdff$11608' with positive edge clock.\nCreating register for signal `\\TRELLIS_DPR16X4.\\muxwre' using process `\\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$146'.\n  created direct connection (no actual register cell created).\nCreating register for signal `\\InstructionCache.\\_zz_3_' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11609' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\lineLoader_address' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11610' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\lineLoader_flushCounter' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11611' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\io_cpu_fetch_data_regNextWhen' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11612' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\decodeStage_mmuRsp_physicalAddress' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11613' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\decodeStage_mmuRsp_isIoAccess' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11614' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\decodeStage_mmuRsp_allowRead' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11615' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\decodeStage_mmuRsp_allowWrite' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11616' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\decodeStage_mmuRsp_allowExecute' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11617' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\decodeStage_mmuRsp_exception' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11618' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\decodeStage_mmuRsp_refilling' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11619' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\decodeStage_hit_valid' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11620' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\decodeStage_hit_error' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\n  created $dff cell `$procdff$11621' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\lineLoader_valid' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:271$3882'.\n  created $dff cell `$procdff$11622' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\lineLoader_hadError' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:271$3882'.\n  created $dff cell `$procdff$11623' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\lineLoader_flushPending' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:271$3882'.\n  created $dff cell `$procdff$11624' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\lineLoader_cmdSent' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:271$3882'.\n  created $dff cell `$procdff$11625' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\lineLoader_wordIndex' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:271$3882'.\n  created $dff cell `$procdff$11626' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\_zz_11_' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:180$3849'.\n  created $dff cell `$procdff$11627' with positive edge clock.\nCreating register for signal `\\InstructionCache.$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_ADDR' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:174$3845'.\n  created $dff cell `$procdff$11628' with positive edge clock.\nCreating register for signal `\\InstructionCache.$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_DATA' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:174$3845'.\n  created $dff cell `$procdff$11629' with positive edge clock.\nCreating register for signal `\\InstructionCache.$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:174$3845'.\n  created $dff cell `$procdff$11630' with positive edge clock.\nCreating register for signal `\\InstructionCache.\\_zz_10_' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:168$3843'.\n  created $dff cell `$procdff$11631' with positive edge clock.\nCreating register for signal `\\InstructionCache.$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_ADDR' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:162$3839'.\n  created $dff cell `$procdff$11632' with positive edge clock.\nCreating register for signal `\\InstructionCache.$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_DATA' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:162$3839'.\n  created $dff cell `$procdff$11633' with positive edge clock.\nCreating register for signal `\\InstructionCache.$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN' using process `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:162$3839'.\n  created $dff cell `$procdff$11634' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_mmuRsp_physicalAddress' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1125$3815'.\n  created $dff cell `$procdff$11635' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_flusher_valid' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1125$3815'.\n  created $dff cell `$procdff$11636' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_lrsc_reserved' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1125$3815'.\n  created $dff cell `$procdff$11637' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_memCmdSent' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1125$3815'.\n  created $dff cell `$procdff$11638' with positive edge clock.\nCreating register for signal `\\DataCache.\\loader_valid' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1125$3815'.\n  created $dff cell `$procdff$11639' with positive edge clock.\nCreating register for signal `\\DataCache.\\loader_counter_value' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1125$3815'.\n  created $dff cell `$procdff$11640' with positive edge clock.\nCreating register for signal `\\DataCache.\\loader_waysAllocator' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1125$3815'.\n  created $dff cell `$procdff$11641' with positive edge clock.\nCreating register for signal `\\DataCache.\\loader_error' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1125$3815'.\n  created $dff cell `$procdff$11642' with positive edge clock.\nCreating register for signal `\\DataCache.\\tagsWriteLastCmd_valid' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11643' with positive edge clock.\nCreating register for signal `\\DataCache.\\tagsWriteLastCmd_payload_way' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11644' with positive edge clock.\nCreating register for signal `\\DataCache.\\tagsWriteLastCmd_payload_address' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11645' with positive edge clock.\nCreating register for signal `\\DataCache.\\tagsWriteLastCmd_payload_data_valid' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11646' with positive edge clock.\nCreating register for signal `\\DataCache.\\tagsWriteLastCmd_payload_data_error' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11647' with positive edge clock.\nCreating register for signal `\\DataCache.\\tagsWriteLastCmd_payload_data_address' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11648' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageA_request_wr' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11649' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageA_request_data' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11650' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageA_request_size' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11651' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageA_request_isLrsc' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11652' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageA_request_isAmo' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11653' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageA_request_amoCtrl_swap' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11654' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageA_request_amoCtrl_alu' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11655' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageA_mask' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11656' with positive edge clock.\nCreating register for signal `\\DataCache.\\stage0_colisions_regNextWhen' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11657' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_request_wr' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11658' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_request_data' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11659' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_request_size' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11660' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_request_isLrsc' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11661' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_isAmo' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11662' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_request_amoCtrl_swap' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11663' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_request_amoCtrl_alu' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11664' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_mmuRsp_isIoAccess' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11665' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_mmuRsp_allowRead' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11666' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_mmuRsp_allowWrite' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11667' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_mmuRsp_allowExecute' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11668' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_mmuRsp_exception' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11669' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_mmuRsp_refilling' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11670' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_tagsReadRsp_0_valid' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11671' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_tagsReadRsp_0_error' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11672' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_tagsReadRsp_0_address' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11673' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_dataReadRsp_0' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11674' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_waysHits' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11675' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_mask' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11676' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_colisions' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11677' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_amo_resultRegValid' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11678' with positive edge clock.\nCreating register for signal `\\DataCache.\\stageB_amo_resultReg' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\n  created $dff cell `$procdff$11679' with positive edge clock.\nCreating register for signal `\\DataCache.\\_zz_38_' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:583$3682'.\n  created $dff cell `$procdff$11680' with positive edge clock.\nCreating register for signal `\\DataCache.\\_zz_39_' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:583$3682'.\n  created $dff cell `$procdff$11681' with positive edge clock.\nCreating register for signal `\\DataCache.\\_zz_40_' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:583$3682'.\n  created $dff cell `$procdff$11682' with positive edge clock.\nCreating register for signal `\\DataCache.\\_zz_41_' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:583$3682'.\n  created $dff cell `$procdff$11683' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_ADDR' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n  created $dff cell `$procdff$11684' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_DATA' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n  created $dff cell `$procdff$11685' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n  created $dff cell `$procdff$11686' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_ADDR' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n  created $dff cell `$procdff$11687' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_DATA' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n  created $dff cell `$procdff$11688' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n  created $dff cell `$procdff$11689' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_ADDR' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n  created $dff cell `$procdff$11690' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_DATA' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n  created $dff cell `$procdff$11691' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n  created $dff cell `$procdff$11692' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_ADDR' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n  created $dff cell `$procdff$11693' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_DATA' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n  created $dff cell `$procdff$11694' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\n  created $dff cell `$procdff$11695' with positive edge clock.\nCreating register for signal `\\DataCache.\\_zz_10_' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:559$3662'.\n  created $dff cell `$procdff$11696' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_ADDR' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:553$3658'.\n  created $dff cell `$procdff$11697' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_DATA' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:553$3658'.\n  created $dff cell `$procdff$11698' with positive edge clock.\nCreating register for signal `\\DataCache.$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN' using process `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:553$3658'.\n  created $dff cell `$procdff$11699' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_119_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11700' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\IBusCachedPlugin_s1_tightlyCoupledHit' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11701' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\IBusCachedPlugin_s2_tightlyCoupledHit' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11702' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_133_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11703' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_134_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11704' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_135_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11705' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_136_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11706' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_137_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11707' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_138_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11708' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_140_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11709' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_141_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11710' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_142_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11711' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_143_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11712' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_144_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11713' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_145_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11714' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_satp_ppn' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11715' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_0_exception' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11716' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_0_superPage' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11717' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_0_virtualAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11718' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_0_virtualAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11719' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_0_physicalAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11720' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_0_physicalAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11721' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_0_allowRead' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11722' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_0_allowWrite' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11723' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_0_allowExecute' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11724' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_0_allowUser' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11725' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_1_exception' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11726' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_1_superPage' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11727' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_1_virtualAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11728' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_1_virtualAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11729' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_1_physicalAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11730' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_1_physicalAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11731' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_1_allowRead' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11732' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_1_allowWrite' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11733' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_1_allowExecute' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11734' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_1_allowUser' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11735' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_2_exception' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11736' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_2_superPage' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11737' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_2_virtualAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11738' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_2_virtualAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11739' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_2_physicalAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11740' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_2_physicalAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11741' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_2_allowRead' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11742' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_2_allowWrite' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11743' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_2_allowExecute' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11744' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_2_allowUser' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11745' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_3_exception' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11746' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_3_superPage' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11747' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_3_virtualAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11748' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_3_virtualAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11749' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_3_physicalAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11750' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_3_physicalAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11751' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_3_allowRead' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11752' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_3_allowWrite' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11753' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_3_allowExecute' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11754' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_3_allowUser' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11755' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_0_exception' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11756' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_0_superPage' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11757' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_0_virtualAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11758' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_0_virtualAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11759' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_0_physicalAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11760' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_0_physicalAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11761' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_0_allowRead' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11762' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_0_allowWrite' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11763' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_0_allowExecute' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11764' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_0_allowUser' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11765' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_1_exception' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11766' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_1_superPage' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11767' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_1_virtualAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11768' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_1_virtualAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11769' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_1_physicalAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11770' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_1_physicalAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11771' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_1_allowRead' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11772' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_1_allowWrite' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11773' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_1_allowExecute' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11774' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_1_allowUser' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11775' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_2_exception' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11776' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_2_superPage' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11777' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_2_virtualAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11778' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_2_virtualAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11779' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_2_physicalAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11780' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_2_physicalAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11781' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_2_allowRead' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11782' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_2_allowWrite' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11783' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_2_allowExecute' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11784' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_2_allowUser' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11785' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_3_exception' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11786' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_3_superPage' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11787' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_3_virtualAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11788' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_3_virtualAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11789' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_3_physicalAddress_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11790' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_3_physicalAddress_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11791' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_3_allowRead' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11792' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_3_allowWrite' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11793' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_3_allowExecute' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11794' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_3_allowUser' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11795' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_vpn_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11796' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_vpn_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11797' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_portId' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11798' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_pteBuffer_V' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11799' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_pteBuffer_R' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11800' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_pteBuffer_W' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11801' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_pteBuffer_X' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11802' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_pteBuffer_U' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11803' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_pteBuffer_G' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11804' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_pteBuffer_A' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11805' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_pteBuffer_D' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11806' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_pteBuffer_RSW' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11807' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_pteBuffer_PPN0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11808' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_pteBuffer_PPN1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11809' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_186_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11810' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_187_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11811' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mtvec_mode' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11812' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mtvec_base' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11813' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mepc' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11814' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mip_MEIP' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11815' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mip_MTIP' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11816' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mip_MSIP' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11817' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mscratch' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11818' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mcause_interrupt' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11819' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mcause_exceptionCode' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11820' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mtval' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11821' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mcycle' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11822' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_minstret' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11823' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_sip_SEIP_INPUT' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11824' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_stvec_mode' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11825' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_stvec_base' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11826' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_sscratch' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11827' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_scause_interrupt' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11828' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_scause_exceptionCode' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11829' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_stval' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11830' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_sepc' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11831' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_exceptionPortCtrl_exceptionContext_code' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11832' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11833' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_interrupt_code' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11834' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_interrupt_targetPrivilege' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11835' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_DivPlugin_rs1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11836' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_DivPlugin_rs2' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11837' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_DivPlugin_accumulator' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11838' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_DivPlugin_div_needRevert' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11839' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_DivPlugin_div_done' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11840' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_DivPlugin_div_result' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11841' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\externalInterruptArray_regNext' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11842' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_MUL_LOW' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11843' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_IS_CSR' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11844' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_REGFILE_WRITE_DATA' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11845' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_ENV_CTRL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11846' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_ENV_CTRL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11847' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_ENV_CTRL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11848' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_MEMORY_MANAGMENT' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11849' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_REGFILE_WRITE_VALID' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11850' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_REGFILE_WRITE_VALID' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11851' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_REGFILE_WRITE_VALID' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11852' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_IS_RS2_SIGNED' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11853' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_INSTRUCTION' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11854' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_INSTRUCTION' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11855' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_MEMORY_ADDRESS_LOW' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11856' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_MEMORY_ADDRESS_LOW' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11857' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_BRANCH_CALC' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11858' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_SHIFT_RIGHT' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11859' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_SRC2_CTRL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11860' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_ALU_BITWISE_CTRL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11861' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_MUL_LL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11862' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_RS2' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11863' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_SRC2_FORCE_ZERO' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11864' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_SRC_LESS_UNSIGNED' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11865' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_MEMORY_AMO' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11866' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_MUL_HL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11867' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_SRC_USE_SUB_LESS' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11868' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_SRC1_CTRL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11869' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_BYPASSABLE_MEMORY_STAGE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11870' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_BYPASSABLE_MEMORY_STAGE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11871' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_MUL_HH' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11872' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_MUL_HH' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11873' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_IS_SFENCE_VMA' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11874' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_IS_SFENCE_VMA' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11875' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_IS_SFENCE_VMA' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11876' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_PREDICTION_HAD_BRANCHED2' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11877' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_BRANCH_DO' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11878' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_CSR_READ_OPCODE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11879' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_ALU_CTRL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11880' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_SHIFT_CTRL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11881' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_SHIFT_CTRL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11882' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_PC' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11883' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_PC' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11884' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_PC' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11885' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_MEMORY_WR' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11886' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_MEMORY_WR' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11887' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_MEMORY_WR' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11888' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_MUL_LH' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11889' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_MEMORY_LRSC' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11890' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_MEMORY_ENABLE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11891' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_MEMORY_ENABLE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11892' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_MEMORY_ENABLE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11893' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_CSR_WRITE_OPCODE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11894' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_BRANCH_CTRL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11895' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_FORMAL_PC_NEXT' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11896' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_FORMAL_PC_NEXT' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11897' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_FORMAL_PC_NEXT' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11898' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_IS_DIV' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11899' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_IS_DIV' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11900' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_IS_MUL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11901' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_IS_MUL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11902' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_IS_MUL' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11903' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_BYPASSABLE_EXECUTE_STAGE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11904' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_RS1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11905' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\decode_to_execute_IS_RS1_SIGNED' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11906' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\iBusWishbone_DAT_MISO_regNext' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11907' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\dBusWishbone_DAT_MISO_regNext' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\n  created $dff cell `$procdff$11908' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_arbitration_isValid' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11909' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_arbitration_isValid' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11910' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\writeBack_arbitration_isValid' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11911' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\IBusCachedPlugin_fetchPc_pcReg' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11912' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\IBusCachedPlugin_fetchPc_booted' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11913' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\IBusCachedPlugin_fetchPc_inc' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11914' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_116_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11915' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_118_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11916' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\IBusCachedPlugin_injector_nextPcCalc_valids_0' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11917' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\IBusCachedPlugin_injector_nextPcCalc_valids_1' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11918' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\IBusCachedPlugin_injector_nextPcCalc_valids_2' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11919' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\IBusCachedPlugin_injector_nextPcCalc_valids_3' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11920' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\IBusCachedPlugin_injector_nextPcCalc_valids_4' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11921' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\IBusCachedPlugin_injector_decodeRemoved' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11922' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\IBusCachedPlugin_rspCounter' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11923' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_132_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11924' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_139_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11925' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\DBusCachedPlugin_rspCounter' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11926' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_status_sum' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11927' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_status_mxr' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11928' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_status_mprv' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11929' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_satp_mode' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11930' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_0_valid' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11931' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_1_valid' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11932' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_2_valid' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11933' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_cache_3_valid' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11934' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_0_entryToReplace_value' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11935' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_0_valid' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11936' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_1_valid' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11937' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_2_valid' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11938' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_cache_3_valid' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11939' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_ports_1_entryToReplace_value' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11940' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\MmuPlugin_shared_state_1_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11941' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_172_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11942' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_185_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11943' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_210_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11944' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mstatus_MIE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11945' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mstatus_MPIE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11946' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mstatus_MPP' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11947' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mie_MEIE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11948' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mie_MTIE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11949' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mie_MSIE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11950' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_medeleg_IAM' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11951' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_medeleg_IAF' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11952' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_medeleg_II' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11953' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_medeleg_LAM' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11954' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_medeleg_LAF' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11955' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_medeleg_SAM' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11956' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_medeleg_SAF' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11957' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_medeleg_EU' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11958' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_medeleg_ES' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11959' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_medeleg_IPF' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11960' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_medeleg_LPF' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11961' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_medeleg_SPF' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11962' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mideleg_ST' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11963' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mideleg_SE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11964' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_mideleg_SS' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11965' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_sstatus_SIE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11966' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_sstatus_SPIE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11967' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_sstatus_SPP' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11968' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_sip_SEIP_SOFT' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11969' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_sip_STIP' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11970' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_sip_SSIP' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11971' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_sie_SEIE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11972' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_sie_STIE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11973' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_sie_SSIE' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11974' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11975' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11976' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11977' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11978' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_interrupt_valid' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11979' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_lastStageWasWfi' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11980' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\CsrPlugin_hadException' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11981' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_CsrPlugin_wfiWake' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11982' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_DivPlugin_div_counter_value' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11983' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_226_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11984' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_228_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11985' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_REGFILE_WRITE_DATA' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11986' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_INSTRUCTION' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11987' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\execute_to_memory_IS_DBUS_SHARING' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11988' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\memory_to_writeBack_IS_DBUS_SHARING' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11989' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_230_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11990' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_231_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11991' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_232_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11992' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_238_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\n  created $dff cell `$procdff$11993' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_266_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3204$2817'.\n  created $dff cell `$procdff$11994' with positive edge clock.\nCreating register for signal `\\VexRiscv.\\_zz_265_' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3198$2815'.\n  created $dff cell `$procdff$11995' with positive edge clock.\nCreating register for signal `\\VexRiscv.$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_ADDR' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3192$2811'.\n  created $dff cell `$procdff$11996' with positive edge clock.\nCreating register for signal `\\VexRiscv.$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_DATA' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3192$2811'.\n  created $dff cell `$procdff$11997' with positive edge clock.\nCreating register for signal `\\VexRiscv.$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN' using process `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3192$2811'.\n  created $dff cell `$procdff$11998' with positive edge clock.\nCreating register for signal `\\top.\\memadr_18' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6107$1927'.\n  created $dff cell `$procdff$11999' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6107$1927'.\n  created $dff cell `$procdff$12000' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6107$1927'.\n  created $dff cell `$procdff$12001' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6107$1927'.\n  created $dff cell `$procdff$12002' with positive edge clock.\nCreating register for signal `\\top.\\memadr_17' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6097$1922'.\n  created $dff cell `$procdff$12003' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6097$1922'.\n  created $dff cell `$procdff$12004' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6097$1922'.\n  created $dff cell `$procdff$12005' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6097$1922'.\n  created $dff cell `$procdff$12006' with positive edge clock.\nCreating register for signal `\\top.\\memadr_16' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6087$1917'.\n  created $dff cell `$procdff$12007' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6087$1917'.\n  created $dff cell `$procdff$12008' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6087$1917'.\n  created $dff cell `$procdff$12009' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6087$1917'.\n  created $dff cell `$procdff$12010' with positive edge clock.\nCreating register for signal `\\top.\\memadr_15' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6077$1912'.\n  created $dff cell `$procdff$12011' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6077$1912'.\n  created $dff cell `$procdff$12012' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6077$1912'.\n  created $dff cell `$procdff$12013' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6077$1912'.\n  created $dff cell `$procdff$12014' with positive edge clock.\nCreating register for signal `\\top.\\memadr_14' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6067$1907'.\n  created $dff cell `$procdff$12015' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6067$1907'.\n  created $dff cell `$procdff$12016' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6067$1907'.\n  created $dff cell `$procdff$12017' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6067$1907'.\n  created $dff cell `$procdff$12018' with positive edge clock.\nCreating register for signal `\\top.\\memadr_13' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6057$1902'.\n  created $dff cell `$procdff$12019' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6057$1902'.\n  created $dff cell `$procdff$12020' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6057$1902'.\n  created $dff cell `$procdff$12021' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6057$1902'.\n  created $dff cell `$procdff$12022' with positive edge clock.\nCreating register for signal `\\top.\\memadr_12' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6047$1897'.\n  created $dff cell `$procdff$12023' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6047$1897'.\n  created $dff cell `$procdff$12024' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6047$1897'.\n  created $dff cell `$procdff$12025' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6047$1897'.\n  created $dff cell `$procdff$12026' with positive edge clock.\nCreating register for signal `\\top.\\memadr_11' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6037$1892'.\n  created $dff cell `$procdff$12027' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6037$1892'.\n  created $dff cell `$procdff$12028' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6037$1892'.\n  created $dff cell `$procdff$12029' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6037$1892'.\n  created $dff cell `$procdff$12030' with positive edge clock.\nCreating register for signal `\\top.\\memadr_10' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6027$1887'.\n  created $dff cell `$procdff$12031' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6027$1887'.\n  created $dff cell `$procdff$12032' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6027$1887'.\n  created $dff cell `$procdff$12033' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6027$1887'.\n  created $dff cell `$procdff$12034' with positive edge clock.\nCreating register for signal `\\top.\\memadr_9' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6017$1882'.\n  created $dff cell `$procdff$12035' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6017$1882'.\n  created $dff cell `$procdff$12036' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6017$1882'.\n  created $dff cell `$procdff$12037' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6017$1882'.\n  created $dff cell `$procdff$12038' with positive edge clock.\nCreating register for signal `\\top.\\memadr_8' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6007$1877'.\n  created $dff cell `$procdff$12039' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6007$1877'.\n  created $dff cell `$procdff$12040' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6007$1877'.\n  created $dff cell `$procdff$12041' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6007$1877'.\n  created $dff cell `$procdff$12042' with positive edge clock.\nCreating register for signal `\\top.\\memadr_7' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5997$1872'.\n  created $dff cell `$procdff$12043' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5997$1872'.\n  created $dff cell `$procdff$12044' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5997$1872'.\n  created $dff cell `$procdff$12045' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5997$1872'.\n  created $dff cell `$procdff$12046' with positive edge clock.\nCreating register for signal `\\top.\\memadr_6' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5987$1867'.\n  created $dff cell `$procdff$12047' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5987$1867'.\n  created $dff cell `$procdff$12048' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5987$1867'.\n  created $dff cell `$procdff$12049' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5987$1867'.\n  created $dff cell `$procdff$12050' with positive edge clock.\nCreating register for signal `\\top.\\memadr_5' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5977$1862'.\n  created $dff cell `$procdff$12051' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5977$1862'.\n  created $dff cell `$procdff$12052' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5977$1862'.\n  created $dff cell `$procdff$12053' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5977$1862'.\n  created $dff cell `$procdff$12054' with positive edge clock.\nCreating register for signal `\\top.\\memadr_4' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5967$1857'.\n  created $dff cell `$procdff$12055' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5967$1857'.\n  created $dff cell `$procdff$12056' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5967$1857'.\n  created $dff cell `$procdff$12057' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5967$1857'.\n  created $dff cell `$procdff$12058' with positive edge clock.\nCreating register for signal `\\top.\\memadr_3' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5957$1852'.\n  created $dff cell `$procdff$12059' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5957$1852'.\n  created $dff cell `$procdff$12060' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5957$1852'.\n  created $dff cell `$procdff$12061' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5957$1852'.\n  created $dff cell `$procdff$12062' with positive edge clock.\nCreating register for signal `\\top.\\memadr_2' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5892$1846'.\n  created $dff cell `$procdff$12063' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5892$1846'.\n  created $dff cell `$procdff$12064' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5892$1846'.\n  created $dff cell `$procdff$12065' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5892$1846'.\n  created $dff cell `$procdff$12066' with positive edge clock.\nCreating register for signal `\\top.\\memdat_8' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5878$1839'.\n  created $dff cell `$procdff$12067' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5878$1839'.\n  created $dff cell `$procdff$12068' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5878$1839'.\n  created $dff cell `$procdff$12069' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5878$1839'.\n  created $dff cell `$procdff$12070' with positive edge clock.\nCreating register for signal `\\top.\\memdat_7' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5864$1832'.\n  created $dff cell `$procdff$12071' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5864$1832'.\n  created $dff cell `$procdff$12072' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5864$1832'.\n  created $dff cell `$procdff$12073' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5864$1832'.\n  created $dff cell `$procdff$12074' with positive edge clock.\nCreating register for signal `\\top.\\memdat_6' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5850$1825'.\n  created $dff cell `$procdff$12075' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5850$1825'.\n  created $dff cell `$procdff$12076' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5850$1825'.\n  created $dff cell `$procdff$12077' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5850$1825'.\n  created $dff cell `$procdff$12078' with positive edge clock.\nCreating register for signal `\\top.\\memdat_5' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5836$1818'.\n  created $dff cell `$procdff$12079' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5836$1818'.\n  created $dff cell `$procdff$12080' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5836$1818'.\n  created $dff cell `$procdff$12081' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5836$1818'.\n  created $dff cell `$procdff$12082' with positive edge clock.\nCreating register for signal `\\top.\\memdat_4' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5826$1816'.\n  created $dff cell `$procdff$12083' with positive edge clock.\nCreating register for signal `\\top.\\memdat_3' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5820$1811'.\n  created $dff cell `$procdff$12084' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5820$1811'.\n  created $dff cell `$procdff$12085' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5820$1811'.\n  created $dff cell `$procdff$12086' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5820$1811'.\n  created $dff cell `$procdff$12087' with positive edge clock.\nCreating register for signal `\\top.\\memdat_2' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5809$1809'.\n  created $dff cell `$procdff$12088' with positive edge clock.\nCreating register for signal `\\top.\\memdat_1' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5803$1804'.\n  created $dff cell `$procdff$12089' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5803$1804'.\n  created $dff cell `$procdff$12090' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5803$1804'.\n  created $dff cell `$procdff$12091' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5803$1804'.\n  created $dff cell `$procdff$12092' with positive edge clock.\nCreating register for signal `\\top.\\memadr_1' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5790$1802'.\n  created $dff cell `$procdff$12093' with positive edge clock.\nCreating register for signal `\\top.\\memadr' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12094' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12095' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12096' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12097' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12098' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12099' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12100' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12101' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12102' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12103' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_ADDR' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12104' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_DATA' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12105' with positive edge clock.\nCreating register for signal `\\top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\n  created $dff cell `$procdff$12106' with positive edge clock.\nCreating register for signal `\\top.\\memdat' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5758$1786'.\n  created $dff cell `$procdff$12107' with positive edge clock.\nCreating register for signal `\\top.\\serial_tx' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12108' with positive edge clock.\nCreating register for signal `\\top.\\spisdcard_clk' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12109' with positive edge clock.\nCreating register for signal `\\top.\\spisdcard_mosi' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12110' with positive edge clock.\nCreating register for signal `\\top.\\spisdcard_cs_n' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12111' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_soccontroller_reset_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12112' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_soccontroller_reset_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12113' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_soccontroller_scratch_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12114' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_soccontroller_scratch_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12115' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_soccontroller_bus_errors' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12116' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_cpu_time_status' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12117' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_cpu_time_cmp_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12118' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_cpu_time_cmp_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12119' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_cpu_time' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12120' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_cpu_time_cmp' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12121' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_soclinux_ram_bus_ack' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12122' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_ram_bus_ram_bus_ack' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12123' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12124' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12125' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_sink_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12126' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_tx_clken' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12127' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_tx_clkphase' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12128' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_tx_reg' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12129' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_tx_bitcount' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12130' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_tx_busy' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12131' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_source_valid' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12132' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_source_payload_data' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12133' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_rx_clken' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12134' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_rx_clkphase' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12135' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_rx_r' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12136' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_rx_reg' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12137' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_rx_bitcount' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12138' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_rx_busy' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12139' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_tx_pending' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12140' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_tx_old_trigger' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12141' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_rx_pending' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12142' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_rx_old_trigger' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12143' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_eventmanager_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12144' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_eventmanager_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12145' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_tx_fifo_readable' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12146' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_tx_fifo_level0' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12147' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_tx_fifo_produce' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12148' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_tx_fifo_consume' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12149' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_rx_fifo_readable' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12150' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_rx_fifo_level0' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12151' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_rx_fifo_produce' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12152' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_uart_rx_fifo_consume' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12153' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_load_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12154' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_load_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12155' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_reload_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12156' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_reload_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12157' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_en_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12158' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_en_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12159' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_update_value_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12160' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_update_value_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12161' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_value_status' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12162' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_zero_pending' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12163' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_zero_old_trigger' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12164' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_eventmanager_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12165' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_eventmanager_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12166' with positive edge clock.\nCreating register for signal `\\top.\\main_soclinux_timer_value' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12167' with positive edge clock.\nCreating register for signal `\\top.\\main_dfi_p0_rddata_valid' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12168' with positive edge clock.\nCreating register for signal `\\top.\\main_rddata_en' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12169' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12170' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12171' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_command_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12172' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_command_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12173' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_address_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12174' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_address_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12175' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_baddress_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12176' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_baddress_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12177' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_wrdata_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12178' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_wrdata_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12179' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_rddata_status' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12180' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_dfi_p0_address' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12181' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_dfi_p0_bank' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12182' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_dfi_p0_cas_n' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12183' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_dfi_p0_cs_n' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12184' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_dfi_p0_ras_n' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12185' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_dfi_p0_we_n' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12186' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_dfi_p0_wrdata_en' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12187' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_dfi_p0_rddata_en' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12188' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_cmd_payload_a' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12189' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_cmd_payload_ba' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12190' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_cmd_payload_cas' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12191' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_cmd_payload_ras' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12192' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_cmd_payload_we' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12193' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_timer_count1' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12194' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_postponer_req_o' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12195' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_postponer_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12196' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_sequencer_done1' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12197' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_sequencer_counter' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12198' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_sequencer_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12199' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_cmd_buffer_lookahead_level' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12200' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_cmd_buffer_lookahead_produce' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12201' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_cmd_buffer_lookahead_consume' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12202' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_cmd_buffer_source_valid' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12203' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_cmd_buffer_source_first' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12204' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_cmd_buffer_source_last' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12205' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_cmd_buffer_source_payload_we' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12206' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_cmd_buffer_source_payload_addr' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12207' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_row' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12208' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_row_opened' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12209' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_twtpcon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12210' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_twtpcon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12211' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_trccon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12212' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_trccon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12213' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_trascon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12214' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine0_trascon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12215' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_cmd_buffer_lookahead_level' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12216' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_cmd_buffer_lookahead_produce' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12217' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_cmd_buffer_lookahead_consume' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12218' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_cmd_buffer_source_valid' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12219' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_cmd_buffer_source_first' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12220' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_cmd_buffer_source_last' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12221' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_cmd_buffer_source_payload_we' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12222' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_cmd_buffer_source_payload_addr' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12223' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_row' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12224' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_row_opened' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12225' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_twtpcon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12226' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_twtpcon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12227' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_trccon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12228' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_trccon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12229' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_trascon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12230' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine1_trascon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12231' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_cmd_buffer_lookahead_level' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12232' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_cmd_buffer_lookahead_produce' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12233' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_cmd_buffer_lookahead_consume' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12234' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_cmd_buffer_source_valid' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12235' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_cmd_buffer_source_first' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12236' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_cmd_buffer_source_last' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12237' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_cmd_buffer_source_payload_we' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12238' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_cmd_buffer_source_payload_addr' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12239' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_row' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12240' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_row_opened' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12241' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_twtpcon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12242' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_twtpcon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12243' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_trccon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12244' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_trccon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12245' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_trascon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12246' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine2_trascon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12247' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_cmd_buffer_lookahead_level' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12248' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_cmd_buffer_lookahead_produce' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12249' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_cmd_buffer_lookahead_consume' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12250' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_cmd_buffer_source_valid' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12251' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_cmd_buffer_source_first' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12252' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_cmd_buffer_source_last' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12253' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_cmd_buffer_source_payload_we' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12254' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_cmd_buffer_source_payload_addr' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12255' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_row' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12256' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_row_opened' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12257' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_twtpcon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12258' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_twtpcon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12259' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_trccon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12260' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_trccon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12261' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_trascon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12262' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_bankmachine3_trascon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12263' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_choose_cmd_grant' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12264' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_choose_req_grant' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12265' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_trrdcon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12266' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_trrdcon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12267' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_tccdcon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12268' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_tccdcon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12269' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_twtrcon_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12270' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_twtrcon_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12271' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_time0' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12272' with positive edge clock.\nCreating register for signal `\\top.\\main_sdram_time1' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12273' with positive edge clock.\nCreating register for signal `\\top.\\main_adr_offset_r' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12274' with positive edge clock.\nCreating register for signal `\\top.\\main_wishbone_bridge_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12275' with positive edge clock.\nCreating register for signal `\\top.\\main_wishbone_bridge_wdata_converter_converter_mux' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12276' with positive edge clock.\nCreating register for signal `\\top.\\main_wishbone_bridge_rdata_converter_converter_source_first' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12277' with positive edge clock.\nCreating register for signal `\\top.\\main_wishbone_bridge_rdata_converter_converter_source_last' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12278' with positive edge clock.\nCreating register for signal `\\top.\\main_wishbone_bridge_rdata_converter_converter_source_payload_data' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12279' with positive edge clock.\nCreating register for signal `\\top.\\main_wishbone_bridge_rdata_converter_converter_source_payload_valid_token_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12280' with positive edge clock.\nCreating register for signal `\\top.\\main_wishbone_bridge_rdata_converter_converter_demux' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12281' with positive edge clock.\nCreating register for signal `\\top.\\main_wishbone_bridge_rdata_converter_converter_strobe_all' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12282' with positive edge clock.\nCreating register for signal `\\top.\\main_wishbone_bridge_cmd_consumed' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12283' with positive edge clock.\nCreating register for signal `\\top.\\main_wishbone_bridge_wdata_consumed' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12284' with positive edge clock.\nCreating register for signal `\\top.\\main_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12285' with positive edge clock.\nCreating register for signal `\\top.\\main_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12286' with positive edge clock.\nCreating register for signal `\\top.\\main_chaser' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12287' with positive edge clock.\nCreating register for signal `\\top.\\main_mode' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12288' with positive edge clock.\nCreating register for signal `\\top.\\main_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12289' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_miso' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12290' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_control_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12291' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_control_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12292' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_mosi_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12293' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_mosi_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12294' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_cs_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12295' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_cs_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12296' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_loopback_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12297' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_loopback_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12298' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12299' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_clk_divider1' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12300' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_mosi_data' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12301' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_mosi_sel' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12302' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_miso_data' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12303' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_storage' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12304' with positive edge clock.\nCreating register for signal `\\top.\\soclinux_re' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12305' with positive edge clock.\nCreating register for signal `\\top.\\builder_refresher_state' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12306' with positive edge clock.\nCreating register for signal `\\top.\\builder_bankmachine0_state' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12307' with positive edge clock.\nCreating register for signal `\\top.\\builder_bankmachine1_state' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12308' with positive edge clock.\nCreating register for signal `\\top.\\builder_bankmachine2_state' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12309' with positive edge clock.\nCreating register for signal `\\top.\\builder_bankmachine3_state' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12310' with positive edge clock.\nCreating register for signal `\\top.\\builder_multiplexer_state' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12311' with positive edge clock.\nCreating register for signal `\\top.\\builder_new_master_wdata_ready' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12312' with positive edge clock.\nCreating register for signal `\\top.\\builder_new_master_rdata_valid0' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12313' with positive edge clock.\nCreating register for signal `\\top.\\builder_new_master_rdata_valid1' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12314' with positive edge clock.\nCreating register for signal `\\top.\\builder_new_master_rdata_valid2' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12315' with positive edge clock.\nCreating register for signal `\\top.\\builder_new_master_rdata_valid3' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12316' with positive edge clock.\nCreating register for signal `\\top.\\builder_fullmemorywe_state' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12317' with positive edge clock.\nCreating register for signal `\\top.\\builder_litedramwishbone2native_state' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12318' with positive edge clock.\nCreating register for signal `\\top.\\builder_spimaster_state' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12319' with positive edge clock.\nCreating register for signal `\\top.\\builder_soclinux_adr' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12320' with positive edge clock.\nCreating register for signal `\\top.\\builder_soclinux_we' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12321' with positive edge clock.\nCreating register for signal `\\top.\\builder_soclinux_dat_w' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12322' with positive edge clock.\nCreating register for signal `\\top.\\builder_grant' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12323' with positive edge clock.\nCreating register for signal `\\top.\\builder_slave_sel_r' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12324' with positive edge clock.\nCreating register for signal `\\top.\\builder_count' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12325' with positive edge clock.\nCreating register for signal `\\top.\\builder_csr_bankarray_interface0_bank_bus_dat_r' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12326' with positive edge clock.\nCreating register for signal `\\top.\\builder_csr_bankarray_interface1_bank_bus_dat_r' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12327' with positive edge clock.\nCreating register for signal `\\top.\\builder_csr_bankarray_sel_r' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12328' with positive edge clock.\nCreating register for signal `\\top.\\builder_csr_bankarray_interface2_bank_bus_dat_r' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12329' with positive edge clock.\nCreating register for signal `\\top.\\builder_csr_bankarray_interface3_bank_bus_dat_r' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12330' with positive edge clock.\nCreating register for signal `\\top.\\builder_csr_bankarray_interface4_bank_bus_dat_r' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12331' with positive edge clock.\nCreating register for signal `\\top.\\builder_csr_bankarray_interface5_bank_bus_dat_r' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12332' with positive edge clock.\nCreating register for signal `\\top.\\builder_csr_bankarray_interface6_bank_bus_dat_r' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12333' with positive edge clock.\nCreating register for signal `\\top.\\builder_csr_bankarray_interface7_bank_bus_dat_r' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12334' with positive edge clock.\nCreating register for signal `\\top.\\builder_state' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12335' with positive edge clock.\nCreating register for signal `\\top.\\builder_regs0' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12336' with positive edge clock.\nCreating register for signal `\\top.\\builder_regs1' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\n  created $dff cell `$procdff$12337' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate0_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12338' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate1_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12339' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate2_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12340' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate3_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12341' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate4_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12342' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate5_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12343' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate6_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12344' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate7_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12345' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate8_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12346' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate9_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12347' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate10_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12348' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate11_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12349' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate12_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12350' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate13_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12351' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate14_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12352' with positive edge clock.\nCreating register for signal `\\top.\\builder_inferedsdrtristate15_oe' using process `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\n  created $dff cell `$procdff$12353' with positive edge clock.\n\n4.5.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$230'.\nFound and cleaned up 2 empty switches in `\\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$226'.\nRemoving empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$226'.\nRemoving empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$223'.\nFound and cleaned up 1 empty switch in `\\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$202'.\nRemoving empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$202'.\nRemoving empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$169'.\nFound and cleaned up 1 empty switch in `\\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$147'.\nRemoving empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$147'.\nRemoving empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$146'.\nFound and cleaned up 7 empty switches in `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\nRemoving empty process `InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:309$3885'.\nFound and cleaned up 10 empty switches in `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:271$3882'.\nRemoving empty process `InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:271$3882'.\nFound and cleaned up 1 empty switch in `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:226$3860'.\nRemoving empty process `InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:226$3860'.\nFound and cleaned up 3 empty switches in `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:210$3855'.\nRemoving empty process `InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:210$3855'.\nFound and cleaned up 2 empty switches in `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:201$3853'.\nRemoving empty process `InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:201$3853'.\nFound and cleaned up 1 empty switch in `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:193$3852'.\nRemoving empty process `InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:193$3852'.\nFound and cleaned up 1 empty switch in `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:186$3851'.\nRemoving empty process `InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:186$3851'.\nFound and cleaned up 1 empty switch in `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:180$3849'.\nRemoving empty process `InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:180$3849'.\nFound and cleaned up 1 empty switch in `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:174$3845'.\nRemoving empty process `InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:174$3845'.\nFound and cleaned up 1 empty switch in `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:168$3843'.\nRemoving empty process `InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:168$3843'.\nFound and cleaned up 1 empty switch in `\\InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:162$3839'.\nRemoving empty process `InstructionCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:162$3839'.\nFound and cleaned up 13 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1125$3815'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1125$3815'.\nFound and cleaned up 11 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1059$3799'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1052$3797'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1052$3797'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1042$3794'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1042$3794'.\nFound and cleaned up 2 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1030$3792'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1030$3792'.\nFound and cleaned up 3 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1017$3789'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1017$3789'.\nFound and cleaned up 3 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1002$3788'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1002$3788'.\nFound and cleaned up 3 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:987$3787'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:987$3787'.\nFound and cleaned up 3 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:972$3786'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:972$3786'.\nFound and cleaned up 11 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:936$3783'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:936$3783'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:924$3762'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:924$3762'.\nFound and cleaned up 6 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:905$3759'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:905$3759'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:885$3754'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:885$3754'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:873$3747'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:873$3747'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:866$3746'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:866$3746'.\nFound and cleaned up 11 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:832$3742'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:832$3742'.\nFound and cleaned up 5 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:816$3739'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:816$3739'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:806$3736'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:806$3736'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:782$3717'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:782$3717'.\nFound and cleaned up 4 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:768$3715'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:768$3715'.\nFound and cleaned up 4 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:754$3713'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:754$3713'.\nFound and cleaned up 4 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:740$3711'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:740$3711'.\nFound and cleaned up 4 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:726$3709'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:726$3709'.\nFound and cleaned up 9 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:699$3706'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:699$3706'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:692$3705'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:692$3705'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:685$3703'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:685$3703'.\nFound and cleaned up 2 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:675$3702'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:675$3702'.\nFound and cleaned up 2 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:665$3701'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:665$3701'.\nFound and cleaned up 2 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:655$3700'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:655$3700'.\nFound and cleaned up 3 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:642$3699'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:642$3699'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:635$3698'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:635$3698'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:628$3697'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:628$3697'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:621$3696'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:621$3696'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:614$3695'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:614$3695'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:599$3689'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:599$3689'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:592$3687'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:592$3687'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:583$3682'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:583$3682'.\nFound and cleaned up 4 empty switches in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:568$3665'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:565$3664'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:559$3662'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:559$3662'.\nFound and cleaned up 1 empty switch in `\\DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:553$3658'.\nRemoving empty process `DataCache.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:553$3658'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2485$3615'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2484$3614'.\nFound and cleaned up 122 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7264$3478'.\nFound and cleaned up 108 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6705$3420'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6677$3408'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6677$3408'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6670$3407'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6670$3407'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6608$3346'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6591$3338'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6591$3338'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6582$3335'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6582$3335'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6573$3334'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6573$3334'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6547$3325'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6547$3325'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6533$3324'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6533$3324'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6519$3319'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6519$3319'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6505$3318'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6505$3318'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6381$3305'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6381$3305'.\nFound and cleaned up 3 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6360$3304'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6360$3304'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6350$3303'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6350$3303'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6341$3299'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6341$3299'.\nFound and cleaned up 15 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6219$3294'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6219$3294'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6211$3292'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6211$3292'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6194$3282'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6194$3282'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6180$3281'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6180$3281'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6173$3280'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6173$3280'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6166$3279'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6166$3279'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6155$3272'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6155$3272'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6140$3270'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6140$3270'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6130$3269'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6130$3269'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6120$3268'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6120$3268'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6110$3267'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6110$3267'.\nFound and cleaned up 13 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6039$3240'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6039$3240'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6023$3232'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6023$3232'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5993$3226'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5978$3225'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5963$3222'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5963$3222'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5940$3221'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5928$3220'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5928$3220'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5912$3215'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5912$3215'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5890$3214'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5875$3213'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5851$3212'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5832$3211'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5832$3211'.\nFound and cleaned up 3 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5820$3204'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5820$3204'.\nFound and cleaned up 10 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5782$3194'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5782$3194'.\nFound and cleaned up 10 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5754$3192'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5754$3192'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5719$3191'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5682$3188'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5670$3184'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5670$3184'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5652$3183'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5652$3183'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5629$3182'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5605$3181'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5586$3180'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5586$3180'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5570$3177'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5570$3177'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5556$3173'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5556$3173'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5547$3171'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5547$3171'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5474$3133'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5474$3133'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5454$3132'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5454$3132'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5432$3119'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5432$3119'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5424$3108'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5424$3108'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5416$3107'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5416$3107'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5408$3106'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5408$3106'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5400$3103'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5400$3103'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5392$3101'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5392$3101'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5382$3093'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5382$3093'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5375$3091'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5375$3091'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5363$3088'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5363$3088'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5335$3058'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5335$3058'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5327$3047'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5327$3047'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5319$3046'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5319$3046'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5311$3045'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5311$3045'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5303$3042'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5303$3042'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5295$3040'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5295$3040'.\nFound and cleaned up 3 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5283$3029'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5283$3029'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5276$3027'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5276$3027'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5264$3024'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5264$3024'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5231$2993'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5231$2993'.\nFound and cleaned up 3 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5220$2991'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5220$2991'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5206$2990'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5206$2990'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5186$2989'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5157$2986'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5139$2983'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5139$2983'.\nFound and cleaned up 4 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5124$2981'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5124$2981'.\nFound and cleaned up 5 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5105$2980'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5105$2980'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5095$2979'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5095$2979'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5086$2976'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5086$2976'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5078$2973'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5078$2973'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5071$2972'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5071$2972'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5061$2970'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5061$2970'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5049$2969'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5049$2969'.\nFound and cleaned up 3 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5037$2968'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5037$2968'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5027$2966'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5027$2966'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5018$2965'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5018$2965'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5004$2964'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5004$2964'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4995$2963'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4995$2963'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4986$2962'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4986$2962'.\nFound and cleaned up 3 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4975$2960'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4975$2960'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4928$2947'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4928$2947'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4918$2946'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4918$2946'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4908$2943'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4908$2943'.\nFound and cleaned up 3 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4895$2942'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4895$2942'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4879$2931'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4855$2927'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4840$2926'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4827$2924'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4827$2924'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4805$2923'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4790$2922'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4782$2917'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4782$2917'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4760$2916'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4743$2910'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4743$2910'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4723$2899'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4723$2899'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4712$2895'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4712$2895'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4701$2891'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4701$2891'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4686$2887'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4686$2887'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4679$2886'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4679$2886'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4672$2885'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4672$2885'.\nFound and cleaned up 3 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4642$2879'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4642$2879'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4632$2878'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4632$2878'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4625$2876'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4625$2876'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4615$2873'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4615$2873'.\nFound and cleaned up 3 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4602$2871'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4602$2871'.\nFound and cleaned up 4 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4582$2870'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4582$2870'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4575$2869'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4575$2869'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4565$2868'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4565$2868'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4557$2867'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4557$2867'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4547$2866'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4547$2866'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4536$2865'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4536$2865'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4526$2864'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4526$2864'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4519$2863'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4519$2863'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4508$2862'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4508$2862'.\nFound and cleaned up 6 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4487$2856'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4487$2856'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4477$2855'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4477$2855'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4466$2854'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4466$2854'.\nFound and cleaned up 4 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4450$2843'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4450$2843'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4443$2840'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4443$2840'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4430$2839'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4430$2839'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4423$2838'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4423$2838'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4414$2837'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4414$2837'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4407$2836'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4407$2836'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4400$2835'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4400$2835'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4393$2834'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4393$2834'.\nFound and cleaned up 3 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4360$2831'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4360$2831'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4348$2829'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4348$2829'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4340$2828'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4340$2828'.\nFound and cleaned up 3 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4303$2827'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4303$2827'.\nFound and cleaned up 11 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4272$2825'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4272$2825'.\nFound and cleaned up 11 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4242$2823'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4242$2823'.\nFound and cleaned up 2 empty switches in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4226$2822'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4226$2822'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3390$2821'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3333$2820'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3313$2819'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3313$2819'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3204$2817'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3204$2817'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3198$2815'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3198$2815'.\nFound and cleaned up 1 empty switch in `\\VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3192$2811'.\nRemoving empty process `VexRiscv.$proc$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3192$2811'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1534$2487'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1530$2486'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1526$2485'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1522$2484'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1518$2483'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1514$2482'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1510$2481'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1506$2480'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1502$2479'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1498$2478'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1494$2477'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1490$2476'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1485$2475'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1484$2474'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1483$2473'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1482$2472'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1481$2471'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1480$2470'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1479$2469'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1478$2468'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1477$2467'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1476$2466'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1475$2465'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1474$2464'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1473$2463'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1472$2462'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1471$2461'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1470$2460'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1469$2459'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1468$2458'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1467$2457'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1466$2456'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1465$2455'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1464$2454'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1463$2453'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1462$2452'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1461$2451'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1460$2450'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1459$2449'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1458$2448'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1457$2447'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1456$2446'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1455$2445'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1454$2444'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1453$2443'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1452$2442'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1451$2441'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1450$2440'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1449$2439'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1448$2438'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1447$2437'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1446$2436'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1445$2435'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1444$2434'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1443$2433'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1442$2432'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1441$2431'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1440$2430'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1439$2429'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1438$2428'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1437$2427'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1436$2426'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1435$2425'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1434$2424'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1433$2423'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1432$2422'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1431$2421'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1430$2420'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1408$2419'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1383$2418'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1318$2417'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1277$2416'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1236$2415'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1227$2414'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1223$2413'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1219$2412'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1178$2411'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1109$2410'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1105$2409'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1102$2408'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1101$2407'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1100$2406'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1099$2405'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1093$2404'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1089$2403'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1086$2402'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1082$2401'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1078$2400'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1074$2399'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1073$2398'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1072$2397'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1071$2396'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1070$2395'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1069$2394'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1068$2393'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1067$2392'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1066$2391'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1065$2390'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1064$2389'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1063$2388'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1062$2387'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1061$2386'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1060$2385'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1059$2384'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1058$2383'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1057$2382'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1056$2381'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1055$2380'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1054$2379'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1053$2378'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1040$2377'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1039$2376'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1038$2375'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1037$2374'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1036$2373'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1035$2372'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1034$2371'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1033$2370'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1032$2369'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1031$2368'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1030$2367'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1029$2366'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1028$2365'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1027$2364'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1026$2363'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1025$2362'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1024$2361'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1021$2360'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1020$2359'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1019$2358'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1018$2357'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1017$2356'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1016$2355'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1015$2354'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1014$2353'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1013$2352'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1012$2351'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1007$2350'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1006$2349'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1001$2348'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1000$2347'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:998$2346'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:994$2345'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:992$2344'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:991$2343'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:988$2342'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:985$2341'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:984$2340'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:983$2339'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:982$2338'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:978$2337'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:977$2336'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:971$2335'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:969$2334'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:968$2333'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:967$2332'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:966$2331'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:965$2330'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:957$2329'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:940$2328'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:938$2327'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:933$2326'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:916$2325'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:908$2324'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:907$2323'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:901$2322'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:898$2321'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:897$2320'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:896$2319'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:891$2318'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:888$2317'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:887$2316'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:886$2315'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:885$2314'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:882$2313'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:880$2312'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:879$2311'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:874$2310'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:870$2309'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:866$2308'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:862$2307'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:861$2306'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:852$2305'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:851$2304'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:849$2303'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:847$2302'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:845$2301'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:844$2300'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:842$2299'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:839$2298'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:838$2297'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:836$2296'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:835$2295'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:833$2294'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:831$2293'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:830$2292'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:828$2291'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:827$2290'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:826$2289'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:825$2288'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:824$2287'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:822$2286'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:820$2285'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:816$2284'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:815$2283'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:814$2282'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:811$2281'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:809$2280'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:807$2279'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:806$2278'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:804$2277'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:802$2276'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:798$2275'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:797$2274'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:796$2273'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:793$2272'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:791$2271'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:790$2270'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:789$2269'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:788$2268'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:785$2267'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:784$2266'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:782$2265'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:781$2264'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:779$2263'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:778$2262'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:776$2261'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:775$2260'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:774$2259'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:772$2258'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:771$2257'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:770$2256'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:769$2255'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:768$2254'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:767$2253'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:765$2252'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:744$2251'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:743$2250'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:742$2249'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:741$2248'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:740$2247'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:725$2246'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:724$2245'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:721$2244'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:720$2243'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:719$2242'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:718$2241'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:717$2240'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:716$2239'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:715$2238'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:713$2237'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:712$2236'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:711$2235'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:710$2234'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:708$2233'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:707$2232'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:701$2231'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:700$2230'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:698$2229'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:697$2228'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:695$2227'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:694$2226'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:692$2225'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:691$2224'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:690$2223'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:688$2222'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:687$2221'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:686$2220'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:685$2219'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:684$2218'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:683$2217'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:681$2216'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:660$2215'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:659$2214'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:658$2213'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:657$2212'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:656$2211'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:641$2210'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:640$2209'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:637$2208'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:636$2207'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:635$2206'.\nRemoving empty process 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`top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:575$2178'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:574$2177'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:573$2176'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:572$2175'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:557$2174'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:556$2173'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:553$2172'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:552$2171'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:551$2170'.\nRemoving empty process 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`top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:466$2133'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:465$2132'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:464$2131'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:463$2130'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:461$2129'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:460$2128'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:459$2127'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:458$2126'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:456$2125'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:455$2124'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:449$2123'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:448$2122'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:447$2121'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:444$2120'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:443$2119'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:442$2118'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:440$2117'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:434$2116'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:433$2115'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:432$2114'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:431$2113'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:430$2112'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:429$2111'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:428$2110'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:427$2109'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:426$2108'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:425$2107'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:422$2106'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:420$2105'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:418$2104'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:414$2103'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:413$2102'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:412$2101'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:411$2100'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:410$2099'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:409$2098'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:407$2097'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:406$2096'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:375$2095'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:374$2094'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:373$2093'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:372$2092'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:371$2091'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:370$2090'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:369$2089'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:368$2088'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:364$2087'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:363$2086'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:362$2085'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:361$2084'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:354$2083'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:353$2082'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:352$2081'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:351$2080'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:350$2079'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:349$2078'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:348$2077'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:347$2076'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:346$2075'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:345$2074'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:344$2073'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:343$2072'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:342$2071'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:341$2070'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:340$2069'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:339$2068'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:324$2067'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:323$2066'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:318$2065'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:314$2064'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:313$2063'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:312$2062'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:311$2061'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:308$2060'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:307$2059'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:282$2058'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:281$2057'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:280$2056'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:271$2055'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:270$2054'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:268$2053'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:263$2052'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:262$2051'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:261$2050'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:260$2049'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:259$2048'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:258$2047'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:257$2046'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:256$2045'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:255$2044'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:254$2043'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:239$2042'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:238$2041'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:237$2040'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:236$2039'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:235$2038'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:228$2037'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:202$2036'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:201$2035'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:200$2034'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:199$2033'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:198$2032'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:191$2031'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:183$2030'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:182$2029'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:163$2028'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:162$2027'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:161$2026'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:157$2025'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:153$2024'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:152$2023'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:150$2022'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:148$2021'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:147$2020'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:145$2019'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:132$2018'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:131$2017'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:130$2016'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:129$2015'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:127$2014'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:126$2013'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:125$2012'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:124$2011'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:123$2010'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:121$2009'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:120$2008'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:119$2007'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:118$2006'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:117$2005'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:116$2004'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:112$2003'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:110$2002'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:109$2001'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:107$2000'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:104$1999'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:100$1998'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:91$1997'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:87$1996'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:80$1995'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:79$1994'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:78$1993'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:76$1992'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:75$1991'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:72$1990'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:71$1989'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:45$1988'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:43$1987'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:37$1986'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:36$1985'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:35$1984'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:34$1983'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6107$1927'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6107$1927'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6097$1922'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6097$1922'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6087$1917'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6087$1917'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6077$1912'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6077$1912'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6067$1907'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6067$1907'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6057$1902'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6057$1902'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6047$1897'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6047$1897'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6037$1892'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6037$1892'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6027$1887'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6027$1887'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6017$1882'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6017$1882'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6007$1877'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6007$1877'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5997$1872'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5997$1872'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5987$1867'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5987$1867'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5977$1862'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5977$1862'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5967$1857'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5967$1857'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5957$1852'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5957$1852'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5892$1846'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5892$1846'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1550$2491'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5878$1839'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5878$1839'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1546$2490'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5864$1832'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5864$1832'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1542$2489'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5850$1825'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5850$1825'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1538$2488'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5836$1818'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5836$1818'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5826$1816'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5826$1816'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5820$1811'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5820$1811'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5809$1809'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5809$1809'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5803$1804'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5803$1804'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5790$1802'.\nFound and cleaned up 4 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5770$1788'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5758$1786'.\nFound and cleaned up 264 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4243$1561'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4224$1560'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4177$1559'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4177$1559'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4160$1552'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4160$1552'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4143$1545'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4143$1545'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4126$1538'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4126$1538'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4109$1531'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4109$1531'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4092$1524'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4092$1524'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4075$1523'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4058$1522'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4058$1522'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4047$1521'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4047$1521'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4036$1520'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4036$1520'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4025$1519'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4025$1519'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4014$1518'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4014$1518'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4003$1517'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4003$1517'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3992$1516'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3992$1516'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3981$1515'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3970$1514'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3962$1500'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3954$1499'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3946$1498'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3938$1484'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3930$1483'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3922$1482'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3914$1468'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3906$1467'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3898$1466'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3890$1452'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3882$1451'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3874$1450'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3857$1449'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3857$1449'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3840$1448'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3840$1448'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3823$1447'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3823$1447'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3806$1446'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3806$1446'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3789$1445'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3789$1445'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3772$1444'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3772$1444'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3755$1443'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3755$1443'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3738$1442'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3721$1441'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3721$1441'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3704$1440'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3704$1440'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3687$1439'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3687$1439'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3670$1438'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3670$1438'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3653$1437'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3653$1437'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3636$1436'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3636$1436'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3619$1435'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3619$1435'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3602$1434'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3602$1434'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3585$1433'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3568$1432'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3568$1432'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3390$1217'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3390$1217'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3304$1073'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3304$1073'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3181$876'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3140$861'.\nFound and cleaned up 2 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3088$849'.\nFound and cleaned up 6 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3039$845'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3013$838'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3013$838'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2983$833'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2932$832'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2897$826'.\nFound and cleaned up 4 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2861$821'.\nFound and cleaned up 7 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2781$795'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2759$794'.\nFound and cleaned up 2 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2744$782'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2724$781'.\nFound and cleaned up 9 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2616$634'.\nFound and cleaned up 2 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2603$625'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2603$625'.\nFound and cleaned up 2 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2594$618'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2594$618'.\nFound and cleaned up 2 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2585$611'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2585$611'.\nFound and cleaned up 2 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2576$604'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2576$604'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2570$603'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2570$603'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2564$602'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2564$602'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2558$601'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2558$601'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2544$548'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2537$545'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2537$545'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2531$544'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2531$544'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2525$543'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2525$543'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2511$490'.\nFound and cleaned up 14 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2404$447'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2388$438'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2388$438'.\nFound and cleaned up 2 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2366$434'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2366$434'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2355$425'.\nFound and cleaned up 14 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2253$417'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2237$408'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2237$408'.\nFound and cleaned up 2 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2215$404'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2215$404'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2204$395'.\nFound and cleaned up 14 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2102$387'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2086$378'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2086$378'.\nFound and cleaned up 2 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2064$374'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2064$374'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2053$365'.\nFound and cleaned up 14 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1951$357'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1935$348'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1935$348'.\nFound and cleaned up 2 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1913$344'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1913$344'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1902$335'.\nFound and cleaned up 4 empty switches in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1857$331'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1798$318'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1798$318'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1740$317'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1694$313'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1694$313'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1676$305'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1676$305'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1646$294'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1646$294'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1624$286'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1618$284'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1618$284'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1613$283'.\nFound and cleaned up 1 empty switch in `\\top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1607$281'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1607$281'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1567$260'.\nRemoving empty process `top.$proc$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1557$258'.\nCleaned up 1119 empty switches.\n\n4.6. Executing FLATTEN pass (flatten design).\nDeleting now unused module InstructionCache.\nDeleting now unused module DataCache.\nDeleting now unused module VexRiscv.\n<suppressed ~3 debug messages>\n\n4.7. Executing TRIBUF pass.\n\n4.8. Executing DEMINOUT pass (demote inout ports to input or output).\n\n4.9. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~928 debug messages>\n\n4.10. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 1015 unused cells and 6955 unused wires.\n<suppressed ~1323 debug messages>\n\n4.11. Executing CHECK pass (checking for obvious problems).\nchecking module top..\nfound and reported 0 problems.\n\n4.12. Executing OPT pass (performing simple optimizations).\n\n4.12.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.12.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\n<suppressed ~3270 debug messages>\nRemoved a total of 1090 cells.\n\n4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n      Replacing known input bits on port B of cell $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$3930: \\VexRiscv.IBusCachedPlugin_cache.lineLoader_flushCounter -> { 1'1 \\VexRiscv.IBusCachedPlugin_cache.lineLoader_flushCounter [6:0] }\n      Replacing known input bits on port A of cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4072: \\VexRiscv.dataCache_1_.stageB_flusher_valid -> 1'0\n      Replacing known input bits on port B of cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4070: \\VexRiscv.dataCache_1_.stageB_flusher_valid -> 1'1\n      Replacing known input bits on port B of cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4704: \\VexRiscv.dataCache_1_.stageB_flusher_valid -> 1'1\n      Replacing known input bits on port A of cell $procmux$10380: \\builder_litedramwishbone2native_state -> 1'1\n      Replacing known input bits on port A of cell $procmux$10378: \\builder_litedramwishbone2native_state -> 1'1\n      Replacing known input bits on port A of cell $procmux$10375: \\builder_litedramwishbone2native_state -> 1'0\n      Replacing known input bits on port A of cell $procmux$9119: \\builder_grant -> 1'0\n      Replacing known input bits on port B of cell $procmux$9117: \\builder_grant -> 1'1\n      Replacing known input bits on port A of cell $procmux$9115: \\builder_grant -> 1'1\n      Replacing known input bits on port B of cell $procmux$9123: \\builder_grant -> 1'0\n      Replacing known input bits on port A of cell $procmux$9121: \\builder_grant -> 1'0\n      Replacing known input bits on port B of cell $procmux$9287: \\main_sdram_twtrcon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9285: \\main_sdram_twtrcon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9303: \\main_sdram_tccdcon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9301: \\main_sdram_tccdcon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9319: \\main_sdram_trrdcon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9317: \\main_sdram_trrdcon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9417: \\main_sdram_bankmachine3_trascon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9415: \\main_sdram_bankmachine3_trascon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9433: \\main_sdram_bankmachine3_trccon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9431: \\main_sdram_bankmachine3_trccon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9449: \\main_sdram_bankmachine3_twtpcon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9447: \\main_sdram_bankmachine3_twtpcon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9512: \\main_sdram_bankmachine2_trascon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9510: \\main_sdram_bankmachine2_trascon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9528: \\main_sdram_bankmachine2_trccon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9526: \\main_sdram_bankmachine2_trccon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9544: \\main_sdram_bankmachine2_twtpcon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9542: \\main_sdram_bankmachine2_twtpcon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9607: \\main_sdram_bankmachine1_trascon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9605: \\main_sdram_bankmachine1_trascon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9623: \\main_sdram_bankmachine1_trccon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9621: \\main_sdram_bankmachine1_trccon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9639: \\main_sdram_bankmachine1_twtpcon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9637: \\main_sdram_bankmachine1_twtpcon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9702: \\main_sdram_bankmachine0_trascon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9700: \\main_sdram_bankmachine0_trascon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9718: \\main_sdram_bankmachine0_trccon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9716: \\main_sdram_bankmachine0_trccon_ready -> 1'0\n      Replacing known input bits on port B of cell $procmux$9734: \\main_sdram_bankmachine0_twtpcon_ready -> 1'1\n      Replacing known input bits on port A of cell $procmux$9732: \\main_sdram_bankmachine0_twtpcon_ready -> 1'0\n      Replacing known input bits on port A of cell $procmux$9788: \\main_sdram_sequencer_count -> 1'0\n      Replacing known input bits on port A of cell $procmux$9955: \\main_soclinux_rx_busy -> 1'1\n      Replacing known input bits on port A of cell $procmux$9951: \\main_soclinux_rx_busy -> 1'1\n      Replacing known input bits on port A of cell $procmux$9948: \\main_soclinux_rx_busy -> 1'1\n      Replacing known input bits on port A of cell $procmux$9958: \\main_soclinux_rx_busy -> 1'0\n  Analyzing evaluation results.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$6515.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$6524.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$6533.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$6542.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$6626.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7009.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7027.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7043.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7052.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7063.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7077.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7093.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7111.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7131.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7153.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7178.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7206.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7236.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7267.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7350.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7357.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7365.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7374.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7384.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7395.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7407.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7420.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7434.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7449.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7465.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7482.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$7505.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$7526.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$7529.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$7535.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$7548.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7550.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7556.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$7566.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7568.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7574.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7592.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$7605.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7607.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7613.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$7623.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7625.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7631.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7649.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7717.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7744.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7759.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7768.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$7778.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7780.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7786.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7808.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7814.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7820.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7829.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7835.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7841.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7847.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7856.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7877.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7886.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7898.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7907.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7920.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7929.\n    dead port 1/2 on $mux $flatten\\VexRiscv.$procmux$7939.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7941.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$7947.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8011.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8083.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8101.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8110.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8173.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8195.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8205.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8207.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8213.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8223.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8225.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8231.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8243.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8249.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8258.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8268.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8270.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8276.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8286.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8288.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8294.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8306.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8312.\n    dead port 2/2 on $mux $flatten\\VexRiscv.$procmux$8321.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$3987.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4159.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4161.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4167.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4194.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4196.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4202.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4212.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4214.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4220.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4233.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4236.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4238.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4245.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4248.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4250.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4257.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4260.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4262.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4270.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4272.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4275.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4277.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4284.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4287.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4289.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4296.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4299.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4301.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4308.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4310.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4317.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4319.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4325.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4345.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4347.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4349.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4356.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4358.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4364.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4389.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4392.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4394.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4402.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4404.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4407.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4409.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4416.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4419.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4421.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4428.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4431.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4433.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4440.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4442.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4449.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4451.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4458.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4460.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4466.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4483.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4485.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4487.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4494.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4496.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4502.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4522.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4524.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4530.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4543.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4545.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4551.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4564.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4566.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4572.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4585.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4587.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4593.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4610.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4612.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4614.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4623.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4625.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4627.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4629.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4637.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4639.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4641.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4649.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4651.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4653.\n    dead port 1/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4660.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4662.\n    dead port 2/2 on $mux $flatten\\VexRiscv.\\dataCache_1_.$procmux$4668.\n    dead port 1/2 on $mux $procmux$9180.\nRemoved 192 multiplexer ports.\n<suppressed ~998 debug messages>\n\n4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6636: $auto$opt_reduce.cc:134:opt_mux$12355\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6643: $auto$opt_reduce.cc:134:opt_mux$12357\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6735: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5035_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $auto$opt_reduce.cc:134:opt_mux$12359 $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$6654_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$6651_CMP $flatten\\VexRiscv.$procmux$5057_CMP $flatten\\VexRiscv.$procmux$6649_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6769: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $auto$opt_reduce.cc:134:opt_mux$12363 $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$6654_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$6651_CMP $flatten\\VexRiscv.$procmux$5057_CMP $auto$opt_reduce.cc:134:opt_mux$12361 }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6789: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $auto$opt_reduce.cc:134:opt_mux$12365 $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$6654_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$6651_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6878: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $auto$opt_reduce.cc:134:opt_mux$12367 $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$6654_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$6651_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6894: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5035_CMP $flatten\\VexRiscv.$procmux$5821_CMP $auto$opt_reduce.cc:134:opt_mux$12375 $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $auto$opt_reduce.cc:134:opt_mux$12373 $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$6654_CMP $flatten\\VexRiscv.$procmux$5093_CMP $auto$opt_reduce.cc:134:opt_mux$12371 $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$6651_CMP $flatten\\VexRiscv.$procmux$5057_CMP $flatten\\VexRiscv.$procmux$6649_CMP $auto$opt_reduce.cc:134:opt_mux$12369 }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6936: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $auto$opt_reduce.cc:134:opt_mux$12377 $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$6654_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$6651_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6952: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $auto$opt_reduce.cc:134:opt_mux$12383 $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $auto$opt_reduce.cc:134:opt_mux$12381 $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$6654_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$6651_CMP $flatten\\VexRiscv.$procmux$5057_CMP $auto$opt_reduce.cc:134:opt_mux$12379 }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6974: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $auto$opt_reduce.cc:134:opt_mux$12385 $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$6654_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$6651_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$7270: { $flatten\\VexRiscv.$procmux$5994_CMP $flatten\\VexRiscv.$procmux$6750_CMP $flatten\\VexRiscv.$procmux$7207_CMP $flatten\\VexRiscv.$procmux$6036_CMP $flatten\\VexRiscv.$procmux$5119_CMP $flatten\\VexRiscv.$procmux$6675_CMP $flatten\\VexRiscv.$procmux$6744_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$6654_CMP $flatten\\VexRiscv.$procmux$6900_CMP $flatten\\VexRiscv.$procmux$6651_CMP $flatten\\VexRiscv.$procmux$6649_CMP $auto$opt_reduce.cc:134:opt_mux$12387 }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$7518: { $flatten\\VexRiscv.$procmux$7521_CMP $auto$opt_reduce.cc:134:opt_mux$12389 }\n    New ctrl vector for $mux cell $flatten\\VexRiscv.$procmux$7595: { }\n    New ctrl vector for $mux cell $flatten\\VexRiscv.$procmux$7652: { }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$7683: $auto$opt_reduce.cc:134:opt_mux$12391\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$8452:\n      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814\n      New ports: A=1'0, B=1'1, Y=$flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0]\n      New connections: $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [31:1] = { $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] $flatten\\VexRiscv.$0$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN[31:0]$2814 [0] }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$4000:\n      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848\n      New ports: A=1'0, B=1'1, Y=$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0]\n      New connections: $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [31:1] = { $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN[31:0]$3848 [0] }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$4008:\n      Old ports: A=22'0000000000000000000000, B=22'1111111111111111111111, Y=$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842\n      New ports: A=1'0, B=1'1, Y=$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0]\n      New connections: $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [21:1] = { $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN[21:0]$3842 [0] }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4732:\n      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN[7:0]$3668\n      New ports: A=1'0, B=1'1, Y=$flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN[7:0]$3668 [0]\n      New connections: $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN[7:0]$3668 [7:1] = { $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN[7:0]$3668 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN[7:0]$3668 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN[7:0]$3668 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN[7:0]$3668 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN[7:0]$3668 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN[7:0]$3668 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN[7:0]$3668 [0] }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4738:\n      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN[7:0]$3671\n      New ports: A=1'0, B=1'1, Y=$flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN[7:0]$3671 [0]\n      New connections: $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN[7:0]$3671 [7:1] = { $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN[7:0]$3671 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN[7:0]$3671 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN[7:0]$3671 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN[7:0]$3671 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN[7:0]$3671 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN[7:0]$3671 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN[7:0]$3671 [0] }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4744:\n      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN[7:0]$3674\n      New ports: A=1'0, B=1'1, Y=$flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN[7:0]$3674 [0]\n      New connections: $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN[7:0]$3674 [7:1] = { $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN[7:0]$3674 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN[7:0]$3674 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN[7:0]$3674 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN[7:0]$3674 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN[7:0]$3674 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN[7:0]$3674 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN[7:0]$3674 [0] }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4750:\n      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN[7:0]$3677\n      New ports: A=1'0, B=1'1, Y=$flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN[7:0]$3677 [0]\n      New connections: $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN[7:0]$3677 [7:1] = { $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN[7:0]$3677 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN[7:0]$3677 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN[7:0]$3677 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN[7:0]$3677 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN[7:0]$3677 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN[7:0]$3677 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN[7:0]$3677 [0] }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4758:\n      Old ports: A=22'0000000000000000000000, B=22'1111111111111111111111, Y=$flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661\n      New ports: A=1'0, B=1'1, Y=$flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0]\n      New connections: $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [21:1] = { $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] $flatten\\VexRiscv.\\dataCache_1_.$0$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN[21:0]$3661 [0] }\n    New ctrl vector for $pmux cell $procmux$10098: $auto$opt_reduce.cc:134:opt_mux$12393\n    New ctrl vector for $pmux cell $procmux$10103: $auto$opt_reduce.cc:134:opt_mux$12395\n    New ctrl vector for $pmux cell $procmux$10108: { $procmux$10101_CMP $auto$opt_reduce.cc:134:opt_mux$12397 }\n    New ctrl vector for $pmux cell $procmux$10113: { $procmux$10101_CMP $auto$opt_reduce.cc:134:opt_mux$12399 }\n    New ctrl vector for $pmux cell $procmux$10118: { $procmux$10101_CMP $auto$opt_reduce.cc:134:opt_mux$12401 }\n    New ctrl vector for $pmux cell $procmux$10123: { $procmux$10101_CMP $auto$opt_reduce.cc:134:opt_mux$12403 }\n    New ctrl vector for $pmux cell $procmux$10128: { $procmux$10101_CMP $auto$opt_reduce.cc:134:opt_mux$12405 }\n    New ctrl vector for $pmux cell $procmux$10271: $auto$opt_reduce.cc:134:opt_mux$12407\n    New ctrl vector for $pmux cell $procmux$10286: $auto$opt_reduce.cc:134:opt_mux$12409\n    New ctrl vector for $pmux cell $procmux$10293: $auto$opt_reduce.cc:134:opt_mux$12411\n    New ctrl vector for $pmux cell $procmux$10297: $auto$opt_reduce.cc:134:opt_mux$12413\n    New ctrl vector for $pmux cell $procmux$10323: $auto$opt_reduce.cc:134:opt_mux$12415\n    New ctrl vector for $pmux cell $procmux$10330: $auto$opt_reduce.cc:134:opt_mux$12417\n    New ctrl vector for $pmux cell $procmux$10335: { $procmux$10314_CMP $auto$opt_reduce.cc:134:opt_mux$12419 }\n    New ctrl vector for $pmux cell $procmux$10465: $auto$opt_reduce.cc:134:opt_mux$12421\n    New ctrl vector for $pmux cell $procmux$10469: $auto$opt_reduce.cc:134:opt_mux$12423\n    New ctrl vector for $pmux cell $procmux$10552: $auto$opt_reduce.cc:134:opt_mux$12425\n    New ctrl vector for $pmux cell $procmux$10559: $auto$opt_reduce.cc:134:opt_mux$12427\n    New ctrl vector for $pmux cell $procmux$10573: { $procmux$10530_CMP $auto$opt_reduce.cc:134:opt_mux$12429 }\n    New ctrl vector for $pmux cell $procmux$10579: $auto$opt_reduce.cc:134:opt_mux$12431\n    New ctrl vector for $pmux cell $procmux$10659: $auto$opt_reduce.cc:134:opt_mux$12433\n    New ctrl vector for $pmux cell $procmux$10679: $auto$opt_reduce.cc:134:opt_mux$12435\n    New ctrl vector for $pmux cell $procmux$10708: { $procmux$10643_CMP $auto$opt_reduce.cc:134:opt_mux$12437 }\n    New ctrl vector for $pmux cell $procmux$10736: $auto$opt_reduce.cc:134:opt_mux$12439\n    New ctrl vector for $pmux cell $procmux$10748: $auto$opt_reduce.cc:134:opt_mux$12441\n    New ctrl vector for $pmux cell $procmux$10770: { $procmux$10643_CMP $procmux$10635_CMP $auto$opt_reduce.cc:134:opt_mux$12443 }\n    New ctrl vector for $pmux cell $procmux$10799: $auto$opt_reduce.cc:134:opt_mux$12445\n    New ctrl vector for $pmux cell $procmux$10819: $auto$opt_reduce.cc:134:opt_mux$12447\n    New ctrl vector for $pmux cell $procmux$10880: $auto$opt_reduce.cc:134:opt_mux$12449\n    New ctrl vector for $pmux cell $procmux$10900: $auto$opt_reduce.cc:134:opt_mux$12451\n    New ctrl vector for $pmux cell $procmux$10929: { $procmux$10864_CMP $auto$opt_reduce.cc:134:opt_mux$12453 }\n    New ctrl vector for $pmux cell $procmux$10957: $auto$opt_reduce.cc:134:opt_mux$12455\n    New ctrl vector for $pmux cell $procmux$10963: $auto$opt_reduce.cc:134:opt_mux$12457\n    New ctrl vector for $pmux cell $procmux$10991: { $procmux$10864_CMP $procmux$10856_CMP $auto$opt_reduce.cc:134:opt_mux$12459 }\n    New ctrl vector for $pmux cell $procmux$11020: $auto$opt_reduce.cc:134:opt_mux$12461\n    New ctrl vector for $pmux cell $procmux$11040: $auto$opt_reduce.cc:134:opt_mux$12463\n    New ctrl vector for $pmux cell $procmux$11101: $auto$opt_reduce.cc:134:opt_mux$12465\n    New ctrl vector for $pmux cell $procmux$11121: $auto$opt_reduce.cc:134:opt_mux$12467\n    New ctrl vector for $pmux cell $procmux$11150: { $procmux$11085_CMP $auto$opt_reduce.cc:134:opt_mux$12469 }\n    New ctrl vector for $pmux cell $procmux$11178: $auto$opt_reduce.cc:134:opt_mux$12471\n    New ctrl vector for $pmux cell $procmux$11184: $auto$opt_reduce.cc:134:opt_mux$12473\n    New ctrl vector for $pmux cell $procmux$11206: { $procmux$11085_CMP $procmux$11077_CMP $auto$opt_reduce.cc:134:opt_mux$12475 }\n    New ctrl vector for $pmux cell $procmux$11235: $auto$opt_reduce.cc:134:opt_mux$12477\n    New ctrl vector for $pmux cell $procmux$11261: $auto$opt_reduce.cc:134:opt_mux$12479\n    New ctrl vector for $pmux cell $procmux$11322: $auto$opt_reduce.cc:134:opt_mux$12481\n    New ctrl vector for $pmux cell $procmux$11342: $auto$opt_reduce.cc:134:opt_mux$12483\n    New ctrl vector for $pmux cell $procmux$11371: { $procmux$11306_CMP $auto$opt_reduce.cc:134:opt_mux$12485 }\n    New ctrl vector for $pmux cell $procmux$11405: $auto$opt_reduce.cc:134:opt_mux$12487\n    New ctrl vector for $pmux cell $procmux$11411: $auto$opt_reduce.cc:134:opt_mux$12489\n    New ctrl vector for $pmux cell $procmux$11433: { $procmux$11306_CMP $procmux$11298_CMP $auto$opt_reduce.cc:134:opt_mux$12491 }\n    New ctrl vector for $pmux cell $procmux$11462: $auto$opt_reduce.cc:134:opt_mux$12493\n    New ctrl vector for $pmux cell $procmux$11482: $auto$opt_reduce.cc:134:opt_mux$12495\n    Consolidated identical input bits for $mux cell $procmux$8458:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN[7:0]$1930\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN[7:0]$1930 [0]\n      New connections: $0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN[7:0]$1930 [7:1] = { $0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN[7:0]$1930 [0] $0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN[7:0]$1930 [0] $0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN[7:0]$1930 [0] $0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN[7:0]$1930 [0] $0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN[7:0]$1930 [0] $0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN[7:0]$1930 [0] $0$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN[7:0]$1930 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8464:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN[7:0]$1925\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN[7:0]$1925 [0]\n      New connections: $0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN[7:0]$1925 [7:1] = { $0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN[7:0]$1925 [0] $0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN[7:0]$1925 [0] $0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN[7:0]$1925 [0] $0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN[7:0]$1925 [0] $0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN[7:0]$1925 [0] $0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN[7:0]$1925 [0] $0$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN[7:0]$1925 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8470:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN[7:0]$1920\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN[7:0]$1920 [0]\n      New connections: $0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN[7:0]$1920 [7:1] = { $0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN[7:0]$1920 [0] $0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN[7:0]$1920 [0] $0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN[7:0]$1920 [0] $0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN[7:0]$1920 [0] $0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN[7:0]$1920 [0] $0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN[7:0]$1920 [0] $0$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN[7:0]$1920 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8476:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN[7:0]$1915\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN[7:0]$1915 [0]\n      New connections: $0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN[7:0]$1915 [7:1] = { $0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN[7:0]$1915 [0] $0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN[7:0]$1915 [0] $0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN[7:0]$1915 [0] $0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN[7:0]$1915 [0] $0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN[7:0]$1915 [0] $0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN[7:0]$1915 [0] $0$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN[7:0]$1915 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8482:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN[7:0]$1910\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN[7:0]$1910 [0]\n      New connections: $0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN[7:0]$1910 [7:1] = { $0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN[7:0]$1910 [0] $0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN[7:0]$1910 [0] $0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN[7:0]$1910 [0] $0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN[7:0]$1910 [0] $0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN[7:0]$1910 [0] $0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN[7:0]$1910 [0] $0$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN[7:0]$1910 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8488:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN[7:0]$1905\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN[7:0]$1905 [0]\n      New connections: $0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN[7:0]$1905 [7:1] = { $0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN[7:0]$1905 [0] $0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN[7:0]$1905 [0] $0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN[7:0]$1905 [0] $0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN[7:0]$1905 [0] $0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN[7:0]$1905 [0] $0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN[7:0]$1905 [0] $0$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN[7:0]$1905 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8494:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN[7:0]$1900\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN[7:0]$1900 [0]\n      New connections: $0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN[7:0]$1900 [7:1] = { $0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN[7:0]$1900 [0] $0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN[7:0]$1900 [0] $0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN[7:0]$1900 [0] $0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN[7:0]$1900 [0] $0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN[7:0]$1900 [0] $0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN[7:0]$1900 [0] $0$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN[7:0]$1900 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8500:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN[7:0]$1895\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN[7:0]$1895 [0]\n      New connections: $0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN[7:0]$1895 [7:1] = { $0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN[7:0]$1895 [0] $0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN[7:0]$1895 [0] $0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN[7:0]$1895 [0] $0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN[7:0]$1895 [0] $0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN[7:0]$1895 [0] $0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN[7:0]$1895 [0] $0$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN[7:0]$1895 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8506:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN[7:0]$1890\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN[7:0]$1890 [0]\n      New connections: $0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN[7:0]$1890 [7:1] = { $0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN[7:0]$1890 [0] $0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN[7:0]$1890 [0] $0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN[7:0]$1890 [0] $0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN[7:0]$1890 [0] $0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN[7:0]$1890 [0] $0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN[7:0]$1890 [0] $0$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN[7:0]$1890 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8512:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN[7:0]$1885\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN[7:0]$1885 [0]\n      New connections: $0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN[7:0]$1885 [7:1] = { $0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN[7:0]$1885 [0] $0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN[7:0]$1885 [0] $0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN[7:0]$1885 [0] $0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN[7:0]$1885 [0] $0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN[7:0]$1885 [0] $0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN[7:0]$1885 [0] $0$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN[7:0]$1885 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8518:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN[7:0]$1880\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN[7:0]$1880 [0]\n      New connections: $0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN[7:0]$1880 [7:1] = { $0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN[7:0]$1880 [0] $0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN[7:0]$1880 [0] $0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN[7:0]$1880 [0] $0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN[7:0]$1880 [0] $0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN[7:0]$1880 [0] $0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN[7:0]$1880 [0] $0$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN[7:0]$1880 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8524:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN[7:0]$1875\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN[7:0]$1875 [0]\n      New connections: $0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN[7:0]$1875 [7:1] = { $0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN[7:0]$1875 [0] $0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN[7:0]$1875 [0] $0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN[7:0]$1875 [0] $0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN[7:0]$1875 [0] $0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN[7:0]$1875 [0] $0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN[7:0]$1875 [0] $0$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN[7:0]$1875 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8530:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN[7:0]$1870\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN[7:0]$1870 [0]\n      New connections: $0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN[7:0]$1870 [7:1] = { $0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN[7:0]$1870 [0] $0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN[7:0]$1870 [0] $0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN[7:0]$1870 [0] $0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN[7:0]$1870 [0] $0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN[7:0]$1870 [0] $0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN[7:0]$1870 [0] $0$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN[7:0]$1870 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8536:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN[7:0]$1865\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN[7:0]$1865 [0]\n      New connections: $0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN[7:0]$1865 [7:1] = { $0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN[7:0]$1865 [0] $0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN[7:0]$1865 [0] $0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN[7:0]$1865 [0] $0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN[7:0]$1865 [0] $0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN[7:0]$1865 [0] $0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN[7:0]$1865 [0] $0$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN[7:0]$1865 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8542:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN[7:0]$1860\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN[7:0]$1860 [0]\n      New connections: $0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN[7:0]$1860 [7:1] = { $0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN[7:0]$1860 [0] $0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN[7:0]$1860 [0] $0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN[7:0]$1860 [0] $0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN[7:0]$1860 [0] $0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN[7:0]$1860 [0] $0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN[7:0]$1860 [0] $0$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN[7:0]$1860 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8548:\n      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN[7:0]$1855\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN[7:0]$1855 [0]\n      New connections: $0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN[7:0]$1855 [7:1] = { $0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN[7:0]$1855 [0] $0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN[7:0]$1855 [0] $0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN[7:0]$1855 [0] $0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN[7:0]$1855 [0] $0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN[7:0]$1855 [0] $0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN[7:0]$1855 [0] $0$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN[7:0]$1855 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8554:\n      Old ports: A=24'000000000000000000000000, B=24'111111111111111111111111, Y=$0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0]\n      New connections: $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [23:1] = { $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] $0$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN[23:0]$1849 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8560:\n      Old ports: A=25'0000000000000000000000000, B=25'1111111111111111111111111, Y=$0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0]\n      New connections: $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [24:1] = { $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] $0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN[24:0]$1842 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8566:\n      Old ports: A=25'0000000000000000000000000, B=25'1111111111111111111111111, Y=$0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0]\n      New connections: $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [24:1] = { $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] $0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN[24:0]$1835 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8572:\n      Old ports: A=25'0000000000000000000000000, B=25'1111111111111111111111111, Y=$0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0]\n      New connections: $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [24:1] = { $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] $0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN[24:0]$1828 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8578:\n      Old ports: A=25'0000000000000000000000000, B=25'1111111111111111111111111, Y=$0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0]\n      New connections: $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [24:1] = { $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] $0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN[24:0]$1821 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8586:\n      Old ports: A=10'0000000000, B=10'1111111111, Y=$0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814 [0]\n      New connections: $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814 [9:1] = { $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814 [0] $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814 [0] $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814 [0] $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814 [0] $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814 [0] $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814 [0] $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814 [0] $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814 [0] $0$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN[9:0]$1814 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8594:\n      Old ports: A=10'0000000000, B=10'1111111111, Y=$0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807 [0]\n      New connections: $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807 [9:1] = { $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807 [0] $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807 [0] $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807 [0] $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807 [0] $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807 [0] $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807 [0] $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807 [0] $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807 [0] $0$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN[9:0]$1807 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8600:\n      Old ports: A=0, B=255, Y=$0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN[31:0]$1791\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN[31:0]$1791 [0]\n      New connections: $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN[31:0]$1791 [31:1] = { 24'000000000000000000000000 $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN[31:0]$1791 [0] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN[31:0]$1791 [0] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN[31:0]$1791 [0] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN[31:0]$1791 [0] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN[31:0]$1791 [0] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN[31:0]$1791 [0] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN[31:0]$1791 [0] }\n    Consolidated identical input bits for $mux cell $procmux$8606:\n      Old ports: A=0, B=65280, Y=$0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN[31:0]$1794\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN[31:0]$1794 [8]\n      New connections: { $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN[31:0]$1794 [31:9] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN[31:0]$1794 [7:0] } = { 16'0000000000000000 $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN[31:0]$1794 [8] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN[31:0]$1794 [8] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN[31:0]$1794 [8] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN[31:0]$1794 [8] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN[31:0]$1794 [8] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN[31:0]$1794 [8] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_EN[31:0]$1794 [8] 8'00000000 }\n    Consolidated identical input bits for $mux cell $procmux$8612:\n      Old ports: A=0, B=16711680, Y=$0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797 [16]\n      New connections: { $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797 [31:17] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797 [15:0] } = { 8'00000000 $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797 [16] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797 [16] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797 [16] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797 [16] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797 [16] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797 [16] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797 [16] 16'0000000000000000 }\n    Consolidated identical input bits for $mux cell $procmux$8618:\n      Old ports: A=0, B=32'11111111000000000000000000000000, Y=$0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN[31:0]$1800\n      New ports: A=1'0, B=1'1, Y=$0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN[31:0]$1800 [24]\n      New connections: { $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN[31:0]$1800 [31:25] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN[31:0]$1800 [23:0] } = { $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN[31:0]$1800 [24] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN[31:0]$1800 [24] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN[31:0]$1800 [24] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN[31:0]$1800 [24] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN[31:0]$1800 [24] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN[31:0]$1800 [24] $0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5778$234_EN[31:0]$1800 [24] 24'000000000000000000000000 }\n    New ctrl vector for $pmux cell $procmux$8893: { $eq$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3266$1010_Y $procmux$8879_CMP $procmux$8877_CMP $procmux$8876_CMP $procmux$8875_CMP $procmux$8874_CMP $procmux$8873_CMP $eq$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3388$1211_Y $procmux$8894_CMP }\n    New ctrl vector for $pmux cell $procmux$8932: { $procmux$8857_CMP $procmux$8856_CMP $procmux$8855_CMP $procmux$8854_CMP $procmux$8853_CMP $procmux$8852_CMP $procmux$8851_CMP $procmux$8850_CMP $procmux$8849_CMP $procmux$8848_CMP $procmux$8847_CMP $procmux$8846_CMP $procmux$8845_CMP $procmux$8844_CMP $procmux$8843_CMP $eq$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3244$1002_Y }\n  Optimizing cells in module \\top.\nPerformed a total of 104 changes.\n\n4.12.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\n<suppressed ~438 debug messages>\nRemoved a total of 146 cells.\n\n4.12.6. Executing OPT_DFF pass (perform DFF optimizations).\nSetting constant 0-bit at position 0 on $procdff$12190 ($dff) from module top.\nSetting constant 0-bit at position 1 on $procdff$12190 ($dff) from module top.\nSetting constant 0-bit at position 2 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 3 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 4 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 5 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 6 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 7 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 8 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 9 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 10 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 11 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 12 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 13 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 14 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 15 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 16 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 17 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 18 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 19 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 20 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 21 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 22 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 23 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 24 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 25 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 26 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 27 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 28 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 29 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 30 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\nSetting constant 0-bit at position 31 on $flatten\\VexRiscv.$procdff$11842 ($dff) from module top.\n\n4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 0 unused cells and 1393 unused wires.\n<suppressed ~22 debug messages>\n\n4.12.8. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~6 debug messages>\n\n4.12.9. Rerunning OPT passes. (Maybe there is more to do..)\n\n4.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\n    dead port 1/2 on $mux $procmux$10293.\n    dead port 2/2 on $mux $procmux$10293.\n    dead port 1/2 on $mux $procmux$10297.\nRemoved 3 multiplexer ports.\n<suppressed ~1004 debug messages>\n\n4.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$5844: $auto$opt_reduce.cc:134:opt_mux$12497\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$5854: $auto$opt_reduce.cc:134:opt_mux$12499\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$5864: $auto$opt_reduce.cc:134:opt_mux$12501\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$5876: $auto$opt_reduce.cc:134:opt_mux$12503\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$5888: $auto$opt_reduce.cc:134:opt_mux$12505\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$5900: $auto$opt_reduce.cc:134:opt_mux$12507\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$5925: $auto$opt_reduce.cc:134:opt_mux$12509\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$5950: $auto$opt_reduce.cc:134:opt_mux$12511\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$5975: $auto$opt_reduce.cc:134:opt_mux$12513\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6446: $auto$opt_reduce.cc:134:opt_mux$12515\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6462: $auto$opt_reduce.cc:134:opt_mux$12517\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6478: $auto$opt_reduce.cc:134:opt_mux$12519\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$7270: { $auto$opt_reduce.cc:134:opt_mux$12523 $auto$opt_reduce.cc:134:opt_mux$12521 $auto$opt_reduce.cc:134:opt_mux$12387 }\n    New ctrl vector for $pmux cell $procmux$10128: $auto$opt_reduce.cc:134:opt_mux$12393\n  Optimizing cells in module \\top.\nPerformed a total of 14 changes.\n\n4.12.12. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\n<suppressed ~36 debug messages>\nRemoved a total of 12 cells.\n\n4.12.13. Executing OPT_DFF pass (perform DFF optimizations).\nSetting constant 0-bit at position 0 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 1 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 2 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 3 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 4 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 5 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 6 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 7 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 8 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 9 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 10 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 11 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 12 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 13 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 14 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 15 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 16 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 17 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 18 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 19 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 20 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 21 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 22 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 23 on $procdff$12106 ($dff) from module top.\nSetting constant 0-bit at position 0 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 1 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 2 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 3 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 4 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 5 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 6 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 7 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 8 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 9 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 10 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 11 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 12 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 13 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 14 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 15 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 24 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 25 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 26 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 27 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 28 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 29 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 30 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 31 on $procdff$12103 ($dff) from module top.\nSetting constant 0-bit at position 0 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 1 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 2 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 3 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 4 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 5 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 6 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 7 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 16 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 17 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 18 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 19 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 20 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 21 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 22 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 23 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 24 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 25 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 26 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 27 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 28 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 29 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 30 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 31 on $procdff$12100 ($dff) from module top.\nSetting constant 0-bit at position 8 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 9 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 10 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 11 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 12 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 13 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 14 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 15 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 16 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 17 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 18 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 19 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 20 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 21 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 22 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 23 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 24 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 25 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 26 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 27 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 28 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 29 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 30 on $procdff$12097 ($dff) from module top.\nSetting constant 0-bit at position 31 on $procdff$12097 ($dff) from module top.\n\n4.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 1 unused cells and 17 unused wires.\n<suppressed ~4 debug messages>\n\n4.12.15. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.12.16. Rerunning OPT passes. (Maybe there is more to do..)\n\n4.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~1004 debug messages>\n\n4.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\nPerformed a total of 0 changes.\n\n4.12.19. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.12.20. Executing OPT_DFF pass (perform DFF optimizations).\n\n4.12.21. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.12.22. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.12.23. Finished OPT passes. (There is nothing left to do.)\n\n4.13. Executing FSM pass (extract and optimize FSM).\n\n4.13.1. Executing FSM_DETECT pass (finding FSMs in design).\nNot marking top.$flatten\\VexRiscv.$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3194$2495_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:176$3834_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$flatten\\VexRiscv.\\dataCache_1_.$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:570$3617_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$flatten\\VexRiscv.\\dataCache_1_.$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:573$3618_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$flatten\\VexRiscv.\\dataCache_1_.$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:576$3619_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$flatten\\VexRiscv.\\dataCache_1_.$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:579$3620_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$flatten\\VexRiscv.\\dataCache_1_.$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:555$3616_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5959$242_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5969$243_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6059$252_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6069$253_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6079$254_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6089$255_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6099$256_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6109$257_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5979$244_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5989$245_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5999$246_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6009$247_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6019$248_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6029$249_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6039$250_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6049$251_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_EN as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_code as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.VexRiscv.CsrPlugin_interrupt_code as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.VexRiscv.CsrPlugin_interrupt_targetPrivilege as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.VexRiscv.MmuPlugin_shared_state_1_ as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.VexRiscv._zz_137_ as FSM state register:\n    Users of register don't seem to benefit from recoding.\nNot marking top.builder_bankmachine0_state as FSM state register:\n    Register has an initialization value.\nNot marking top.builder_bankmachine1_state as FSM state register:\n    Register has an initialization value.\nNot marking top.builder_bankmachine2_state as FSM state register:\n    Register has an initialization value.\nNot marking top.builder_bankmachine3_state as FSM state register:\n    Register has an initialization value.\nNot marking top.builder_fullmemorywe_state as FSM state register:\n    Register has an initialization value.\nNot marking top.builder_multiplexer_state as FSM state register:\n    Register has an initialization value.\nNot marking top.builder_refresher_state as FSM state register:\n    Register has an initialization value.\nNot marking top.builder_spimaster_state as FSM state register:\n    Register has an initialization value.\nNot marking top.builder_state as FSM state register:\n    Register has an initialization value.\nNot marking top.main_sdram_choose_req_grant as FSM state register:\n    Register has an initialization value.\nNot marking top.main_sdram_cmd_payload_a as FSM state register:\n    Users of register don't seem to benefit from recoding.\n    Register has an initialization value.\nNot marking top.main_sdram_dfi_p0_bank as FSM state register:\n    Users of register don't seem to benefit from recoding.\n    Register has an initialization value.\n\n4.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).\n\n4.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).\n\n4.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).\n\n4.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).\n\n4.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).\n\n4.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).\n\n4.14. Executing OPT pass (performing simple optimizations).\n\n4.14.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.14.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~1004 debug messages>\n\n4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\nPerformed a total of 0 changes.\n\n4.14.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.14.6. Executing OPT_DFF pass (perform DFF optimizations).\nAdding SRST signal on $procdff$12335 ($dff) from module top (D = \\builder_next_state, Q = \\builder_state, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12524 ($sdff) from module top (D = \\builder_next_state, Q = \\builder_state).\nAdding SRST signal on $procdff$12334 ($dff) from module top (D = $procmux$8811_Y, Q = \\builder_csr_bankarray_interface7_bank_bus_dat_r, rval = 8'00000000).\nAdding SRST signal on $procdff$12333 ($dff) from module top (D = $procmux$8820_Y, Q = \\builder_csr_bankarray_interface6_bank_bus_dat_r, rval = 8'00000000).\nAdding SRST signal on $procdff$12332 ($dff) from module top (D = $procmux$8841_Y, Q = \\builder_csr_bankarray_interface5_bank_bus_dat_r, rval = 8'00000000).\nAdding SRST signal on $procdff$12331 ($dff) from module top (D = $procmux$8871_Y, Q = \\builder_csr_bankarray_interface4_bank_bus_dat_r, rval = 8'00000000).\nAdding SRST signal on $procdff$12330 ($dff) from module top (D = $procmux$8893_Y, Q = \\builder_csr_bankarray_interface3_bank_bus_dat_r, rval = 8'00000000).\nAdding SRST signal on $procdff$12329 ($dff) from module top (D = \\main_storage, Q = \\builder_csr_bankarray_interface2_bank_bus_dat_r, rval = 8'00000000).\nAdding SRST signal on $procdff$12328 ($dff) from module top (D = \\builder_csr_bankarray_sel, Q = \\builder_csr_bankarray_sel_r, rval = 1'0).\nAdding SRST signal on $procdff$12327 ($dff) from module top (D = $procmux$8918_Y, Q = \\builder_csr_bankarray_interface1_bank_bus_dat_r, rval = 8'00000000).\nAdding SRST signal on $procdff$12326 ($dff) from module top (D = $procmux$8932_Y, Q = \\builder_csr_bankarray_interface0_bank_bus_dat_r, rval = 8'00000000).\nAdding SRST signal on $procdff$12325 ($dff) from module top (D = $procmux$9109_Y, Q = \\builder_count, rval = 20'11110100001001000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12545 ($sdff) from module top (D = $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5128$1785_Y, Q = \\builder_count).\nAdding SRST signal on $procdff$12324 ($dff) from module top (D = \\builder_slave_sel, Q = \\builder_slave_sel_r, rval = 4'0000).\nAdding SRST signal on $procdff$12323 ($dff) from module top (D = $procmux$9119_Y, Q = \\builder_grant, rval = 1'0).\nAdding EN signal on $procdff$12322 ($dff) from module top (D = \\builder_soclinux_wishbone_dat_w [7:0], Q = \\builder_soclinux_dat_w).\nAdding SRST signal on $procdff$12321 ($dff) from module top (D = $procmux$9130_Y, Q = \\builder_soclinux_we, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12550 ($sdff) from module top (D = \\builder_soclinux_we_next_value2, Q = \\builder_soclinux_we).\nAdding EN signal on $procdff$12320 ($dff) from module top (D = \\builder_soclinux_adr_next_value1, Q = \\builder_soclinux_adr).\nAdding SRST signal on $auto$opt_dff.cc:764:run$12552 ($dffe) from module top (D = { \\builder_shared_adr [13:11] \\builder_soclinux_wishbone_adr [10:0] }, Q = \\builder_soclinux_adr, rval = 14'00000000000000).\nAdding SRST signal on $procdff$12319 ($dff) from module top (D = \\builder_spimaster_next_state, Q = \\builder_spimaster_state, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12558 ($sdff) from module top (D = \\builder_spimaster_next_state, Q = \\builder_spimaster_state).\nAdding SRST signal on $procdff$12318 ($dff) from module top (D = \\builder_litedramwishbone2native_next_state, Q = \\builder_litedramwishbone2native_state, rval = 1'0).\nAdding SRST signal on $procdff$12317 ($dff) from module top (D = \\builder_fullmemorywe_next_state, Q = \\builder_fullmemorywe_state, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12573 ($sdff) from module top (D = \\builder_fullmemorywe_next_state, Q = \\builder_fullmemorywe_state).\nAdding SRST signal on $procdff$12316 ($dff) from module top (D = \\builder_new_master_rdata_valid2, Q = \\builder_new_master_rdata_valid3, rval = 1'0).\nAdding SRST signal on $procdff$12315 ($dff) from module top (D = \\builder_new_master_rdata_valid1, Q = \\builder_new_master_rdata_valid2, rval = 1'0).\nAdding SRST signal on $procdff$12314 ($dff) from module top (D = \\builder_new_master_rdata_valid0, Q = \\builder_new_master_rdata_valid1, rval = 1'0).\nAdding SRST signal on $procdff$12313 ($dff) from module top (D = $or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4967$1760_Y, Q = \\builder_new_master_rdata_valid0, rval = 1'0).\nAdding SRST signal on $procdff$12312 ($dff) from module top (D = $or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4966$1748_Y, Q = \\builder_new_master_wdata_ready, rval = 1'0).\nAdding SRST signal on $procdff$12311 ($dff) from module top (D = \\builder_multiplexer_next_state, Q = \\builder_multiplexer_state, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12588 ($sdff) from module top (D = \\builder_multiplexer_next_state, Q = \\builder_multiplexer_state).\nAdding SRST signal on $procdff$12310 ($dff) from module top (D = \\builder_bankmachine3_next_state, Q = \\builder_bankmachine3_state, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12604 ($sdff) from module top (D = \\builder_bankmachine3_next_state, Q = \\builder_bankmachine3_state).\nAdding SRST signal on $procdff$12309 ($dff) from module top (D = \\builder_bankmachine2_next_state, Q = \\builder_bankmachine2_state, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12624 ($sdff) from module top (D = \\builder_bankmachine2_next_state, Q = \\builder_bankmachine2_state).\nAdding SRST signal on $procdff$12308 ($dff) from module top (D = \\builder_bankmachine1_next_state, Q = \\builder_bankmachine1_state, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12644 ($sdff) from module top (D = \\builder_bankmachine1_next_state, Q = \\builder_bankmachine1_state).\nAdding SRST signal on $procdff$12307 ($dff) from module top (D = \\builder_bankmachine0_next_state, Q = \\builder_bankmachine0_state, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12664 ($sdff) from module top (D = \\builder_bankmachine0_next_state, Q = \\builder_bankmachine0_state).\nAdding SRST signal on $procdff$12306 ($dff) from module top (D = \\builder_refresher_next_state, Q = \\builder_refresher_state, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12684 ($sdff) from module top (D = \\builder_refresher_next_state, Q = \\builder_refresher_state).\nAdding SRST signal on $procdff$12304 ($dff) from module top (D = { $procmux$8624_Y $procmux$9859_Y }, Q = \\soclinux_storage, rval = 16'0000000001111101).\nAdding EN signal on $auto$opt_dff.cc:702:run$12694 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\soclinux_storage [15:8]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12694 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\soclinux_storage [7:0]).\nAdding SRST signal on $procdff$12303 ($dff) from module top (D = $procmux$9143_Y, Q = \\soclinux_miso_data, rval = 8'00000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12697 ($sdff) from module top (D = $procmux$9141_Y, Q = \\soclinux_miso_data).\nAdding SRST signal on $procdff$12302 ($dff) from module top (D = $procmux$9150_Y, Q = \\soclinux_mosi_sel, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12699 ($sdff) from module top (D = $procmux$9150_Y, Q = \\soclinux_mosi_sel).\nAdding SRST signal on $procdff$12301 ($dff) from module top (D = $procmux$9155_Y, Q = \\soclinux_mosi_data, rval = 8'00000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12703 ($sdff) from module top (D = \\soclinux_mosi_storage, Q = \\soclinux_mosi_data).\nAdding SRST signal on $procdff$12300 ($dff) from module top (D = $procmux$8963_Y, Q = \\soclinux_clk_divider1, rval = 16'0000000000000000).\nAdding SRST signal on $procdff$12299 ($dff) from module top (D = $procmux$9159_Y, Q = \\soclinux_count, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12706 ($sdff) from module top (D = \\soclinux_count_spimaster_next_value, Q = \\soclinux_count).\nAdding SRST signal on $procdff$12297 ($dff) from module top (D = $procmux$9163_Y, Q = \\soclinux_loopback_storage, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12708 ($sdff) from module top (D = \\builder_soclinux_dat_w [0], Q = \\soclinux_loopback_storage).\nAdding SRST signal on $procdff$12295 ($dff) from module top (D = $procmux$9167_Y, Q = \\soclinux_cs_storage, rval = 1'1).\nAdding EN signal on $auto$opt_dff.cc:702:run$12710 ($sdff) from module top (D = \\builder_soclinux_dat_w [0], Q = \\soclinux_cs_storage).\nAdding EN signal on $procdff$12293 ($dff) from module top (D = \\builder_soclinux_dat_w, Q = \\soclinux_mosi_storage).\nAdding SRST signal on $procdff$12292 ($dff) from module top (D = \\builder_csr_bankarray_csrbank4_control0_re, Q = \\soclinux_control_re, rval = 1'0).\nAdding SRST signal on $procdff$12291 ($dff) from module top (D = { $procmux$8671_Y $procmux$9136_Y }, Q = \\soclinux_control_storage, rval = 16'0000000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12714 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\soclinux_control_storage [15:8]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12714 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\soclinux_control_storage [7:0]).\nAdding SRST signal on $procdff$12290 ($dff) from module top (D = $procmux$9175_Y, Q = \\soclinux_miso, rval = 8'00000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12717 ($sdff) from module top (D = \\soclinux_miso_data, Q = \\soclinux_miso).\nAdding SRST signal on $procdff$12289 ($dff) from module top (D = $procmux$9180_Y, Q = \\main_count, rval = 22'1011111010111100001000).\nAdding SRST signal on $procdff$12288 ($dff) from module top (D = $procmux$9186_Y, Q = \\main_mode, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12722 ($sdff) from module top (D = 1'1, Q = \\main_mode).\nAdding SRST signal on $procdff$12287 ($dff) from module top (D = $procmux$9190_Y, Q = \\main_chaser, rval = 8'00000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12724 ($sdff) from module top (D = { \\main_chaser [6:0] $not$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5052$1774_Y }, Q = \\main_chaser).\nAdding SRST signal on $procdff$12286 ($dff) from module top (D = \\builder_csr_bankarray_csrbank2_out0_re, Q = \\main_re, rval = 1'0).\nAdding SRST signal on $procdff$12285 ($dff) from module top (D = $procmux$9194_Y, Q = \\main_storage, rval = 8'00000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12727 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_storage).\nAdding SRST signal on $procdff$12284 ($dff) from module top (D = $procmux$9198_Y, Q = \\main_wishbone_bridge_wdata_consumed, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12731 ($sdff) from module top (D = 1'1, Q = \\main_wishbone_bridge_wdata_consumed).\nAdding SRST signal on $procdff$12283 ($dff) from module top (D = $procmux$9205_Y, Q = \\main_wishbone_bridge_cmd_consumed, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12735 ($sdff) from module top (D = 1'1, Q = \\main_wishbone_bridge_cmd_consumed).\nAdding SRST signal on $procdff$12282 ($dff) from module top (D = $procmux$9217_Y, Q = \\main_wishbone_bridge_rdata_converter_converter_strobe_all, rval = 1'0).\nAdding SRST signal on $procdff$12281 ($dff) from module top (D = $procmux$9224_Y, Q = \\main_wishbone_bridge_rdata_converter_converter_demux, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12738 ($sdff) from module top (D = $procmux$9222_Y, Q = \\main_wishbone_bridge_rdata_converter_converter_demux).\nAdding SRST signal on $procdff$12279 ($dff) from module top (D = { $procmux$8677_Y $procmux$10037_Y $procmux$8729_Y $procmux$8738_Y $procmux$8748_Y $procmux$8759_Y $procmux$8771_Y $procmux$8784_Y }, Q = \\main_wishbone_bridge_rdata_converter_converter_source_payload_data, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12740 ($sdff) from module top (D = \\main_wishbone_bridge_rdata_converter_converter_sink_payload_data, Q = \\main_wishbone_bridge_rdata_converter_converter_source_payload_data [127:112]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12740 ($sdff) from module top (D = \\main_wishbone_bridge_rdata_converter_converter_sink_payload_data, Q = \\main_wishbone_bridge_rdata_converter_converter_source_payload_data [95:80]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12740 ($sdff) from module top (D = \\main_wishbone_bridge_rdata_converter_converter_sink_payload_data, Q = \\main_wishbone_bridge_rdata_converter_converter_source_payload_data [79:64]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12740 ($sdff) from module top (D = \\main_wishbone_bridge_rdata_converter_converter_sink_payload_data, Q = \\main_wishbone_bridge_rdata_converter_converter_source_payload_data [63:48]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12740 ($sdff) from module top (D = \\main_wishbone_bridge_rdata_converter_converter_sink_payload_data, Q = \\main_wishbone_bridge_rdata_converter_converter_source_payload_data [47:32]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12740 ($sdff) from module top (D = \\main_wishbone_bridge_rdata_converter_converter_sink_payload_data, Q = \\main_wishbone_bridge_rdata_converter_converter_source_payload_data [31:16]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12740 ($sdff) from module top (D = \\main_wishbone_bridge_rdata_converter_converter_sink_payload_data, Q = \\main_wishbone_bridge_rdata_converter_converter_source_payload_data [15:0]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12740 ($sdff) from module top (D = \\main_wishbone_bridge_rdata_converter_converter_sink_payload_data, Q = \\main_wishbone_bridge_rdata_converter_converter_source_payload_data [111:96]).\nAdding SRST signal on $procdff$12276 ($dff) from module top (D = $procmux$9256_Y, Q = \\main_wishbone_bridge_wdata_converter_converter_mux, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12765 ($sdff) from module top (D = $procmux$9254_Y, Q = \\main_wishbone_bridge_wdata_converter_converter_mux).\nAdding SRST signal on $procdff$12275 ($dff) from module top (D = $procmux$9260_Y, Q = \\main_wishbone_bridge_count, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12767 ($sdff) from module top (D = \\main_wishbone_bridge_count_litedramwishbone2native_next_value, Q = \\main_wishbone_bridge_count).\nAdding SRST signal on $procdff$12273 ($dff) from module top (D = $procmux$9267_Y, Q = \\main_sdram_time1, rval = 4'0000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12769 ($sdff) from module top (D = $procmux$9267_Y, Q = \\main_sdram_time1).\nAdding SRST signal on $procdff$12272 ($dff) from module top (D = $procmux$9274_Y, Q = \\main_sdram_time0, rval = 5'00000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12773 ($sdff) from module top (D = $procmux$9274_Y, Q = \\main_sdram_time0).\nAdding SRST signal on $procdff$12271 ($dff) from module top (D = $procmux$9281_Y [2], Q = \\main_sdram_twtrcon_count [2], rval = 1'0).\nAdding SRST signal on $procdff$12271 ($dff) from module top (D = $procmux$9278_Y [1:0], Q = \\main_sdram_twtrcon_count [1:0], rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12780 ($sdff) from module top (D = $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4959$1735_Y [1:0], Q = \\main_sdram_twtrcon_count [1:0]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12777 ($sdff) from module top (D = $procmux$9281_Y [2], Q = \\main_sdram_twtrcon_count [2]).\nAdding SRST signal on $procdff$12270 ($dff) from module top (D = $procmux$9287_Y, Q = \\main_sdram_twtrcon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12269 ($dff) from module top (D = $procmux$9294_Y, Q = \\main_sdram_tccdcon_count, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12790 ($sdff) from module top (D = $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4944$1732_Y, Q = \\main_sdram_tccdcon_count).\nAdding SRST signal on $procdff$12268 ($dff) from module top (D = $procmux$9306_Y, Q = \\main_sdram_tccdcon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12267 ($dff) from module top (D = $procmux$9310_Y, Q = \\main_sdram_trrdcon_count, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12795 ($sdff) from module top (D = $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4929$1729_Y, Q = \\main_sdram_trrdcon_count).\nAdding SRST signal on $procdff$12266 ($dff) from module top (D = $procmux$9322_Y, Q = \\main_sdram_trrdcon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12265 ($dff) from module top (D = $procmux$9363_Y, Q = \\main_sdram_choose_req_grant, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12798 ($sdff) from module top (D = $procmux$9334_Y, Q = \\main_sdram_choose_req_grant).\nAdding SRST signal on $procdff$12263 ($dff) from module top (D = $procmux$9411_Y [1], Q = \\main_sdram_bankmachine3_trascon_count [1], rval = 1'0).\nAdding SRST signal on $procdff$12263 ($dff) from module top (D = $procmux$9408_Y [0], Q = \\main_sdram_bankmachine3_trascon_count [0], rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12815 ($sdff) from module top (D = $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4779$1717_Y [0], Q = \\main_sdram_bankmachine3_trascon_count [0]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12812 ($sdff) from module top (D = $procmux$9411_Y [1], Q = \\main_sdram_bankmachine3_trascon_count [1]).\nAdding SRST signal on $procdff$12262 ($dff) from module top (D = $procmux$9417_Y, Q = \\main_sdram_bankmachine3_trascon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12261 ($dff) from module top (D = $procmux$9427_Y, Q = \\main_sdram_bankmachine3_trccon_count, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12823 ($sdff) from module top (D = $procmux$9427_Y, Q = \\main_sdram_bankmachine3_trccon_count).\nAdding SRST signal on $procdff$12260 ($dff) from module top (D = $procmux$9433_Y, Q = \\main_sdram_bankmachine3_trccon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12259 ($dff) from module top (D = $procmux$9443_Y, Q = \\main_sdram_bankmachine3_twtpcon_count, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12830 ($sdff) from module top (D = $procmux$9443_Y, Q = \\main_sdram_bankmachine3_twtpcon_count).\nAdding SRST signal on $procdff$12258 ($dff) from module top (D = $procmux$9449_Y, Q = \\main_sdram_bankmachine3_twtpcon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12257 ($dff) from module top (D = $procmux$9456_Y, Q = \\main_sdram_bankmachine3_row_opened, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12839 ($sdff) from module top (D = 1'1, Q = \\main_sdram_bankmachine3_row_opened).\nAdding SRST signal on $procdff$12256 ($dff) from module top (D = $procmux$9466_Y, Q = \\main_sdram_bankmachine3_row, rval = 13'0000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12841 ($sdff) from module top (D = \\main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9], Q = \\main_sdram_bankmachine3_row).\nAdding SRST signal on $procdff$12255 ($dff) from module top (D = $procmux$9470_Y, Q = \\main_sdram_bankmachine3_cmd_buffer_source_payload_addr, rval = 22'0000000000000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12847 ($sdff) from module top (D = \\main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r [22:1], Q = \\main_sdram_bankmachine3_cmd_buffer_source_payload_addr).\nAdding SRST signal on $procdff$12254 ($dff) from module top (D = $procmux$9474_Y, Q = \\main_sdram_bankmachine3_cmd_buffer_source_payload_we, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12849 ($sdff) from module top (D = \\main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r [0], Q = \\main_sdram_bankmachine3_cmd_buffer_source_payload_we).\nAdding SRST signal on $procdff$12251 ($dff) from module top (D = $procmux$9482_Y, Q = \\main_sdram_bankmachine3_cmd_buffer_source_valid, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12851 ($sdff) from module top (D = \\main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid, Q = \\main_sdram_bankmachine3_cmd_buffer_source_valid).\nAdding SRST signal on $procdff$12250 ($dff) from module top (D = $procmux$9486_Y, Q = \\main_sdram_bankmachine3_cmd_buffer_lookahead_consume, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12853 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4722$1701_Y, Q = \\main_sdram_bankmachine3_cmd_buffer_lookahead_consume).\nAdding SRST signal on $procdff$12249 ($dff) from module top (D = $procmux$9490_Y, Q = \\main_sdram_bankmachine3_cmd_buffer_lookahead_produce, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12855 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4719$1700_Y, Q = \\main_sdram_bankmachine3_cmd_buffer_lookahead_produce).\nAdding SRST signal on $procdff$12248 ($dff) from module top (D = $procmux$9499_Y, Q = \\main_sdram_bankmachine3_cmd_buffer_lookahead_level, rval = 4'0000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12857 ($sdff) from module top (D = $procmux$9499_Y, Q = \\main_sdram_bankmachine3_cmd_buffer_lookahead_level).\nAdding SRST signal on $procdff$12247 ($dff) from module top (D = $procmux$9506_Y [1], Q = \\main_sdram_bankmachine2_trascon_count [1], rval = 1'0).\nAdding SRST signal on $procdff$12247 ($dff) from module top (D = $procmux$9503_Y [0], Q = \\main_sdram_bankmachine2_trascon_count [0], rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12868 ($sdff) from module top (D = $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4703$1695_Y [0], Q = \\main_sdram_bankmachine2_trascon_count [0]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12865 ($sdff) from module top (D = $procmux$9506_Y [1], Q = \\main_sdram_bankmachine2_trascon_count [1]).\nAdding SRST signal on $procdff$12246 ($dff) from module top (D = $procmux$9512_Y, Q = \\main_sdram_bankmachine2_trascon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12245 ($dff) from module top (D = $procmux$9522_Y, Q = \\main_sdram_bankmachine2_trccon_count, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12876 ($sdff) from module top (D = $procmux$9522_Y, Q = \\main_sdram_bankmachine2_trccon_count).\nAdding SRST signal on $procdff$12244 ($dff) from module top (D = $procmux$9528_Y, Q = \\main_sdram_bankmachine2_trccon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12243 ($dff) from module top (D = $procmux$9538_Y, Q = \\main_sdram_bankmachine2_twtpcon_count, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12883 ($sdff) from module top (D = $procmux$9538_Y, Q = \\main_sdram_bankmachine2_twtpcon_count).\nAdding SRST signal on $procdff$12242 ($dff) from module top (D = $procmux$9544_Y, Q = \\main_sdram_bankmachine2_twtpcon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12241 ($dff) from module top (D = $procmux$9551_Y, Q = \\main_sdram_bankmachine2_row_opened, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12892 ($sdff) from module top (D = 1'1, Q = \\main_sdram_bankmachine2_row_opened).\nAdding SRST signal on $procdff$12240 ($dff) from module top (D = $procmux$9561_Y, Q = \\main_sdram_bankmachine2_row, rval = 13'0000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12894 ($sdff) from module top (D = \\main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9], Q = \\main_sdram_bankmachine2_row).\nAdding SRST signal on $procdff$12239 ($dff) from module top (D = $procmux$9565_Y, Q = \\main_sdram_bankmachine2_cmd_buffer_source_payload_addr, rval = 22'0000000000000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12900 ($sdff) from module top (D = \\main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r [22:1], Q = \\main_sdram_bankmachine2_cmd_buffer_source_payload_addr).\nAdding SRST signal on $procdff$12238 ($dff) from module top (D = $procmux$9569_Y, Q = \\main_sdram_bankmachine2_cmd_buffer_source_payload_we, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12902 ($sdff) from module top (D = \\main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r [0], Q = \\main_sdram_bankmachine2_cmd_buffer_source_payload_we).\nAdding SRST signal on $procdff$12235 ($dff) from module top (D = $procmux$9577_Y, Q = \\main_sdram_bankmachine2_cmd_buffer_source_valid, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12904 ($sdff) from module top (D = \\main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid, Q = \\main_sdram_bankmachine2_cmd_buffer_source_valid).\nAdding SRST signal on $procdff$12234 ($dff) from module top (D = $procmux$9581_Y, Q = \\main_sdram_bankmachine2_cmd_buffer_lookahead_consume, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12906 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4646$1679_Y, Q = \\main_sdram_bankmachine2_cmd_buffer_lookahead_consume).\nAdding SRST signal on $procdff$12233 ($dff) from module top (D = $procmux$9585_Y, Q = \\main_sdram_bankmachine2_cmd_buffer_lookahead_produce, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12908 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4643$1678_Y, Q = \\main_sdram_bankmachine2_cmd_buffer_lookahead_produce).\nAdding SRST signal on $procdff$12232 ($dff) from module top (D = $procmux$9594_Y, Q = \\main_sdram_bankmachine2_cmd_buffer_lookahead_level, rval = 4'0000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12910 ($sdff) from module top (D = $procmux$9594_Y, Q = \\main_sdram_bankmachine2_cmd_buffer_lookahead_level).\nAdding SRST signal on $procdff$12231 ($dff) from module top (D = $procmux$9601_Y [1], Q = \\main_sdram_bankmachine1_trascon_count [1], rval = 1'0).\nAdding SRST signal on $procdff$12231 ($dff) from module top (D = $procmux$9598_Y [0], Q = \\main_sdram_bankmachine1_trascon_count [0], rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12921 ($sdff) from module top (D = $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4627$1673_Y [0], Q = \\main_sdram_bankmachine1_trascon_count [0]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12918 ($sdff) from module top (D = $procmux$9601_Y [1], Q = \\main_sdram_bankmachine1_trascon_count [1]).\nAdding SRST signal on $procdff$12230 ($dff) from module top (D = $procmux$9607_Y, Q = \\main_sdram_bankmachine1_trascon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12229 ($dff) from module top (D = $procmux$9617_Y, Q = \\main_sdram_bankmachine1_trccon_count, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12929 ($sdff) from module top (D = $procmux$9617_Y, Q = \\main_sdram_bankmachine1_trccon_count).\nAdding SRST signal on $procdff$12228 ($dff) from module top (D = $procmux$9623_Y, Q = \\main_sdram_bankmachine1_trccon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12227 ($dff) from module top (D = $procmux$9633_Y, Q = \\main_sdram_bankmachine1_twtpcon_count, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12936 ($sdff) from module top (D = $procmux$9633_Y, Q = \\main_sdram_bankmachine1_twtpcon_count).\nAdding SRST signal on $procdff$12226 ($dff) from module top (D = $procmux$9639_Y, Q = \\main_sdram_bankmachine1_twtpcon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12225 ($dff) from module top (D = $procmux$9646_Y, Q = \\main_sdram_bankmachine1_row_opened, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12945 ($sdff) from module top (D = 1'1, Q = \\main_sdram_bankmachine1_row_opened).\nAdding SRST signal on $procdff$12224 ($dff) from module top (D = $procmux$9656_Y, Q = \\main_sdram_bankmachine1_row, rval = 13'0000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12947 ($sdff) from module top (D = \\main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9], Q = \\main_sdram_bankmachine1_row).\nAdding SRST signal on $procdff$12223 ($dff) from module top (D = $procmux$9660_Y, Q = \\main_sdram_bankmachine1_cmd_buffer_source_payload_addr, rval = 22'0000000000000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12953 ($sdff) from module top (D = \\main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r [22:1], Q = \\main_sdram_bankmachine1_cmd_buffer_source_payload_addr).\nAdding SRST signal on $procdff$12222 ($dff) from module top (D = $procmux$9664_Y, Q = \\main_sdram_bankmachine1_cmd_buffer_source_payload_we, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12955 ($sdff) from module top (D = \\main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r [0], Q = \\main_sdram_bankmachine1_cmd_buffer_source_payload_we).\nAdding SRST signal on $procdff$12219 ($dff) from module top (D = $procmux$9672_Y, Q = \\main_sdram_bankmachine1_cmd_buffer_source_valid, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12957 ($sdff) from module top (D = \\main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid, Q = \\main_sdram_bankmachine1_cmd_buffer_source_valid).\nAdding SRST signal on $procdff$12218 ($dff) from module top (D = $procmux$9676_Y, Q = \\main_sdram_bankmachine1_cmd_buffer_lookahead_consume, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12959 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4570$1657_Y, Q = \\main_sdram_bankmachine1_cmd_buffer_lookahead_consume).\nAdding SRST signal on $procdff$12217 ($dff) from module top (D = $procmux$9680_Y, Q = \\main_sdram_bankmachine1_cmd_buffer_lookahead_produce, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12961 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4567$1656_Y, Q = \\main_sdram_bankmachine1_cmd_buffer_lookahead_produce).\nAdding SRST signal on $procdff$12216 ($dff) from module top (D = $procmux$9689_Y, Q = \\main_sdram_bankmachine1_cmd_buffer_lookahead_level, rval = 4'0000).\nAdding EN signal on $auto$opt_dff.cc:702:run$12963 ($sdff) from module top (D = $procmux$9689_Y, Q = \\main_sdram_bankmachine1_cmd_buffer_lookahead_level).\nAdding SRST signal on $procdff$12215 ($dff) from module top (D = $procmux$9696_Y [1], Q = \\main_sdram_bankmachine0_trascon_count [1], rval = 1'0).\nAdding SRST signal on $procdff$12215 ($dff) from module top (D = $procmux$9693_Y [0], Q = \\main_sdram_bankmachine0_trascon_count [0], rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12974 ($sdff) from module top (D = $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4551$1651_Y [0], Q = \\main_sdram_bankmachine0_trascon_count [0]).\nAdding EN signal on $auto$opt_dff.cc:702:run$12971 ($sdff) from module top (D = $procmux$9696_Y [1], Q = \\main_sdram_bankmachine0_trascon_count [1]).\nAdding SRST signal on $procdff$12214 ($dff) from module top (D = $procmux$9702_Y, Q = \\main_sdram_bankmachine0_trascon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12213 ($dff) from module top (D = $procmux$9712_Y, Q = \\main_sdram_bankmachine0_trccon_count, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12982 ($sdff) from module top (D = $procmux$9712_Y, Q = \\main_sdram_bankmachine0_trccon_count).\nAdding SRST signal on $procdff$12212 ($dff) from module top (D = $procmux$9718_Y, Q = \\main_sdram_bankmachine0_trccon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12211 ($dff) from module top (D = $procmux$9728_Y, Q = \\main_sdram_bankmachine0_twtpcon_count, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$12989 ($sdff) from module top (D = $procmux$9728_Y, Q = \\main_sdram_bankmachine0_twtpcon_count).\nAdding SRST signal on $procdff$12210 ($dff) from module top (D = $procmux$9734_Y, Q = \\main_sdram_bankmachine0_twtpcon_ready, rval = 1'0).\nAdding SRST signal on $procdff$12209 ($dff) from module top (D = $procmux$9741_Y, Q = \\main_sdram_bankmachine0_row_opened, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$12998 ($sdff) from module top (D = 1'1, Q = \\main_sdram_bankmachine0_row_opened).\nAdding SRST signal on $procdff$12208 ($dff) from module top (D = $procmux$9751_Y, Q = \\main_sdram_bankmachine0_row, rval = 13'0000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13000 ($sdff) from module top (D = \\main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9], Q = \\main_sdram_bankmachine0_row).\nAdding SRST signal on $procdff$12207 ($dff) from module top (D = $procmux$9755_Y, Q = \\main_sdram_bankmachine0_cmd_buffer_source_payload_addr, rval = 22'0000000000000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13006 ($sdff) from module top (D = \\main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r [22:1], Q = \\main_sdram_bankmachine0_cmd_buffer_source_payload_addr).\nAdding SRST signal on $procdff$12206 ($dff) from module top (D = $procmux$9759_Y, Q = \\main_sdram_bankmachine0_cmd_buffer_source_payload_we, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13008 ($sdff) from module top (D = \\main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r [0], Q = \\main_sdram_bankmachine0_cmd_buffer_source_payload_we).\nAdding SRST signal on $procdff$12203 ($dff) from module top (D = $procmux$9767_Y, Q = \\main_sdram_bankmachine0_cmd_buffer_source_valid, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13010 ($sdff) from module top (D = \\main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid, Q = \\main_sdram_bankmachine0_cmd_buffer_source_valid).\nAdding SRST signal on $procdff$12202 ($dff) from module top (D = $procmux$9771_Y, Q = \\main_sdram_bankmachine0_cmd_buffer_lookahead_consume, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13012 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4494$1635_Y, Q = \\main_sdram_bankmachine0_cmd_buffer_lookahead_consume).\nAdding SRST signal on $procdff$12201 ($dff) from module top (D = $procmux$9775_Y, Q = \\main_sdram_bankmachine0_cmd_buffer_lookahead_produce, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13014 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4491$1634_Y, Q = \\main_sdram_bankmachine0_cmd_buffer_lookahead_produce).\nAdding SRST signal on $procdff$12200 ($dff) from module top (D = $procmux$9784_Y, Q = \\main_sdram_bankmachine0_cmd_buffer_lookahead_level, rval = 4'0000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13016 ($sdff) from module top (D = $procmux$9784_Y, Q = \\main_sdram_bankmachine0_cmd_buffer_lookahead_level).\nAdding SRST signal on $procdff$12199 ($dff) from module top (D = $procmux$9790_Y, Q = \\main_sdram_sequencer_count, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13026 ($sdff) from module top (D = $procmux$9788_Y, Q = \\main_sdram_sequencer_count).\nAdding SRST signal on $procdff$12198 ($dff) from module top (D = $procmux$9800_Y, Q = \\main_sdram_sequencer_counter, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13030 ($sdff) from module top (D = $procmux$9800_Y, Q = \\main_sdram_sequencer_counter).\nAdding SRST signal on $procdff$12197 ($dff) from module top (D = $procmux$9009_Y, Q = \\main_sdram_sequencer_done1, rval = 1'0).\nAdding SRST signal on $procdff$12196 ($dff) from module top (D = $procmux$9809_Y, Q = \\main_sdram_postponer_count, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13035 ($sdff) from module top (D = $procmux$9807_Y, Q = \\main_sdram_postponer_count).\nAdding SRST signal on $procdff$12195 ($dff) from module top (D = $procmux$9048_Y, Q = \\main_sdram_postponer_req_o, rval = 1'0).\nAdding SRST signal on $procdff$12194 ($dff) from module top (D = $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4421$1619_Y, Q = \\main_sdram_timer_count1, rval = 9'110000110).\nAdding SRST signal on $procdff$12193 ($dff) from module top (D = $procmux$9013_Y, Q = \\main_sdram_cmd_payload_we, rval = 1'0).\nAdding SRST signal on $procdff$12192 ($dff) from module top (D = $procmux$9023_Y, Q = \\main_sdram_cmd_payload_ras, rval = 1'0).\nAdding SRST signal on $procdff$12191 ($dff) from module top (D = $procmux$9030_Y, Q = \\main_sdram_cmd_payload_cas, rval = 1'0).\nAdding SRST signal on $procdff$12189 ($dff) from module top (D = $procmux$9040_Y, Q = \\main_sdram_cmd_payload_a, rval = 13'0000000000000).\nAdding SRST signal on $procdff$12188 ($dff) from module top (D = $and$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4150$1547_Y, Q = \\main_sdram_dfi_p0_rddata_en, rval = 1'0).\nAdding SRST signal on $procdff$12187 ($dff) from module top (D = \\main_sdram_twtrcon_valid, Q = \\main_sdram_dfi_p0_wrdata_en, rval = 1'0).\nAdding SRST signal on $procdff$12186 ($dff) from module top (D = $not$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4917$1727_Y, Q = \\main_sdram_dfi_p0_we_n, rval = 1'1).\nAdding SRST signal on $procdff$12185 ($dff) from module top (D = $not$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4916$1726_Y, Q = \\main_sdram_dfi_p0_ras_n, rval = 1'1).\nAdding SRST signal on $procdff$12183 ($dff) from module top (D = $not$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4915$1725_Y, Q = \\main_sdram_dfi_p0_cas_n, rval = 1'1).\nAdding SRST signal on $procdff$12182 ($dff) from module top (D = \\main_sdram_choose_req_cmd_payload_ba, Q = \\main_sdram_dfi_p0_bank, rval = 2'00).\nAdding SRST signal on $procdff$12181 ($dff) from module top (D = \\builder_sync_rhs_array_muxed1, Q = \\main_sdram_dfi_p0_address, rval = 13'0000000000000).\nAdding SRST signal on $procdff$12180 ($dff) from module top (D = $procmux$9813_Y, Q = \\main_sdram_rddata_status, rval = 16'0000000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13076 ($sdff) from module top (D = \\main_sdram_inti_p0_rddata, Q = \\main_sdram_rddata_status).\nAdding EN signal on $procdff$12178 ($dff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_sdram_wrdata_storage [15:8]).\nAdding EN signal on $procdff$12178 ($dff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_sdram_wrdata_storage [7:0]).\nAdding EN signal on $procdff$12176 ($dff) from module top (D = \\builder_soclinux_dat_w [1:0], Q = \\main_sdram_baddress_storage).\nAdding EN signal on $procdff$12174 ($dff) from module top (D = \\builder_soclinux_dat_w [4:0], Q = \\main_sdram_address_storage [12:8]).\nAdding EN signal on $procdff$12174 ($dff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_sdram_address_storage [7:0]).\nAdding SRST signal on $procdff$12172 ($dff) from module top (D = $procmux$9825_Y, Q = \\main_sdram_command_storage, rval = 6'000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13083 ($sdff) from module top (D = \\builder_soclinux_dat_w [5:0], Q = \\main_sdram_command_storage).\nAdding SRST signal on $procdff$12170 ($dff) from module top (D = $procmux$9829_Y, Q = \\main_sdram_storage, rval = 4'0001).\nAdding EN signal on $auto$opt_dff.cc:702:run$13085 ($sdff) from module top (D = \\builder_soclinux_dat_w [3:0], Q = \\main_sdram_storage).\nAdding SRST signal on $procdff$12169 ($dff) from module top (D = { \\main_rddata_en [1:0] \\main_dfi_p0_rddata_en }, Q = \\main_rddata_en, rval = 3'000).\nAdding SRST signal on $procdff$12168 ($dff) from module top (D = \\main_rddata_en [2], Q = \\main_dfi_p0_rddata_valid, rval = 1'0).\nAdding SRST signal on $procdff$12167 ($dff) from module top (D = $procmux$8796_Y, Q = \\main_soclinux_timer_value, rval = 0).\nAdding SRST signal on $procdff$12165 ($dff) from module top (D = $procmux$9833_Y, Q = \\main_soclinux_timer_eventmanager_storage, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13090 ($sdff) from module top (D = \\builder_soclinux_dat_w [0], Q = \\main_soclinux_timer_eventmanager_storage).\nAdding SRST signal on $procdff$12164 ($dff) from module top (D = \\main_soclinux_timer_eventmanager_status_w, Q = \\main_soclinux_timer_zero_old_trigger, rval = 1'0).\nAdding SRST signal on $procdff$12163 ($dff) from module top (D = $procmux$9839_Y, Q = \\main_soclinux_timer_zero_pending, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13093 ($sdff) from module top (D = $procmux$9839_Y, Q = \\main_soclinux_timer_zero_pending).\nAdding SRST signal on $procdff$12162 ($dff) from module top (D = $procmux$9843_Y, Q = \\main_soclinux_timer_value_status, rval = 0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13097 ($sdff) from module top (D = \\main_soclinux_timer_value, Q = \\main_soclinux_timer_value_status).\nAdding SRST signal on $procdff$12161 ($dff) from module top (D = \\builder_csr_bankarray_csrbank5_update_value0_re, Q = \\main_soclinux_timer_update_value_re, rval = 1'0).\nAdding SRST signal on $procdff$12160 ($dff) from module top (D = $procmux$9847_Y, Q = \\main_soclinux_timer_update_value_storage, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13100 ($sdff) from module top (D = \\builder_soclinux_dat_w [0], Q = \\main_soclinux_timer_update_value_storage).\nAdding SRST signal on $procdff$12158 ($dff) from module top (D = $procmux$9851_Y, Q = \\main_soclinux_timer_en_storage, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13102 ($sdff) from module top (D = \\builder_soclinux_dat_w [0], Q = \\main_soclinux_timer_en_storage).\nAdding SRST signal on $procdff$12156 ($dff) from module top (D = { $procmux$8788_Y $procmux$8654_Y $procmux$8650_Y $procmux$10026_Y }, Q = \\main_soclinux_timer_reload_storage, rval = 0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13104 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_timer_reload_storage [31:24]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13104 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_timer_reload_storage [23:16]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13104 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_timer_reload_storage [15:8]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13104 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_timer_reload_storage [7:0]).\nAdding SRST signal on $procdff$12154 ($dff) from module top (D = { $procmux$8646_Y $procmux$8667_Y $procmux$8663_Y $procmux$9855_Y }, Q = \\main_soclinux_timer_load_storage, rval = 0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13109 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_timer_load_storage [31:24]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13109 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_timer_load_storage [23:16]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13109 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_timer_load_storage [15:8]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13109 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_timer_load_storage [7:0]).\nAdding SRST signal on $procdff$12153 ($dff) from module top (D = $procmux$9863_Y, Q = \\main_soclinux_uart_rx_fifo_consume, rval = 4'0000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13114 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4371$1606_Y, Q = \\main_soclinux_uart_rx_fifo_consume).\nAdding SRST signal on $procdff$12152 ($dff) from module top (D = $procmux$9869_Y, Q = \\main_soclinux_uart_rx_fifo_produce, rval = 4'0000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13116 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4368$1605_Y, Q = \\main_soclinux_uart_rx_fifo_produce).\nAdding SRST signal on $procdff$12151 ($dff) from module top (D = $procmux$9880_Y, Q = \\main_soclinux_uart_rx_fifo_level0, rval = 5'00000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13118 ($sdff) from module top (D = $procmux$9880_Y, Q = \\main_soclinux_uart_rx_fifo_level0).\nAdding SRST signal on $procdff$12150 ($dff) from module top (D = $procmux$9889_Y, Q = \\main_soclinux_uart_rx_fifo_readable, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13126 ($sdff) from module top (D = $procmux$9889_Y, Q = \\main_soclinux_uart_rx_fifo_readable).\nAdding SRST signal on $procdff$12149 ($dff) from module top (D = $procmux$9895_Y, Q = \\main_soclinux_uart_tx_fifo_consume, rval = 4'0000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13130 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4349$1595_Y, Q = \\main_soclinux_uart_tx_fifo_consume).\nAdding SRST signal on $procdff$12148 ($dff) from module top (D = $procmux$9901_Y, Q = \\main_soclinux_uart_tx_fifo_produce, rval = 4'0000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13132 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4346$1594_Y, Q = \\main_soclinux_uart_tx_fifo_produce).\nAdding SRST signal on $procdff$12147 ($dff) from module top (D = $procmux$9912_Y, Q = \\main_soclinux_uart_tx_fifo_level0, rval = 5'00000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13134 ($sdff) from module top (D = $procmux$9912_Y, Q = \\main_soclinux_uart_tx_fifo_level0).\nAdding SRST signal on $procdff$12146 ($dff) from module top (D = $procmux$9921_Y, Q = \\main_soclinux_uart_tx_fifo_readable, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13142 ($sdff) from module top (D = $procmux$9921_Y, Q = \\main_soclinux_uart_tx_fifo_readable).\nAdding SRST signal on $procdff$12144 ($dff) from module top (D = $procmux$9927_Y, Q = \\main_soclinux_uart_eventmanager_storage, rval = 2'00).\nAdding EN signal on $auto$opt_dff.cc:702:run$13146 ($sdff) from module top (D = \\builder_soclinux_dat_w [1:0], Q = \\main_soclinux_uart_eventmanager_storage).\nAdding SRST signal on $procdff$12143 ($dff) from module top (D = \\builder_csr_bankarray_csrbank6_rxempty_w, Q = \\main_soclinux_uart_rx_old_trigger, rval = 1'0).\nAdding SRST signal on $procdff$12142 ($dff) from module top (D = $procmux$9933_Y, Q = \\main_soclinux_uart_rx_pending, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13149 ($sdff) from module top (D = $procmux$9933_Y, Q = \\main_soclinux_uart_rx_pending).\nAdding SRST signal on $procdff$12141 ($dff) from module top (D = \\builder_csr_bankarray_csrbank6_txfull_w, Q = \\main_soclinux_uart_tx_old_trigger, rval = 1'0).\nAdding SRST signal on $procdff$12140 ($dff) from module top (D = $procmux$9941_Y, Q = \\main_soclinux_uart_tx_pending, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13154 ($sdff) from module top (D = $procmux$9941_Y, Q = \\main_soclinux_uart_tx_pending).\nAdding SRST signal on $procdff$12139 ($dff) from module top (D = $procmux$9960_Y, Q = \\main_soclinux_rx_busy, rval = 1'0).\nAdding EN signal on $procdff$12138 ($dff) from module top (D = $0\\main_soclinux_rx_bitcount[3:0], Q = \\main_soclinux_rx_bitcount).\nAdding EN signal on $procdff$12137 ($dff) from module top (D = { \\builder_regs1 \\main_soclinux_rx_reg [7:1] }, Q = \\main_soclinux_rx_reg).\nAdding SRST signal on $procdff$12136 ($dff) from module top (D = \\builder_regs1, Q = \\main_soclinux_rx_r, rval = 1'0).\nAdding SRST signal on $procdff$12135 ($dff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4320$1586_Y [31:0], Q = \\main_soclinux_rx_clkphase, rval = 32'10000000000000000000000000000000).\nAdding SRST signal on $procdff$12134 ($dff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4320$1586_Y [32], Q = \\main_soclinux_rx_clken, rval = 1'0).\nAdding SRST signal on $procdff$12133 ($dff) from module top (D = $procmux$9993_Y, Q = \\main_soclinux_source_payload_data, rval = 8'00000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13180 ($sdff) from module top (D = \\main_soclinux_rx_reg, Q = \\main_soclinux_source_payload_data).\nAdding SRST signal on $procdff$12132 ($dff) from module top (D = $procmux$9071_Y, Q = \\main_soclinux_source_valid, rval = 1'0).\nAdding SRST signal on $procdff$12131 ($dff) from module top (D = $procmux$10006_Y, Q = \\main_soclinux_tx_busy, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13195 ($sdff) from module top (D = $procmux$10006_Y, Q = \\main_soclinux_tx_busy).\nAdding SRST signal on $procdff$12130 ($dff) from module top (D = $procmux$10010_Y, Q = \\main_soclinux_tx_bitcount, rval = 4'0000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13205 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4272$1576_Y, Q = \\main_soclinux_tx_bitcount).\nAdding EN signal on $procdff$12129 ($dff) from module top (D = $0\\main_soclinux_tx_reg[7:0], Q = \\main_soclinux_tx_reg).\nAdding SRST signal on $procdff$12127 ($dff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4288$1579_Y [32], Q = \\main_soclinux_tx_clken, rval = 1'0).\nAdding SRST signal on $procdff$12126 ($dff) from module top (D = $procmux$9086_Y, Q = \\main_soclinux_sink_ready, rval = 1'0).\nAdding SRST signal on $procdff$12124 ($dff) from module top (D = { $procmux$8805_Y $procmux$8642_Y $procmux$8638_Y $procmux$8685_Y }, Q = \\main_soclinux_storage, rval = 85899345).\nAdding EN signal on $auto$opt_dff.cc:702:run$13226 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_storage [31:24]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13226 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_storage [23:16]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13226 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_storage [15:8]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13226 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_storage [7:0]).\nAdding SRST signal on $procdff$12123 ($dff) from module top (D = $procmux$9098_Y, Q = \\main_soclinux_ram_bus_ram_bus_ack, rval = 1'0).\nAdding SRST signal on $procdff$12122 ($dff) from module top (D = $procmux$9102_Y, Q = \\main_soclinux_soclinux_ram_bus_ack, rval = 1'0).\nAdding SRST signal on $procdff$12121 ($dff) from module top (D = $procmux$10030_Y, Q = \\main_soclinux_cpu_time_cmp, rval = 64'1111111111111111111111111111111111111111111111111111111111111111).\nAdding EN signal on $auto$opt_dff.cc:702:run$13233 ($sdff) from module top (D = \\main_soclinux_cpu_time_cmp_storage, Q = \\main_soclinux_cpu_time_cmp).\nAdding SRST signal on $procdff$12120 ($dff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4249$1564_Y, Q = \\main_soclinux_cpu_time, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).\nAdding SRST signal on $procdff$12118 ($dff) from module top (D = { $procmux$8634_Y $procmux$8721_Y $procmux$8717_Y $procmux$8713_Y $procmux$8709_Y $procmux$8705_Y $procmux$8701_Y $procmux$10051_Y }, Q = \\main_soclinux_cpu_time_cmp_storage, rval = 64'1111111111111111111111111111111111111111111111111111111111111111).\nAdding EN signal on $auto$opt_dff.cc:702:run$13236 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_cpu_time_cmp_storage [63:56]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13236 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_cpu_time_cmp_storage [55:48]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13236 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_cpu_time_cmp_storage [47:40]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13236 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_cpu_time_cmp_storage [39:32]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13236 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_cpu_time_cmp_storage [31:24]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13236 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_cpu_time_cmp_storage [23:16]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13236 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_cpu_time_cmp_storage [15:8]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13236 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_cpu_time_cmp_storage [7:0]).\nAdding SRST signal on $procdff$12117 ($dff) from module top (D = $procmux$10041_Y, Q = \\main_soclinux_cpu_time_status, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13245 ($sdff) from module top (D = \\main_soclinux_cpu_time, Q = \\main_soclinux_cpu_time_status).\nAdding SRST signal on $procdff$12116 ($dff) from module top (D = $procmux$10047_Y, Q = \\main_soclinux_soccontroller_bus_errors, rval = 0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13247 ($sdff) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4246$1563_Y, Q = \\main_soclinux_soccontroller_bus_errors).\nAdding SRST signal on $procdff$12114 ($dff) from module top (D = { $procmux$8697_Y $procmux$8693_Y $procmux$8689_Y $procmux$9821_Y }, Q = \\main_soclinux_soccontroller_scratch_storage, rval = 305419896).\nAdding EN signal on $auto$opt_dff.cc:702:run$13251 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_soccontroller_scratch_storage [31:24]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13251 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_soccontroller_scratch_storage [23:16]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13251 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_soccontroller_scratch_storage [15:8]).\nAdding EN signal on $auto$opt_dff.cc:702:run$13251 ($sdff) from module top (D = \\builder_soclinux_dat_w, Q = \\main_soclinux_soccontroller_scratch_storage [7:0]).\nAdding SRST signal on $procdff$12113 ($dff) from module top (D = \\builder_csr_bankarray_csrbank1_reset0_re, Q = \\main_soclinux_soccontroller_reset_re, rval = 1'0).\nAdding SRST signal on $procdff$12112 ($dff) from module top (D = $procmux$10055_Y, Q = \\main_soclinux_soccontroller_reset_storage, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13257 ($sdff) from module top (D = \\builder_soclinux_dat_w [0], Q = \\main_soclinux_soccontroller_reset_storage).\nAdding SRST signal on $procdff$12111 ($dff) from module top (D = $or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5073$1780_Y, Q = \\spisdcard_cs_n, rval = 1'0).\nAdding SRST signal on $procdff$12110 ($dff) from module top (D = $procmux$10064_Y, Q = \\spisdcard_mosi, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13260 ($sdff) from module top (D = \\builder_sync_f_array_muxed, Q = \\spisdcard_mosi).\nAdding SRST signal on $procdff$12109 ($dff) from module top (D = $procmux$10071_Y, Q = \\spisdcard_clk, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13266 ($sdff) from module top (D = $procmux$10071_Y, Q = \\spisdcard_clk).\nAdding SRST signal on $procdff$12108 ($dff) from module top (D = $procmux$10084_Y, Q = \\serial_tx, rval = 1'1).\nAdding EN signal on $auto$opt_dff.cc:702:run$13270 ($sdff) from module top (D = $procmux$10084_Y, Q = \\serial_tx).\nAdding SRST signal on $procdff$12102 ($dff) from module top (D = 8'xxxxxxxx, Q = $memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_DATA [31:24], rval = 8'00000000).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$13274 ($sdff) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$13274 ($sdff) from module top.\nSetting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$13274 ($sdff) from module top.\nSetting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$13274 ($sdff) from module top.\nSetting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$13274 ($sdff) from module top.\nSetting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$13274 ($sdff) from module top.\nSetting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$13274 ($sdff) from module top.\nSetting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$13274 ($sdff) from module top.\nAdding SRST signal on $procdff$12099 ($dff) from module top (D = 16'xxxxxxxxxxxxxxxx, Q = $memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_DATA [31:16], rval = 16'0000000000000000).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nSetting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$13275 ($sdff) from module top.\nAdding SRST signal on $procdff$12096 ($dff) from module top (D = 24'xxxxxxxxxxxxxxxxxxxxxxxx, Q = $memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_DATA [31:8], rval = 24'000000000000000000000000).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nSetting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$13276 ($sdff) from module top.\nAdding SRST signal on $procdff$12091 ($dff) from module top (D = 2'xx, Q = $memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_DATA [9:8], rval = 2'00).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$13277 ($sdff) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$13277 ($sdff) from module top.\nAdding EN signal on $procdff$12088 ($dff) from module top (D = $memrd$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5811$1810_DATA, Q = \\memdat_2).\nAdding SRST signal on $procdff$12086 ($dff) from module top (D = 2'xx, Q = $memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_DATA [9:8], rval = 2'00).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$13279 ($sdff) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$13279 ($sdff) from module top.\nAdding EN signal on $procdff$12083 ($dff) from module top (D = $memrd$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5828$1817_DATA, Q = \\memdat_4).\nAdding SRST signal on $procdff$12081 ($dff) from module top (D = 2'xx, Q = $memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_DATA [24:23], rval = 2'00).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$13281 ($sdff) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$13281 ($sdff) from module top.\nAdding SRST signal on $procdff$12077 ($dff) from module top (D = 2'xx, Q = $memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_DATA [24:23], rval = 2'00).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$13282 ($sdff) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$13282 ($sdff) from module top.\nAdding SRST signal on $procdff$12073 ($dff) from module top (D = 2'xx, Q = $memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_DATA [24:23], rval = 2'00).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$13283 ($sdff) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$13283 ($sdff) from module top.\nAdding SRST signal on $procdff$12069 ($dff) from module top (D = 2'xx, Q = $memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_DATA [24:23], rval = 2'00).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$13284 ($sdff) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$13284 ($sdff) from module top.\nAdding SRST signal on $procdff$12065 ($dff) from module top (D = 4'xxxx, Q = $memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_DATA [22:19], rval = 4'0000).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$13285 ($sdff) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$13285 ($sdff) from module top.\nSetting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$13285 ($sdff) from module top.\nSetting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$13285 ($sdff) from module top.\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11696 ($dff) from module top (D = $flatten\\VexRiscv.\\dataCache_1_.$memrd$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:561$3663_DATA, Q = \\VexRiscv.dataCache_1_._zz_10_).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11683 ($dff) from module top (D = $flatten\\VexRiscv.\\dataCache_1_.$memrd$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:588$3686_DATA, Q = \\VexRiscv.dataCache_1_._zz_41_).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11682 ($dff) from module top (D = $flatten\\VexRiscv.\\dataCache_1_.$memrd$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:587$3685_DATA, Q = \\VexRiscv.dataCache_1_._zz_40_).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11681 ($dff) from module top (D = $flatten\\VexRiscv.\\dataCache_1_.$memrd$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:586$3684_DATA, Q = \\VexRiscv.dataCache_1_._zz_39_).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11680 ($dff) from module top (D = $flatten\\VexRiscv.\\dataCache_1_.$memrd$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:585$3683_DATA, Q = \\VexRiscv.dataCache_1_._zz_38_).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11677 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stageA_colisions, Q = \\VexRiscv.dataCache_1_.stageB_colisions).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11676 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stageA_mask, Q = \\VexRiscv.dataCache_1_.stageB_mask).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11675 ($dff) from module top (D = \\VexRiscv.dataCache_1_._zz_8_, Q = \\VexRiscv.dataCache_1_.stageB_waysHits).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11674 ($dff) from module top (D = { \\VexRiscv.dataCache_1_._zz_41_ \\VexRiscv.dataCache_1_._zz_40_ \\VexRiscv.dataCache_1_._zz_39_ \\VexRiscv.dataCache_1_._zz_38_ }, Q = \\VexRiscv.dataCache_1_.stageB_dataReadRsp_0).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11672 ($dff) from module top (D = \\VexRiscv.dataCache_1_._zz_10_ [1], Q = \\VexRiscv.dataCache_1_.stageB_tagsReadRsp_0_error).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11670 ($dff) from module top (D = \\VexRiscv.DBusCachedPlugin_mmuBus_rsp_refilling, Q = \\VexRiscv.dataCache_1_.stageB_mmuRsp_refilling).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11669 ($dff) from module top (D = \\VexRiscv.dataCache_1_.io_cpu_memory_mmuBus_rsp_exception, Q = \\VexRiscv.dataCache_1_.stageB_mmuRsp_exception).\nAdding SRST signal on $auto$opt_dff.cc:764:run$13297 ($dffe) from module top (D = $flatten\\VexRiscv.$logic_and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5329$3057_Y, Q = \\VexRiscv.dataCache_1_.stageB_mmuRsp_exception, rval = 1'0).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11667 ($dff) from module top (D = \\VexRiscv.dataCache_1_.io_cpu_memory_mmuBus_rsp_allowWrite, Q = \\VexRiscv.dataCache_1_.stageB_mmuRsp_allowWrite).\nAdding SRST signal on $auto$opt_dff.cc:764:run$13299 ($dffe) from module top (D = \\VexRiscv.MmuPlugin_ports_0_cacheLine_allowWrite, Q = \\VexRiscv.dataCache_1_.stageB_mmuRsp_allowWrite, rval = 1'1).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11666 ($dff) from module top (D = \\VexRiscv.dataCache_1_.io_cpu_memory_mmuBus_rsp_allowRead, Q = \\VexRiscv.dataCache_1_.stageB_mmuRsp_allowRead).\nAdding SRST signal on $auto$opt_dff.cc:764:run$13301 ($dffe) from module top (D = $flatten\\VexRiscv.$logic_or$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5305$3044_Y, Q = \\VexRiscv.dataCache_1_.stageB_mmuRsp_allowRead, rval = 1'1).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11665 ($dff) from module top (D = \\VexRiscv.dataCache_1_.io_cpu_memory_mmuBus_rsp_isIoAccess, Q = \\VexRiscv.dataCache_1_.stageB_mmuRsp_isIoAccess).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11664 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stageA_request_amoCtrl_alu, Q = \\VexRiscv.dataCache_1_.stageB_request_amoCtrl_alu).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11663 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stageA_request_amoCtrl_swap, Q = \\VexRiscv.dataCache_1_.stageB_request_amoCtrl_swap).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11662 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stageA_request_isAmo, Q = \\VexRiscv.dataCache_1_.stageB_isAmo).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11661 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stageA_request_isLrsc, Q = \\VexRiscv.dataCache_1_.stageB_request_isLrsc).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11660 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stageA_request_size, Q = \\VexRiscv.dataCache_1_.stageB_request_size).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11659 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stageA_request_data, Q = \\VexRiscv.dataCache_1_.stageB_request_data).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11658 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stageA_request_wr, Q = \\VexRiscv.dataCache_1_.stageB_request_wr).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11657 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stage0_colisions, Q = \\VexRiscv.dataCache_1_.stage0_colisions_regNextWhen).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11656 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stage0_mask, Q = \\VexRiscv.dataCache_1_.stageA_mask).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11655 ($dff) from module top (D = \\VexRiscv.decode_to_execute_INSTRUCTION [31:29], Q = \\VexRiscv.dataCache_1_.stageA_request_amoCtrl_alu).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11654 ($dff) from module top (D = \\VexRiscv.decode_to_execute_INSTRUCTION [27], Q = \\VexRiscv.dataCache_1_.stageA_request_amoCtrl_swap).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11653 ($dff) from module top (D = \\VexRiscv.dataCache_1_.io_cpu_execute_args_isAmo, Q = \\VexRiscv.dataCache_1_.stageA_request_isAmo).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11652 ($dff) from module top (D = \\VexRiscv.dataCache_1_.io_cpu_execute_args_isLrsc, Q = \\VexRiscv.dataCache_1_.stageA_request_isLrsc).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11651 ($dff) from module top (D = \\VexRiscv.dataCache_1_.io_cpu_execute_args_size, Q = \\VexRiscv.dataCache_1_.stageA_request_size).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11650 ($dff) from module top (D = \\VexRiscv.dataCache_1_.io_cpu_execute_args_data, Q = \\VexRiscv.dataCache_1_.stageA_request_data).\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11649 ($dff) from module top (D = \\VexRiscv.dataCache_1_.io_cpu_execute_args_wr, Q = \\VexRiscv.dataCache_1_.stageA_request_wr).\nAdding SRST signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11642 ($dff) from module top (D = $flatten\\VexRiscv.\\dataCache_1_.$procmux$4038_Y, Q = \\VexRiscv.dataCache_1_.loader_error, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13320 ($sdff) from module top (D = 1'0, Q = \\VexRiscv.dataCache_1_.loader_error).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$13321 ($sdffe) from module top.\nAdding EN signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11641 ($dff) from module top (D = 1'1, Q = \\VexRiscv.dataCache_1_.loader_waysAllocator).\nSetting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$13322 ($dffe) from module top.\nAdding SRST signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11640 ($dff) from module top (D = \\VexRiscv.dataCache_1_.loader_counter_valueNext, Q = \\VexRiscv.dataCache_1_.loader_counter_value, rval = 3'000).\nAdding SRST signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11639 ($dff) from module top (D = $flatten\\VexRiscv.\\dataCache_1_.$procmux$4048_Y, Q = \\VexRiscv.dataCache_1_.loader_valid, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13326 ($sdff) from module top (D = 1'1, Q = \\VexRiscv.dataCache_1_.loader_valid).\nAdding SRST signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11638 ($dff) from module top (D = $flatten\\VexRiscv.\\dataCache_1_.$procmux$4055_Y, Q = \\VexRiscv.dataCache_1_.stageB_memCmdSent, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13332 ($sdff) from module top (D = 1'1, Q = \\VexRiscv.dataCache_1_.stageB_memCmdSent).\nAdding SRST signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11637 ($dff) from module top (D = $flatten\\VexRiscv.\\dataCache_1_.$procmux$4062_Y, Q = \\VexRiscv.dataCache_1_.stageB_lrsc_reserved, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13336 ($sdff) from module top (D = 1'1, Q = \\VexRiscv.dataCache_1_.stageB_lrsc_reserved).\nAdding SRST signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11636 ($dff) from module top (D = $flatten\\VexRiscv.\\dataCache_1_.$procmux$4072_Y, Q = \\VexRiscv.dataCache_1_.stageB_flusher_valid, rval = 1'1).\nAdding SRST signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11635 ($dff) from module top (D = $flatten\\VexRiscv.\\dataCache_1_.$procmux$4024_Y, Q = \\VexRiscv.dataCache_1_.stageB_mmuRsp_physicalAddress [11:5], rval = 7'0000000).\nAdding SRST signal on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11635 ($dff) from module top (D = { $flatten\\VexRiscv.\\dataCache_1_.$procmux$4014_Y $flatten\\VexRiscv.\\dataCache_1_.$procmux$4031_Y }, Q = { \\VexRiscv.dataCache_1_.stageB_mmuRsp_physicalAddress [31:12] \\VexRiscv.dataCache_1_.stageB_mmuRsp_physicalAddress [4:0] }, rval = 25'0000000000000000000000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13344 ($sdff) from module top (D = { \\VexRiscv.DBusCachedPlugin_mmuBus_rsp_physicalAddress [31:28] \\VexRiscv.dataCache_1_.io_cpu_memory_mmuBus_rsp_physicalAddress [27:12] \\VexRiscv.dataCache_1_.io_cpu_memory_mmuBus_rsp_physicalAddress [4:0] }, Q = { \\VexRiscv.dataCache_1_.stageB_mmuRsp_physicalAddress [31:12] \\VexRiscv.dataCache_1_.stageB_mmuRsp_physicalAddress [4:0] }).\nAdding EN signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11631 ($dff) from module top (D = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$memrd$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:170$3844_DATA, Q = \\VexRiscv.IBusCachedPlugin_cache._zz_10_).\nAdding EN signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11627 ($dff) from module top (D = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$memrd$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:182$3850_DATA, Q = \\VexRiscv.IBusCachedPlugin_cache._zz_11_).\nAdding SRST signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11626 ($dff) from module top (D = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$3936_Y, Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_wordIndex, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13348 ($sdff) from module top (D = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:301$3884_Y, Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_wordIndex).\nAdding SRST signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11625 ($dff) from module top (D = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$3941_Y, Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_cmdSent, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13352 ($sdff) from module top (D = 1'1, Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_cmdSent).\nAdding SRST signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11624 ($dff) from module top (D = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$3950_Y, Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_flushPending, rval = 1'1).\nAdding EN signal on $auto$opt_dff.cc:702:run$13354 ($sdff) from module top (D = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$3950_Y, Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_flushPending).\nAdding SRST signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11623 ($dff) from module top (D = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$3955_Y, Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_hadError, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13358 ($sdff) from module top (D = 1'0, Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_hadError).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$13359 ($sdffe) from module top.\nAdding SRST signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11622 ($dff) from module top (D = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$3966_Y, Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_valid, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13360 ($sdff) from module top (D = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$3966_Y, Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_valid).\nAdding EN signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11621 ($dff) from module top (D = \\VexRiscv.IBusCachedPlugin_cache._zz_10_ [1], Q = \\VexRiscv.IBusCachedPlugin_cache.decodeStage_hit_error).\nAdding EN signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11620 ($dff) from module top (D = \\VexRiscv.IBusCachedPlugin_cache.fetchStage_hit_valid, Q = \\VexRiscv.IBusCachedPlugin_cache.decodeStage_hit_valid).\nAdding EN signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11619 ($dff) from module top (D = \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuBus_rsp_refilling, Q = \\VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_refilling).\nAdding EN signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11618 ($dff) from module top (D = \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuBus_rsp_exception, Q = \\VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_exception).\nAdding SRST signal on $auto$opt_dff.cc:764:run$13367 ($dffe) from module top (D = $flatten\\VexRiscv.$logic_and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5426$3118_Y, Q = \\VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_exception, rval = 1'0).\nAdding EN signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11617 ($dff) from module top (D = \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuBus_rsp_allowExecute, Q = \\VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_allowExecute).\nAdding SRST signal on $auto$opt_dff.cc:764:run$13369 ($dffe) from module top (D = \\VexRiscv.MmuPlugin_ports_1_cacheLine_allowExecute, Q = \\VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_allowExecute, rval = 1'1).\nAdding EN signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11613 ($dff) from module top (D = \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuBus_rsp_physicalAddress, Q = \\VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress).\nAdding EN signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11612 ($dff) from module top (D = \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data, Q = \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen).\nAdding SRST signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11611 ($dff) from module top (D = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$3930_Y, Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_flushCounter, rval = 8'00000000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13373 ($sdff) from module top (D = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:314$3886_Y [6:0], Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_flushCounter [6:0]).\nAdding EN signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11610 ($dff) from module top (D = \\VexRiscv.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress, Q = \\VexRiscv.IBusCachedPlugin_cache.lineLoader_address).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11993 ($dff) from module top (D = $flatten\\VexRiscv.$logic_and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7260$3477_Y, Q = \\VexRiscv._zz_238_, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11992 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5777_Y, Q = \\VexRiscv._zz_232_, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13377 ($sdff) from module top (D = $flatten\\VexRiscv.$procmux$5775_Y, Q = \\VexRiscv._zz_232_).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11991 ($dff) from module top (D = $flatten\\VexRiscv.$logic_and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7253$3472_Y, Q = \\VexRiscv._zz_231_, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11990 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5784_Y, Q = \\VexRiscv._zz_230_, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13380 ($sdff) from module top (D = $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7250$3471_Y, Q = \\VexRiscv._zz_230_).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11989 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5789_Y, Q = \\VexRiscv.memory_to_writeBack_IS_DBUS_SHARING, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13386 ($sdff) from module top (D = \\VexRiscv.execute_to_memory_IS_DBUS_SHARING, Q = \\VexRiscv.memory_to_writeBack_IS_DBUS_SHARING).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11988 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5796_Y, Q = \\VexRiscv.execute_to_memory_IS_DBUS_SHARING, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13388 ($sdff) from module top (D = \\VexRiscv.execute_IS_DBUS_SHARING, Q = \\VexRiscv.execute_to_memory_IS_DBUS_SHARING).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11987 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5801_Y, Q = \\VexRiscv.memory_to_writeBack_INSTRUCTION, rval = 0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13390 ($sdff) from module top (D = \\VexRiscv.execute_to_memory_INSTRUCTION, Q = \\VexRiscv.memory_to_writeBack_INSTRUCTION).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11986 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5806_Y, Q = \\VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA, rval = 0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13392 ($sdff) from module top (D = \\VexRiscv._zz_43_, Q = \\VexRiscv.memory_to_writeBack_REGFILE_WRITE_DATA).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11985 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5820_Y, Q = \\VexRiscv._zz_228_, rval = 0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13394 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData, Q = \\VexRiscv._zz_228_).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11984 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5837_Y, Q = \\VexRiscv._zz_226_, rval = 0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13398 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData, Q = \\VexRiscv._zz_226_).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11983 ($dff) from module top (D = $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6595$3339_Y, Q = \\VexRiscv.memory_DivPlugin_div_counter_value, rval = 6'000000).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11982 ($dff) from module top (D = $flatten\\VexRiscv.$ne$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7083$3451_Y, Q = \\VexRiscv.execute_CsrPlugin_wfiWake, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11981 ($dff) from module top (D = \\VexRiscv.CsrPlugin_exception, Q = \\VexRiscv.CsrPlugin_hadException, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11979 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5731_Y, Q = \\VexRiscv.CsrPlugin_interrupt_valid, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11978 ($dff) from module top (D = $flatten\\VexRiscv.$logic_and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7010$3448_Y, Q = \\VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11977 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5743_Y, Q = \\VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11976 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5749_Y, Q = \\VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11975 ($dff) from module top (D = \\VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionValids_decode, Q = \\VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11974 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5844_Y, Q = \\VexRiscv.CsrPlugin_sie_SSIE, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13420 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [1], Q = \\VexRiscv.CsrPlugin_sie_SSIE).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11973 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5854_Y, Q = \\VexRiscv.CsrPlugin_sie_STIE, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13424 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [5], Q = \\VexRiscv.CsrPlugin_sie_STIE).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11972 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5864_Y, Q = \\VexRiscv.CsrPlugin_sie_SEIE, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13428 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [9], Q = \\VexRiscv.CsrPlugin_sie_SEIE).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11971 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5876_Y, Q = \\VexRiscv.CsrPlugin_sip_SSIP, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13432 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [1], Q = \\VexRiscv.CsrPlugin_sip_SSIP).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11970 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5888_Y, Q = \\VexRiscv.CsrPlugin_sip_STIP, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13436 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [5], Q = \\VexRiscv.CsrPlugin_sip_STIP).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11969 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5900_Y, Q = \\VexRiscv.CsrPlugin_sip_SEIP_SOFT, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13440 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [9], Q = \\VexRiscv.CsrPlugin_sip_SEIP_SOFT).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11968 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5925_Y, Q = \\VexRiscv.CsrPlugin_sstatus_SPP, rval = 1'1).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11967 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5950_Y, Q = \\VexRiscv.CsrPlugin_sstatus_SPIE, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11966 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5975_Y, Q = \\VexRiscv.CsrPlugin_sstatus_SIE, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11965 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5993_Y, Q = \\VexRiscv.CsrPlugin_mideleg_SS, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13447 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [1], Q = \\VexRiscv.CsrPlugin_mideleg_SS).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11964 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6008_Y, Q = \\VexRiscv.CsrPlugin_mideleg_SE, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13451 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [9], Q = \\VexRiscv.CsrPlugin_mideleg_SE).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11963 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6023_Y, Q = \\VexRiscv.CsrPlugin_mideleg_ST, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13455 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [5], Q = \\VexRiscv.CsrPlugin_mideleg_ST).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11962 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6035_Y, Q = \\VexRiscv.CsrPlugin_medeleg_SPF, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13459 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [15], Q = \\VexRiscv.CsrPlugin_medeleg_SPF).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11961 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6047_Y, Q = \\VexRiscv.CsrPlugin_medeleg_LPF, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13463 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [13], Q = \\VexRiscv.CsrPlugin_medeleg_LPF).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11960 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6059_Y, Q = \\VexRiscv.CsrPlugin_medeleg_IPF, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13467 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [12], Q = \\VexRiscv.CsrPlugin_medeleg_IPF).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11959 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6071_Y, Q = \\VexRiscv.CsrPlugin_medeleg_ES, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13471 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [9], Q = \\VexRiscv.CsrPlugin_medeleg_ES).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11958 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6083_Y, Q = \\VexRiscv.CsrPlugin_medeleg_EU, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13475 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [8], Q = \\VexRiscv.CsrPlugin_medeleg_EU).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11957 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6095_Y, Q = \\VexRiscv.CsrPlugin_medeleg_SAF, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13479 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [7], Q = \\VexRiscv.CsrPlugin_medeleg_SAF).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11956 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6107_Y, Q = \\VexRiscv.CsrPlugin_medeleg_SAM, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13483 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [6], Q = \\VexRiscv.CsrPlugin_medeleg_SAM).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11955 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6119_Y, Q = \\VexRiscv.CsrPlugin_medeleg_LAF, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13487 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [5], Q = \\VexRiscv.CsrPlugin_medeleg_LAF).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11954 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6131_Y, Q = \\VexRiscv.CsrPlugin_medeleg_LAM, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13491 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [4], Q = \\VexRiscv.CsrPlugin_medeleg_LAM).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11953 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6143_Y, Q = \\VexRiscv.CsrPlugin_medeleg_II, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13495 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [2], Q = \\VexRiscv.CsrPlugin_medeleg_II).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11952 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6155_Y, Q = \\VexRiscv.CsrPlugin_medeleg_IAF, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13499 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [1], Q = \\VexRiscv.CsrPlugin_medeleg_IAF).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11951 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6167_Y, Q = \\VexRiscv.CsrPlugin_medeleg_IAM, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13503 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [0], Q = \\VexRiscv.CsrPlugin_medeleg_IAM).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11950 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6175_Y, Q = \\VexRiscv.CsrPlugin_mie_MSIE, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13507 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [3], Q = \\VexRiscv.CsrPlugin_mie_MSIE).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11949 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6183_Y, Q = \\VexRiscv.CsrPlugin_mie_MTIE, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13511 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [7], Q = \\VexRiscv.CsrPlugin_mie_MTIE).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11948 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6191_Y, Q = \\VexRiscv.CsrPlugin_mie_MEIE, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13515 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [11], Q = \\VexRiscv.CsrPlugin_mie_MEIE).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11947 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6216_Y, Q = \\VexRiscv.CsrPlugin_mstatus_MPP, rval = 2'11).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11946 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6241_Y, Q = \\VexRiscv.CsrPlugin_mstatus_MPIE, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11945 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6266_Y, Q = \\VexRiscv.CsrPlugin_mstatus_MIE, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11944 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6276_Y, Q = \\VexRiscv._zz_210_, rval = 2'11).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11943 ($dff) from module top (D = \\VexRiscv._zz_184_, Q = \\VexRiscv._zz_185_, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11941 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6288_Y, Q = \\VexRiscv.MmuPlugin_shared_state_1_, rval = 3'000).\nAdding EN signal on $auto$opt_dff.cc:702:run$13524 ($sdff) from module top (D = $flatten\\VexRiscv.$procmux$6288_Y, Q = \\VexRiscv.MmuPlugin_shared_state_1_).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11940 ($dff) from module top (D = \\VexRiscv.MmuPlugin_ports_1_entryToReplace_valueNext, Q = \\VexRiscv.MmuPlugin_ports_1_entryToReplace_value, rval = 2'00).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11939 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6316_Y, Q = \\VexRiscv.MmuPlugin_ports_1_cache_3_valid, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11938 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6331_Y, Q = \\VexRiscv.MmuPlugin_ports_1_cache_2_valid, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11937 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6346_Y, Q = \\VexRiscv.MmuPlugin_ports_1_cache_1_valid, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11936 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6361_Y, Q = \\VexRiscv.MmuPlugin_ports_1_cache_0_valid, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11935 ($dff) from module top (D = \\VexRiscv.MmuPlugin_ports_0_entryToReplace_valueNext, Q = \\VexRiscv.MmuPlugin_ports_0_entryToReplace_value, rval = 2'00).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11934 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6376_Y, Q = \\VexRiscv.MmuPlugin_ports_0_cache_3_valid, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11933 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6391_Y, Q = \\VexRiscv.MmuPlugin_ports_0_cache_2_valid, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11932 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6406_Y, Q = \\VexRiscv.MmuPlugin_ports_0_cache_1_valid, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11931 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6421_Y, Q = \\VexRiscv.MmuPlugin_ports_0_cache_0_valid, rval = 1'0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11930 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6433_Y, Q = \\VexRiscv.MmuPlugin_satp_mode, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13564 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [31], Q = \\VexRiscv.MmuPlugin_satp_mode).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11929 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6446_Y, Q = \\VexRiscv.MmuPlugin_status_mprv, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13568 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [17], Q = \\VexRiscv.MmuPlugin_status_mprv).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11928 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6462_Y, Q = \\VexRiscv.MmuPlugin_status_mxr, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13572 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [19], Q = \\VexRiscv.MmuPlugin_status_mxr).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11927 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6478_Y, Q = \\VexRiscv.MmuPlugin_status_sum, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13576 ($sdff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [18], Q = \\VexRiscv.MmuPlugin_status_sum).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11925 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6491_Y, Q = \\VexRiscv._zz_139_, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13580 ($sdff) from module top (D = \\VexRiscv.dataCache_1__io_mem_cmd_s2mPipe_valid, Q = \\VexRiscv._zz_139_).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11924 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6498_Y, Q = \\VexRiscv._zz_132_, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13582 ($sdff) from module top (D = $flatten\\VexRiscv.$procmux$6498_Y, Q = \\VexRiscv._zz_132_).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11922 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6508_Y, Q = \\VexRiscv.IBusCachedPlugin_injector_decodeRemoved, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13588 ($sdff) from module top (D = 1'1, Q = \\VexRiscv.IBusCachedPlugin_injector_decodeRemoved).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11921 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6517_Y, Q = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_4, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13592 ($sdff) from module top (D = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_3, Q = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_4).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11920 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6526_Y, Q = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_3, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13596 ($sdff) from module top (D = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_2, Q = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_3).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11919 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6535_Y, Q = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_2, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13600 ($sdff) from module top (D = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_1, Q = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_2).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11918 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6544_Y, Q = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_1, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13604 ($sdff) from module top (D = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_0, Q = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_1).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11917 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6553_Y, Q = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_0, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13606 ($sdff) from module top (D = $flatten\\VexRiscv.$procmux$6553_Y, Q = \\VexRiscv.IBusCachedPlugin_injector_nextPcCalc_valids_0).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11916 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6558_Y, Q = \\VexRiscv._zz_118_, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13612 ($sdff) from module top (D = \\VexRiscv.IBusCachedPlugin_iBusRsp_stages_1_output_valid, Q = \\VexRiscv._zz_118_).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11915 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6567_Y, Q = \\VexRiscv._zz_116_, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13614 ($sdff) from module top (D = $flatten\\VexRiscv.$procmux$6567_Y, Q = \\VexRiscv._zz_116_).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11914 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6574_Y, Q = \\VexRiscv.IBusCachedPlugin_fetchPc_inc, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13620 ($sdff) from module top (D = $flatten\\VexRiscv.$procmux$6574_Y, Q = \\VexRiscv.IBusCachedPlugin_fetchPc_inc).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11912 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6581_Y, Q = \\VexRiscv.IBusCachedPlugin_fetchPc_pcReg, rval = 0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13624 ($sdff) from module top (D = { \\VexRiscv.IBusCachedPlugin_fetchPc_pc [31:12] \\VexRiscv.IBusCachedPlugin_cache._zz_5_ \\VexRiscv.IBusCachedPlugin_cache._zz_8_ [2:0] 2'00 }, Q = \\VexRiscv.IBusCachedPlugin_fetchPc_pcReg).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$13625 ($sdffe) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$13625 ($sdffe) from module top.\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11911 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6588_Y, Q = \\VexRiscv.writeBack_arbitration_isValid, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13626 ($sdff) from module top (D = $flatten\\VexRiscv.$procmux$6588_Y, Q = \\VexRiscv.writeBack_arbitration_isValid).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11910 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6595_Y, Q = \\VexRiscv.memory_arbitration_isValid, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13630 ($sdff) from module top (D = $flatten\\VexRiscv.$procmux$6595_Y, Q = \\VexRiscv.memory_arbitration_isValid).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11909 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$6602_Y, Q = \\VexRiscv.execute_arbitration_isValid, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13634 ($sdff) from module top (D = $flatten\\VexRiscv.$procmux$6602_Y, Q = \\VexRiscv.execute_arbitration_isValid).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11907 ($dff) from module top (D = $or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3186$886_Y, Q = \\VexRiscv.iBusWishbone_DAT_MISO_regNext, rval = 32'11111111111111111111111111111111).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11906 ($dff) from module top (D = \\VexRiscv.decode_IS_RS1_SIGNED, Q = \\VexRiscv.decode_to_execute_IS_RS1_SIGNED).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11905 ($dff) from module top (D = \\VexRiscv.decode_RS1, Q = \\VexRiscv.decode_to_execute_RS1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11904 ($dff) from module top (D = \\VexRiscv.decode_BYPASSABLE_EXECUTE_STAGE, Q = \\VexRiscv.decode_to_execute_BYPASSABLE_EXECUTE_STAGE).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11903 ($dff) from module top (D = \\VexRiscv.execute_to_memory_IS_MUL, Q = \\VexRiscv.memory_to_writeBack_IS_MUL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11902 ($dff) from module top (D = \\VexRiscv.decode_to_execute_IS_MUL, Q = \\VexRiscv.execute_to_memory_IS_MUL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11901 ($dff) from module top (D = \\VexRiscv.decode_IS_MUL, Q = \\VexRiscv.decode_to_execute_IS_MUL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11900 ($dff) from module top (D = \\VexRiscv.decode_to_execute_IS_DIV, Q = \\VexRiscv.execute_to_memory_IS_DIV).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11899 ($dff) from module top (D = \\VexRiscv.decode_IS_DIV, Q = \\VexRiscv.decode_to_execute_IS_DIV).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11895 ($dff) from module top (D = { \\VexRiscv._zz_522_ \\VexRiscv._zz_523_ }, Q = \\VexRiscv.decode_to_execute_BRANCH_CTRL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11894 ($dff) from module top (D = \\VexRiscv.decode_CSR_WRITE_OPCODE, Q = \\VexRiscv.decode_to_execute_CSR_WRITE_OPCODE).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11893 ($dff) from module top (D = \\VexRiscv.execute_to_memory_MEMORY_ENABLE, Q = \\VexRiscv.memory_to_writeBack_MEMORY_ENABLE).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11892 ($dff) from module top (D = \\VexRiscv.decode_to_execute_MEMORY_ENABLE, Q = \\VexRiscv.execute_to_memory_MEMORY_ENABLE).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11891 ($dff) from module top (D = \\VexRiscv.decode_MEMORY_ENABLE, Q = \\VexRiscv.decode_to_execute_MEMORY_ENABLE).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11890 ($dff) from module top (D = \\VexRiscv.decode_MEMORY_LRSC, Q = \\VexRiscv.decode_to_execute_MEMORY_LRSC).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11889 ($dff) from module top (D = \\VexRiscv.execute_MUL_LH, Q = \\VexRiscv.execute_to_memory_MUL_LH).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11888 ($dff) from module top (D = \\VexRiscv.execute_to_memory_MEMORY_WR, Q = \\VexRiscv.memory_to_writeBack_MEMORY_WR).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11887 ($dff) from module top (D = \\VexRiscv.decode_to_execute_MEMORY_WR, Q = \\VexRiscv.execute_to_memory_MEMORY_WR).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11886 ($dff) from module top (D = \\VexRiscv.decode_MEMORY_WR, Q = \\VexRiscv.decode_to_execute_MEMORY_WR).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11885 ($dff) from module top (D = \\VexRiscv.execute_to_memory_PC, Q = \\VexRiscv.memory_to_writeBack_PC).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11884 ($dff) from module top (D = \\VexRiscv.decode_to_execute_PC, Q = \\VexRiscv.execute_to_memory_PC).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11883 ($dff) from module top (D = \\VexRiscv._zz_119_, Q = \\VexRiscv.decode_to_execute_PC).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11882 ($dff) from module top (D = \\VexRiscv.decode_to_execute_SHIFT_CTRL, Q = \\VexRiscv.execute_to_memory_SHIFT_CTRL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11881 ($dff) from module top (D = { \\VexRiscv._zz_547_ \\VexRiscv._zz_6_ [0] }, Q = \\VexRiscv.decode_to_execute_SHIFT_CTRL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11880 ($dff) from module top (D = { \\VexRiscv._zz_627_ \\VexRiscv._zz_628_ }, Q = \\VexRiscv.decode_to_execute_ALU_CTRL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11879 ($dff) from module top (D = \\VexRiscv.decode_CSR_READ_OPCODE, Q = \\VexRiscv.decode_to_execute_CSR_READ_OPCODE).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11878 ($dff) from module top (D = \\VexRiscv.execute_BRANCH_DO, Q = \\VexRiscv.execute_to_memory_BRANCH_DO).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11877 ($dff) from module top (D = \\VexRiscv.IBusCachedPlugin_decodePrediction_cmd_hadBranch, Q = \\VexRiscv.decode_to_execute_PREDICTION_HAD_BRANCHED2).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11876 ($dff) from module top (D = \\VexRiscv.execute_to_memory_IS_SFENCE_VMA, Q = \\VexRiscv.memory_to_writeBack_IS_SFENCE_VMA).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11875 ($dff) from module top (D = \\VexRiscv.decode_to_execute_IS_SFENCE_VMA, Q = \\VexRiscv.execute_to_memory_IS_SFENCE_VMA).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11874 ($dff) from module top (D = \\VexRiscv.decode_IS_SFENCE_VMA, Q = \\VexRiscv.decode_to_execute_IS_SFENCE_VMA).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11873 ($dff) from module top (D = \\VexRiscv.execute_to_memory_MUL_HH, Q = \\VexRiscv.memory_to_writeBack_MUL_HH).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11872 ($dff) from module top (D = \\VexRiscv.execute_MUL_HH, Q = \\VexRiscv.execute_to_memory_MUL_HH).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11871 ($dff) from module top (D = \\VexRiscv.decode_to_execute_BYPASSABLE_MEMORY_STAGE, Q = \\VexRiscv.execute_to_memory_BYPASSABLE_MEMORY_STAGE).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11870 ($dff) from module top (D = \\VexRiscv.decode_BYPASSABLE_MEMORY_STAGE, Q = \\VexRiscv.decode_to_execute_BYPASSABLE_MEMORY_STAGE).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11869 ($dff) from module top (D = { \\VexRiscv._zz_609_ \\VexRiscv._zz_12_ [0] }, Q = \\VexRiscv.decode_to_execute_SRC1_CTRL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11868 ($dff) from module top (D = \\VexRiscv.decode_SRC_USE_SUB_LESS, Q = \\VexRiscv.decode_to_execute_SRC_USE_SUB_LESS).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11867 ($dff) from module top (D = \\VexRiscv.execute_MUL_HL, Q = \\VexRiscv.execute_to_memory_MUL_HL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11866 ($dff) from module top (D = \\VexRiscv.decode_MEMORY_AMO, Q = \\VexRiscv.decode_to_execute_MEMORY_AMO).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11865 ($dff) from module top (D = \\VexRiscv.decode_SRC_LESS_UNSIGNED, Q = \\VexRiscv.decode_to_execute_SRC_LESS_UNSIGNED).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11864 ($dff) from module top (D = \\VexRiscv.decode_SRC2_FORCE_ZERO, Q = \\VexRiscv.decode_to_execute_SRC2_FORCE_ZERO).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11863 ($dff) from module top (D = \\VexRiscv.decode_RS2, Q = \\VexRiscv.decode_to_execute_RS2).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11862 ($dff) from module top (D = \\VexRiscv.execute_MUL_LL, Q = \\VexRiscv.execute_to_memory_MUL_LL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11861 ($dff) from module top (D = { \\VexRiscv._zz_509_ \\VexRiscv._zz_511_ }, Q = \\VexRiscv.decode_to_execute_ALU_BITWISE_CTRL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11860 ($dff) from module top (D = { \\VexRiscv._zz_565_ \\VexRiscv._zz_566_ }, Q = \\VexRiscv.decode_to_execute_SRC2_CTRL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11859 ($dff) from module top (D = \\VexRiscv._zz_406_ [31:0], Q = \\VexRiscv.execute_to_memory_SHIFT_RIGHT).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11858 ($dff) from module top (D = { \\VexRiscv.execute_BranchPlugin_branchAdder [31:1] 1'0 }, Q = \\VexRiscv.execute_to_memory_BRANCH_CALC).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$13684 ($dffe) from module top.\nAdding EN signal on $flatten\\VexRiscv.$procdff$11857 ($dff) from module top (D = \\VexRiscv.execute_to_memory_MEMORY_ADDRESS_LOW, Q = \\VexRiscv.memory_to_writeBack_MEMORY_ADDRESS_LOW).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11856 ($dff) from module top (D = \\VexRiscv.dataCache_1_.io_cpu_execute_address [1:0], Q = \\VexRiscv.execute_to_memory_MEMORY_ADDRESS_LOW).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11855 ($dff) from module top (D = \\VexRiscv.decode_to_execute_INSTRUCTION, Q = \\VexRiscv.execute_to_memory_INSTRUCTION).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11854 ($dff) from module top (D = \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen, Q = \\VexRiscv.decode_to_execute_INSTRUCTION).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11853 ($dff) from module top (D = \\VexRiscv.decode_IS_RS1_SIGNED, Q = \\VexRiscv.decode_to_execute_IS_RS2_SIGNED).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11852 ($dff) from module top (D = \\VexRiscv.execute_to_memory_REGFILE_WRITE_VALID, Q = \\VexRiscv.memory_to_writeBack_REGFILE_WRITE_VALID).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11851 ($dff) from module top (D = \\VexRiscv.decode_to_execute_REGFILE_WRITE_VALID, Q = \\VexRiscv.execute_to_memory_REGFILE_WRITE_VALID).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11850 ($dff) from module top (D = \\VexRiscv.decode_REGFILE_WRITE_VALID, Q = \\VexRiscv.decode_to_execute_REGFILE_WRITE_VALID).\nAdding SRST signal on $auto$opt_dff.cc:764:run$13692 ($dffe) from module top (D = \\VexRiscv._zz_74_, Q = \\VexRiscv.decode_to_execute_REGFILE_WRITE_VALID, rval = 1'0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11849 ($dff) from module top (D = \\VexRiscv.decode_MEMORY_MANAGMENT, Q = \\VexRiscv.decode_to_execute_MEMORY_MANAGMENT).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11848 ($dff) from module top (D = \\VexRiscv.execute_to_memory_ENV_CTRL, Q = \\VexRiscv.memory_to_writeBack_ENV_CTRL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11847 ($dff) from module top (D = \\VexRiscv.decode_to_execute_ENV_CTRL, Q = \\VexRiscv.execute_to_memory_ENV_CTRL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11846 ($dff) from module top (D = { \\VexRiscv._zz_536_ \\VexRiscv._zz_537_ }, Q = \\VexRiscv.decode_to_execute_ENV_CTRL).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11845 ($dff) from module top (D = \\VexRiscv._zz_42_, Q = \\VexRiscv.execute_to_memory_REGFILE_WRITE_DATA).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11844 ($dff) from module top (D = \\VexRiscv.decode_IS_CSR, Q = \\VexRiscv.decode_to_execute_IS_CSR).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11843 ($dff) from module top (D = \\VexRiscv.memory_MUL_LOW, Q = \\VexRiscv.memory_to_writeBack_MUL_LOW).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11841 ($dff) from module top (D = \\VexRiscv._zz_440_ [31:0], Q = \\VexRiscv.memory_DivPlugin_div_result).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11840 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$4908_Y, Q = \\VexRiscv.memory_DivPlugin_div_done, rval = 1'0).\nAdding EN signal on $auto$opt_dff.cc:702:run$13706 ($sdff) from module top (D = 1'1, Q = \\VexRiscv.memory_DivPlugin_div_done).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11839 ($dff) from module top (D = $flatten\\VexRiscv.$logic_and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7536$3546_Y, Q = \\VexRiscv.memory_DivPlugin_div_needRevert).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11838 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$4768_Y, Q = \\VexRiscv.memory_DivPlugin_accumulator [31:0], rval = 0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11838 ($dff) from module top (D = 33'000000000000000000000000000000000, Q = \\VexRiscv.memory_DivPlugin_accumulator [64:32]).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 2 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 4 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 5 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 6 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 7 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 8 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 9 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 10 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 11 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 12 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 13 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 14 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 15 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 16 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 17 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 18 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 19 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 20 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 21 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 22 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 23 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 24 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 25 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 26 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 27 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 28 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 29 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 30 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 31 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nSetting constant 0-bit at position 32 on $auto$opt_dff.cc:764:run$13710 ($dffe) from module top.\nAdding EN signal on $auto$opt_dff.cc:702:run$13709 ($sdff) from module top (D = $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7526$3530_Y, Q = \\VexRiscv.memory_DivPlugin_accumulator [31:0]).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11837 ($dff) from module top (D = $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7535$3537_Y, Q = \\VexRiscv.memory_DivPlugin_rs2).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11836 ($dff) from module top (D = $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3534_Y [32], Q = \\VexRiscv.memory_DivPlugin_rs1 [32]).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11836 ($dff) from module top (D = $flatten\\VexRiscv.$0\\memory_DivPlugin_rs1[32:0] [31:0], Q = \\VexRiscv.memory_DivPlugin_rs1 [31:0]).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11833 ($dff) from module top (D = $flatten\\VexRiscv.$0\\CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[31:0], Q = \\VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11832 ($dff) from module top (D = $flatten\\VexRiscv.$0\\CsrPlugin_exceptionPortCtrl_exceptionContext_code[3:0], Q = \\VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_code).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11827 ($dff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData, Q = \\VexRiscv.CsrPlugin_sscratch).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11826 ($dff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [31:2], Q = \\VexRiscv.CsrPlugin_stvec_base).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11825 ($dff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [1:0], Q = \\VexRiscv.CsrPlugin_stvec_mode).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11821 ($dff) from module top (D = \\VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr, Q = \\VexRiscv.CsrPlugin_mtval).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11820 ($dff) from module top (D = \\VexRiscv.CsrPlugin_trapCause, Q = \\VexRiscv.CsrPlugin_mcause_exceptionCode).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11819 ($dff) from module top (D = $flatten\\VexRiscv.$logic_not$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7498$3525_Y, Q = \\VexRiscv.CsrPlugin_mcause_interrupt).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11818 ($dff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData, Q = \\VexRiscv.CsrPlugin_mscratch).\nAdding SRST signal on $flatten\\VexRiscv.$procdff$11817 ($dff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [3], Q = \\VexRiscv.CsrPlugin_mip_MSIP, rval = 1'0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11813 ($dff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [31:2], Q = \\VexRiscv.CsrPlugin_mtvec_base).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11811 ($dff) from module top (D = \\VexRiscv._zz_93_, Q = \\VexRiscv._zz_187_).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11810 ($dff) from module top (D = \\VexRiscv.memory_to_writeBack_INSTRUCTION [11:7], Q = \\VexRiscv._zz_186_).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11809 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [31:20], Q = \\VexRiscv.MmuPlugin_shared_pteBuffer_PPN1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11808 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [19:10], Q = \\VexRiscv.MmuPlugin_shared_pteBuffer_PPN0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11798 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5158_Y, Q = \\VexRiscv.MmuPlugin_shared_portId).\nAdding SRST signal on $auto$opt_dff.cc:764:run$13766 ($dffe) from module top (D = $flatten\\VexRiscv.$procmux$5156_Y, Q = \\VexRiscv.MmuPlugin_shared_portId, rval = 1'1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11797 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5164_Y, Q = \\VexRiscv.MmuPlugin_shared_vpn_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11796 ($dff) from module top (D = $flatten\\VexRiscv.$procmux$5170_Y, Q = \\VexRiscv.MmuPlugin_shared_vpn_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11795 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [4], Q = \\VexRiscv.MmuPlugin_ports_1_cache_3_allowUser).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11794 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [3], Q = \\VexRiscv.MmuPlugin_ports_1_cache_3_allowExecute).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11791 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [29:20], Q = \\VexRiscv.MmuPlugin_ports_1_cache_3_physicalAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11790 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [19:10], Q = \\VexRiscv.MmuPlugin_ports_1_cache_3_physicalAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11789 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_1, Q = \\VexRiscv.MmuPlugin_ports_1_cache_3_virtualAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11788 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_0, Q = \\VexRiscv.MmuPlugin_ports_1_cache_3_virtualAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11787 ($dff) from module top (D = $flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3481_Y, Q = \\VexRiscv.MmuPlugin_ports_1_cache_3_superPage).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11786 ($dff) from module top (D = $flatten\\VexRiscv.$logic_or$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3484_Y, Q = \\VexRiscv.MmuPlugin_ports_1_cache_3_exception).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11785 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [4], Q = \\VexRiscv.MmuPlugin_ports_1_cache_2_allowUser).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11784 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [3], Q = \\VexRiscv.MmuPlugin_ports_1_cache_2_allowExecute).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11781 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [29:20], Q = \\VexRiscv.MmuPlugin_ports_1_cache_2_physicalAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11780 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [19:10], Q = \\VexRiscv.MmuPlugin_ports_1_cache_2_physicalAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11779 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_1, Q = \\VexRiscv.MmuPlugin_ports_1_cache_2_virtualAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11778 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_0, Q = \\VexRiscv.MmuPlugin_ports_1_cache_2_virtualAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11777 ($dff) from module top (D = $flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3481_Y, Q = \\VexRiscv.MmuPlugin_ports_1_cache_2_superPage).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11776 ($dff) from module top (D = $flatten\\VexRiscv.$logic_or$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3484_Y, Q = \\VexRiscv.MmuPlugin_ports_1_cache_2_exception).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11775 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [4], Q = \\VexRiscv.MmuPlugin_ports_1_cache_1_allowUser).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11774 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [3], Q = \\VexRiscv.MmuPlugin_ports_1_cache_1_allowExecute).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11771 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [29:20], Q = \\VexRiscv.MmuPlugin_ports_1_cache_1_physicalAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11770 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [19:10], Q = \\VexRiscv.MmuPlugin_ports_1_cache_1_physicalAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11769 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_1, Q = \\VexRiscv.MmuPlugin_ports_1_cache_1_virtualAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11768 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_0, Q = \\VexRiscv.MmuPlugin_ports_1_cache_1_virtualAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11767 ($dff) from module top (D = $flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3481_Y, Q = \\VexRiscv.MmuPlugin_ports_1_cache_1_superPage).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11766 ($dff) from module top (D = $flatten\\VexRiscv.$logic_or$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3484_Y, Q = \\VexRiscv.MmuPlugin_ports_1_cache_1_exception).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11765 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [4], Q = \\VexRiscv.MmuPlugin_ports_1_cache_0_allowUser).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11764 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [3], Q = \\VexRiscv.MmuPlugin_ports_1_cache_0_allowExecute).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11761 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [29:20], Q = \\VexRiscv.MmuPlugin_ports_1_cache_0_physicalAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11760 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [19:10], Q = \\VexRiscv.MmuPlugin_ports_1_cache_0_physicalAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11759 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_1, Q = \\VexRiscv.MmuPlugin_ports_1_cache_0_virtualAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11758 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_0, Q = \\VexRiscv.MmuPlugin_ports_1_cache_0_virtualAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11757 ($dff) from module top (D = $flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3481_Y, Q = \\VexRiscv.MmuPlugin_ports_1_cache_0_superPage).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11756 ($dff) from module top (D = $flatten\\VexRiscv.$logic_or$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3484_Y, Q = \\VexRiscv.MmuPlugin_ports_1_cache_0_exception).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11755 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [4], Q = \\VexRiscv.MmuPlugin_ports_0_cache_3_allowUser).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11754 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [3], Q = \\VexRiscv.MmuPlugin_ports_0_cache_3_allowExecute).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11753 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [2], Q = \\VexRiscv.MmuPlugin_ports_0_cache_3_allowWrite).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11752 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [1], Q = \\VexRiscv.MmuPlugin_ports_0_cache_3_allowRead).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11751 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [29:20], Q = \\VexRiscv.MmuPlugin_ports_0_cache_3_physicalAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11750 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [19:10], Q = \\VexRiscv.MmuPlugin_ports_0_cache_3_physicalAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11749 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_1, Q = \\VexRiscv.MmuPlugin_ports_0_cache_3_virtualAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11748 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_0, Q = \\VexRiscv.MmuPlugin_ports_0_cache_3_virtualAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11747 ($dff) from module top (D = $flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3481_Y, Q = \\VexRiscv.MmuPlugin_ports_0_cache_3_superPage).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11746 ($dff) from module top (D = $flatten\\VexRiscv.$logic_or$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3484_Y, Q = \\VexRiscv.MmuPlugin_ports_0_cache_3_exception).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11745 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [4], Q = \\VexRiscv.MmuPlugin_ports_0_cache_2_allowUser).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11744 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [3], Q = \\VexRiscv.MmuPlugin_ports_0_cache_2_allowExecute).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11743 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [2], Q = \\VexRiscv.MmuPlugin_ports_0_cache_2_allowWrite).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11742 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [1], Q = \\VexRiscv.MmuPlugin_ports_0_cache_2_allowRead).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11741 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [29:20], Q = \\VexRiscv.MmuPlugin_ports_0_cache_2_physicalAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11740 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [19:10], Q = \\VexRiscv.MmuPlugin_ports_0_cache_2_physicalAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11739 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_1, Q = \\VexRiscv.MmuPlugin_ports_0_cache_2_virtualAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11738 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_0, Q = \\VexRiscv.MmuPlugin_ports_0_cache_2_virtualAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11737 ($dff) from module top (D = $flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3481_Y, Q = \\VexRiscv.MmuPlugin_ports_0_cache_2_superPage).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11736 ($dff) from module top (D = $flatten\\VexRiscv.$logic_or$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3484_Y, Q = \\VexRiscv.MmuPlugin_ports_0_cache_2_exception).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11735 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [4], Q = \\VexRiscv.MmuPlugin_ports_0_cache_1_allowUser).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11734 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [3], Q = \\VexRiscv.MmuPlugin_ports_0_cache_1_allowExecute).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11733 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [2], Q = \\VexRiscv.MmuPlugin_ports_0_cache_1_allowWrite).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11732 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [1], Q = \\VexRiscv.MmuPlugin_ports_0_cache_1_allowRead).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11731 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [29:20], Q = \\VexRiscv.MmuPlugin_ports_0_cache_1_physicalAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11730 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [19:10], Q = \\VexRiscv.MmuPlugin_ports_0_cache_1_physicalAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11729 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_1, Q = \\VexRiscv.MmuPlugin_ports_0_cache_1_virtualAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11728 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_0, Q = \\VexRiscv.MmuPlugin_ports_0_cache_1_virtualAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11727 ($dff) from module top (D = $flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3481_Y, Q = \\VexRiscv.MmuPlugin_ports_0_cache_1_superPage).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11726 ($dff) from module top (D = $flatten\\VexRiscv.$logic_or$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3484_Y, Q = \\VexRiscv.MmuPlugin_ports_0_cache_1_exception).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11725 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [4], Q = \\VexRiscv.MmuPlugin_ports_0_cache_0_allowUser).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11724 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [3], Q = \\VexRiscv.MmuPlugin_ports_0_cache_0_allowExecute).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11723 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [2], Q = \\VexRiscv.MmuPlugin_ports_0_cache_0_allowWrite).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11722 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [1], Q = \\VexRiscv.MmuPlugin_ports_0_cache_0_allowRead).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11721 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [29:20], Q = \\VexRiscv.MmuPlugin_ports_0_cache_0_physicalAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11720 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_cpu_writeBack_data [19:10], Q = \\VexRiscv.MmuPlugin_ports_0_cache_0_physicalAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11719 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_1, Q = \\VexRiscv.MmuPlugin_ports_0_cache_0_virtualAddress_1).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11718 ($dff) from module top (D = \\VexRiscv.MmuPlugin_shared_vpn_0, Q = \\VexRiscv.MmuPlugin_ports_0_cache_0_virtualAddress_0).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11717 ($dff) from module top (D = $flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3481_Y, Q = \\VexRiscv.MmuPlugin_ports_0_cache_0_superPage).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11716 ($dff) from module top (D = $flatten\\VexRiscv.$logic_or$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3484_Y, Q = \\VexRiscv.MmuPlugin_ports_0_cache_0_exception).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11715 ($dff) from module top (D = \\VexRiscv.execute_CsrPlugin_writeData [19:0], Q = \\VexRiscv.MmuPlugin_satp_ppn).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11713 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_mem_cmd_s2mPipe_payload_length, Q = \\VexRiscv._zz_144_).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11712 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_mem_cmd_s2mPipe_payload_mask, Q = \\VexRiscv._zz_143_).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11711 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_mem_cmd_s2mPipe_payload_data, Q = \\VexRiscv._zz_142_).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11710 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_mem_cmd_s2mPipe_payload_address, Q = \\VexRiscv._zz_141_).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11709 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_mem_cmd_s2mPipe_payload_wr, Q = \\VexRiscv._zz_140_).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11707 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_mem_cmd_payload_length, Q = \\VexRiscv._zz_137_).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11706 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stageB_mask, Q = \\VexRiscv._zz_136_).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11705 ($dff) from module top (D = \\VexRiscv.dataCache_1_.stageB_requestDataBypass, Q = \\VexRiscv._zz_135_).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11704 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_mem_cmd_payload_address, Q = \\VexRiscv._zz_134_).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11703 ($dff) from module top (D = \\VexRiscv.dataCache_1__io_mem_cmd_payload_wr, Q = \\VexRiscv._zz_133_).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11702 ($dff) from module top (D = \\VexRiscv.IBusCachedPlugin_s1_tightlyCoupledHit, Q = \\VexRiscv.IBusCachedPlugin_s2_tightlyCoupledHit).\nAdding EN signal on $flatten\\VexRiscv.$procdff$11701 ($dff) from module top (D = 1'0, Q = \\VexRiscv.IBusCachedPlugin_s1_tightlyCoupledHit).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$14072 ($dffe) from module top.\nAdding EN signal on $flatten\\VexRiscv.$procdff$11700 ($dff) from module top (D = \\VexRiscv.IBusCachedPlugin_fetchPc_pcReg, Q = \\VexRiscv._zz_119_).\n\n4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 985 unused cells and 959 unused wires.\n<suppressed ~1007 debug messages>\n\n4.14.8. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~46 debug messages>\n\n4.14.9. Rerunning OPT passes. (Maybe there is more to do..)\n\n4.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~610 debug messages>\n\n4.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\n    New input vector for $reduce_or cell $auto$opt_dff.cc:277:combine_resets$12556: { $auto$rtlil.cc:2121:Not$12554 $procmux$10261_CMP $procmux$10260_CMP }\n  Optimizing cells in module \\top.\nPerformed a total of 1 changes.\n\n4.14.12. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\n<suppressed ~522 debug messages>\nRemoved a total of 174 cells.\n\n4.14.13. Executing OPT_DFF pass (perform DFF optimizations).\nAdding SRST signal on $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11633 ($dff) from module top (D = 1'x, Q = $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:164$3833_DATA [1], rval = 1'0).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$14074 ($sdff) from module top.\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$14073 ($dffe) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$14073 ($dffe) from module top.\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$14071 ($dffe) from module top.\n\n4.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 0 unused cells and 174 unused wires.\n<suppressed ~1 debug messages>\n\n4.14.15. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~2 debug messages>\n\n4.14.16. Rerunning OPT passes. (Maybe there is more to do..)\n\n4.14.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~613 debug messages>\n\n4.14.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\nPerformed a total of 0 changes.\n\n4.14.19. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.14.20. Executing OPT_DFF pass (perform DFF optimizations).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$13659 ($dffe) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$13659 ($dffe) from module top.\n\n4.14.21. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 0 unused cells and 1 unused wires.\n<suppressed ~1 debug messages>\n\n4.14.22. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.14.23. Rerunning OPT passes. (Maybe there is more to do..)\n\n4.14.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~613 debug messages>\n\n4.14.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\nPerformed a total of 0 changes.\n\n4.14.26. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.14.27. Executing OPT_DFF pass (perform DFF optimizations).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$13658 ($dffe) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$13658 ($dffe) from module top.\n\n4.14.28. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.14.29. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.14.30. Rerunning OPT passes. (Maybe there is more to do..)\n\n4.14.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~613 debug messages>\n\n4.14.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\nPerformed a total of 0 changes.\n\n4.14.33. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.14.34. Executing OPT_DFF pass (perform DFF optimizations).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$13657 ($dffe) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$13657 ($dffe) from module top.\n\n4.14.35. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.14.36. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.14.37. Rerunning OPT passes. (Maybe there is more to do..)\n\n4.14.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~613 debug messages>\n\n4.14.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\nPerformed a total of 0 changes.\n\n4.14.40. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.14.41. Executing OPT_DFF pass (perform DFF optimizations).\n\n4.14.42. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.14.43. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.14.44. Finished OPT passes. (There is nothing left to do.)\n\n4.15. Executing WREDUCE pass (reducing word size of cells).\nRemoved top 18 address bits (of 32) from memory init port top.$meminit$\\mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1954 (mem).\nRemoved top 26 address bits (of 32) from memory init port top.$meminit$\\mem_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1955 (mem_2).\nRemoved top 2 bits (of 13) from port A of cell top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1907$337 ($or).\nRemoved top 4 bits (of 13) from port B of cell top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1907$337 ($or).\nRemoved top 2 bits (of 13) from port Y of cell top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1907$337 ($or).\nRemoved top 2 bits (of 13) from port A of cell top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2058$367 ($or).\nRemoved top 4 bits (of 13) from port B of cell top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2058$367 ($or).\nRemoved top 2 bits (of 13) from port Y of cell top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2058$367 ($or).\nRemoved top 2 bits (of 13) from port A of cell top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2209$397 ($or).\nRemoved top 4 bits (of 13) from port B of cell top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2209$397 ($or).\nRemoved top 2 bits (of 13) from port Y of cell top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2209$397 ($or).\nRemoved top 5 bits (of 9) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$12628 ($ne).\nRemoved top 2 bits (of 13) from port A of cell top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2360$427 ($or).\nRemoved top 4 bits (of 13) from port B of cell top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2360$427 ($or).\nRemoved top 2 bits (of 13) from port Y of cell top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2360$427 ($or).\nRemoved top 9 bits (of 30) from port Y of cell top.$sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2847$798 ($sub).\nRemoved top 9 bits (of 30) from port A of cell top.$sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2847$798 ($sub).\nRemoved top 26 bits (of 27) from port B of cell top.$sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2847$798 ($sub).\nRemoved top 5 bits (of 9) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$12648 ($ne).\nRemoved top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$12775 ($ne).\nRemoved top 5 bits (of 9) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$12668 ($ne).\nRemoved cell top.$procmux$8460 ($mux).\nRemoved cell top.$procmux$8462 ($mux).\nRemoved cell top.$procmux$8466 ($mux).\nRemoved cell top.$procmux$8468 ($mux).\nRemoved cell top.$procmux$8472 ($mux).\nRemoved cell top.$procmux$8474 ($mux).\nRemoved cell top.$procmux$8478 ($mux).\nRemoved cell top.$procmux$8480 ($mux).\nRemoved cell top.$procmux$8484 ($mux).\nRemoved cell top.$procmux$8486 ($mux).\nRemoved cell top.$procmux$8490 ($mux).\nRemoved cell top.$procmux$8492 ($mux).\nRemoved cell top.$procmux$8496 ($mux).\nRemoved cell top.$procmux$8498 ($mux).\nRemoved cell top.$procmux$8502 ($mux).\nRemoved cell top.$procmux$8504 ($mux).\nRemoved cell top.$procmux$8508 ($mux).\nRemoved cell top.$procmux$8510 ($mux).\nRemoved cell top.$procmux$8514 ($mux).\nRemoved cell top.$procmux$8516 ($mux).\nRemoved cell top.$procmux$8520 ($mux).\nRemoved cell top.$procmux$8522 ($mux).\nRemoved cell top.$procmux$8526 ($mux).\nRemoved cell top.$procmux$8528 ($mux).\nRemoved cell top.$procmux$8532 ($mux).\nRemoved cell top.$procmux$8534 ($mux).\nRemoved cell top.$procmux$8538 ($mux).\nRemoved cell top.$procmux$8540 ($mux).\nRemoved cell top.$procmux$8544 ($mux).\nRemoved cell top.$procmux$8546 ($mux).\nRemoved cell top.$procmux$8550 ($mux).\nRemoved cell top.$procmux$8552 ($mux).\nRemoved cell top.$procmux$8556 ($mux).\nRemoved cell top.$procmux$8558 ($mux).\nRemoved cell top.$procmux$8562 ($mux).\nRemoved cell top.$procmux$8564 ($mux).\nRemoved cell top.$procmux$8568 ($mux).\nRemoved cell top.$procmux$8570 ($mux).\nRemoved cell top.$procmux$8574 ($mux).\nRemoved cell top.$procmux$8576 ($mux).\nRemoved cell top.$procmux$8580 ($mux).\nRemoved cell top.$procmux$8582 ($mux).\nRemoved cell top.$procmux$8588 ($mux).\nRemoved cell top.$procmux$8590 ($mux).\nRemoved cell top.$procmux$8596 ($mux).\nRemoved cell top.$procmux$8598 ($mux).\nRemoved cell top.$procmux$8602 ($mux).\nRemoved cell top.$procmux$8604 ($mux).\nRemoved cell top.$procmux$8608 ($mux).\nRemoved cell top.$procmux$8610 ($mux).\nRemoved cell top.$procmux$8614 ($mux).\nRemoved cell top.$procmux$8616 ($mux).\nRemoved cell top.$procmux$8620 ($mux).\nRemoved cell top.$procmux$8622 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$8747_CMP0 ($eq).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$8758_CMP0 ($eq).\nRemoved top 2 bits (of 3) from port B of cell top.$procmux$8770_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$procmux$8814_CMP0 ($eq).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$8825_CMP0 ($eq).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$8826_CMP0 ($eq).\nRemoved top 2 bits (of 3) from port B of cell top.$procmux$8827_CMP0 ($eq).\nRemoved top 1 bits (of 5) from port B of cell top.$procmux$8843_CMP0 ($eq).\nRemoved top 1 bits (of 5) from port B of cell top.$procmux$8844_CMP0 ($eq).\nRemoved top 1 bits (of 5) from port B of cell top.$procmux$8845_CMP0 ($eq).\nRemoved top 1 bits (of 5) from port B of cell top.$procmux$8846_CMP0 ($eq).\nRemoved top 1 bits (of 5) from port B of cell top.$procmux$8847_CMP0 ($eq).\nRemoved top 1 bits (of 5) from port B of cell top.$procmux$8848_CMP0 ($eq).\nRemoved top 1 bits (of 5) from port B of cell top.$procmux$8849_CMP0 ($eq).\nRemoved top 1 bits (of 5) from port B of cell top.$procmux$8850_CMP0 ($eq).\nRemoved top 2 bits (of 5) from port B of cell top.$procmux$8851_CMP0 ($eq).\nRemoved top 2 bits (of 5) from port B of cell top.$procmux$8852_CMP0 ($eq).\nRemoved top 2 bits (of 5) from port B of cell top.$procmux$8853_CMP0 ($eq).\nRemoved top 2 bits (of 5) from port B of cell top.$procmux$8854_CMP0 ($eq).\nRemoved top 3 bits (of 5) from port B of cell top.$procmux$8855_CMP0 ($eq).\nRemoved top 3 bits (of 5) from port B of cell top.$procmux$8856_CMP0 ($eq).\nRemoved top 4 bits (of 5) from port B of cell top.$procmux$8857_CMP0 ($eq).\nRemoved top 1 bits (of 4) from port B of cell top.$procmux$8873_CMP0 ($eq).\nRemoved top 1 bits (of 4) from port B of cell top.$procmux$8874_CMP0 ($eq).\nRemoved top 1 bits (of 4) from port B of cell top.$procmux$8875_CMP0 ($eq).\nRemoved top 1 bits (of 4) from port B of cell top.$procmux$8876_CMP0 ($eq).\nRemoved top 2 bits (of 4) from port B of cell top.$procmux$8877_CMP0 ($eq).\nRemoved top 2 bits (of 4) from port B of cell top.$procmux$8878_CMP0 ($eq).\nRemoved top 3 bits (of 4) from port B of cell top.$procmux$8879_CMP0 ($eq).\nRemoved top 2 bits (of 13) from mux cell top.$procmux$9040 ($mux).\nRemoved top 7 bits (of 8) from mux cell top.$procmux$9141 ($mux).\nRemoved cell top.$procmux$9147 ($mux).\nRemoved cell top.$procmux$9264 ($mux).\nRemoved cell top.$procmux$9271 ($mux).\nRemoved top 1 bits (of 3) from mux cell top.$procmux$9278 ($mux).\nRemoved cell top.$procmux$9326 ($mux).\nRemoved cell top.$procmux$9336 ($mux).\nRemoved top 1 bits (of 2) from mux cell top.$procmux$9339 ($mux).\nRemoved cell top.$procmux$9345 ($mux).\nRemoved cell top.$procmux$9354 ($mux).\nRemoved top 1 bits (of 2) from mux cell top.$procmux$9357 ($mux).\nRemoved top 1 bits (of 2) from mux cell top.$procmux$9408 ($mux).\nRemoved cell top.$procmux$9424 ($mux).\nRemoved cell top.$procmux$9440 ($mux).\nRemoved cell top.$procmux$9494 ($mux).\nRemoved cell top.$procmux$9497 ($mux).\nRemoved top 1 bits (of 2) from mux cell top.$procmux$9503 ($mux).\nRemoved cell top.$procmux$9519 ($mux).\nRemoved cell top.$procmux$9535 ($mux).\nRemoved cell top.$procmux$9589 ($mux).\nRemoved cell top.$procmux$9592 ($mux).\nRemoved top 1 bits (of 2) from mux cell top.$procmux$9598 ($mux).\nRemoved cell top.$procmux$9614 ($mux).\nRemoved cell top.$procmux$9630 ($mux).\nRemoved cell top.$procmux$9684 ($mux).\nRemoved cell top.$procmux$9687 ($mux).\nRemoved top 1 bits (of 2) from mux cell top.$procmux$9693 ($mux).\nRemoved cell top.$procmux$9709 ($mux).\nRemoved cell top.$procmux$9725 ($mux).\nRemoved cell top.$procmux$9779 ($mux).\nRemoved cell top.$procmux$9782 ($mux).\nRemoved cell top.$procmux$9797 ($mux).\nRemoved cell top.$procmux$9837 ($mux).\nRemoved cell top.$procmux$9875 ($mux).\nRemoved cell top.$procmux$9878 ($mux).\nRemoved cell top.$procmux$9886 ($mux).\nRemoved cell top.$procmux$9907 ($mux).\nRemoved cell top.$procmux$9910 ($mux).\nRemoved cell top.$procmux$9918 ($mux).\nRemoved cell top.$procmux$9939 ($mux).\nRemoved cell top.$procmux$9964 ($mux).\nRemoved cell top.$procmux$9967 ($mux).\nRemoved cell top.$procmux$9998 ($mux).\nRemoved cell top.$procmux$10001 ($mux).\nRemoved cell top.$procmux$10003 ($mux).\nRemoved cell top.$procmux$10016 ($mux).\nRemoved cell top.$procmux$10019 ($mux).\nRemoved cell top.$procmux$10021 ($mux).\nRemoved cell top.$procmux$10068 ($mux).\nRemoved cell top.$procmux$10081 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$10093_CMP0 ($eq).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$10094_CMP0 ($eq).\nRemoved top 2 bits (of 3) from port B of cell top.$procmux$10095_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$procmux$10100_CMP0 ($eq).\nRemoved cell top.$procmux$10151 ($mux).\nRemoved top 1 bits (of 2) from port B of cell top.$procmux$10159_CMP0 ($eq).\nRemoved cell top.$procmux$10256 ($mux).\nRemoved top 1 bits (of 2) from port B of cell top.$procmux$10261_CMP0 ($eq).\nRemoved top 24 bits (of 32) from mux cell top.$procmux$10290 ($mux).\nRemoved cell top.$procmux$10300 ($mux).\nRemoved cell top.$procmux$10303 ($mux).\nRemoved cell top.$procmux$10307 ($mux).\nRemoved cell top.$procmux$10309 ($mux).\nRemoved cell top.$procmux$10312 ($mux).\nRemoved top 1 bits (of 2) from port B of cell top.$procmux$10314_CMP0 ($eq).\nRemoved top 2 bits (of 18) from mux cell top.$procmux$10367 ($pmux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$10371_CMP0 ($eq).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$10372_CMP0 ($eq).\nRemoved top 2 bits (of 3) from port B of cell top.$procmux$10373_CMP0 ($eq).\nRemoved cell top.$procmux$10410 ($mux).\nRemoved cell top.$procmux$10413 ($mux).\nRemoved cell top.$procmux$10417 ($mux).\nRemoved top 1 bits (of 2) from mux cell top.$procmux$10421 ($mux).\nRemoved top 1 bits (of 2) from port B of cell top.$procmux$10426_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$procmux$10499_CMP0 ($eq).\nRemoved cell top.$procmux$10515 ($mux).\nRemoved cell top.$procmux$10517 ($mux).\nRemoved cell top.$procmux$10525 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$10527_CMP0 ($eq).\nRemoved cell top.$procmux$10528 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$10530_CMP0 ($eq).\nRemoved cell top.$procmux$10531 ($mux).\nRemoved cell top.$procmux$10533 ($mux).\nRemoved top 2 bits (of 3) from mux cell top.$procmux$10535 ($mux).\nRemoved top 2 bits (of 3) from port B of cell top.$procmux$10537_CMP0 ($eq).\nRemoved cell top.$procmux$10615 ($mux).\nRemoved top 1 bits (of 3) from mux cell top.$procmux$10617 ($mux).\nRemoved top 1 bits (of 3) from mux cell top.$procmux$10619 ($mux).\nRemoved cell top.$procmux$10621 ($mux).\nRemoved cell top.$procmux$10627 ($mux).\nRemoved cell top.$procmux$10631 ($mux).\nRemoved cell top.$procmux$10633 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$10635_CMP0 ($eq).\nRemoved cell top.$procmux$10636 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$10638_CMP0 ($eq).\nRemoved cell top.$procmux$10639 ($mux).\nRemoved cell top.$procmux$10641 ($mux).\nRemoved top 2 bits (of 3) from port B of cell top.$procmux$10643_CMP0 ($eq).\nRemoved cell top.$procmux$10836 ($mux).\nRemoved top 1 bits (of 3) from mux cell top.$procmux$10838 ($mux).\nRemoved top 1 bits (of 3) from mux cell top.$procmux$10840 ($mux).\nRemoved cell top.$procmux$10842 ($mux).\nRemoved cell top.$procmux$10852 ($mux).\nRemoved cell top.$procmux$10854 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$10856_CMP0 ($eq).\nRemoved cell top.$procmux$10857 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$10859_CMP0 ($eq).\nRemoved cell top.$procmux$10860 ($mux).\nRemoved cell top.$procmux$10862 ($mux).\nRemoved top 2 bits (of 3) from port B of cell top.$procmux$10864_CMP0 ($eq).\nRemoved cell top.$procmux$11057 ($mux).\nRemoved top 1 bits (of 3) from mux cell top.$procmux$11059 ($mux).\nRemoved top 1 bits (of 3) from mux cell top.$procmux$11061 ($mux).\nRemoved cell top.$procmux$11063 ($mux).\nRemoved cell top.$procmux$11073 ($mux).\nRemoved cell top.$procmux$11075 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$11077_CMP0 ($eq).\nRemoved cell top.$procmux$11078 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$11080_CMP0 ($eq).\nRemoved cell top.$procmux$11081 ($mux).\nRemoved cell top.$procmux$11083 ($mux).\nRemoved top 2 bits (of 3) from port B of cell top.$procmux$11085_CMP0 ($eq).\nRemoved cell top.$procmux$11278 ($mux).\nRemoved top 1 bits (of 3) from mux cell top.$procmux$11280 ($mux).\nRemoved top 1 bits (of 3) from mux cell top.$procmux$11282 ($mux).\nRemoved cell top.$procmux$11284 ($mux).\nRemoved cell top.$procmux$11294 ($mux).\nRemoved cell top.$procmux$11296 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$11298_CMP0 ($eq).\nRemoved cell top.$procmux$11299 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$procmux$11301_CMP0 ($eq).\nRemoved cell top.$procmux$11302 ($mux).\nRemoved cell top.$procmux$11304 ($mux).\nRemoved top 2 bits (of 3) from port B of cell top.$procmux$11306_CMP0 ($eq).\nRemoved cell top.$procmux$11497 ($mux).\nRemoved cell top.$procmux$11500 ($mux).\nRemoved cell top.$procmux$11504 ($mux).\nRemoved top 1 bits (of 2) from port B of cell top.$procmux$11506_CMP0 ($eq).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12002 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12006 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12010 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12014 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12018 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12022 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12026 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12030 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12034 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12038 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12042 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12046 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12050 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12054 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12058 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12062 ($dff).\nRemoved top 23 bits (of 24) from FF cell top.$procdff$12066 ($dff).\nRemoved top 24 bits (of 25) from FF cell top.$procdff$12070 ($dff).\nRemoved top 24 bits (of 25) from FF cell top.$procdff$12074 ($dff).\nRemoved top 24 bits (of 25) from FF cell top.$procdff$12078 ($dff).\nRemoved top 24 bits (of 25) from FF cell top.$procdff$12082 ($dff).\nRemoved top 9 bits (of 10) from FF cell top.$procdff$12087 ($dff).\nRemoved top 2 bits (of 10) from FF cell top.$auto$opt_dff.cc:764:run$13280 ($dffe).\nRemoved top 9 bits (of 10) from FF cell top.$procdff$12092 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12097 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12100 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12103 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$procdff$12106 ($dff).\nRemoved top 2 bits (of 10) from FF cell top.$auto$opt_dff.cc:764:run$13278 ($dffe).\nRemoved top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$13721 ($ne).\nRemoved top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$13534 ($ne).\nRemoved top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$13532 ($ne).\nRemoved top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$13530 ($ne).\nRemoved top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$13528 ($ne).\nRemoved top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$13199 ($ne).\nRemoved top 2 bits (of 13) from FF cell top.$auto$opt_dff.cc:702:run$13056 ($sdff).\nRemoved top 30 bits (of 32) from port B of cell top.$flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:540$3652 ($add).\nRemoved top 1 bits (of 2) from mux cell top.$flatten\\VexRiscv.\\dataCache_1_.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:544$3656 ($mux).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.\\dataCache_1_.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:934$3778 ($eq).\nRemoved top 2 bits (of 3) from port B of cell top.$flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1053$3798 ($add).\nRemoved top 6 bits (of 7) from port B of cell top.$flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1141$3817 ($add).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4205 ($mux).\nRemoved top 27 bits (of 32) from mux cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4209 ($mux).\nRemoved top 27 bits (of 32) from mux cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4218 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4223 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4371_CMP0 ($eq).\nRemoved top 1 bits (of 3) from port B of cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4372_CMP0 ($eq).\nRemoved top 2 bits (of 3) from port B of cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4373_CMP0 ($eq).\nRemoved top 7 bits (of 8) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$12600 ($ne).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4512_CMP0 ($eq).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4520 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4528 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4533 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4541 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4549 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4554 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4562 ($mux).\nRemoved top 5 bits (of 9) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$12608 ($ne).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4570 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4575 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4583 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4591 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4596 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4674 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4677 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4683 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4689 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4695 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4707 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4713 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4734 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4736 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4740 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4742 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4746 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4748 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4752 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4754 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4760 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4762 ($mux).\nRemoved top 7 bits (of 8) from FF cell top.$flatten\\VexRiscv.\\dataCache_1_.$procdff$11686 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$flatten\\VexRiscv.\\dataCache_1_.$procdff$11689 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$flatten\\VexRiscv.\\dataCache_1_.$procdff$11692 ($dff).\nRemoved top 7 bits (of 8) from FF cell top.$flatten\\VexRiscv.\\dataCache_1_.$procdff$11695 ($dff).\nRemoved top 21 bits (of 22) from FF cell top.$flatten\\VexRiscv.\\dataCache_1_.$procdff$11699 ($dff).\nRemoved top 2 bits (of 3) from port B of cell top.$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:301$3884 ($add).\nRemoved top 7 bits (of 8) from port B of cell top.$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:314$3886 ($add).\nRemoved cell top.$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$3948 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$3964 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$4002 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$4004 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$4010 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procmux$4012 ($mux).\nRemoved top 31 bits (of 32) from FF cell top.$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11630 ($dff).\nRemoved top 21 bits (of 22) from FF cell top.$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$procdff$11634 ($dff).\nRemoved top 31 bits (of 32) from FF cell top.$flatten\\VexRiscv.$procdff$11998 ($dff).\nRemoved top 2 bits (of 32) from FF cell top.$auto$opt_dff.cc:764:run$13391 ($sdffe).\nRemoved top 2 bits (of 32) from FF cell top.$auto$opt_dff.cc:764:run$13687 ($dffe).\nRemoved top 2 bits (of 12) from FF cell top.$auto$opt_dff.cc:764:run$13760 ($dffe).\nRemoved cell top.$flatten\\VexRiscv.$procmux$8456 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$8454 ($mux).\nRemoved top 2 bits (of 3) from port B of cell top.$flatten\\VexRiscv.$procmux$8446_CMP0 ($eq).\nRemoved top 1 bits (of 3) from port B of cell top.$flatten\\VexRiscv.$procmux$8445_CMP0 ($eq).\nRemoved top 1 bits (of 3) from port B of cell top.$flatten\\VexRiscv.$procmux$8444_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$procmux$8390_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$procmux$8335_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$procmux$8194_CMP0 ($eq).\nRemoved cell top.$flatten\\VexRiscv.$procmux$8017 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$7956 ($mux).\nRemoved top 20 bits (of 32) from mux cell top.$flatten\\VexRiscv.$procmux$7932 ($mux).\nRemoved top 20 bits (of 32) from mux cell top.$flatten\\VexRiscv.$procmux$7927 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$7905 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$7823 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$7818 ($mux).\nRemoved top 1 bits (of 4) from mux cell top.$flatten\\VexRiscv.$procmux$7812 ($mux).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$procmux$7803_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$procmux$7793_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$procmux$7673_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$procmux$7669_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$procmux$7664_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$procmux$7660_CMP0 ($eq).\nRemoved top 2 bits (of 4) from port B of cell top.$flatten\\VexRiscv.$procmux$7466_CMP0 ($eq).\nRemoved top 1 bits (of 4) from port B of cell top.$flatten\\VexRiscv.$procmux$7450_CMP0 ($eq).\nRemoved top 1 bits (of 4) from port B of cell top.$flatten\\VexRiscv.$procmux$7421_CMP0 ($eq).\nRemoved top 1 bits (of 4) from port B of cell top.$flatten\\VexRiscv.$procmux$7408_CMP0 ($eq).\nRemoved top 3 bits (of 4) from port B of cell top.$flatten\\VexRiscv.$procmux$7396_CMP0 ($eq).\nRemoved top 1 bits (of 4) from port B of cell top.$flatten\\VexRiscv.$procmux$7358_CMP0 ($eq).\nRemoved cell top.$flatten\\VexRiscv.$procmux$7015 ($mux).\nRemoved top 2 bits (of 4) from mux cell top.$flatten\\VexRiscv.$procmux$7006 ($pmux).\nRemoved top 2 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$6656_CMP0 ($eq).\nRemoved top 2 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$6649_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$procmux$6634_CMP0 ($eq).\nRemoved cell top.$flatten\\VexRiscv.$procmux$6600 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$6593 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$6586 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$6572 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$6551 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$6496 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$6300 ($mux).\nRemoved top 2 bits (of 3) from port B of cell top.$flatten\\VexRiscv.$procmux$6299_CMP0 ($eq).\nRemoved cell top.$flatten\\VexRiscv.$procmux$6297 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$6294 ($mux).\nRemoved top 1 bits (of 3) from mux cell top.$flatten\\VexRiscv.$procmux$6290 ($mux).\nRemoved top 1 bits (of 3) from port B of cell top.$flatten\\VexRiscv.$procmux$6289_CMP0 ($eq).\nRemoved cell top.$flatten\\VexRiscv.$procmux$6286 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$6283 ($mux).\nRemoved top 1 bits (of 3) from mux cell top.$flatten\\VexRiscv.$procmux$6281 ($mux).\nRemoved top 2 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$6036_CMP0 ($eq).\nRemoved top 2 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5994_CMP0 ($eq).\nRemoved top 2 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5929_CMP0 ($eq).\nRemoved top 3 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5926_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$procmux$5914_CMP0 ($eq).\nRemoved top 3 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5877_CMP0 ($eq).\nRemoved top 2 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5848_CMP0 ($eq).\nRemoved top 3 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5845_CMP0 ($eq).\nRemoved top 3 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5662_CMP0 ($eq).\nRemoved cell top.$flatten\\VexRiscv.$procmux$5168 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$5162 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$5156 ($mux).\nRemoved top 2 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5119_CMP0 ($eq).\nRemoved top 2 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5109_CMP0 ($eq).\nRemoved top 2 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5093_CMP0 ($eq).\nRemoved top 3 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5064_CMP0 ($eq).\nRemoved top 3 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5057_CMP0 ($eq).\nRemoved top 3 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5035_CMP0 ($eq).\nRemoved top 3 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5017_CMP0 ($eq).\nRemoved top 3 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$5005_CMP0 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$procmux$4995_CMP0 ($eq).\nRemoved cell top.$flatten\\VexRiscv.$procmux$4985 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$4977 ($mux).\nRemoved top 2 bits (of 12) from port B of cell top.$flatten\\VexRiscv.$procmux$4932_CMP0 ($eq).\nRemoved cell top.$flatten\\VexRiscv.$procmux$4916 ($mux).\nRemoved cell top.$flatten\\VexRiscv.$procmux$4914 ($mux).\nRemoved top 31 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7535$3537 ($add).\nRemoved top 32 bits (of 33) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3534 ($add).\nRemoved top 1 bits (of 33) from port Y of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3534 ($add).\nRemoved top 1 bits (of 33) from port A of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3534 ($add).\nRemoved top 1 bits (of 33) from mux cell top.$flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3533 ($mux).\nRemoved top 1 bits (of 33) from port Y of cell top.$flatten\\VexRiscv.$not$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3532 ($not).\nRemoved top 1 bits (of 33) from port A of cell top.$flatten\\VexRiscv.$not$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3532 ($not).\nRemoved top 1 bits (of 3) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7328$3481 ($eq).\nRemoved top 2 bits (of 3) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7255$3474 ($add).\nRemoved top 2 bits (of 3) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7250$3471 ($add).\nRemoved top 27 bits (of 32) from mux cell top.$flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6693$3414 ($mux).\nRemoved top 30 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6615$3350 ($and).\nRemoved top 30 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6613$3348 ($and).\nRemoved top 1 bits (of 33) from port B of cell top.$flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6604$3340 ($sub).\nRemoved top 5 bits (of 6) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6595$3339 ($add).\nRemoved top 14 bits (of 66) from port A of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6572$3333 ($add).\nRemoved top 2 bits (of 66) from port Y of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6572$3333 ($add).\nRemoved top 2 bits (of 66) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6572$3333 ($add).\nRemoved top 2 bits (of 52) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6571$3332 ($add).\nRemoved top 17 bits (of 34) from port A of cell top.$flatten\\VexRiscv.$mul$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6570$3331 ($mul).\nRemoved top 17 bits (of 34) from port B of cell top.$flatten\\VexRiscv.$mul$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6570$3331 ($mul).\nRemoved top 17 bits (of 34) from port A of cell top.$flatten\\VexRiscv.$mul$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6569$3330 ($mul).\nRemoved top 17 bits (of 34) from port B of cell top.$flatten\\VexRiscv.$mul$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6569$3330 ($mul).\nRemoved top 17 bits (of 34) from port A of cell top.$flatten\\VexRiscv.$mul$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6568$3329 ($mul).\nRemoved top 17 bits (of 34) from port B of cell top.$flatten\\VexRiscv.$mul$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6568$3329 ($mul).\nRemoved top 1 bits (of 7) from port B of cell top.$flatten\\VexRiscv.$ne$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6210$3291 ($ne).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6209$3283 ($eq).\nRemoved top 12 bits (of 32) from mux cell top.$flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5969$3224 ($mux).\nRemoved top 2 bits (of 3) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5823$3206 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5717$3189 ($eq).\nRemoved top 27 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5503$3166 ($eq).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5503$3165 ($and).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5503$3164 ($eq).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5503$3163 ($and).\nRemoved top 30 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5503$3162 ($eq).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5503$3161 ($and).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5503$3160 ($eq).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5503$3159 ($and).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5503$3158 ($eq).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5502$3156 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5502$3154 ($eq).\nRemoved top 29 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5500$3149 ($eq).\nRemoved top 29 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5500$3148 ($and).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5499$3147 ($eq).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5499$3146 ($and).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5498$3145 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5498$3144 ($and).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5497$3143 ($eq).\nRemoved top 29 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5496$3141 ($eq).\nRemoved top 28 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5496$3140 ($and).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5376$3092 ($add).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5277$3028 ($add).\nRemoved top 2 bits (of 4) from mux cell top.$flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5134$2982 ($mux).\nRemoved top 7 bits (of 32) from mux cell top.$flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4893$2941 ($mux).\nRemoved top 12 bits (of 32) from mux cell top.$flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4877$2929 ($mux).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4783$2919 ($eq).\nRemoved top 29 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4687$2888 ($add).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4461$2849 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4461$2847 ($eq).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3188$2810 ($eq).\nRemoved top 3 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3187$2808 ($eq).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3183$2805 ($eq).\nRemoved top 3 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3183$2803 ($eq).\nRemoved top 3 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3183$2801 ($eq).\nRemoved top 3 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3183$2799 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3182$2798 ($eq).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3181$2796 ($eq).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3177$2793 ($eq).\nRemoved top 4 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3177$2791 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3177$2789 ($eq).\nRemoved top 7 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3177$2788 ($and).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3177$2787 ($eq).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3176$2786 ($eq).\nRemoved top 3 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3176$2785 ($and).\nRemoved top 28 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3175$2784 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3175$2783 ($and).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3173$2782 ($and).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3171$2781 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3171$2780 ($and).\nRemoved top 30 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3171$2779 ($eq).\nRemoved top 30 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3171$2777 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3171$2776 ($and).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3171$2775 ($eq).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3170$2774 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3169$2772 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3169$2771 ($and).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3167$2770 ($and).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3162$2769 ($and).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3160$2768 ($and).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3158$2767 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3158$2766 ($and).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3157$2765 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3157$2764 ($and).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3156$2763 ($eq).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3153$2760 ($eq).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3153$2759 ($eq).\nRemoved top 27 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3152$2758 ($eq).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3152$2757 ($and).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3151$2756 ($eq).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3151$2755 ($and).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3150$2754 ($eq).\nRemoved top 3 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3150$2753 ($and).\nRemoved top 4 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3149$2752 ($eq).\nRemoved top 4 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3149$2751 ($and).\nRemoved top 28 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3143$2746 ($eq).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3140$2745 ($eq).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3139$2744 ($eq).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3139$2743 ($and).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3137$2742 ($and).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3132$2738 ($eq).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3130$2737 ($eq).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3130$2736 ($and).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3126$2733 ($and).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3113$2725 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3112$2724 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3112$2723 ($and).\nRemoved top 29 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3111$2722 ($eq).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3111$2721 ($and).\nRemoved top 29 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3110$2720 ($eq).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3092$2709 ($and).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3090$2708 ($and).\nRemoved top 3 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3086$2706 ($and).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3080$2702 ($eq).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3080$2701 ($eq).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3079$2700 ($eq).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3079$2699 ($eq).\nRemoved top 4 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3078$2698 ($eq).\nRemoved top 4 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3078$2697 ($and).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3077$2695 ($and).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3075$2694 ($and).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3073$2693 ($and).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3067$2691 ($and).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3060$2688 ($eq).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3058$2687 ($eq).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3057$2686 ($eq).\nRemoved top 1 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3056$2685 ($eq).\nRemoved top 1 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3056$2684 ($and).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3054$2683 ($and).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3052$2682 ($and).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3051$2681 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3051$2680 ($and).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3049$2679 ($and).\nRemoved top 27 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3045$2677 ($eq).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3045$2676 ($and).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3043$2675 ($and).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3036$2672 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3035$2671 ($eq).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3033$2670 ($and).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3031$2669 ($eq).\nRemoved top 27 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3030$2667 ($and).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3026$2665 ($eq).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3025$2664 ($eq).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3025$2663 ($and).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3023$2662 ($and).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3020$2658 ($eq).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3017$2656 ($eq).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3014$2655 ($and).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3011$2651 ($eq).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3010$2649 ($eq).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3010$2648 ($and).\nRemoved top 3 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3008$2647 ($eq).\nRemoved top 3 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3008$2646 ($and).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3006$2645 ($and).\nRemoved top 27 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3004$2644 ($and).\nRemoved top 1 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3002$2643 ($and).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3000$2642 ($and).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2997$2638 ($eq).\nRemoved top 29 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2996$2636 ($eq).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2994$2635 ($eq).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2994$2634 ($and).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2994$2633 ($eq).\nRemoved top 1 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2994$2632 ($eq).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2992$2631 ($and).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2989$2630 ($and).\nRemoved top 18 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2985$2626 ($eq).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2983$2625 ($eq).\nRemoved top 19 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2983$2624 ($and).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2982$2623 ($eq).\nRemoved top 6 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2982$2622 ($and).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2980$2621 ($and).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2979$2620 ($eq).\nRemoved top 27 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2978$2619 ($eq).\nRemoved top 26 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2978$2618 ($and).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2977$2617 ($eq).\nRemoved top 17 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2977$2616 ($and).\nRemoved top 25 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2975$2615 ($and).\nRemoved top 1 bits (of 33) from port A of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2916$2613 ($add).\nRemoved top 32 bits (of 33) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2916$2613 ($add).\nRemoved top 1 bits (of 33) from port Y of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2916$2613 ($add).\nRemoved top 19 bits (of 52) from port A of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2895$2605 ($add).\nRemoved top 2 bits (of 52) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2895$2605 ($add).\nRemoved top 1 bits (of 52) from port Y of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2895$2605 ($add).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2894$2604 ($sub).\nRemoved top 1 bits (of 2) from port Y of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2893$2603 ($and).\nRemoved top 1 bits (of 2) from port A of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2893$2603 ($and).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$and$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2893$2603 ($and).\nRemoved top 1 bits (of 2) from port Y of cell top.$flatten\\VexRiscv.$not$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2893$2602 ($not).\nRemoved top 1 bits (of 2) from port A of cell top.$flatten\\VexRiscv.$not$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2893$2602 ($not).\nRemoved top 1 bits (of 33) from port Y of cell top.$flatten\\VexRiscv.$sshr$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2880$2599 ($sshr).\nRemoved top 31 bits (of 32) from mux cell top.$flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2877$2598 ($mux).\nRemoved top 30 bits (of 32) from port B of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2873$2594 ($add).\nRemoved top 1 bits (of 3) from mux cell top.$flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2835$2593 ($mux).\nRemoved top 1 bits (of 3) from mux cell top.$flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2834$2592 ($mux).\nRemoved top 4 bits (of 5) from port B of cell top.$flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2823$2591 ($sub).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$lt$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2809$2560 ($lt).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2809$2558 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2806$2555 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2802$2551 ($eq).\nRemoved top 1 bits (of 2) from port B of cell top.$flatten\\VexRiscv.$eq$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2778$2517 ($eq).\nRemoved top 7 bits (of 10) from mux cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4557 ($mux).\nRemoved cell top.$flatten\\VexRiscv.\\dataCache_1_.$procmux$4686 ($mux).\nRemoved top 2 bits (of 34) from FF cell top.$auto$opt_dff.cc:764:run$13669 ($dffe).\nRemoved top 1 bits (of 52) from port A of cell top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6571$3332 ($add).\nRemoved top 1 bits (of 2) from port Y of cell top.$flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2894$2604 ($sub).\nRemoved top 1 bits (of 2) from port A of cell top.$flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2894$2604 ($sub).\nRemoved top 2 bits (of 34) from FF cell top.$auto$opt_dff.cc:764:run$13670 ($dffe).\nRemoved top 2 bits (of 34) from port Y of cell top.$flatten\\VexRiscv.$mul$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6570$3331 ($mul).\nRemoved top 24 bits (of 32) from wire top.$0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_EN[31:0]$1791.\nRemoved top 16 bits (of 32) from wire top.$0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_DATA[31:0]$1793.\nRemoved top 8 bits (of 32) from wire top.$0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_DATA[31:0]$1796.\nRemoved top 8 bits (of 32) from wire top.$0$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_EN[31:0]$1797.\nRemoved top 2 bits (of 25) from wire top.$0$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_DATA[24:0]$1820.\nRemoved top 2 bits (of 25) from wire top.$0$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_DATA[24:0]$1827.\nRemoved top 2 bits (of 25) from wire top.$0$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_DATA[24:0]$1834.\nRemoved top 2 bits (of 25) from wire top.$0$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_DATA[24:0]$1841.\nRemoved top 1 bits (of 33) from wire top.$flatten\\VexRiscv.$0\\memory_DivPlugin_rs1[32:0].\nRemoved top 2 bits (of 4) from wire top.$flatten\\VexRiscv.$2\\DBusCachedPlugin_exceptionBus_payload_code[3:0].\nRemoved top 20 bits (of 32) from wire top.$flatten\\VexRiscv.$2\\_zz_249_[31:0].\nRemoved top 2 bits (of 4) from wire top.$flatten\\VexRiscv.$3\\CsrPlugin_selfException_payload_code[3:0].\nRemoved top 1 bits (of 4) from wire top.$flatten\\VexRiscv.$3\\DBusCachedPlugin_exceptionBus_payload_code[3:0].\nRemoved top 1 bits (of 33) from wire top.$flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3534_Y.\nRemoved top 1 bits (of 2) from wire top.$flatten\\VexRiscv.$not$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2893$2602_Y.\nRemoved top 1 bits (of 33) from wire top.$flatten\\VexRiscv.$not$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3532_Y.\nRemoved top 1 bits (of 3) from wire top.$flatten\\VexRiscv.$procmux$6281_Y.\nRemoved top 1 bits (of 3) from wire top.$flatten\\VexRiscv.$procmux$6290_Y.\nRemoved top 2 bits (of 4) from wire top.$flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5134$2982_Y.\nRemoved top 1 bits (of 33) from wire top.$flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3533_Y.\nRemoved top 24 bits (of 32) from wire top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5772$231_DATA.\nRemoved top 16 bits (of 32) from wire top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5774$232_DATA.\nRemoved top 8 bits (of 32) from wire top.$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5776$233_DATA.\nRemoved top 2 bits (of 10) from wire top.$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5805$235_DATA.\nRemoved top 2 bits (of 10) from wire top.$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5822$236_DATA.\nRemoved top 2 bits (of 25) from wire top.$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5838$237_DATA.\nRemoved top 2 bits (of 25) from wire top.$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5852$238_DATA.\nRemoved top 2 bits (of 25) from wire top.$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5866$239_DATA.\nRemoved top 2 bits (of 25) from wire top.$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5880$240_DATA.\nRemoved top 2 bits (of 13) from wire top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1907$337_Y.\nRemoved top 2 bits (of 13) from wire top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2058$367_Y.\nRemoved top 2 bits (of 13) from wire top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2209$397_Y.\nRemoved top 2 bits (of 13) from wire top.$or$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2360$427_Y.\nRemoved top 1 bits (of 8) from wire top.$procmux$10016_Y.\nRemoved top 1 bits (of 8) from wire top.$procmux$10019_Y.\nRemoved top 1 bits (of 8) from wire top.$procmux$10021_Y.\nRemoved top 1 bits (of 2) from wire top.$procmux$10421_Y.\nRemoved top 2 bits (of 3) from wire top.$procmux$10535_Y.\nRemoved top 1 bits (of 3) from wire top.$procmux$10617_Y.\nRemoved top 1 bits (of 3) from wire top.$procmux$10619_Y.\nRemoved top 1 bits (of 3) from wire top.$procmux$10838_Y.\nRemoved top 1 bits (of 3) from wire top.$procmux$10840_Y.\nRemoved top 1 bits (of 3) from wire top.$procmux$11059_Y.\nRemoved top 1 bits (of 3) from wire top.$procmux$11061_Y.\nRemoved top 1 bits (of 3) from wire top.$procmux$11280_Y.\nRemoved top 1 bits (of 3) from wire top.$procmux$11282_Y.\nRemoved top 2 bits (of 13) from wire top.$procmux$9040_Y.\nRemoved top 1 bits (of 2) from wire top.$procmux$9339_Y.\nRemoved top 1 bits (of 2) from wire top.$procmux$9357_Y.\nRemoved top 24 bits (of 32) from wire top.builder_soclinux_wishbone_dat_r.\nRemoved top 2 bits (of 25) from wire top.main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din.\nRemoved top 2 bits (of 25) from wire top.main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w.\nRemoved top 2 bits (of 25) from wire top.main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din.\nRemoved top 2 bits (of 25) from wire top.main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w.\nRemoved top 2 bits (of 25) from wire top.main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din.\nRemoved top 2 bits (of 25) from wire top.main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w.\nRemoved top 2 bits (of 25) from wire top.main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din.\nRemoved top 2 bits (of 25) from wire top.main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w.\nRemoved top 30 bits (of 32) from wire top.main_soclinux_cpu_interrupt0.\nRemoved top 4 bits (of 23) from wire top.main_tag_di_tag.\nRemoved top 2 bits (of 144) from wire top.main_wishbone_bridge_wdata_converter_converter_sink_payload_data.\n\n4.16. Executing PEEPOPT pass (run peephole optimizers).\n\n4.17. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 1 unused cells and 276 unused wires.\n<suppressed ~14 debug messages>\n\n4.18. Executing SHARE pass (SAT-based resource sharing).\nFound 18 cells in module top that may be considered for resource sharing.\n  Analyzing resource sharing options for $memrd$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5898$1850 ($memrd):\n    Found 5 activation_patterns using ctrl signal { $procmux$10426_CMP $eq$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2796$796_Y \\builder_done \\builder_litedramwishbone2native_state \\main_write_from_slave }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\mem_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5794$1803 ($memrd):\n    Found 1 activation_patterns using ctrl signal { $procmux$10260_CMP \\builder_csr_bankarray_sel_r }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6053$1901 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10499_CMP $procmux$10370_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6043$1896 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10499_CMP $procmux$10370_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6033$1891 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10498_CMP $procmux$10371_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6023$1886 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10498_CMP $procmux$10371_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6013$1881 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10498_CMP $procmux$10372_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6003$1876 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10498_CMP $procmux$10372_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5993$1871 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10500_CMP $procmux$10499_CMP $procmux$10498_CMP $procmux$10373_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5983$1866 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10500_CMP $procmux$10499_CMP $procmux$10498_CMP $procmux$10373_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6113$1931 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10500_CMP $procmux$10374_CMP $procmux$10373_CMP $procmux$10372_CMP $procmux$10371_CMP $procmux$10370_CMP $procmux$10369_CMP $procmux$10368_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6103$1926 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10500_CMP $procmux$10374_CMP $procmux$10373_CMP $procmux$10372_CMP $procmux$10371_CMP $procmux$10370_CMP $procmux$10369_CMP $procmux$10368_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6093$1921 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10500_CMP $procmux$10368_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6083$1916 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10500_CMP $procmux$10368_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6073$1911 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10499_CMP $procmux$10369_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6063$1906 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10499_CMP $procmux$10369_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5973$1861 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10500_CMP $procmux$10499_CMP $procmux$10498_CMP $procmux$10374_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n  Analyzing resource sharing options for $memrd$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5963$1856 ($memrd):\n    Found 2 activation_patterns using ctrl signal { $procmux$10500_CMP $procmux$10499_CMP $procmux$10498_CMP $procmux$10374_CMP \\builder_new_master_wdata_ready \\main_sdram_storage [0] }.\n    No candidates found.\n\n4.19. Executing TECHMAP pass (map to technology primitives).\n\n4.19.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v\nParsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.\nGenerating RTLIL representation for module `\\_90_lut_cmp_'.\nSuccessfully finished Verilog frontend.\n\n4.19.2. Continuing TECHMAP pass.\nUsing template $paramod$3ee26d6ec3e84c62780ab3a1e6835af3ab9d7465\\_90_lut_cmp_ for cells of type $lt.\nUsing template $paramod$f3a9875e03c52965378a785308bba19d20f90391\\_90_lut_cmp_ for cells of type $lt.\nNo more expansions possible.\n<suppressed ~118 debug messages>\n\n4.20. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~5 debug messages>\n\n4.21. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 0 unused cells and 8 unused wires.\n<suppressed ~2 debug messages>\n\n4.22. Executing TECHMAP pass (map to technology primitives).\n\n4.22.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/mul2dsp.v\nParsing Verilog input from `/usr/local/bin/../share/yosys/mul2dsp.v' to AST representation.\nGenerating RTLIL representation for module `\\_80_mul'.\nGenerating RTLIL representation for module `\\_90_soft_mul'.\nSuccessfully finished Verilog frontend.\n\n4.22.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/dsp_map.v\nParsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/dsp_map.v' to AST representation.\nGenerating RTLIL representation for module `\\$__MUL18X18'.\nSuccessfully finished Verilog frontend.\n\n4.22.3. Continuing TECHMAP pass.\nUsing template $paramod$57246927cd958ceb8a1b66d0a5c7acbd283b286a\\_80_mul for cells of type $mul.\nUsing template $paramod$4f6754d98eb10d060cb1338d1ad25ec95f03045a\\_80_mul for cells of type $mul.\nUsing template $paramod$738639264c9aebc655ebda67fba0129d74a9b416\\_80_mul for cells of type $mul.\nUsing template $paramod\\$__MUL18X18\\A_WIDTH=18\\B_WIDTH=18\\Y_WIDTH=32\\A_SIGNED=1\\B_SIGNED=1 for cells of type $__MUL18X18.\nUsing template $paramod\\$__MUL18X18\\A_WIDTH=18\\B_WIDTH=18\\Y_WIDTH=32\\A_SIGNED=0\\B_SIGNED=0 for cells of type $__MUL18X18.\nUsing template $paramod\\$__MUL18X18\\A_WIDTH=18\\B_WIDTH=18\\Y_WIDTH=34\\A_SIGNED=1\\B_SIGNED=1 for cells of type $__MUL18X18.\nNo more expansions possible.\n<suppressed ~268 debug messages>\n\n4.23. Executing ALUMACC pass (create $alu and $macc cells).\nExtracting $alu and $macc cells in module top:\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2876$824 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3063$846 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4246$1563 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4249$1564 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4272$1576 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4288$1579 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4301$1583 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4320$1586 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4346$1594 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4349$1595 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4353$1600 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4368$1605 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4371$1606 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4375$1611 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4474$1630 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4491$1634 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4494$1635 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4498$1640 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4567$1656 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4570$1657 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4574$1662 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4643$1678 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4646$1679 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4650$1684 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4719$1700 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4722$1701 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4726$1706 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4992$1764 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5003$1767 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5064$1777 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2873$2594 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2874$2595 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2895$2605 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2916$2613 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4687$2888 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4877$2930 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5277$3028 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5376$3092 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6015$3227 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6571$3332 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6572$3333 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6595$3339 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7250$3471 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7255$3474 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3534 ($add).\n  creating $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7535$3537 ($add).\n  creating $macc model for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2874$823 ($add).\n  creating $macc model for $flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2823$2591 ($sub).\n  creating $macc model for $flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2894$2604 ($sub).\n  creating $macc model for $flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6604$3340 ($sub).\n  creating $macc model for $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:301$3884 ($add).\n  creating $macc model for $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:314$3886 ($add).\n  creating $macc model for $flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1053$3798 ($add).\n  creating $macc model for $flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1141$3817 ($add).\n  creating $macc model for $flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:540$3652 ($add).\n  creating $macc model for $flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:541$3653 ($add).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3036$841 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3037$843 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3065$847 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4357$1601 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4379$1612 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4400$1614 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4421$1619 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4427$1620 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4438$1623 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4502$1641 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4521$1645 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4536$1648 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4551$1651 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4578$1663 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4597$1667 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4612$1670 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4627$1673 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4654$1685 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4673$1689 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4688$1692 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4703$1695 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4730$1707 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4749$1711 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4764$1714 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4779$1717 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4790$1721 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4797$1724 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4929$1729 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4944$1732 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4959$1735 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5059$1776 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5082$1781 ($sub).\n  creating $macc model for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5128$1785 ($sub).\n  merging $macc model for $flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:541$3653 into $flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:540$3652.\n  merging $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2895$2605 into $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6571$3332.\n  merging $macc model for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2874$2595 into $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2873$2594.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4959$1735.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4944$1732.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4929$1729.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4797$1724.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4790$1721.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4779$1717.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4764$1714.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4749$1711.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4730$1707.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4703$1695.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4688$1692.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4673$1689.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4654$1685.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4627$1673.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4612$1670.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4597$1667.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4578$1663.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4551$1651.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4536$1648.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4521$1645.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4502$1641.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4438$1623.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4427$1620.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4421$1619.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4400$1614.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4379$1612.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4357$1601.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3065$847.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3037$843.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3036$841.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5059$1776.\n  creating $alu model for $macc $flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1141$3817.\n  creating $alu model for $macc $flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1053$3798.\n  creating $alu model for $macc $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:314$3886.\n  creating $alu model for $macc $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:301$3884.\n  creating $alu model for $macc $flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6604$3340.\n  creating $alu model for $macc $flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2894$2604.\n  creating $alu model for $macc $flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2823$2591.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2874$823.\n  creating $alu model for $macc $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7535$3537.\n  creating $alu model for $macc $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3534.\n  creating $alu model for $macc $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7255$3474.\n  creating $alu model for $macc $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7250$3471.\n  creating $alu model for $macc $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6595$3339.\n  creating $alu model for $macc $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6572$3333.\n  creating $alu model for $macc $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6015$3227.\n  creating $alu model for $macc $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5376$3092.\n  creating $alu model for $macc $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5277$3028.\n  creating $alu model for $macc $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4877$2930.\n  creating $alu model for $macc $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4687$2888.\n  creating $alu model for $macc $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2916$2613.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5082$1781.\n  creating $alu model for $macc $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5128$1785.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5064$1777.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5003$1767.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4992$1764.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4726$1706.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4722$1701.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4719$1700.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4650$1684.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4646$1679.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4643$1678.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4574$1662.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4570$1657.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4567$1656.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4498$1640.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4494$1635.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4491$1634.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4474$1630.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4375$1611.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4371$1606.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4368$1605.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4353$1600.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4349$1595.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4346$1594.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4320$1586.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4301$1583.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4288$1579.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4272$1576.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4249$1564.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4246$1563.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3063$846.\n  creating $alu model for $macc $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2876$824.\n  creating $macc cell for $flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:540$3652: $auto$alumacc.cc:365:replace_macc$14148\n  creating $macc cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6571$3332: $auto$alumacc.cc:365:replace_macc$14149\n  creating $macc cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2873$2594: $auto$alumacc.cc:365:replace_macc$14150\n  creating $alu model for $flatten\\VexRiscv.$lt$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6107$3265 ($lt): new $alu\n  creating $alu model for $flatten\\VexRiscv.$lt$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6333$3295 ($lt): new $alu\n  creating $alu model for $ge$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1564$259 ($ge): new $alu\n  creating $alu cell for $ge$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:1564$259: $auto$alumacc.cc:485:replace_alu$14154\n  creating $alu cell for $flatten\\VexRiscv.$lt$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6333$3295: $auto$alumacc.cc:485:replace_alu$14163\n  creating $alu cell for $flatten\\VexRiscv.$lt$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6107$3265: $auto$alumacc.cc:485:replace_alu$14168\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2876$824: $auto$alumacc.cc:485:replace_alu$14173\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3063$846: $auto$alumacc.cc:485:replace_alu$14176\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4246$1563: $auto$alumacc.cc:485:replace_alu$14179\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4249$1564: $auto$alumacc.cc:485:replace_alu$14182\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4272$1576: $auto$alumacc.cc:485:replace_alu$14185\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4288$1579: $auto$alumacc.cc:485:replace_alu$14188\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4301$1583: $auto$alumacc.cc:485:replace_alu$14191\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4320$1586: $auto$alumacc.cc:485:replace_alu$14194\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4346$1594: $auto$alumacc.cc:485:replace_alu$14197\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4349$1595: $auto$alumacc.cc:485:replace_alu$14200\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4353$1600: $auto$alumacc.cc:485:replace_alu$14203\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4368$1605: $auto$alumacc.cc:485:replace_alu$14206\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4371$1606: $auto$alumacc.cc:485:replace_alu$14209\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4375$1611: $auto$alumacc.cc:485:replace_alu$14212\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4474$1630: $auto$alumacc.cc:485:replace_alu$14215\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4491$1634: $auto$alumacc.cc:485:replace_alu$14218\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4494$1635: $auto$alumacc.cc:485:replace_alu$14221\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4498$1640: $auto$alumacc.cc:485:replace_alu$14224\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4567$1656: $auto$alumacc.cc:485:replace_alu$14227\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4570$1657: $auto$alumacc.cc:485:replace_alu$14230\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4574$1662: $auto$alumacc.cc:485:replace_alu$14233\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4643$1678: $auto$alumacc.cc:485:replace_alu$14236\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4646$1679: $auto$alumacc.cc:485:replace_alu$14239\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4650$1684: $auto$alumacc.cc:485:replace_alu$14242\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4719$1700: $auto$alumacc.cc:485:replace_alu$14245\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4722$1701: $auto$alumacc.cc:485:replace_alu$14248\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4726$1706: $auto$alumacc.cc:485:replace_alu$14251\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4992$1764: $auto$alumacc.cc:485:replace_alu$14254\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5003$1767: $auto$alumacc.cc:485:replace_alu$14257\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5064$1777: $auto$alumacc.cc:485:replace_alu$14260\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5128$1785: $auto$alumacc.cc:485:replace_alu$14263\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5082$1781: $auto$alumacc.cc:485:replace_alu$14266\n  creating $alu cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2916$2613: $auto$alumacc.cc:485:replace_alu$14269\n  creating $alu cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4687$2888: $auto$alumacc.cc:485:replace_alu$14272\n  creating $alu cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4877$2930: $auto$alumacc.cc:485:replace_alu$14275\n  creating $alu cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5277$3028: $auto$alumacc.cc:485:replace_alu$14278\n  creating $alu cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5376$3092: $auto$alumacc.cc:485:replace_alu$14281\n  creating $alu cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6015$3227: $auto$alumacc.cc:485:replace_alu$14284\n  creating $alu cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6572$3333: $auto$alumacc.cc:485:replace_alu$14287\n  creating $alu cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6595$3339: $auto$alumacc.cc:485:replace_alu$14290\n  creating $alu cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7250$3471: $auto$alumacc.cc:485:replace_alu$14293\n  creating $alu cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7255$3474: $auto$alumacc.cc:485:replace_alu$14296\n  creating $alu cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7534$3534: $auto$alumacc.cc:485:replace_alu$14299\n  creating $alu cell for $flatten\\VexRiscv.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7535$3537: $auto$alumacc.cc:485:replace_alu$14302\n  creating $alu cell for $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2874$823: $auto$alumacc.cc:485:replace_alu$14305\n  creating $alu cell for $flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2823$2591: $auto$alumacc.cc:485:replace_alu$14308\n  creating $alu cell for $flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2894$2604: $auto$alumacc.cc:485:replace_alu$14311\n  creating $alu cell for $flatten\\VexRiscv.$sub$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6604$3340: $auto$alumacc.cc:485:replace_alu$14314\n  creating $alu cell for $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:301$3884: $auto$alumacc.cc:485:replace_alu$14317\n  creating $alu cell for $flatten\\VexRiscv.\\IBusCachedPlugin_cache.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:314$3886: $auto$alumacc.cc:485:replace_alu$14320\n  creating $alu cell for $flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1053$3798: $auto$alumacc.cc:485:replace_alu$14323\n  creating $alu cell for $flatten\\VexRiscv.\\dataCache_1_.$add$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:1141$3817: $auto$alumacc.cc:485:replace_alu$14326\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5059$1776: $auto$alumacc.cc:485:replace_alu$14329\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3036$841: $auto$alumacc.cc:485:replace_alu$14332\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3037$843: $auto$alumacc.cc:485:replace_alu$14335\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:3065$847: $auto$alumacc.cc:485:replace_alu$14338\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4357$1601: $auto$alumacc.cc:485:replace_alu$14341\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4379$1612: $auto$alumacc.cc:485:replace_alu$14344\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4400$1614: $auto$alumacc.cc:485:replace_alu$14347\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4421$1619: $auto$alumacc.cc:485:replace_alu$14350\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4427$1620: $auto$alumacc.cc:485:replace_alu$14353\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4438$1623: $auto$alumacc.cc:485:replace_alu$14356\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4502$1641: $auto$alumacc.cc:485:replace_alu$14359\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4521$1645: $auto$alumacc.cc:485:replace_alu$14362\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4536$1648: $auto$alumacc.cc:485:replace_alu$14365\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4551$1651: $auto$alumacc.cc:485:replace_alu$14368\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4578$1663: $auto$alumacc.cc:485:replace_alu$14371\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4597$1667: $auto$alumacc.cc:485:replace_alu$14374\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4612$1670: $auto$alumacc.cc:485:replace_alu$14377\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4627$1673: $auto$alumacc.cc:485:replace_alu$14380\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4654$1685: $auto$alumacc.cc:485:replace_alu$14383\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4673$1689: $auto$alumacc.cc:485:replace_alu$14386\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4688$1692: $auto$alumacc.cc:485:replace_alu$14389\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4703$1695: $auto$alumacc.cc:485:replace_alu$14392\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4730$1707: $auto$alumacc.cc:485:replace_alu$14395\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4749$1711: $auto$alumacc.cc:485:replace_alu$14398\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4764$1714: $auto$alumacc.cc:485:replace_alu$14401\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4779$1717: $auto$alumacc.cc:485:replace_alu$14404\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4790$1721: $auto$alumacc.cc:485:replace_alu$14407\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4797$1724: $auto$alumacc.cc:485:replace_alu$14410\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4929$1729: $auto$alumacc.cc:485:replace_alu$14413\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4944$1732: $auto$alumacc.cc:485:replace_alu$14416\n  creating $alu cell for $sub$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4959$1735: $auto$alumacc.cc:485:replace_alu$14419\n  created 86 $alu and 3 $macc cells.\n\n4.24. Executing OPT pass (performing simple optimizations).\n\n4.24.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~3 debug messages>\n\n4.24.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\n<suppressed ~153 debug messages>\nRemoved a total of 51 cells.\n\n4.24.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~536 debug messages>\n\n4.24.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\n    New ctrl vector for $pmux cell $procmux$10415: { $procmux$10426_CMP $procmux$10419_CMP }\n    New ctrl vector for $pmux cell $procmux$10522: { $procmux$10537_CMP $auto$opt_reduce.cc:134:opt_mux$14423 $procmux$10524_CMP $procmux$10523_CMP }\n    New ctrl vector for $pmux cell $procmux$10629: { $auto$opt_reduce.cc:134:opt_mux$14427 $auto$opt_reduce.cc:134:opt_mux$14425 }\n    New ctrl vector for $pmux cell $procmux$10850: { $auto$opt_reduce.cc:134:opt_mux$14431 $auto$opt_reduce.cc:134:opt_mux$14429 }\n    New ctrl vector for $pmux cell $procmux$11071: { $auto$opt_reduce.cc:134:opt_mux$14435 $auto$opt_reduce.cc:134:opt_mux$14433 }\n    New ctrl vector for $pmux cell $procmux$11292: { $auto$opt_reduce.cc:134:opt_mux$14439 $auto$opt_reduce.cc:134:opt_mux$14437 }\n  Optimizing cells in module \\top.\nPerformed a total of 6 changes.\n\n4.24.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\n<suppressed ~9 debug messages>\nRemoved a total of 3 cells.\n\n4.24.6. Executing OPT_DFF pass (perform DFF optimizations).\nSetting constant 1-bit at position 0 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 1 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 2 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 3 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 4 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 5 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 6 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 7 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 8 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 9 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 10 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 11 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 12 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 13 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 14 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 15 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 16 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 17 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 18 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 19 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 20 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 21 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 22 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 23 on $procdff$12105 ($dff) from module top.\nSetting constant 1-bit at position 0 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 1 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 2 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 3 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 4 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 5 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 6 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 7 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 8 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 9 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 10 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 11 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 12 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 13 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 14 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 15 on $procdff$12102 ($dff) from module top.\nSetting constant 1-bit at position 0 on $procdff$12099 ($dff) from module top.\nSetting constant 1-bit at position 1 on $procdff$12099 ($dff) from module top.\nSetting constant 1-bit at position 2 on $procdff$12099 ($dff) from module top.\nSetting constant 1-bit at position 3 on $procdff$12099 ($dff) from module top.\nSetting constant 1-bit at position 4 on $procdff$12099 ($dff) from module top.\nSetting constant 1-bit at position 5 on $procdff$12099 ($dff) from module top.\nSetting constant 1-bit at position 6 on $procdff$12099 ($dff) from module top.\nSetting constant 1-bit at position 7 on $procdff$12099 ($dff) from module top.\nAdding SRST signal on $procdff$12069 ($dff) from module top (D = { $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2874$823_Y [23:11] $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:2874$823_Y [8:0] \\main_interface_we }, Q = $auto$wreduce.cc:454:run$14103 [22:0], rval = 23'00000000000000000000000).\nAdding SRST signal on $procdff$12065 ($dff) from module top (D = $procmux$10431_Y, Q = $memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5894$241_DATA [23], rval = 1'0).\nSetting constant 0-bit at position 1 on $flatten\\VexRiscv.\\dataCache_1_.$procdff$11698 ($dff) from module top.\nAdding SRST signal on $auto$opt_dff.cc:764:run$13215 ($dffe) from module top (D = \\memdat_2 [7], Q = \\main_soclinux_tx_reg [7], rval = 1'0).\nAdding SRST signal on $auto$opt_dff.cc:764:run$13165 ($dffe) from module top (D = $add$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:4301$1583_Y, Q = \\main_soclinux_rx_bitcount, rval = 4'0000).\n\n4.24.7. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 9 unused cells and 117 unused wires.\n<suppressed ~34 debug messages>\n\n4.24.8. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.24.9. Rerunning OPT passes. (Maybe there is more to do..)\n\n4.24.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~534 debug messages>\n\n4.24.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\nPerformed a total of 0 changes.\n\n4.24.12. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.24.13. Executing OPT_DFF pass (perform DFF optimizations).\n\n4.24.14. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.24.15. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.24.16. Finished OPT passes. (There is nothing left to do.)\n\n4.25. Executing MEMORY pass.\n\n4.25.1. Executing OPT_MEM pass (optimize memories).\nPerformed a total of 0 transformations.\n\n4.25.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\nChecking cell `$flatten\\VexRiscv.$memwr$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:0$3613' in module `\\top': merged $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$memwr$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:0$3892' in module `\\top': merged $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:0$3891' in module `\\top': merged $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\dataCache_1_.$memwr$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:0$3829' in module `\\top': merged $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\dataCache_1_.$memwr$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:0$3830' in module `\\top': merged $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\dataCache_1_.$memwr$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:0$3831' in module `\\top': merged $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\dataCache_1_.$memwr$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:0$3832' in module `\\top': merged $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\dataCache_1_.$memwr$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:0$3828' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1967' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1968' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1977' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1978' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1979' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1980' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1981' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1982' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1969' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1970' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1971' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1972' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1973' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1974' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1975' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1976' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1956' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1957' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1958' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1959' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1960' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1961' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1962' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1963' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1964' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1965' in module `\\top': merged $dff to cell.\nChecking cell `$memwr$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1966' in module `\\top': merged $dff to cell.\nChecking cell `$flatten\\VexRiscv.$memrd$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3200$2816' in module `\\top': merged data $dff to cell.\nChecking cell `$flatten\\VexRiscv.$memrd$\\RegFilePlugin_regFile$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:3206$2818' in module `\\top': merged data $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$memrd$\\ways_0_datas$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:182$3850' in module `\\top': merged data $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\IBusCachedPlugin_cache.$memrd$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:170$3844' in module `\\top': merged data $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\dataCache_1_.$memrd$\\ways_0_data_symbol0$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:585$3683' in module `\\top': merged data $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\dataCache_1_.$memrd$\\ways_0_data_symbol1$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:586$3684' in module `\\top': merged data $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\dataCache_1_.$memrd$\\ways_0_data_symbol2$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:587$3685' in module `\\top': merged data $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\dataCache_1_.$memrd$\\ways_0_data_symbol3$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:588$3686' in module `\\top': merged data $dff to cell.\nChecking cell `$flatten\\VexRiscv.\\dataCache_1_.$memrd$\\ways_0_tags$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:561$3663' in module `\\top': merged data $dff to cell.\nChecking cell `$memrd$\\data_mem_grain0$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5963$1856' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5973$1861' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain10$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6063$1906' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain11$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6073$1911' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain12$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6083$1916' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain13$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6093$1921' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain14$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6103$1926' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain15$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6113$1931' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5983$1866' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5993$1871' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6003$1876' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6013$1881' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain6$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6023$1886' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain7$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6033$1891' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain8$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6043$1896' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\data_mem_grain9$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:6053$1901' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5759$1787' in module `\\top': merged data $dff to cell.\nChecking cell `$memrd$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5782$1801' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\mem_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5794$1803' in module `\\top': merged address $dff to cell.\nChecking cell `$memrd$\\storage$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5811$1810' in module `\\top': no (compatible) $dff found.\nChecking cell `$memrd$\\storage_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5828$1817' in module `\\top': no (compatible) $dff found.\nChecking cell `$memrd$\\storage_2$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5846$1824' in module `\\top': no (compatible) $dff found.\nChecking cell `$memrd$\\storage_3$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5860$1831' in module `\\top': no (compatible) $dff found.\nChecking cell `$memrd$\\storage_4$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5874$1838' in module `\\top': no (compatible) $dff found.\nChecking cell `$memrd$\\storage_5$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5888$1845' in module `\\top': no (compatible) $dff found.\nChecking cell `$memrd$\\tag_mem$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:5898$1850' in module `\\top': merged address $dff to cell.\n\n4.25.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 92 unused cells and 117 unused wires.\n<suppressed ~112 debug messages>\n\n4.25.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\nConsolidating write ports of memory top.mem_1 by address:\n  New clock domain: posedge \\VexRiscv.IBusCachedPlugin_cache.clk\n    Port 0 ($memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1956) has addr \\builder_soclinux_wishbone_adr [10:0].\n      Active bits: 00000000000000000000000011111111\n    Port 1 ($memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1957) has addr \\builder_soclinux_wishbone_adr [10:0].\n      Active bits: 00000000000000001111111100000000\n      Merging port 0 into this one.\n      Active bits: 00000000000000001111111111111111\n    Port 2 ($memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1958) has addr \\builder_soclinux_wishbone_adr [10:0].\n      Active bits: 00000000111111110000000000000000\n      Merging port 1 into this one.\n      Active bits: 00000000111111111111111111111111\n    Port 3 ($memwr$\\mem_1$/home/pi/oss/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v:0$1959) has addr \\builder_soclinux_wishbone_adr [10:0].\n      Active bits: 11111111000000000000000000000000\n      Merging port 2 into this one.\n      Active bits: 11111111111111111111111111111111\n\n4.25.5. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.25.6. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n4.26. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.27. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\nProcessing top.VexRiscv.IBusCachedPlugin_cache.ways_0_datas:\n  Properties: ports=2 bits=32768 rports=1 wports=1 dbits=32 abits=10 words=1024\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=4 bwaste=2048 waste=2048 efficiency=88\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -1 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=2048 efficiency=88\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=4 bwaste=2048 waste=2048 efficiency=88\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=4 bwaste=2048 waste=2048 efficiency=88\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=4096 waste=4096 efficiency=88\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -1 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=4096 efficiency=88\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=4 bwaste=13312 waste=13312 efficiency=44\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -1 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=13312 efficiency=44\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=12288 efficiency=25\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 5):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=4096 waste=4096 efficiency=88\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=4 bwaste=13312 waste=13312 efficiency=44\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=4096 waste=4096 efficiency=88\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=4 bwaste=13312 waste=13312 efficiency=44\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 6 rules:\n    Efficiency for rule 4.5: efficiency=6, cells=32, acells=1\n    Efficiency for rule 4.4: efficiency=12, cells=16, acells=1\n    Efficiency for rule 4.3: efficiency=25, cells=8, acells=1\n    Efficiency for rule 4.2: efficiency=44, cells=4, acells=1\n    Efficiency for rule 4.1: efficiency=88, cells=2, acells=1\n    Efficiency for rule 1.1: efficiency=88, cells=2, acells=2\n    Selected rule 4.1 with efficiency 88.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -1 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: VexRiscv.IBusCachedPlugin_cache.ways_0_datas.0.0.0\n      Creating $__ECP5_DP16KD cell at grid position <1 0 0>: VexRiscv.IBusCachedPlugin_cache.ways_0_datas.1.0.0\nProcessing top.VexRiscv.IBusCachedPlugin_cache.ways_0_tags:\n  Properties: ports=2 bits=2816 rports=1 wports=1 dbits=22 abits=7 words=128\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=384 dwaste=14 bwaste=15616 waste=15616 efficiency=15\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 -1 -1 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15616 efficiency=15\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=384 dwaste=14 bwaste=15616 waste=15616 efficiency=15\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=384 dwaste=14 bwaste=15616 waste=15616 efficiency=15\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=896 dwaste=14 bwaste=17920 waste=17920 efficiency=7\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 -1 -1 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=17920 efficiency=7\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1920 dwaste=5 bwaste=17920 waste=17920 efficiency=5\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 -1 -1 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=17920 efficiency=5\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3968 dwaste=2 bwaste=16128 waste=16128 efficiency=2\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8064 dwaste=0 bwaste=16128 waste=16128 efficiency=1\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16256 dwaste=0 bwaste=16256 waste=16256 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=896 dwaste=14 bwaste=17920 waste=17920 efficiency=7\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1920 dwaste=5 bwaste=17920 waste=17920 efficiency=5\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3968 dwaste=2 bwaste=16128 waste=16128 efficiency=2\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8064 dwaste=0 bwaste=16128 waste=16128 efficiency=1\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16256 dwaste=0 bwaste=16256 waste=16256 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=896 dwaste=14 bwaste=17920 waste=17920 efficiency=7\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1920 dwaste=5 bwaste=17920 waste=17920 efficiency=5\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3968 dwaste=2 bwaste=16128 waste=16128 efficiency=2\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8064 dwaste=0 bwaste=16128 waste=16128 efficiency=1\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16256 dwaste=0 bwaste=16256 waste=16256 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 3 rules:\n    Efficiency for rule 4.2: efficiency=5, cells=3, acells=1\n    Efficiency for rule 4.1: efficiency=7, cells=2, acells=1\n    Efficiency for rule 1.1: efficiency=15, cells=1, acells=1\n    Selected rule 1.1 with efficiency 15.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 -1 -1 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_PDPW16KD cell at grid position <0 0 0>: VexRiscv.IBusCachedPlugin_cache.ways_0_tags.0.0.0\nProcessing top.VexRiscv.RegFilePlugin_regFile:\n  Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min bits 2048' not met.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  No acceptable bram resources found.\nProcessing top.VexRiscv.dataCache_1_.ways_0_data_symbol0:\n  Properties: ports=2 bits=8192 rports=1 wports=1 dbits=8 abits=10 words=1024\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=10240 efficiency=44\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=1 bwaste=10240 waste=10240 efficiency=44\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=10240 efficiency=44\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=12288 efficiency=25\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 5):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=1 bwaste=10240 waste=10240 efficiency=44\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=1 bwaste=10240 waste=10240 efficiency=44\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 6 rules:\n    Efficiency for rule 4.5: efficiency=6, cells=8, acells=1\n    Efficiency for rule 4.4: efficiency=12, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=25, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=44, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=44, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=2, acells=2\n    Selected rule 4.2 with efficiency 44.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: VexRiscv.dataCache_1_.ways_0_data_symbol0.0.0.0\nProcessing top.VexRiscv.dataCache_1_.ways_0_data_symbol1:\n  Properties: ports=2 bits=8192 rports=1 wports=1 dbits=8 abits=10 words=1024\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=10240 efficiency=44\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=1 bwaste=10240 waste=10240 efficiency=44\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=10240 efficiency=44\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=12288 efficiency=25\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 5):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=1 bwaste=10240 waste=10240 efficiency=44\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=1 bwaste=10240 waste=10240 efficiency=44\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 6 rules:\n    Efficiency for rule 4.5: efficiency=6, cells=8, acells=1\n    Efficiency for rule 4.4: efficiency=12, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=25, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=44, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=44, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=2, acells=2\n    Selected rule 4.2 with efficiency 44.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: VexRiscv.dataCache_1_.ways_0_data_symbol1.0.0.0\nProcessing top.VexRiscv.dataCache_1_.ways_0_data_symbol2:\n  Properties: ports=2 bits=8192 rports=1 wports=1 dbits=8 abits=10 words=1024\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=10240 efficiency=44\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=1 bwaste=10240 waste=10240 efficiency=44\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=10240 efficiency=44\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=12288 efficiency=25\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 5):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=1 bwaste=10240 waste=10240 efficiency=44\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=1 bwaste=10240 waste=10240 efficiency=44\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 6 rules:\n    Efficiency for rule 4.5: efficiency=6, cells=8, acells=1\n    Efficiency for rule 4.4: efficiency=12, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=25, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=44, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=44, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=2, acells=2\n    Selected rule 4.2 with efficiency 44.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: VexRiscv.dataCache_1_.ways_0_data_symbol2.0.0.0\nProcessing top.VexRiscv.dataCache_1_.ways_0_data_symbol3:\n  Properties: ports=2 bits=8192 rports=1 wports=1 dbits=8 abits=10 words=1024\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=10240 efficiency=44\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=1 bwaste=10240 waste=10240 efficiency=44\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=10240 efficiency=44\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=12288 efficiency=25\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 5):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=1 bwaste=10240 waste=10240 efficiency=44\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1024 dwaste=1 bwaste=10240 waste=10240 efficiency=44\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 6 rules:\n    Efficiency for rule 4.5: efficiency=6, cells=8, acells=1\n    Efficiency for rule 4.4: efficiency=12, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=25, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=44, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=44, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=2, acells=2\n    Selected rule 4.2 with efficiency 44.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: VexRiscv.dataCache_1_.ways_0_data_symbol3.0.0.0\nProcessing top.VexRiscv.dataCache_1_.ways_0_tags:\n  Properties: ports=2 bits=2816 rports=1 wports=1 dbits=22 abits=7 words=128\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=384 dwaste=14 bwaste=15616 waste=15616 efficiency=15\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 -1 -1 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15616 efficiency=15\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=384 dwaste=14 bwaste=15616 waste=15616 efficiency=15\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=384 dwaste=14 bwaste=15616 waste=15616 efficiency=15\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=896 dwaste=14 bwaste=17920 waste=17920 efficiency=7\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 -1 -1 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=17920 efficiency=7\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1920 dwaste=5 bwaste=17920 waste=17920 efficiency=5\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 -1 -1 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=17920 efficiency=5\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3968 dwaste=2 bwaste=16128 waste=16128 efficiency=2\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8064 dwaste=0 bwaste=16128 waste=16128 efficiency=1\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16256 dwaste=0 bwaste=16256 waste=16256 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=896 dwaste=14 bwaste=17920 waste=17920 efficiency=7\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1920 dwaste=5 bwaste=17920 waste=17920 efficiency=5\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3968 dwaste=2 bwaste=16128 waste=16128 efficiency=2\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8064 dwaste=0 bwaste=16128 waste=16128 efficiency=1\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16256 dwaste=0 bwaste=16256 waste=16256 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=896 dwaste=14 bwaste=17920 waste=17920 efficiency=7\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1920 dwaste=5 bwaste=17920 waste=17920 efficiency=5\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3968 dwaste=2 bwaste=16128 waste=16128 efficiency=2\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8064 dwaste=0 bwaste=16128 waste=16128 efficiency=1\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16256 dwaste=0 bwaste=16256 waste=16256 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 3 rules:\n    Efficiency for rule 4.2: efficiency=5, cells=3, acells=1\n    Efficiency for rule 4.1: efficiency=7, cells=2, acells=1\n    Efficiency for rule 1.1: efficiency=15, cells=1, acells=1\n    Selected rule 1.1 with efficiency 15.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 -1 -1 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_PDPW16KD cell at grid position <0 0 0>: VexRiscv.dataCache_1_.ways_0_tags.0.0.0\nProcessing top.data_mem_grain0:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain0.0.0.0\nProcessing top.data_mem_grain1:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain1.0.0.0\nProcessing top.data_mem_grain10:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain10.0.0.0\nProcessing top.data_mem_grain11:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain11.0.0.0\nProcessing top.data_mem_grain12:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain12.0.0.0\nProcessing top.data_mem_grain13:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain13.0.0.0\nProcessing top.data_mem_grain14:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain14.0.0.0\nProcessing top.data_mem_grain15:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain15.0.0.0\nProcessing top.data_mem_grain2:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain2.0.0.0\nProcessing top.data_mem_grain3:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain3.0.0.0\nProcessing top.data_mem_grain4:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain4.0.0.0\nProcessing top.data_mem_grain5:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain5.0.0.0\nProcessing top.data_mem_grain6:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain6.0.0.0\nProcessing top.data_mem_grain7:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain7.0.0.0\nProcessing top.data_mem_grain8:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain8.0.0.0\nProcessing top.data_mem_grain9:\n  Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=10 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=1 bwaste=14336 waste=14336 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=4, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=2, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=1, acells=1\n    Efficiency for rule 4.1: efficiency=22, cells=1, acells=1\n    Efficiency for rule 1.1: efficiency=22, cells=1, acells=1\n    Selected rule 4.2 with efficiency 22.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: data_mem_grain9.0.0.0\nProcessing top.mem:\n  Properties: ports=1 bits=327680 rports=1 wports=0 dbits=32 abits=14 words=10240\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=4 bwaste=2048 waste=2048 efficiency=88\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=2048 efficiency=88\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=4 bwaste=2048 waste=2048 efficiency=88\n    Rule #2 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min wports 1' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=4 bwaste=2048 waste=2048 efficiency=88\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_romstyle=\"ebr\" ...' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=4096 waste=4096 efficiency=88\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=4096 efficiency=88\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=8192 waste=8192 efficiency=88\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=8192 efficiency=88\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=83\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=8192 efficiency=83\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=62\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=12288 efficiency=62\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=6144 waste=6144 efficiency=62\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 5):\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=6144 efficiency=62\n      Storing for later selection.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=4096 waste=4096 efficiency=88\n    Rule #5 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min wports 1' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=8192 waste=8192 efficiency=88\n    Rule #5 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min wports 1' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=83\n    Rule #5 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min wports 1' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=62\n    Rule #5 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min wports 1' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=6144 waste=6144 efficiency=62\n    Rule #5 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min wports 1' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=4096 waste=4096 efficiency=88\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_romstyle=\"ebr\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=8192 waste=8192 efficiency=88\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_romstyle=\"ebr\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=83\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_romstyle=\"ebr\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=62\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_romstyle=\"ebr\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=6144 waste=6144 efficiency=62\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_romstyle=\"ebr\" ...' not met.\n  Selecting best of 6 rules:\n    Efficiency for rule 4.5: efficiency=62, cells=32, acells=1\n    Efficiency for rule 4.4: efficiency=62, cells=32, acells=2\n    Efficiency for rule 4.3: efficiency=83, cells=24, acells=3\n    Efficiency for rule 4.2: efficiency=88, cells=20, acells=5\n    Efficiency for rule 4.1: efficiency=88, cells=20, acells=10\n    Efficiency for rule 1.1: efficiency=88, cells=20, acells=20\n    Selected rule 4.2 with efficiency 88.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: mem.0.0.0\n      Creating $__ECP5_DP16KD cell at grid position <0 1 0>: mem.0.1.0\n      Creating $__ECP5_DP16KD cell at grid position <0 2 0>: mem.0.2.0\n      Creating $__ECP5_DP16KD cell at grid position <0 3 0>: mem.0.3.0\n      Creating $__ECP5_DP16KD cell at grid position <0 4 0>: mem.0.4.0\n      Creating $__ECP5_DP16KD cell at grid position <1 0 0>: mem.1.0.0\n      Creating $__ECP5_DP16KD cell at grid position <1 1 0>: mem.1.1.0\n      Creating $__ECP5_DP16KD cell at grid position <1 2 0>: mem.1.2.0\n      Creating $__ECP5_DP16KD cell at grid position <1 3 0>: mem.1.3.0\n      Creating $__ECP5_DP16KD cell at grid position <1 4 0>: mem.1.4.0\n      Creating $__ECP5_DP16KD cell at grid position <2 0 0>: mem.2.0.0\n      Creating $__ECP5_DP16KD cell at grid position <2 1 0>: mem.2.1.0\n      Creating $__ECP5_DP16KD cell at grid position <2 2 0>: mem.2.2.0\n      Creating $__ECP5_DP16KD cell at grid position <2 3 0>: mem.2.3.0\n      Creating $__ECP5_DP16KD cell at grid position <2 4 0>: mem.2.4.0\n      Creating $__ECP5_DP16KD cell at grid position <3 0 0>: mem.3.0.0\n      Creating $__ECP5_DP16KD cell at grid position <3 1 0>: mem.3.1.0\n      Creating $__ECP5_DP16KD cell at grid position <3 2 0>: mem.3.2.0\n      Creating $__ECP5_DP16KD cell at grid position <3 3 0>: mem.3.3.0\n      Creating $__ECP5_DP16KD cell at grid position <3 4 0>: mem.3.4.0\nProcessing top.mem_1:\n  Properties: ports=2 bits=65536 rports=1 wports=1 dbits=32 abits=11 words=2048\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=4 bwaste=2048 waste=2048 efficiency=88\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 8 9 10 11 12 13 14 15 -1 16 17 18 19 20 21 22 23 -1 24 25 26 27 28 29 30 31 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=2048 efficiency=88\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=4 bwaste=2048 waste=2048 efficiency=88\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=4 bwaste=2048 waste=2048 efficiency=88\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=4096 waste=4096 efficiency=88\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 8 9 10 11 12 13 14 15 -1 16 17 18 19 20 21 22 23 -1 24 25 26 27 28 29 30 31 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=4096 efficiency=88\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=8192 waste=8192 efficiency=88\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 8 9 10 11 12 13 14 15 -1 16 17 18 19 20 21 22 23 -1 24 25 26 27 28 29 30 31 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=8192 efficiency=88\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=8192 efficiency=50\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=12288 efficiency=25\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 5):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=4096 waste=4096 efficiency=88\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=8192 waste=8192 efficiency=88\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=4096 waste=4096 efficiency=88\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=0 dwaste=4 bwaste=8192 waste=8192 efficiency=88\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 6 rules:\n    Efficiency for rule 4.5: efficiency=12, cells=32, acells=1\n    Efficiency for rule 4.4: efficiency=25, cells=16, acells=1\n    Efficiency for rule 4.3: efficiency=50, cells=8, acells=1\n    Efficiency for rule 4.2: efficiency=88, cells=4, acells=1\n    Efficiency for rule 4.1: efficiency=88, cells=4, acells=2\n    Efficiency for rule 1.1: efficiency=88, cells=4, acells=4\n    Selected rule 4.2 with efficiency 88.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 8 9 10 11 12 13 14 15 -1 16 17 18 19 20 21 22 23 -1 24 25 26 27 28 29 30 31 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_DP16KD cell at grid position <0 0 0>: mem_1.0.0.0\n      Creating $__ECP5_DP16KD cell at grid position <1 0 0>: mem_1.1.0.0\n      Creating $__ECP5_DP16KD cell at grid position <2 0 0>: mem_1.2.0.0\n      Creating $__ECP5_DP16KD cell at grid position <3 0 0>: mem_1.3.0.0\nProcessing top.mem_2:\n  Properties: ports=1 bits=312 rports=1 wports=0 dbits=8 abits=6 words=39\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=473 dwaste=28 bwaste=18120 waste=18120 efficiency=1\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=473 dwaste=28 bwaste=18120 waste=18120 efficiency=1\n    Rule #2 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min wports 1' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=473 dwaste=28 bwaste=18120 waste=18120 efficiency=1\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_romstyle=\"ebr\" ...' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=985 dwaste=10 bwaste=18120 waste=18120 efficiency=1\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2009 dwaste=1 bwaste=18120 waste=18120 efficiency=1\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4057 dwaste=0 bwaste=16228 waste=16228 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8153 dwaste=0 bwaste=16306 waste=16306 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16345 dwaste=0 bwaste=16345 waste=16345 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=985 dwaste=10 bwaste=18120 waste=18120 efficiency=1\n    Rule #5 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min wports 1' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2009 dwaste=1 bwaste=18120 waste=18120 efficiency=1\n    Rule #5 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min wports 1' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4057 dwaste=0 bwaste=16228 waste=16228 efficiency=0\n    Rule #5 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min wports 1' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8153 dwaste=0 bwaste=16306 waste=16306 efficiency=0\n    Rule #5 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min wports 1' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16345 dwaste=0 bwaste=16345 waste=16345 efficiency=0\n    Rule #5 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min wports 1' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=985 dwaste=10 bwaste=18120 waste=18120 efficiency=1\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_romstyle=\"ebr\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2009 dwaste=1 bwaste=18120 waste=18120 efficiency=1\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_romstyle=\"ebr\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4057 dwaste=0 bwaste=16228 waste=16228 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_romstyle=\"ebr\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8153 dwaste=0 bwaste=16306 waste=16306 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_romstyle=\"ebr\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16345 dwaste=0 bwaste=16345 waste=16345 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_romstyle=\"ebr\" ...' not met.\n  No acceptable bram resources found.\nProcessing top.storage:\n  Properties: ports=2 bits=160 rports=1 wports=1 dbits=10 abits=4 words=16\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=26 bwaste=18272 waste=18272 efficiency=0\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=26 bwaste=18272 waste=18272 efficiency=0\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=26 bwaste=18272 waste=18272 efficiency=0\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=8 bwaste=18272 waste=18272 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=8 bwaste=18416 waste=18416 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=2 bwaste=16352 waste=16352 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=8 bwaste=18272 waste=18272 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=8 bwaste=18416 waste=18416 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=2 bwaste=16352 waste=16352 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=8 bwaste=18272 waste=18272 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=8 bwaste=18416 waste=18416 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=2 bwaste=16352 waste=16352 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  No acceptable bram resources found.\nProcessing top.storage_1:\n  Properties: ports=2 bits=160 rports=1 wports=1 dbits=10 abits=4 words=16\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=26 bwaste=18272 waste=18272 efficiency=0\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=26 bwaste=18272 waste=18272 efficiency=0\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=26 bwaste=18272 waste=18272 efficiency=0\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=8 bwaste=18272 waste=18272 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=8 bwaste=18416 waste=18416 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=2 bwaste=16352 waste=16352 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=8 bwaste=18272 waste=18272 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=8 bwaste=18416 waste=18416 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=2 bwaste=16352 waste=16352 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=8 bwaste=18272 waste=18272 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=8 bwaste=18416 waste=18416 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=2 bwaste=16352 waste=16352 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  No acceptable bram resources found.\nProcessing top.storage_2:\n  Properties: ports=2 bits=200 rports=1 wports=1 dbits=25 abits=3 words=8\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=504 dwaste=11 bwaste=18232 waste=18232 efficiency=1\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=504 dwaste=11 bwaste=18232 waste=18232 efficiency=1\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=504 dwaste=11 bwaste=18232 waste=18232 efficiency=1\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1016 dwaste=11 bwaste=18376 waste=18376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2040 dwaste=2 bwaste=18376 waste=18376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4088 dwaste=3 bwaste=16376 waste=16376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8184 dwaste=1 bwaste=16376 waste=16376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16376 dwaste=0 bwaste=16376 waste=16376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1016 dwaste=11 bwaste=18376 waste=18376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2040 dwaste=2 bwaste=18376 waste=18376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4088 dwaste=3 bwaste=16376 waste=16376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8184 dwaste=1 bwaste=16376 waste=16376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16376 dwaste=0 bwaste=16376 waste=16376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1016 dwaste=11 bwaste=18376 waste=18376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2040 dwaste=2 bwaste=18376 waste=18376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4088 dwaste=3 bwaste=16376 waste=16376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8184 dwaste=1 bwaste=16376 waste=16376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16376 dwaste=0 bwaste=16376 waste=16376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  No acceptable bram resources found.\nProcessing top.storage_3:\n  Properties: ports=2 bits=200 rports=1 wports=1 dbits=25 abits=3 words=8\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=504 dwaste=11 bwaste=18232 waste=18232 efficiency=1\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=504 dwaste=11 bwaste=18232 waste=18232 efficiency=1\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=504 dwaste=11 bwaste=18232 waste=18232 efficiency=1\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1016 dwaste=11 bwaste=18376 waste=18376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2040 dwaste=2 bwaste=18376 waste=18376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4088 dwaste=3 bwaste=16376 waste=16376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8184 dwaste=1 bwaste=16376 waste=16376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16376 dwaste=0 bwaste=16376 waste=16376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1016 dwaste=11 bwaste=18376 waste=18376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2040 dwaste=2 bwaste=18376 waste=18376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4088 dwaste=3 bwaste=16376 waste=16376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8184 dwaste=1 bwaste=16376 waste=16376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16376 dwaste=0 bwaste=16376 waste=16376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1016 dwaste=11 bwaste=18376 waste=18376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2040 dwaste=2 bwaste=18376 waste=18376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4088 dwaste=3 bwaste=16376 waste=16376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8184 dwaste=1 bwaste=16376 waste=16376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16376 dwaste=0 bwaste=16376 waste=16376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  No acceptable bram resources found.\nProcessing top.storage_4:\n  Properties: ports=2 bits=200 rports=1 wports=1 dbits=25 abits=3 words=8\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=504 dwaste=11 bwaste=18232 waste=18232 efficiency=1\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=504 dwaste=11 bwaste=18232 waste=18232 efficiency=1\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=504 dwaste=11 bwaste=18232 waste=18232 efficiency=1\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1016 dwaste=11 bwaste=18376 waste=18376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2040 dwaste=2 bwaste=18376 waste=18376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4088 dwaste=3 bwaste=16376 waste=16376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8184 dwaste=1 bwaste=16376 waste=16376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16376 dwaste=0 bwaste=16376 waste=16376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1016 dwaste=11 bwaste=18376 waste=18376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2040 dwaste=2 bwaste=18376 waste=18376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4088 dwaste=3 bwaste=16376 waste=16376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8184 dwaste=1 bwaste=16376 waste=16376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16376 dwaste=0 bwaste=16376 waste=16376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1016 dwaste=11 bwaste=18376 waste=18376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2040 dwaste=2 bwaste=18376 waste=18376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4088 dwaste=3 bwaste=16376 waste=16376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8184 dwaste=1 bwaste=16376 waste=16376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16376 dwaste=0 bwaste=16376 waste=16376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  No acceptable bram resources found.\nProcessing top.storage_5:\n  Properties: ports=2 bits=200 rports=1 wports=1 dbits=25 abits=3 words=8\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=504 dwaste=11 bwaste=18232 waste=18232 efficiency=1\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=504 dwaste=11 bwaste=18232 waste=18232 efficiency=1\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=504 dwaste=11 bwaste=18232 waste=18232 efficiency=1\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1016 dwaste=11 bwaste=18376 waste=18376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2040 dwaste=2 bwaste=18376 waste=18376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4088 dwaste=3 bwaste=16376 waste=16376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8184 dwaste=1 bwaste=16376 waste=16376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16376 dwaste=0 bwaste=16376 waste=16376 efficiency=0\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1016 dwaste=11 bwaste=18376 waste=18376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2040 dwaste=2 bwaste=18376 waste=18376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4088 dwaste=3 bwaste=16376 waste=16376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8184 dwaste=1 bwaste=16376 waste=16376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16376 dwaste=0 bwaste=16376 waste=16376 efficiency=0\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1016 dwaste=11 bwaste=18376 waste=18376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=2040 dwaste=2 bwaste=18376 waste=18376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=4088 dwaste=3 bwaste=16376 waste=16376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=8184 dwaste=1 bwaste=16376 waste=16376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=16376 dwaste=0 bwaste=16376 waste=16376 efficiency=0\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  No acceptable bram resources found.\nProcessing top.tag_mem:\n  Properties: ports=2 bits=12288 rports=1 wports=1 dbits=24 abits=9 words=512\n  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=12 bwaste=6144 waste=6144 efficiency=66\n    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=6144 efficiency=66\n      Storing for later selection.\n  Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=12 bwaste=6144 waste=6144 efficiency=66\n    Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):\n    Bram geometry: abits=9 dbits=36 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=12 bwaste=6144 waste=6144 efficiency=66\n    Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=12 bwaste=15360 waste=15360 efficiency=33\n    Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=33\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=3 bwaste=15360 waste=15360 efficiency=22\n    Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 2):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=22\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 3):\n      Shuffle bit order to accommodate enable buckets of size 4..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=14336 efficiency=12\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.\n    Mapping to bram type $__ECP5_DP16KD (variant 4):\n      Shuffle bit order to accommodate enable buckets of size 2..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Updated properties: dups=1 waste=15360 efficiency=6\n      Storing for later selection.\n  Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=12 bwaste=15360 waste=15360 efficiency=33\n    Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=3 bwaste=15360 waste=15360 efficiency=22\n    Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle=\"block_ram\" ...' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):\n    Bram geometry: abits=10 dbits=18 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=512 dwaste=12 bwaste=15360 waste=15360 efficiency=33\n    Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):\n    Bram geometry: abits=11 dbits=9 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=1536 dwaste=3 bwaste=15360 waste=15360 efficiency=22\n    Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):\n    Bram geometry: abits=12 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=3584 dwaste=0 bwaste=14336 waste=14336 efficiency=12\n    Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):\n    Bram geometry: abits=13 dbits=2 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=7680 dwaste=0 bwaste=15360 waste=15360 efficiency=6\n    Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.\n  Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):\n    Bram geometry: abits=14 dbits=1 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__ECP5_DP16KD: awaste=15872 dwaste=0 bwaste=15872 waste=15872 efficiency=3\n    Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.\n  Selecting best of 5 rules:\n    Efficiency for rule 4.4: efficiency=6, cells=12, acells=1\n    Efficiency for rule 4.3: efficiency=12, cells=6, acells=1\n    Efficiency for rule 4.2: efficiency=22, cells=3, acells=1\n    Efficiency for rule 4.1: efficiency=33, cells=2, acells=1\n    Efficiency for rule 1.1: efficiency=66, cells=1, acells=1\n    Selected rule 1.1 with efficiency 66.\n    Mapping to bram type $__ECP5_PDPW16KD (variant 1):\n      Shuffle bit order to accommodate enable buckets of size 9..\n      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 -1 -1 -1\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.1.\n      Creating $__ECP5_PDPW16KD cell at grid position <0 0 0>: tag_mem.0.0.0\n        Adding extra logic for transparent port B1.1.\n\n4.28. Executing TECHMAP pass (map to technology primitives).\n\n4.28.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/brams_map.v\nParsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/brams_map.v' to AST representation.\nGenerating RTLIL representation for module `\\$__ECP5_DP16KD'.\nGenerating RTLIL representation for module `\\$__ECP5_PDPW16KD'.\nSuccessfully finished Verilog frontend.\n\n4.28.2. Continuing TECHMAP pass.\nUsing template $paramod$66f7b7a9dd3f499ead7b66dfbda87042c3f31926\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$7f392415bd247690db0a4876148cbdaca096adcc\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$69a26f7f448eb95fc0c630cd7d82fffadcc94e8f\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$984bab16f115495353a693bd74039aafda73082b\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$2c48ff25feb7c3fcf8816c75cd2e17468568357c\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$7b0132d0f2f8fc3e347dbb8225293c5a5fd24378\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$d270131e564ae16d5164f2d7409e0409e7bfcbc9\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$485c88400d10b0f3643f823407982828a2024fad\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod\\$__ECP5_PDPW16KD\\CLKPOL2=1\\CLKPOL3=1 for cells of type $__ECP5_PDPW16KD.\nUsing template $paramod$903d550286893f2a2052112d826717bae0cfddd6\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$bdab9a4289d40ebe1d36b23ee9c37342344d5f9d\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$53ee28ef64dad4154760d925d330877195073d27\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$65796086bbb28e4fc94fd5158e5ad83744ede8d4\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$20e509a3c17e2cb7edaa2497a0ec8bb2daefb1c0\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$e5258842f9b7ed66e96cfd1568239e8f598c6bfe\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$2b5dbca6cf9d8c28f27aa7cecb1218d9e9fe4bc6\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$094ab2ece720e830030ef932be0bd0a7cc36a56f\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$6155bd6e214cdd2ad90b45a4ae9946bae0900e64\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$76fe95d9135a02f68dd3d5fcb8e02052f6a88689\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$571f5959f24a1d6cbe7e90d33b0a7ea2422f4a8c\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nUsing template $paramod$c97c0060ae32aa3cbc9f8d33231fd7f04341b337\\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.\nNo more expansions possible.\n<suppressed ~486 debug messages>\n\n4.29. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\nProcessing top.VexRiscv.RegFilePlugin_regFile:\n  Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32\n  Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):\n    Bram geometry: abits=4 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100\n    Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.\n    Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.1.\n      Read port #1 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Failed to map read port #1.\n      Growing more read ports by duplicating bram cells.\n      Read port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.1.\n      Read port #1 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port A1.2.\n      Updated properties: dups=2 waste=0 efficiency=50\n      Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: VexRiscv.RegFilePlugin_regFile.0.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 1>: VexRiscv.RegFilePlugin_regFile.0.0.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 0>: VexRiscv.RegFilePlugin_regFile.0.1.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 1>: VexRiscv.RegFilePlugin_regFile.0.1.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: VexRiscv.RegFilePlugin_regFile.1.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 1>: VexRiscv.RegFilePlugin_regFile.1.0.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 0>: VexRiscv.RegFilePlugin_regFile.1.1.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 1>: VexRiscv.RegFilePlugin_regFile.1.1.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: VexRiscv.RegFilePlugin_regFile.2.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 1>: VexRiscv.RegFilePlugin_regFile.2.0.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 0>: VexRiscv.RegFilePlugin_regFile.2.1.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 1>: VexRiscv.RegFilePlugin_regFile.2.1.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 0>: VexRiscv.RegFilePlugin_regFile.3.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 1>: VexRiscv.RegFilePlugin_regFile.3.0.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 0>: VexRiscv.RegFilePlugin_regFile.3.1.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 1>: VexRiscv.RegFilePlugin_regFile.3.1.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 0>: VexRiscv.RegFilePlugin_regFile.4.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 1>: VexRiscv.RegFilePlugin_regFile.4.0.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 0>: VexRiscv.RegFilePlugin_regFile.4.1.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 1>: VexRiscv.RegFilePlugin_regFile.4.1.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 0>: VexRiscv.RegFilePlugin_regFile.5.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 1>: VexRiscv.RegFilePlugin_regFile.5.0.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 0>: VexRiscv.RegFilePlugin_regFile.5.1.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 1>: VexRiscv.RegFilePlugin_regFile.5.1.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 0>: VexRiscv.RegFilePlugin_regFile.6.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 1>: VexRiscv.RegFilePlugin_regFile.6.0.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 0>: VexRiscv.RegFilePlugin_regFile.6.1.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 1>: VexRiscv.RegFilePlugin_regFile.6.1.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 0>: VexRiscv.RegFilePlugin_regFile.7.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 1>: VexRiscv.RegFilePlugin_regFile.7.0.1\n      Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 0>: VexRiscv.RegFilePlugin_regFile.7.1.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 1>: VexRiscv.RegFilePlugin_regFile.7.1.1\nProcessing top.mem_2:\n  Properties: ports=1 bits=312 rports=1 wports=0 dbits=8 abits=6 words=39\n  Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):\n    Bram geometry: abits=4 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__TRELLIS_DPR16X4: awaste=9 dwaste=0 bwaste=36 waste=36 efficiency=81\n    Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) rejected: requirement 'min wports 1' not met.\n  No acceptable bram resources found.\nProcessing top.storage:\n  Properties: ports=2 bits=160 rports=1 wports=1 dbits=10 abits=4 words=16\n  Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):\n    Bram geometry: abits=4 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=2 bwaste=32 waste=32 efficiency=83\n    Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.\n    Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.\n      Read port #0 is in clock domain !~async~.\n        Mapped to bram port A1.1.\n      Updated properties: dups=1 waste=32 efficiency=83\n      Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: storage.0.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: storage.1.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: storage.2.0.0\nProcessing top.storage_1:\n  Properties: ports=2 bits=160 rports=1 wports=1 dbits=10 abits=4 words=16\n  Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):\n    Bram geometry: abits=4 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=2 bwaste=32 waste=32 efficiency=83\n    Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.\n    Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.\n      Read port #0 is in clock domain !~async~.\n        Mapped to bram port A1.1.\n      Updated properties: dups=1 waste=32 efficiency=83\n      Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: storage_1.0.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: storage_1.1.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: storage_1.2.0.0\nProcessing top.storage_2:\n  Properties: ports=2 bits=200 rports=1 wports=1 dbits=25 abits=3 words=8\n  Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):\n    Bram geometry: abits=4 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__TRELLIS_DPR16X4: awaste=8 dwaste=3 bwaste=56 waste=56 efficiency=44\n    Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.\n    Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.\n      Read port #0 is in clock domain !~async~.\n        Mapped to bram port A1.1.\n      Updated properties: dups=1 waste=56 efficiency=44\n      Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: storage_2.0.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: storage_2.1.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: storage_2.2.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 0>: storage_2.3.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 0>: storage_2.4.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 0>: storage_2.5.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 0>: storage_2.6.0.0\nProcessing top.storage_3:\n  Properties: ports=2 bits=200 rports=1 wports=1 dbits=25 abits=3 words=8\n  Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):\n    Bram geometry: abits=4 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__TRELLIS_DPR16X4: awaste=8 dwaste=3 bwaste=56 waste=56 efficiency=44\n    Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.\n    Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.\n      Read port #0 is in clock domain !~async~.\n        Mapped to bram port A1.1.\n      Updated properties: dups=1 waste=56 efficiency=44\n      Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: storage_3.0.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: storage_3.1.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: storage_3.2.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 0>: storage_3.3.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 0>: storage_3.4.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 0>: storage_3.5.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 0>: storage_3.6.0.0\nProcessing top.storage_4:\n  Properties: ports=2 bits=200 rports=1 wports=1 dbits=25 abits=3 words=8\n  Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):\n    Bram geometry: abits=4 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__TRELLIS_DPR16X4: awaste=8 dwaste=3 bwaste=56 waste=56 efficiency=44\n    Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.\n    Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.\n      Read port #0 is in clock domain !~async~.\n        Mapped to bram port A1.1.\n      Updated properties: dups=1 waste=56 efficiency=44\n      Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: storage_4.0.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: storage_4.1.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: storage_4.2.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 0>: storage_4.3.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 0>: storage_4.4.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 0>: storage_4.5.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 0>: storage_4.6.0.0\nProcessing top.storage_5:\n  Properties: ports=2 bits=200 rports=1 wports=1 dbits=25 abits=3 words=8\n  Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):\n    Bram geometry: abits=4 dbits=4 wports=0 rports=0\n    Estimated number of duplicates for more read ports: dups=1\n    Metrics for $__TRELLIS_DPR16X4: awaste=8 dwaste=3 bwaste=56 waste=56 efficiency=44\n    Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.\n    Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):\n      Write port #0 is in clock domain \\VexRiscv.IBusCachedPlugin_cache.clk.\n        Mapped to bram port B1.\n      Read port #0 is in clock domain !~async~.\n        Mapped to bram port A1.1.\n      Updated properties: dups=1 waste=56 efficiency=44\n      Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: storage_5.0.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: storage_5.1.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: storage_5.2.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 0>: storage_5.3.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 0>: storage_5.4.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 0>: storage_5.5.0.0\n      Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 0>: storage_5.6.0.0\n\n4.30. Executing TECHMAP pass (map to technology primitives).\n\n4.30.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/lutrams_map.v\nParsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/lutrams_map.v' to AST representation.\nGenerating RTLIL representation for module `\\$__TRELLIS_DPR16X4'.\nSuccessfully finished Verilog frontend.\n\n4.30.2. Continuing TECHMAP pass.\nUsing template $paramod\\$__TRELLIS_DPR16X4\\CLKPOL2=1 for cells of type $__TRELLIS_DPR16X4.\nNo more expansions possible.\n<suppressed ~80 debug messages>\n\n4.31. Executing OPT pass (performing simple optimizations).\n\n4.31.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~1304 debug messages>\n\n4.31.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\n<suppressed ~561 debug messages>\nRemoved a total of 187 cells.\n\n4.31.3. Executing OPT_DFF pass (perform DFF optimizations).\nAdding SRST signal on $auto$memory_bram.cc:991:replace_memory$14865 ($dff) from module top (D = $auto$memory_bram.cc:886:replace_memory$14858, Q = $auto$memory_bram.cc:990:replace_memory$14864, rval = 4'0000).\n\n4.31.4. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 12 unused cells and 1577 unused wires.\n<suppressed ~26 debug messages>\n\n4.31.5. Rerunning OPT passes. (Removed registers in this run.)\n\n4.31.6. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~12 debug messages>\n\n4.31.7. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.31.8. Executing OPT_DFF pass (perform DFF optimizations).\nSetting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$15792 ($sdff) from module top.\nSetting constant 0-bit at position 19 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 20 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 21 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 22 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 24 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 25 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 26 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 27 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 28 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 29 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 30 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 31 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 32 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 33 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 34 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\nSetting constant 0-bit at position 35 on $auto$memory_bram.cc:884:replace_memory$14857 ($dff) from module top.\n\n4.31.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 0 unused cells and 2 unused wires.\n<suppressed ~1 debug messages>\n\n4.31.10. Rerunning OPT passes. (Removed registers in this run.)\n\n4.31.11. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.31.12. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.31.13. Executing OPT_DFF pass (perform DFF optimizations).\nRemoving never-active SRST on $auto$opt_dff.cc:702:run$15792 ($sdff) from module top.\n\n4.31.14. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.31.15. Rerunning OPT passes. (Removed registers in this run.)\n\n4.31.16. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.31.17. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.31.18. Executing OPT_DFF pass (perform DFF optimizations).\n\n4.31.19. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.31.20. Finished fast OPT passes.\n\n4.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\nMapping memory \\mem_2 in module \\top:\n  created 39 $dff cells and 0 static cells of width 8.\nExtracted addr FF from read port 0 of top.mem_2: mem_2$rdreg[0]\n  read interface: 1 $dff and 63 $mux cells.\n  write interface: 0 write mux blocks.\n\n4.33. Executing OPT pass (performing simple optimizations).\n\n4.33.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~47 debug messages>\n\n4.33.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~502 debug messages>\n\n4.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\n    New input vector for $reduce_or cell $auto$opt_dff.cc:277:combine_resets$12997: { $procmux$11306_CMP $procmux$11301_CMP $procmux$11293_CMP \\sys_rst }\n    New input vector for $reduce_or cell $auto$opt_dff.cc:277:combine_resets$12944: { $procmux$11085_CMP $procmux$11080_CMP $procmux$11072_CMP \\sys_rst }\n    New input vector for $reduce_or cell $auto$opt_dff.cc:277:combine_resets$12891: { $procmux$10864_CMP $procmux$10859_CMP $procmux$10851_CMP \\sys_rst }\n    New input vector for $reduce_or cell $auto$opt_dff.cc:277:combine_resets$12838: { $procmux$10643_CMP $procmux$10638_CMP $procmux$10630_CMP \\sys_rst }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$6281:\n      Old ports: A=2'00, B=2'11, Y=$auto$wreduce.cc:454:run$14091 [1:0]\n      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$14091 [0]\n      New connections: $auto$wreduce.cc:454:run$14091 [1] = $auto$wreduce.cc:454:run$14091 [0]\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$6290:\n      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:454:run$14092 [1:0]\n      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$14092 [0]\n      New connections: $auto$wreduce.cc:454:run$14092 [1] = $auto$wreduce.cc:454:run$14092 [0]\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$6292:\n      Old ports: A={ 1'0 $auto$wreduce.cc:454:run$14092 [1:0] }, B=3'001, Y=$flatten\\VexRiscv.$procmux$6292_Y\n      New ports: A=$auto$wreduce.cc:454:run$14092 [1:0], B=2'01, Y=$flatten\\VexRiscv.$procmux$6292_Y [1:0]\n      New connections: $flatten\\VexRiscv.$procmux$6292_Y [2] = 1'0\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6648: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5035_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP $flatten\\VexRiscv.$procmux$6649_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6666: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$6675_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6682: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5929_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$4932_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5848_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6701: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5929_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$4932_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5848_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6720: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6755: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6769: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $auto$opt_reduce.cc:134:opt_mux$12357 $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP $auto$opt_reduce.cc:134:opt_mux$12361 }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6789: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $auto$opt_reduce.cc:134:opt_mux$12365 $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6806: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5035_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP $flatten\\VexRiscv.$procmux$6649_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6824: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5929_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$6675_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6841: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5929_CMP $flatten\\VexRiscv.$procmux$5035_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$4932_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5848_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP $flatten\\VexRiscv.$procmux$6649_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6862: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6878: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $auto$opt_reduce.cc:134:opt_mux$12365 $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6920: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6936: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $auto$opt_reduce.cc:134:opt_mux$12365 $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6952: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $auto$opt_reduce.cc:134:opt_mux$12365 $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $auto$opt_reduce.cc:134:opt_mux$12357 $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP $auto$opt_reduce.cc:134:opt_mux$12361 }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6974: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $auto$opt_reduce.cc:134:opt_mux$12365 $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5662_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    New ctrl vector for $pmux cell $flatten\\VexRiscv.$procmux$6992: { $flatten\\VexRiscv.$procmux$5838_CMP $flatten\\VexRiscv.$procmux$5821_CMP $flatten\\VexRiscv.$procmux$5109_CMP $flatten\\VexRiscv.$procmux$5005_CMP $flatten\\VexRiscv.$procmux$6656_CMP $flatten\\VexRiscv.$procmux$5064_CMP $flatten\\VexRiscv.$procmux$5093_CMP $flatten\\VexRiscv.$procmux$5017_CMP $flatten\\VexRiscv.$procmux$5057_CMP }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7012:\n      Old ports: A=4'0010, B={ 2'10 $auto$wreduce.cc:454:run$14086 [1:0] }, Y=\\VexRiscv.CsrPlugin_selfException_payload_code\n      New ports: A=3'010, B={ 1'1 $auto$wreduce.cc:454:run$14086 [1:0] }, Y={ \\VexRiscv.CsrPlugin_selfException_payload_code [3] \\VexRiscv.CsrPlugin_selfException_payload_code [1:0] }\n      New connections: \\VexRiscv.CsrPlugin_selfException_payload_code [2] = 1'0\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7348:\n      Old ports: A=2'11, B=2'01, Y=$flatten\\VexRiscv.$13\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.$13\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1]\n      New connections: $flatten\\VexRiscv.$13\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7355:\n      Old ports: A=2'11, B=2'01, Y=$flatten\\VexRiscv.$12\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.$12\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1]\n      New connections: $flatten\\VexRiscv.$12\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7363:\n      Old ports: A=2'11, B=2'01, Y=$flatten\\VexRiscv.$11\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.$11\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1]\n      New connections: $flatten\\VexRiscv.$11\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7372:\n      Old ports: A=2'11, B=2'01, Y=$flatten\\VexRiscv.$10\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.$10\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1]\n      New connections: $flatten\\VexRiscv.$10\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7382:\n      Old ports: A=2'11, B=2'01, Y=$flatten\\VexRiscv.$9\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.$9\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1]\n      New connections: $flatten\\VexRiscv.$9\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7393:\n      Old ports: A=2'11, B=2'01, Y=$flatten\\VexRiscv.$8\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.$8\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1]\n      New connections: $flatten\\VexRiscv.$8\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7405:\n      Old ports: A=2'11, B=2'01, Y=$flatten\\VexRiscv.$7\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.$7\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1]\n      New connections: $flatten\\VexRiscv.$7\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7418:\n      Old ports: A=2'11, B=2'01, Y=$flatten\\VexRiscv.$6\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.$6\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1]\n      New connections: $flatten\\VexRiscv.$6\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7432:\n      Old ports: A=2'11, B=2'01, Y=$flatten\\VexRiscv.$5\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.$5\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1]\n      New connections: $flatten\\VexRiscv.$5\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7447:\n      Old ports: A=2'11, B=2'01, Y=$flatten\\VexRiscv.$4\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.$4\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1]\n      New connections: $flatten\\VexRiscv.$4\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7463:\n      Old ports: A=2'11, B=2'01, Y=$flatten\\VexRiscv.$3\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.$3\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1]\n      New connections: $flatten\\VexRiscv.$3\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7480:\n      Old ports: A=2'11, B=2'01, Y=$flatten\\VexRiscv.$2\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.$2\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1]\n      New connections: $flatten\\VexRiscv.$2\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7502:\n      Old ports: A={ \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5969$3224_Y [19:0] }, B=4, Y=$flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0]\n      New ports: A={ \\VexRiscv.decode_to_execute_INSTRUCTION [31] $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5969$3224_Y [19:0] }, B=21'000000000000000000100, Y=$flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20:0]\n      New connections: $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [31:21] = { $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20] }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7679:\n      Old ports: A={ \\VexRiscv.MmuPlugin_satp_ppn \\VexRiscv.MmuPlugin_shared_vpn_1 2'00 }, B={ \\VexRiscv.MmuPlugin_shared_pteBuffer_PPN1 [9:0] \\VexRiscv.MmuPlugin_shared_pteBuffer_PPN0 \\VexRiscv.MmuPlugin_shared_vpn_0 2'00 }, Y=\\VexRiscv.MmuPlugin_dBusAccess_cmd_payload_address\n      New ports: A={ \\VexRiscv.MmuPlugin_satp_ppn \\VexRiscv.MmuPlugin_shared_vpn_1 }, B={ \\VexRiscv.MmuPlugin_shared_pteBuffer_PPN1 [9:0] \\VexRiscv.MmuPlugin_shared_pteBuffer_PPN0 \\VexRiscv.MmuPlugin_shared_vpn_0 }, Y=\\VexRiscv.MmuPlugin_dBusAccess_cmd_payload_address [31:2]\n      New connections: \\VexRiscv.MmuPlugin_dBusAccess_cmd_payload_address [1:0] = 2'00\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7702:\n      Old ports: A={ \\VexRiscv.IBusCachedPlugin_fetchPc_pcReg [31:2] 2'00 }, B={ \\VexRiscv.MmuPlugin_ports_1_cacheLine_physicalAddress_1 $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5394$3102_Y \\VexRiscv.IBusCachedPlugin_fetchPc_pcReg [11:2] 2'00 }, Y=\\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuBus_rsp_physicalAddress\n      New ports: A=\\VexRiscv.IBusCachedPlugin_fetchPc_pcReg [31:12], B={ \\VexRiscv.MmuPlugin_ports_1_cacheLine_physicalAddress_1 $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5394$3102_Y }, Y=\\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuBus_rsp_physicalAddress [31:12]\n      New connections: \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_mmuBus_rsp_physicalAddress [11:0] = { \\VexRiscv.IBusCachedPlugin_fetchPc_pcReg [11:2] 2'00 }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7738:\n      Old ports: A=\\VexRiscv.execute_to_memory_REGFILE_WRITE_DATA, B={ \\VexRiscv.MmuPlugin_ports_0_cacheLine_physicalAddress_1 $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5297$3041_Y \\VexRiscv.execute_to_memory_REGFILE_WRITE_DATA [11:0] }, Y={ \\VexRiscv.DBusCachedPlugin_mmuBus_rsp_physicalAddress [31:28] \\VexRiscv.dataCache_1_.io_cpu_memory_mmuBus_rsp_physicalAddress [27:0] }\n      New ports: A=\\VexRiscv.execute_to_memory_REGFILE_WRITE_DATA [31:12], B={ \\VexRiscv.MmuPlugin_ports_0_cacheLine_physicalAddress_1 $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5297$3041_Y }, Y={ \\VexRiscv.DBusCachedPlugin_mmuBus_rsp_physicalAddress [31:28] \\VexRiscv.dataCache_1_.io_cpu_memory_mmuBus_rsp_physicalAddress [27:12] }\n      New connections: \\VexRiscv.dataCache_1_.io_cpu_memory_mmuBus_rsp_physicalAddress [11:0] = \\VexRiscv.execute_to_memory_REGFILE_WRITE_DATA [11:0]\n    Consolidated identical input bits for $pmux cell $flatten\\VexRiscv.$procmux$7792:\n      Old ports: A={ \\VexRiscv.dataCache_1__io_cpu_writeBack_data [31:16] \\VexRiscv._zz_151_ [15:8] \\VexRiscv._zz_149_ [7:0] }, B={ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_149_ [7:0] \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_151_ [15:8] \\VexRiscv._zz_149_ [7:0] }, Y=\\VexRiscv.writeBack_DBusCachedPlugin_rspFormated\n      New ports: A={ \\VexRiscv.dataCache_1__io_cpu_writeBack_data [31:16] \\VexRiscv._zz_151_ [15:8] }, B={ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_148_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_150_ \\VexRiscv._zz_151_ [15:8] }, Y=\\VexRiscv.writeBack_DBusCachedPlugin_rspFormated [31:8]\n      New connections: \\VexRiscv.writeBack_DBusCachedPlugin_rspFormated [7:0] = \\VexRiscv._zz_149_ [7:0]\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7812:\n      Old ports: A={ 1'1 \\VexRiscv._zz_360_ [1:0] }, B={ 1'1 \\VexRiscv._zz_361_ [1:0] }, Y=$auto$wreduce.cc:454:run$14087 [2:0]\n      New ports: A=\\VexRiscv._zz_360_ [1:0], B=\\VexRiscv._zz_361_ [1:0], Y=$auto$wreduce.cc:454:run$14087 [1:0]\n      New connections: $auto$wreduce.cc:454:run$14087 [2] = 1'1\n    Consolidated identical input bits for $pmux cell $flatten\\VexRiscv.$procmux$7913:\n      Old ports: A=\\VexRiscv.decode_to_execute_RS2, B={ \\VexRiscv.decode_to_execute_RS2 [7:0] \\VexRiscv.decode_to_execute_RS2 [7:0] \\VexRiscv.decode_to_execute_RS2 [7:0] \\VexRiscv.decode_to_execute_RS2 [7:0] \\VexRiscv.decode_to_execute_RS2 [15:0] \\VexRiscv.decode_to_execute_RS2 [15:0] }, Y=\\VexRiscv._zz_147_\n      New ports: A=\\VexRiscv.decode_to_execute_RS2 [31:8], B={ \\VexRiscv.decode_to_execute_RS2 [7:0] \\VexRiscv.decode_to_execute_RS2 [7:0] \\VexRiscv.decode_to_execute_RS2 [7:0] \\VexRiscv.decode_to_execute_RS2 [15:0] \\VexRiscv.decode_to_execute_RS2 [15:8] }, Y=\\VexRiscv._zz_147_ [31:8]\n      New connections: \\VexRiscv._zz_147_ [7:0] = \\VexRiscv.decode_to_execute_RS2 [7:0]\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7953:\n      Old ports: A=4'1100, B=4'0001, Y=\\VexRiscv.IBusCachedPlugin_decodeExceptionPort_payload_code\n      New ports: A=2'10, B=2'01, Y={ \\VexRiscv.IBusCachedPlugin_decodeExceptionPort_payload_code [2] \\VexRiscv.IBusCachedPlugin_decodeExceptionPort_payload_code [0] }\n      New connections: { \\VexRiscv.IBusCachedPlugin_decodeExceptionPort_payload_code [3] \\VexRiscv.IBusCachedPlugin_decodeExceptionPort_payload_code [1] } = { \\VexRiscv.IBusCachedPlugin_decodeExceptionPort_payload_code [2] 1'0 }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2834$2592:\n      Old ports: A=2'01, B=2'11, Y=\\VexRiscv._zz_360_ [1:0]\n      New ports: A=1'0, B=1'1, Y=\\VexRiscv._zz_360_ [1]\n      New connections: \\VexRiscv._zz_360_ [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:2835$2593:\n      Old ports: A=2'00, B=2'10, Y=\\VexRiscv._zz_361_ [1:0]\n      New ports: A=1'0, B=1'1, Y=\\VexRiscv._zz_361_ [1]\n      New connections: \\VexRiscv._zz_361_ [0] = 1'0\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4877$2929:\n      Old ports: A={ \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [7] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [30:25] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [11:8] 1'0 }, B={ \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [19:12] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [20] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [30:21] 1'0 }, Y={ $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4877$2929_Y [19:2] \\VexRiscv.IBusCachedPlugin_predictionJumpInterface_payload [1:0] }\n      New ports: A={ \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [7] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [11:8] }, B={ \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [19:12] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [20] \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [24:21] }, Y={ $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4877$2929_Y [19:11] $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4877$2929_Y [4:2] \\VexRiscv.IBusCachedPlugin_predictionJumpInterface_payload [1] }\n      New connections: { $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4877$2929_Y [10:5] \\VexRiscv.IBusCachedPlugin_predictionJumpInterface_payload [0] } = { \\VexRiscv.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [30:25] 1'0 }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5969$3224:\n      Old ports: A={ \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [7] \\VexRiscv.decode_to_execute_INSTRUCTION [30:25] \\VexRiscv.decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \\VexRiscv.decode_to_execute_INSTRUCTION [19:12] \\VexRiscv.decode_to_execute_INSTRUCTION [20] \\VexRiscv.decode_to_execute_INSTRUCTION [30:21] 1'0 }, Y=$flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5969$3224_Y [19:0]\n      New ports: A={ \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [7] \\VexRiscv.decode_to_execute_INSTRUCTION [11:8] }, B={ \\VexRiscv.decode_to_execute_INSTRUCTION [19:12] \\VexRiscv.decode_to_execute_INSTRUCTION [20] \\VexRiscv.decode_to_execute_INSTRUCTION [24:21] }, Y={ $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5969$3224_Y [19:11] $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5969$3224_Y [4:1] }\n      New connections: { $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5969$3224_Y [10:5] $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5969$3224_Y [0] } = { \\VexRiscv.decode_to_execute_INSTRUCTION [30:25] 1'0 }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6693$3414:\n      Old ports: A={ \\VexRiscv._zz_141_ [4:2] 2'00 }, B={ \\VexRiscv._zz_232_ 2'00 }, Y={ \\main_soclinux_cpu_dbus_adr [2:0] $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6693$3414_Y [1:0] }\n      New ports: A=\\VexRiscv._zz_141_ [4:2], B=\\VexRiscv._zz_232_, Y=\\main_soclinux_cpu_dbus_adr [2:0]\n      New connections: $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:6693$3414_Y [1:0] = 2'00\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4191:\n      Old ports: A=3'111, B=3'000, Y=$flatten\\VexRiscv.\\dataCache_1_.$3\\io_mem_cmd_payload_length[2:0]\n      New ports: A=1'1, B=1'0, Y=$flatten\\VexRiscv.\\dataCache_1_.$3\\io_mem_cmd_payload_length[2:0] [0]\n      New connections: $flatten\\VexRiscv.\\dataCache_1_.$3\\io_mem_cmd_payload_length[2:0] [2:1] = { $flatten\\VexRiscv.\\dataCache_1_.$3\\io_mem_cmd_payload_length[2:0] [0] $flatten\\VexRiscv.\\dataCache_1_.$3\\io_mem_cmd_payload_length[2:0] [0] }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4209:\n      Old ports: A=5'00000, B={ \\VexRiscv.dataCache_1_.stageB_mmuRsp_physicalAddress [4:2] 2'00 }, Y=$flatten\\VexRiscv.\\dataCache_1_.$3\\io_mem_cmd_payload_address[31:0] [4:0]\n      New ports: A=3'000, B=\\VexRiscv.dataCache_1_.stageB_mmuRsp_physicalAddress [4:2], Y=$flatten\\VexRiscv.\\dataCache_1_.$3\\io_mem_cmd_payload_address[31:0] [4:2]\n      New connections: $flatten\\VexRiscv.\\dataCache_1_.$3\\io_mem_cmd_payload_address[31:0] [1:0] = 2'00\n    Consolidated identical input bits for $pmux cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4511:\n      Old ports: A=4'1111, B=8'00010011, Y=\\VexRiscv.dataCache_1_._zz_6_\n      New ports: A=2'11, B=4'0001, Y=\\VexRiscv.dataCache_1_._zz_6_ [2:1]\n      New connections: { \\VexRiscv.dataCache_1_._zz_6_ [3] \\VexRiscv.dataCache_1_._zz_6_ [0] } = { \\VexRiscv.dataCache_1_._zz_6_ [2] 1'1 }\n    Consolidated identical input bits for $mux cell $procmux$10510:\n      Old ports: A=2'00, B=2'11, Y=\\main_sdram_interface_wdata_we\n      New ports: A=1'0, B=1'1, Y=\\main_sdram_interface_wdata_we [0]\n      New connections: \\main_sdram_interface_wdata_we [1] = \\main_sdram_interface_wdata_we [0]\n    Consolidated identical input bits for $mux cell $procmux$10519:\n      Old ports: A=3'100, B=3'010, Y=$procmux$10519_Y\n      New ports: A=2'10, B=2'01, Y=$procmux$10519_Y [2:1]\n      New connections: $procmux$10519_Y [0] = 1'0\n    Consolidated identical input bits for $mux cell $procmux$9040:\n      Old ports: A=11'00000000000, B=11'10000000000, Y=$auto$wreduce.cc:454:run$14121 [10:0]\n      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$14121 [10]\n      New connections: $auto$wreduce.cc:454:run$14121 [9:0] = 10'0000000000\n    Consolidated identical input bits for $mux cell $procmux$9348:\n      Old ports: A=2'00, B=2'11, Y=$procmux$9348_Y\n      New ports: A=1'0, B=1'1, Y=$procmux$9348_Y [0]\n      New connections: $procmux$9348_Y [1] = $procmux$9348_Y [0]\n  Optimizing cells in module \\top.\n    Consolidated identical input bits for $pmux cell $flatten\\VexRiscv.$procmux$7485:\n      Old ports: A=2'11, B={ $flatten\\VexRiscv.$2\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] $flatten\\VexRiscv.$3\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] $flatten\\VexRiscv.$4\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] $flatten\\VexRiscv.$5\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] $flatten\\VexRiscv.$6\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] $flatten\\VexRiscv.$7\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] $flatten\\VexRiscv.$8\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] $flatten\\VexRiscv.$9\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] $flatten\\VexRiscv.$10\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] $flatten\\VexRiscv.$11\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] $flatten\\VexRiscv.$12\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] $flatten\\VexRiscv.$13\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] }, Y=\\VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped\n      New ports: A=1'1, B={ $flatten\\VexRiscv.$2\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1] $flatten\\VexRiscv.$3\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1] $flatten\\VexRiscv.$4\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1] $flatten\\VexRiscv.$5\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1] $flatten\\VexRiscv.$6\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1] $flatten\\VexRiscv.$7\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1] $flatten\\VexRiscv.$8\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1] $flatten\\VexRiscv.$9\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1] $flatten\\VexRiscv.$10\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1] $flatten\\VexRiscv.$11\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1] $flatten\\VexRiscv.$12\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1] $flatten\\VexRiscv.$13\\CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped[1:0] [1] }, Y=\\VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped [1]\n      New connections: \\VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped [0] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7502:\n      Old ports: A={ \\VexRiscv.decode_to_execute_INSTRUCTION [31] $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5969$3224_Y [19:0] }, B=21'000000000000000000100, Y=$flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20:0]\n      New ports: A={ \\VexRiscv.decode_to_execute_INSTRUCTION [31] $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5969$3224_Y [19:11] \\VexRiscv.decode_to_execute_INSTRUCTION [30:25] $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:5969$3224_Y [4:1] }, B=20'00000000000000000010, Y=$flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20:1]\n      New connections: $flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [0] = 1'0\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7508:\n      Old ports: A=$flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0], B={ \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31:20] }, Y=\\VexRiscv.execute_BranchPlugin_branch_src2\n      New ports: A=$flatten\\VexRiscv.$2\\execute_BranchPlugin_branch_src2[31:0] [20:0], B={ \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31] \\VexRiscv.decode_to_execute_INSTRUCTION [31:20] }, Y=\\VexRiscv.execute_BranchPlugin_branch_src2 [20:0]\n      New connections: \\VexRiscv.execute_BranchPlugin_branch_src2 [31:21] = { \\VexRiscv.execute_BranchPlugin_branch_src2 [20] \\VexRiscv.execute_BranchPlugin_branch_src2 [20] \\VexRiscv.execute_BranchPlugin_branch_src2 [20] \\VexRiscv.execute_BranchPlugin_branch_src2 [20] \\VexRiscv.execute_BranchPlugin_branch_src2 [20] \\VexRiscv.execute_BranchPlugin_branch_src2 [20] \\VexRiscv.execute_BranchPlugin_branch_src2 [20] \\VexRiscv.execute_BranchPlugin_branch_src2 [20] \\VexRiscv.execute_BranchPlugin_branch_src2 [20] \\VexRiscv.execute_BranchPlugin_branch_src2 [20] \\VexRiscv.execute_BranchPlugin_branch_src2 [20] }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7806:\n      Old ports: A={ 1'0 $auto$wreduce.cc:454:run$14087 [2:0] }, B={ 2'11 \\VexRiscv._zz_360_ [1:0] }, Y=\\VexRiscv.DBusCachedPlugin_exceptionBus_payload_code\n      New ports: A={ 1'0 $auto$wreduce.cc:454:run$14087 [1:0] }, B={ 1'1 \\VexRiscv._zz_360_ [1] 1'1 }, Y={ \\VexRiscv.DBusCachedPlugin_exceptionBus_payload_code [3] \\VexRiscv.DBusCachedPlugin_exceptionBus_payload_code [1:0] }\n      New connections: \\VexRiscv.DBusCachedPlugin_exceptionBus_payload_code [2] = 1'1\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:7440$3523:\n      Old ports: A=4'0010, B=\\VexRiscv.IBusCachedPlugin_decodeExceptionPort_payload_code, Y=$flatten\\VexRiscv.$procmux$4985_Y\n      New ports: A=3'010, B={ \\VexRiscv.IBusCachedPlugin_decodeExceptionPort_payload_code [2] 1'0 \\VexRiscv.IBusCachedPlugin_decodeExceptionPort_payload_code [0] }, Y=$flatten\\VexRiscv.$procmux$4985_Y [2:0]\n      New connections: $flatten\\VexRiscv.$procmux$4985_Y [3] = $flatten\\VexRiscv.$procmux$4985_Y [2]\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4200:\n      Old ports: A=$flatten\\VexRiscv.\\dataCache_1_.$3\\io_mem_cmd_payload_length[2:0], B=3'000, Y=\\VexRiscv.dataCache_1__io_mem_cmd_payload_length\n      New ports: A=$flatten\\VexRiscv.\\dataCache_1_.$3\\io_mem_cmd_payload_length[2:0] [0], B=1'0, Y=\\VexRiscv.dataCache_1__io_mem_cmd_payload_length [0]\n      New connections: \\VexRiscv.dataCache_1__io_mem_cmd_payload_length [2:1] = { \\VexRiscv.dataCache_1__io_mem_cmd_payload_length [0] \\VexRiscv.dataCache_1__io_mem_cmd_payload_length [0] }\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.\\dataCache_1_.$procmux$4218:\n      Old ports: A=$flatten\\VexRiscv.\\dataCache_1_.$3\\io_mem_cmd_payload_address[31:0] [4:0], B={ \\VexRiscv.dataCache_1_.stageB_mmuRsp_physicalAddress [4:2] 2'00 }, Y=\\VexRiscv.dataCache_1__io_mem_cmd_payload_address [4:0]\n      New ports: A=$flatten\\VexRiscv.\\dataCache_1_.$3\\io_mem_cmd_payload_address[31:0] [4:2], B=\\VexRiscv.dataCache_1_.stageB_mmuRsp_physicalAddress [4:2], Y=\\VexRiscv.dataCache_1__io_mem_cmd_payload_address [4:2]\n      New connections: \\VexRiscv.dataCache_1__io_mem_cmd_payload_address [1:0] = 2'00\n  Optimizing cells in module \\top.\nPerformed a total of 65 changes.\n\n4.33.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\n<suppressed ~3 debug messages>\nRemoved a total of 1 cells.\n\n4.33.6. Executing OPT_DFF pass (perform DFF optimizations).\nAdding SRST signal on $auto$opt_dff.cc:764:run$13730 ($dffe) from module top (D = $flatten\\VexRiscv.$procmux$4989_Y [2], Q = \\VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_code [2], rval = 1'1).\nHandling const CLK on $memory\\mem_2[0]$15793 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[0]$15793 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[0]$15793 ($dff) from module top.\nSetting constant 1-bit at position 2 on $memory\\mem_2[0]$15793 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[0]$15793 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[0]$15793 ($dff) from module top.\nSetting constant 0-bit at position 5 on $memory\\mem_2[0]$15793 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[0]$15793 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[0]$15793 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[1]$15795 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[1]$15795 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[1]$15795 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[1]$15795 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[1]$15795 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[1]$15795 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[1]$15795 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[1]$15795 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[1]$15795 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[2]$15797 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[2]$15797 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[2]$15797 ($dff) from module top.\nSetting constant 1-bit at position 2 on $memory\\mem_2[2]$15797 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[2]$15797 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[2]$15797 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[2]$15797 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[2]$15797 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[2]$15797 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[3]$15799 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[3]$15799 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[3]$15799 ($dff) from module top.\nSetting constant 1-bit at position 2 on $memory\\mem_2[3]$15799 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[3]$15799 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[3]$15799 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[3]$15799 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[3]$15799 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[3]$15799 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[4]$15801 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[4]$15801 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[4]$15801 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[4]$15801 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[4]$15801 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[4]$15801 ($dff) from module top.\nSetting constant 0-bit at position 5 on $memory\\mem_2[4]$15801 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[4]$15801 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[4]$15801 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[5]$15803 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[5]$15803 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[5]$15803 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[5]$15803 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[5]$15803 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[5]$15803 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[5]$15803 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[5]$15803 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[5]$15803 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[6]$15805 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[6]$15805 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[6]$15805 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[6]$15805 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[6]$15805 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[6]$15805 ($dff) from module top.\nSetting constant 0-bit at position 5 on $memory\\mem_2[6]$15805 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[6]$15805 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[6]$15805 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[7]$15807 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[7]$15807 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[7]$15807 ($dff) from module top.\nSetting constant 1-bit at position 2 on $memory\\mem_2[7]$15807 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[7]$15807 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[7]$15807 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[7]$15807 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[7]$15807 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[7]$15807 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[8]$15809 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[8]$15809 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[8]$15809 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[8]$15809 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[8]$15809 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[8]$15809 ($dff) from module top.\nSetting constant 0-bit at position 5 on $memory\\mem_2[8]$15809 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[8]$15809 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[8]$15809 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[9]$15811 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[9]$15811 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[9]$15811 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[9]$15811 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[9]$15811 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[9]$15811 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[9]$15811 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[9]$15811 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[9]$15811 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[10]$15813 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[10]$15813 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[10]$15813 ($dff) from module top.\nSetting constant 1-bit at position 2 on $memory\\mem_2[10]$15813 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[10]$15813 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[10]$15813 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[10]$15813 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[10]$15813 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[10]$15813 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[11]$15815 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[11]$15815 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[11]$15815 ($dff) from module top.\nSetting constant 1-bit at position 2 on $memory\\mem_2[11]$15815 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[11]$15815 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[11]$15815 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[11]$15815 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[11]$15815 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[11]$15815 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[12]$15817 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[12]$15817 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[12]$15817 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[12]$15817 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[12]$15817 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[12]$15817 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[12]$15817 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[12]$15817 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[12]$15817 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[13]$15819 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[13]$15819 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[13]$15819 ($dff) from module top.\nSetting constant 1-bit at position 2 on $memory\\mem_2[13]$15819 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[13]$15819 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[13]$15819 ($dff) from module top.\nSetting constant 0-bit at position 5 on $memory\\mem_2[13]$15819 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[13]$15819 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[13]$15819 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[14]$15821 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[14]$15821 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[14]$15821 ($dff) from module top.\nSetting constant 1-bit at position 2 on $memory\\mem_2[14]$15821 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[14]$15821 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[14]$15821 ($dff) from module top.\nSetting constant 0-bit at position 5 on $memory\\mem_2[14]$15821 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[14]$15821 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[14]$15821 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[15]$15823 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[15]$15823 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[15]$15823 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[15]$15823 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[15]$15823 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[15]$15823 ($dff) from module top.\nSetting constant 0-bit at position 5 on $memory\\mem_2[15]$15823 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[15]$15823 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[15]$15823 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[16]$15825 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[16]$15825 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[16]$15825 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[16]$15825 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[16]$15825 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[16]$15825 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[16]$15825 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[16]$15825 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[16]$15825 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[17]$15827 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[17]$15827 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[17]$15827 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[17]$15827 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[17]$15827 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[17]$15827 ($dff) from module top.\nSetting constant 0-bit at position 5 on $memory\\mem_2[17]$15827 ($dff) from module top.\nSetting constant 1-bit at position 6 on $memory\\mem_2[17]$15827 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[17]$15827 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[18]$15829 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[18]$15829 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[18]$15829 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[18]$15829 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[18]$15829 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[18]$15829 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[18]$15829 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[18]$15829 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[18]$15829 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[19]$15831 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[19]$15831 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[19]$15831 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[19]$15831 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[19]$15831 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[19]$15831 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[19]$15831 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[19]$15831 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[19]$15831 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[20]$15833 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[20]$15833 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[20]$15833 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[20]$15833 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[20]$15833 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[20]$15833 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[20]$15833 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[20]$15833 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[20]$15833 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[21]$15835 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[21]$15835 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[21]$15835 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[21]$15835 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[21]$15835 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[21]$15835 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[21]$15835 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[21]$15835 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[21]$15835 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[22]$15837 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[22]$15837 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[22]$15837 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[22]$15837 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[22]$15837 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[22]$15837 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[22]$15837 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[22]$15837 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[22]$15837 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[23]$15839 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[23]$15839 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[23]$15839 ($dff) from module top.\nSetting constant 1-bit at position 2 on $memory\\mem_2[23]$15839 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[23]$15839 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[23]$15839 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[23]$15839 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[23]$15839 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[23]$15839 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[24]$15841 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[24]$15841 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[24]$15841 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[24]$15841 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[24]$15841 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[24]$15841 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[24]$15841 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[24]$15841 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[24]$15841 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[25]$15843 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[25]$15843 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[25]$15843 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[25]$15843 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[25]$15843 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[25]$15843 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[25]$15843 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[25]$15843 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[25]$15843 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[26]$15845 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[26]$15845 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[26]$15845 ($dff) from module top.\nSetting constant 1-bit at position 2 on $memory\\mem_2[26]$15845 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[26]$15845 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[26]$15845 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[26]$15845 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[26]$15845 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[26]$15845 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[27]$15847 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[27]$15847 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[27]$15847 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[27]$15847 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[27]$15847 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[27]$15847 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[27]$15847 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[27]$15847 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[27]$15847 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[28]$15849 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[28]$15849 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[28]$15849 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[28]$15849 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[28]$15849 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[28]$15849 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[28]$15849 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[28]$15849 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[28]$15849 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[29]$15851 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[29]$15851 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[29]$15851 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[29]$15851 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[29]$15851 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[29]$15851 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[29]$15851 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[29]$15851 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[29]$15851 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[30]$15853 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[30]$15853 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[30]$15853 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[30]$15853 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[30]$15853 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[30]$15853 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[30]$15853 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[30]$15853 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[30]$15853 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[31]$15855 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[31]$15855 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[31]$15855 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[31]$15855 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[31]$15855 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[31]$15855 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[31]$15855 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[31]$15855 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[31]$15855 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[32]$15857 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[32]$15857 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[32]$15857 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[32]$15857 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[32]$15857 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[32]$15857 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[32]$15857 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[32]$15857 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[32]$15857 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[33]$15859 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[33]$15859 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[33]$15859 ($dff) from module top.\nSetting constant 1-bit at position 2 on $memory\\mem_2[33]$15859 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[33]$15859 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[33]$15859 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[33]$15859 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[33]$15859 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[33]$15859 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[34]$15861 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[34]$15861 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[34]$15861 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[34]$15861 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[34]$15861 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[34]$15861 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[34]$15861 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[34]$15861 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[34]$15861 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[35]$15863 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[35]$15863 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[35]$15863 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[35]$15863 ($dff) from module top.\nSetting constant 1-bit at position 3 on $memory\\mem_2[35]$15863 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[35]$15863 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[35]$15863 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[35]$15863 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[35]$15863 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[36]$15865 ($dff) from module top (removing D path).\nSetting constant 1-bit at position 0 on $memory\\mem_2[36]$15865 ($dff) from module top.\nSetting constant 1-bit at position 1 on $memory\\mem_2[36]$15865 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[36]$15865 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[36]$15865 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[36]$15865 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[36]$15865 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[36]$15865 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[36]$15865 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[37]$15867 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[37]$15867 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[37]$15867 ($dff) from module top.\nSetting constant 1-bit at position 2 on $memory\\mem_2[37]$15867 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[37]$15867 ($dff) from module top.\nSetting constant 1-bit at position 4 on $memory\\mem_2[37]$15867 ($dff) from module top.\nSetting constant 1-bit at position 5 on $memory\\mem_2[37]$15867 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[37]$15867 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[37]$15867 ($dff) from module top.\nHandling const CLK on $memory\\mem_2[38]$15869 ($dff) from module top (removing D path).\nSetting constant 0-bit at position 0 on $memory\\mem_2[38]$15869 ($dff) from module top.\nSetting constant 0-bit at position 1 on $memory\\mem_2[38]$15869 ($dff) from module top.\nSetting constant 0-bit at position 2 on $memory\\mem_2[38]$15869 ($dff) from module top.\nSetting constant 0-bit at position 3 on $memory\\mem_2[38]$15869 ($dff) from module top.\nSetting constant 0-bit at position 4 on $memory\\mem_2[38]$15869 ($dff) from module top.\nSetting constant 0-bit at position 5 on $memory\\mem_2[38]$15869 ($dff) from module top.\nSetting constant 0-bit at position 6 on $memory\\mem_2[38]$15869 ($dff) from module top.\nSetting constant 0-bit at position 7 on $memory\\mem_2[38]$15869 ($dff) from module top.\nRemoving always-active EN on mem_2$rdreg[0] ($dffe) from module top.\n\n4.33.7. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 0 unused cells and 126 unused wires.\n<suppressed ~1 debug messages>\n\n4.33.8. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~4 debug messages>\n\n4.33.9. Rerunning OPT passes. (Maybe there is more to do..)\n\n4.33.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~503 debug messages>\n\n4.33.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7812:\n      Old ports: A={ \\VexRiscv._zz_360_ [1] 1'1 }, B={ \\VexRiscv._zz_360_ [1] 1'0 }, Y=$auto$wreduce.cc:454:run$14087 [1:0]\n      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$14087 [0]\n      New connections: $auto$wreduce.cc:454:run$14087 [1] = \\VexRiscv._zz_360_ [1]\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][0]$15964:\n      Old ports: A=8'01001100, B=8'01101001, Y=$memory\\mem_2$rdmux[0][4][0]$a$15917\n      New ports: A=2'10, B=2'01, Y={ $memory\\mem_2$rdmux[0][4][0]$a$15917 [2] $memory\\mem_2$rdmux[0][4][0]$a$15917 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][4][0]$a$15917 [7:3] $memory\\mem_2$rdmux[0][4][0]$a$15917 [1] } = { 2'01 $memory\\mem_2$rdmux[0][4][0]$a$15917 [0] 3'010 }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][10]$15994:\n      Old ports: A=8'00110000, B=8'00110010, Y=$memory\\mem_2$rdmux[0][4][5]$a$15932\n      New ports: A=1'0, B=1'1, Y=$memory\\mem_2$rdmux[0][4][5]$a$15932 [1]\n      New connections: { $memory\\mem_2$rdmux[0][4][5]$a$15932 [7:2] $memory\\mem_2$rdmux[0][4][5]$a$15932 [0] } = 7'0011000\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][11]$15997:\n      Old ports: A=8'00110000, B=8'00101101, Y=$memory\\mem_2$rdmux[0][4][5]$b$15933\n      New ports: A=2'10, B=2'01, Y={ $memory\\mem_2$rdmux[0][4][5]$b$15933 [4] $memory\\mem_2$rdmux[0][4][5]$b$15933 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][4][5]$b$15933 [7:5] $memory\\mem_2$rdmux[0][4][5]$b$15933 [3:1] } = { 3'001 $memory\\mem_2$rdmux[0][4][5]$b$15933 [0] $memory\\mem_2$rdmux[0][4][5]$b$15933 [0] 1'0 }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][13]$16003:\n      Old ports: A=8'00101101, B=8'00110001, Y=$memory\\mem_2$rdmux[0][4][6]$b$15936\n      New ports: A=2'01, B=2'10, Y={ $memory\\mem_2$rdmux[0][4][6]$b$15936 [4] $memory\\mem_2$rdmux[0][4][6]$b$15936 [2] }\n      New connections: { $memory\\mem_2$rdmux[0][4][6]$b$15936 [7:5] $memory\\mem_2$rdmux[0][4][6]$b$15936 [3] $memory\\mem_2$rdmux[0][4][6]$b$15936 [1:0] } = { 3'001 $memory\\mem_2$rdmux[0][4][6]$b$15936 [2] 2'01 }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][14]$16006:\n      Old ports: A=8'00110001, B=8'00100000, Y=$memory\\mem_2$rdmux[0][4][7]$a$15938\n      New ports: A=1'1, B=1'0, Y=$memory\\mem_2$rdmux[0][4][7]$a$15938 [0]\n      New connections: $memory\\mem_2$rdmux[0][4][7]$a$15938 [7:1] = { 3'001 $memory\\mem_2$rdmux[0][4][7]$a$15938 [0] 3'000 }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][15]$16009:\n      Old ports: A=8'00110000, B=8'00111001, Y=$memory\\mem_2$rdmux[0][4][7]$b$15939\n      New ports: A=1'0, B=1'1, Y=$memory\\mem_2$rdmux[0][4][7]$b$15939 [0]\n      New connections: $memory\\mem_2$rdmux[0][4][7]$b$15939 [7:1] = { 4'0011 $memory\\mem_2$rdmux[0][4][7]$b$15939 [0] 2'00 }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][16]$16012:\n      Old ports: A=8'00111010, B=8'00110100, Y=$memory\\mem_2$rdmux[0][4][8]$a$15941\n      New ports: A=2'01, B=2'10, Y=$memory\\mem_2$rdmux[0][4][8]$a$15941 [2:1]\n      New connections: { $memory\\mem_2$rdmux[0][4][8]$a$15941 [7:3] $memory\\mem_2$rdmux[0][4][8]$a$15941 [0] } = { 4'0011 $memory\\mem_2$rdmux[0][4][8]$a$15941 [1] 1'0 }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][17]$16015:\n      Old ports: A=8'00110011, B=8'00111010, Y=$memory\\mem_2$rdmux[0][4][8]$b$15942\n      New ports: A=2'01, B=2'10, Y={ $memory\\mem_2$rdmux[0][4][8]$b$15942 [3] $memory\\mem_2$rdmux[0][4][8]$b$15942 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][4][8]$b$15942 [7:4] $memory\\mem_2$rdmux[0][4][8]$b$15942 [2:1] } = 6'001101\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][18]$16018:\n      Old ports: A=8'00110011, B=8'00110100, Y=$memory\\mem_2$rdmux[0][4][9]$a$15944\n      New ports: A=2'01, B=2'10, Y={ $memory\\mem_2$rdmux[0][4][9]$a$15944 [2] $memory\\mem_2$rdmux[0][4][9]$a$15944 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][4][9]$a$15944 [7:3] $memory\\mem_2$rdmux[0][4][9]$a$15944 [1] } = { 5'00110 $memory\\mem_2$rdmux[0][4][9]$a$15944 [0] }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][19]$16021:\n      Old ports: A=8'00000000, B=8'xxxxxxxx, Y=$memory\\mem_2$rdmux[0][4][9]$b$15945\n      New ports: A=1'0, B=1'x, Y=$memory\\mem_2$rdmux[0][4][9]$b$15945 [0]\n      New connections: $memory\\mem_2$rdmux[0][4][9]$b$15945 [7:1] = { $memory\\mem_2$rdmux[0][4][9]$b$15945 [0] $memory\\mem_2$rdmux[0][4][9]$b$15945 [0] $memory\\mem_2$rdmux[0][4][9]$b$15945 [0] $memory\\mem_2$rdmux[0][4][9]$b$15945 [0] $memory\\mem_2$rdmux[0][4][9]$b$15945 [0] $memory\\mem_2$rdmux[0][4][9]$b$15945 [0] $memory\\mem_2$rdmux[0][4][9]$b$15945 [0] }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][1]$15967:\n      Old ports: A=8'01110100, B=8'01100101, Y=$memory\\mem_2$rdmux[0][4][0]$b$15918\n      New ports: A=2'10, B=2'01, Y={ $memory\\mem_2$rdmux[0][4][0]$b$15918 [4] $memory\\mem_2$rdmux[0][4][0]$b$15918 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][4][0]$b$15918 [7:5] $memory\\mem_2$rdmux[0][4][0]$b$15918 [3:1] } = 6'011010\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][2]$15970:\n      Old ports: A=8'01011000, B=8'00100000, Y=$memory\\mem_2$rdmux[0][4][1]$a$15920\n      New ports: A=2'01, B=2'10, Y={ $memory\\mem_2$rdmux[0][4][1]$a$15920 [5] $memory\\mem_2$rdmux[0][4][1]$a$15920 [3] }\n      New connections: { $memory\\mem_2$rdmux[0][4][1]$a$15920 [7:6] $memory\\mem_2$rdmux[0][4][1]$a$15920 [4] $memory\\mem_2$rdmux[0][4][1]$a$15920 [2:0] } = { 1'0 $memory\\mem_2$rdmux[0][4][1]$a$15920 [3] $memory\\mem_2$rdmux[0][4][1]$a$15920 [3] 3'000 }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][3]$15973:\n      Old ports: A=8'01010011, B=8'01101111, Y=$memory\\mem_2$rdmux[0][4][1]$b$15921\n      New ports: A=2'10, B=2'01, Y={ $memory\\mem_2$rdmux[0][4][1]$b$15921 [4] $memory\\mem_2$rdmux[0][4][1]$b$15921 [2] }\n      New connections: { $memory\\mem_2$rdmux[0][4][1]$b$15921 [7:5] $memory\\mem_2$rdmux[0][4][1]$b$15921 [3] $memory\\mem_2$rdmux[0][4][1]$b$15921 [1:0] } = { 2'01 $memory\\mem_2$rdmux[0][4][1]$b$15921 [2] $memory\\mem_2$rdmux[0][4][1]$b$15921 [2] 2'11 }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][4]$15976:\n      Old ports: A=8'01000011, B=8'00100000, Y=$memory\\mem_2$rdmux[0][4][2]$a$15923\n      New ports: A=2'01, B=2'10, Y={ $memory\\mem_2$rdmux[0][4][2]$a$15923 [5] $memory\\mem_2$rdmux[0][4][2]$a$15923 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][4][2]$a$15923 [7:6] $memory\\mem_2$rdmux[0][4][2]$a$15923 [4:1] } = { 1'0 $memory\\mem_2$rdmux[0][4][2]$a$15923 [0] 3'000 $memory\\mem_2$rdmux[0][4][2]$a$15923 [0] }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][5]$15979:\n      Old ports: A=8'01101111, B=8'01101110, Y=$memory\\mem_2$rdmux[0][4][2]$b$15924\n      New ports: A=1'1, B=1'0, Y=$memory\\mem_2$rdmux[0][4][2]$b$15924 [0]\n      New connections: $memory\\mem_2$rdmux[0][4][2]$b$15924 [7:1] = 7'0110111\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][6]$15982:\n      Old ports: A=8'00100000, B=8'01010101, Y=$memory\\mem_2$rdmux[0][4][3]$a$15926\n      New ports: A=2'10, B=2'01, Y={ $memory\\mem_2$rdmux[0][4][3]$a$15926 [5] $memory\\mem_2$rdmux[0][4][3]$a$15926 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][4][3]$a$15926 [7:6] $memory\\mem_2$rdmux[0][4][3]$a$15926 [4:1] } = { 1'0 $memory\\mem_2$rdmux[0][4][3]$a$15926 [0] $memory\\mem_2$rdmux[0][4][3]$a$15926 [0] 1'0 $memory\\mem_2$rdmux[0][4][3]$a$15926 [0] 1'0 }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][7]$15985:\n      Old ports: A=8'01001100, B=8'01011000, Y=$memory\\mem_2$rdmux[0][4][3]$b$15927\n      New ports: A=2'01, B=2'10, Y={ $memory\\mem_2$rdmux[0][4][3]$b$15927 [4] $memory\\mem_2$rdmux[0][4][3]$b$15927 [2] }\n      New connections: { $memory\\mem_2$rdmux[0][4][3]$b$15927 [7:5] $memory\\mem_2$rdmux[0][4][3]$b$15927 [3] $memory\\mem_2$rdmux[0][4][3]$b$15927 [1:0] } = 6'010100\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][8]$15988:\n      Old ports: A=8'00110011, B=8'01010011, Y=$memory\\mem_2$rdmux[0][4][4]$a$15929\n      New ports: A=2'01, B=2'10, Y=$memory\\mem_2$rdmux[0][4][4]$a$15929 [6:5]\n      New connections: { $memory\\mem_2$rdmux[0][4][4]$a$15929 [7] $memory\\mem_2$rdmux[0][4][4]$a$15929 [4:0] } = 6'010011\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][5][9]$15991:\n      Old ports: A=8'00100000, B=8'00110010, Y=$memory\\mem_2$rdmux[0][4][4]$b$15930\n      New ports: A=1'0, B=1'1, Y=$memory\\mem_2$rdmux[0][4][4]$b$15930 [1]\n      New connections: { $memory\\mem_2$rdmux[0][4][4]$b$15930 [7:2] $memory\\mem_2$rdmux[0][4][4]$b$15930 [0] } = { 3'001 $memory\\mem_2$rdmux[0][4][4]$b$15930 [1] 3'000 }\n    Consolidated identical input bits for $mux cell $procmux$11540:\n      Old ports: A=2'00, B=\\main_sdram_slave_p0_wrdata_mask, Y=\\main_dfi_p0_wrdata_mask\n      New ports: A=1'0, B=$auto$opt_expr.cc:205:group_cell_inputs$16061, Y=\\main_dfi_p0_wrdata_mask [0]\n      New connections: \\main_dfi_p0_wrdata_mask [1] = \\main_dfi_p0_wrdata_mask [0]\n  Optimizing cells in module \\top.\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$procmux$7806:\n      Old ports: A={ 1'0 $auto$wreduce.cc:454:run$14087 [1:0] }, B={ 1'1 \\VexRiscv._zz_360_ [1] 1'1 }, Y={ \\VexRiscv.DBusCachedPlugin_exceptionBus_payload_code [3] \\VexRiscv.DBusCachedPlugin_exceptionBus_payload_code [1:0] }\n      New ports: A={ 1'0 $auto$wreduce.cc:454:run$14087 [0] }, B=2'11, Y={ \\VexRiscv.DBusCachedPlugin_exceptionBus_payload_code [3] \\VexRiscv.DBusCachedPlugin_exceptionBus_payload_code [0] }\n      New connections: \\VexRiscv.DBusCachedPlugin_exceptionBus_payload_code [1] = \\VexRiscv._zz_360_ [1]\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][4][0]$15916:\n      Old ports: A=$memory\\mem_2$rdmux[0][4][0]$a$15917, B=$memory\\mem_2$rdmux[0][4][0]$b$15918, Y=$memory\\mem_2$rdmux[0][3][0]$a$15893\n      New ports: A={ $memory\\mem_2$rdmux[0][4][0]$a$15917 [0] 2'01 $memory\\mem_2$rdmux[0][4][0]$a$15917 [2] $memory\\mem_2$rdmux[0][4][0]$a$15917 [0] }, B={ 1'1 $memory\\mem_2$rdmux[0][4][0]$b$15918 [4] 2'01 $memory\\mem_2$rdmux[0][4][0]$b$15918 [0] }, Y={ $memory\\mem_2$rdmux[0][3][0]$a$15893 [5:2] $memory\\mem_2$rdmux[0][3][0]$a$15893 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][3][0]$a$15893 [7:6] $memory\\mem_2$rdmux[0][3][0]$a$15893 [1] } = 3'010\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][4][1]$15919:\n      Old ports: A=$memory\\mem_2$rdmux[0][4][1]$a$15920, B=$memory\\mem_2$rdmux[0][4][1]$b$15921, Y=$memory\\mem_2$rdmux[0][3][0]$b$15894\n      New ports: A={ $memory\\mem_2$rdmux[0][4][1]$a$15920 [3] $memory\\mem_2$rdmux[0][4][1]$a$15920 [5] $memory\\mem_2$rdmux[0][4][1]$a$15920 [3] $memory\\mem_2$rdmux[0][4][1]$a$15920 [3] 2'00 }, B={ 1'1 $memory\\mem_2$rdmux[0][4][1]$b$15921 [2] $memory\\mem_2$rdmux[0][4][1]$b$15921 [4] $memory\\mem_2$rdmux[0][4][1]$b$15921 [2] $memory\\mem_2$rdmux[0][4][1]$b$15921 [2] 1'1 }, Y={ $memory\\mem_2$rdmux[0][3][0]$b$15894 [6:2] $memory\\mem_2$rdmux[0][3][0]$b$15894 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][3][0]$b$15894 [7] $memory\\mem_2$rdmux[0][3][0]$b$15894 [1] } = { 1'0 $memory\\mem_2$rdmux[0][3][0]$b$15894 [0] }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][4][2]$15922:\n      Old ports: A=$memory\\mem_2$rdmux[0][4][2]$a$15923, B=$memory\\mem_2$rdmux[0][4][2]$b$15924, Y=$memory\\mem_2$rdmux[0][3][1]$a$15896\n      New ports: A={ $memory\\mem_2$rdmux[0][4][2]$a$15923 [5] 1'0 $memory\\mem_2$rdmux[0][4][2]$a$15923 [0] $memory\\mem_2$rdmux[0][4][2]$a$15923 [0] }, B={ 3'111 $memory\\mem_2$rdmux[0][4][2]$b$15924 [0] }, Y={ $memory\\mem_2$rdmux[0][3][1]$a$15896 [5] $memory\\mem_2$rdmux[0][3][1]$a$15896 [2:0] }\n      New connections: { $memory\\mem_2$rdmux[0][3][1]$a$15896 [7:6] $memory\\mem_2$rdmux[0][3][1]$a$15896 [4:3] } = { 1'0 $memory\\mem_2$rdmux[0][3][1]$a$15896 [1] 1'0 $memory\\mem_2$rdmux[0][3][1]$a$15896 [2] }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][4][3]$15925:\n      Old ports: A=$memory\\mem_2$rdmux[0][4][3]$a$15926, B=$memory\\mem_2$rdmux[0][4][3]$b$15927, Y=$memory\\mem_2$rdmux[0][3][1]$b$15897\n      New ports: A={ $memory\\mem_2$rdmux[0][4][3]$a$15926 [0] $memory\\mem_2$rdmux[0][4][3]$a$15926 [5] $memory\\mem_2$rdmux[0][4][3]$a$15926 [0] 1'0 $memory\\mem_2$rdmux[0][4][3]$a$15926 [0] $memory\\mem_2$rdmux[0][4][3]$a$15926 [0] }, B={ 2'10 $memory\\mem_2$rdmux[0][4][3]$b$15927 [4] 1'1 $memory\\mem_2$rdmux[0][4][3]$b$15927 [2] 1'0 }, Y={ $memory\\mem_2$rdmux[0][3][1]$b$15897 [6:2] $memory\\mem_2$rdmux[0][3][1]$b$15897 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][3][1]$b$15897 [7] $memory\\mem_2$rdmux[0][3][1]$b$15897 [1] } = 2'00\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][4][4]$15928:\n      Old ports: A=$memory\\mem_2$rdmux[0][4][4]$a$15929, B=$memory\\mem_2$rdmux[0][4][4]$b$15930, Y=$memory\\mem_2$rdmux[0][3][2]$a$15899\n      New ports: A={ $memory\\mem_2$rdmux[0][4][4]$a$15929 [6:5] 2'11 }, B={ 2'01 $memory\\mem_2$rdmux[0][4][4]$b$15930 [1] 1'0 }, Y={ $memory\\mem_2$rdmux[0][3][2]$a$15899 [6:5] $memory\\mem_2$rdmux[0][3][2]$a$15899 [1:0] }\n      New connections: { $memory\\mem_2$rdmux[0][3][2]$a$15899 [7] $memory\\mem_2$rdmux[0][3][2]$a$15899 [4:2] } = { 1'0 $memory\\mem_2$rdmux[0][3][2]$a$15899 [1] 2'00 }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][4][5]$15931:\n      Old ports: A=$memory\\mem_2$rdmux[0][4][5]$a$15932, B=$memory\\mem_2$rdmux[0][4][5]$b$15933, Y=$memory\\mem_2$rdmux[0][3][2]$b$15900\n      New ports: A={ 1'1 $memory\\mem_2$rdmux[0][4][5]$a$15932 [1] 1'0 }, B={ $memory\\mem_2$rdmux[0][4][5]$b$15933 [4] 1'0 $memory\\mem_2$rdmux[0][4][5]$b$15933 [0] }, Y={ $memory\\mem_2$rdmux[0][3][2]$b$15900 [4] $memory\\mem_2$rdmux[0][3][2]$b$15900 [1:0] }\n      New connections: { $memory\\mem_2$rdmux[0][3][2]$b$15900 [7:5] $memory\\mem_2$rdmux[0][3][2]$b$15900 [3:2] } = { 3'001 $memory\\mem_2$rdmux[0][3][2]$b$15900 [0] $memory\\mem_2$rdmux[0][3][2]$b$15900 [0] }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][4][6]$15934:\n      Old ports: A=$memory\\mem_2$rdmux[0][4][6]$a$15935, B=$memory\\mem_2$rdmux[0][4][6]$b$15936, Y=$memory\\mem_2$rdmux[0][3][3]$a$15902\n      New ports: A=2'10, B={ $memory\\mem_2$rdmux[0][4][6]$b$15936 [4] $memory\\mem_2$rdmux[0][4][6]$b$15936 [2] }, Y={ $memory\\mem_2$rdmux[0][3][3]$a$15902 [4] $memory\\mem_2$rdmux[0][3][3]$a$15902 [2] }\n      New connections: { $memory\\mem_2$rdmux[0][3][3]$a$15902 [7:5] $memory\\mem_2$rdmux[0][3][3]$a$15902 [3] $memory\\mem_2$rdmux[0][3][3]$a$15902 [1:0] } = { 3'001 $memory\\mem_2$rdmux[0][3][3]$a$15902 [2] 2'01 }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][4][7]$15937:\n      Old ports: A=$memory\\mem_2$rdmux[0][4][7]$a$15938, B=$memory\\mem_2$rdmux[0][4][7]$b$15939, Y=$memory\\mem_2$rdmux[0][3][3]$b$15903\n      New ports: A={ $memory\\mem_2$rdmux[0][4][7]$a$15938 [0] 1'0 $memory\\mem_2$rdmux[0][4][7]$a$15938 [0] }, B={ 1'1 $memory\\mem_2$rdmux[0][4][7]$b$15939 [0] $memory\\mem_2$rdmux[0][4][7]$b$15939 [0] }, Y={ $memory\\mem_2$rdmux[0][3][3]$b$15903 [4:3] $memory\\mem_2$rdmux[0][3][3]$b$15903 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][3][3]$b$15903 [7:5] $memory\\mem_2$rdmux[0][3][3]$b$15903 [2:1] } = 5'00100\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][4][8]$15940:\n      Old ports: A=$memory\\mem_2$rdmux[0][4][8]$a$15941, B=$memory\\mem_2$rdmux[0][4][8]$b$15942, Y=$memory\\mem_2$rdmux[0][3][4]$a$15905\n      New ports: A={ $memory\\mem_2$rdmux[0][4][8]$a$15941 [1] $memory\\mem_2$rdmux[0][4][8]$a$15941 [2:1] 1'0 }, B={ $memory\\mem_2$rdmux[0][4][8]$b$15942 [3] 2'01 $memory\\mem_2$rdmux[0][4][8]$b$15942 [0] }, Y=$memory\\mem_2$rdmux[0][3][4]$a$15905 [3:0]\n      New connections: $memory\\mem_2$rdmux[0][3][4]$a$15905 [7:4] = 4'0011\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][4][9]$15943:\n      Old ports: A=$memory\\mem_2$rdmux[0][4][9]$a$15944, B=$memory\\mem_2$rdmux[0][4][9]$b$15945, Y=$memory\\mem_2$rdmux[0][3][4]$b$15906\n      New ports: A={ 2'10 $memory\\mem_2$rdmux[0][4][9]$a$15944 [2] $memory\\mem_2$rdmux[0][4][9]$a$15944 [0] }, B={ $memory\\mem_2$rdmux[0][4][9]$b$15945 [0] $memory\\mem_2$rdmux[0][4][9]$b$15945 [0] $memory\\mem_2$rdmux[0][4][9]$b$15945 [0] $memory\\mem_2$rdmux[0][4][9]$b$15945 [0] }, Y={ $memory\\mem_2$rdmux[0][3][4]$b$15906 [4:2] $memory\\mem_2$rdmux[0][3][4]$b$15906 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][3][4]$b$15906 [7:5] $memory\\mem_2$rdmux[0][3][4]$b$15906 [1] } = { $memory\\mem_2$rdmux[0][3][4]$b$15906 [3] $memory\\mem_2$rdmux[0][3][4]$b$15906 [3] $memory\\mem_2$rdmux[0][3][4]$b$15906 [4] $memory\\mem_2$rdmux[0][3][4]$b$15906 [0] }\n  Optimizing cells in module \\top.\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][3][0]$15892:\n      Old ports: A=$memory\\mem_2$rdmux[0][3][0]$a$15893, B=$memory\\mem_2$rdmux[0][3][0]$b$15894, Y=$memory\\mem_2$rdmux[0][2][0]$a$15881\n      New ports: A={ 1'1 $memory\\mem_2$rdmux[0][3][0]$a$15893 [5:2] 1'0 $memory\\mem_2$rdmux[0][3][0]$a$15893 [0] }, B={ $memory\\mem_2$rdmux[0][3][0]$b$15894 [6:2] $memory\\mem_2$rdmux[0][3][0]$b$15894 [0] $memory\\mem_2$rdmux[0][3][0]$b$15894 [0] }, Y=$memory\\mem_2$rdmux[0][2][0]$a$15881 [6:0]\n      New connections: $memory\\mem_2$rdmux[0][2][0]$a$15881 [7] = 1'0\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][3][1]$15895:\n      Old ports: A=$memory\\mem_2$rdmux[0][3][1]$a$15896, B=$memory\\mem_2$rdmux[0][3][1]$b$15897, Y=$memory\\mem_2$rdmux[0][2][0]$b$15882\n      New ports: A={ $memory\\mem_2$rdmux[0][3][1]$a$15896 [1] $memory\\mem_2$rdmux[0][3][1]$a$15896 [5] 1'0 $memory\\mem_2$rdmux[0][3][1]$a$15896 [2] $memory\\mem_2$rdmux[0][3][1]$a$15896 [2:0] }, B={ $memory\\mem_2$rdmux[0][3][1]$b$15897 [6:2] 1'0 $memory\\mem_2$rdmux[0][3][1]$b$15897 [0] }, Y=$memory\\mem_2$rdmux[0][2][0]$b$15882 [6:0]\n      New connections: $memory\\mem_2$rdmux[0][2][0]$b$15882 [7] = 1'0\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][3][2]$15898:\n      Old ports: A=$memory\\mem_2$rdmux[0][3][2]$a$15899, B=$memory\\mem_2$rdmux[0][3][2]$b$15900, Y=$memory\\mem_2$rdmux[0][2][1]$a$15884\n      New ports: A={ $memory\\mem_2$rdmux[0][3][2]$a$15899 [6:5] $memory\\mem_2$rdmux[0][3][2]$a$15899 [1] 1'0 $memory\\mem_2$rdmux[0][3][2]$a$15899 [1:0] }, B={ 2'01 $memory\\mem_2$rdmux[0][3][2]$b$15900 [4] $memory\\mem_2$rdmux[0][3][2]$b$15900 [0] $memory\\mem_2$rdmux[0][3][2]$b$15900 [1:0] }, Y={ $memory\\mem_2$rdmux[0][2][1]$a$15884 [6:4] $memory\\mem_2$rdmux[0][2][1]$a$15884 [2:0] }\n      New connections: { $memory\\mem_2$rdmux[0][2][1]$a$15884 [7] $memory\\mem_2$rdmux[0][2][1]$a$15884 [3] } = { 1'0 $memory\\mem_2$rdmux[0][2][1]$a$15884 [2] }\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][3][3]$15901:\n      Old ports: A=$memory\\mem_2$rdmux[0][3][3]$a$15902, B=$memory\\mem_2$rdmux[0][3][3]$b$15903, Y=$memory\\mem_2$rdmux[0][2][1]$b$15885\n      New ports: A={ $memory\\mem_2$rdmux[0][3][3]$a$15902 [4] $memory\\mem_2$rdmux[0][3][3]$a$15902 [2] $memory\\mem_2$rdmux[0][3][3]$a$15902 [2] 1'1 }, B={ $memory\\mem_2$rdmux[0][3][3]$b$15903 [4:3] 1'0 $memory\\mem_2$rdmux[0][3][3]$b$15903 [0] }, Y={ $memory\\mem_2$rdmux[0][2][1]$b$15885 [4:2] $memory\\mem_2$rdmux[0][2][1]$b$15885 [0] }\n      New connections: { $memory\\mem_2$rdmux[0][2][1]$b$15885 [7:5] $memory\\mem_2$rdmux[0][2][1]$b$15885 [1] } = 4'0010\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][3][4]$15904:\n      Old ports: A=$memory\\mem_2$rdmux[0][3][4]$a$15905, B=$memory\\mem_2$rdmux[0][3][4]$b$15906, Y=$memory\\mem_2$rdmux[0][2][2]$a$15887\n      New ports: A={ 2'01 $memory\\mem_2$rdmux[0][3][4]$a$15905 [3:0] }, B={ $memory\\mem_2$rdmux[0][3][4]$b$15906 [3] $memory\\mem_2$rdmux[0][3][4]$b$15906 [4:2] $memory\\mem_2$rdmux[0][3][4]$b$15906 [0] $memory\\mem_2$rdmux[0][3][4]$b$15906 [0] }, Y={ $memory\\mem_2$rdmux[0][2][2]$a$15887 [6] $memory\\mem_2$rdmux[0][2][2]$a$15887 [4:0] }\n      New connections: { $memory\\mem_2$rdmux[0][2][2]$a$15887 [7] $memory\\mem_2$rdmux[0][2][2]$a$15887 [5] } = { $memory\\mem_2$rdmux[0][2][2]$a$15887 [6] $memory\\mem_2$rdmux[0][2][2]$a$15887 [4] }\n  Optimizing cells in module \\top.\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][2][0]$15880:\n      Old ports: A=$memory\\mem_2$rdmux[0][2][0]$a$15881, B=$memory\\mem_2$rdmux[0][2][0]$b$15882, Y=$memory\\mem_2$rdmux[0][1][0]$a$15875\n      New ports: A=$memory\\mem_2$rdmux[0][2][0]$a$15881 [6:0], B=$memory\\mem_2$rdmux[0][2][0]$b$15882 [6:0], Y=$memory\\mem_2$rdmux[0][1][0]$a$15875 [6:0]\n      New connections: $memory\\mem_2$rdmux[0][1][0]$a$15875 [7] = 1'0\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][2][1]$15883:\n      Old ports: A=$memory\\mem_2$rdmux[0][2][1]$a$15884, B=$memory\\mem_2$rdmux[0][2][1]$b$15885, Y=$memory\\mem_2$rdmux[0][1][0]$b$15876\n      New ports: A={ $memory\\mem_2$rdmux[0][2][1]$a$15884 [6:4] $memory\\mem_2$rdmux[0][2][1]$a$15884 [2] $memory\\mem_2$rdmux[0][2][1]$a$15884 [2:0] }, B={ 2'01 $memory\\mem_2$rdmux[0][2][1]$b$15885 [4:2] 1'0 $memory\\mem_2$rdmux[0][2][1]$b$15885 [0] }, Y=$memory\\mem_2$rdmux[0][1][0]$b$15876 [6:0]\n      New connections: $memory\\mem_2$rdmux[0][1][0]$b$15876 [7] = 1'0\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][2][2]$15886:\n      Old ports: A=$memory\\mem_2$rdmux[0][2][2]$a$15887, B=8'xxxxxxxx, Y=$memory\\mem_2$rdmux[0][1][1]$a$15878\n      New ports: A={ $memory\\mem_2$rdmux[0][2][2]$a$15887 [6] $memory\\mem_2$rdmux[0][2][2]$a$15887 [4:0] }, B=6'xxxxxx, Y={ $memory\\mem_2$rdmux[0][1][1]$a$15878 [6] $memory\\mem_2$rdmux[0][1][1]$a$15878 [4:0] }\n      New connections: { $memory\\mem_2$rdmux[0][1][1]$a$15878 [7] $memory\\mem_2$rdmux[0][1][1]$a$15878 [5] } = { $memory\\mem_2$rdmux[0][1][1]$a$15878 [6] $memory\\mem_2$rdmux[0][1][1]$a$15878 [4] }\n  Optimizing cells in module \\top.\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][1][0]$15874:\n      Old ports: A=$memory\\mem_2$rdmux[0][1][0]$a$15875, B=$memory\\mem_2$rdmux[0][1][0]$b$15876, Y=$memory\\mem_2$rdmux[0][0][0]$a$15872\n      New ports: A=$memory\\mem_2$rdmux[0][1][0]$a$15875 [6:0], B=$memory\\mem_2$rdmux[0][1][0]$b$15876 [6:0], Y=$memory\\mem_2$rdmux[0][0][0]$a$15872 [6:0]\n      New connections: $memory\\mem_2$rdmux[0][0][0]$a$15872 [7] = 1'0\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][1][1]$15877:\n      Old ports: A=$memory\\mem_2$rdmux[0][1][1]$a$15878, B=8'xxxxxxxx, Y=$memory\\mem_2$rdmux[0][0][0]$b$15873\n      New ports: A={ $memory\\mem_2$rdmux[0][1][1]$a$15878 [6] $memory\\mem_2$rdmux[0][1][1]$a$15878 [4:0] }, B=6'xxxxxx, Y={ $memory\\mem_2$rdmux[0][0][0]$b$15873 [6] $memory\\mem_2$rdmux[0][0][0]$b$15873 [4:0] }\n      New connections: { $memory\\mem_2$rdmux[0][0][0]$b$15873 [7] $memory\\mem_2$rdmux[0][0][0]$b$15873 [5] } = { $memory\\mem_2$rdmux[0][0][0]$b$15873 [6] $memory\\mem_2$rdmux[0][0][0]$b$15873 [4] }\n  Optimizing cells in module \\top.\nPerformed a total of 42 changes.\n\n4.33.12. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\n<suppressed ~45 debug messages>\nRemoved a total of 15 cells.\n\n4.33.13. Executing OPT_DFF pass (perform DFF optimizations).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$14069 ($dffe) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$14069 ($dffe) from module top.\nAdding SRST signal on $auto$opt_dff.cc:764:run$14064 ($dffe) from module top (D = \\VexRiscv._zz_134_ [1:0], Q = \\VexRiscv._zz_141_ [1:0], rval = 2'00).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$13371 ($dffe) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$13371 ($dffe) from module top.\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$13056 ($sdff) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$13056 ($sdff) from module top.\nSetting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$13056 ($sdff) from module top.\nSetting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$13056 ($sdff) from module top.\nSetting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$13056 ($sdff) from module top.\nSetting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$13056 ($sdff) from module top.\nSetting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$13056 ($sdff) from module top.\nSetting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$13056 ($sdff) from module top.\nSetting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$13056 ($sdff) from module top.\nSetting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$13056 ($sdff) from module top.\n\n4.33.14. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 1 unused cells and 17 unused wires.\n<suppressed ~2 debug messages>\n\n4.33.15. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~2 debug messages>\n\n4.33.16. Rerunning OPT passes. (Maybe there is more to do..)\n\n4.33.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~506 debug messages>\n\n4.33.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\n    Consolidated identical input bits for $mux cell $flatten\\VexRiscv.$ternary$/home/pi/oss/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v:4953$2952:\n      Old ports: A={ \\VexRiscv.dataCache_1_.stageB_mmuRsp_physicalAddress [31:5] \\VexRiscv.dataCache_1__io_mem_cmd_payload_address [4:2] 2'00 }, B={ \\VexRiscv._zz_134_ [31:2] 2'00 }, Y=\\VexRiscv.dataCache_1__io_mem_cmd_s2mPipe_payload_address\n      New ports: A={ \\VexRiscv.dataCache_1_.stageB_mmuRsp_physicalAddress [31:5] \\VexRiscv.dataCache_1__io_mem_cmd_payload_address [4:2] }, B=\\VexRiscv._zz_134_ [31:2], Y=\\VexRiscv.dataCache_1__io_mem_cmd_s2mPipe_payload_address [31:2]\n      New connections: \\VexRiscv.dataCache_1__io_mem_cmd_s2mPipe_payload_address [1:0] = 2'00\n    Consolidated identical input bits for $mux cell $memory\\mem_2$rdmux[0][4][0]$15916:\n      Old ports: A={ $memory\\mem_2$rdmux[0][4][0]$a$15917 [5] 2'01 $memory\\mem_2$rdmux[0][4][0]$a$15917 [2] $memory\\mem_2$rdmux[0][4][0]$a$15917 [5] }, B={ 1'1 $memory\\mem_2$rdmux[0][4][0]$a$15917 [2] 2'01 $memory\\mem_2$rdmux[0][4][0]$a$15917 [5] }, Y={ $memory\\mem_2$rdmux[0][3][0]$a$15893 [5:2] $memory\\mem_2$rdmux[0][3][0]$a$15893 [0] }\n      New ports: A={ $memory\\mem_2$rdmux[0][4][0]$a$15917 [5] 2'01 $memory\\mem_2$rdmux[0][4][0]$a$15917 [2] }, B={ 1'1 $memory\\mem_2$rdmux[0][4][0]$a$15917 [2] 2'01 }, Y=$memory\\mem_2$rdmux[0][3][0]$a$15893 [5:2]\n      New connections: $memory\\mem_2$rdmux[0][3][0]$a$15893 [0] = $memory\\mem_2$rdmux[0][4][0]$a$15917 [5]\n  Optimizing cells in module \\top.\nPerformed a total of 2 changes.\n\n4.33.19. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.33.20. Executing OPT_DFF pass (perform DFF optimizations).\nSetting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$13375 ($dffe) from module top.\nSetting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$13375 ($dffe) from module top.\n\n4.33.21. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.33.22. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.33.23. Rerunning OPT passes. (Maybe there is more to do..)\n\n4.33.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\top..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~506 debug messages>\n\n4.33.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\top.\nPerformed a total of 0 changes.\n\n4.33.26. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\nRemoved a total of 0 cells.\n\n4.33.27. Executing OPT_DFF pass (perform DFF optimizations).\n\n4.33.28. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.33.29. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n\n4.33.30. Finished OPT passes. (There is nothing left to do.)\n\n4.34. Executing TECHMAP pass (map to technology primitives).\n\n4.34.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v\nParsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.\nGenerating RTLIL representation for module `\\_90_simplemap_bool_ops'.\nGenerating RTLIL representation for module `\\_90_simplemap_reduce_ops'.\nGenerating RTLIL representation for module `\\_90_simplemap_logic_ops'.\nGenerating RTLIL representation for module `\\_90_simplemap_compare_ops'.\nGenerating RTLIL representation for module `\\_90_simplemap_various'.\nGenerating RTLIL representation for module `\\_90_simplemap_registers'.\nGenerating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.\nGenerating RTLIL representation for module `\\_90_shift_shiftx'.\nGenerating RTLIL representation for module `\\_90_fa'.\nGenerating RTLIL representation for module `\\_90_lcu'.\nGenerating RTLIL representation for module `\\_90_alu'.\nGenerating RTLIL representation for module `\\_90_macc'.\nGenerating RTLIL representation for module `\\_90_alumacc'.\nGenerating RTLIL representation for module `\\$__div_mod_u'.\nGenerating RTLIL representation for module `\\$__div_mod_trunc'.\nGenerating RTLIL representation for module `\\_90_div'.\nGenerating RTLIL representation for module `\\_90_mod'.\nGenerating RTLIL representation for module `\\$__div_mod_floor'.\nGenerating RTLIL representation for module `\\_90_divfloor'.\nGenerating RTLIL representation for module `\\_90_modfloor'.\nGenerating RTLIL representation for module `\\_90_pow'.\nGenerating RTLIL representation for module `\\_90_pmux'.\nGenerating RTLIL representation for module `\\_90_lut'.\nSuccessfully finished Verilog frontend.\n\n4.34.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/arith_map.v\nParsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/arith_map.v' to AST representation.\nGenerating RTLIL representation for module `\\_80_ecp5_alu'.\nSuccessfully finished Verilog frontend.\n\n4.34.3. Continuing TECHMAP pass.\nUsing extmapper simplemap for cells of type $mux.\nUsing extmapper simplemap for cells of type $reduce_bool.\nUsing extmapper simplemap for cells of type $reduce_or.\nUsing extmapper simplemap for cells of type $sdff.\nUsing extmapper simplemap for cells of type $reduce_and.\nUsing extmapper simplemap for cells of type $sdffe.\nUsing extmapper simplemap for cells of type $dff.\nUsing extmapper simplemap for cells of type $eq.\nUsing template $paramod\\_90_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=2\\B_WIDTH=2\\Y_WIDTH=2 for cells of type $alu.\nUsing extmapper simplemap for cells of type $and.\nUsing extmapper simplemap for cells of type $ne.\nUsing extmapper simplemap for cells of type $not.\nUsing extmapper simplemap for cells of type $or.\nUsing extmapper simplemap for cells of type $logic_not.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=5\\B_WIDTH=1\\Y_WIDTH=5 for cells of type $alu.\nUsing template $paramod\\_90_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=1\\B_WIDTH=3\\Y_WIDTH=3 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=16\\B_WIDTH=1\\Y_WIDTH=16 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=8\\B_WIDTH=1\\Y_WIDTH=8 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=1\\B_WIDTH=32\\Y_WIDTH=32 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=1\\B_WIDTH=64\\Y_WIDTH=64 for cells of type $alu.\nUsing template $paramod\\_90_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=1\\B_WIDTH=4\\Y_WIDTH=4 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=32\\B_WIDTH=32\\Y_WIDTH=33 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=1\\B_WIDTH=5\\Y_WIDTH=5 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=32\\B_WIDTH=1\\Y_WIDTH=32 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=9\\B_WIDTH=1\\Y_WIDTH=9 for cells of type $alu.\nUsing extmapper simplemap for cells of type $sdffce.\nUsing template $paramod\\_90_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=1\\B_WIDTH=1\\Y_WIDTH=1 for cells of type $alu.\nUsing template $paramod\\_90_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=4\\B_WIDTH=1\\Y_WIDTH=4 for cells of type $alu.\nUsing template $paramod\\_90_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=2\\B_WIDTH=1\\Y_WIDTH=2 for cells of type $alu.\nUsing template $paramod\\_90_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=3\\B_WIDTH=1\\Y_WIDTH=3 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=1\\B_WIDTH=16\\Y_WIDTH=16 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=15\\B_WIDTH=1\\Y_WIDTH=16 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=20\\B_WIDTH=1\\Y_WIDTH=20 for cells of type $alu.\nUsing template $paramod\\_90_pmux\\WIDTH=8\\S_WIDTH=3 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=8\\S_WIDTH=7 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=8\\S_WIDTH=17 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=8\\S_WIDTH=9 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=8\\S_WIDTH=16 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=1\\S_WIDTH=2 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=2\\S_WIDTH=3 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=1\\S_WIDTH=7 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=13\\S_WIDTH=3 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=13\\S_WIDTH=2 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=1\\S_WIDTH=3 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=2\\S_WIDTH=2 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=16\\S_WIDTH=7 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=32\\S_WIDTH=3 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=3\\S_WIDTH=4 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=3\\S_WIDTH=2 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=9\\S_WIDTH=4 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=5\\S_WIDTH=4 for cells of type $pmux.\nUsing extmapper simplemap for cells of type $dffe.\nUsing extmapper maccmap for cells of type $macc.\n  add \\VexRiscv.dataCache_1_.stageB_request_data (32 bits, signed)\n  add { 1'0 \\VexRiscv.dataCache_1_.stageB_request_amoCtrl_alu [2] } (2 bits, signed)\n  add \\VexRiscv.dataCache_1_._zz_28_ (32 bits, signed)\n  packed 1 (1) bits / 1 words into adder tree\nUsing extmapper simplemap for cells of type $logic_and.\nUsing extmapper simplemap for cells of type $logic_or.\n  add { 1'0 \\VexRiscv.execute_to_memory_MUL_LL } (33 bits, signed)\n  add { \\VexRiscv.execute_to_memory_MUL_HL 16'0000000000000000 } (50 bits, signed)\n  add { \\VexRiscv.execute_to_memory_MUL_LH 16'0000000000000000 } (50 bits, signed)\nUsing template $paramod$constmap:6e3026a439ed4a6e7983ca0e910890cc59b2f7b2$paramod$4953c9d565c18659745e06f13317fd2eea31522c\\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.\nUsing extmapper simplemap for cells of type $xor.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=1\\B_WIDTH=7\\Y_WIDTH=7 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=22\\B_WIDTH=1\\Y_WIDTH=22 for cells of type $alu.\nUsing template $paramod\\_90_pmux\\WIDTH=32\\S_WIDTH=4 for cells of type $pmux.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=64\\B_WIDTH=64\\Y_WIDTH=64 for cells of type $alu.\nUsing extmapper simplemap for cells of type $lut.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=1\\B_WIDTH=8\\Y_WIDTH=8 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=30\\B_WIDTH=30\\Y_WIDTH=30 for cells of type $alu.\nUsing template $paramod\\_90_pmux\\WIDTH=10\\S_WIDTH=3 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=32\\S_WIDTH=2 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=24\\S_WIDTH=2 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=1\\S_WIDTH=12 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=5\\S_WIDTH=9 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=1\\S_WIDTH=11 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=1\\S_WIDTH=13 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=1\\S_WIDTH=10 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=1\\S_WIDTH=18 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=1\\S_WIDTH=15 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=4\\S_WIDTH=10 for cells of type $pmux.\nUsing template $paramod\\_90_pmux\\WIDTH=6\\S_WIDTH=10 for cells of type $pmux.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=1\\B_WIDTH=6\\Y_WIDTH=6 for cells of type $alu.\n  add \\VexRiscv._zz_401_ (32 bits, signed)\n  add { 1'0 \\VexRiscv.decode_to_execute_SRC_USE_SUB_LESS } (2 bits, signed)\n  add \\VexRiscv._zz_402_ (32 bits, signed)\n  packed 1 (1) bits / 1 words into adder tree\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=1\\B_SIGNED=1\\A_WIDTH=20\\B_WIDTH=32\\Y_WIDTH=32 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=32\\B_WIDTH=32\\Y_WIDTH=32 for cells of type $alu.\nUsing template $paramod\\_90_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=1\\B_WIDTH=2\\Y_WIDTH=2 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=1\\B_WIDTH=30\\Y_WIDTH=30 for cells of type $alu.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=33\\B_WIDTH=32\\Y_WIDTH=33 for cells of type $alu.\nUsing template $paramod$constmap:87f69c0bea22f84de4bcd0314b57cb19e61b5eb7$paramod$88abf4b792300efa328894e6936be740fdc22f6d\\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.\nUsing extmapper simplemap for cells of type $pos.\nUsing template $paramod\\_90_fa\\WIDTH=52 for cells of type $fa.\nUsing template $paramod\\_80_ecp5_alu\\A_SIGNED=0\\B_SIGNED=0\\A_WIDTH=52\\B_WIDTH=52\\Y_WIDTH=52 for cells of type $alu.\nUsing template $paramod\\_90_lcu\\WIDTH=4 for cells of type $lcu.\nUsing template $paramod\\_90_lcu\\WIDTH=2 for cells of type $lcu.\nUsing template $paramod\\_90_lcu\\WIDTH=3 for cells of type $lcu.\nUsing template $paramod\\_90_lcu\\WIDTH=1 for cells of type $lcu.\nNo more expansions possible.\n<suppressed ~9161 debug messages>\n\n4.35. Executing OPT pass (performing simple optimizations).\n\n4.35.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~6580 debug messages>\n\n4.35.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\top'.\n<suppressed ~5931 debug messages>\nRemoved a total of 1977 cells.\n\n4.35.3. Executing OPT_DFF pass (perform DFF optimizations).\n\n4.35.4. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 1946 unused cells and 9522 unused wires.\n<suppressed ~1952 debug messages>\n\n4.35.5. Finished fast OPT passes.\n\n4.36. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\n\n4.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n\n4.38. Executing TECHMAP pass (map to technology primitives).\n\n4.38.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v\nParsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.\nGenerating RTLIL representation for module `\\$_DFF_N_'.\nGenerating RTLIL representation for module `\\$_DFF_P_'.\nGenerating RTLIL representation for module `\\$_DFFE_NN_'.\nGenerating RTLIL representation for module `\\$_DFFE_PN_'.\nGenerating RTLIL representation for module `\\$_DFFE_NP_'.\nGenerating RTLIL representation for module `\\$_DFFE_PP_'.\nGenerating RTLIL representation for module `\\$_DFF_NP0_'.\nGenerating RTLIL representation for module `\\$_DFF_NP1_'.\nGenerating RTLIL representation for module `\\$_DFF_PP0_'.\nGenerating RTLIL representation for module `\\$_DFF_PP1_'.\nGenerating RTLIL representation for module `\\$_SDFF_NP0_'.\nGenerating RTLIL representation for module `\\$_SDFF_NP1_'.\nGenerating RTLIL representation for module `\\$_SDFF_PP0_'.\nGenerating RTLIL representation for module `\\$_SDFF_PP1_'.\nGenerating RTLIL representation for module `\\$_DFFE_NP0P_'.\nGenerating RTLIL representation for module `\\$_DFFE_NP1P_'.\nGenerating RTLIL representation for module `\\$_DFFE_PP0P_'.\nGenerating RTLIL representation for module `\\$_DFFE_PP1P_'.\nGenerating RTLIL representation for module `\\$_DFFE_NP0N_'.\nGenerating RTLIL representation for module `\\$_DFFE_NP1N_'.\nGenerating RTLIL representation for module `\\$_DFFE_PP0N_'.\nGenerating RTLIL representation for module `\\$_DFFE_PP1N_'.\nGenerating RTLIL representation for module `\\$_SDFFE_NP0P_'.\nGenerating RTLIL representation for module `\\$_SDFFE_NP1P_'.\nGenerating RTLIL representation for module `\\$_SDFFE_PP0P_'.\nGenerating RTLIL representation for module `\\$_SDFFE_PP1P_'.\nGenerating RTLIL representation for module `\\$_SDFFE_NP0N_'.\nGenerating RTLIL representation for module `\\$_SDFFE_NP1N_'.\nGenerating RTLIL representation for module `\\$_SDFFE_PP0N_'.\nGenerating RTLIL representation for module `\\$_SDFFE_PP1N_'.\nGenerating RTLIL representation for module `\\FD1P3AX'.\nGenerating RTLIL representation for module `\\FD1P3AY'.\nGenerating RTLIL representation for module `\\FD1P3BX'.\nGenerating RTLIL representation for module `\\FD1P3DX'.\nGenerating RTLIL representation for module `\\FD1P3IX'.\nGenerating RTLIL representation for module `\\FD1P3JX'.\nGenerating RTLIL representation for module `\\FD1S3AX'.\nGenerating RTLIL representation for module `\\FD1S3AY'.\nGenerating RTLIL representation for module `\\FD1S3BX'.\nGenerating RTLIL representation for module `\\FD1S3DX'.\nGenerating RTLIL representation for module `\\FD1S3IX'.\nGenerating RTLIL representation for module `\\FD1S3JX'.\nGenerating RTLIL representation for module `\\IFS1P3BX'.\nGenerating RTLIL representation for module `\\IFS1P3DX'.\nGenerating RTLIL representation for module `\\IFS1P3IX'.\nGenerating RTLIL representation for module `\\IFS1P3JX'.\nGenerating RTLIL representation for module `\\OFS1P3BX'.\nGenerating RTLIL representation for module `\\OFS1P3DX'.\nGenerating RTLIL representation for module `\\OFS1P3IX'.\nGenerating RTLIL representation for module `\\OFS1P3JX'.\nGenerating RTLIL representation for module `\\IB'.\nGenerating RTLIL representation for module `\\IBPU'.\nGenerating RTLIL representation for module `\\IBPD'.\nGenerating RTLIL representation for module `\\OB'.\nGenerating RTLIL representation for module `\\OBZ'.\nGenerating RTLIL representation for module `\\OBZPU'.\nGenerating RTLIL representation for module `\\OBZPD'.\nGenerating RTLIL representation for module `\\OBCO'.\nGenerating RTLIL representation for module `\\BB'.\nGenerating RTLIL representation for module `\\BBPU'.\nGenerating RTLIL representation for module `\\BBPD'.\nGenerating RTLIL representation for module `\\ILVDS'.\nGenerating RTLIL representation for module `\\OLVDS'.\nSuccessfully finished Verilog frontend.\n\n4.38.2. Continuing TECHMAP pass.\nUsing template FD1S3BX for cells of type FD1S3BX.\nUsing template IFS1P3BX for cells of type IFS1P3BX.\nUsing template OFS1P3BX for cells of type OFS1P3BX.\nUsing template \\$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.\nUsing template $paramod\\$_DFFE_PP_\\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.\nUsing template $paramod\\$_DFFE_PN_\\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PN_.\nUsing template \\$_SDFF_PP0_ for cells of type $_SDFF_PP0_.\nUsing template $paramod\\$_DFF_P_\\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.\nUsing template \\$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.\nUsing template \\$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.\nUsing template $paramod\\$_DFFE_PP_\\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.\nUsing template $paramod\\$_DFF_P_\\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.\nUsing template \\$_SDFF_PP1_ for cells of type $_SDFF_PP1_.\nUsing template $paramod\\$_DFFE_PN_\\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.\nUsing template $paramod\\$_DFF_P_\\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFF_P_.\nNo more expansions possible.\n<suppressed ~3956 debug messages>\n\n4.39. Executing OPT_EXPR pass (perform const folding).\nOptimizing module top.\n<suppressed ~82 debug messages>\n\n4.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).\n\n4.41. Executing ECP5_GSR pass (implement FF init values).\nHandling GSR in top.\n\n4.42. Executing ATTRMVCP pass (move or copy attributes).\n\n4.43. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\top..\nRemoved 0 unused cells and 19976 unused wires.\n<suppressed ~1 debug messages>\n\n4.44. Executing TECHMAP pass (map to technology primitives).\n\n4.44.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/latches_map.v\nParsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/latches_map.v' to AST representation.\nGenerating RTLIL representation for module `\\$_DLATCH_N_'.\nGenerating RTLIL representation for module `\\$_DLATCH_P_'.\nSuccessfully finished Verilog frontend.\n\n4.44.2. Continuing TECHMAP pass.\nNo more expansions possible.\n<suppressed ~4 debug messages>\n\n4.45. Executing ABC pass (technology mapping using ABC).\n\n4.45.1. Extracting gate netlist of module `\\top' to `<abc-temp-dir>/input.blif'..\nExtracted 13347 gates and 17599 wires to a netlist network with 4250 inputs and 2344 outputs.\n\n4.45.1.1. Executing ABC.\nRunning ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\nABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\nABC: \nABC: + read_blif <abc-temp-dir>/input.blif \nABC: + read_lut <abc-temp-dir>/lutdefs.txt \nABC: + strash \nABC: + ifraig \nABC: + scorr \nABC: Warning: The network is combinational (run \"fraig\" or \"fraig_sweep\").\nABC: + dc2 \nABC: + dretime \nABC: + strash \nABC: + dch -f \nABC: + if \nABC: + mfs2 \nABC: Currently \"mfs\" cannot process the network containing nodes with more than 6 fanins.\nABC: + dress \nABC: Total number of equiv classes                =    3320.\nABC: Participating nodes from both networks       =    7366.\nABC: Participating nodes from the first network   =    3443. (  63.88 % of nodes)\nABC: Participating nodes from the second network  =    3923. (  72.78 % of nodes)\nABC: Node pairs (any polarity)                    =    3443. (  63.88 % of names can be moved)\nABC: Node pairs (same polarity)                   =    2801. (  51.97 % of names can be moved)\nABC: Total runtime =     2.50 sec\nABC: + write_blif <abc-temp-dir>/output.blif \n\n4.45.1.2. Re-integrating ABC results.\nABC RESULTS:              $lut cells:     5387\nABC RESULTS:        internal signals:    11005\nABC RESULTS:           input signals:     4250\nABC RESULTS:          output signals:     2344\nRemoving temp directory.\nRemoved 0 unused cells and 10030 unused wires.\n\n4.46. Executing TECHMAP pass (map to technology primitives).\n\n4.46.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v\nParsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.\nGenerating RTLIL representation for module `\\$_DFF_N_'.\nGenerating RTLIL representation for module `\\$_DFF_P_'.\nGenerating RTLIL representation for module `\\$_DFFE_NN_'.\nGenerating RTLIL representation for module `\\$_DFFE_PN_'.\nGenerating RTLIL representation for module `\\$_DFFE_NP_'.\nGenerating RTLIL representation for module `\\$_DFFE_PP_'.\nGenerating RTLIL representation for module `\\$_DFF_NP0_'.\nGenerating RTLIL representation for module `\\$_DFF_NP1_'.\nGenerating RTLIL representation for module `\\$_DFF_PP0_'.\nGenerating RTLIL representation for module `\\$_DFF_PP1_'.\nGenerating RTLIL representation for module `\\$_SDFF_NP0_'.\nGenerating RTLIL representation for module `\\$_SDFF_NP1_'.\nGenerating RTLIL representation for module `\\$_SDFF_PP0_'.\nGenerating RTLIL representation for module `\\$_SDFF_PP1_'.\nGenerating RTLIL representation for module `\\$_DFFE_NP0P_'.\nGenerating RTLIL representation for module `\\$_DFFE_NP1P_'.\nGenerating RTLIL representation for module `\\$_DFFE_PP0P_'.\nGenerating RTLIL representation for module `\\$_DFFE_PP1P_'.\nGenerating RTLIL representation for module `\\$_DFFE_NP0N_'.\nGenerating RTLIL representation for module `\\$_DFFE_NP1N_'.\nGenerating RTLIL representation for module `\\$_DFFE_PP0N_'.\nGenerating RTLIL representation for module `\\$_DFFE_PP1N_'.\nGenerating RTLIL representation for module `\\$_SDFFE_NP0P_'.\nGenerating RTLIL representation for module `\\$_SDFFE_NP1P_'.\nGenerating RTLIL representation for module `\\$_SDFFE_PP0P_'.\nGenerating RTLIL representation for module `\\$_SDFFE_PP1P_'.\nGenerating RTLIL representation for module `\\$_SDFFE_NP0N_'.\nGenerating RTLIL representation for module `\\$_SDFFE_NP1N_'.\nGenerating RTLIL representation for module `\\$_SDFFE_PP0N_'.\nGenerating RTLIL representation for module `\\$_SDFFE_PP1N_'.\nGenerating RTLIL representation for module `\\FD1P3AX'.\nGenerating RTLIL representation for module `\\FD1P3AY'.\nGenerating RTLIL representation for module `\\FD1P3BX'.\nGenerating RTLIL representation for module `\\FD1P3DX'.\nGenerating RTLIL representation for module `\\FD1P3IX'.\nGenerating RTLIL representation for module `\\FD1P3JX'.\nGenerating RTLIL representation for module `\\FD1S3AX'.\nGenerating RTLIL representation for module `\\FD1S3AY'.\nGenerating RTLIL representation for module `\\FD1S3BX'.\nGenerating RTLIL representation for module `\\FD1S3DX'.\nGenerating RTLIL representation for module `\\FD1S3IX'.\nGenerating RTLIL representation for module `\\FD1S3JX'.\nGenerating RTLIL representation for module `\\IFS1P3BX'.\nGenerating RTLIL representation for module `\\IFS1P3DX'.\nGenerating RTLIL representation for module `\\IFS1P3IX'.\nGenerating RTLIL representation for module `\\IFS1P3JX'.\nGenerating RTLIL representation for module `\\OFS1P3BX'.\nGenerating RTLIL representation for module `\\OFS1P3DX'.\nGenerating RTLIL representation for module `\\OFS1P3IX'.\nGenerating RTLIL representation for module `\\OFS1P3JX'.\nGenerating RTLIL representation for module `\\IB'.\nGenerating RTLIL representation for module `\\IBPU'.\nGenerating RTLIL representation for module `\\IBPD'.\nGenerating RTLIL representation for module `\\OB'.\nGenerating RTLIL representation for module `\\OBZ'.\nGenerating RTLIL representation for module `\\OBZPU'.\nGenerating RTLIL representation for module `\\OBZPD'.\nGenerating RTLIL representation for module `\\OBCO'.\nGenerating RTLIL representation for module `\\BB'.\nGenerating RTLIL representation for module `\\BBPU'.\nGenerating RTLIL representation for module `\\BBPD'.\nGenerating RTLIL representation for module `\\ILVDS'.\nGenerating RTLIL representation for module `\\OLVDS'.\nGenerating RTLIL representation for module `\\$lut'.\nSuccessfully finished Verilog frontend.\n\n4.46.2. Continuing TECHMAP pass.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111111111111110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=2\\LUT=4'0001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'00000001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=2\\LUT=4'1011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'10101100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=2\\LUT=4'1000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1010110000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=65279 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0001000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000000000001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=16777216 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111110111111110000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'00000111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'10000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11101111000000000000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=2\\LUT=4'0100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'01000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000000011111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=234881024 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'01111000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=2\\LUT=4'0110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=11193584 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000101000001100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1010000000001100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'00110101 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1100111100001010 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'11001010 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000001100000101 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0011010100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000111100010001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'10010110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=2\\LUT=4'1001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0100000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000011101110111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'01110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1000111100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=1\\LUT=2'01 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=861212671 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0001000011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'01010011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1429409791 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0111011100001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'00010000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111010101010011001100001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1000000011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'11000101 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'00001110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=252693674 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'00111010 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000101000000011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'11101000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0111111110000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1429467376 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1906311167 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1100111011100000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1438662485 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'00010100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111111111111111111111111000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111100011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=125239296 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0111000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=2\\LUT=4'0111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000000001011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000110011100000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10111111101111110000000010111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=53452 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000111000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000111110111011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1110111100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'00001011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=57103 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000000000111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=866840816 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'00001101 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0011010101010011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110001111100010000000011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110000111100000011001101010101 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000011111110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110000111100001100110010101010 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1011000010111011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1001000000001001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'10110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111010000001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1110000100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1001000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1101000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=268435456 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111000011101110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=2147418112 for cells of type $lut.\nUsing template $paramod$6241fa3e5fa8d57b087a5d779d84dffa6ea27828\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'10010000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10000000000000000000000000000000 for cells of type $lut.\nUsing template $paramod$b1ab02b6d7b4a1d589d377b09bec30a2b2c62af9\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1011000000001011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11010000000000000000000000000000 for cells of type $lut.\nUsing template $paramod$c7a7d23abbb477e83fd9c5f925e1194205e0200e\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1011000000000000 for cells of type $lut.\nUsing template $paramod$f2cc8492cfd8058506ca681e889e3139ac9bdb7f\\$lut for cells of type $lut.\nUsing template $paramod$aa446779a3087d39dd4cd79a0d522cc75090ac62\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1073741824 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0100010011110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=252654421 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000011100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'10111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111000001110111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'01111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000011110100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0100111100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000110000001010 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000110100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1011111101000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=2\\LUT=4'1110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111110000101001111111101000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=251 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'01001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11010000000011010000000000000000 for cells of type $lut.\nUsing template $paramod$3dd1cfeaac2399e8e1df42382a37ba2eafacb216\\$lut for cells of type $lut.\nUsing template $paramod$3f90aed0d8eb548f602005ffe2ca4ddb51e8f26a\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10110000000010110000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111110001111111111111101001010 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0101110000000000 for cells of type $lut.\nUsing template $paramod$5cea99b479a5e94263e7feab8f12d9efb8eebb68\\$lut for cells of type $lut.\nUsing template $paramod$f78689128b22f4dca36b8e3adbad7168cdba8784\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000001111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10010000000010010000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10110000000000000000000000000000 for cells of type $lut.\nUsing template $paramod$f8bdca125e424c8e9c5f5e84960e0e034e7c473c\\$lut for cells of type $lut.\nUsing template $paramod$50ddde3c53ed9f3a904830da716060dc2a4a6794\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'11010000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=218103808 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=184549387 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1611284429 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0101001100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=805306367 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111010000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=65536 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0001111111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=7 for cells of type $lut.\nUsing template $paramod$1929d44748517239e36a599c0facfb62ddb99607\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0010101100100010 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1110000000000000 for cells of type $lut.\nUsing template $paramod$4623a96babc0fb9d0dd6b1878a40933c5488119e\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'11100000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000011101111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=11599856 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000000001110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111111110110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111100110010001111111111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000010111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0001000000000001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1011101110110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1618477048 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0100000100000000 for cells of type $lut.\nUsing template $paramod$8fe2ebad1feba325f96d63263e14cfcbdc4b0421\\$lut for cells of type $lut.\nUsing template $paramod$5547587bde2f1ca8d884d89fe5b90567ab8bb30e\\$lut for cells of type $lut.\nUsing template $paramod$5fba6fa4affd3d8cb90b92595f737467c857f3c8\\$lut for cells of type $lut.\nUsing template $paramod$e10ca4aca4e4c8627be5bb912095a9253494b061\\$lut for cells of type $lut.\nUsing template $paramod$6e4e41657a70f7188049c87aa81ca2df3d479a9f\\$lut for cells of type $lut.\nUsing template $paramod$01de5b25c9605395c5c293f0e6a105e4eabbd154\\$lut for cells of type $lut.\nUsing template $paramod$a3da6745c5c369438a7754a834b174016720be2d\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10001111000000000000000000000000 for cells of type $lut.\nUsing template $paramod$305ef200f2c199f2d21f47ca6eddb0b35f944ea3\\$lut for cells of type $lut.\nUsing template $paramod$e4410f6068ac195e7117d07a11f0b8cdeea2c9e5\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0110111111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=24527 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111111110101100111111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'11101011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111100000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111111111111111111111111110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111111111101111111111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10101010110011001111000011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111100000000000000000000000 for cells of type $lut.\nUsing template $paramod$68bce9973fad834e383d298cea29cf1d88c767d4\\$lut for cells of type $lut.\nUsing template $paramod$c614a6037ff5e3bd91eb090d0bc47ed503ea34bf\\$lut for cells of type $lut.\nUsing template $paramod$4d83f945ff11bb3e47ac1f4a1cecabb1e1192f01\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000010001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000101110111011 for cells of type $lut.\nUsing template $paramod$4bc18ab29081ac9de33990d134f0fc57d437a5b9\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111110101001111001000111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0101001110101100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1010110001010011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1011101100001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110011000000001111010111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111101011001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=143 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'11101111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111000001000100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=4460288 for cells of type $lut.\nUsing template $paramod$50cdf14cdecda7c7e34d569928f5004293af93b8\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0001111100010001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1886912511 for cells of type $lut.\nUsing template $paramod$becad630673be44c4d16e3360f816e9223d9cbcf\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000000001101 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11101111111111110000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=65423 for cells of type $lut.\nUsing template $paramod$ecd267f563a33374e8db574aacb7bf6428d7e297\\$lut for cells of type $lut.\nUsing template $paramod$898e48637bc4b974fd02ac07b81fd0d72f50e9da\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0111011101110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000100010000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0011110001011010 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=357913940 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=285212671 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1011111111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'11111000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'11111110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'10001111 for cells of type $lut.\nUsing template $paramod$84ae49d5974e27ed78140b3ccba055ea77a05f5f\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=11 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=50659328 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10111011000010110000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111111011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111100010001000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000001001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1011111100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0100000011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000011111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1110000011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111111111110111011101110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000101100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110000111110101111000011111100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111110011111111111111100000 for cells of type $lut.\nUsing template $paramod$d51c2b2783ae0ae911a216695a268e63487765f2\\$lut for cells of type $lut.\nUsing template $paramod$02b9e8ca5d05d74a2c377c2e4f488f4d7f7ec1fd\\$lut for cells of type $lut.\nUsing template $paramod$e22d3901d8cb6f0f9c3212e3eab1d88f3ad5612f\\$lut for cells of type $lut.\nUsing template $paramod$190c1eb6625f8032b16b3e629910dc099fd508bc\\$lut for cells of type $lut.\nUsing template $paramod$e2e74d4a24e34ee1e8ee4682783e085e84aff1be\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'01011100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1010001100000000 for cells of type $lut.\nUsing template $paramod$5da641478b14e7ad2256d36cddc5fa4ddaa50ad8\\$lut for cells of type $lut.\nUsing template $paramod$335437ca8357770e7141cf695894febc9bf11aa3\\$lut for cells of type $lut.\nUsing template $paramod$a3e0af0bd3444be7a9fbe1699810c5aa88202b82\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=218103821 for cells of type $lut.\nUsing template $paramod$a3d87b515d81b1a62643058b4ddeee7f36002591\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=268500992 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1090519040 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000010100001100 for cells of type $lut.\nUsing template $paramod$b10a866498802752e38df3e29b7faf21196ddaf2\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0101110010100011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'01100000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10101010111100001111000011001100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0101001111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111101010100011001100001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111000010111011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0111111111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10101010110011001111000011110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111111011110001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'01101111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'11100001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1739918019 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'11110100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111100010001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'01101001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11001100101010101111000011110000 for cells of type $lut.\nUsing template $paramod$57619346c001bba14f685682aaa48a843cd5a7a5\\$lut for cells of type $lut.\nUsing template $paramod$9c1fdb72bfab429eb035e50b86046f0edb412905\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110000111100001010101011001100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=259981312 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1001010001001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1806696448 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111111111110111111100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11001011000011000000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=65524 for cells of type $lut.\nUsing template $paramod$04579d5a7f7d11008d5c4dab02ae6edd004a19ac\\$lut for cells of type $lut.\nUsing template $paramod$978fde68d9b11247a3be46539b9e0e7d13edab9b\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1879048192 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1100101011111100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0111111100000000 for cells of type $lut.\nUsing template $paramod$593041bd4188997093fb78f92597731fc77bd928\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111111101110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=252663091 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1911 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111001111110101 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0011010111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110011111101010000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=252663244 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1000100000001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1100101000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=251986703 for cells of type $lut.\nUsing template $paramod$76666f44bff191e671564a6be8ce47db7409d0b8\\$lut for cells of type $lut.\nUsing template $paramod$275d4b7dd557f9880a1c9fb2b17e6b0e5a1bc217\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000111101110111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11100000000000001111000011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=255066026 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10010000000000000000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1000100011110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'10100011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111000100010000111100001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110000111101011111000011110011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10101010110011000000111100001111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=7799024 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111010111111001111000011110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1063190528 for cells of type $lut.\nUsing template $paramod$2cb6faf85742a77ecc70cb7934aab8f2374586c0\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110000111100001111111110001000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=252641399 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111000000001111100011111000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110000111100001010101000110011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10101010110011001111111111110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0101000000000011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=267321344 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11001111110011110000000010001010 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=63743 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0111000011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=47883 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111010001000100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111111111111000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111000000001110111111101111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=16744319 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1010110011001100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0011111101010000 for cells of type $lut.\nUsing template $paramod$d86957ebe1bb9ca515f523aa958649e2723664a9\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111111111110000011101110111 for cells of type $lut.\nUsing template $paramod$c731a3e322df28554ad1a6bf78a4b11a42a31c7e\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111111110000000 for cells of type $lut.\nUsing template $paramod$757292a7295756f9722b03a98e9457973f8eb505\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=268400384 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110100111101000000000011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000111101000100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111000000010001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=252684851 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000011111000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111111111110100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000000011110001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0011001100111010 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1000111111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1100110011001010 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1011000011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'00101100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=24383 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111111111110000001011110011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111010111110011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111000010001000 for cells of type $lut.\nUsing template $paramod$8eb77df048276dedcb8dacff952b6a11adcd51f5\\$lut for cells of type $lut.\nUsing template $paramod$1d1818d1f1b1719676dd231e382e918f6e9a16a2\\$lut for cells of type $lut.\nUsing template $paramod$7ff4b01bd30f1dbada9f4fe1d6eac8eb39b49a62\\$lut for cells of type $lut.\nUsing template $paramod$fd38c96984eb26c814acbee76ca31f3b56799839\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10000000101111111000000010000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1429470991 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0001010000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11100000111101001110111100000100 for cells of type $lut.\nUsing template $paramod$855ff89ad82822e604e1374fa366bdfab06b8fd1\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1392508928 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=84219199 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0001111100000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111111111110001000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=2147450880 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1110000111111111 for cells of type $lut.\nUsing template $paramod$a34f92a1382803f51908f04132e54ab18ee6b780\\$lut for cells of type $lut.\nUsing template $paramod$7df0a6c7a83f8c495c3947973e0fe0c90468f413\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0111100011100001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=2139160065 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=2139159553 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110000111100001111000011110111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'11110001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0111100000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1110111111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0111111100110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10101111000011000000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1342111744 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10001111100010000000000000000000 for cells of type $lut.\nUsing template $paramod$8079ce169c889d045b9ca39f082cea396fabd2d5\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111111111111111010001000100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0011010100000011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111111100001110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=15663104 for cells of type $lut.\nUsing template $paramod$cf259b608f798b47fdd7498435e4ed20d0ccc604\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111100000001111111111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111001011111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1895796480 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111000100000000 for cells of type $lut.\nUsing template $paramod$258b22cbc2b77dd674a53d92d975320b9c9adf5a\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0100111101000100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111111100010000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0001000100001111 for cells of type $lut.\nUsing template $paramod$5234f84f9a5edce2ce261a52bee20f4d450344f1\\$lut for cells of type $lut.\nUsing template $paramod$5670d49caeedffba0d3e963ca10324a7856030e2\\$lut for cells of type $lut.\nUsing template $paramod$5f664f54d0df1747ad1906c3be299d878454a5eb\\$lut for cells of type $lut.\nUsing template $paramod$78ff8ebd5f0b3cfeb5955de4d93a5313ae37aeb3\\$lut for cells of type $lut.\nUsing template $paramod$cdc33ef2d7b170c946799ccf1ee9304a2dd4e51d\\$lut for cells of type $lut.\nUsing template $paramod$3b8376d34890e9044b1e4cab1dcaf9a2297495a0\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=3967 for cells of type $lut.\nUsing template $paramod$9c59d3d5f05ce12c807b8c26edd2b7b3caf117c3\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=459000 for cells of type $lut.\nUsing template $paramod$a69058a1112c52503532f44ae40017ff569449c9\\$lut for cells of type $lut.\nUsing template $paramod$5f4374372854f9b7b92ad49646de545e25672d6b\\$lut for cells of type $lut.\nUsing template $paramod$d7dd954bfadc6b031d1f21190f2ef4ca266fffb2\\$lut for cells of type $lut.\nUsing template $paramod$5fc2231c15aee7c77d483e5a1f3eb748810c2368\\$lut for cells of type $lut.\nUsing template $paramod$7368a7edd03021f4844660f3d43bf812be80cfb8\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10001000100000001111111111110000 for cells of type $lut.\nUsing template $paramod$31a0bf18b19634f35aea5e02fea0bbe67d4e46a4\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110111111100000000000000000000 for cells of type $lut.\nUsing template $paramod$e5700c80c0ed7fb9bfa1e6e7cd7a6c440b3856aa\\$lut for cells of type $lut.\nUsing template $paramod$6ef5aff3b463a10358f4104fdc5f8d4f48a784d9\\$lut for cells of type $lut.\nUsing template $paramod$b3ac7605e8bd5ec90d402d6e365fc62fc43054ed\\$lut for cells of type $lut.\nUsing template $paramod$ca6d8a7e025cf3f7f8d51f324707a6eb4c591430\\$lut for cells of type $lut.\nUsing template $paramod$6e9d841278d1b4d1ee3a2f7bfdd7effe7c41cabe\\$lut for cells of type $lut.\nUsing template $paramod$0b0f90d5cb75cccd00ea3d436ff365e9bcd265c4\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000101100000100 for cells of type $lut.\nUsing template $paramod$55e49321004e7b2d9fc78909ab6aa39da79410ab\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11010101011111110000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=45007 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111010011111111 for cells of type $lut.\nUsing template $paramod$1b3a424ee2420dea1e49e22858b390cb487e13c6\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=3003 for cells of type $lut.\nUsing template $paramod$66a66bc26c214da26d22ad2ada8c13c4cff5f879\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111010100111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0011111111110101 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=61694 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000010100000011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000111111101110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110000111100001100110001010101 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110000111100000000000010111011 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=2139029631 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=268404991 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111000100011111000011110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11000000110010100000000011001100 for cells of type $lut.\nUsing template $paramod$1ee2a7579c6186174c99cd3ee563c80621b7120f\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'10110010 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=33488896 for cells of type $lut.\nUsing template $paramod$9fb31a77262b563371005613991df329116739f8\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=16760767 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111010001001111000011110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10101111000000000000110000001100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=4456688 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111101011111100 for cells of type $lut.\nUsing template $paramod$3e3eff717dce2fc824db03d938fa124c2f06e387\\$lut for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=655372 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110000111100001111000011111110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111111111100000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111111101000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1100110111000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10111111111111110100000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=917504 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0000111000000001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'00011100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111111111100000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1010111111111100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1100110000001110 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=3\\LUT=8'10011111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'0101000000110001 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111010001100111111111111110000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1111010111011100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111101001111111111111111111111 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=4\\LUT=16'1001010111011100 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11111111000111110000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'11110101111100110000000000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=32'10001100100011110000110000000000 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=252649676 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=50397695 for cells of type $lut.\nUsing template $paramod\\$lut\\WIDTH=5\\LUT=1566528989 for cells of type $lut.\nNo more expansions possible.\n<suppressed ~11254 debug messages>\n\n4.47. Executing OPT_LUT_INS pass (discard unused LUT inputs).\nOptimizing LUTs in top.\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59469.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59461.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56781.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59265.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59264.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59262.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58821.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58830.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58820.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58814.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58813.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58809.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58808.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58818.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58812.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58802.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58817.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58807.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58796.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58806.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58784.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58795.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58785.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58791.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58789.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58779.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58793.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58778.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58788.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58777.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58773.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58787.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58772.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58782.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58771.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58766.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58756.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58756.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58751.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58744.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58769.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58732.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58731.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58736.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58725.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58721.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58735.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58720.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58730.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58719.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58718.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58644.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58614.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58614.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58614.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58603.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58561.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58438.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58345.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58296.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58281.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58281.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58189.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58588.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58588.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58180.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58164.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58165.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58155.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58167.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58168.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58157.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58150.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59843.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58135.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58140.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58134.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58103.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58114.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58097.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59767.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59772.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58108.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58100.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58096.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58080.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58090.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58084.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58078.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58055.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57550.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58072.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58056.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58047.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58022.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57304.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57904.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57904.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57884.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57884.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58195.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57888.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57888.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58225.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57908.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57908.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58204.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58214.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57896.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57896.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57868.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57868.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57876.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57876.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57856.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57856.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57847.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57847.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57834.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57834.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57818.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57818.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57302.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57783.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57756.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57756.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57756.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57756.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57756.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57756.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57712.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57630.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57630.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57619.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57619.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56774.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56792.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56786.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56783.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56775.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56782.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56779.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56773.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56770.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56778.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56766.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56777.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56765.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56618.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56618.lut3 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56460.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56460.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56460.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56460.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56460.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56583.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56583.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56583.lut4 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56583.lut5 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56583.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56583.lut7 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56582.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56582.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56582.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56582.lut4 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56582.lut5 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56582.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56582.lut7 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56565.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56573.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56573.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56573.lut4 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56573.lut5 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56573.lut6 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56573.lut7 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56575.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56575.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56575.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56575.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56578.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56578.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56578.lut4 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56578.lut5 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56578.lut6 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56578.lut7 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56567.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56567.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56567.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56567.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56567.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56549.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56549.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56549.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56549.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56564.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56564.lut2 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56564.lut3 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56558.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56558.lut2 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56558.lut3 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56560.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56560.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56560.lut4 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56560.lut5 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56560.lut6 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56560.lut7 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56559.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56559.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56559.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56559.lut4 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56559.lut5 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56559.lut6 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56559.lut7 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56554.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56554.lut2 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56554.lut3 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56540.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56540.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56540.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56540.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56543.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56543.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56547.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56547.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56533.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56533.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56537.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56537.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56535.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56535.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56461.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56461.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56461.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56461.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56461.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56461.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56494.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56494.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56494.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56494.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56494.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56494.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60386.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60337.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56453.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56453.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56453.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56453.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56453.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56445.lut2 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56445.lut3 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56445.lut4 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56445.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56445.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56412.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56441.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56441.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56433.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56433.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56433.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56433.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56433.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56435.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56436.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56437.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56437.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56437.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56437.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56437.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56437.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56440.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56440.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56440.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56440.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56439.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56439.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56439.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56439.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56439.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56439.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56424.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56425.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56425.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56425.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56425.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56425.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56429.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56429.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56429.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56429.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56429.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56429.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56427.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56427.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56427.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56427.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56428.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56428.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56428.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56428.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56428.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56428.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56423.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56423.lut2 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56423.lut3 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56413.lut2 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56413.lut3 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56413.lut4 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56413.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56413.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56415.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56419.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56419.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56419.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56419.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56421.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56421.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56421.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56421.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56418.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56418.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56418.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56418.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56418.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56418.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56403.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56403.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56403.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56403.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56405.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56405.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56409.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56409.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56367.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56367.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56367.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56367.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56367.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56402.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56402.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56398.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56398.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56307.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56307.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56355.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56355.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56329.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56329.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56329.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56329.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56347.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56152.lut2 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56152.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56027.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56027.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55811.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55703.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55703.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55703.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55703.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55703.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55702.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55702.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55702.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55702.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55699.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55699.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55699.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56693.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57519.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57519.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57496.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57496.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57416.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57416.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57416.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57416.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57416.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57416.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57434.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57430.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57430.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60121.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57397.lut2 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57397.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59895.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59787.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58601.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58587.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58587.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58587.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58609.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58609.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58609.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58609.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58609.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58609.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56000.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56001.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56001.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56001.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56001.lut4 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56001.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56001.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58822.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58625.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58754.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58754.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58608.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58608.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58666.lut2 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58666.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58219.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57736.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57892.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57892.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58198.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57872.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57872.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58192.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57864.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57864.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58183.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57852.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57852.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57813.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57813.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58137.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58131.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58116.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58105.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58099.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58093.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58087.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58081.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58075.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58069.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58065.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58066.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57842.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57842.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57838.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57838.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58054.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57826.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57826.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58051.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57822.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57822.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57537.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58041.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58042.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57807.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58037.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58037.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58035.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57796.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57463.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58026.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57900.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57900.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57880.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57880.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57860.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57860.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57830.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57830.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57707.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56689.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57539.lut2 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57539.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57539.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57539.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57539.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57539.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57509.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57509.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57497.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56648.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57100.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57095.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57090.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57085.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55561.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55560.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56832.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56790.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56785.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56780.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56776.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56771.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56767.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56673.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56676.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56664.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56666.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56652.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56640.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56587.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56587.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56580.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56556.lut2 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56556.lut3 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56551.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56551.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56551.lut4 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56551.lut5 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56551.lut6 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56551.lut7 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56545.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56545.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56539.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56539.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56532.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56532.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56532.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56498.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56518.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56518.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56518.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56518.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56493.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56493.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56491.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56491.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56463.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56463.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56463.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56463.lut4 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56463.lut5 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56463.lut6 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56463.lut7 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56464.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56482.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56484.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56484.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56484.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56484.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56484.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56487.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56487.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56465.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56465.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56465.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56465.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56465.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56466.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56469.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56472.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56472.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56448.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56448.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56438.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56438.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56438.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56432.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56426.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56426.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56426.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56426.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56420.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56420.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56420.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56420.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56420.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56420.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56416.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56416.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56416.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56416.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56416.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55687.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55687.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55687.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55687.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55687.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55687.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55686.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55686.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55686.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55686.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55686.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55686.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55685.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55685.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55685.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55685.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56411.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56411.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56407.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56407.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56400.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56400.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56400.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56368.lut2 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56368.lut3 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56368.lut4 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56368.lut5 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56368.lut6 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56368.lut7 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56395.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56395.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56395.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56369.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56369.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56369.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56369.lut4 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56369.lut5 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56369.lut6 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56369.lut7 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56396.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56396.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56396.lut3 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56370.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56379.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56385.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56386.lut2 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56376.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56142.lut2 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56142.lut5 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56142.lut7 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56017.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56017.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56017.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56017.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56017.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55499.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55499.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55499.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55499.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55499.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55434.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55448.lut2 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55448.lut3 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55473.lut2 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55833.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55833.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55833.lut4 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55833.lut5 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55833.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55833.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55834.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55834.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55834.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55837.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55837.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55837.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55837.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55837.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55837.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55707.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55701.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55701.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55701.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55701.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55701.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55701.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55695.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55693.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55250.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55692.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55683.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55683.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55683.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55683.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55257.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55257.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55258.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55258.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55283.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55283.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55283.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55283.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55283.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55283.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55290.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55277.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55277.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55278.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55281.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55281.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55270.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55276.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55271.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55271.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55275.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55251.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55251.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55252.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55256.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55256.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55255.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55255.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55659.lut2 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55659.lut3 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55373.lut2 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55373.lut3 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55373.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55373.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55373.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55373.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55405.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55307.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55307.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55307.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55307.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55307.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55310.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55312.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55312.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55309.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55318.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55340.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55340.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55340.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55340.lut6 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55340.lut7 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55345.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55343.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55342.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55342.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55351.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55324.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55324.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55329.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55329.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55328.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55328.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55326.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55325.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55325.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55289.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55284.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55284.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55284.lut4 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55284.lut5 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55279.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55279.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55264.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55264.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55265.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55265.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55268.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55268.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55266.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55269.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55269.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55259.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55259.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55254.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55254.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55801.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55603.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55603.lut2 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55603.lut3 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55803.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55585.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55585.lut3 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55585.lut4 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55585.lut5 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55585.lut6 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55585.lut7 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55565.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55565.lut2 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55565.lut3 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55565.lut4 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55565.lut5 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55565.lut6 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55565.lut7 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55623.lut2 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55623.lut3 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55429.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60260.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55205.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55206.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55226.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55242.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58690.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55249.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55251.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55252.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55257.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55260.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55264.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55266.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55270.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55276.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55274.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55277.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55270.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55278.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55283.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55290.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55292.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55307.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55307.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55310.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55309.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55314.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55317.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55318.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55324.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55326.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55330.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55333.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55335.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55340.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55343.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55345.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55340.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55351.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55373.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55392.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55393.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55405.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55410.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55405.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55373.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55434.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55435.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55448.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55456.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55469.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55475.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55477.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55480.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55481.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55431.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55499.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55505.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55503.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55520.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55525.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55434.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55473.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56017.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55550.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55560.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55561.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55585.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55565.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55566.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55580.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55585.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55586.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55591.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55600.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55603.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55620.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55623.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55638.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55641.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59372.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55652.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55659.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55801.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55669.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55670.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55679.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55683.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55685.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55686.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55687.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55693.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55693.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55695.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55695.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55699.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55699.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55703.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55701.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55702.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55703.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55726.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55753.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55759.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55803.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55763.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55763.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55776.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55778.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57539.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55799.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55801.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55802.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55803.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55805.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55807.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55811.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55813.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55809.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55811.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55824.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55827.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55828.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55833.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55835.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55837.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55838.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55840.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55840.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55842.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55843.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55833.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55829.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55876.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55910.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55946.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55951.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55951.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55956.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55957.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55958.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55959.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55960.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55961.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55962.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55970.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55970.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55976.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55976.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60036.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55990.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55992.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56000.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56001.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56000.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56004.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56005.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56011.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56011.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55499.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56017.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56021.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56022.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56027.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56038.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56061.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56063.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56086.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56142.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56152.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56159.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56161.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56164.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56177.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56189.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56194.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58666.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56263.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56347.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56307.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56685.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56320.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56324.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56320.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56330.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56324.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56330.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57507.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56348.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56348.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56356.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56356.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56365.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56366.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56367.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56368.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56369.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56373.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56374.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56376.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56377.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56386.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56384.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56386.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56387.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56390.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56395.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56396.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56398.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56398.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56400.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56402.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56402.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56405.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56405.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56407.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56407.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56409.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56409.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56411.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56411.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56412.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56413.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56417.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56416.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56417.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56418.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56419.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56420.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56421.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56425.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56426.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56427.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56428.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56429.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56433.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56435.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56435.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56436.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56437.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56438.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56439.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56440.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56441.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56438.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56445.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56412.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56448.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56448.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56453.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56455.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56458.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56460.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56460.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56491.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56463.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56465.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56470.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56474.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56483.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56484.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56465.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56489.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56491.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56493.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56493.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56494.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56499.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56506.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56510.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56516.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56521.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56523.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56524.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56527.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56532.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56535.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56535.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56537.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56537.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56539.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56539.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56543.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56543.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56545.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56545.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56547.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56547.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56549.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56551.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56551.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56552.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56554.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56555.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56556.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56559.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56560.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56560.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56556.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56563.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56564.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56575.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56567.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56568.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56573.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56573.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56549.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56578.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56578.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56581.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56582.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56583.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56583.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56585.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56587.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56587.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56595.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60403.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56613.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56618.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56619.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56623.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56623.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56625.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56630.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56628.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56628.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56630.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56635.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56633.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56686.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56635.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56638.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56638.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56640.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56657.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56642.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56644.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56644.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56647.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56648.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56650.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56655.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56652.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56655.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56657.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56660.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56660.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56662.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56662.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56664.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56666.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56667.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56671.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56671.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56673.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56675.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56675.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56676.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56679.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56679.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56680.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56682.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56682.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56685.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56686.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56689.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56691.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56693.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56695.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56691.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56704.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56704.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56705.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56712.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56713.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56718.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56712.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56718.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56710.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56791.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56763.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56768.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56769.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56763.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56764.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56765.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56766.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56767.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56768.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56769.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56770.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56771.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56772.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56773.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56774.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56775.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56776.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56777.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56778.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56779.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56780.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56781.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56782.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56783.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56784.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56785.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56786.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56787.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56788.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56789.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56790.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56791.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56792.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56793.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56794.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56784.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56794.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56788.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56789.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56793.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56787.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57444.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57436.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56906.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56906.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56956.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56152.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60336.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57085.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57085.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57090.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57090.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57095.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57095.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57100.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57100.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58918.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60098.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55659.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58888.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58829.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58653.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57307.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57756.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57746.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58604.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58613.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57299.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57300.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57302.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57303.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57304.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57305.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57306.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57307.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57530.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57306.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57397.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57397.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58783.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57401.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57406.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57416.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57418.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57430.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57438.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57440.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58021.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57455.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57485.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57463.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57466.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58025.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57478.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57483.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57473.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57490.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57492.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57493.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57496.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57497.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57497.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57505.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57508.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57509.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57512.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57514.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57517.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57519.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57523.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57525.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57528.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57535.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58045.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57538.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57539.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57542.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56680.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57553.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57556.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57561.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57565.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57572.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57574.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57576.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59966.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56647.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57585.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57587.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57596.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57597.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57598.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56633.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57611.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57613.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57617.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57619.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57623.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57625.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57596.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57628.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57630.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57633.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58774.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57635.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57641.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57652.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57641.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57663.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57664.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57666.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58191.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56650.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57673.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57675.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59837.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57684.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57685.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57687.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57673.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57694.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57705.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57713.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58734.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59936.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57724.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57727.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57729.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57734.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57736.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57737.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57739.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56625.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57746.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57747.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57749.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59795.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57763.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56613.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57771.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57771.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57783.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57787.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57788.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57791.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57795.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57796.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57801.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57802.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57807.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57809.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57809.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58037.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57813.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57818.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57822.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57826.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57830.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57834.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57838.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57842.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58061.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57847.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57852.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57856.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57860.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57864.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58186.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57868.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57872.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57663.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57876.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57880.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57884.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57888.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57892.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58207.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57896.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57900.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57904.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57908.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58200.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59951.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57913.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58111.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57916.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57919.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57305.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57922.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57925.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57791.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57928.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57931.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57801.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57934.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57937.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57940.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57943.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57946.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57949.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57952.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57955.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57574.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57958.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57961.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57964.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57967.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57970.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57973.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57976.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57979.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57982.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57985.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57988.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57991.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57994.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57997.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58000.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58003.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58006.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58008.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58010.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58010.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58011.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58014.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58019.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58021.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58022.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58024.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58024.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58025.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58026.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58030.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58030.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58034.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58034.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58035.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58037.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58041.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58042.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58044.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58044.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58045.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58046.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58047.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58050.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58050.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58051.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58058.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58053.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58054.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58055.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58056.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58053.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58058.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58060.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58060.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58061.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58063.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58063.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57585.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58065.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58066.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58068.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58068.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58069.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58071.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58071.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58072.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58074.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58074.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58075.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58077.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58078.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58080.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58081.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58083.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58083.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58084.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58086.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58086.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58087.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58089.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58089.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58090.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58092.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58092.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58093.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58095.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58095.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58096.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58097.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58099.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58100.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58102.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58102.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58103.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58105.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58107.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58107.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58108.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58110.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58110.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58111.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58113.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58113.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58114.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58116.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58124.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58136.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58130.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58130.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58131.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58133.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58133.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58134.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58135.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58136.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58137.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58139.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58139.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58140.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58141.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58143.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58143.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58145.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58145.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58141.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58149.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58149.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58150.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58151.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58153.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58153.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58154.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58155.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58151.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58157.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58159.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58159.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58154.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58161.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58164.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58165.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58161.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58167.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58168.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58171.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58175.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58171.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58179.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58179.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58180.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58182.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58182.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58183.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58185.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58185.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58186.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58188.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58188.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58189.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58191.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58192.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58194.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58194.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58195.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58197.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58197.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58198.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58200.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58201.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58203.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58203.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58204.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58206.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58206.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58207.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58208.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58210.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58210.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58211.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58213.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58213.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58214.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58216.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58216.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58218.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58218.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58219.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58221.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58221.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58222.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58224.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58224.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58225.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58226.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58227.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58222.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58245.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58249.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58242.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58253.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58254.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58267.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58263.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58274.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58253.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58281.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58282.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58278.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58272.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58281.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58292.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58299.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58300.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58290.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58309.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58313.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58320.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58324.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58332.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58328.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58299.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58338.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58345.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58346.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58347.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58356.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58360.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58346.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58366.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58370.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58374.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58364.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58381.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58381.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58387.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58383.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58393.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58402.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58406.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58414.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58410.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58400.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60382.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58424.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58420.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58434.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58430.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59929.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58440.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58444.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58447.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58448.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58456.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58457.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58465.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58466.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58456.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58465.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58476.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58482.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58484.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58488.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58482.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58474.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58494.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58501.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58502.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60391.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57684.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58498.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58501.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60401.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58561.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58573.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58573.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58574.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58575.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58576.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58577.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58578.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58579.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58580.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58581.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58587.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58588.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58590.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58601.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57299.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58603.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58604.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58608.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58609.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58613.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58614.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58615.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58625.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58810.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58615.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58644.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58622.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58786.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58644.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58653.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57303.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58666.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58780.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58674.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58674.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58724.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58729.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58718.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58719.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58720.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58721.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58608.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58724.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58725.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58726.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58729.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58730.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58731.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58732.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58734.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58735.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58736.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58737.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58726.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58742.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58743.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58744.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58745.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58737.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58750.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58751.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58754.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58756.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58755.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58766.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58605.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58768.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58769.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58770.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58771.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58772.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58773.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58774.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58775.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58776.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58777.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58778.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58779.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58780.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58781.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58782.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58783.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58784.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58785.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58786.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58787.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58788.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58789.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58790.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58791.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58792.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58793.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58794.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58795.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58796.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58797.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58798.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58800.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58801.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58802.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58798.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58792.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58790.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58806.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58807.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58808.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58809.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58810.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58811.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58812.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58813.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58814.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58815.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58816.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58817.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58818.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58819.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58820.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58821.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58822.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58797.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58815.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58827.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58828.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58829.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58830.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58827.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58819.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58835.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58836.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58828.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58839.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58750.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58835.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58855.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58855.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58858.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58860.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58864.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58864.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58867.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58867.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58870.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58858.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58873.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58873.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58876.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58870.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58879.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58879.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58881.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58885.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58885.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58876.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58888.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58836.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58891.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58894.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58894.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58897.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58897.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58900.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58900.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58903.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58903.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58905.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58891.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58908.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58912.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58912.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58914.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58930.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58918.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58920.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58923.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58926.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58933.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58930.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58816.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58933.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58936.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58936.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58939.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58939.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58941.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59394.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58492.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59261.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59268.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59267.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59261.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59262.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59263.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59264.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59265.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59266.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59267.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59268.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59270.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59270.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59272.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59263.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59272.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59266.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59284.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59285.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59290.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59296.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59300.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59305.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59311.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59315.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59320.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59331.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59337.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59357.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59371.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59382.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59387.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59393.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59400.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59407.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60399.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59410.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59413.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59416.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59419.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59422.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59425.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59428.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59435.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60088.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59438.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59445.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59446.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59452.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59467.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59471.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59468.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59475.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59478.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59516.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59538.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59563.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59568.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59578.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58811.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56772.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58768.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59383.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59651.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59705.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59708.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58046.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58077.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58770.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59767.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59789.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59783.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59783.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59785.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59785.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59787.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59789.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59791.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59793.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59795.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59797.lut0 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59793.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59791.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57705.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59797.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59798.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57694.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59819.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59824.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60105.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59824.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59827.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59830.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59830.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59833.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59833.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59839.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59839.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57652.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59845.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59851.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59854.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59854.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59845.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59857.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59860.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59860.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59863.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59866.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59866.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59870.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59870.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59876.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59879.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59879.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59882.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59885.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59885.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59888.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59891.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59891.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59895.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59899.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59901.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59910.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59907.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59901.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59910.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59916.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59913.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59916.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59920.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59920.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59926.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59929.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59932.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59935.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59935.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59938.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59938.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58447.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59944.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58201.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59947.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59947.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58318.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59951.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59957.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57787.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59960.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59960.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59963.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59966.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58175.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56368.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60036.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60042.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60046.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60049.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60049.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60053.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60056.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60058.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60060.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60057.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59439.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60072.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60075.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60075.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60084.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60087.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60087.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60095.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60076.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60098.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60102.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60105.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60107.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60115.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60118.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60118.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57776.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60124.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60130.lut0 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60056.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58391.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58397.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$59831.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58008.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58019.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58226.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58208.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60260.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60375.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60279.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60312.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60312.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60389.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60333.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60336.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60337.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60279.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60346.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$57630.lut1 (4 -> 2)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60369.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60369.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60333.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60375.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60382.lut0 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60386.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60389.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60391.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60346.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60394.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60394.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60396.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60399.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60401.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60403.lut0 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60396.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58794.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58742.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$55500.lut1 (4 -> 0)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58745.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$56764.lut1 (4 -> 3)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58743.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58775.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58776.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58781.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$58211.lut1 (4 -> 1)\n  Optimizing lut $abc$55201$auto$blifparse.cc:498:parse_blif$60017.lut1 (4 -> 0)\nRemoved 0 unused cells and 12155 unused wires.\n\n4.48. Executing AUTONAME pass.\nRenamed 337865 objects in module top (158 iterations).\n<suppressed ~19132 debug messages>\n\n4.49. Executing HIERARCHY pass (managing design hierarchy).\n\n4.49.1. Analyzing design hierarchy..\nTop module:  \\top\n\n4.49.2. Analyzing design hierarchy..\nTop module:  \\top\nRemoved 0 unused modules.\n\n4.50. Printing statistics.\n\n=== top ===\n\n   Number of wires:               8448\n   Number of wire bits:          36696\n   Number of public wires:        8448\n   Number of public wire bits:   36696\n   Number of memories:               0\n   Number of memory bits:            0\n   Number of processes:              0\n   Number of cells:              13186\n     CCU2C                         398\n     DP16KD                         46\n     EHXPLLL                         1\n     L6MUX21                       353\n     LUT4                         7071\n     MULT18X18D                      4\n     ODDRX1F                         1\n     PDPW16KD                        3\n     PFUMX                        1419\n     TRELLIS_DPR16X4                60\n     TRELLIS_FF                   3814\n     TRELLIS_IO                     16\n\n4.51. Executing CHECK pass (checking for obvious problems).\nchecking module top..\nfound and reported 0 problems.\n\n4.52. Executing JSON backend.\n\nWarnings: 1 unique messages, 1 total\nEnd of script. Logfile hash: 648cf46120, CPU: user 135.25s system 3.52s, MEM: 1165.72 MB peak\nYosys 0.9+3672 (git sha1 924f1713, gcc 8.3.0-6+rpi1 -fPIC -Os)\nTime spent: 21% 8x techmap (33 sec), 13% 1x autoname (20 sec), ...\n"
  },
  {
    "path": "src/litex_linux/top.svf",
    "content": "HDR\t0;\nHIR\t0;\nTDR\t0;\nTIR\t0;\nENDDR\tDRPAUSE;\nENDIR\tIRPAUSE;\nSTATE\tIDLE;\nSIR\t8\tTDI  (E0);\nSDR\t32\tTDI  (00000000)\n\t\t\tTDO  (41111043)\n\t\t\tMASK (FFFFFFFF);\n\nSIR\t8\tTDI  (1C);\nSDR\t510\tTDI  (3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF\n\t\t\t\tFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);\n\nSIR\t8\tTDI  (C6);\nSDR\t8\tTDI  (00);\nRUNTEST\tIDLE\t2 TCK\t1.00E-02 SEC;\n\nSIR\t8\tTDI  (0E);\nSDR\t8\tTDI  (01);\nRUNTEST\tIDLE\t2 TCK\t1.00E-02 SEC;\n\nSIR\t8\tTDI  (3C);\nSDR\t32\tTDI  (00000000)\n\t\t\tTDO  (00000000)\n\t\t\tMASK (0000B000);\n\nSIR\t8\tTDI  (46);\nSDR\t8\tTDI  (01);\nRUNTEST\tIDLE\t2 TCK\t1.00E-02 SEC;\n\nSIR\t8\tTDI  (7A);\nRUNTEST\tIDLE\t2 TCK\t1.00E-02 SEC;\nSDR\t8000\tTDI  (0000000000000000000000FF409B0000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000000000FF409B0000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000000000FF409B0000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t0000FF82980000000000000000000000000002000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000000000000000000000000000000000000000FF\n\t\t\t77B80000200000200200000000000000000000000200000000000000000000000000000000000000\n\t\t\t000000080200000000000000000080000080000000000000000000000000000000000000FFAC1D00\n\t\t\t00000000000000000400000002000400000000000000000000000000100000100000000000100000\n\t\t\t400100000000000000000000000000000000000000000000000000000000000000FF5C5F00002000\n\t\t\t00200200000200600000000000000200000000000000000000080000080000000000080000280280\n\t\t\t000000180000000080000080000000000000000000000000000000000000FF409B00000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000000000000000FF409B00000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000000000FF409B00000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000000000FF409B00000000000000000000000000000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t000000000000000000000000000000000000FF6C2400000000000000000000000000000004000000\n\t\t\t00000000000000000000000000000000000000000000000000000000000000000000000000000000\n\t\t\t00000000000000000000000000000051B88941000000620000080200000044C20888820000004700\n\t\t\t0000DCFFFFFFFFCDBDFFFFFF006CAC4C82E24282C26CB462AC4CB4AAACA26232045C2E4E860A00FF);\nSDR\t8000\tTDI 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 (FF);\nRUNTEST\tIDLE\t100 TCK\t1.00E-02 SEC;\n\nSIR\t8\tTDI  (C0);\nRUNTEST\tIDLE\t2 TCK\t1.00E-03 SEC;\nSDR\t32\tTDI  (00000000)\n\t\t\tTDO  (00000000)\n\t\t\tMASK (FFFFFFFF);\n\nSIR\t8\tTDI  (26);\nRUNTEST\tIDLE\t2 TCK\t2.00E-01 SEC;\n\nSIR\t8\tTDI  (FF);\nRUNTEST\tIDLE\t2 TCK\t1.00E-03 SEC;\n\nSIR\t8\tTDI  (3C);\nSDR\t32\tTDI  (00000000)\n\t\t\tTDO  (00000100)\n\t\t\tMASK (00002100);\n"
  },
  {
    "path": "src/litex_linux/top.v",
    "content": "//--------------------------------------------------------------------------------\n// Auto-generated by Migen (cc6e76e) & LiteX (275932f5) on 2020-11-11 09:43:42\n//--------------------------------------------------------------------------------\nmodule top(\n\toutput reg serial_tx,\n\tinput wire serial_rx,\n\tinput wire clk25,\n\tinput wire rst,\n\toutput wire sdram_clock,\n\toutput wire wifi_gpio0,\n\toutput wire [12:0] sdram_a,\n\tinput wire [15:0] sdram_dq,\n\toutput wire sdram_we_n,\n\toutput wire sdram_ras_n,\n\toutput wire sdram_cas_n,\n\toutput wire sdram_cs_n,\n\toutput wire sdram_cke,\n\toutput wire [1:0] sdram_ba,\n\toutput wire [1:0] sdram_dm,\n\toutput reg user_led0,\n\toutput reg user_led1,\n\toutput reg user_led2,\n\toutput reg user_led3,\n\toutput reg user_led4,\n\toutput reg user_led5,\n\toutput reg user_led6,\n\toutput reg user_led7,\n\toutput reg spisdcard_clk,\n\toutput reg spisdcard_mosi,\n\toutput reg spisdcard_cs_n,\n\tinput wire spisdcard_miso\n);\n\nreg main_soclinux_soccontroller_reset_storage = 1'd0;\nreg main_soclinux_soccontroller_reset_re = 1'd0;\nreg [31:0] main_soclinux_soccontroller_scratch_storage = 32'd305419896;\nreg main_soclinux_soccontroller_scratch_re = 1'd0;\nwire [31:0] main_soclinux_soccontroller_bus_errors_status;\nwire main_soclinux_soccontroller_bus_errors_we;\nwire main_soclinux_soccontroller_bus_errors_re;\nwire main_soclinux_soccontroller_reset;\nwire main_soclinux_soccontroller_bus_error;\nreg [31:0] main_soclinux_soccontroller_bus_errors = 32'd0;\nwire main_soclinux_cpu_reset;\nreg [31:0] main_soclinux_cpu_interrupt0 = 32'd0;\nwire [29:0] main_soclinux_cpu_ibus_adr;\nwire [31:0] main_soclinux_cpu_ibus_dat_w;\nwire [31:0] main_soclinux_cpu_ibus_dat_r;\nwire [3:0] main_soclinux_cpu_ibus_sel;\nwire main_soclinux_cpu_ibus_cyc;\nwire main_soclinux_cpu_ibus_stb;\nwire main_soclinux_cpu_ibus_ack;\nwire main_soclinux_cpu_ibus_we;\nwire [2:0] main_soclinux_cpu_ibus_cti;\nwire [1:0] main_soclinux_cpu_ibus_bte;\nwire main_soclinux_cpu_ibus_err;\nwire [29:0] main_soclinux_cpu_dbus_adr;\nwire [31:0] main_soclinux_cpu_dbus_dat_w;\nwire [31:0] main_soclinux_cpu_dbus_dat_r;\nwire [3:0] main_soclinux_cpu_dbus_sel;\nwire main_soclinux_cpu_dbus_cyc;\nwire main_soclinux_cpu_dbus_stb;\nwire main_soclinux_cpu_dbus_ack;\nwire main_soclinux_cpu_dbus_we;\nwire [2:0] main_soclinux_cpu_dbus_cti;\nwire [1:0] main_soclinux_cpu_dbus_bte;\nwire main_soclinux_cpu_dbus_err;\nwire main_soclinux_cpu_latch_re;\nwire main_soclinux_cpu_latch_r;\nwire main_soclinux_cpu_latch_we;\nreg main_soclinux_cpu_latch_w = 1'd0;\nreg [63:0] main_soclinux_cpu_time_status = 64'd0;\nwire main_soclinux_cpu_time_we;\nwire main_soclinux_cpu_time_re;\nreg [63:0] main_soclinux_cpu_time_cmp_storage = 64'd18446744073709551615;\nreg main_soclinux_cpu_time_cmp_re = 1'd0;\nwire main_soclinux_cpu_interrupt1;\nreg [63:0] main_soclinux_cpu_time = 64'd0;\nreg [63:0] main_soclinux_cpu_time_cmp = 64'd18446744073709551615;\nreg [31:0] main_soclinux_vexriscv = 32'd0;\nwire [29:0] main_soclinux_soclinux_ram_bus_adr;\nwire [31:0] main_soclinux_soclinux_ram_bus_dat_w;\nwire [31:0] main_soclinux_soclinux_ram_bus_dat_r;\nwire [3:0] main_soclinux_soclinux_ram_bus_sel;\nwire main_soclinux_soclinux_ram_bus_cyc;\nwire main_soclinux_soclinux_ram_bus_stb;\nreg main_soclinux_soclinux_ram_bus_ack = 1'd0;\nwire main_soclinux_soclinux_ram_bus_we;\nwire [2:0] main_soclinux_soclinux_ram_bus_cti;\nwire [1:0] main_soclinux_soclinux_ram_bus_bte;\nreg main_soclinux_soclinux_ram_bus_err = 1'd0;\nwire [13:0] main_soclinux_soclinux_adr;\nwire [31:0] main_soclinux_soclinux_dat_r;\nwire [29:0] main_soclinux_ram_bus_ram_bus_adr;\nwire [31:0] main_soclinux_ram_bus_ram_bus_dat_w;\nwire [31:0] main_soclinux_ram_bus_ram_bus_dat_r;\nwire [3:0] main_soclinux_ram_bus_ram_bus_sel;\nwire main_soclinux_ram_bus_ram_bus_cyc;\nwire main_soclinux_ram_bus_ram_bus_stb;\nreg main_soclinux_ram_bus_ram_bus_ack = 1'd0;\nwire main_soclinux_ram_bus_ram_bus_we;\nwire [2:0] main_soclinux_ram_bus_ram_bus_cti;\nwire [1:0] main_soclinux_ram_bus_ram_bus_bte;\nreg main_soclinux_ram_bus_ram_bus_err = 1'd0;\nwire [10:0] main_soclinux_ram_adr;\nwire [31:0] main_soclinux_ram_dat_r;\nreg [3:0] main_soclinux_ram_we = 4'd0;\nwire [31:0] main_soclinux_ram_dat_w;\nreg [31:0] main_soclinux_storage = 32'd85899345;\nreg main_soclinux_re = 1'd0;\nwire main_soclinux_sink_valid;\nreg main_soclinux_sink_ready = 1'd0;\nwire main_soclinux_sink_first;\nwire main_soclinux_sink_last;\nwire [7:0] main_soclinux_sink_payload_data;\nreg main_soclinux_tx_clken = 1'd0;\nreg [31:0] main_soclinux_tx_clkphase = 32'd0;\nreg [7:0] main_soclinux_tx_reg = 8'd0;\nreg [3:0] main_soclinux_tx_bitcount = 4'd0;\nreg main_soclinux_tx_busy = 1'd0;\nreg main_soclinux_source_valid = 1'd0;\nwire main_soclinux_source_ready;\nreg main_soclinux_source_first = 1'd0;\nreg main_soclinux_source_last = 1'd0;\nreg [7:0] main_soclinux_source_payload_data = 8'd0;\nreg main_soclinux_rx_clken = 1'd0;\nreg [31:0] main_soclinux_rx_clkphase = 32'd0;\nwire main_soclinux_rx;\nreg main_soclinux_rx_r = 1'd0;\nreg [7:0] main_soclinux_rx_reg = 8'd0;\nreg [3:0] main_soclinux_rx_bitcount = 4'd0;\nreg main_soclinux_rx_busy = 1'd0;\nwire main_soclinux_uart_rxtx_re;\nwire [7:0] main_soclinux_uart_rxtx_r;\nwire main_soclinux_uart_rxtx_we;\nwire [7:0] main_soclinux_uart_rxtx_w;\nwire main_soclinux_uart_txfull_status;\nwire main_soclinux_uart_txfull_we;\nwire main_soclinux_uart_txfull_re;\nwire main_soclinux_uart_rxempty_status;\nwire main_soclinux_uart_rxempty_we;\nwire main_soclinux_uart_rxempty_re;\nwire main_soclinux_uart_irq;\nwire main_soclinux_uart_tx_status;\nreg main_soclinux_uart_tx_pending = 1'd0;\nwire main_soclinux_uart_tx_trigger;\nreg main_soclinux_uart_tx_clear = 1'd0;\nreg main_soclinux_uart_tx_old_trigger = 1'd0;\nwire main_soclinux_uart_rx_status;\nreg main_soclinux_uart_rx_pending = 1'd0;\nwire main_soclinux_uart_rx_trigger;\nreg main_soclinux_uart_rx_clear = 1'd0;\nreg main_soclinux_uart_rx_old_trigger = 1'd0;\nwire main_soclinux_uart_eventmanager_status_re;\nwire [1:0] main_soclinux_uart_eventmanager_status_r;\nwire main_soclinux_uart_eventmanager_status_we;\nreg [1:0] main_soclinux_uart_eventmanager_status_w = 2'd0;\nwire main_soclinux_uart_eventmanager_pending_re;\nwire [1:0] main_soclinux_uart_eventmanager_pending_r;\nwire main_soclinux_uart_eventmanager_pending_we;\nreg [1:0] main_soclinux_uart_eventmanager_pending_w = 2'd0;\nreg [1:0] main_soclinux_uart_eventmanager_storage = 2'd0;\nreg main_soclinux_uart_eventmanager_re = 1'd0;\nwire main_soclinux_uart_txempty_status;\nwire main_soclinux_uart_txempty_we;\nwire main_soclinux_uart_txempty_re;\nwire main_soclinux_uart_rxfull_status;\nwire main_soclinux_uart_rxfull_we;\nwire main_soclinux_uart_rxfull_re;\nwire main_soclinux_uart_uart_sink_valid;\nwire main_soclinux_uart_uart_sink_ready;\nwire main_soclinux_uart_uart_sink_first;\nwire main_soclinux_uart_uart_sink_last;\nwire [7:0] main_soclinux_uart_uart_sink_payload_data;\nwire main_soclinux_uart_uart_source_valid;\nwire main_soclinux_uart_uart_source_ready;\nwire main_soclinux_uart_uart_source_first;\nwire main_soclinux_uart_uart_source_last;\nwire [7:0] main_soclinux_uart_uart_source_payload_data;\nwire main_soclinux_uart_tx_fifo_sink_valid;\nwire main_soclinux_uart_tx_fifo_sink_ready;\nreg main_soclinux_uart_tx_fifo_sink_first = 1'd0;\nreg main_soclinux_uart_tx_fifo_sink_last = 1'd0;\nwire [7:0] main_soclinux_uart_tx_fifo_sink_payload_data;\nwire main_soclinux_uart_tx_fifo_source_valid;\nwire main_soclinux_uart_tx_fifo_source_ready;\nwire main_soclinux_uart_tx_fifo_source_first;\nwire main_soclinux_uart_tx_fifo_source_last;\nwire [7:0] main_soclinux_uart_tx_fifo_source_payload_data;\nwire main_soclinux_uart_tx_fifo_re;\nreg main_soclinux_uart_tx_fifo_readable = 1'd0;\nwire main_soclinux_uart_tx_fifo_syncfifo_we;\nwire main_soclinux_uart_tx_fifo_syncfifo_writable;\nwire main_soclinux_uart_tx_fifo_syncfifo_re;\nwire main_soclinux_uart_tx_fifo_syncfifo_readable;\nwire [9:0] main_soclinux_uart_tx_fifo_syncfifo_din;\nwire [9:0] main_soclinux_uart_tx_fifo_syncfifo_dout;\nreg [4:0] main_soclinux_uart_tx_fifo_level0 = 5'd0;\nreg main_soclinux_uart_tx_fifo_replace = 1'd0;\nreg [3:0] main_soclinux_uart_tx_fifo_produce = 4'd0;\nreg [3:0] main_soclinux_uart_tx_fifo_consume = 4'd0;\nreg [3:0] main_soclinux_uart_tx_fifo_wrport_adr = 4'd0;\nwire [9:0] main_soclinux_uart_tx_fifo_wrport_dat_r;\nwire main_soclinux_uart_tx_fifo_wrport_we;\nwire [9:0] main_soclinux_uart_tx_fifo_wrport_dat_w;\nwire main_soclinux_uart_tx_fifo_do_read;\nwire [3:0] main_soclinux_uart_tx_fifo_rdport_adr;\nwire [9:0] main_soclinux_uart_tx_fifo_rdport_dat_r;\nwire main_soclinux_uart_tx_fifo_rdport_re;\nwire [4:0] main_soclinux_uart_tx_fifo_level1;\nwire [7:0] main_soclinux_uart_tx_fifo_fifo_in_payload_data;\nwire main_soclinux_uart_tx_fifo_fifo_in_first;\nwire main_soclinux_uart_tx_fifo_fifo_in_last;\nwire [7:0] main_soclinux_uart_tx_fifo_fifo_out_payload_data;\nwire main_soclinux_uart_tx_fifo_fifo_out_first;\nwire main_soclinux_uart_tx_fifo_fifo_out_last;\nwire main_soclinux_uart_rx_fifo_sink_valid;\nwire main_soclinux_uart_rx_fifo_sink_ready;\nwire main_soclinux_uart_rx_fifo_sink_first;\nwire main_soclinux_uart_rx_fifo_sink_last;\nwire [7:0] main_soclinux_uart_rx_fifo_sink_payload_data;\nwire main_soclinux_uart_rx_fifo_source_valid;\nwire main_soclinux_uart_rx_fifo_source_ready;\nwire main_soclinux_uart_rx_fifo_source_first;\nwire main_soclinux_uart_rx_fifo_source_last;\nwire [7:0] main_soclinux_uart_rx_fifo_source_payload_data;\nwire main_soclinux_uart_rx_fifo_re;\nreg main_soclinux_uart_rx_fifo_readable = 1'd0;\nwire main_soclinux_uart_rx_fifo_syncfifo_we;\nwire main_soclinux_uart_rx_fifo_syncfifo_writable;\nwire main_soclinux_uart_rx_fifo_syncfifo_re;\nwire main_soclinux_uart_rx_fifo_syncfifo_readable;\nwire [9:0] main_soclinux_uart_rx_fifo_syncfifo_din;\nwire [9:0] main_soclinux_uart_rx_fifo_syncfifo_dout;\nreg [4:0] main_soclinux_uart_rx_fifo_level0 = 5'd0;\nreg main_soclinux_uart_rx_fifo_replace = 1'd0;\nreg [3:0] main_soclinux_uart_rx_fifo_produce = 4'd0;\nreg [3:0] main_soclinux_uart_rx_fifo_consume = 4'd0;\nreg [3:0] main_soclinux_uart_rx_fifo_wrport_adr = 4'd0;\nwire [9:0] main_soclinux_uart_rx_fifo_wrport_dat_r;\nwire main_soclinux_uart_rx_fifo_wrport_we;\nwire [9:0] main_soclinux_uart_rx_fifo_wrport_dat_w;\nwire main_soclinux_uart_rx_fifo_do_read;\nwire [3:0] main_soclinux_uart_rx_fifo_rdport_adr;\nwire [9:0] main_soclinux_uart_rx_fifo_rdport_dat_r;\nwire main_soclinux_uart_rx_fifo_rdport_re;\nwire [4:0] main_soclinux_uart_rx_fifo_level1;\nwire [7:0] main_soclinux_uart_rx_fifo_fifo_in_payload_data;\nwire main_soclinux_uart_rx_fifo_fifo_in_first;\nwire main_soclinux_uart_rx_fifo_fifo_in_last;\nwire [7:0] main_soclinux_uart_rx_fifo_fifo_out_payload_data;\nwire main_soclinux_uart_rx_fifo_fifo_out_first;\nwire main_soclinux_uart_rx_fifo_fifo_out_last;\nreg main_soclinux_uart_reset = 1'd0;\nreg [31:0] main_soclinux_timer_load_storage = 32'd0;\nreg main_soclinux_timer_load_re = 1'd0;\nreg [31:0] main_soclinux_timer_reload_storage = 32'd0;\nreg main_soclinux_timer_reload_re = 1'd0;\nreg main_soclinux_timer_en_storage = 1'd0;\nreg main_soclinux_timer_en_re = 1'd0;\nreg main_soclinux_timer_update_value_storage = 1'd0;\nreg main_soclinux_timer_update_value_re = 1'd0;\nreg [31:0] main_soclinux_timer_value_status = 32'd0;\nwire main_soclinux_timer_value_we;\nwire main_soclinux_timer_value_re;\nwire main_soclinux_timer_irq;\nwire main_soclinux_timer_zero_status;\nreg main_soclinux_timer_zero_pending = 1'd0;\nwire main_soclinux_timer_zero_trigger;\nreg main_soclinux_timer_zero_clear = 1'd0;\nreg main_soclinux_timer_zero_old_trigger = 1'd0;\nwire main_soclinux_timer_eventmanager_status_re;\nwire main_soclinux_timer_eventmanager_status_r;\nwire main_soclinux_timer_eventmanager_status_we;\nwire main_soclinux_timer_eventmanager_status_w;\nwire main_soclinux_timer_eventmanager_pending_re;\nwire main_soclinux_timer_eventmanager_pending_r;\nwire main_soclinux_timer_eventmanager_pending_we;\nwire main_soclinux_timer_eventmanager_pending_w;\nreg main_soclinux_timer_eventmanager_storage = 1'd0;\nreg main_soclinux_timer_eventmanager_re = 1'd0;\nreg [31:0] main_soclinux_timer_value = 32'd0;\nwire main_rst;\nwire sys_clk;\nwire sys_rst;\nwire sys_ps_clk;\nwire main_reset;\nwire main_locked;\nwire main_clkin;\nwire main_clkout0;\nwire main_clkout1;\nwire [12:0] main_dfi_p0_address;\nwire [1:0] main_dfi_p0_bank;\nwire main_dfi_p0_cas_n;\nwire main_dfi_p0_cs_n;\nwire main_dfi_p0_ras_n;\nwire main_dfi_p0_we_n;\nwire main_dfi_p0_cke;\nwire main_dfi_p0_odt;\nwire main_dfi_p0_reset_n;\nwire main_dfi_p0_act_n;\nwire [15:0] main_dfi_p0_wrdata;\nwire main_dfi_p0_wrdata_en;\nwire [1:0] main_dfi_p0_wrdata_mask;\nwire main_dfi_p0_rddata_en;\nwire [15:0] main_dfi_p0_rddata;\nreg main_dfi_p0_rddata_valid = 1'd0;\nreg [2:0] main_rddata_en = 3'd0;\nwire [12:0] main_sdram_inti_p0_address;\nwire [1:0] main_sdram_inti_p0_bank;\nreg main_sdram_inti_p0_cas_n = 1'd1;\nreg main_sdram_inti_p0_cs_n = 1'd1;\nreg main_sdram_inti_p0_ras_n = 1'd1;\nreg main_sdram_inti_p0_we_n = 1'd1;\nwire main_sdram_inti_p0_cke;\nwire main_sdram_inti_p0_odt;\nwire main_sdram_inti_p0_reset_n;\nreg main_sdram_inti_p0_act_n = 1'd1;\nwire [15:0] main_sdram_inti_p0_wrdata;\nwire main_sdram_inti_p0_wrdata_en;\nwire [1:0] main_sdram_inti_p0_wrdata_mask;\nwire main_sdram_inti_p0_rddata_en;\nreg [15:0] main_sdram_inti_p0_rddata = 16'd0;\nreg main_sdram_inti_p0_rddata_valid = 1'd0;\nwire [12:0] main_sdram_slave_p0_address;\nwire [1:0] main_sdram_slave_p0_bank;\nwire main_sdram_slave_p0_cas_n;\nwire main_sdram_slave_p0_cs_n;\nwire main_sdram_slave_p0_ras_n;\nwire main_sdram_slave_p0_we_n;\nwire main_sdram_slave_p0_cke;\nwire main_sdram_slave_p0_odt;\nwire main_sdram_slave_p0_reset_n;\nwire main_sdram_slave_p0_act_n;\nwire [15:0] main_sdram_slave_p0_wrdata;\nwire main_sdram_slave_p0_wrdata_en;\nwire [1:0] main_sdram_slave_p0_wrdata_mask;\nwire main_sdram_slave_p0_rddata_en;\nreg [15:0] main_sdram_slave_p0_rddata = 16'd0;\nreg main_sdram_slave_p0_rddata_valid = 1'd0;\nreg [12:0] main_sdram_master_p0_address = 13'd0;\nreg [1:0] main_sdram_master_p0_bank = 2'd0;\nreg main_sdram_master_p0_cas_n = 1'd1;\nreg main_sdram_master_p0_cs_n = 1'd1;\nreg main_sdram_master_p0_ras_n = 1'd1;\nreg main_sdram_master_p0_we_n = 1'd1;\nreg main_sdram_master_p0_cke = 1'd0;\nreg main_sdram_master_p0_odt = 1'd0;\nreg main_sdram_master_p0_reset_n = 1'd0;\nreg main_sdram_master_p0_act_n = 1'd1;\nreg [15:0] main_sdram_master_p0_wrdata = 16'd0;\nreg main_sdram_master_p0_wrdata_en = 1'd0;\nreg [1:0] main_sdram_master_p0_wrdata_mask = 2'd0;\nreg main_sdram_master_p0_rddata_en = 1'd0;\nwire [15:0] main_sdram_master_p0_rddata;\nwire main_sdram_master_p0_rddata_valid;\nwire main_sdram_sel;\nwire main_sdram_cke1;\nwire main_sdram_odt;\nwire main_sdram_reset_n;\nreg [3:0] main_sdram_storage = 4'd1;\nreg main_sdram_re = 1'd0;\nreg [5:0] main_sdram_command_storage = 6'd0;\nreg main_sdram_command_re = 1'd0;\nwire main_sdram_command_issue_re;\nwire main_sdram_command_issue_r;\nwire main_sdram_command_issue_we;\nreg main_sdram_command_issue_w = 1'd0;\nreg [12:0] main_sdram_address_storage = 13'd0;\nreg main_sdram_address_re = 1'd0;\nreg [1:0] main_sdram_baddress_storage = 2'd0;\nreg main_sdram_baddress_re = 1'd0;\nreg [15:0] main_sdram_wrdata_storage = 16'd0;\nreg main_sdram_wrdata_re = 1'd0;\nreg [15:0] main_sdram_rddata_status = 16'd0;\nwire main_sdram_rddata_we;\nwire main_sdram_rddata_re;\nwire main_sdram_interface_bank0_valid;\nwire main_sdram_interface_bank0_ready;\nwire main_sdram_interface_bank0_we;\nwire [21:0] main_sdram_interface_bank0_addr;\nwire main_sdram_interface_bank0_lock;\nwire main_sdram_interface_bank0_wdata_ready;\nwire main_sdram_interface_bank0_rdata_valid;\nwire main_sdram_interface_bank1_valid;\nwire main_sdram_interface_bank1_ready;\nwire main_sdram_interface_bank1_we;\nwire [21:0] main_sdram_interface_bank1_addr;\nwire main_sdram_interface_bank1_lock;\nwire main_sdram_interface_bank1_wdata_ready;\nwire main_sdram_interface_bank1_rdata_valid;\nwire main_sdram_interface_bank2_valid;\nwire main_sdram_interface_bank2_ready;\nwire main_sdram_interface_bank2_we;\nwire [21:0] main_sdram_interface_bank2_addr;\nwire main_sdram_interface_bank2_lock;\nwire main_sdram_interface_bank2_wdata_ready;\nwire main_sdram_interface_bank2_rdata_valid;\nwire main_sdram_interface_bank3_valid;\nwire main_sdram_interface_bank3_ready;\nwire main_sdram_interface_bank3_we;\nwire [21:0] main_sdram_interface_bank3_addr;\nwire main_sdram_interface_bank3_lock;\nwire main_sdram_interface_bank3_wdata_ready;\nwire main_sdram_interface_bank3_rdata_valid;\nreg [15:0] main_sdram_interface_wdata = 16'd0;\nreg [1:0] main_sdram_interface_wdata_we = 2'd0;\nwire [15:0] main_sdram_interface_rdata;\nreg [12:0] main_sdram_dfi_p0_address = 13'd0;\nreg [1:0] main_sdram_dfi_p0_bank = 2'd0;\nreg main_sdram_dfi_p0_cas_n = 1'd1;\nreg main_sdram_dfi_p0_cs_n = 1'd1;\nreg main_sdram_dfi_p0_ras_n = 1'd1;\nreg main_sdram_dfi_p0_we_n = 1'd1;\nwire main_sdram_dfi_p0_cke;\nwire main_sdram_dfi_p0_odt;\nwire main_sdram_dfi_p0_reset_n;\nreg main_sdram_dfi_p0_act_n = 1'd1;\nwire [15:0] main_sdram_dfi_p0_wrdata;\nreg main_sdram_dfi_p0_wrdata_en = 1'd0;\nwire [1:0] main_sdram_dfi_p0_wrdata_mask;\nreg main_sdram_dfi_p0_rddata_en = 1'd0;\nwire [15:0] main_sdram_dfi_p0_rddata;\nwire main_sdram_dfi_p0_rddata_valid;\nreg main_sdram_cmd_valid = 1'd0;\nreg main_sdram_cmd_ready = 1'd0;\nreg main_sdram_cmd_last = 1'd0;\nreg [12:0] main_sdram_cmd_payload_a = 13'd0;\nreg [1:0] main_sdram_cmd_payload_ba = 2'd0;\nreg main_sdram_cmd_payload_cas = 1'd0;\nreg main_sdram_cmd_payload_ras = 1'd0;\nreg main_sdram_cmd_payload_we = 1'd0;\nreg main_sdram_cmd_payload_is_read = 1'd0;\nreg main_sdram_cmd_payload_is_write = 1'd0;\nwire main_sdram_wants_refresh;\nwire main_sdram_timer_wait;\nwire main_sdram_timer_done0;\nwire [8:0] main_sdram_timer_count0;\nwire main_sdram_timer_done1;\nreg [8:0] main_sdram_timer_count1 = 9'd390;\nwire main_sdram_postponer_req_i;\nreg main_sdram_postponer_req_o = 1'd0;\nreg main_sdram_postponer_count = 1'd0;\nreg main_sdram_sequencer_start0 = 1'd0;\nwire main_sdram_sequencer_done0;\nwire main_sdram_sequencer_start1;\nreg main_sdram_sequencer_done1 = 1'd0;\nreg [2:0] main_sdram_sequencer_counter = 3'd0;\nreg main_sdram_sequencer_count = 1'd0;\nwire main_sdram_bankmachine0_req_valid;\nwire main_sdram_bankmachine0_req_ready;\nwire main_sdram_bankmachine0_req_we;\nwire [21:0] main_sdram_bankmachine0_req_addr;\nwire main_sdram_bankmachine0_req_lock;\nreg main_sdram_bankmachine0_req_wdata_ready = 1'd0;\nreg main_sdram_bankmachine0_req_rdata_valid = 1'd0;\nwire main_sdram_bankmachine0_refresh_req;\nreg main_sdram_bankmachine0_refresh_gnt = 1'd0;\nreg main_sdram_bankmachine0_cmd_valid = 1'd0;\nreg main_sdram_bankmachine0_cmd_ready = 1'd0;\nreg [12:0] main_sdram_bankmachine0_cmd_payload_a = 13'd0;\nwire [1:0] main_sdram_bankmachine0_cmd_payload_ba;\nreg main_sdram_bankmachine0_cmd_payload_cas = 1'd0;\nreg main_sdram_bankmachine0_cmd_payload_ras = 1'd0;\nreg main_sdram_bankmachine0_cmd_payload_we = 1'd0;\nreg main_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;\nreg main_sdram_bankmachine0_cmd_payload_is_read = 1'd0;\nreg main_sdram_bankmachine0_cmd_payload_is_write = 1'd0;\nreg main_sdram_bankmachine0_auto_precharge = 1'd0;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;\nreg main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;\nreg main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;\nwire [21:0] main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_source_first;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_source_last;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;\nwire [21:0] main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;\nwire [24:0] main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;\nwire [24:0] main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;\nreg [3:0] main_sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0;\nreg main_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;\nreg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0;\nreg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0;\nreg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0;\nwire [24:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;\nwire [24:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_do_read;\nwire [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;\nwire [24:0] main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;\nwire [21:0] main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;\nwire [21:0] main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;\nwire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;\nwire main_sdram_bankmachine0_cmd_buffer_sink_valid;\nwire main_sdram_bankmachine0_cmd_buffer_sink_ready;\nwire main_sdram_bankmachine0_cmd_buffer_sink_first;\nwire main_sdram_bankmachine0_cmd_buffer_sink_last;\nwire main_sdram_bankmachine0_cmd_buffer_sink_payload_we;\nwire [21:0] main_sdram_bankmachine0_cmd_buffer_sink_payload_addr;\nreg main_sdram_bankmachine0_cmd_buffer_source_valid = 1'd0;\nwire main_sdram_bankmachine0_cmd_buffer_source_ready;\nreg main_sdram_bankmachine0_cmd_buffer_source_first = 1'd0;\nreg main_sdram_bankmachine0_cmd_buffer_source_last = 1'd0;\nreg main_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0;\nreg [21:0] main_sdram_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;\nreg [12:0] main_sdram_bankmachine0_row = 13'd0;\nreg main_sdram_bankmachine0_row_opened = 1'd0;\nwire main_sdram_bankmachine0_row_hit;\nreg main_sdram_bankmachine0_row_open = 1'd0;\nreg main_sdram_bankmachine0_row_close = 1'd0;\nreg main_sdram_bankmachine0_row_col_n_addr_sel = 1'd0;\nwire main_sdram_bankmachine0_twtpcon_valid;\nreg main_sdram_bankmachine0_twtpcon_ready = 1'd0;\nreg [1:0] main_sdram_bankmachine0_twtpcon_count = 2'd0;\nwire main_sdram_bankmachine0_trccon_valid;\nreg main_sdram_bankmachine0_trccon_ready = 1'd0;\nreg [1:0] main_sdram_bankmachine0_trccon_count = 2'd0;\nwire main_sdram_bankmachine0_trascon_valid;\nreg main_sdram_bankmachine0_trascon_ready = 1'd0;\nreg [1:0] main_sdram_bankmachine0_trascon_count = 2'd0;\nwire main_sdram_bankmachine1_req_valid;\nwire main_sdram_bankmachine1_req_ready;\nwire main_sdram_bankmachine1_req_we;\nwire [21:0] main_sdram_bankmachine1_req_addr;\nwire main_sdram_bankmachine1_req_lock;\nreg main_sdram_bankmachine1_req_wdata_ready = 1'd0;\nreg main_sdram_bankmachine1_req_rdata_valid = 1'd0;\nwire main_sdram_bankmachine1_refresh_req;\nreg main_sdram_bankmachine1_refresh_gnt = 1'd0;\nreg main_sdram_bankmachine1_cmd_valid = 1'd0;\nreg main_sdram_bankmachine1_cmd_ready = 1'd0;\nreg [12:0] main_sdram_bankmachine1_cmd_payload_a = 13'd0;\nwire [1:0] main_sdram_bankmachine1_cmd_payload_ba;\nreg main_sdram_bankmachine1_cmd_payload_cas = 1'd0;\nreg main_sdram_bankmachine1_cmd_payload_ras = 1'd0;\nreg main_sdram_bankmachine1_cmd_payload_we = 1'd0;\nreg main_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;\nreg main_sdram_bankmachine1_cmd_payload_is_read = 1'd0;\nreg main_sdram_bankmachine1_cmd_payload_is_write = 1'd0;\nreg main_sdram_bankmachine1_auto_precharge = 1'd0;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;\nreg main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;\nreg main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;\nwire [21:0] main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_source_first;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_source_last;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;\nwire [21:0] main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;\nwire [24:0] main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;\nwire [24:0] main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;\nreg [3:0] main_sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0;\nreg main_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;\nreg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0;\nreg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0;\nreg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0;\nwire [24:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;\nwire [24:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_do_read;\nwire [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;\nwire [24:0] main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;\nwire [21:0] main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;\nwire [21:0] main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;\nwire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;\nwire main_sdram_bankmachine1_cmd_buffer_sink_valid;\nwire main_sdram_bankmachine1_cmd_buffer_sink_ready;\nwire main_sdram_bankmachine1_cmd_buffer_sink_first;\nwire main_sdram_bankmachine1_cmd_buffer_sink_last;\nwire main_sdram_bankmachine1_cmd_buffer_sink_payload_we;\nwire [21:0] main_sdram_bankmachine1_cmd_buffer_sink_payload_addr;\nreg main_sdram_bankmachine1_cmd_buffer_source_valid = 1'd0;\nwire main_sdram_bankmachine1_cmd_buffer_source_ready;\nreg main_sdram_bankmachine1_cmd_buffer_source_first = 1'd0;\nreg main_sdram_bankmachine1_cmd_buffer_source_last = 1'd0;\nreg main_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0;\nreg [21:0] main_sdram_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;\nreg [12:0] main_sdram_bankmachine1_row = 13'd0;\nreg main_sdram_bankmachine1_row_opened = 1'd0;\nwire main_sdram_bankmachine1_row_hit;\nreg main_sdram_bankmachine1_row_open = 1'd0;\nreg main_sdram_bankmachine1_row_close = 1'd0;\nreg main_sdram_bankmachine1_row_col_n_addr_sel = 1'd0;\nwire main_sdram_bankmachine1_twtpcon_valid;\nreg main_sdram_bankmachine1_twtpcon_ready = 1'd0;\nreg [1:0] main_sdram_bankmachine1_twtpcon_count = 2'd0;\nwire main_sdram_bankmachine1_trccon_valid;\nreg main_sdram_bankmachine1_trccon_ready = 1'd0;\nreg [1:0] main_sdram_bankmachine1_trccon_count = 2'd0;\nwire main_sdram_bankmachine1_trascon_valid;\nreg main_sdram_bankmachine1_trascon_ready = 1'd0;\nreg [1:0] main_sdram_bankmachine1_trascon_count = 2'd0;\nwire main_sdram_bankmachine2_req_valid;\nwire main_sdram_bankmachine2_req_ready;\nwire main_sdram_bankmachine2_req_we;\nwire [21:0] main_sdram_bankmachine2_req_addr;\nwire main_sdram_bankmachine2_req_lock;\nreg main_sdram_bankmachine2_req_wdata_ready = 1'd0;\nreg main_sdram_bankmachine2_req_rdata_valid = 1'd0;\nwire main_sdram_bankmachine2_refresh_req;\nreg main_sdram_bankmachine2_refresh_gnt = 1'd0;\nreg main_sdram_bankmachine2_cmd_valid = 1'd0;\nreg main_sdram_bankmachine2_cmd_ready = 1'd0;\nreg [12:0] main_sdram_bankmachine2_cmd_payload_a = 13'd0;\nwire [1:0] main_sdram_bankmachine2_cmd_payload_ba;\nreg main_sdram_bankmachine2_cmd_payload_cas = 1'd0;\nreg main_sdram_bankmachine2_cmd_payload_ras = 1'd0;\nreg main_sdram_bankmachine2_cmd_payload_we = 1'd0;\nreg main_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;\nreg main_sdram_bankmachine2_cmd_payload_is_read = 1'd0;\nreg main_sdram_bankmachine2_cmd_payload_is_write = 1'd0;\nreg main_sdram_bankmachine2_auto_precharge = 1'd0;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;\nreg main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;\nreg main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;\nwire [21:0] main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_source_first;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_source_last;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;\nwire [21:0] main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;\nwire [24:0] main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;\nwire [24:0] main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;\nreg [3:0] main_sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0;\nreg main_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;\nreg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0;\nreg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0;\nreg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0;\nwire [24:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;\nwire [24:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_do_read;\nwire [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;\nwire [24:0] main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;\nwire [21:0] main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;\nwire [21:0] main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;\nwire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;\nwire main_sdram_bankmachine2_cmd_buffer_sink_valid;\nwire main_sdram_bankmachine2_cmd_buffer_sink_ready;\nwire main_sdram_bankmachine2_cmd_buffer_sink_first;\nwire main_sdram_bankmachine2_cmd_buffer_sink_last;\nwire main_sdram_bankmachine2_cmd_buffer_sink_payload_we;\nwire [21:0] main_sdram_bankmachine2_cmd_buffer_sink_payload_addr;\nreg main_sdram_bankmachine2_cmd_buffer_source_valid = 1'd0;\nwire main_sdram_bankmachine2_cmd_buffer_source_ready;\nreg main_sdram_bankmachine2_cmd_buffer_source_first = 1'd0;\nreg main_sdram_bankmachine2_cmd_buffer_source_last = 1'd0;\nreg main_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0;\nreg [21:0] main_sdram_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;\nreg [12:0] main_sdram_bankmachine2_row = 13'd0;\nreg main_sdram_bankmachine2_row_opened = 1'd0;\nwire main_sdram_bankmachine2_row_hit;\nreg main_sdram_bankmachine2_row_open = 1'd0;\nreg main_sdram_bankmachine2_row_close = 1'd0;\nreg main_sdram_bankmachine2_row_col_n_addr_sel = 1'd0;\nwire main_sdram_bankmachine2_twtpcon_valid;\nreg main_sdram_bankmachine2_twtpcon_ready = 1'd0;\nreg [1:0] main_sdram_bankmachine2_twtpcon_count = 2'd0;\nwire main_sdram_bankmachine2_trccon_valid;\nreg main_sdram_bankmachine2_trccon_ready = 1'd0;\nreg [1:0] main_sdram_bankmachine2_trccon_count = 2'd0;\nwire main_sdram_bankmachine2_trascon_valid;\nreg main_sdram_bankmachine2_trascon_ready = 1'd0;\nreg [1:0] main_sdram_bankmachine2_trascon_count = 2'd0;\nwire main_sdram_bankmachine3_req_valid;\nwire main_sdram_bankmachine3_req_ready;\nwire main_sdram_bankmachine3_req_we;\nwire [21:0] main_sdram_bankmachine3_req_addr;\nwire main_sdram_bankmachine3_req_lock;\nreg main_sdram_bankmachine3_req_wdata_ready = 1'd0;\nreg main_sdram_bankmachine3_req_rdata_valid = 1'd0;\nwire main_sdram_bankmachine3_refresh_req;\nreg main_sdram_bankmachine3_refresh_gnt = 1'd0;\nreg main_sdram_bankmachine3_cmd_valid = 1'd0;\nreg main_sdram_bankmachine3_cmd_ready = 1'd0;\nreg [12:0] main_sdram_bankmachine3_cmd_payload_a = 13'd0;\nwire [1:0] main_sdram_bankmachine3_cmd_payload_ba;\nreg main_sdram_bankmachine3_cmd_payload_cas = 1'd0;\nreg main_sdram_bankmachine3_cmd_payload_ras = 1'd0;\nreg main_sdram_bankmachine3_cmd_payload_we = 1'd0;\nreg main_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;\nreg main_sdram_bankmachine3_cmd_payload_is_read = 1'd0;\nreg main_sdram_bankmachine3_cmd_payload_is_write = 1'd0;\nreg main_sdram_bankmachine3_auto_precharge = 1'd0;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;\nreg main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;\nreg main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;\nwire [21:0] main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_source_first;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_source_last;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;\nwire [21:0] main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;\nwire [24:0] main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;\nwire [24:0] main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;\nreg [3:0] main_sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0;\nreg main_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;\nreg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0;\nreg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0;\nreg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0;\nwire [24:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;\nwire [24:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_do_read;\nwire [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;\nwire [24:0] main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;\nwire [21:0] main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;\nwire [21:0] main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;\nwire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;\nwire main_sdram_bankmachine3_cmd_buffer_sink_valid;\nwire main_sdram_bankmachine3_cmd_buffer_sink_ready;\nwire main_sdram_bankmachine3_cmd_buffer_sink_first;\nwire main_sdram_bankmachine3_cmd_buffer_sink_last;\nwire main_sdram_bankmachine3_cmd_buffer_sink_payload_we;\nwire [21:0] main_sdram_bankmachine3_cmd_buffer_sink_payload_addr;\nreg main_sdram_bankmachine3_cmd_buffer_source_valid = 1'd0;\nwire main_sdram_bankmachine3_cmd_buffer_source_ready;\nreg main_sdram_bankmachine3_cmd_buffer_source_first = 1'd0;\nreg main_sdram_bankmachine3_cmd_buffer_source_last = 1'd0;\nreg main_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0;\nreg [21:0] main_sdram_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;\nreg [12:0] main_sdram_bankmachine3_row = 13'd0;\nreg main_sdram_bankmachine3_row_opened = 1'd0;\nwire main_sdram_bankmachine3_row_hit;\nreg main_sdram_bankmachine3_row_open = 1'd0;\nreg main_sdram_bankmachine3_row_close = 1'd0;\nreg main_sdram_bankmachine3_row_col_n_addr_sel = 1'd0;\nwire main_sdram_bankmachine3_twtpcon_valid;\nreg main_sdram_bankmachine3_twtpcon_ready = 1'd0;\nreg [1:0] main_sdram_bankmachine3_twtpcon_count = 2'd0;\nwire main_sdram_bankmachine3_trccon_valid;\nreg main_sdram_bankmachine3_trccon_ready = 1'd0;\nreg [1:0] main_sdram_bankmachine3_trccon_count = 2'd0;\nwire main_sdram_bankmachine3_trascon_valid;\nreg main_sdram_bankmachine3_trascon_ready = 1'd0;\nreg [1:0] main_sdram_bankmachine3_trascon_count = 2'd0;\nwire main_sdram_ras_allowed;\nwire main_sdram_cas_allowed;\nreg main_sdram_choose_cmd_want_reads = 1'd0;\nreg main_sdram_choose_cmd_want_writes = 1'd0;\nreg main_sdram_choose_cmd_want_cmds = 1'd0;\nreg main_sdram_choose_cmd_want_activates = 1'd0;\nwire main_sdram_choose_cmd_cmd_valid;\nreg main_sdram_choose_cmd_cmd_ready = 1'd0;\nwire [12:0] main_sdram_choose_cmd_cmd_payload_a;\nwire [1:0] main_sdram_choose_cmd_cmd_payload_ba;\nreg main_sdram_choose_cmd_cmd_payload_cas = 1'd0;\nreg main_sdram_choose_cmd_cmd_payload_ras = 1'd0;\nreg main_sdram_choose_cmd_cmd_payload_we = 1'd0;\nwire main_sdram_choose_cmd_cmd_payload_is_cmd;\nwire main_sdram_choose_cmd_cmd_payload_is_read;\nwire main_sdram_choose_cmd_cmd_payload_is_write;\nreg [3:0] main_sdram_choose_cmd_valids = 4'd0;\nwire [3:0] main_sdram_choose_cmd_request;\nreg [1:0] main_sdram_choose_cmd_grant = 2'd0;\nwire main_sdram_choose_cmd_ce;\nreg main_sdram_choose_req_want_reads = 1'd0;\nreg main_sdram_choose_req_want_writes = 1'd0;\nwire main_sdram_choose_req_want_cmds;\nreg main_sdram_choose_req_want_activates = 1'd0;\nwire main_sdram_choose_req_cmd_valid;\nreg main_sdram_choose_req_cmd_ready = 1'd0;\nwire [12:0] main_sdram_choose_req_cmd_payload_a;\nwire [1:0] main_sdram_choose_req_cmd_payload_ba;\nreg main_sdram_choose_req_cmd_payload_cas = 1'd0;\nreg main_sdram_choose_req_cmd_payload_ras = 1'd0;\nreg main_sdram_choose_req_cmd_payload_we = 1'd0;\nwire main_sdram_choose_req_cmd_payload_is_cmd;\nwire main_sdram_choose_req_cmd_payload_is_read;\nwire main_sdram_choose_req_cmd_payload_is_write;\nreg [3:0] main_sdram_choose_req_valids = 4'd0;\nwire [3:0] main_sdram_choose_req_request;\nreg [1:0] main_sdram_choose_req_grant = 2'd0;\nwire main_sdram_choose_req_ce;\nreg [12:0] main_sdram_nop_a = 13'd0;\nreg [1:0] main_sdram_nop_ba = 2'd0;\nreg [1:0] main_sdram_steerer_sel = 2'd0;\nreg main_sdram_steerer0 = 1'd1;\nreg main_sdram_steerer1 = 1'd1;\nwire main_sdram_trrdcon_valid;\nreg main_sdram_trrdcon_ready = 1'd0;\nreg main_sdram_trrdcon_count = 1'd0;\nwire main_sdram_tfawcon_valid;\nreg main_sdram_tfawcon_ready = 1'd1;\nwire main_sdram_tccdcon_valid;\nreg main_sdram_tccdcon_ready = 1'd0;\nreg main_sdram_tccdcon_count = 1'd0;\nwire main_sdram_twtrcon_valid;\nreg main_sdram_twtrcon_ready = 1'd0;\nreg [2:0] main_sdram_twtrcon_count = 3'd0;\nwire main_sdram_read_available;\nwire main_sdram_write_available;\nreg main_sdram_en0 = 1'd0;\nwire main_sdram_max_time0;\nreg [4:0] main_sdram_time0 = 5'd0;\nreg main_sdram_en1 = 1'd0;\nwire main_sdram_max_time1;\nreg [3:0] main_sdram_time1 = 4'd0;\nwire main_sdram_go_to_refresh;\nreg main_port_cmd_valid = 1'd0;\nwire main_port_cmd_ready;\nreg main_port_cmd_payload_we = 1'd0;\nreg [23:0] main_port_cmd_payload_addr = 24'd0;\nwire main_port_wdata_valid;\nwire main_port_wdata_ready;\nwire main_port_wdata_first;\nwire main_port_wdata_last;\nwire [15:0] main_port_wdata_payload_data;\nwire [1:0] main_port_wdata_payload_we;\nwire main_port_rdata_valid;\nwire main_port_rdata_ready;\nreg main_port_rdata_first = 1'd0;\nreg main_port_rdata_last = 1'd0;\nwire [15:0] main_port_rdata_payload_data;\nwire [29:0] main_wb_sdram_adr;\nwire [31:0] main_wb_sdram_dat_w;\nreg [31:0] main_wb_sdram_dat_r = 32'd0;\nwire [3:0] main_wb_sdram_sel;\nwire main_wb_sdram_cyc;\nwire main_wb_sdram_stb;\nreg main_wb_sdram_ack = 1'd0;\nwire main_wb_sdram_we;\nwire [2:0] main_wb_sdram_cti;\nwire [1:0] main_wb_sdram_bte;\nreg main_wb_sdram_err = 1'd0;\nwire [29:0] main_interface_adr;\nwire [127:0] main_interface_dat_w;\nwire [127:0] main_interface_dat_r;\nwire [15:0] main_interface_sel;\nreg main_interface_cyc = 1'd0;\nreg main_interface_stb = 1'd0;\nwire main_interface_ack;\nreg main_interface_we = 1'd0;\nwire [8:0] main_data_port_adr;\nwire [127:0] main_data_port_dat_r;\nreg [15:0] main_data_port_we = 16'd0;\nreg [127:0] main_data_port_dat_w = 128'd0;\nreg main_write_from_slave = 1'd0;\nreg [1:0] main_adr_offset_r = 2'd0;\nwire [8:0] main_tag_port_adr;\nwire [23:0] main_tag_port_dat_r;\nreg main_tag_port_we = 1'd0;\nwire [23:0] main_tag_port_dat_w;\nwire [22:0] main_tag_do_tag;\nwire main_tag_do_dirty;\nwire [22:0] main_tag_di_tag;\nreg main_tag_di_dirty = 1'd0;\nreg main_word_clr = 1'd0;\nreg main_word_inc = 1'd0;\nwire main_wishbone_bridge_flush;\nwire main_wishbone_bridge_cmd_valid;\nreg main_wishbone_bridge_cmd_ready = 1'd0;\nwire main_wishbone_bridge_cmd_last;\nwire main_wishbone_bridge_cmd_payload_we;\nwire [20:0] main_wishbone_bridge_cmd_payload_addr;\nwire main_wishbone_bridge_wdata_valid;\nwire main_wishbone_bridge_wdata_ready;\nreg main_wishbone_bridge_wdata_first = 1'd0;\nreg main_wishbone_bridge_wdata_last = 1'd0;\nwire [127:0] main_wishbone_bridge_wdata_payload_data;\nwire [15:0] main_wishbone_bridge_wdata_payload_we;\nwire main_wishbone_bridge_rdata_valid;\nwire main_wishbone_bridge_rdata_ready;\nwire main_wishbone_bridge_rdata_first;\nwire main_wishbone_bridge_rdata_last;\nwire [127:0] main_wishbone_bridge_rdata_payload_data;\nreg [2:0] main_wishbone_bridge_count = 3'd0;\nwire main_wishbone_bridge_wdata_converter_sink_valid;\nwire main_wishbone_bridge_wdata_converter_sink_ready;\nwire main_wishbone_bridge_wdata_converter_sink_first;\nwire main_wishbone_bridge_wdata_converter_sink_last;\nwire [127:0] main_wishbone_bridge_wdata_converter_sink_payload_data;\nwire [15:0] main_wishbone_bridge_wdata_converter_sink_payload_we;\nwire main_wishbone_bridge_wdata_converter_source_valid;\nwire main_wishbone_bridge_wdata_converter_source_ready;\nwire main_wishbone_bridge_wdata_converter_source_first;\nwire main_wishbone_bridge_wdata_converter_source_last;\nwire [15:0] main_wishbone_bridge_wdata_converter_source_payload_data;\nwire [1:0] main_wishbone_bridge_wdata_converter_source_payload_we;\nwire main_wishbone_bridge_wdata_converter_converter_sink_valid;\nwire main_wishbone_bridge_wdata_converter_converter_sink_ready;\nwire main_wishbone_bridge_wdata_converter_converter_sink_first;\nwire main_wishbone_bridge_wdata_converter_converter_sink_last;\nreg [143:0] main_wishbone_bridge_wdata_converter_converter_sink_payload_data = 144'd0;\nwire main_wishbone_bridge_wdata_converter_converter_source_valid;\nwire main_wishbone_bridge_wdata_converter_converter_source_ready;\nwire main_wishbone_bridge_wdata_converter_converter_source_first;\nwire main_wishbone_bridge_wdata_converter_converter_source_last;\nreg [17:0] main_wishbone_bridge_wdata_converter_converter_source_payload_data = 18'd0;\nwire main_wishbone_bridge_wdata_converter_converter_source_payload_valid_token_count;\nreg [2:0] main_wishbone_bridge_wdata_converter_converter_mux = 3'd0;\nwire main_wishbone_bridge_wdata_converter_converter_first;\nwire main_wishbone_bridge_wdata_converter_converter_last;\nwire main_wishbone_bridge_wdata_converter_source_source_valid;\nwire main_wishbone_bridge_wdata_converter_source_source_ready;\nwire main_wishbone_bridge_wdata_converter_source_source_first;\nwire main_wishbone_bridge_wdata_converter_source_source_last;\nwire [17:0] main_wishbone_bridge_wdata_converter_source_source_payload_data;\nwire main_wishbone_bridge_rdata_converter_sink_valid;\nwire main_wishbone_bridge_rdata_converter_sink_ready;\nwire main_wishbone_bridge_rdata_converter_sink_first;\nwire main_wishbone_bridge_rdata_converter_sink_last;\nwire [15:0] main_wishbone_bridge_rdata_converter_sink_payload_data;\nwire main_wishbone_bridge_rdata_converter_source_valid;\nwire main_wishbone_bridge_rdata_converter_source_ready;\nwire main_wishbone_bridge_rdata_converter_source_first;\nwire main_wishbone_bridge_rdata_converter_source_last;\nreg [127:0] main_wishbone_bridge_rdata_converter_source_payload_data = 128'd0;\nwire main_wishbone_bridge_rdata_converter_converter_sink_valid;\nwire main_wishbone_bridge_rdata_converter_converter_sink_ready;\nwire main_wishbone_bridge_rdata_converter_converter_sink_first;\nwire main_wishbone_bridge_rdata_converter_converter_sink_last;\nwire [15:0] main_wishbone_bridge_rdata_converter_converter_sink_payload_data;\nwire main_wishbone_bridge_rdata_converter_converter_source_valid;\nwire main_wishbone_bridge_rdata_converter_converter_source_ready;\nreg main_wishbone_bridge_rdata_converter_converter_source_first = 1'd0;\nreg main_wishbone_bridge_rdata_converter_converter_source_last = 1'd0;\nreg [127:0] main_wishbone_bridge_rdata_converter_converter_source_payload_data = 128'd0;\nreg [3:0] main_wishbone_bridge_rdata_converter_converter_source_payload_valid_token_count = 4'd0;\nreg [2:0] main_wishbone_bridge_rdata_converter_converter_demux = 3'd0;\nwire main_wishbone_bridge_rdata_converter_converter_load_part;\nreg main_wishbone_bridge_rdata_converter_converter_strobe_all = 1'd0;\nwire main_wishbone_bridge_rdata_converter_source_source_valid;\nwire main_wishbone_bridge_rdata_converter_source_source_ready;\nwire main_wishbone_bridge_rdata_converter_source_source_first;\nwire main_wishbone_bridge_rdata_converter_source_source_last;\nwire [127:0] main_wishbone_bridge_rdata_converter_source_source_payload_data;\nreg main_wishbone_bridge_cmd_consumed = 1'd0;\nreg main_wishbone_bridge_wdata_consumed = 1'd0;\nwire main_wishbone_bridge_ack_cmd;\nwire main_wishbone_bridge_ack_wdata;\nwire main_wishbone_bridge_ack_rdata;\nreg [7:0] main_storage = 8'd0;\nreg main_re = 1'd0;\nreg [7:0] main_chaser = 8'd0;\nreg main_mode = 1'd0;\nwire main_wait;\nwire main_done;\nreg [21:0] main_count = 22'd3125000;\nwire soclinux_start0;\nwire [7:0] soclinux_length0;\nreg soclinux_done0 = 1'd0;\nreg soclinux_irq = 1'd0;\nwire [7:0] soclinux_mosi;\nreg [7:0] soclinux_miso = 8'd0;\nwire soclinux_cs;\nwire soclinux_loopback;\nwire [15:0] soclinux_clk_divider0;\nreg soclinux_start1 = 1'd0;\nwire [7:0] soclinux_length1;\nreg [15:0] soclinux_control_storage = 16'd0;\nreg soclinux_control_re = 1'd0;\nwire soclinux_done1;\nwire soclinux_status_status;\nwire soclinux_status_we;\nwire soclinux_status_re;\nreg [7:0] soclinux_mosi_storage = 8'd0;\nreg soclinux_mosi_re = 1'd0;\nwire [7:0] soclinux_miso_status;\nwire soclinux_miso_we;\nwire soclinux_miso_re;\nwire soclinux_sel;\nreg soclinux_cs_storage = 1'd1;\nreg soclinux_cs_re = 1'd0;\nreg soclinux_loopback_storage = 1'd0;\nreg soclinux_loopback_re = 1'd0;\nreg soclinux_clk_enable = 1'd0;\nreg soclinux_cs_enable = 1'd0;\nreg [2:0] soclinux_count = 3'd0;\nreg soclinux_mosi_latch = 1'd0;\nreg soclinux_miso_latch = 1'd0;\nreg [15:0] soclinux_clk_divider1 = 16'd0;\nwire soclinux_clk_rise;\nwire soclinux_clk_fall;\nreg [7:0] soclinux_mosi_data = 8'd0;\nreg [2:0] soclinux_mosi_sel = 3'd0;\nreg [7:0] soclinux_miso_data = 8'd0;\nreg [15:0] soclinux_storage = 16'd125;\nreg soclinux_re = 1'd0;\nreg [1:0] builder_refresher_state = 2'd0;\nreg [1:0] builder_refresher_next_state = 2'd0;\nreg [2:0] builder_bankmachine0_state = 3'd0;\nreg [2:0] builder_bankmachine0_next_state = 3'd0;\nreg [2:0] builder_bankmachine1_state = 3'd0;\nreg [2:0] builder_bankmachine1_next_state = 3'd0;\nreg [2:0] builder_bankmachine2_state = 3'd0;\nreg [2:0] builder_bankmachine2_next_state = 3'd0;\nreg [2:0] builder_bankmachine3_state = 3'd0;\nreg [2:0] builder_bankmachine3_next_state = 3'd0;\nreg [2:0] builder_multiplexer_state = 3'd0;\nreg [2:0] builder_multiplexer_next_state = 3'd0;\nwire builder_roundrobin0_request;\nwire builder_roundrobin0_grant;\nwire builder_roundrobin0_ce;\nwire builder_roundrobin1_request;\nwire builder_roundrobin1_grant;\nwire builder_roundrobin1_ce;\nwire builder_roundrobin2_request;\nwire builder_roundrobin2_grant;\nwire builder_roundrobin2_ce;\nwire builder_roundrobin3_request;\nwire builder_roundrobin3_grant;\nwire builder_roundrobin3_ce;\nreg builder_locked0 = 1'd0;\nreg builder_locked1 = 1'd0;\nreg builder_locked2 = 1'd0;\nreg builder_locked3 = 1'd0;\nreg builder_new_master_wdata_ready = 1'd0;\nreg builder_new_master_rdata_valid0 = 1'd0;\nreg builder_new_master_rdata_valid1 = 1'd0;\nreg builder_new_master_rdata_valid2 = 1'd0;\nreg builder_new_master_rdata_valid3 = 1'd0;\nreg [1:0] builder_fullmemorywe_state = 2'd0;\nreg [1:0] builder_fullmemorywe_next_state = 2'd0;\nreg builder_litedramwishbone2native_state = 1'd0;\nreg builder_litedramwishbone2native_next_state = 1'd0;\nreg [2:0] main_wishbone_bridge_count_litedramwishbone2native_next_value = 3'd0;\nreg main_wishbone_bridge_count_litedramwishbone2native_next_value_ce = 1'd0;\nreg [1:0] builder_spimaster_state = 2'd0;\nreg [1:0] builder_spimaster_next_state = 2'd0;\nreg [2:0] soclinux_count_spimaster_next_value = 3'd0;\nreg soclinux_count_spimaster_next_value_ce = 1'd0;\nreg [13:0] builder_soclinux_adr = 14'd0;\nreg builder_soclinux_we = 1'd0;\nreg [7:0] builder_soclinux_dat_w = 8'd0;\nwire [7:0] builder_soclinux_dat_r;\nwire [29:0] builder_soclinux_wishbone_adr;\nwire [31:0] builder_soclinux_wishbone_dat_w;\nreg [31:0] builder_soclinux_wishbone_dat_r = 32'd0;\nwire [3:0] builder_soclinux_wishbone_sel;\nwire builder_soclinux_wishbone_cyc;\nwire builder_soclinux_wishbone_stb;\nreg builder_soclinux_wishbone_ack = 1'd0;\nwire builder_soclinux_wishbone_we;\nwire [2:0] builder_soclinux_wishbone_cti;\nwire [1:0] builder_soclinux_wishbone_bte;\nreg builder_soclinux_wishbone_err = 1'd0;\nwire [29:0] builder_shared_adr;\nwire [31:0] builder_shared_dat_w;\nreg [31:0] builder_shared_dat_r = 32'd0;\nwire [3:0] builder_shared_sel;\nwire builder_shared_cyc;\nwire builder_shared_stb;\nreg builder_shared_ack = 1'd0;\nwire builder_shared_we;\nwire [2:0] builder_shared_cti;\nwire [1:0] builder_shared_bte;\nwire builder_shared_err;\nwire [1:0] builder_request;\nreg builder_grant = 1'd0;\nreg [3:0] builder_slave_sel = 4'd0;\nreg [3:0] builder_slave_sel_r = 4'd0;\nreg builder_error = 1'd0;\nwire builder_wait;\nwire builder_done;\nreg [19:0] builder_count = 20'd1000000;\nwire [13:0] builder_csr_bankarray_interface0_bank_bus_adr;\nwire builder_csr_bankarray_interface0_bank_bus_we;\nwire [7:0] builder_csr_bankarray_interface0_bank_bus_dat_w;\nreg [7:0] builder_csr_bankarray_interface0_bank_bus_dat_r = 8'd0;\nwire builder_csr_bankarray_csrbank0_timer_time7_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time7_r;\nwire builder_csr_bankarray_csrbank0_timer_time7_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time7_w;\nwire builder_csr_bankarray_csrbank0_timer_time6_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time6_r;\nwire builder_csr_bankarray_csrbank0_timer_time6_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time6_w;\nwire builder_csr_bankarray_csrbank0_timer_time5_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time5_r;\nwire builder_csr_bankarray_csrbank0_timer_time5_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time5_w;\nwire builder_csr_bankarray_csrbank0_timer_time4_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time4_r;\nwire builder_csr_bankarray_csrbank0_timer_time4_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time4_w;\nwire builder_csr_bankarray_csrbank0_timer_time3_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time3_r;\nwire builder_csr_bankarray_csrbank0_timer_time3_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time3_w;\nwire builder_csr_bankarray_csrbank0_timer_time2_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time2_r;\nwire builder_csr_bankarray_csrbank0_timer_time2_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time2_w;\nwire builder_csr_bankarray_csrbank0_timer_time1_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time1_r;\nwire builder_csr_bankarray_csrbank0_timer_time1_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time1_w;\nwire builder_csr_bankarray_csrbank0_timer_time0_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time0_r;\nwire builder_csr_bankarray_csrbank0_timer_time0_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time0_w;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp7_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp7_r;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp7_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp7_w;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp6_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp6_r;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp6_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp6_w;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp5_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp5_r;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp5_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp5_w;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp4_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp4_r;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp4_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp4_w;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp3_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp3_r;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp3_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp3_w;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp2_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp2_r;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp2_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp2_w;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp1_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp1_r;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp1_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp1_w;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp0_re;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp0_r;\nwire builder_csr_bankarray_csrbank0_timer_time_cmp0_we;\nwire [7:0] builder_csr_bankarray_csrbank0_timer_time_cmp0_w;\nwire builder_csr_bankarray_csrbank0_sel;\nwire [13:0] builder_csr_bankarray_interface1_bank_bus_adr;\nwire builder_csr_bankarray_interface1_bank_bus_we;\nwire [7:0] builder_csr_bankarray_interface1_bank_bus_dat_w;\nreg [7:0] builder_csr_bankarray_interface1_bank_bus_dat_r = 8'd0;\nwire builder_csr_bankarray_csrbank1_reset0_re;\nwire builder_csr_bankarray_csrbank1_reset0_r;\nwire builder_csr_bankarray_csrbank1_reset0_we;\nwire builder_csr_bankarray_csrbank1_reset0_w;\nwire builder_csr_bankarray_csrbank1_scratch3_re;\nwire [7:0] builder_csr_bankarray_csrbank1_scratch3_r;\nwire builder_csr_bankarray_csrbank1_scratch3_we;\nwire [7:0] builder_csr_bankarray_csrbank1_scratch3_w;\nwire builder_csr_bankarray_csrbank1_scratch2_re;\nwire [7:0] builder_csr_bankarray_csrbank1_scratch2_r;\nwire builder_csr_bankarray_csrbank1_scratch2_we;\nwire [7:0] builder_csr_bankarray_csrbank1_scratch2_w;\nwire builder_csr_bankarray_csrbank1_scratch1_re;\nwire [7:0] builder_csr_bankarray_csrbank1_scratch1_r;\nwire builder_csr_bankarray_csrbank1_scratch1_we;\nwire [7:0] builder_csr_bankarray_csrbank1_scratch1_w;\nwire builder_csr_bankarray_csrbank1_scratch0_re;\nwire [7:0] builder_csr_bankarray_csrbank1_scratch0_r;\nwire builder_csr_bankarray_csrbank1_scratch0_we;\nwire [7:0] builder_csr_bankarray_csrbank1_scratch0_w;\nwire builder_csr_bankarray_csrbank1_bus_errors3_re;\nwire [7:0] builder_csr_bankarray_csrbank1_bus_errors3_r;\nwire builder_csr_bankarray_csrbank1_bus_errors3_we;\nwire [7:0] builder_csr_bankarray_csrbank1_bus_errors3_w;\nwire builder_csr_bankarray_csrbank1_bus_errors2_re;\nwire [7:0] builder_csr_bankarray_csrbank1_bus_errors2_r;\nwire builder_csr_bankarray_csrbank1_bus_errors2_we;\nwire [7:0] builder_csr_bankarray_csrbank1_bus_errors2_w;\nwire builder_csr_bankarray_csrbank1_bus_errors1_re;\nwire [7:0] builder_csr_bankarray_csrbank1_bus_errors1_r;\nwire builder_csr_bankarray_csrbank1_bus_errors1_we;\nwire [7:0] builder_csr_bankarray_csrbank1_bus_errors1_w;\nwire builder_csr_bankarray_csrbank1_bus_errors0_re;\nwire [7:0] builder_csr_bankarray_csrbank1_bus_errors0_r;\nwire builder_csr_bankarray_csrbank1_bus_errors0_we;\nwire [7:0] builder_csr_bankarray_csrbank1_bus_errors0_w;\nwire builder_csr_bankarray_csrbank1_sel;\nwire [13:0] builder_csr_bankarray_sram_bus_adr;\nwire builder_csr_bankarray_sram_bus_we;\nwire [7:0] builder_csr_bankarray_sram_bus_dat_w;\nreg [7:0] builder_csr_bankarray_sram_bus_dat_r = 8'd0;\nwire [5:0] builder_csr_bankarray_adr;\nwire [7:0] builder_csr_bankarray_dat_r;\nwire builder_csr_bankarray_sel;\nreg builder_csr_bankarray_sel_r = 1'd0;\nwire [13:0] builder_csr_bankarray_interface2_bank_bus_adr;\nwire builder_csr_bankarray_interface2_bank_bus_we;\nwire [7:0] builder_csr_bankarray_interface2_bank_bus_dat_w;\nreg [7:0] builder_csr_bankarray_interface2_bank_bus_dat_r = 8'd0;\nwire builder_csr_bankarray_csrbank2_out0_re;\nwire [7:0] builder_csr_bankarray_csrbank2_out0_r;\nwire builder_csr_bankarray_csrbank2_out0_we;\nwire [7:0] builder_csr_bankarray_csrbank2_out0_w;\nwire builder_csr_bankarray_csrbank2_sel;\nwire [13:0] builder_csr_bankarray_interface3_bank_bus_adr;\nwire builder_csr_bankarray_interface3_bank_bus_we;\nwire [7:0] builder_csr_bankarray_interface3_bank_bus_dat_w;\nreg [7:0] builder_csr_bankarray_interface3_bank_bus_dat_r = 8'd0;\nwire builder_csr_bankarray_csrbank3_dfii_control0_re;\nwire [3:0] builder_csr_bankarray_csrbank3_dfii_control0_r;\nwire builder_csr_bankarray_csrbank3_dfii_control0_we;\nwire [3:0] builder_csr_bankarray_csrbank3_dfii_control0_w;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_command0_re;\nwire [5:0] builder_csr_bankarray_csrbank3_dfii_pi0_command0_r;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_command0_we;\nwire [5:0] builder_csr_bankarray_csrbank3_dfii_pi0_command0_w;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_address1_re;\nwire [4:0] builder_csr_bankarray_csrbank3_dfii_pi0_address1_r;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_address1_we;\nwire [4:0] builder_csr_bankarray_csrbank3_dfii_pi0_address1_w;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_address0_re;\nwire [7:0] builder_csr_bankarray_csrbank3_dfii_pi0_address0_r;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_address0_we;\nwire [7:0] builder_csr_bankarray_csrbank3_dfii_pi0_address0_w;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_baddress0_re;\nwire [1:0] builder_csr_bankarray_csrbank3_dfii_pi0_baddress0_r;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_baddress0_we;\nwire [1:0] builder_csr_bankarray_csrbank3_dfii_pi0_baddress0_w;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_wrdata1_re;\nwire [7:0] builder_csr_bankarray_csrbank3_dfii_pi0_wrdata1_r;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_wrdata1_we;\nwire [7:0] builder_csr_bankarray_csrbank3_dfii_pi0_wrdata1_w;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_wrdata0_re;\nwire [7:0] builder_csr_bankarray_csrbank3_dfii_pi0_wrdata0_r;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_wrdata0_we;\nwire [7:0] builder_csr_bankarray_csrbank3_dfii_pi0_wrdata0_w;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_rddata1_re;\nwire [7:0] builder_csr_bankarray_csrbank3_dfii_pi0_rddata1_r;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_rddata1_we;\nwire [7:0] builder_csr_bankarray_csrbank3_dfii_pi0_rddata1_w;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_rddata0_re;\nwire [7:0] builder_csr_bankarray_csrbank3_dfii_pi0_rddata0_r;\nwire builder_csr_bankarray_csrbank3_dfii_pi0_rddata0_we;\nwire [7:0] builder_csr_bankarray_csrbank3_dfii_pi0_rddata0_w;\nwire builder_csr_bankarray_csrbank3_sel;\nwire [13:0] builder_csr_bankarray_interface4_bank_bus_adr;\nwire builder_csr_bankarray_interface4_bank_bus_we;\nwire [7:0] builder_csr_bankarray_interface4_bank_bus_dat_w;\nreg [7:0] builder_csr_bankarray_interface4_bank_bus_dat_r = 8'd0;\nwire builder_csr_bankarray_csrbank4_control1_re;\nwire [7:0] builder_csr_bankarray_csrbank4_control1_r;\nwire builder_csr_bankarray_csrbank4_control1_we;\nwire [7:0] builder_csr_bankarray_csrbank4_control1_w;\nwire builder_csr_bankarray_csrbank4_control0_re;\nwire [7:0] builder_csr_bankarray_csrbank4_control0_r;\nwire builder_csr_bankarray_csrbank4_control0_we;\nwire [7:0] builder_csr_bankarray_csrbank4_control0_w;\nwire builder_csr_bankarray_csrbank4_status_re;\nwire builder_csr_bankarray_csrbank4_status_r;\nwire builder_csr_bankarray_csrbank4_status_we;\nwire builder_csr_bankarray_csrbank4_status_w;\nwire builder_csr_bankarray_csrbank4_mosi0_re;\nwire [7:0] builder_csr_bankarray_csrbank4_mosi0_r;\nwire builder_csr_bankarray_csrbank4_mosi0_we;\nwire [7:0] builder_csr_bankarray_csrbank4_mosi0_w;\nwire builder_csr_bankarray_csrbank4_miso_re;\nwire [7:0] builder_csr_bankarray_csrbank4_miso_r;\nwire builder_csr_bankarray_csrbank4_miso_we;\nwire [7:0] builder_csr_bankarray_csrbank4_miso_w;\nwire builder_csr_bankarray_csrbank4_cs0_re;\nwire builder_csr_bankarray_csrbank4_cs0_r;\nwire builder_csr_bankarray_csrbank4_cs0_we;\nwire builder_csr_bankarray_csrbank4_cs0_w;\nwire builder_csr_bankarray_csrbank4_loopback0_re;\nwire builder_csr_bankarray_csrbank4_loopback0_r;\nwire builder_csr_bankarray_csrbank4_loopback0_we;\nwire builder_csr_bankarray_csrbank4_loopback0_w;\nwire builder_csr_bankarray_csrbank4_clk_divider1_re;\nwire [7:0] builder_csr_bankarray_csrbank4_clk_divider1_r;\nwire builder_csr_bankarray_csrbank4_clk_divider1_we;\nwire [7:0] builder_csr_bankarray_csrbank4_clk_divider1_w;\nwire builder_csr_bankarray_csrbank4_clk_divider0_re;\nwire [7:0] builder_csr_bankarray_csrbank4_clk_divider0_r;\nwire builder_csr_bankarray_csrbank4_clk_divider0_we;\nwire [7:0] builder_csr_bankarray_csrbank4_clk_divider0_w;\nwire builder_csr_bankarray_csrbank4_sel;\nwire [13:0] builder_csr_bankarray_interface5_bank_bus_adr;\nwire builder_csr_bankarray_interface5_bank_bus_we;\nwire [7:0] builder_csr_bankarray_interface5_bank_bus_dat_w;\nreg [7:0] builder_csr_bankarray_interface5_bank_bus_dat_r = 8'd0;\nwire builder_csr_bankarray_csrbank5_load3_re;\nwire [7:0] builder_csr_bankarray_csrbank5_load3_r;\nwire builder_csr_bankarray_csrbank5_load3_we;\nwire [7:0] builder_csr_bankarray_csrbank5_load3_w;\nwire builder_csr_bankarray_csrbank5_load2_re;\nwire [7:0] builder_csr_bankarray_csrbank5_load2_r;\nwire builder_csr_bankarray_csrbank5_load2_we;\nwire [7:0] builder_csr_bankarray_csrbank5_load2_w;\nwire builder_csr_bankarray_csrbank5_load1_re;\nwire [7:0] builder_csr_bankarray_csrbank5_load1_r;\nwire builder_csr_bankarray_csrbank5_load1_we;\nwire [7:0] builder_csr_bankarray_csrbank5_load1_w;\nwire builder_csr_bankarray_csrbank5_load0_re;\nwire [7:0] builder_csr_bankarray_csrbank5_load0_r;\nwire builder_csr_bankarray_csrbank5_load0_we;\nwire [7:0] builder_csr_bankarray_csrbank5_load0_w;\nwire builder_csr_bankarray_csrbank5_reload3_re;\nwire [7:0] builder_csr_bankarray_csrbank5_reload3_r;\nwire builder_csr_bankarray_csrbank5_reload3_we;\nwire [7:0] builder_csr_bankarray_csrbank5_reload3_w;\nwire builder_csr_bankarray_csrbank5_reload2_re;\nwire [7:0] builder_csr_bankarray_csrbank5_reload2_r;\nwire builder_csr_bankarray_csrbank5_reload2_we;\nwire [7:0] builder_csr_bankarray_csrbank5_reload2_w;\nwire builder_csr_bankarray_csrbank5_reload1_re;\nwire [7:0] builder_csr_bankarray_csrbank5_reload1_r;\nwire builder_csr_bankarray_csrbank5_reload1_we;\nwire [7:0] builder_csr_bankarray_csrbank5_reload1_w;\nwire builder_csr_bankarray_csrbank5_reload0_re;\nwire [7:0] builder_csr_bankarray_csrbank5_reload0_r;\nwire builder_csr_bankarray_csrbank5_reload0_we;\nwire [7:0] builder_csr_bankarray_csrbank5_reload0_w;\nwire builder_csr_bankarray_csrbank5_en0_re;\nwire builder_csr_bankarray_csrbank5_en0_r;\nwire builder_csr_bankarray_csrbank5_en0_we;\nwire builder_csr_bankarray_csrbank5_en0_w;\nwire builder_csr_bankarray_csrbank5_update_value0_re;\nwire builder_csr_bankarray_csrbank5_update_value0_r;\nwire builder_csr_bankarray_csrbank5_update_value0_we;\nwire builder_csr_bankarray_csrbank5_update_value0_w;\nwire builder_csr_bankarray_csrbank5_value3_re;\nwire [7:0] builder_csr_bankarray_csrbank5_value3_r;\nwire builder_csr_bankarray_csrbank5_value3_we;\nwire [7:0] builder_csr_bankarray_csrbank5_value3_w;\nwire builder_csr_bankarray_csrbank5_value2_re;\nwire [7:0] builder_csr_bankarray_csrbank5_value2_r;\nwire builder_csr_bankarray_csrbank5_value2_we;\nwire [7:0] builder_csr_bankarray_csrbank5_value2_w;\nwire builder_csr_bankarray_csrbank5_value1_re;\nwire [7:0] builder_csr_bankarray_csrbank5_value1_r;\nwire builder_csr_bankarray_csrbank5_value1_we;\nwire [7:0] builder_csr_bankarray_csrbank5_value1_w;\nwire builder_csr_bankarray_csrbank5_value0_re;\nwire [7:0] builder_csr_bankarray_csrbank5_value0_r;\nwire builder_csr_bankarray_csrbank5_value0_we;\nwire [7:0] builder_csr_bankarray_csrbank5_value0_w;\nwire builder_csr_bankarray_csrbank5_ev_enable0_re;\nwire builder_csr_bankarray_csrbank5_ev_enable0_r;\nwire builder_csr_bankarray_csrbank5_ev_enable0_we;\nwire builder_csr_bankarray_csrbank5_ev_enable0_w;\nwire builder_csr_bankarray_csrbank5_sel;\nwire [13:0] builder_csr_bankarray_interface6_bank_bus_adr;\nwire builder_csr_bankarray_interface6_bank_bus_we;\nwire [7:0] builder_csr_bankarray_interface6_bank_bus_dat_w;\nreg [7:0] builder_csr_bankarray_interface6_bank_bus_dat_r = 8'd0;\nwire builder_csr_bankarray_csrbank6_txfull_re;\nwire builder_csr_bankarray_csrbank6_txfull_r;\nwire builder_csr_bankarray_csrbank6_txfull_we;\nwire builder_csr_bankarray_csrbank6_txfull_w;\nwire builder_csr_bankarray_csrbank6_rxempty_re;\nwire builder_csr_bankarray_csrbank6_rxempty_r;\nwire builder_csr_bankarray_csrbank6_rxempty_we;\nwire builder_csr_bankarray_csrbank6_rxempty_w;\nwire builder_csr_bankarray_csrbank6_ev_enable0_re;\nwire [1:0] builder_csr_bankarray_csrbank6_ev_enable0_r;\nwire builder_csr_bankarray_csrbank6_ev_enable0_we;\nwire [1:0] builder_csr_bankarray_csrbank6_ev_enable0_w;\nwire builder_csr_bankarray_csrbank6_txempty_re;\nwire builder_csr_bankarray_csrbank6_txempty_r;\nwire builder_csr_bankarray_csrbank6_txempty_we;\nwire builder_csr_bankarray_csrbank6_txempty_w;\nwire builder_csr_bankarray_csrbank6_rxfull_re;\nwire builder_csr_bankarray_csrbank6_rxfull_r;\nwire builder_csr_bankarray_csrbank6_rxfull_we;\nwire builder_csr_bankarray_csrbank6_rxfull_w;\nwire builder_csr_bankarray_csrbank6_sel;\nwire [13:0] builder_csr_bankarray_interface7_bank_bus_adr;\nwire builder_csr_bankarray_interface7_bank_bus_we;\nwire [7:0] builder_csr_bankarray_interface7_bank_bus_dat_w;\nreg [7:0] builder_csr_bankarray_interface7_bank_bus_dat_r = 8'd0;\nwire builder_csr_bankarray_csrbank7_tuning_word3_re;\nwire [7:0] builder_csr_bankarray_csrbank7_tuning_word3_r;\nwire builder_csr_bankarray_csrbank7_tuning_word3_we;\nwire [7:0] builder_csr_bankarray_csrbank7_tuning_word3_w;\nwire builder_csr_bankarray_csrbank7_tuning_word2_re;\nwire [7:0] builder_csr_bankarray_csrbank7_tuning_word2_r;\nwire builder_csr_bankarray_csrbank7_tuning_word2_we;\nwire [7:0] builder_csr_bankarray_csrbank7_tuning_word2_w;\nwire builder_csr_bankarray_csrbank7_tuning_word1_re;\nwire [7:0] builder_csr_bankarray_csrbank7_tuning_word1_r;\nwire builder_csr_bankarray_csrbank7_tuning_word1_we;\nwire [7:0] builder_csr_bankarray_csrbank7_tuning_word1_w;\nwire builder_csr_bankarray_csrbank7_tuning_word0_re;\nwire [7:0] builder_csr_bankarray_csrbank7_tuning_word0_r;\nwire builder_csr_bankarray_csrbank7_tuning_word0_we;\nwire [7:0] builder_csr_bankarray_csrbank7_tuning_word0_w;\nwire builder_csr_bankarray_csrbank7_sel;\nwire [13:0] builder_csr_interconnect_adr;\nwire builder_csr_interconnect_we;\nwire [7:0] builder_csr_interconnect_dat_w;\nwire [7:0] builder_csr_interconnect_dat_r;\nreg [1:0] builder_state = 2'd0;\nreg [1:0] builder_next_state = 2'd0;\nreg [7:0] builder_soclinux_dat_w_next_value0 = 8'd0;\nreg builder_soclinux_dat_w_next_value_ce0 = 1'd0;\nreg [13:0] builder_soclinux_adr_next_value1 = 14'd0;\nreg builder_soclinux_adr_next_value_ce1 = 1'd0;\nreg builder_soclinux_we_next_value2 = 1'd0;\nreg builder_soclinux_we_next_value_ce2 = 1'd0;\nreg builder_comb_rhs_array_muxed0 = 1'd0;\nreg [12:0] builder_comb_rhs_array_muxed1 = 13'd0;\nreg [1:0] builder_comb_rhs_array_muxed2 = 2'd0;\nreg builder_comb_rhs_array_muxed3 = 1'd0;\nreg builder_comb_rhs_array_muxed4 = 1'd0;\nreg builder_comb_rhs_array_muxed5 = 1'd0;\nreg builder_comb_t_array_muxed0 = 1'd0;\nreg builder_comb_t_array_muxed1 = 1'd0;\nreg builder_comb_t_array_muxed2 = 1'd0;\nreg builder_comb_rhs_array_muxed6 = 1'd0;\nreg [12:0] builder_comb_rhs_array_muxed7 = 13'd0;\nreg [1:0] builder_comb_rhs_array_muxed8 = 2'd0;\nreg builder_comb_rhs_array_muxed9 = 1'd0;\nreg builder_comb_rhs_array_muxed10 = 1'd0;\nreg builder_comb_rhs_array_muxed11 = 1'd0;\nreg builder_comb_t_array_muxed3 = 1'd0;\nreg builder_comb_t_array_muxed4 = 1'd0;\nreg builder_comb_t_array_muxed5 = 1'd0;\nreg [21:0] builder_comb_rhs_array_muxed12 = 22'd0;\nreg builder_comb_rhs_array_muxed13 = 1'd0;\nreg builder_comb_rhs_array_muxed14 = 1'd0;\nreg [21:0] builder_comb_rhs_array_muxed15 = 22'd0;\nreg builder_comb_rhs_array_muxed16 = 1'd0;\nreg builder_comb_rhs_array_muxed17 = 1'd0;\nreg [21:0] builder_comb_rhs_array_muxed18 = 22'd0;\nreg builder_comb_rhs_array_muxed19 = 1'd0;\nreg builder_comb_rhs_array_muxed20 = 1'd0;\nreg [21:0] builder_comb_rhs_array_muxed21 = 22'd0;\nreg builder_comb_rhs_array_muxed22 = 1'd0;\nreg builder_comb_rhs_array_muxed23 = 1'd0;\nreg [29:0] builder_comb_rhs_array_muxed24 = 30'd0;\nreg [31:0] builder_comb_rhs_array_muxed25 = 32'd0;\nreg [3:0] builder_comb_rhs_array_muxed26 = 4'd0;\nreg builder_comb_rhs_array_muxed27 = 1'd0;\nreg builder_comb_rhs_array_muxed28 = 1'd0;\nreg builder_comb_rhs_array_muxed29 = 1'd0;\nreg [2:0] builder_comb_rhs_array_muxed30 = 3'd0;\nreg [1:0] builder_comb_rhs_array_muxed31 = 2'd0;\nreg [1:0] builder_sync_rhs_array_muxed0 = 2'd0;\nreg [12:0] builder_sync_rhs_array_muxed1 = 13'd0;\nreg builder_sync_rhs_array_muxed2 = 1'd0;\nreg builder_sync_rhs_array_muxed3 = 1'd0;\nreg builder_sync_rhs_array_muxed4 = 1'd0;\nreg builder_sync_rhs_array_muxed5 = 1'd0;\nreg builder_sync_rhs_array_muxed6 = 1'd0;\nreg builder_sync_f_array_muxed = 1'd0;\nreg builder_regs0 = 1'd0;\nreg builder_regs1 = 1'd0;\nwire builder_latticeecp5asyncresetsynchronizerimpl0_rst1;\nwire builder_latticeecp5asyncresetsynchronizerimpl1_rst1;\nwire builder_latticeecp5asyncresetsynchronizerimpl1_expr;\nwire builder_inferedsdrtristate0__o;\nreg builder_inferedsdrtristate0_oe = 1'd0;\nwire builder_inferedsdrtristate0__i;\nwire sdrio_clk;\nwire builder_inferedsdrtristate1__o;\nreg builder_inferedsdrtristate1_oe = 1'd0;\nwire builder_inferedsdrtristate1__i;\nwire sdrio_clk_1;\nwire builder_inferedsdrtristate2__o;\nreg builder_inferedsdrtristate2_oe = 1'd0;\nwire builder_inferedsdrtristate2__i;\nwire sdrio_clk_2;\nwire builder_inferedsdrtristate3__o;\nreg builder_inferedsdrtristate3_oe = 1'd0;\nwire builder_inferedsdrtristate3__i;\nwire sdrio_clk_3;\nwire builder_inferedsdrtristate4__o;\nreg builder_inferedsdrtristate4_oe = 1'd0;\nwire builder_inferedsdrtristate4__i;\nwire sdrio_clk_4;\nwire builder_inferedsdrtristate5__o;\nreg builder_inferedsdrtristate5_oe = 1'd0;\nwire builder_inferedsdrtristate5__i;\nwire sdrio_clk_5;\nwire builder_inferedsdrtristate6__o;\nreg builder_inferedsdrtristate6_oe = 1'd0;\nwire builder_inferedsdrtristate6__i;\nwire sdrio_clk_6;\nwire builder_inferedsdrtristate7__o;\nreg builder_inferedsdrtristate7_oe = 1'd0;\nwire builder_inferedsdrtristate7__i;\nwire sdrio_clk_7;\nwire builder_inferedsdrtristate8__o;\nreg builder_inferedsdrtristate8_oe = 1'd0;\nwire builder_inferedsdrtristate8__i;\nwire sdrio_clk_8;\nwire builder_inferedsdrtristate9__o;\nreg builder_inferedsdrtristate9_oe = 1'd0;\nwire builder_inferedsdrtristate9__i;\nwire sdrio_clk_9;\nwire builder_inferedsdrtristate10__o;\nreg builder_inferedsdrtristate10_oe = 1'd0;\nwire builder_inferedsdrtristate10__i;\nwire sdrio_clk_10;\nwire builder_inferedsdrtristate11__o;\nreg builder_inferedsdrtristate11_oe = 1'd0;\nwire builder_inferedsdrtristate11__i;\nwire sdrio_clk_11;\nwire builder_inferedsdrtristate12__o;\nreg builder_inferedsdrtristate12_oe = 1'd0;\nwire builder_inferedsdrtristate12__i;\nwire sdrio_clk_12;\nwire builder_inferedsdrtristate13__o;\nreg builder_inferedsdrtristate13_oe = 1'd0;\nwire builder_inferedsdrtristate13__i;\nwire sdrio_clk_13;\nwire builder_inferedsdrtristate14__o;\nreg builder_inferedsdrtristate14_oe = 1'd0;\nwire builder_inferedsdrtristate14__i;\nwire sdrio_clk_14;\nwire builder_inferedsdrtristate15__o;\nreg builder_inferedsdrtristate15_oe = 1'd0;\nwire builder_inferedsdrtristate15__i;\nwire sdrio_clk_15;\n\nassign main_soclinux_cpu_reset = main_soclinux_soccontroller_reset;\nassign main_rst = main_soclinux_soccontroller_reset_re;\nassign main_soclinux_soccontroller_bus_error = builder_error;\nalways @(*) begin\n\tmain_soclinux_cpu_interrupt0 <= 32'd0;\n\tmain_soclinux_cpu_interrupt0[1] <= main_soclinux_timer_irq;\n\tmain_soclinux_cpu_interrupt0[0] <= main_soclinux_uart_irq;\nend\nassign main_soclinux_soccontroller_reset = main_soclinux_soccontroller_reset_re;\nassign main_soclinux_soccontroller_bus_errors_status = main_soclinux_soccontroller_bus_errors;\nassign main_soclinux_cpu_interrupt1 = (main_soclinux_cpu_time >= main_soclinux_cpu_time_cmp);\nassign main_soclinux_soclinux_adr = main_soclinux_soclinux_ram_bus_adr[13:0];\nassign main_soclinux_soclinux_ram_bus_dat_r = main_soclinux_soclinux_dat_r;\nalways @(*) begin\n\tmain_soclinux_ram_we <= 4'd0;\n\tmain_soclinux_ram_we[0] <= (((main_soclinux_ram_bus_ram_bus_cyc & main_soclinux_ram_bus_ram_bus_stb) & main_soclinux_ram_bus_ram_bus_we) & main_soclinux_ram_bus_ram_bus_sel[0]);\n\tmain_soclinux_ram_we[1] <= (((main_soclinux_ram_bus_ram_bus_cyc & main_soclinux_ram_bus_ram_bus_stb) & main_soclinux_ram_bus_ram_bus_we) & main_soclinux_ram_bus_ram_bus_sel[1]);\n\tmain_soclinux_ram_we[2] <= (((main_soclinux_ram_bus_ram_bus_cyc & main_soclinux_ram_bus_ram_bus_stb) & main_soclinux_ram_bus_ram_bus_we) & main_soclinux_ram_bus_ram_bus_sel[2]);\n\tmain_soclinux_ram_we[3] <= (((main_soclinux_ram_bus_ram_bus_cyc & main_soclinux_ram_bus_ram_bus_stb) & main_soclinux_ram_bus_ram_bus_we) & main_soclinux_ram_bus_ram_bus_sel[3]);\nend\nassign main_soclinux_ram_adr = main_soclinux_ram_bus_ram_bus_adr[10:0];\nassign main_soclinux_ram_bus_ram_bus_dat_r = main_soclinux_ram_dat_r;\nassign main_soclinux_ram_dat_w = main_soclinux_ram_bus_ram_bus_dat_w;\nassign main_soclinux_uart_uart_sink_valid = main_soclinux_source_valid;\nassign main_soclinux_source_ready = main_soclinux_uart_uart_sink_ready;\nassign main_soclinux_uart_uart_sink_first = main_soclinux_source_first;\nassign main_soclinux_uart_uart_sink_last = main_soclinux_source_last;\nassign main_soclinux_uart_uart_sink_payload_data = main_soclinux_source_payload_data;\nassign main_soclinux_sink_valid = main_soclinux_uart_uart_source_valid;\nassign main_soclinux_uart_uart_source_ready = main_soclinux_sink_ready;\nassign main_soclinux_sink_first = main_soclinux_uart_uart_source_first;\nassign main_soclinux_sink_last = main_soclinux_uart_uart_source_last;\nassign main_soclinux_sink_payload_data = main_soclinux_uart_uart_source_payload_data;\nassign main_soclinux_uart_tx_fifo_sink_valid = main_soclinux_uart_rxtx_re;\nassign main_soclinux_uart_tx_fifo_sink_payload_data = main_soclinux_uart_rxtx_r;\nassign main_soclinux_uart_txfull_status = (~main_soclinux_uart_tx_fifo_sink_ready);\nassign main_soclinux_uart_txempty_status = (~main_soclinux_uart_tx_fifo_source_valid);\nassign main_soclinux_uart_uart_source_valid = main_soclinux_uart_tx_fifo_source_valid;\nassign main_soclinux_uart_tx_fifo_source_ready = main_soclinux_uart_uart_source_ready;\nassign main_soclinux_uart_uart_source_first = main_soclinux_uart_tx_fifo_source_first;\nassign main_soclinux_uart_uart_source_last = main_soclinux_uart_tx_fifo_source_last;\nassign main_soclinux_uart_uart_source_payload_data = main_soclinux_uart_tx_fifo_source_payload_data;\nassign main_soclinux_uart_tx_trigger = (~main_soclinux_uart_tx_fifo_sink_ready);\nassign main_soclinux_uart_rx_fifo_sink_valid = main_soclinux_uart_uart_sink_valid;\nassign main_soclinux_uart_uart_sink_ready = main_soclinux_uart_rx_fifo_sink_ready;\nassign main_soclinux_uart_rx_fifo_sink_first = main_soclinux_uart_uart_sink_first;\nassign main_soclinux_uart_rx_fifo_sink_last = main_soclinux_uart_uart_sink_last;\nassign main_soclinux_uart_rx_fifo_sink_payload_data = main_soclinux_uart_uart_sink_payload_data;\nassign main_soclinux_uart_rxempty_status = (~main_soclinux_uart_rx_fifo_source_valid);\nassign main_soclinux_uart_rxfull_status = (~main_soclinux_uart_rx_fifo_sink_ready);\nassign main_soclinux_uart_rxtx_w = main_soclinux_uart_rx_fifo_source_payload_data;\nassign main_soclinux_uart_rx_fifo_source_ready = (main_soclinux_uart_rx_clear | (1'd0 & main_soclinux_uart_rxtx_we));\nassign main_soclinux_uart_rx_trigger = (~main_soclinux_uart_rx_fifo_source_valid);\nalways @(*) begin\n\tmain_soclinux_uart_tx_clear <= 1'd0;\n\tif ((main_soclinux_uart_eventmanager_pending_re & main_soclinux_uart_eventmanager_pending_r[0])) begin\n\t\tmain_soclinux_uart_tx_clear <= 1'd1;\n\tend\nend\nalways @(*) begin\n\tmain_soclinux_uart_eventmanager_status_w <= 2'd0;\n\tmain_soclinux_uart_eventmanager_status_w[0] <= main_soclinux_uart_tx_status;\n\tmain_soclinux_uart_eventmanager_status_w[1] <= main_soclinux_uart_rx_status;\nend\nalways @(*) begin\n\tmain_soclinux_uart_rx_clear <= 1'd0;\n\tif ((main_soclinux_uart_eventmanager_pending_re & main_soclinux_uart_eventmanager_pending_r[1])) begin\n\t\tmain_soclinux_uart_rx_clear <= 1'd1;\n\tend\nend\nalways @(*) begin\n\tmain_soclinux_uart_eventmanager_pending_w <= 2'd0;\n\tmain_soclinux_uart_eventmanager_pending_w[0] <= main_soclinux_uart_tx_pending;\n\tmain_soclinux_uart_eventmanager_pending_w[1] <= main_soclinux_uart_rx_pending;\nend\nassign main_soclinux_uart_irq = ((main_soclinux_uart_eventmanager_pending_w[0] & main_soclinux_uart_eventmanager_storage[0]) | (main_soclinux_uart_eventmanager_pending_w[1] & main_soclinux_uart_eventmanager_storage[1]));\nassign main_soclinux_uart_tx_status = main_soclinux_uart_tx_trigger;\nassign main_soclinux_uart_rx_status = main_soclinux_uart_rx_trigger;\nassign main_soclinux_uart_tx_fifo_syncfifo_din = {main_soclinux_uart_tx_fifo_fifo_in_last, main_soclinux_uart_tx_fifo_fifo_in_first, main_soclinux_uart_tx_fifo_fifo_in_payload_data};\nassign {main_soclinux_uart_tx_fifo_fifo_out_last, main_soclinux_uart_tx_fifo_fifo_out_first, main_soclinux_uart_tx_fifo_fifo_out_payload_data} = main_soclinux_uart_tx_fifo_syncfifo_dout;\nassign main_soclinux_uart_tx_fifo_sink_ready = main_soclinux_uart_tx_fifo_syncfifo_writable;\nassign main_soclinux_uart_tx_fifo_syncfifo_we = main_soclinux_uart_tx_fifo_sink_valid;\nassign main_soclinux_uart_tx_fifo_fifo_in_first = main_soclinux_uart_tx_fifo_sink_first;\nassign main_soclinux_uart_tx_fifo_fifo_in_last = main_soclinux_uart_tx_fifo_sink_last;\nassign main_soclinux_uart_tx_fifo_fifo_in_payload_data = main_soclinux_uart_tx_fifo_sink_payload_data;\nassign main_soclinux_uart_tx_fifo_source_valid = main_soclinux_uart_tx_fifo_readable;\nassign main_soclinux_uart_tx_fifo_source_first = main_soclinux_uart_tx_fifo_fifo_out_first;\nassign main_soclinux_uart_tx_fifo_source_last = main_soclinux_uart_tx_fifo_fifo_out_last;\nassign main_soclinux_uart_tx_fifo_source_payload_data = main_soclinux_uart_tx_fifo_fifo_out_payload_data;\nassign main_soclinux_uart_tx_fifo_re = main_soclinux_uart_tx_fifo_source_ready;\nassign main_soclinux_uart_tx_fifo_syncfifo_re = (main_soclinux_uart_tx_fifo_syncfifo_readable & ((~main_soclinux_uart_tx_fifo_readable) | main_soclinux_uart_tx_fifo_re));\nassign main_soclinux_uart_tx_fifo_level1 = (main_soclinux_uart_tx_fifo_level0 + main_soclinux_uart_tx_fifo_readable);\nalways @(*) begin\n\tmain_soclinux_uart_tx_fifo_wrport_adr <= 4'd0;\n\tif (main_soclinux_uart_tx_fifo_replace) begin\n\t\tmain_soclinux_uart_tx_fifo_wrport_adr <= (main_soclinux_uart_tx_fifo_produce - 1'd1);\n\tend else begin\n\t\tmain_soclinux_uart_tx_fifo_wrport_adr <= main_soclinux_uart_tx_fifo_produce;\n\tend\nend\nassign main_soclinux_uart_tx_fifo_wrport_dat_w = main_soclinux_uart_tx_fifo_syncfifo_din;\nassign main_soclinux_uart_tx_fifo_wrport_we = (main_soclinux_uart_tx_fifo_syncfifo_we & (main_soclinux_uart_tx_fifo_syncfifo_writable | main_soclinux_uart_tx_fifo_replace));\nassign main_soclinux_uart_tx_fifo_do_read = (main_soclinux_uart_tx_fifo_syncfifo_readable & main_soclinux_uart_tx_fifo_syncfifo_re);\nassign main_soclinux_uart_tx_fifo_rdport_adr = main_soclinux_uart_tx_fifo_consume;\nassign main_soclinux_uart_tx_fifo_syncfifo_dout = main_soclinux_uart_tx_fifo_rdport_dat_r;\nassign main_soclinux_uart_tx_fifo_rdport_re = main_soclinux_uart_tx_fifo_do_read;\nassign main_soclinux_uart_tx_fifo_syncfifo_writable = (main_soclinux_uart_tx_fifo_level0 != 5'd16);\nassign main_soclinux_uart_tx_fifo_syncfifo_readable = (main_soclinux_uart_tx_fifo_level0 != 1'd0);\nassign main_soclinux_uart_rx_fifo_syncfifo_din = {main_soclinux_uart_rx_fifo_fifo_in_last, main_soclinux_uart_rx_fifo_fifo_in_first, main_soclinux_uart_rx_fifo_fifo_in_payload_data};\nassign {main_soclinux_uart_rx_fifo_fifo_out_last, main_soclinux_uart_rx_fifo_fifo_out_first, main_soclinux_uart_rx_fifo_fifo_out_payload_data} = main_soclinux_uart_rx_fifo_syncfifo_dout;\nassign main_soclinux_uart_rx_fifo_sink_ready = main_soclinux_uart_rx_fifo_syncfifo_writable;\nassign main_soclinux_uart_rx_fifo_syncfifo_we = main_soclinux_uart_rx_fifo_sink_valid;\nassign main_soclinux_uart_rx_fifo_fifo_in_first = main_soclinux_uart_rx_fifo_sink_first;\nassign main_soclinux_uart_rx_fifo_fifo_in_last = main_soclinux_uart_rx_fifo_sink_last;\nassign main_soclinux_uart_rx_fifo_fifo_in_payload_data = main_soclinux_uart_rx_fifo_sink_payload_data;\nassign main_soclinux_uart_rx_fifo_source_valid = main_soclinux_uart_rx_fifo_readable;\nassign main_soclinux_uart_rx_fifo_source_first = main_soclinux_uart_rx_fifo_fifo_out_first;\nassign main_soclinux_uart_rx_fifo_source_last = main_soclinux_uart_rx_fifo_fifo_out_last;\nassign main_soclinux_uart_rx_fifo_source_payload_data = main_soclinux_uart_rx_fifo_fifo_out_payload_data;\nassign main_soclinux_uart_rx_fifo_re = main_soclinux_uart_rx_fifo_source_ready;\nassign main_soclinux_uart_rx_fifo_syncfifo_re = (main_soclinux_uart_rx_fifo_syncfifo_readable & ((~main_soclinux_uart_rx_fifo_readable) | main_soclinux_uart_rx_fifo_re));\nassign main_soclinux_uart_rx_fifo_level1 = (main_soclinux_uart_rx_fifo_level0 + main_soclinux_uart_rx_fifo_readable);\nalways @(*) begin\n\tmain_soclinux_uart_rx_fifo_wrport_adr <= 4'd0;\n\tif (main_soclinux_uart_rx_fifo_replace) begin\n\t\tmain_soclinux_uart_rx_fifo_wrport_adr <= (main_soclinux_uart_rx_fifo_produce - 1'd1);\n\tend else begin\n\t\tmain_soclinux_uart_rx_fifo_wrport_adr <= main_soclinux_uart_rx_fifo_produce;\n\tend\nend\nassign main_soclinux_uart_rx_fifo_wrport_dat_w = main_soclinux_uart_rx_fifo_syncfifo_din;\nassign main_soclinux_uart_rx_fifo_wrport_we = (main_soclinux_uart_rx_fifo_syncfifo_we & (main_soclinux_uart_rx_fifo_syncfifo_writable | main_soclinux_uart_rx_fifo_replace));\nassign main_soclinux_uart_rx_fifo_do_read = (main_soclinux_uart_rx_fifo_syncfifo_readable & main_soclinux_uart_rx_fifo_syncfifo_re);\nassign main_soclinux_uart_rx_fifo_rdport_adr = main_soclinux_uart_rx_fifo_consume;\nassign main_soclinux_uart_rx_fifo_syncfifo_dout = main_soclinux_uart_rx_fifo_rdport_dat_r;\nassign main_soclinux_uart_rx_fifo_rdport_re = main_soclinux_uart_rx_fifo_do_read;\nassign main_soclinux_uart_rx_fifo_syncfifo_writable = (main_soclinux_uart_rx_fifo_level0 != 5'd16);\nassign main_soclinux_uart_rx_fifo_syncfifo_readable = (main_soclinux_uart_rx_fifo_level0 != 1'd0);\nassign main_soclinux_timer_zero_trigger = (main_soclinux_timer_value != 1'd0);\nassign main_soclinux_timer_eventmanager_status_w = main_soclinux_timer_zero_status;\nalways @(*) begin\n\tmain_soclinux_timer_zero_clear <= 1'd0;\n\tif ((main_soclinux_timer_eventmanager_pending_re & main_soclinux_timer_eventmanager_pending_r)) begin\n\t\tmain_soclinux_timer_zero_clear <= 1'd1;\n\tend\nend\nassign main_soclinux_timer_eventmanager_pending_w = main_soclinux_timer_zero_pending;\nassign main_soclinux_timer_irq = (main_soclinux_timer_eventmanager_pending_w & main_soclinux_timer_eventmanager_storage);\nassign main_soclinux_timer_zero_status = main_soclinux_timer_zero_trigger;\nassign main_reset = (rst | main_rst);\nassign wifi_gpio0 = 1'd1;\nassign main_clkin = clk25;\nassign sys_clk = main_clkout0;\nassign sys_ps_clk = main_clkout1;\nassign main_dfi_p0_address = main_sdram_master_p0_address;\nassign main_dfi_p0_bank = main_sdram_master_p0_bank;\nassign main_dfi_p0_cas_n = main_sdram_master_p0_cas_n;\nassign main_dfi_p0_cs_n = main_sdram_master_p0_cs_n;\nassign main_dfi_p0_ras_n = main_sdram_master_p0_ras_n;\nassign main_dfi_p0_we_n = main_sdram_master_p0_we_n;\nassign main_dfi_p0_cke = main_sdram_master_p0_cke;\nassign main_dfi_p0_odt = main_sdram_master_p0_odt;\nassign main_dfi_p0_reset_n = main_sdram_master_p0_reset_n;\nassign main_dfi_p0_act_n = main_sdram_master_p0_act_n;\nassign main_dfi_p0_wrdata = main_sdram_master_p0_wrdata;\nassign main_dfi_p0_wrdata_en = main_sdram_master_p0_wrdata_en;\nassign main_dfi_p0_wrdata_mask = main_sdram_master_p0_wrdata_mask;\nassign main_dfi_p0_rddata_en = main_sdram_master_p0_rddata_en;\nassign main_sdram_master_p0_rddata = main_dfi_p0_rddata;\nassign main_sdram_master_p0_rddata_valid = main_dfi_p0_rddata_valid;\nassign main_sdram_slave_p0_address = main_sdram_dfi_p0_address;\nassign main_sdram_slave_p0_bank = main_sdram_dfi_p0_bank;\nassign main_sdram_slave_p0_cas_n = main_sdram_dfi_p0_cas_n;\nassign main_sdram_slave_p0_cs_n = main_sdram_dfi_p0_cs_n;\nassign main_sdram_slave_p0_ras_n = main_sdram_dfi_p0_ras_n;\nassign main_sdram_slave_p0_we_n = main_sdram_dfi_p0_we_n;\nassign main_sdram_slave_p0_cke = main_sdram_dfi_p0_cke;\nassign main_sdram_slave_p0_odt = main_sdram_dfi_p0_odt;\nassign main_sdram_slave_p0_reset_n = main_sdram_dfi_p0_reset_n;\nassign main_sdram_slave_p0_act_n = main_sdram_dfi_p0_act_n;\nassign main_sdram_slave_p0_wrdata = main_sdram_dfi_p0_wrdata;\nassign main_sdram_slave_p0_wrdata_en = main_sdram_dfi_p0_wrdata_en;\nassign main_sdram_slave_p0_wrdata_mask = main_sdram_dfi_p0_wrdata_mask;\nassign main_sdram_slave_p0_rddata_en = main_sdram_dfi_p0_rddata_en;\nassign main_sdram_dfi_p0_rddata = main_sdram_slave_p0_rddata;\nassign main_sdram_dfi_p0_rddata_valid = main_sdram_slave_p0_rddata_valid;\nalways @(*) begin\n\tmain_sdram_slave_p0_rddata <= 16'd0;\n\tmain_sdram_slave_p0_rddata_valid <= 1'd0;\n\tmain_sdram_master_p0_address <= 13'd0;\n\tmain_sdram_master_p0_bank <= 2'd0;\n\tmain_sdram_master_p0_cas_n <= 1'd1;\n\tmain_sdram_master_p0_cs_n <= 1'd1;\n\tmain_sdram_master_p0_ras_n <= 1'd1;\n\tmain_sdram_master_p0_we_n <= 1'd1;\n\tmain_sdram_master_p0_cke <= 1'd0;\n\tmain_sdram_master_p0_odt <= 1'd0;\n\tmain_sdram_master_p0_reset_n <= 1'd0;\n\tmain_sdram_inti_p0_rddata <= 16'd0;\n\tmain_sdram_master_p0_act_n <= 1'd1;\n\tmain_sdram_inti_p0_rddata_valid <= 1'd0;\n\tmain_sdram_master_p0_wrdata <= 16'd0;\n\tmain_sdram_master_p0_wrdata_en <= 1'd0;\n\tmain_sdram_master_p0_wrdata_mask <= 2'd0;\n\tmain_sdram_master_p0_rddata_en <= 1'd0;\n\tif (main_sdram_sel) begin\n\t\tmain_sdram_master_p0_address <= main_sdram_slave_p0_address;\n\t\tmain_sdram_master_p0_bank <= main_sdram_slave_p0_bank;\n\t\tmain_sdram_master_p0_cas_n <= main_sdram_slave_p0_cas_n;\n\t\tmain_sdram_master_p0_cs_n <= main_sdram_slave_p0_cs_n;\n\t\tmain_sdram_master_p0_ras_n <= main_sdram_slave_p0_ras_n;\n\t\tmain_sdram_master_p0_we_n <= main_sdram_slave_p0_we_n;\n\t\tmain_sdram_master_p0_cke <= main_sdram_slave_p0_cke;\n\t\tmain_sdram_master_p0_odt <= main_sdram_slave_p0_odt;\n\t\tmain_sdram_master_p0_reset_n <= main_sdram_slave_p0_reset_n;\n\t\tmain_sdram_master_p0_act_n <= main_sdram_slave_p0_act_n;\n\t\tmain_sdram_master_p0_wrdata <= main_sdram_slave_p0_wrdata;\n\t\tmain_sdram_master_p0_wrdata_en <= main_sdram_slave_p0_wrdata_en;\n\t\tmain_sdram_master_p0_wrdata_mask <= main_sdram_slave_p0_wrdata_mask;\n\t\tmain_sdram_master_p0_rddata_en <= main_sdram_slave_p0_rddata_en;\n\t\tmain_sdram_slave_p0_rddata <= main_sdram_master_p0_rddata;\n\t\tmain_sdram_slave_p0_rddata_valid <= main_sdram_master_p0_rddata_valid;\n\tend else begin\n\t\tmain_sdram_master_p0_address <= main_sdram_inti_p0_address;\n\t\tmain_sdram_master_p0_bank <= main_sdram_inti_p0_bank;\n\t\tmain_sdram_master_p0_cas_n <= main_sdram_inti_p0_cas_n;\n\t\tmain_sdram_master_p0_cs_n <= main_sdram_inti_p0_cs_n;\n\t\tmain_sdram_master_p0_ras_n <= main_sdram_inti_p0_ras_n;\n\t\tmain_sdram_master_p0_we_n <= main_sdram_inti_p0_we_n;\n\t\tmain_sdram_master_p0_cke <= main_sdram_inti_p0_cke;\n\t\tmain_sdram_master_p0_odt <= main_sdram_inti_p0_odt;\n\t\tmain_sdram_master_p0_reset_n <= main_sdram_inti_p0_reset_n;\n\t\tmain_sdram_master_p0_act_n <= main_sdram_inti_p0_act_n;\n\t\tmain_sdram_master_p0_wrdata <= main_sdram_inti_p0_wrdata;\n\t\tmain_sdram_master_p0_wrdata_en <= main_sdram_inti_p0_wrdata_en;\n\t\tmain_sdram_master_p0_wrdata_mask <= main_sdram_inti_p0_wrdata_mask;\n\t\tmain_sdram_master_p0_rddata_en <= main_sdram_inti_p0_rddata_en;\n\t\tmain_sdram_inti_p0_rddata <= main_sdram_master_p0_rddata;\n\t\tmain_sdram_inti_p0_rddata_valid <= main_sdram_master_p0_rddata_valid;\n\tend\nend\nassign main_sdram_inti_p0_cke = main_sdram_cke1;\nassign main_sdram_inti_p0_odt = main_sdram_odt;\nassign main_sdram_inti_p0_reset_n = main_sdram_reset_n;\nalways @(*) begin\n\tmain_sdram_inti_p0_ras_n <= 1'd1;\n\tmain_sdram_inti_p0_we_n <= 1'd1;\n\tmain_sdram_inti_p0_cas_n <= 1'd1;\n\tmain_sdram_inti_p0_cs_n <= 1'd1;\n\tif (main_sdram_command_issue_re) begin\n\t\tmain_sdram_inti_p0_cs_n <= {1{(~main_sdram_command_storage[0])}};\n\t\tmain_sdram_inti_p0_we_n <= (~main_sdram_command_storage[1]);\n\t\tmain_sdram_inti_p0_cas_n <= (~main_sdram_command_storage[2]);\n\t\tmain_sdram_inti_p0_ras_n <= (~main_sdram_command_storage[3]);\n\tend else begin\n\t\tmain_sdram_inti_p0_cs_n <= {1{1'd1}};\n\t\tmain_sdram_inti_p0_we_n <= 1'd1;\n\t\tmain_sdram_inti_p0_cas_n <= 1'd1;\n\t\tmain_sdram_inti_p0_ras_n <= 1'd1;\n\tend\nend\nassign main_sdram_inti_p0_address = main_sdram_address_storage;\nassign main_sdram_inti_p0_bank = main_sdram_baddress_storage;\nassign main_sdram_inti_p0_wrdata_en = (main_sdram_command_issue_re & main_sdram_command_storage[4]);\nassign main_sdram_inti_p0_rddata_en = (main_sdram_command_issue_re & main_sdram_command_storage[5]);\nassign main_sdram_inti_p0_wrdata = main_sdram_wrdata_storage;\nassign main_sdram_inti_p0_wrdata_mask = 1'd0;\nassign main_sdram_bankmachine0_req_valid = main_sdram_interface_bank0_valid;\nassign main_sdram_interface_bank0_ready = main_sdram_bankmachine0_req_ready;\nassign main_sdram_bankmachine0_req_we = main_sdram_interface_bank0_we;\nassign main_sdram_bankmachine0_req_addr = main_sdram_interface_bank0_addr;\nassign main_sdram_interface_bank0_lock = main_sdram_bankmachine0_req_lock;\nassign main_sdram_interface_bank0_wdata_ready = main_sdram_bankmachine0_req_wdata_ready;\nassign main_sdram_interface_bank0_rdata_valid = main_sdram_bankmachine0_req_rdata_valid;\nassign main_sdram_bankmachine1_req_valid = main_sdram_interface_bank1_valid;\nassign main_sdram_interface_bank1_ready = main_sdram_bankmachine1_req_ready;\nassign main_sdram_bankmachine1_req_we = main_sdram_interface_bank1_we;\nassign main_sdram_bankmachine1_req_addr = main_sdram_interface_bank1_addr;\nassign main_sdram_interface_bank1_lock = main_sdram_bankmachine1_req_lock;\nassign main_sdram_interface_bank1_wdata_ready = main_sdram_bankmachine1_req_wdata_ready;\nassign main_sdram_interface_bank1_rdata_valid = main_sdram_bankmachine1_req_rdata_valid;\nassign main_sdram_bankmachine2_req_valid = main_sdram_interface_bank2_valid;\nassign main_sdram_interface_bank2_ready = main_sdram_bankmachine2_req_ready;\nassign main_sdram_bankmachine2_req_we = main_sdram_interface_bank2_we;\nassign main_sdram_bankmachine2_req_addr = main_sdram_interface_bank2_addr;\nassign main_sdram_interface_bank2_lock = main_sdram_bankmachine2_req_lock;\nassign main_sdram_interface_bank2_wdata_ready = main_sdram_bankmachine2_req_wdata_ready;\nassign main_sdram_interface_bank2_rdata_valid = main_sdram_bankmachine2_req_rdata_valid;\nassign main_sdram_bankmachine3_req_valid = main_sdram_interface_bank3_valid;\nassign main_sdram_interface_bank3_ready = main_sdram_bankmachine3_req_ready;\nassign main_sdram_bankmachine3_req_we = main_sdram_interface_bank3_we;\nassign main_sdram_bankmachine3_req_addr = main_sdram_interface_bank3_addr;\nassign main_sdram_interface_bank3_lock = main_sdram_bankmachine3_req_lock;\nassign main_sdram_interface_bank3_wdata_ready = main_sdram_bankmachine3_req_wdata_ready;\nassign main_sdram_interface_bank3_rdata_valid = main_sdram_bankmachine3_req_rdata_valid;\nassign main_sdram_timer_wait = (~main_sdram_timer_done0);\nassign main_sdram_postponer_req_i = main_sdram_timer_done0;\nassign main_sdram_wants_refresh = main_sdram_postponer_req_o;\nassign main_sdram_timer_done1 = (main_sdram_timer_count1 == 1'd0);\nassign main_sdram_timer_done0 = main_sdram_timer_done1;\nassign main_sdram_timer_count0 = main_sdram_timer_count1;\nassign main_sdram_sequencer_start1 = (main_sdram_sequencer_start0 | (main_sdram_sequencer_count != 1'd0));\nassign main_sdram_sequencer_done0 = (main_sdram_sequencer_done1 & (main_sdram_sequencer_count == 1'd0));\nalways @(*) begin\n\tbuilder_refresher_next_state <= 2'd0;\n\tmain_sdram_cmd_last <= 1'd0;\n\tmain_sdram_sequencer_start0 <= 1'd0;\n\tmain_sdram_cmd_valid <= 1'd0;\n\tbuilder_refresher_next_state <= builder_refresher_state;\n\tcase (builder_refresher_state)\n\t\t1'd1: begin\n\t\t\tmain_sdram_cmd_valid <= 1'd1;\n\t\t\tif (main_sdram_cmd_ready) begin\n\t\t\t\tmain_sdram_sequencer_start0 <= 1'd1;\n\t\t\t\tbuilder_refresher_next_state <= 2'd2;\n\t\t\tend\n\t\tend\n\t\t2'd2: begin\n\t\t\tmain_sdram_cmd_valid <= 1'd1;\n\t\t\tif (main_sdram_sequencer_done0) begin\n\t\t\t\tmain_sdram_cmd_valid <= 1'd0;\n\t\t\t\tmain_sdram_cmd_last <= 1'd1;\n\t\t\t\tbuilder_refresher_next_state <= 1'd0;\n\t\t\tend\n\t\tend\n\t\tdefault: begin\n\t\t\tif (1'd1) begin\n\t\t\t\tif (main_sdram_wants_refresh) begin\n\t\t\t\t\tbuilder_refresher_next_state <= 1'd1;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tendcase\nend\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine0_req_valid;\nassign main_sdram_bankmachine0_req_ready = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine0_req_we;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine0_req_addr;\nassign main_sdram_bankmachine0_cmd_buffer_sink_valid = main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine0_cmd_buffer_sink_ready;\nassign main_sdram_bankmachine0_cmd_buffer_sink_first = main_sdram_bankmachine0_cmd_buffer_lookahead_source_first;\nassign main_sdram_bankmachine0_cmd_buffer_sink_last = main_sdram_bankmachine0_cmd_buffer_lookahead_source_last;\nassign main_sdram_bankmachine0_cmd_buffer_sink_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;\nassign main_sdram_bankmachine0_cmd_buffer_sink_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;\nassign main_sdram_bankmachine0_cmd_buffer_source_ready = (main_sdram_bankmachine0_req_wdata_ready | main_sdram_bankmachine0_req_rdata_valid);\nassign main_sdram_bankmachine0_req_lock = (main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine0_cmd_buffer_source_valid);\nassign main_sdram_bankmachine0_row_hit = (main_sdram_bankmachine0_row == main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9]);\nassign main_sdram_bankmachine0_cmd_payload_ba = 1'd0;\nalways @(*) begin\n\tmain_sdram_bankmachine0_cmd_payload_a <= 13'd0;\n\tif (main_sdram_bankmachine0_row_col_n_addr_sel) begin\n\t\tmain_sdram_bankmachine0_cmd_payload_a <= main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];\n\tend else begin\n\t\tmain_sdram_bankmachine0_cmd_payload_a <= ((main_sdram_bankmachine0_auto_precharge <<< 4'd10) | {main_sdram_bankmachine0_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});\n\tend\nend\nassign main_sdram_bankmachine0_twtpcon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_cmd_payload_is_write);\nassign main_sdram_bankmachine0_trccon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_row_open);\nassign main_sdram_bankmachine0_trascon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_row_open);\nalways @(*) begin\n\tmain_sdram_bankmachine0_auto_precharge <= 1'd0;\n\tif ((main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine0_cmd_buffer_source_valid)) begin\n\t\tif ((main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:9] != main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9])) begin\n\t\t\tmain_sdram_bankmachine0_auto_precharge <= (main_sdram_bankmachine0_row_close == 1'd0);\n\t\tend\n\tend\nend\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};\nassign {main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_source_first = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_source_last = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;\nalways @(*) begin\n\tmain_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0;\n\tif (main_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin\n\t\tmain_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);\n\tend else begin\n\t\tmain_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine0_cmd_buffer_lookahead_produce;\n\tend\nend\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_sdram_bankmachine0_cmd_buffer_lookahead_replace));\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine0_cmd_buffer_lookahead_consume;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8);\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);\nassign main_sdram_bankmachine0_cmd_buffer_sink_ready = ((~main_sdram_bankmachine0_cmd_buffer_source_valid) | main_sdram_bankmachine0_cmd_buffer_source_ready);\nalways @(*) begin\n\tmain_sdram_bankmachine0_req_wdata_ready <= 1'd0;\n\tmain_sdram_bankmachine0_req_rdata_valid <= 1'd0;\n\tmain_sdram_bankmachine0_refresh_gnt <= 1'd0;\n\tmain_sdram_bankmachine0_cmd_valid <= 1'd0;\n\tmain_sdram_bankmachine0_row_open <= 1'd0;\n\tmain_sdram_bankmachine0_row_close <= 1'd0;\n\tmain_sdram_bankmachine0_cmd_payload_cas <= 1'd0;\n\tmain_sdram_bankmachine0_cmd_payload_ras <= 1'd0;\n\tmain_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;\n\tmain_sdram_bankmachine0_cmd_payload_we <= 1'd0;\n\tmain_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;\n\tmain_sdram_bankmachine0_cmd_payload_is_read <= 1'd0;\n\tbuilder_bankmachine0_next_state <= 3'd0;\n\tmain_sdram_bankmachine0_cmd_payload_is_write <= 1'd0;\n\tbuilder_bankmachine0_next_state <= builder_bankmachine0_state;\n\tcase (builder_bankmachine0_state)\n\t\t1'd1: begin\n\t\t\tif ((main_sdram_bankmachine0_twtpcon_ready & main_sdram_bankmachine0_trascon_ready)) begin\n\t\t\t\tmain_sdram_bankmachine0_cmd_valid <= 1'd1;\n\t\t\t\tif (main_sdram_bankmachine0_cmd_ready) begin\n\t\t\t\t\tbuilder_bankmachine0_next_state <= 2'd3;\n\t\t\t\tend\n\t\t\t\tmain_sdram_bankmachine0_cmd_payload_ras <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine0_cmd_payload_we <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;\n\t\t\tend\n\t\t\tmain_sdram_bankmachine0_row_close <= 1'd1;\n\t\tend\n\t\t2'd2: begin\n\t\t\tif ((main_sdram_bankmachine0_twtpcon_ready & main_sdram_bankmachine0_trascon_ready)) begin\n\t\t\t\tbuilder_bankmachine0_next_state <= 2'd3;\n\t\t\tend\n\t\t\tmain_sdram_bankmachine0_row_close <= 1'd1;\n\t\tend\n\t\t2'd3: begin\n\t\t\tif (main_sdram_bankmachine0_trccon_ready) begin\n\t\t\t\tmain_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine0_row_open <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine0_cmd_valid <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;\n\t\t\t\tif (main_sdram_bankmachine0_cmd_ready) begin\n\t\t\t\t\tbuilder_bankmachine0_next_state <= 1'd0;\n\t\t\t\tend\n\t\t\t\tmain_sdram_bankmachine0_cmd_payload_ras <= 1'd1;\n\t\t\tend\n\t\tend\n\t\t3'd4: begin\n\t\t\tif (main_sdram_bankmachine0_twtpcon_ready) begin\n\t\t\t\tmain_sdram_bankmachine0_refresh_gnt <= 1'd1;\n\t\t\tend\n\t\t\tmain_sdram_bankmachine0_row_close <= 1'd1;\n\t\t\tmain_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;\n\t\t\tif ((~main_sdram_bankmachine0_refresh_req)) begin\n\t\t\t\tbuilder_bankmachine0_next_state <= 1'd0;\n\t\t\tend\n\t\tend\n\t\tdefault: begin\n\t\t\tif (main_sdram_bankmachine0_refresh_req) begin\n\t\t\t\tbuilder_bankmachine0_next_state <= 3'd4;\n\t\t\tend else begin\n\t\t\t\tif (main_sdram_bankmachine0_cmd_buffer_source_valid) begin\n\t\t\t\t\tif (main_sdram_bankmachine0_row_opened) begin\n\t\t\t\t\t\tif (main_sdram_bankmachine0_row_hit) begin\n\t\t\t\t\t\t\tmain_sdram_bankmachine0_cmd_valid <= 1'd1;\n\t\t\t\t\t\t\tif (main_sdram_bankmachine0_cmd_buffer_source_payload_we) begin\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine0_req_wdata_ready <= main_sdram_bankmachine0_cmd_ready;\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine0_cmd_payload_is_write <= 1'd1;\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine0_cmd_payload_we <= 1'd1;\n\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine0_req_rdata_valid <= main_sdram_bankmachine0_cmd_ready;\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine0_cmd_payload_is_read <= 1'd1;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tmain_sdram_bankmachine0_cmd_payload_cas <= 1'd1;\n\t\t\t\t\t\t\tif ((main_sdram_bankmachine0_cmd_ready & main_sdram_bankmachine0_auto_precharge)) begin\n\t\t\t\t\t\t\t\tbuilder_bankmachine0_next_state <= 2'd2;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\tbuilder_bankmachine0_next_state <= 1'd1;\n\t\t\t\t\t\tend\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tbuilder_bankmachine0_next_state <= 2'd3;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tendcase\nend\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine1_req_valid;\nassign main_sdram_bankmachine1_req_ready = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine1_req_we;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine1_req_addr;\nassign main_sdram_bankmachine1_cmd_buffer_sink_valid = main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine1_cmd_buffer_sink_ready;\nassign main_sdram_bankmachine1_cmd_buffer_sink_first = main_sdram_bankmachine1_cmd_buffer_lookahead_source_first;\nassign main_sdram_bankmachine1_cmd_buffer_sink_last = main_sdram_bankmachine1_cmd_buffer_lookahead_source_last;\nassign main_sdram_bankmachine1_cmd_buffer_sink_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;\nassign main_sdram_bankmachine1_cmd_buffer_sink_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;\nassign main_sdram_bankmachine1_cmd_buffer_source_ready = (main_sdram_bankmachine1_req_wdata_ready | main_sdram_bankmachine1_req_rdata_valid);\nassign main_sdram_bankmachine1_req_lock = (main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine1_cmd_buffer_source_valid);\nassign main_sdram_bankmachine1_row_hit = (main_sdram_bankmachine1_row == main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9]);\nassign main_sdram_bankmachine1_cmd_payload_ba = 1'd1;\nalways @(*) begin\n\tmain_sdram_bankmachine1_cmd_payload_a <= 13'd0;\n\tif (main_sdram_bankmachine1_row_col_n_addr_sel) begin\n\t\tmain_sdram_bankmachine1_cmd_payload_a <= main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];\n\tend else begin\n\t\tmain_sdram_bankmachine1_cmd_payload_a <= ((main_sdram_bankmachine1_auto_precharge <<< 4'd10) | {main_sdram_bankmachine1_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});\n\tend\nend\nassign main_sdram_bankmachine1_twtpcon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_cmd_payload_is_write);\nassign main_sdram_bankmachine1_trccon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_row_open);\nassign main_sdram_bankmachine1_trascon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_row_open);\nalways @(*) begin\n\tmain_sdram_bankmachine1_auto_precharge <= 1'd0;\n\tif ((main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine1_cmd_buffer_source_valid)) begin\n\t\tif ((main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:9] != main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9])) begin\n\t\t\tmain_sdram_bankmachine1_auto_precharge <= (main_sdram_bankmachine1_row_close == 1'd0);\n\t\tend\n\tend\nend\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};\nassign {main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_source_first = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_source_last = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;\nalways @(*) begin\n\tmain_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0;\n\tif (main_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin\n\t\tmain_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);\n\tend else begin\n\t\tmain_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine1_cmd_buffer_lookahead_produce;\n\tend\nend\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_sdram_bankmachine1_cmd_buffer_lookahead_replace));\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine1_cmd_buffer_lookahead_consume;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8);\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);\nassign main_sdram_bankmachine1_cmd_buffer_sink_ready = ((~main_sdram_bankmachine1_cmd_buffer_source_valid) | main_sdram_bankmachine1_cmd_buffer_source_ready);\nalways @(*) begin\n\tmain_sdram_bankmachine1_req_wdata_ready <= 1'd0;\n\tmain_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;\n\tmain_sdram_bankmachine1_req_rdata_valid <= 1'd0;\n\tmain_sdram_bankmachine1_refresh_gnt <= 1'd0;\n\tmain_sdram_bankmachine1_cmd_valid <= 1'd0;\n\tmain_sdram_bankmachine1_row_open <= 1'd0;\n\tmain_sdram_bankmachine1_row_close <= 1'd0;\n\tmain_sdram_bankmachine1_cmd_payload_cas <= 1'd0;\n\tbuilder_bankmachine1_next_state <= 3'd0;\n\tmain_sdram_bankmachine1_cmd_payload_ras <= 1'd0;\n\tmain_sdram_bankmachine1_cmd_payload_we <= 1'd0;\n\tmain_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;\n\tmain_sdram_bankmachine1_cmd_payload_is_read <= 1'd0;\n\tmain_sdram_bankmachine1_cmd_payload_is_write <= 1'd0;\n\tbuilder_bankmachine1_next_state <= builder_bankmachine1_state;\n\tcase (builder_bankmachine1_state)\n\t\t1'd1: begin\n\t\t\tif ((main_sdram_bankmachine1_twtpcon_ready & main_sdram_bankmachine1_trascon_ready)) begin\n\t\t\t\tmain_sdram_bankmachine1_cmd_valid <= 1'd1;\n\t\t\t\tif (main_sdram_bankmachine1_cmd_ready) begin\n\t\t\t\t\tbuilder_bankmachine1_next_state <= 2'd3;\n\t\t\t\tend\n\t\t\t\tmain_sdram_bankmachine1_cmd_payload_ras <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine1_cmd_payload_we <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;\n\t\t\tend\n\t\t\tmain_sdram_bankmachine1_row_close <= 1'd1;\n\t\tend\n\t\t2'd2: begin\n\t\t\tif ((main_sdram_bankmachine1_twtpcon_ready & main_sdram_bankmachine1_trascon_ready)) begin\n\t\t\t\tbuilder_bankmachine1_next_state <= 2'd3;\n\t\t\tend\n\t\t\tmain_sdram_bankmachine1_row_close <= 1'd1;\n\t\tend\n\t\t2'd3: begin\n\t\t\tif (main_sdram_bankmachine1_trccon_ready) begin\n\t\t\t\tmain_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine1_row_open <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine1_cmd_valid <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;\n\t\t\t\tif (main_sdram_bankmachine1_cmd_ready) begin\n\t\t\t\t\tbuilder_bankmachine1_next_state <= 1'd0;\n\t\t\t\tend\n\t\t\t\tmain_sdram_bankmachine1_cmd_payload_ras <= 1'd1;\n\t\t\tend\n\t\tend\n\t\t3'd4: begin\n\t\t\tif (main_sdram_bankmachine1_twtpcon_ready) begin\n\t\t\t\tmain_sdram_bankmachine1_refresh_gnt <= 1'd1;\n\t\t\tend\n\t\t\tmain_sdram_bankmachine1_row_close <= 1'd1;\n\t\t\tmain_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;\n\t\t\tif ((~main_sdram_bankmachine1_refresh_req)) begin\n\t\t\t\tbuilder_bankmachine1_next_state <= 1'd0;\n\t\t\tend\n\t\tend\n\t\tdefault: begin\n\t\t\tif (main_sdram_bankmachine1_refresh_req) begin\n\t\t\t\tbuilder_bankmachine1_next_state <= 3'd4;\n\t\t\tend else begin\n\t\t\t\tif (main_sdram_bankmachine1_cmd_buffer_source_valid) begin\n\t\t\t\t\tif (main_sdram_bankmachine1_row_opened) begin\n\t\t\t\t\t\tif (main_sdram_bankmachine1_row_hit) begin\n\t\t\t\t\t\t\tmain_sdram_bankmachine1_cmd_valid <= 1'd1;\n\t\t\t\t\t\t\tif (main_sdram_bankmachine1_cmd_buffer_source_payload_we) begin\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine1_req_wdata_ready <= main_sdram_bankmachine1_cmd_ready;\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine1_cmd_payload_is_write <= 1'd1;\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine1_cmd_payload_we <= 1'd1;\n\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine1_req_rdata_valid <= main_sdram_bankmachine1_cmd_ready;\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine1_cmd_payload_is_read <= 1'd1;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tmain_sdram_bankmachine1_cmd_payload_cas <= 1'd1;\n\t\t\t\t\t\t\tif ((main_sdram_bankmachine1_cmd_ready & main_sdram_bankmachine1_auto_precharge)) begin\n\t\t\t\t\t\t\t\tbuilder_bankmachine1_next_state <= 2'd2;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\tbuilder_bankmachine1_next_state <= 1'd1;\n\t\t\t\t\t\tend\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tbuilder_bankmachine1_next_state <= 2'd3;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tendcase\nend\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine2_req_valid;\nassign main_sdram_bankmachine2_req_ready = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine2_req_we;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine2_req_addr;\nassign main_sdram_bankmachine2_cmd_buffer_sink_valid = main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine2_cmd_buffer_sink_ready;\nassign main_sdram_bankmachine2_cmd_buffer_sink_first = main_sdram_bankmachine2_cmd_buffer_lookahead_source_first;\nassign main_sdram_bankmachine2_cmd_buffer_sink_last = main_sdram_bankmachine2_cmd_buffer_lookahead_source_last;\nassign main_sdram_bankmachine2_cmd_buffer_sink_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;\nassign main_sdram_bankmachine2_cmd_buffer_sink_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;\nassign main_sdram_bankmachine2_cmd_buffer_source_ready = (main_sdram_bankmachine2_req_wdata_ready | main_sdram_bankmachine2_req_rdata_valid);\nassign main_sdram_bankmachine2_req_lock = (main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine2_cmd_buffer_source_valid);\nassign main_sdram_bankmachine2_row_hit = (main_sdram_bankmachine2_row == main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9]);\nassign main_sdram_bankmachine2_cmd_payload_ba = 2'd2;\nalways @(*) begin\n\tmain_sdram_bankmachine2_cmd_payload_a <= 13'd0;\n\tif (main_sdram_bankmachine2_row_col_n_addr_sel) begin\n\t\tmain_sdram_bankmachine2_cmd_payload_a <= main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];\n\tend else begin\n\t\tmain_sdram_bankmachine2_cmd_payload_a <= ((main_sdram_bankmachine2_auto_precharge <<< 4'd10) | {main_sdram_bankmachine2_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});\n\tend\nend\nassign main_sdram_bankmachine2_twtpcon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_cmd_payload_is_write);\nassign main_sdram_bankmachine2_trccon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_row_open);\nassign main_sdram_bankmachine2_trascon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_row_open);\nalways @(*) begin\n\tmain_sdram_bankmachine2_auto_precharge <= 1'd0;\n\tif ((main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine2_cmd_buffer_source_valid)) begin\n\t\tif ((main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:9] != main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9])) begin\n\t\t\tmain_sdram_bankmachine2_auto_precharge <= (main_sdram_bankmachine2_row_close == 1'd0);\n\t\tend\n\tend\nend\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};\nassign {main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_source_first = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_source_last = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;\nalways @(*) begin\n\tmain_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0;\n\tif (main_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin\n\t\tmain_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);\n\tend else begin\n\t\tmain_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine2_cmd_buffer_lookahead_produce;\n\tend\nend\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_sdram_bankmachine2_cmd_buffer_lookahead_replace));\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine2_cmd_buffer_lookahead_consume;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8);\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);\nassign main_sdram_bankmachine2_cmd_buffer_sink_ready = ((~main_sdram_bankmachine2_cmd_buffer_source_valid) | main_sdram_bankmachine2_cmd_buffer_source_ready);\nalways @(*) begin\n\tmain_sdram_bankmachine2_req_wdata_ready <= 1'd0;\n\tmain_sdram_bankmachine2_req_rdata_valid <= 1'd0;\n\tmain_sdram_bankmachine2_refresh_gnt <= 1'd0;\n\tmain_sdram_bankmachine2_cmd_valid <= 1'd0;\n\tmain_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;\n\tbuilder_bankmachine2_next_state <= 3'd0;\n\tmain_sdram_bankmachine2_row_open <= 1'd0;\n\tmain_sdram_bankmachine2_row_close <= 1'd0;\n\tmain_sdram_bankmachine2_cmd_payload_cas <= 1'd0;\n\tmain_sdram_bankmachine2_cmd_payload_ras <= 1'd0;\n\tmain_sdram_bankmachine2_cmd_payload_we <= 1'd0;\n\tmain_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;\n\tmain_sdram_bankmachine2_cmd_payload_is_read <= 1'd0;\n\tmain_sdram_bankmachine2_cmd_payload_is_write <= 1'd0;\n\tbuilder_bankmachine2_next_state <= builder_bankmachine2_state;\n\tcase (builder_bankmachine2_state)\n\t\t1'd1: begin\n\t\t\tif ((main_sdram_bankmachine2_twtpcon_ready & main_sdram_bankmachine2_trascon_ready)) begin\n\t\t\t\tmain_sdram_bankmachine2_cmd_valid <= 1'd1;\n\t\t\t\tif (main_sdram_bankmachine2_cmd_ready) begin\n\t\t\t\t\tbuilder_bankmachine2_next_state <= 2'd3;\n\t\t\t\tend\n\t\t\t\tmain_sdram_bankmachine2_cmd_payload_ras <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine2_cmd_payload_we <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;\n\t\t\tend\n\t\t\tmain_sdram_bankmachine2_row_close <= 1'd1;\n\t\tend\n\t\t2'd2: begin\n\t\t\tif ((main_sdram_bankmachine2_twtpcon_ready & main_sdram_bankmachine2_trascon_ready)) begin\n\t\t\t\tbuilder_bankmachine2_next_state <= 2'd3;\n\t\t\tend\n\t\t\tmain_sdram_bankmachine2_row_close <= 1'd1;\n\t\tend\n\t\t2'd3: begin\n\t\t\tif (main_sdram_bankmachine2_trccon_ready) begin\n\t\t\t\tmain_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine2_row_open <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine2_cmd_valid <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;\n\t\t\t\tif (main_sdram_bankmachine2_cmd_ready) begin\n\t\t\t\t\tbuilder_bankmachine2_next_state <= 1'd0;\n\t\t\t\tend\n\t\t\t\tmain_sdram_bankmachine2_cmd_payload_ras <= 1'd1;\n\t\t\tend\n\t\tend\n\t\t3'd4: begin\n\t\t\tif (main_sdram_bankmachine2_twtpcon_ready) begin\n\t\t\t\tmain_sdram_bankmachine2_refresh_gnt <= 1'd1;\n\t\t\tend\n\t\t\tmain_sdram_bankmachine2_row_close <= 1'd1;\n\t\t\tmain_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;\n\t\t\tif ((~main_sdram_bankmachine2_refresh_req)) begin\n\t\t\t\tbuilder_bankmachine2_next_state <= 1'd0;\n\t\t\tend\n\t\tend\n\t\tdefault: begin\n\t\t\tif (main_sdram_bankmachine2_refresh_req) begin\n\t\t\t\tbuilder_bankmachine2_next_state <= 3'd4;\n\t\t\tend else begin\n\t\t\t\tif (main_sdram_bankmachine2_cmd_buffer_source_valid) begin\n\t\t\t\t\tif (main_sdram_bankmachine2_row_opened) begin\n\t\t\t\t\t\tif (main_sdram_bankmachine2_row_hit) begin\n\t\t\t\t\t\t\tmain_sdram_bankmachine2_cmd_valid <= 1'd1;\n\t\t\t\t\t\t\tif (main_sdram_bankmachine2_cmd_buffer_source_payload_we) begin\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine2_req_wdata_ready <= main_sdram_bankmachine2_cmd_ready;\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine2_cmd_payload_is_write <= 1'd1;\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine2_cmd_payload_we <= 1'd1;\n\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine2_req_rdata_valid <= main_sdram_bankmachine2_cmd_ready;\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine2_cmd_payload_is_read <= 1'd1;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tmain_sdram_bankmachine2_cmd_payload_cas <= 1'd1;\n\t\t\t\t\t\t\tif ((main_sdram_bankmachine2_cmd_ready & main_sdram_bankmachine2_auto_precharge)) begin\n\t\t\t\t\t\t\t\tbuilder_bankmachine2_next_state <= 2'd2;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\tbuilder_bankmachine2_next_state <= 1'd1;\n\t\t\t\t\t\tend\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tbuilder_bankmachine2_next_state <= 2'd3;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tendcase\nend\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine3_req_valid;\nassign main_sdram_bankmachine3_req_ready = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine3_req_we;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine3_req_addr;\nassign main_sdram_bankmachine3_cmd_buffer_sink_valid = main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine3_cmd_buffer_sink_ready;\nassign main_sdram_bankmachine3_cmd_buffer_sink_first = main_sdram_bankmachine3_cmd_buffer_lookahead_source_first;\nassign main_sdram_bankmachine3_cmd_buffer_sink_last = main_sdram_bankmachine3_cmd_buffer_lookahead_source_last;\nassign main_sdram_bankmachine3_cmd_buffer_sink_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;\nassign main_sdram_bankmachine3_cmd_buffer_sink_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;\nassign main_sdram_bankmachine3_cmd_buffer_source_ready = (main_sdram_bankmachine3_req_wdata_ready | main_sdram_bankmachine3_req_rdata_valid);\nassign main_sdram_bankmachine3_req_lock = (main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine3_cmd_buffer_source_valid);\nassign main_sdram_bankmachine3_row_hit = (main_sdram_bankmachine3_row == main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9]);\nassign main_sdram_bankmachine3_cmd_payload_ba = 2'd3;\nalways @(*) begin\n\tmain_sdram_bankmachine3_cmd_payload_a <= 13'd0;\n\tif (main_sdram_bankmachine3_row_col_n_addr_sel) begin\n\t\tmain_sdram_bankmachine3_cmd_payload_a <= main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];\n\tend else begin\n\t\tmain_sdram_bankmachine3_cmd_payload_a <= ((main_sdram_bankmachine3_auto_precharge <<< 4'd10) | {main_sdram_bankmachine3_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});\n\tend\nend\nassign main_sdram_bankmachine3_twtpcon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_cmd_payload_is_write);\nassign main_sdram_bankmachine3_trccon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_row_open);\nassign main_sdram_bankmachine3_trascon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_row_open);\nalways @(*) begin\n\tmain_sdram_bankmachine3_auto_precharge <= 1'd0;\n\tif ((main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine3_cmd_buffer_source_valid)) begin\n\t\tif ((main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:9] != main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9])) begin\n\t\t\tmain_sdram_bankmachine3_auto_precharge <= (main_sdram_bankmachine3_row_close == 1'd0);\n\t\tend\n\tend\nend\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};\nassign {main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_source_first = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_source_last = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;\nalways @(*) begin\n\tmain_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0;\n\tif (main_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin\n\t\tmain_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);\n\tend else begin\n\t\tmain_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine3_cmd_buffer_lookahead_produce;\n\tend\nend\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_sdram_bankmachine3_cmd_buffer_lookahead_replace));\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine3_cmd_buffer_lookahead_consume;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8);\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);\nassign main_sdram_bankmachine3_cmd_buffer_sink_ready = ((~main_sdram_bankmachine3_cmd_buffer_source_valid) | main_sdram_bankmachine3_cmd_buffer_source_ready);\nalways @(*) begin\n\tmain_sdram_bankmachine3_req_wdata_ready <= 1'd0;\n\tmain_sdram_bankmachine3_req_rdata_valid <= 1'd0;\n\tbuilder_bankmachine3_next_state <= 3'd0;\n\tmain_sdram_bankmachine3_refresh_gnt <= 1'd0;\n\tmain_sdram_bankmachine3_cmd_valid <= 1'd0;\n\tmain_sdram_bankmachine3_row_open <= 1'd0;\n\tmain_sdram_bankmachine3_row_close <= 1'd0;\n\tmain_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;\n\tmain_sdram_bankmachine3_cmd_payload_cas <= 1'd0;\n\tmain_sdram_bankmachine3_cmd_payload_ras <= 1'd0;\n\tmain_sdram_bankmachine3_cmd_payload_we <= 1'd0;\n\tmain_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;\n\tmain_sdram_bankmachine3_cmd_payload_is_read <= 1'd0;\n\tmain_sdram_bankmachine3_cmd_payload_is_write <= 1'd0;\n\tbuilder_bankmachine3_next_state <= builder_bankmachine3_state;\n\tcase (builder_bankmachine3_state)\n\t\t1'd1: begin\n\t\t\tif ((main_sdram_bankmachine3_twtpcon_ready & main_sdram_bankmachine3_trascon_ready)) begin\n\t\t\t\tmain_sdram_bankmachine3_cmd_valid <= 1'd1;\n\t\t\t\tif (main_sdram_bankmachine3_cmd_ready) begin\n\t\t\t\t\tbuilder_bankmachine3_next_state <= 2'd3;\n\t\t\t\tend\n\t\t\t\tmain_sdram_bankmachine3_cmd_payload_ras <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine3_cmd_payload_we <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;\n\t\t\tend\n\t\t\tmain_sdram_bankmachine3_row_close <= 1'd1;\n\t\tend\n\t\t2'd2: begin\n\t\t\tif ((main_sdram_bankmachine3_twtpcon_ready & main_sdram_bankmachine3_trascon_ready)) begin\n\t\t\t\tbuilder_bankmachine3_next_state <= 2'd3;\n\t\t\tend\n\t\t\tmain_sdram_bankmachine3_row_close <= 1'd1;\n\t\tend\n\t\t2'd3: begin\n\t\t\tif (main_sdram_bankmachine3_trccon_ready) begin\n\t\t\t\tmain_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine3_row_open <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine3_cmd_valid <= 1'd1;\n\t\t\t\tmain_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;\n\t\t\t\tif (main_sdram_bankmachine3_cmd_ready) begin\n\t\t\t\t\tbuilder_bankmachine3_next_state <= 1'd0;\n\t\t\t\tend\n\t\t\t\tmain_sdram_bankmachine3_cmd_payload_ras <= 1'd1;\n\t\t\tend\n\t\tend\n\t\t3'd4: begin\n\t\t\tif (main_sdram_bankmachine3_twtpcon_ready) begin\n\t\t\t\tmain_sdram_bankmachine3_refresh_gnt <= 1'd1;\n\t\t\tend\n\t\t\tmain_sdram_bankmachine3_row_close <= 1'd1;\n\t\t\tmain_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;\n\t\t\tif ((~main_sdram_bankmachine3_refresh_req)) begin\n\t\t\t\tbuilder_bankmachine3_next_state <= 1'd0;\n\t\t\tend\n\t\tend\n\t\tdefault: begin\n\t\t\tif (main_sdram_bankmachine3_refresh_req) begin\n\t\t\t\tbuilder_bankmachine3_next_state <= 3'd4;\n\t\t\tend else begin\n\t\t\t\tif (main_sdram_bankmachine3_cmd_buffer_source_valid) begin\n\t\t\t\t\tif (main_sdram_bankmachine3_row_opened) begin\n\t\t\t\t\t\tif (main_sdram_bankmachine3_row_hit) begin\n\t\t\t\t\t\t\tmain_sdram_bankmachine3_cmd_valid <= 1'd1;\n\t\t\t\t\t\t\tif (main_sdram_bankmachine3_cmd_buffer_source_payload_we) begin\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine3_req_wdata_ready <= main_sdram_bankmachine3_cmd_ready;\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine3_cmd_payload_is_write <= 1'd1;\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine3_cmd_payload_we <= 1'd1;\n\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine3_req_rdata_valid <= main_sdram_bankmachine3_cmd_ready;\n\t\t\t\t\t\t\t\tmain_sdram_bankmachine3_cmd_payload_is_read <= 1'd1;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tmain_sdram_bankmachine3_cmd_payload_cas <= 1'd1;\n\t\t\t\t\t\t\tif ((main_sdram_bankmachine3_cmd_ready & main_sdram_bankmachine3_auto_precharge)) begin\n\t\t\t\t\t\t\t\tbuilder_bankmachine3_next_state <= 2'd2;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\tbuilder_bankmachine3_next_state <= 1'd1;\n\t\t\t\t\t\tend\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tbuilder_bankmachine3_next_state <= 2'd3;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tendcase\nend\nassign main_sdram_choose_req_want_cmds = 1'd1;\nassign main_sdram_trrdcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & ((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we)));\nassign main_sdram_tfawcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & ((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we)));\nassign main_sdram_ras_allowed = (main_sdram_trrdcon_ready & main_sdram_tfawcon_ready);\nassign main_sdram_tccdcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_cmd_payload_is_write | main_sdram_choose_req_cmd_payload_is_read));\nassign main_sdram_cas_allowed = main_sdram_tccdcon_ready;\nassign main_sdram_twtrcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);\nassign main_sdram_read_available = ((((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_payload_is_read) | (main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_payload_is_read)) | (main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_payload_is_read)) | (main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_payload_is_read));\nassign main_sdram_write_available = ((((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_payload_is_write) | (main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_payload_is_write)) | (main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_payload_is_write)) | (main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_payload_is_write));\nassign main_sdram_max_time0 = (main_sdram_time0 == 1'd0);\nassign main_sdram_max_time1 = (main_sdram_time1 == 1'd0);\nassign main_sdram_bankmachine0_refresh_req = main_sdram_cmd_valid;\nassign main_sdram_bankmachine1_refresh_req = main_sdram_cmd_valid;\nassign main_sdram_bankmachine2_refresh_req = main_sdram_cmd_valid;\nassign main_sdram_bankmachine3_refresh_req = main_sdram_cmd_valid;\nassign main_sdram_go_to_refresh = (((main_sdram_bankmachine0_refresh_gnt & main_sdram_bankmachine1_refresh_gnt) & main_sdram_bankmachine2_refresh_gnt) & main_sdram_bankmachine3_refresh_gnt);\nassign main_sdram_interface_rdata = {main_sdram_dfi_p0_rddata};\nassign {main_sdram_dfi_p0_wrdata} = main_sdram_interface_wdata;\nassign {main_sdram_dfi_p0_wrdata_mask} = (~main_sdram_interface_wdata_we);\nalways @(*) begin\n\tmain_sdram_choose_cmd_valids <= 4'd0;\n\tmain_sdram_choose_cmd_valids[0] <= (main_sdram_bankmachine0_cmd_valid & (((main_sdram_bankmachine0_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine0_cmd_payload_ras & (~main_sdram_bankmachine0_cmd_payload_cas)) & (~main_sdram_bankmachine0_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine0_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine0_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));\n\tmain_sdram_choose_cmd_valids[1] <= (main_sdram_bankmachine1_cmd_valid & (((main_sdram_bankmachine1_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine1_cmd_payload_ras & (~main_sdram_bankmachine1_cmd_payload_cas)) & (~main_sdram_bankmachine1_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine1_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine1_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));\n\tmain_sdram_choose_cmd_valids[2] <= (main_sdram_bankmachine2_cmd_valid & (((main_sdram_bankmachine2_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine2_cmd_payload_ras & (~main_sdram_bankmachine2_cmd_payload_cas)) & (~main_sdram_bankmachine2_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine2_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine2_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));\n\tmain_sdram_choose_cmd_valids[3] <= (main_sdram_bankmachine3_cmd_valid & (((main_sdram_bankmachine3_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine3_cmd_payload_ras & (~main_sdram_bankmachine3_cmd_payload_cas)) & (~main_sdram_bankmachine3_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine3_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine3_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));\nend\nassign main_sdram_choose_cmd_request = main_sdram_choose_cmd_valids;\nassign main_sdram_choose_cmd_cmd_valid = builder_comb_rhs_array_muxed0;\nassign main_sdram_choose_cmd_cmd_payload_a = builder_comb_rhs_array_muxed1;\nassign main_sdram_choose_cmd_cmd_payload_ba = builder_comb_rhs_array_muxed2;\nassign main_sdram_choose_cmd_cmd_payload_is_read = builder_comb_rhs_array_muxed3;\nassign main_sdram_choose_cmd_cmd_payload_is_write = builder_comb_rhs_array_muxed4;\nassign main_sdram_choose_cmd_cmd_payload_is_cmd = builder_comb_rhs_array_muxed5;\nalways @(*) begin\n\tmain_sdram_choose_cmd_cmd_payload_cas <= 1'd0;\n\tif (main_sdram_choose_cmd_cmd_valid) begin\n\t\tmain_sdram_choose_cmd_cmd_payload_cas <= builder_comb_t_array_muxed0;\n\tend\nend\nalways @(*) begin\n\tmain_sdram_choose_cmd_cmd_payload_ras <= 1'd0;\n\tif (main_sdram_choose_cmd_cmd_valid) begin\n\t\tmain_sdram_choose_cmd_cmd_payload_ras <= builder_comb_t_array_muxed1;\n\tend\nend\nalways @(*) begin\n\tmain_sdram_choose_cmd_cmd_payload_we <= 1'd0;\n\tif (main_sdram_choose_cmd_cmd_valid) begin\n\t\tmain_sdram_choose_cmd_cmd_payload_we <= builder_comb_t_array_muxed2;\n\tend\nend\nassign main_sdram_choose_cmd_ce = (main_sdram_choose_cmd_cmd_ready | (~main_sdram_choose_cmd_cmd_valid));\nalways @(*) begin\n\tmain_sdram_choose_req_valids <= 4'd0;\n\tmain_sdram_choose_req_valids[0] <= (main_sdram_bankmachine0_cmd_valid & (((main_sdram_bankmachine0_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine0_cmd_payload_ras & (~main_sdram_bankmachine0_cmd_payload_cas)) & (~main_sdram_bankmachine0_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine0_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine0_cmd_payload_is_write == main_sdram_choose_req_want_writes))));\n\tmain_sdram_choose_req_valids[1] <= (main_sdram_bankmachine1_cmd_valid & (((main_sdram_bankmachine1_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine1_cmd_payload_ras & (~main_sdram_bankmachine1_cmd_payload_cas)) & (~main_sdram_bankmachine1_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine1_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine1_cmd_payload_is_write == main_sdram_choose_req_want_writes))));\n\tmain_sdram_choose_req_valids[2] <= (main_sdram_bankmachine2_cmd_valid & (((main_sdram_bankmachine2_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine2_cmd_payload_ras & (~main_sdram_bankmachine2_cmd_payload_cas)) & (~main_sdram_bankmachine2_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine2_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine2_cmd_payload_is_write == main_sdram_choose_req_want_writes))));\n\tmain_sdram_choose_req_valids[3] <= (main_sdram_bankmachine3_cmd_valid & (((main_sdram_bankmachine3_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine3_cmd_payload_ras & (~main_sdram_bankmachine3_cmd_payload_cas)) & (~main_sdram_bankmachine3_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine3_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine3_cmd_payload_is_write == main_sdram_choose_req_want_writes))));\nend\nassign main_sdram_choose_req_request = main_sdram_choose_req_valids;\nassign main_sdram_choose_req_cmd_valid = builder_comb_rhs_array_muxed6;\nassign main_sdram_choose_req_cmd_payload_a = builder_comb_rhs_array_muxed7;\nassign main_sdram_choose_req_cmd_payload_ba = builder_comb_rhs_array_muxed8;\nassign main_sdram_choose_req_cmd_payload_is_read = builder_comb_rhs_array_muxed9;\nassign main_sdram_choose_req_cmd_payload_is_write = builder_comb_rhs_array_muxed10;\nassign main_sdram_choose_req_cmd_payload_is_cmd = builder_comb_rhs_array_muxed11;\nalways @(*) begin\n\tmain_sdram_choose_req_cmd_payload_cas <= 1'd0;\n\tif (main_sdram_choose_req_cmd_valid) begin\n\t\tmain_sdram_choose_req_cmd_payload_cas <= builder_comb_t_array_muxed3;\n\tend\nend\nalways @(*) begin\n\tmain_sdram_choose_req_cmd_payload_ras <= 1'd0;\n\tif (main_sdram_choose_req_cmd_valid) begin\n\t\tmain_sdram_choose_req_cmd_payload_ras <= builder_comb_t_array_muxed4;\n\tend\nend\nalways @(*) begin\n\tmain_sdram_choose_req_cmd_payload_we <= 1'd0;\n\tif (main_sdram_choose_req_cmd_valid) begin\n\t\tmain_sdram_choose_req_cmd_payload_we <= builder_comb_t_array_muxed5;\n\tend\nend\nalways @(*) begin\n\tmain_sdram_bankmachine0_cmd_ready <= 1'd0;\n\tif (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 1'd0))) begin\n\t\tmain_sdram_bankmachine0_cmd_ready <= 1'd1;\n\tend\n\tif (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 1'd0))) begin\n\t\tmain_sdram_bankmachine0_cmd_ready <= 1'd1;\n\tend\nend\nalways @(*) begin\n\tmain_sdram_bankmachine1_cmd_ready <= 1'd0;\n\tif (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 1'd1))) begin\n\t\tmain_sdram_bankmachine1_cmd_ready <= 1'd1;\n\tend\n\tif (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 1'd1))) begin\n\t\tmain_sdram_bankmachine1_cmd_ready <= 1'd1;\n\tend\nend\nalways @(*) begin\n\tmain_sdram_bankmachine2_cmd_ready <= 1'd0;\n\tif (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 2'd2))) begin\n\t\tmain_sdram_bankmachine2_cmd_ready <= 1'd1;\n\tend\n\tif (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 2'd2))) begin\n\t\tmain_sdram_bankmachine2_cmd_ready <= 1'd1;\n\tend\nend\nalways @(*) begin\n\tmain_sdram_bankmachine3_cmd_ready <= 1'd0;\n\tif (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 2'd3))) begin\n\t\tmain_sdram_bankmachine3_cmd_ready <= 1'd1;\n\tend\n\tif (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 2'd3))) begin\n\t\tmain_sdram_bankmachine3_cmd_ready <= 1'd1;\n\tend\nend\nassign main_sdram_choose_req_ce = (main_sdram_choose_req_cmd_ready | (~main_sdram_choose_req_cmd_valid));\nassign main_sdram_dfi_p0_reset_n = 1'd1;\nassign main_sdram_dfi_p0_cke = {1{main_sdram_steerer0}};\nassign main_sdram_dfi_p0_odt = {1{main_sdram_steerer1}};\nalways @(*) begin\n\tmain_sdram_choose_req_want_activates <= 1'd0;\n\tmain_sdram_choose_req_cmd_ready <= 1'd0;\n\tmain_sdram_steerer_sel <= 2'd0;\n\tmain_sdram_en1 <= 1'd0;\n\tmain_sdram_en0 <= 1'd0;\n\tmain_sdram_choose_req_want_reads <= 1'd0;\n\tmain_sdram_choose_req_want_writes <= 1'd0;\n\tbuilder_multiplexer_next_state <= 3'd0;\n\tmain_sdram_cmd_ready <= 1'd0;\n\tmain_sdram_choose_req_want_activates <= main_sdram_ras_allowed;\n\tbuilder_multiplexer_next_state <= builder_multiplexer_state;\n\tcase (builder_multiplexer_state)\n\t\t1'd1: begin\n\t\t\tmain_sdram_en1 <= 1'd1;\n\t\t\tmain_sdram_choose_req_want_writes <= 1'd1;\n\t\t\tif (1'd1) begin\n\t\t\t\tmain_sdram_choose_req_cmd_ready <= (main_sdram_cas_allowed & ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed));\n\t\t\tend else begin\n\t\t\t\tmain_sdram_choose_req_want_activates <= main_sdram_ras_allowed;\n\t\t\t\tmain_sdram_choose_req_cmd_ready <= ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed);\n\t\t\t\tmain_sdram_choose_req_cmd_ready <= main_sdram_cas_allowed;\n\t\t\tend\n\t\t\tmain_sdram_steerer_sel <= 1'd0;\n\t\t\tif (1'd1) begin\n\t\t\t\tmain_sdram_steerer_sel <= 2'd2;\n\t\t\tend\n\t\t\tif (1'd1) begin\n\t\t\t\tmain_sdram_steerer_sel <= 1'd1;\n\t\t\tend\n\t\t\tif (main_sdram_read_available) begin\n\t\t\t\tif (((~main_sdram_write_available) | main_sdram_max_time1)) begin\n\t\t\t\t\tbuilder_multiplexer_next_state <= 2'd3;\n\t\t\t\tend\n\t\t\tend\n\t\t\tif (main_sdram_go_to_refresh) begin\n\t\t\t\tbuilder_multiplexer_next_state <= 2'd2;\n\t\t\tend\n\t\tend\n\t\t2'd2: begin\n\t\t\tmain_sdram_steerer_sel <= 2'd3;\n\t\t\tmain_sdram_cmd_ready <= 1'd1;\n\t\t\tif (main_sdram_cmd_last) begin\n\t\t\t\tbuilder_multiplexer_next_state <= 1'd0;\n\t\t\tend\n\t\tend\n\t\t2'd3: begin\n\t\t\tif (main_sdram_twtrcon_ready) begin\n\t\t\t\tbuilder_multiplexer_next_state <= 1'd0;\n\t\t\tend\n\t\tend\n\t\t3'd4: begin\n\t\t\tbuilder_multiplexer_next_state <= 3'd5;\n\t\tend\n\t\t3'd5: begin\n\t\t\tbuilder_multiplexer_next_state <= 1'd1;\n\t\tend\n\t\tdefault: begin\n\t\t\tmain_sdram_en0 <= 1'd1;\n\t\t\tmain_sdram_choose_req_want_reads <= 1'd1;\n\t\t\tif (1'd1) begin\n\t\t\t\tmain_sdram_choose_req_cmd_ready <= (main_sdram_cas_allowed & ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed));\n\t\t\tend else begin\n\t\t\t\tmain_sdram_choose_req_want_activates <= main_sdram_ras_allowed;\n\t\t\t\tmain_sdram_choose_req_cmd_ready <= ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed);\n\t\t\t\tmain_sdram_choose_req_cmd_ready <= main_sdram_cas_allowed;\n\t\t\tend\n\t\t\tmain_sdram_steerer_sel <= 1'd0;\n\t\t\tif (1'd1) begin\n\t\t\t\tmain_sdram_steerer_sel <= 2'd2;\n\t\t\tend\n\t\t\tif (1'd1) begin\n\t\t\t\tmain_sdram_steerer_sel <= 1'd1;\n\t\t\tend\n\t\t\tif (main_sdram_write_available) begin\n\t\t\t\tif (((~main_sdram_read_available) | main_sdram_max_time0)) begin\n\t\t\t\t\tbuilder_multiplexer_next_state <= 3'd4;\n\t\t\t\tend\n\t\t\tend\n\t\t\tif (main_sdram_go_to_refresh) begin\n\t\t\t\tbuilder_multiplexer_next_state <= 2'd2;\n\t\t\tend\n\t\tend\n\tendcase\nend\nassign builder_roundrobin0_request = {(((main_port_cmd_payload_addr[10:9] == 1'd0) & (~(((builder_locked0 | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))))) & main_port_cmd_valid)};\nassign builder_roundrobin0_ce = ((~main_sdram_interface_bank0_valid) & (~main_sdram_interface_bank0_lock));\nassign main_sdram_interface_bank0_addr = builder_comb_rhs_array_muxed12;\nassign main_sdram_interface_bank0_we = builder_comb_rhs_array_muxed13;\nassign main_sdram_interface_bank0_valid = builder_comb_rhs_array_muxed14;\nassign builder_roundrobin1_request = {(((main_port_cmd_payload_addr[10:9] == 1'd1) & (~(((builder_locked1 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))))) & main_port_cmd_valid)};\nassign builder_roundrobin1_ce = ((~main_sdram_interface_bank1_valid) & (~main_sdram_interface_bank1_lock));\nassign main_sdram_interface_bank1_addr = builder_comb_rhs_array_muxed15;\nassign main_sdram_interface_bank1_we = builder_comb_rhs_array_muxed16;\nassign main_sdram_interface_bank1_valid = builder_comb_rhs_array_muxed17;\nassign builder_roundrobin2_request = {(((main_port_cmd_payload_addr[10:9] == 2'd2) & (~(((builder_locked2 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))))) & main_port_cmd_valid)};\nassign builder_roundrobin2_ce = ((~main_sdram_interface_bank2_valid) & (~main_sdram_interface_bank2_lock));\nassign main_sdram_interface_bank2_addr = builder_comb_rhs_array_muxed18;\nassign main_sdram_interface_bank2_we = builder_comb_rhs_array_muxed19;\nassign main_sdram_interface_bank2_valid = builder_comb_rhs_array_muxed20;\nassign builder_roundrobin3_request = {(((main_port_cmd_payload_addr[10:9] == 2'd3) & (~(((builder_locked3 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))))) & main_port_cmd_valid)};\nassign builder_roundrobin3_ce = ((~main_sdram_interface_bank3_valid) & (~main_sdram_interface_bank3_lock));\nassign main_sdram_interface_bank3_addr = builder_comb_rhs_array_muxed21;\nassign main_sdram_interface_bank3_we = builder_comb_rhs_array_muxed22;\nassign main_sdram_interface_bank3_valid = builder_comb_rhs_array_muxed23;\nassign main_port_cmd_ready = ((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_port_cmd_payload_addr[10:9] == 1'd0) & (~(((builder_locked0 | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0)))))) & main_sdram_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_port_cmd_payload_addr[10:9] == 1'd1) & (~(((builder_locked1 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0)))))) & main_sdram_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_port_cmd_payload_addr[10:9] == 2'd2) & (~(((builder_locked2 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0)))))) & main_sdram_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_port_cmd_payload_addr[10:9] == 2'd3) & (~(((builder_locked3 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0)))))) & main_sdram_interface_bank3_ready));\nassign main_port_wdata_ready = builder_new_master_wdata_ready;\nassign main_port_rdata_valid = builder_new_master_rdata_valid3;\nalways @(*) begin\n\tmain_sdram_interface_wdata <= 16'd0;\n\tmain_sdram_interface_wdata_we <= 2'd0;\n\tcase ({builder_new_master_wdata_ready})\n\t\t1'd1: begin\n\t\t\tmain_sdram_interface_wdata <= main_port_wdata_payload_data;\n\t\t\tmain_sdram_interface_wdata_we <= main_port_wdata_payload_we;\n\t\tend\n\t\tdefault: begin\n\t\t\tmain_sdram_interface_wdata <= 1'd0;\n\t\t\tmain_sdram_interface_wdata_we <= 1'd0;\n\t\tend\n\tendcase\nend\nassign main_port_rdata_payload_data = main_sdram_interface_rdata;\nassign builder_roundrobin0_grant = 1'd0;\nassign builder_roundrobin1_grant = 1'd0;\nassign builder_roundrobin2_grant = 1'd0;\nassign builder_roundrobin3_grant = 1'd0;\nassign main_data_port_adr = main_wb_sdram_adr[10:2];\nalways @(*) begin\n\tmain_data_port_we <= 16'd0;\n\tmain_data_port_dat_w <= 128'd0;\n\tif (main_write_from_slave) begin\n\t\tmain_data_port_dat_w <= main_interface_dat_r;\n\t\tmain_data_port_we <= {16{1'd1}};\n\tend else begin\n\t\tmain_data_port_dat_w <= {4{main_wb_sdram_dat_w}};\n\t\tif ((((main_wb_sdram_cyc & main_wb_sdram_stb) & main_wb_sdram_we) & main_wb_sdram_ack)) begin\n\t\t\tmain_data_port_we <= {({4{(main_wb_sdram_adr[1:0] == 1'd0)}} & main_wb_sdram_sel), ({4{(main_wb_sdram_adr[1:0] == 1'd1)}} & main_wb_sdram_sel), ({4{(main_wb_sdram_adr[1:0] == 2'd2)}} & main_wb_sdram_sel), ({4{(main_wb_sdram_adr[1:0] == 2'd3)}} & main_wb_sdram_sel)};\n\t\tend\n\tend\nend\nassign main_interface_dat_w = main_data_port_dat_r;\nassign main_interface_sel = 16'd65535;\nalways @(*) begin\n\tmain_wb_sdram_dat_r <= 32'd0;\n\tcase (main_adr_offset_r)\n\t\t1'd0: begin\n\t\t\tmain_wb_sdram_dat_r <= main_data_port_dat_r[127:96];\n\t\tend\n\t\t1'd1: begin\n\t\t\tmain_wb_sdram_dat_r <= main_data_port_dat_r[95:64];\n\t\tend\n\t\t2'd2: begin\n\t\t\tmain_wb_sdram_dat_r <= main_data_port_dat_r[63:32];\n\t\tend\n\t\tdefault: begin\n\t\t\tmain_wb_sdram_dat_r <= main_data_port_dat_r[31:0];\n\t\tend\n\tendcase\nend\nassign {main_tag_do_dirty, main_tag_do_tag} = main_tag_port_dat_r;\nassign main_tag_port_dat_w = {main_tag_di_dirty, main_tag_di_tag};\nassign main_tag_port_adr = main_wb_sdram_adr[10:2];\nassign main_tag_di_tag = main_wb_sdram_adr[29:11];\nassign main_interface_adr = {main_tag_do_tag, main_wb_sdram_adr[10:2]};\nalways @(*) begin\n\tmain_word_clr <= 1'd0;\n\tbuilder_fullmemorywe_next_state <= 2'd0;\n\tmain_word_inc <= 1'd0;\n\tmain_write_from_slave <= 1'd0;\n\tmain_interface_cyc <= 1'd0;\n\tmain_interface_stb <= 1'd0;\n\tmain_tag_port_we <= 1'd0;\n\tmain_interface_we <= 1'd0;\n\tmain_wb_sdram_ack <= 1'd0;\n\tmain_tag_di_dirty <= 1'd0;\n\tbuilder_fullmemorywe_next_state <= builder_fullmemorywe_state;\n\tcase (builder_fullmemorywe_state)\n\t\t1'd1: begin\n\t\t\tmain_word_clr <= 1'd1;\n\t\t\tif ((main_tag_do_tag == main_wb_sdram_adr[29:11])) begin\n\t\t\t\tmain_wb_sdram_ack <= 1'd1;\n\t\t\t\tif (main_wb_sdram_we) begin\n\t\t\t\t\tmain_tag_di_dirty <= 1'd1;\n\t\t\t\t\tmain_tag_port_we <= 1'd1;\n\t\t\t\tend\n\t\t\t\tbuilder_fullmemorywe_next_state <= 1'd0;\n\t\t\tend else begin\n\t\t\t\tif (main_tag_do_dirty) begin\n\t\t\t\t\tbuilder_fullmemorywe_next_state <= 2'd2;\n\t\t\t\tend else begin\n\t\t\t\t\tmain_tag_port_we <= 1'd1;\n\t\t\t\t\tmain_word_clr <= 1'd1;\n\t\t\t\t\tbuilder_fullmemorywe_next_state <= 2'd3;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\t\t2'd2: begin\n\t\t\tmain_interface_stb <= 1'd1;\n\t\t\tmain_interface_cyc <= 1'd1;\n\t\t\tmain_interface_we <= 1'd1;\n\t\t\tif (main_interface_ack) begin\n\t\t\t\tmain_word_inc <= 1'd1;\n\t\t\t\tif (1'd1) begin\n\t\t\t\t\tmain_tag_port_we <= 1'd1;\n\t\t\t\t\tmain_word_clr <= 1'd1;\n\t\t\t\t\tbuilder_fullmemorywe_next_state <= 2'd3;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\t\t2'd3: begin\n\t\t\tmain_interface_stb <= 1'd1;\n\t\t\tmain_interface_cyc <= 1'd1;\n\t\t\tmain_interface_we <= 1'd0;\n\t\t\tif (main_interface_ack) begin\n\t\t\t\tmain_write_from_slave <= 1'd1;\n\t\t\t\tmain_word_inc <= 1'd1;\n\t\t\t\tif (1'd1) begin\n\t\t\t\t\tbuilder_fullmemorywe_next_state <= 1'd1;\n\t\t\t\tend else begin\n\t\t\t\t\tbuilder_fullmemorywe_next_state <= 2'd3;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\t\tdefault: begin\n\t\t\tif ((main_wb_sdram_cyc & main_wb_sdram_stb)) begin\n\t\t\t\tbuilder_fullmemorywe_next_state <= 1'd1;\n\t\t\tend\n\t\tend\n\tendcase\nend\nassign main_wishbone_bridge_cmd_payload_addr = (main_interface_adr - 27'd67108864);\nassign main_wishbone_bridge_cmd_payload_we = main_interface_we;\nassign main_wishbone_bridge_wdata_payload_data = main_interface_dat_w;\nassign main_wishbone_bridge_wdata_payload_we = main_interface_sel;\nassign main_interface_dat_r = main_wishbone_bridge_rdata_payload_data;\nassign main_wishbone_bridge_flush = (~main_interface_cyc);\nassign main_wishbone_bridge_cmd_last = (~main_interface_we);\nassign main_wishbone_bridge_cmd_valid = ((main_interface_cyc & main_interface_stb) & (~main_wishbone_bridge_cmd_consumed));\nassign main_wishbone_bridge_wdata_valid = (((main_wishbone_bridge_cmd_valid | main_wishbone_bridge_cmd_consumed) & main_wishbone_bridge_cmd_payload_we) & (~main_wishbone_bridge_wdata_consumed));\nassign main_wishbone_bridge_rdata_ready = ((main_wishbone_bridge_cmd_valid | main_wishbone_bridge_cmd_consumed) & (~main_wishbone_bridge_cmd_payload_we));\nassign main_interface_ack = (main_wishbone_bridge_ack_cmd & ((main_interface_we & main_wishbone_bridge_ack_wdata) | ((~main_interface_we) & main_wishbone_bridge_ack_rdata)));\nassign main_wishbone_bridge_ack_cmd = ((main_wishbone_bridge_cmd_valid & main_wishbone_bridge_cmd_ready) | main_wishbone_bridge_cmd_consumed);\nassign main_wishbone_bridge_ack_wdata = ((main_wishbone_bridge_wdata_valid & main_wishbone_bridge_wdata_ready) | main_wishbone_bridge_wdata_consumed);\nassign main_wishbone_bridge_ack_rdata = (main_wishbone_bridge_rdata_valid & main_wishbone_bridge_rdata_ready);\nalways @(*) begin\n\tmain_wishbone_bridge_cmd_ready <= 1'd0;\n\tmain_port_cmd_payload_we <= 1'd0;\n\tmain_port_cmd_payload_addr <= 24'd0;\n\tbuilder_litedramwishbone2native_next_state <= 1'd0;\n\tmain_wishbone_bridge_count_litedramwishbone2native_next_value <= 3'd0;\n\tmain_port_cmd_valid <= 1'd0;\n\tmain_wishbone_bridge_count_litedramwishbone2native_next_value_ce <= 1'd0;\n\tbuilder_litedramwishbone2native_next_state <= builder_litedramwishbone2native_state;\n\tcase (builder_litedramwishbone2native_state)\n\t\t1'd1: begin\n\t\t\tmain_port_cmd_valid <= 1'd1;\n\t\t\tmain_port_cmd_payload_we <= main_wishbone_bridge_cmd_payload_we;\n\t\t\tmain_port_cmd_payload_addr <= ((main_wishbone_bridge_cmd_payload_addr * 4'd8) + main_wishbone_bridge_count);\n\t\t\tif (main_port_cmd_ready) begin\n\t\t\t\tmain_wishbone_bridge_count_litedramwishbone2native_next_value <= (main_wishbone_bridge_count + 1'd1);\n\t\t\t\tmain_wishbone_bridge_count_litedramwishbone2native_next_value_ce <= 1'd1;\n\t\t\t\tif ((main_wishbone_bridge_count == 3'd7)) begin\n\t\t\t\t\tmain_wishbone_bridge_cmd_ready <= 1'd1;\n\t\t\t\t\tbuilder_litedramwishbone2native_next_state <= 1'd0;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\t\tdefault: begin\n\t\t\tmain_wishbone_bridge_count_litedramwishbone2native_next_value <= 1'd0;\n\t\t\tmain_wishbone_bridge_count_litedramwishbone2native_next_value_ce <= 1'd1;\n\t\t\tif (main_wishbone_bridge_cmd_valid) begin\n\t\t\t\tbuilder_litedramwishbone2native_next_state <= 1'd1;\n\t\t\tend\n\t\tend\n\tendcase\nend\nassign main_wishbone_bridge_wdata_converter_converter_sink_valid = main_wishbone_bridge_wdata_converter_sink_valid;\nassign main_wishbone_bridge_wdata_converter_converter_sink_first = main_wishbone_bridge_wdata_converter_sink_first;\nassign main_wishbone_bridge_wdata_converter_converter_sink_last = main_wishbone_bridge_wdata_converter_sink_last;\nassign main_wishbone_bridge_wdata_converter_sink_ready = main_wishbone_bridge_wdata_converter_converter_sink_ready;\nalways @(*) begin\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data <= 144'd0;\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[15:0] <= main_wishbone_bridge_wdata_converter_sink_payload_data[15:0];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[17:16] <= main_wishbone_bridge_wdata_converter_sink_payload_we[1:0];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[33:18] <= main_wishbone_bridge_wdata_converter_sink_payload_data[31:16];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[35:34] <= main_wishbone_bridge_wdata_converter_sink_payload_we[3:2];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[51:36] <= main_wishbone_bridge_wdata_converter_sink_payload_data[47:32];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[53:52] <= main_wishbone_bridge_wdata_converter_sink_payload_we[5:4];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[69:54] <= main_wishbone_bridge_wdata_converter_sink_payload_data[63:48];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[71:70] <= main_wishbone_bridge_wdata_converter_sink_payload_we[7:6];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[87:72] <= main_wishbone_bridge_wdata_converter_sink_payload_data[79:64];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[89:88] <= main_wishbone_bridge_wdata_converter_sink_payload_we[9:8];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[105:90] <= main_wishbone_bridge_wdata_converter_sink_payload_data[95:80];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[107:106] <= main_wishbone_bridge_wdata_converter_sink_payload_we[11:10];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[123:108] <= main_wishbone_bridge_wdata_converter_sink_payload_data[111:96];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[125:124] <= main_wishbone_bridge_wdata_converter_sink_payload_we[13:12];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[141:126] <= main_wishbone_bridge_wdata_converter_sink_payload_data[127:112];\n\tmain_wishbone_bridge_wdata_converter_converter_sink_payload_data[143:142] <= main_wishbone_bridge_wdata_converter_sink_payload_we[15:14];\nend\nassign main_wishbone_bridge_wdata_converter_source_valid = main_wishbone_bridge_wdata_converter_source_source_valid;\nassign main_wishbone_bridge_wdata_converter_source_first = main_wishbone_bridge_wdata_converter_source_source_first;\nassign main_wishbone_bridge_wdata_converter_source_last = main_wishbone_bridge_wdata_converter_source_source_last;\nassign main_wishbone_bridge_wdata_converter_source_source_ready = main_wishbone_bridge_wdata_converter_source_ready;\nassign {main_wishbone_bridge_wdata_converter_source_payload_we, main_wishbone_bridge_wdata_converter_source_payload_data} = main_wishbone_bridge_wdata_converter_source_source_payload_data;\nassign main_wishbone_bridge_wdata_converter_source_source_valid = main_wishbone_bridge_wdata_converter_converter_source_valid;\nassign main_wishbone_bridge_wdata_converter_converter_source_ready = main_wishbone_bridge_wdata_converter_source_source_ready;\nassign main_wishbone_bridge_wdata_converter_source_source_first = main_wishbone_bridge_wdata_converter_converter_source_first;\nassign main_wishbone_bridge_wdata_converter_source_source_last = main_wishbone_bridge_wdata_converter_converter_source_last;\nassign main_wishbone_bridge_wdata_converter_source_source_payload_data = main_wishbone_bridge_wdata_converter_converter_source_payload_data;\nassign main_wishbone_bridge_wdata_converter_converter_first = (main_wishbone_bridge_wdata_converter_converter_mux == 1'd0);\nassign main_wishbone_bridge_wdata_converter_converter_last = (main_wishbone_bridge_wdata_converter_converter_mux == 3'd7);\nassign main_wishbone_bridge_wdata_converter_converter_source_valid = main_wishbone_bridge_wdata_converter_converter_sink_valid;\nassign main_wishbone_bridge_wdata_converter_converter_source_first = (main_wishbone_bridge_wdata_converter_converter_sink_first & main_wishbone_bridge_wdata_converter_converter_first);\nassign main_wishbone_bridge_wdata_converter_converter_source_last = (main_wishbone_bridge_wdata_converter_converter_sink_last & main_wishbone_bridge_wdata_converter_converter_last);\nassign main_wishbone_bridge_wdata_converter_converter_sink_ready = (main_wishbone_bridge_wdata_converter_converter_last & main_wishbone_bridge_wdata_converter_converter_source_ready);\nalways @(*) begin\n\tmain_wishbone_bridge_wdata_converter_converter_source_payload_data <= 18'd0;\n\tcase (main_wishbone_bridge_wdata_converter_converter_mux)\n\t\t1'd0: begin\n\t\t\tmain_wishbone_bridge_wdata_converter_converter_source_payload_data <= main_wishbone_bridge_wdata_converter_converter_sink_payload_data[17:0];\n\t\tend\n\t\t1'd1: begin\n\t\t\tmain_wishbone_bridge_wdata_converter_converter_source_payload_data <= main_wishbone_bridge_wdata_converter_converter_sink_payload_data[35:18];\n\t\tend\n\t\t2'd2: begin\n\t\t\tmain_wishbone_bridge_wdata_converter_converter_source_payload_data <= main_wishbone_bridge_wdata_converter_converter_sink_payload_data[53:36];\n\t\tend\n\t\t2'd3: begin\n\t\t\tmain_wishbone_bridge_wdata_converter_converter_source_payload_data <= main_wishbone_bridge_wdata_converter_converter_sink_payload_data[71:54];\n\t\tend\n\t\t3'd4: begin\n\t\t\tmain_wishbone_bridge_wdata_converter_converter_source_payload_data <= main_wishbone_bridge_wdata_converter_converter_sink_payload_data[89:72];\n\t\tend\n\t\t3'd5: begin\n\t\t\tmain_wishbone_bridge_wdata_converter_converter_source_payload_data <= main_wishbone_bridge_wdata_converter_converter_sink_payload_data[107:90];\n\t\tend\n\t\t3'd6: begin\n\t\t\tmain_wishbone_bridge_wdata_converter_converter_source_payload_data <= main_wishbone_bridge_wdata_converter_converter_sink_payload_data[125:108];\n\t\tend\n\t\tdefault: begin\n\t\t\tmain_wishbone_bridge_wdata_converter_converter_source_payload_data <= main_wishbone_bridge_wdata_converter_converter_sink_payload_data[143:126];\n\t\tend\n\tendcase\nend\nassign main_wishbone_bridge_wdata_converter_converter_source_payload_valid_token_count = main_wishbone_bridge_wdata_converter_converter_last;\nassign main_wishbone_bridge_wdata_converter_sink_valid = main_wishbone_bridge_wdata_valid;\nassign main_wishbone_bridge_wdata_ready = main_wishbone_bridge_wdata_converter_sink_ready;\nassign main_wishbone_bridge_wdata_converter_sink_first = main_wishbone_bridge_wdata_first;\nassign main_wishbone_bridge_wdata_converter_sink_last = main_wishbone_bridge_wdata_last;\nassign main_wishbone_bridge_wdata_converter_sink_payload_data = main_wishbone_bridge_wdata_payload_data;\nassign main_wishbone_bridge_wdata_converter_sink_payload_we = main_wishbone_bridge_wdata_payload_we;\nassign main_port_wdata_valid = main_wishbone_bridge_wdata_converter_source_valid;\nassign main_wishbone_bridge_wdata_converter_source_ready = main_port_wdata_ready;\nassign main_port_wdata_first = main_wishbone_bridge_wdata_converter_source_first;\nassign main_port_wdata_last = main_wishbone_bridge_wdata_converter_source_last;\nassign main_port_wdata_payload_data = main_wishbone_bridge_wdata_converter_source_payload_data;\nassign main_port_wdata_payload_we = main_wishbone_bridge_wdata_converter_source_payload_we;\nassign main_wishbone_bridge_rdata_converter_converter_sink_valid = main_wishbone_bridge_rdata_converter_sink_valid;\nassign main_wishbone_bridge_rdata_converter_converter_sink_first = main_wishbone_bridge_rdata_converter_sink_first;\nassign main_wishbone_bridge_rdata_converter_converter_sink_last = main_wishbone_bridge_rdata_converter_sink_last;\nassign main_wishbone_bridge_rdata_converter_sink_ready = main_wishbone_bridge_rdata_converter_converter_sink_ready;\nassign main_wishbone_bridge_rdata_converter_converter_sink_payload_data = {main_wishbone_bridge_rdata_converter_sink_payload_data};\nassign main_wishbone_bridge_rdata_converter_source_valid = main_wishbone_bridge_rdata_converter_source_source_valid;\nassign main_wishbone_bridge_rdata_converter_source_first = main_wishbone_bridge_rdata_converter_source_source_first;\nassign main_wishbone_bridge_rdata_converter_source_last = main_wishbone_bridge_rdata_converter_source_source_last;\nassign main_wishbone_bridge_rdata_converter_source_source_ready = main_wishbone_bridge_rdata_converter_source_ready;\nalways @(*) begin\n\tmain_wishbone_bridge_rdata_converter_source_payload_data <= 128'd0;\n\tmain_wishbone_bridge_rdata_converter_source_payload_data[15:0] <= main_wishbone_bridge_rdata_converter_source_source_payload_data[15:0];\n\tmain_wishbone_bridge_rdata_converter_source_payload_data[31:16] <= main_wishbone_bridge_rdata_converter_source_source_payload_data[31:16];\n\tmain_wishbone_bridge_rdata_converter_source_payload_data[47:32] <= main_wishbone_bridge_rdata_converter_source_source_payload_data[47:32];\n\tmain_wishbone_bridge_rdata_converter_source_payload_data[63:48] <= main_wishbone_bridge_rdata_converter_source_source_payload_data[63:48];\n\tmain_wishbone_bridge_rdata_converter_source_payload_data[79:64] <= main_wishbone_bridge_rdata_converter_source_source_payload_data[79:64];\n\tmain_wishbone_bridge_rdata_converter_source_payload_data[95:80] <= main_wishbone_bridge_rdata_converter_source_source_payload_data[95:80];\n\tmain_wishbone_bridge_rdata_converter_source_payload_data[111:96] <= main_wishbone_bridge_rdata_converter_source_source_payload_data[111:96];\n\tmain_wishbone_bridge_rdata_converter_source_payload_data[127:112] <= main_wishbone_bridge_rdata_converter_source_source_payload_data[127:112];\nend\nassign main_wishbone_bridge_rdata_converter_source_source_valid = main_wishbone_bridge_rdata_converter_converter_source_valid;\nassign main_wishbone_bridge_rdata_converter_converter_source_ready = main_wishbone_bridge_rdata_converter_source_source_ready;\nassign main_wishbone_bridge_rdata_converter_source_source_first = main_wishbone_bridge_rdata_converter_converter_source_first;\nassign main_wishbone_bridge_rdata_converter_source_source_last = main_wishbone_bridge_rdata_converter_converter_source_last;\nassign main_wishbone_bridge_rdata_converter_source_source_payload_data = main_wishbone_bridge_rdata_converter_converter_source_payload_data;\nassign main_wishbone_bridge_rdata_converter_converter_sink_ready = ((~main_wishbone_bridge_rdata_converter_converter_strobe_all) | main_wishbone_bridge_rdata_converter_converter_source_ready);\nassign main_wishbone_bridge_rdata_converter_converter_source_valid = main_wishbone_bridge_rdata_converter_converter_strobe_all;\nassign main_wishbone_bridge_rdata_converter_converter_load_part = (main_wishbone_bridge_rdata_converter_converter_sink_valid & main_wishbone_bridge_rdata_converter_converter_sink_ready);\nassign main_wishbone_bridge_rdata_converter_sink_valid = main_port_rdata_valid;\nassign main_port_rdata_ready = main_wishbone_bridge_rdata_converter_sink_ready;\nassign main_wishbone_bridge_rdata_converter_sink_first = main_port_rdata_first;\nassign main_wishbone_bridge_rdata_converter_sink_last = main_port_rdata_last;\nassign main_wishbone_bridge_rdata_converter_sink_payload_data = main_port_rdata_payload_data;\nassign main_wishbone_bridge_rdata_valid = main_wishbone_bridge_rdata_converter_source_valid;\nassign main_wishbone_bridge_rdata_converter_source_ready = main_wishbone_bridge_rdata_ready;\nassign main_wishbone_bridge_rdata_first = main_wishbone_bridge_rdata_converter_source_first;\nassign main_wishbone_bridge_rdata_last = main_wishbone_bridge_rdata_converter_source_last;\nassign main_wishbone_bridge_rdata_payload_data = main_wishbone_bridge_rdata_converter_source_payload_data;\nassign main_wait = (~main_done);\nalways @(*) begin\n\tuser_led0 <= 1'd0;\n\tuser_led1 <= 1'd0;\n\tuser_led2 <= 1'd0;\n\tuser_led3 <= 1'd0;\n\tuser_led4 <= 1'd0;\n\tuser_led5 <= 1'd0;\n\tuser_led6 <= 1'd0;\n\tuser_led7 <= 1'd0;\n\tif ((main_mode == 1'd1)) begin\n\t\t{user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= main_storage;\n\tend else begin\n\t\t{user_led7, user_led6, user_led5, user_led4, user_led3, user_led2, user_led1, user_led0} <= main_chaser;\n\tend\nend\nassign main_done = (main_count == 1'd0);\nassign soclinux_start0 = soclinux_start1;\nassign soclinux_length0 = soclinux_length1;\nassign soclinux_mosi = soclinux_mosi_storage;\nassign soclinux_done1 = soclinux_done0;\nassign soclinux_miso_status = soclinux_miso;\nassign soclinux_cs = soclinux_cs_storage;\nassign soclinux_loopback = soclinux_loopback_storage;\nassign soclinux_clk_rise = (soclinux_clk_divider1 == (soclinux_clk_divider0[15:1] - 1'd1));\nassign soclinux_clk_fall = (soclinux_clk_divider1 == (soclinux_clk_divider0 - 1'd1));\nassign soclinux_clk_divider0 = soclinux_storage;\nalways @(*) begin\n\tsoclinux_irq <= 1'd0;\n\tbuilder_spimaster_next_state <= 2'd0;\n\tsoclinux_count_spimaster_next_value <= 3'd0;\n\tsoclinux_count_spimaster_next_value_ce <= 1'd0;\n\tsoclinux_clk_enable <= 1'd0;\n\tsoclinux_cs_enable <= 1'd0;\n\tsoclinux_done0 <= 1'd0;\n\tsoclinux_mosi_latch <= 1'd0;\n\tsoclinux_miso_latch <= 1'd0;\n\tbuilder_spimaster_next_state <= builder_spimaster_state;\n\tcase (builder_spimaster_state)\n\t\t1'd1: begin\n\t\t\tsoclinux_count_spimaster_next_value <= 1'd0;\n\t\t\tsoclinux_count_spimaster_next_value_ce <= 1'd1;\n\t\t\tif (soclinux_clk_fall) begin\n\t\t\t\tsoclinux_cs_enable <= 1'd1;\n\t\t\t\tbuilder_spimaster_next_state <= 2'd2;\n\t\t\tend\n\t\tend\n\t\t2'd2: begin\n\t\t\tsoclinux_clk_enable <= 1'd1;\n\t\t\tsoclinux_cs_enable <= 1'd1;\n\t\t\tif (soclinux_clk_fall) begin\n\t\t\t\tsoclinux_count_spimaster_next_value <= (soclinux_count + 1'd1);\n\t\t\t\tsoclinux_count_spimaster_next_value_ce <= 1'd1;\n\t\t\t\tif ((soclinux_count == (soclinux_length0 - 1'd1))) begin\n\t\t\t\t\tbuilder_spimaster_next_state <= 2'd3;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\t\t2'd3: begin\n\t\t\tsoclinux_cs_enable <= 1'd1;\n\t\t\tif (soclinux_clk_rise) begin\n\t\t\t\tsoclinux_miso_latch <= 1'd1;\n\t\t\t\tsoclinux_irq <= 1'd1;\n\t\t\t\tbuilder_spimaster_next_state <= 1'd0;\n\t\t\tend\n\t\tend\n\t\tdefault: begin\n\t\t\tsoclinux_done0 <= 1'd1;\n\t\t\tif (soclinux_start0) begin\n\t\t\t\tsoclinux_done0 <= 1'd0;\n\t\t\t\tsoclinux_mosi_latch <= 1'd1;\n\t\t\t\tbuilder_spimaster_next_state <= 1'd1;\n\t\t\tend\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_next_state <= 2'd0;\n\tbuilder_soclinux_dat_w_next_value0 <= 8'd0;\n\tbuilder_soclinux_dat_w_next_value_ce0 <= 1'd0;\n\tbuilder_soclinux_wishbone_dat_r <= 32'd0;\n\tbuilder_soclinux_adr_next_value1 <= 14'd0;\n\tbuilder_soclinux_wishbone_ack <= 1'd0;\n\tbuilder_soclinux_adr_next_value_ce1 <= 1'd0;\n\tbuilder_soclinux_we_next_value2 <= 1'd0;\n\tbuilder_soclinux_we_next_value_ce2 <= 1'd0;\n\tbuilder_next_state <= builder_state;\n\tcase (builder_state)\n\t\t1'd1: begin\n\t\t\tbuilder_soclinux_adr_next_value1 <= 1'd0;\n\t\t\tbuilder_soclinux_adr_next_value_ce1 <= 1'd1;\n\t\t\tbuilder_soclinux_we_next_value2 <= 1'd0;\n\t\t\tbuilder_soclinux_we_next_value_ce2 <= 1'd1;\n\t\t\tbuilder_next_state <= 2'd2;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_soclinux_wishbone_ack <= 1'd1;\n\t\t\tbuilder_soclinux_wishbone_dat_r <= builder_soclinux_dat_r;\n\t\t\tbuilder_next_state <= 1'd0;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_soclinux_dat_w_next_value0 <= builder_soclinux_wishbone_dat_w;\n\t\t\tbuilder_soclinux_dat_w_next_value_ce0 <= 1'd1;\n\t\t\tif ((builder_soclinux_wishbone_cyc & builder_soclinux_wishbone_stb)) begin\n\t\t\t\tbuilder_soclinux_adr_next_value1 <= builder_soclinux_wishbone_adr;\n\t\t\t\tbuilder_soclinux_adr_next_value_ce1 <= 1'd1;\n\t\t\t\tbuilder_soclinux_we_next_value2 <= (builder_soclinux_wishbone_we & (builder_soclinux_wishbone_sel != 1'd0));\n\t\t\t\tbuilder_soclinux_we_next_value_ce2 <= 1'd1;\n\t\t\t\tbuilder_next_state <= 1'd1;\n\t\t\tend\n\t\tend\n\tendcase\nend\nassign builder_shared_adr = builder_comb_rhs_array_muxed24;\nassign builder_shared_dat_w = builder_comb_rhs_array_muxed25;\nassign builder_shared_sel = builder_comb_rhs_array_muxed26;\nassign builder_shared_cyc = builder_comb_rhs_array_muxed27;\nassign builder_shared_stb = builder_comb_rhs_array_muxed28;\nassign builder_shared_we = builder_comb_rhs_array_muxed29;\nassign builder_shared_cti = builder_comb_rhs_array_muxed30;\nassign builder_shared_bte = builder_comb_rhs_array_muxed31;\nassign main_soclinux_cpu_ibus_dat_r = builder_shared_dat_r;\nassign main_soclinux_cpu_dbus_dat_r = builder_shared_dat_r;\nassign main_soclinux_cpu_ibus_ack = (builder_shared_ack & (builder_grant == 1'd0));\nassign main_soclinux_cpu_dbus_ack = (builder_shared_ack & (builder_grant == 1'd1));\nassign main_soclinux_cpu_ibus_err = (builder_shared_err & (builder_grant == 1'd0));\nassign main_soclinux_cpu_dbus_err = (builder_shared_err & (builder_grant == 1'd1));\nassign builder_request = {main_soclinux_cpu_dbus_cyc, main_soclinux_cpu_ibus_cyc};\nalways @(*) begin\n\tbuilder_slave_sel <= 4'd0;\n\tbuilder_slave_sel[0] <= (builder_shared_adr[29:14] == 1'd0);\n\tbuilder_slave_sel[1] <= (builder_shared_adr[29:11] == 16'd32768);\n\tbuilder_slave_sel[2] <= (builder_shared_adr[29:23] == 6'd32);\n\tbuilder_slave_sel[3] <= (builder_shared_adr[29:14] == 16'd61440);\nend\nassign main_soclinux_soclinux_ram_bus_adr = builder_shared_adr;\nassign main_soclinux_soclinux_ram_bus_dat_w = builder_shared_dat_w;\nassign main_soclinux_soclinux_ram_bus_sel = builder_shared_sel;\nassign main_soclinux_soclinux_ram_bus_stb = builder_shared_stb;\nassign main_soclinux_soclinux_ram_bus_we = builder_shared_we;\nassign main_soclinux_soclinux_ram_bus_cti = builder_shared_cti;\nassign main_soclinux_soclinux_ram_bus_bte = builder_shared_bte;\nassign main_soclinux_ram_bus_ram_bus_adr = builder_shared_adr;\nassign main_soclinux_ram_bus_ram_bus_dat_w = builder_shared_dat_w;\nassign main_soclinux_ram_bus_ram_bus_sel = builder_shared_sel;\nassign main_soclinux_ram_bus_ram_bus_stb = builder_shared_stb;\nassign main_soclinux_ram_bus_ram_bus_we = builder_shared_we;\nassign main_soclinux_ram_bus_ram_bus_cti = builder_shared_cti;\nassign main_soclinux_ram_bus_ram_bus_bte = builder_shared_bte;\nassign main_wb_sdram_adr = builder_shared_adr;\nassign main_wb_sdram_dat_w = builder_shared_dat_w;\nassign main_wb_sdram_sel = builder_shared_sel;\nassign main_wb_sdram_stb = builder_shared_stb;\nassign main_wb_sdram_we = builder_shared_we;\nassign main_wb_sdram_cti = builder_shared_cti;\nassign main_wb_sdram_bte = builder_shared_bte;\nassign builder_soclinux_wishbone_adr = builder_shared_adr;\nassign builder_soclinux_wishbone_dat_w = builder_shared_dat_w;\nassign builder_soclinux_wishbone_sel = builder_shared_sel;\nassign builder_soclinux_wishbone_stb = builder_shared_stb;\nassign builder_soclinux_wishbone_we = builder_shared_we;\nassign builder_soclinux_wishbone_cti = builder_shared_cti;\nassign builder_soclinux_wishbone_bte = builder_shared_bte;\nassign main_soclinux_soclinux_ram_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]);\nassign main_soclinux_ram_bus_ram_bus_cyc = (builder_shared_cyc & builder_slave_sel[1]);\nassign main_wb_sdram_cyc = (builder_shared_cyc & builder_slave_sel[2]);\nassign builder_soclinux_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[3]);\nassign builder_shared_err = (((main_soclinux_soclinux_ram_bus_err | main_soclinux_ram_bus_ram_bus_err) | main_wb_sdram_err) | builder_soclinux_wishbone_err);\nassign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack));\nalways @(*) begin\n\tbuilder_error <= 1'd0;\n\tbuilder_shared_ack <= 1'd0;\n\tbuilder_shared_dat_r <= 32'd0;\n\tbuilder_shared_ack <= (((main_soclinux_soclinux_ram_bus_ack | main_soclinux_ram_bus_ram_bus_ack) | main_wb_sdram_ack) | builder_soclinux_wishbone_ack);\n\tbuilder_shared_dat_r <= (((({32{builder_slave_sel_r[0]}} & main_soclinux_soclinux_ram_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & main_soclinux_ram_bus_ram_bus_dat_r)) | ({32{builder_slave_sel_r[2]}} & main_wb_sdram_dat_r)) | ({32{builder_slave_sel_r[3]}} & builder_soclinux_wishbone_dat_r));\n\tif (builder_done) begin\n\t\tbuilder_shared_dat_r <= 32'd4294967295;\n\t\tbuilder_shared_ack <= 1'd1;\n\t\tbuilder_error <= 1'd1;\n\tend\nend\nassign builder_done = (builder_count == 1'd0);\nassign builder_csr_bankarray_csrbank0_sel = (builder_csr_bankarray_interface0_bank_bus_adr[13:9] == 1'd1);\nassign main_soclinux_cpu_latch_r = builder_csr_bankarray_interface0_bank_bus_dat_w[0];\nassign main_soclinux_cpu_latch_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 1'd0));\nassign main_soclinux_cpu_latch_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 1'd0));\nassign builder_csr_bankarray_csrbank0_timer_time7_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time7_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 1'd1));\nassign builder_csr_bankarray_csrbank0_timer_time7_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 1'd1));\nassign builder_csr_bankarray_csrbank0_timer_time6_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time6_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 2'd2));\nassign builder_csr_bankarray_csrbank0_timer_time6_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 2'd2));\nassign builder_csr_bankarray_csrbank0_timer_time5_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time5_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 2'd3));\nassign builder_csr_bankarray_csrbank0_timer_time5_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 2'd3));\nassign builder_csr_bankarray_csrbank0_timer_time4_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time4_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 3'd4));\nassign builder_csr_bankarray_csrbank0_timer_time4_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 3'd4));\nassign builder_csr_bankarray_csrbank0_timer_time3_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time3_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 3'd5));\nassign builder_csr_bankarray_csrbank0_timer_time3_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 3'd5));\nassign builder_csr_bankarray_csrbank0_timer_time2_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time2_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 3'd6));\nassign builder_csr_bankarray_csrbank0_timer_time2_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 3'd6));\nassign builder_csr_bankarray_csrbank0_timer_time1_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time1_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 3'd7));\nassign builder_csr_bankarray_csrbank0_timer_time1_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 3'd7));\nassign builder_csr_bankarray_csrbank0_timer_time0_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time0_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd8));\nassign builder_csr_bankarray_csrbank0_timer_time0_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd8));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp7_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp7_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd9));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp7_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd9));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp6_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp6_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd10));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp6_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd10));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp5_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp5_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd11));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp5_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd11));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp4_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp4_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd12));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp4_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd12));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp3_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp3_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd13));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp3_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd13));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp2_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp2_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd14));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp2_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd14));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp1_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp1_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd15));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp1_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 4'd15));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp0_r = builder_csr_bankarray_interface0_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp0_re = ((builder_csr_bankarray_csrbank0_sel & builder_csr_bankarray_interface0_bank_bus_we) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 5'd16));\nassign builder_csr_bankarray_csrbank0_timer_time_cmp0_we = ((builder_csr_bankarray_csrbank0_sel & (~builder_csr_bankarray_interface0_bank_bus_we)) & (builder_csr_bankarray_interface0_bank_bus_adr[4:0] == 5'd16));\nassign builder_csr_bankarray_csrbank0_timer_time7_w = main_soclinux_cpu_time_status[63:56];\nassign builder_csr_bankarray_csrbank0_timer_time6_w = main_soclinux_cpu_time_status[55:48];\nassign builder_csr_bankarray_csrbank0_timer_time5_w = main_soclinux_cpu_time_status[47:40];\nassign builder_csr_bankarray_csrbank0_timer_time4_w = main_soclinux_cpu_time_status[39:32];\nassign builder_csr_bankarray_csrbank0_timer_time3_w = main_soclinux_cpu_time_status[31:24];\nassign builder_csr_bankarray_csrbank0_timer_time2_w = main_soclinux_cpu_time_status[23:16];\nassign builder_csr_bankarray_csrbank0_timer_time1_w = main_soclinux_cpu_time_status[15:8];\nassign builder_csr_bankarray_csrbank0_timer_time0_w = main_soclinux_cpu_time_status[7:0];\nassign main_soclinux_cpu_time_we = builder_csr_bankarray_csrbank0_timer_time0_we;\nassign main_soclinux_cpu_time_re = builder_csr_bankarray_csrbank0_timer_time0_re;\nassign builder_csr_bankarray_csrbank0_timer_time_cmp7_w = main_soclinux_cpu_time_cmp_storage[63:56];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp6_w = main_soclinux_cpu_time_cmp_storage[55:48];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp5_w = main_soclinux_cpu_time_cmp_storage[47:40];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp4_w = main_soclinux_cpu_time_cmp_storage[39:32];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp3_w = main_soclinux_cpu_time_cmp_storage[31:24];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp2_w = main_soclinux_cpu_time_cmp_storage[23:16];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp1_w = main_soclinux_cpu_time_cmp_storage[15:8];\nassign builder_csr_bankarray_csrbank0_timer_time_cmp0_w = main_soclinux_cpu_time_cmp_storage[7:0];\nassign builder_csr_bankarray_csrbank1_sel = (builder_csr_bankarray_interface1_bank_bus_adr[13:9] == 1'd0);\nassign builder_csr_bankarray_csrbank1_reset0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[0];\nassign builder_csr_bankarray_csrbank1_reset0_re = ((builder_csr_bankarray_csrbank1_sel & builder_csr_bankarray_interface1_bank_bus_we) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 1'd0));\nassign builder_csr_bankarray_csrbank1_reset0_we = ((builder_csr_bankarray_csrbank1_sel & (~builder_csr_bankarray_interface1_bank_bus_we)) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 1'd0));\nassign builder_csr_bankarray_csrbank1_scratch3_r = builder_csr_bankarray_interface1_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank1_scratch3_re = ((builder_csr_bankarray_csrbank1_sel & builder_csr_bankarray_interface1_bank_bus_we) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 1'd1));\nassign builder_csr_bankarray_csrbank1_scratch3_we = ((builder_csr_bankarray_csrbank1_sel & (~builder_csr_bankarray_interface1_bank_bus_we)) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 1'd1));\nassign builder_csr_bankarray_csrbank1_scratch2_r = builder_csr_bankarray_interface1_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank1_scratch2_re = ((builder_csr_bankarray_csrbank1_sel & builder_csr_bankarray_interface1_bank_bus_we) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 2'd2));\nassign builder_csr_bankarray_csrbank1_scratch2_we = ((builder_csr_bankarray_csrbank1_sel & (~builder_csr_bankarray_interface1_bank_bus_we)) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 2'd2));\nassign builder_csr_bankarray_csrbank1_scratch1_r = builder_csr_bankarray_interface1_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank1_scratch1_re = ((builder_csr_bankarray_csrbank1_sel & builder_csr_bankarray_interface1_bank_bus_we) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 2'd3));\nassign builder_csr_bankarray_csrbank1_scratch1_we = ((builder_csr_bankarray_csrbank1_sel & (~builder_csr_bankarray_interface1_bank_bus_we)) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 2'd3));\nassign builder_csr_bankarray_csrbank1_scratch0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank1_scratch0_re = ((builder_csr_bankarray_csrbank1_sel & builder_csr_bankarray_interface1_bank_bus_we) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd4));\nassign builder_csr_bankarray_csrbank1_scratch0_we = ((builder_csr_bankarray_csrbank1_sel & (~builder_csr_bankarray_interface1_bank_bus_we)) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd4));\nassign builder_csr_bankarray_csrbank1_bus_errors3_r = builder_csr_bankarray_interface1_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank1_bus_errors3_re = ((builder_csr_bankarray_csrbank1_sel & builder_csr_bankarray_interface1_bank_bus_we) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd5));\nassign builder_csr_bankarray_csrbank1_bus_errors3_we = ((builder_csr_bankarray_csrbank1_sel & (~builder_csr_bankarray_interface1_bank_bus_we)) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd5));\nassign builder_csr_bankarray_csrbank1_bus_errors2_r = builder_csr_bankarray_interface1_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank1_bus_errors2_re = ((builder_csr_bankarray_csrbank1_sel & builder_csr_bankarray_interface1_bank_bus_we) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd6));\nassign builder_csr_bankarray_csrbank1_bus_errors2_we = ((builder_csr_bankarray_csrbank1_sel & (~builder_csr_bankarray_interface1_bank_bus_we)) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd6));\nassign builder_csr_bankarray_csrbank1_bus_errors1_r = builder_csr_bankarray_interface1_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank1_bus_errors1_re = ((builder_csr_bankarray_csrbank1_sel & builder_csr_bankarray_interface1_bank_bus_we) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd7));\nassign builder_csr_bankarray_csrbank1_bus_errors1_we = ((builder_csr_bankarray_csrbank1_sel & (~builder_csr_bankarray_interface1_bank_bus_we)) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 3'd7));\nassign builder_csr_bankarray_csrbank1_bus_errors0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank1_bus_errors0_re = ((builder_csr_bankarray_csrbank1_sel & builder_csr_bankarray_interface1_bank_bus_we) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd8));\nassign builder_csr_bankarray_csrbank1_bus_errors0_we = ((builder_csr_bankarray_csrbank1_sel & (~builder_csr_bankarray_interface1_bank_bus_we)) & (builder_csr_bankarray_interface1_bank_bus_adr[3:0] == 4'd8));\nassign builder_csr_bankarray_csrbank1_reset0_w = main_soclinux_soccontroller_reset_storage;\nassign builder_csr_bankarray_csrbank1_scratch3_w = main_soclinux_soccontroller_scratch_storage[31:24];\nassign builder_csr_bankarray_csrbank1_scratch2_w = main_soclinux_soccontroller_scratch_storage[23:16];\nassign builder_csr_bankarray_csrbank1_scratch1_w = main_soclinux_soccontroller_scratch_storage[15:8];\nassign builder_csr_bankarray_csrbank1_scratch0_w = main_soclinux_soccontroller_scratch_storage[7:0];\nassign builder_csr_bankarray_csrbank1_bus_errors3_w = main_soclinux_soccontroller_bus_errors_status[31:24];\nassign builder_csr_bankarray_csrbank1_bus_errors2_w = main_soclinux_soccontroller_bus_errors_status[23:16];\nassign builder_csr_bankarray_csrbank1_bus_errors1_w = main_soclinux_soccontroller_bus_errors_status[15:8];\nassign builder_csr_bankarray_csrbank1_bus_errors0_w = main_soclinux_soccontroller_bus_errors_status[7:0];\nassign main_soclinux_soccontroller_bus_errors_we = builder_csr_bankarray_csrbank1_bus_errors0_we;\nassign main_soclinux_soccontroller_bus_errors_re = builder_csr_bankarray_csrbank1_bus_errors0_re;\nassign builder_csr_bankarray_sel = (builder_csr_bankarray_sram_bus_adr[13:9] == 3'd4);\nalways @(*) begin\n\tbuilder_csr_bankarray_sram_bus_dat_r <= 8'd0;\n\tif (builder_csr_bankarray_sel_r) begin\n\t\tbuilder_csr_bankarray_sram_bus_dat_r <= builder_csr_bankarray_dat_r;\n\tend\nend\nassign builder_csr_bankarray_adr = builder_csr_bankarray_sram_bus_adr[5:0];\nassign builder_csr_bankarray_csrbank2_sel = (builder_csr_bankarray_interface2_bank_bus_adr[13:9] == 3'd7);\nassign builder_csr_bankarray_csrbank2_out0_r = builder_csr_bankarray_interface2_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank2_out0_re = ((builder_csr_bankarray_csrbank2_sel & builder_csr_bankarray_interface2_bank_bus_we) & (builder_csr_bankarray_interface2_bank_bus_adr[0] == 1'd0));\nassign builder_csr_bankarray_csrbank2_out0_we = ((builder_csr_bankarray_csrbank2_sel & (~builder_csr_bankarray_interface2_bank_bus_we)) & (builder_csr_bankarray_interface2_bank_bus_adr[0] == 1'd0));\nassign builder_csr_bankarray_csrbank2_out0_w = main_storage[7:0];\nassign builder_csr_bankarray_csrbank3_sel = (builder_csr_bankarray_interface3_bank_bus_adr[13:9] == 3'd6);\nassign builder_csr_bankarray_csrbank3_dfii_control0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[3:0];\nassign builder_csr_bankarray_csrbank3_dfii_control0_re = ((builder_csr_bankarray_csrbank3_sel & builder_csr_bankarray_interface3_bank_bus_we) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 1'd0));\nassign builder_csr_bankarray_csrbank3_dfii_control0_we = ((builder_csr_bankarray_csrbank3_sel & (~builder_csr_bankarray_interface3_bank_bus_we)) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 1'd0));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_command0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[5:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_command0_re = ((builder_csr_bankarray_csrbank3_sel & builder_csr_bankarray_interface3_bank_bus_we) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 1'd1));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_command0_we = ((builder_csr_bankarray_csrbank3_sel & (~builder_csr_bankarray_interface3_bank_bus_we)) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 1'd1));\nassign main_sdram_command_issue_r = builder_csr_bankarray_interface3_bank_bus_dat_w[0];\nassign main_sdram_command_issue_re = ((builder_csr_bankarray_csrbank3_sel & builder_csr_bankarray_interface3_bank_bus_we) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 2'd2));\nassign main_sdram_command_issue_we = ((builder_csr_bankarray_csrbank3_sel & (~builder_csr_bankarray_interface3_bank_bus_we)) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 2'd2));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_address1_r = builder_csr_bankarray_interface3_bank_bus_dat_w[4:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_address1_re = ((builder_csr_bankarray_csrbank3_sel & builder_csr_bankarray_interface3_bank_bus_we) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 2'd3));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_address1_we = ((builder_csr_bankarray_csrbank3_sel & (~builder_csr_bankarray_interface3_bank_bus_we)) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 2'd3));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_address0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_address0_re = ((builder_csr_bankarray_csrbank3_sel & builder_csr_bankarray_interface3_bank_bus_we) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 3'd4));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_address0_we = ((builder_csr_bankarray_csrbank3_sel & (~builder_csr_bankarray_interface3_bank_bus_we)) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 3'd4));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_baddress0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[1:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_baddress0_re = ((builder_csr_bankarray_csrbank3_sel & builder_csr_bankarray_interface3_bank_bus_we) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 3'd5));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_baddress0_we = ((builder_csr_bankarray_csrbank3_sel & (~builder_csr_bankarray_interface3_bank_bus_we)) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 3'd5));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_wrdata1_r = builder_csr_bankarray_interface3_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_wrdata1_re = ((builder_csr_bankarray_csrbank3_sel & builder_csr_bankarray_interface3_bank_bus_we) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 3'd6));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_wrdata1_we = ((builder_csr_bankarray_csrbank3_sel & (~builder_csr_bankarray_interface3_bank_bus_we)) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 3'd6));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_wrdata0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_wrdata0_re = ((builder_csr_bankarray_csrbank3_sel & builder_csr_bankarray_interface3_bank_bus_we) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 3'd7));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_wrdata0_we = ((builder_csr_bankarray_csrbank3_sel & (~builder_csr_bankarray_interface3_bank_bus_we)) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 3'd7));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_rddata1_r = builder_csr_bankarray_interface3_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_rddata1_re = ((builder_csr_bankarray_csrbank3_sel & builder_csr_bankarray_interface3_bank_bus_we) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 4'd8));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_rddata1_we = ((builder_csr_bankarray_csrbank3_sel & (~builder_csr_bankarray_interface3_bank_bus_we)) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 4'd8));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_rddata0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_rddata0_re = ((builder_csr_bankarray_csrbank3_sel & builder_csr_bankarray_interface3_bank_bus_we) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 4'd9));\nassign builder_csr_bankarray_csrbank3_dfii_pi0_rddata0_we = ((builder_csr_bankarray_csrbank3_sel & (~builder_csr_bankarray_interface3_bank_bus_we)) & (builder_csr_bankarray_interface3_bank_bus_adr[3:0] == 4'd9));\nassign main_sdram_sel = main_sdram_storage[0];\nassign main_sdram_cke1 = main_sdram_storage[1];\nassign main_sdram_odt = main_sdram_storage[2];\nassign main_sdram_reset_n = main_sdram_storage[3];\nassign builder_csr_bankarray_csrbank3_dfii_control0_w = main_sdram_storage[3:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_command0_w = main_sdram_command_storage[5:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_address1_w = main_sdram_address_storage[12:8];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_address0_w = main_sdram_address_storage[7:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_baddress0_w = main_sdram_baddress_storage[1:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_wrdata1_w = main_sdram_wrdata_storage[15:8];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_wrdata0_w = main_sdram_wrdata_storage[7:0];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_rddata1_w = main_sdram_rddata_status[15:8];\nassign builder_csr_bankarray_csrbank3_dfii_pi0_rddata0_w = main_sdram_rddata_status[7:0];\nassign main_sdram_rddata_we = builder_csr_bankarray_csrbank3_dfii_pi0_rddata0_we;\nassign main_sdram_rddata_re = builder_csr_bankarray_csrbank3_dfii_pi0_rddata0_re;\nassign builder_csr_bankarray_csrbank4_sel = (builder_csr_bankarray_interface4_bank_bus_adr[13:9] == 4'd8);\nassign builder_csr_bankarray_csrbank4_control1_r = builder_csr_bankarray_interface4_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank4_control1_re = ((builder_csr_bankarray_csrbank4_sel & builder_csr_bankarray_interface4_bank_bus_we) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 1'd0));\nassign builder_csr_bankarray_csrbank4_control1_we = ((builder_csr_bankarray_csrbank4_sel & (~builder_csr_bankarray_interface4_bank_bus_we)) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 1'd0));\nassign builder_csr_bankarray_csrbank4_control0_r = builder_csr_bankarray_interface4_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank4_control0_re = ((builder_csr_bankarray_csrbank4_sel & builder_csr_bankarray_interface4_bank_bus_we) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 1'd1));\nassign builder_csr_bankarray_csrbank4_control0_we = ((builder_csr_bankarray_csrbank4_sel & (~builder_csr_bankarray_interface4_bank_bus_we)) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 1'd1));\nassign builder_csr_bankarray_csrbank4_status_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0];\nassign builder_csr_bankarray_csrbank4_status_re = ((builder_csr_bankarray_csrbank4_sel & builder_csr_bankarray_interface4_bank_bus_we) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 2'd2));\nassign builder_csr_bankarray_csrbank4_status_we = ((builder_csr_bankarray_csrbank4_sel & (~builder_csr_bankarray_interface4_bank_bus_we)) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 2'd2));\nassign builder_csr_bankarray_csrbank4_mosi0_r = builder_csr_bankarray_interface4_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank4_mosi0_re = ((builder_csr_bankarray_csrbank4_sel & builder_csr_bankarray_interface4_bank_bus_we) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 2'd3));\nassign builder_csr_bankarray_csrbank4_mosi0_we = ((builder_csr_bankarray_csrbank4_sel & (~builder_csr_bankarray_interface4_bank_bus_we)) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 2'd3));\nassign builder_csr_bankarray_csrbank4_miso_r = builder_csr_bankarray_interface4_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank4_miso_re = ((builder_csr_bankarray_csrbank4_sel & builder_csr_bankarray_interface4_bank_bus_we) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 3'd4));\nassign builder_csr_bankarray_csrbank4_miso_we = ((builder_csr_bankarray_csrbank4_sel & (~builder_csr_bankarray_interface4_bank_bus_we)) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 3'd4));\nassign builder_csr_bankarray_csrbank4_cs0_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0];\nassign builder_csr_bankarray_csrbank4_cs0_re = ((builder_csr_bankarray_csrbank4_sel & builder_csr_bankarray_interface4_bank_bus_we) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 3'd5));\nassign builder_csr_bankarray_csrbank4_cs0_we = ((builder_csr_bankarray_csrbank4_sel & (~builder_csr_bankarray_interface4_bank_bus_we)) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 3'd5));\nassign builder_csr_bankarray_csrbank4_loopback0_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0];\nassign builder_csr_bankarray_csrbank4_loopback0_re = ((builder_csr_bankarray_csrbank4_sel & builder_csr_bankarray_interface4_bank_bus_we) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 3'd6));\nassign builder_csr_bankarray_csrbank4_loopback0_we = ((builder_csr_bankarray_csrbank4_sel & (~builder_csr_bankarray_interface4_bank_bus_we)) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 3'd6));\nassign builder_csr_bankarray_csrbank4_clk_divider1_r = builder_csr_bankarray_interface4_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank4_clk_divider1_re = ((builder_csr_bankarray_csrbank4_sel & builder_csr_bankarray_interface4_bank_bus_we) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 3'd7));\nassign builder_csr_bankarray_csrbank4_clk_divider1_we = ((builder_csr_bankarray_csrbank4_sel & (~builder_csr_bankarray_interface4_bank_bus_we)) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 3'd7));\nassign builder_csr_bankarray_csrbank4_clk_divider0_r = builder_csr_bankarray_interface4_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank4_clk_divider0_re = ((builder_csr_bankarray_csrbank4_sel & builder_csr_bankarray_interface4_bank_bus_we) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 4'd8));\nassign builder_csr_bankarray_csrbank4_clk_divider0_we = ((builder_csr_bankarray_csrbank4_sel & (~builder_csr_bankarray_interface4_bank_bus_we)) & (builder_csr_bankarray_interface4_bank_bus_adr[3:0] == 4'd8));\nalways @(*) begin\n\tsoclinux_start1 <= 1'd0;\n\tif (soclinux_control_re) begin\n\t\tsoclinux_start1 <= soclinux_control_storage[0];\n\tend\nend\nassign soclinux_length1 = soclinux_control_storage[15:8];\nassign builder_csr_bankarray_csrbank4_control1_w = soclinux_control_storage[15:8];\nassign builder_csr_bankarray_csrbank4_control0_w = soclinux_control_storage[7:0];\nassign soclinux_status_status = soclinux_done1;\nassign builder_csr_bankarray_csrbank4_status_w = soclinux_status_status;\nassign soclinux_status_we = builder_csr_bankarray_csrbank4_status_we;\nassign soclinux_status_re = builder_csr_bankarray_csrbank4_status_re;\nassign builder_csr_bankarray_csrbank4_mosi0_w = soclinux_mosi_storage[7:0];\nassign builder_csr_bankarray_csrbank4_miso_w = soclinux_miso_status[7:0];\nassign soclinux_miso_we = builder_csr_bankarray_csrbank4_miso_we;\nassign soclinux_miso_re = builder_csr_bankarray_csrbank4_miso_re;\nassign soclinux_sel = soclinux_cs_storage;\nassign builder_csr_bankarray_csrbank4_cs0_w = soclinux_cs_storage;\nassign builder_csr_bankarray_csrbank4_loopback0_w = soclinux_loopback_storage;\nassign builder_csr_bankarray_csrbank4_clk_divider1_w = soclinux_storage[15:8];\nassign builder_csr_bankarray_csrbank4_clk_divider0_w = soclinux_storage[7:0];\nassign builder_csr_bankarray_csrbank5_sel = (builder_csr_bankarray_interface5_bank_bus_adr[13:9] == 2'd3);\nassign builder_csr_bankarray_csrbank5_load3_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank5_load3_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 1'd0));\nassign builder_csr_bankarray_csrbank5_load3_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 1'd0));\nassign builder_csr_bankarray_csrbank5_load2_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank5_load2_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 1'd1));\nassign builder_csr_bankarray_csrbank5_load2_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 1'd1));\nassign builder_csr_bankarray_csrbank5_load1_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank5_load1_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 2'd2));\nassign builder_csr_bankarray_csrbank5_load1_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 2'd2));\nassign builder_csr_bankarray_csrbank5_load0_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank5_load0_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 2'd3));\nassign builder_csr_bankarray_csrbank5_load0_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 2'd3));\nassign builder_csr_bankarray_csrbank5_reload3_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank5_reload3_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 3'd4));\nassign builder_csr_bankarray_csrbank5_reload3_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 3'd4));\nassign builder_csr_bankarray_csrbank5_reload2_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank5_reload2_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 3'd5));\nassign builder_csr_bankarray_csrbank5_reload2_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 3'd5));\nassign builder_csr_bankarray_csrbank5_reload1_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank5_reload1_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 3'd6));\nassign builder_csr_bankarray_csrbank5_reload1_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 3'd6));\nassign builder_csr_bankarray_csrbank5_reload0_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank5_reload0_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 3'd7));\nassign builder_csr_bankarray_csrbank5_reload0_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 3'd7));\nassign builder_csr_bankarray_csrbank5_en0_r = builder_csr_bankarray_interface5_bank_bus_dat_w[0];\nassign builder_csr_bankarray_csrbank5_en0_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd8));\nassign builder_csr_bankarray_csrbank5_en0_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd8));\nassign builder_csr_bankarray_csrbank5_update_value0_r = builder_csr_bankarray_interface5_bank_bus_dat_w[0];\nassign builder_csr_bankarray_csrbank5_update_value0_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd9));\nassign builder_csr_bankarray_csrbank5_update_value0_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd9));\nassign builder_csr_bankarray_csrbank5_value3_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank5_value3_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd10));\nassign builder_csr_bankarray_csrbank5_value3_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd10));\nassign builder_csr_bankarray_csrbank5_value2_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank5_value2_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd11));\nassign builder_csr_bankarray_csrbank5_value2_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd11));\nassign builder_csr_bankarray_csrbank5_value1_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank5_value1_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd12));\nassign builder_csr_bankarray_csrbank5_value1_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd12));\nassign builder_csr_bankarray_csrbank5_value0_r = builder_csr_bankarray_interface5_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank5_value0_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd13));\nassign builder_csr_bankarray_csrbank5_value0_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd13));\nassign main_soclinux_timer_eventmanager_status_r = builder_csr_bankarray_interface5_bank_bus_dat_w[0];\nassign main_soclinux_timer_eventmanager_status_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd14));\nassign main_soclinux_timer_eventmanager_status_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd14));\nassign main_soclinux_timer_eventmanager_pending_r = builder_csr_bankarray_interface5_bank_bus_dat_w[0];\nassign main_soclinux_timer_eventmanager_pending_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd15));\nassign main_soclinux_timer_eventmanager_pending_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 4'd15));\nassign builder_csr_bankarray_csrbank5_ev_enable0_r = builder_csr_bankarray_interface5_bank_bus_dat_w[0];\nassign builder_csr_bankarray_csrbank5_ev_enable0_re = ((builder_csr_bankarray_csrbank5_sel & builder_csr_bankarray_interface5_bank_bus_we) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 5'd16));\nassign builder_csr_bankarray_csrbank5_ev_enable0_we = ((builder_csr_bankarray_csrbank5_sel & (~builder_csr_bankarray_interface5_bank_bus_we)) & (builder_csr_bankarray_interface5_bank_bus_adr[4:0] == 5'd16));\nassign builder_csr_bankarray_csrbank5_load3_w = main_soclinux_timer_load_storage[31:24];\nassign builder_csr_bankarray_csrbank5_load2_w = main_soclinux_timer_load_storage[23:16];\nassign builder_csr_bankarray_csrbank5_load1_w = main_soclinux_timer_load_storage[15:8];\nassign builder_csr_bankarray_csrbank5_load0_w = main_soclinux_timer_load_storage[7:0];\nassign builder_csr_bankarray_csrbank5_reload3_w = main_soclinux_timer_reload_storage[31:24];\nassign builder_csr_bankarray_csrbank5_reload2_w = main_soclinux_timer_reload_storage[23:16];\nassign builder_csr_bankarray_csrbank5_reload1_w = main_soclinux_timer_reload_storage[15:8];\nassign builder_csr_bankarray_csrbank5_reload0_w = main_soclinux_timer_reload_storage[7:0];\nassign builder_csr_bankarray_csrbank5_en0_w = main_soclinux_timer_en_storage;\nassign builder_csr_bankarray_csrbank5_update_value0_w = main_soclinux_timer_update_value_storage;\nassign builder_csr_bankarray_csrbank5_value3_w = main_soclinux_timer_value_status[31:24];\nassign builder_csr_bankarray_csrbank5_value2_w = main_soclinux_timer_value_status[23:16];\nassign builder_csr_bankarray_csrbank5_value1_w = main_soclinux_timer_value_status[15:8];\nassign builder_csr_bankarray_csrbank5_value0_w = main_soclinux_timer_value_status[7:0];\nassign main_soclinux_timer_value_we = builder_csr_bankarray_csrbank5_value0_we;\nassign main_soclinux_timer_value_re = builder_csr_bankarray_csrbank5_value0_re;\nassign builder_csr_bankarray_csrbank5_ev_enable0_w = main_soclinux_timer_eventmanager_storage;\nassign builder_csr_bankarray_csrbank6_sel = (builder_csr_bankarray_interface6_bank_bus_adr[13:9] == 2'd2);\nassign main_soclinux_uart_rxtx_r = builder_csr_bankarray_interface6_bank_bus_dat_w[7:0];\nassign main_soclinux_uart_rxtx_re = ((builder_csr_bankarray_csrbank6_sel & builder_csr_bankarray_interface6_bank_bus_we) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 1'd0));\nassign main_soclinux_uart_rxtx_we = ((builder_csr_bankarray_csrbank6_sel & (~builder_csr_bankarray_interface6_bank_bus_we)) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 1'd0));\nassign builder_csr_bankarray_csrbank6_txfull_r = builder_csr_bankarray_interface6_bank_bus_dat_w[0];\nassign builder_csr_bankarray_csrbank6_txfull_re = ((builder_csr_bankarray_csrbank6_sel & builder_csr_bankarray_interface6_bank_bus_we) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 1'd1));\nassign builder_csr_bankarray_csrbank6_txfull_we = ((builder_csr_bankarray_csrbank6_sel & (~builder_csr_bankarray_interface6_bank_bus_we)) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 1'd1));\nassign builder_csr_bankarray_csrbank6_rxempty_r = builder_csr_bankarray_interface6_bank_bus_dat_w[0];\nassign builder_csr_bankarray_csrbank6_rxempty_re = ((builder_csr_bankarray_csrbank6_sel & builder_csr_bankarray_interface6_bank_bus_we) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 2'd2));\nassign builder_csr_bankarray_csrbank6_rxempty_we = ((builder_csr_bankarray_csrbank6_sel & (~builder_csr_bankarray_interface6_bank_bus_we)) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 2'd2));\nassign main_soclinux_uart_eventmanager_status_r = builder_csr_bankarray_interface6_bank_bus_dat_w[1:0];\nassign main_soclinux_uart_eventmanager_status_re = ((builder_csr_bankarray_csrbank6_sel & builder_csr_bankarray_interface6_bank_bus_we) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 2'd3));\nassign main_soclinux_uart_eventmanager_status_we = ((builder_csr_bankarray_csrbank6_sel & (~builder_csr_bankarray_interface6_bank_bus_we)) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 2'd3));\nassign main_soclinux_uart_eventmanager_pending_r = builder_csr_bankarray_interface6_bank_bus_dat_w[1:0];\nassign main_soclinux_uart_eventmanager_pending_re = ((builder_csr_bankarray_csrbank6_sel & builder_csr_bankarray_interface6_bank_bus_we) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 3'd4));\nassign main_soclinux_uart_eventmanager_pending_we = ((builder_csr_bankarray_csrbank6_sel & (~builder_csr_bankarray_interface6_bank_bus_we)) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 3'd4));\nassign builder_csr_bankarray_csrbank6_ev_enable0_r = builder_csr_bankarray_interface6_bank_bus_dat_w[1:0];\nassign builder_csr_bankarray_csrbank6_ev_enable0_re = ((builder_csr_bankarray_csrbank6_sel & builder_csr_bankarray_interface6_bank_bus_we) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 3'd5));\nassign builder_csr_bankarray_csrbank6_ev_enable0_we = ((builder_csr_bankarray_csrbank6_sel & (~builder_csr_bankarray_interface6_bank_bus_we)) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 3'd5));\nassign builder_csr_bankarray_csrbank6_txempty_r = builder_csr_bankarray_interface6_bank_bus_dat_w[0];\nassign builder_csr_bankarray_csrbank6_txempty_re = ((builder_csr_bankarray_csrbank6_sel & builder_csr_bankarray_interface6_bank_bus_we) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 3'd6));\nassign builder_csr_bankarray_csrbank6_txempty_we = ((builder_csr_bankarray_csrbank6_sel & (~builder_csr_bankarray_interface6_bank_bus_we)) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 3'd6));\nassign builder_csr_bankarray_csrbank6_rxfull_r = builder_csr_bankarray_interface6_bank_bus_dat_w[0];\nassign builder_csr_bankarray_csrbank6_rxfull_re = ((builder_csr_bankarray_csrbank6_sel & builder_csr_bankarray_interface6_bank_bus_we) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 3'd7));\nassign builder_csr_bankarray_csrbank6_rxfull_we = ((builder_csr_bankarray_csrbank6_sel & (~builder_csr_bankarray_interface6_bank_bus_we)) & (builder_csr_bankarray_interface6_bank_bus_adr[2:0] == 3'd7));\nassign builder_csr_bankarray_csrbank6_txfull_w = main_soclinux_uart_txfull_status;\nassign main_soclinux_uart_txfull_we = builder_csr_bankarray_csrbank6_txfull_we;\nassign main_soclinux_uart_txfull_re = builder_csr_bankarray_csrbank6_txfull_re;\nassign builder_csr_bankarray_csrbank6_rxempty_w = main_soclinux_uart_rxempty_status;\nassign main_soclinux_uart_rxempty_we = builder_csr_bankarray_csrbank6_rxempty_we;\nassign main_soclinux_uart_rxempty_re = builder_csr_bankarray_csrbank6_rxempty_re;\nassign builder_csr_bankarray_csrbank6_ev_enable0_w = main_soclinux_uart_eventmanager_storage[1:0];\nassign builder_csr_bankarray_csrbank6_txempty_w = main_soclinux_uart_txempty_status;\nassign main_soclinux_uart_txempty_we = builder_csr_bankarray_csrbank6_txempty_we;\nassign main_soclinux_uart_txempty_re = builder_csr_bankarray_csrbank6_txempty_re;\nassign builder_csr_bankarray_csrbank6_rxfull_w = main_soclinux_uart_rxfull_status;\nassign main_soclinux_uart_rxfull_we = builder_csr_bankarray_csrbank6_rxfull_we;\nassign main_soclinux_uart_rxfull_re = builder_csr_bankarray_csrbank6_rxfull_re;\nassign builder_csr_bankarray_csrbank7_sel = (builder_csr_bankarray_interface7_bank_bus_adr[13:9] == 3'd5);\nassign builder_csr_bankarray_csrbank7_tuning_word3_r = builder_csr_bankarray_interface7_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank7_tuning_word3_re = ((builder_csr_bankarray_csrbank7_sel & builder_csr_bankarray_interface7_bank_bus_we) & (builder_csr_bankarray_interface7_bank_bus_adr[1:0] == 1'd0));\nassign builder_csr_bankarray_csrbank7_tuning_word3_we = ((builder_csr_bankarray_csrbank7_sel & (~builder_csr_bankarray_interface7_bank_bus_we)) & (builder_csr_bankarray_interface7_bank_bus_adr[1:0] == 1'd0));\nassign builder_csr_bankarray_csrbank7_tuning_word2_r = builder_csr_bankarray_interface7_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank7_tuning_word2_re = ((builder_csr_bankarray_csrbank7_sel & builder_csr_bankarray_interface7_bank_bus_we) & (builder_csr_bankarray_interface7_bank_bus_adr[1:0] == 1'd1));\nassign builder_csr_bankarray_csrbank7_tuning_word2_we = ((builder_csr_bankarray_csrbank7_sel & (~builder_csr_bankarray_interface7_bank_bus_we)) & (builder_csr_bankarray_interface7_bank_bus_adr[1:0] == 1'd1));\nassign builder_csr_bankarray_csrbank7_tuning_word1_r = builder_csr_bankarray_interface7_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank7_tuning_word1_re = ((builder_csr_bankarray_csrbank7_sel & builder_csr_bankarray_interface7_bank_bus_we) & (builder_csr_bankarray_interface7_bank_bus_adr[1:0] == 2'd2));\nassign builder_csr_bankarray_csrbank7_tuning_word1_we = ((builder_csr_bankarray_csrbank7_sel & (~builder_csr_bankarray_interface7_bank_bus_we)) & (builder_csr_bankarray_interface7_bank_bus_adr[1:0] == 2'd2));\nassign builder_csr_bankarray_csrbank7_tuning_word0_r = builder_csr_bankarray_interface7_bank_bus_dat_w[7:0];\nassign builder_csr_bankarray_csrbank7_tuning_word0_re = ((builder_csr_bankarray_csrbank7_sel & builder_csr_bankarray_interface7_bank_bus_we) & (builder_csr_bankarray_interface7_bank_bus_adr[1:0] == 2'd3));\nassign builder_csr_bankarray_csrbank7_tuning_word0_we = ((builder_csr_bankarray_csrbank7_sel & (~builder_csr_bankarray_interface7_bank_bus_we)) & (builder_csr_bankarray_interface7_bank_bus_adr[1:0] == 2'd3));\nassign builder_csr_bankarray_csrbank7_tuning_word3_w = main_soclinux_storage[31:24];\nassign builder_csr_bankarray_csrbank7_tuning_word2_w = main_soclinux_storage[23:16];\nassign builder_csr_bankarray_csrbank7_tuning_word1_w = main_soclinux_storage[15:8];\nassign builder_csr_bankarray_csrbank7_tuning_word0_w = main_soclinux_storage[7:0];\nassign builder_csr_interconnect_adr = builder_soclinux_adr;\nassign builder_csr_interconnect_we = builder_soclinux_we;\nassign builder_csr_interconnect_dat_w = builder_soclinux_dat_w;\nassign builder_soclinux_dat_r = builder_csr_interconnect_dat_r;\nassign builder_csr_bankarray_interface0_bank_bus_adr = builder_csr_interconnect_adr;\nassign builder_csr_bankarray_interface1_bank_bus_adr = builder_csr_interconnect_adr;\nassign builder_csr_bankarray_interface2_bank_bus_adr = builder_csr_interconnect_adr;\nassign builder_csr_bankarray_interface3_bank_bus_adr = builder_csr_interconnect_adr;\nassign builder_csr_bankarray_interface4_bank_bus_adr = builder_csr_interconnect_adr;\nassign builder_csr_bankarray_interface5_bank_bus_adr = builder_csr_interconnect_adr;\nassign builder_csr_bankarray_interface6_bank_bus_adr = builder_csr_interconnect_adr;\nassign builder_csr_bankarray_interface7_bank_bus_adr = builder_csr_interconnect_adr;\nassign builder_csr_bankarray_sram_bus_adr = builder_csr_interconnect_adr;\nassign builder_csr_bankarray_interface0_bank_bus_we = builder_csr_interconnect_we;\nassign builder_csr_bankarray_interface1_bank_bus_we = builder_csr_interconnect_we;\nassign builder_csr_bankarray_interface2_bank_bus_we = builder_csr_interconnect_we;\nassign builder_csr_bankarray_interface3_bank_bus_we = builder_csr_interconnect_we;\nassign builder_csr_bankarray_interface4_bank_bus_we = builder_csr_interconnect_we;\nassign builder_csr_bankarray_interface5_bank_bus_we = builder_csr_interconnect_we;\nassign builder_csr_bankarray_interface6_bank_bus_we = builder_csr_interconnect_we;\nassign builder_csr_bankarray_interface7_bank_bus_we = builder_csr_interconnect_we;\nassign builder_csr_bankarray_sram_bus_we = builder_csr_interconnect_we;\nassign builder_csr_bankarray_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;\nassign builder_csr_bankarray_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;\nassign builder_csr_bankarray_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;\nassign builder_csr_bankarray_interface3_bank_bus_dat_w = builder_csr_interconnect_dat_w;\nassign builder_csr_bankarray_interface4_bank_bus_dat_w = builder_csr_interconnect_dat_w;\nassign builder_csr_bankarray_interface5_bank_bus_dat_w = builder_csr_interconnect_dat_w;\nassign builder_csr_bankarray_interface6_bank_bus_dat_w = builder_csr_interconnect_dat_w;\nassign builder_csr_bankarray_interface7_bank_bus_dat_w = builder_csr_interconnect_dat_w;\nassign builder_csr_bankarray_sram_bus_dat_w = builder_csr_interconnect_dat_w;\nassign builder_csr_interconnect_dat_r = ((((((((builder_csr_bankarray_interface0_bank_bus_dat_r | builder_csr_bankarray_interface1_bank_bus_dat_r) | builder_csr_bankarray_interface2_bank_bus_dat_r) | builder_csr_bankarray_interface3_bank_bus_dat_r) | builder_csr_bankarray_interface4_bank_bus_dat_r) | builder_csr_bankarray_interface5_bank_bus_dat_r) | builder_csr_bankarray_interface6_bank_bus_dat_r) | builder_csr_bankarray_interface7_bank_bus_dat_r) | builder_csr_bankarray_sram_bus_dat_r);\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed0 <= 1'd0;\n\tcase (main_sdram_choose_cmd_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[0];\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[1];\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[2];\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[3];\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed1 <= 13'd0;\n\tcase (main_sdram_choose_cmd_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed1 <= main_sdram_bankmachine0_cmd_payload_a;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_rhs_array_muxed1 <= main_sdram_bankmachine1_cmd_payload_a;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_rhs_array_muxed1 <= main_sdram_bankmachine2_cmd_payload_a;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed1 <= main_sdram_bankmachine3_cmd_payload_a;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed2 <= 2'd0;\n\tcase (main_sdram_choose_cmd_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed2 <= main_sdram_bankmachine0_cmd_payload_ba;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_rhs_array_muxed2 <= main_sdram_bankmachine1_cmd_payload_ba;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_rhs_array_muxed2 <= main_sdram_bankmachine2_cmd_payload_ba;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed2 <= main_sdram_bankmachine3_cmd_payload_ba;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed3 <= 1'd0;\n\tcase (main_sdram_choose_cmd_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed3 <= main_sdram_bankmachine0_cmd_payload_is_read;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_rhs_array_muxed3 <= main_sdram_bankmachine1_cmd_payload_is_read;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_rhs_array_muxed3 <= main_sdram_bankmachine2_cmd_payload_is_read;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed3 <= main_sdram_bankmachine3_cmd_payload_is_read;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed4 <= 1'd0;\n\tcase (main_sdram_choose_cmd_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed4 <= main_sdram_bankmachine0_cmd_payload_is_write;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_rhs_array_muxed4 <= main_sdram_bankmachine1_cmd_payload_is_write;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_rhs_array_muxed4 <= main_sdram_bankmachine2_cmd_payload_is_write;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed4 <= main_sdram_bankmachine3_cmd_payload_is_write;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed5 <= 1'd0;\n\tcase (main_sdram_choose_cmd_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed5 <= main_sdram_bankmachine0_cmd_payload_is_cmd;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_rhs_array_muxed5 <= main_sdram_bankmachine1_cmd_payload_is_cmd;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_rhs_array_muxed5 <= main_sdram_bankmachine2_cmd_payload_is_cmd;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed5 <= main_sdram_bankmachine3_cmd_payload_is_cmd;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_t_array_muxed0 <= 1'd0;\n\tcase (main_sdram_choose_cmd_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_t_array_muxed0 <= main_sdram_bankmachine0_cmd_payload_cas;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_t_array_muxed0 <= main_sdram_bankmachine1_cmd_payload_cas;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_t_array_muxed0 <= main_sdram_bankmachine2_cmd_payload_cas;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_t_array_muxed0 <= main_sdram_bankmachine3_cmd_payload_cas;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_t_array_muxed1 <= 1'd0;\n\tcase (main_sdram_choose_cmd_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_t_array_muxed1 <= main_sdram_bankmachine0_cmd_payload_ras;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_t_array_muxed1 <= main_sdram_bankmachine1_cmd_payload_ras;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_t_array_muxed1 <= main_sdram_bankmachine2_cmd_payload_ras;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_t_array_muxed1 <= main_sdram_bankmachine3_cmd_payload_ras;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_t_array_muxed2 <= 1'd0;\n\tcase (main_sdram_choose_cmd_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_t_array_muxed2 <= main_sdram_bankmachine0_cmd_payload_we;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_t_array_muxed2 <= main_sdram_bankmachine1_cmd_payload_we;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_t_array_muxed2 <= main_sdram_bankmachine2_cmd_payload_we;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_t_array_muxed2 <= main_sdram_bankmachine3_cmd_payload_we;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed6 <= 1'd0;\n\tcase (main_sdram_choose_req_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed6 <= main_sdram_choose_req_valids[0];\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_rhs_array_muxed6 <= main_sdram_choose_req_valids[1];\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_rhs_array_muxed6 <= main_sdram_choose_req_valids[2];\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed6 <= main_sdram_choose_req_valids[3];\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed7 <= 13'd0;\n\tcase (main_sdram_choose_req_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed7 <= main_sdram_bankmachine0_cmd_payload_a;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_rhs_array_muxed7 <= main_sdram_bankmachine1_cmd_payload_a;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_rhs_array_muxed7 <= main_sdram_bankmachine2_cmd_payload_a;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed7 <= main_sdram_bankmachine3_cmd_payload_a;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed8 <= 2'd0;\n\tcase (main_sdram_choose_req_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed8 <= main_sdram_bankmachine0_cmd_payload_ba;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_rhs_array_muxed8 <= main_sdram_bankmachine1_cmd_payload_ba;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_rhs_array_muxed8 <= main_sdram_bankmachine2_cmd_payload_ba;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed8 <= main_sdram_bankmachine3_cmd_payload_ba;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed9 <= 1'd0;\n\tcase (main_sdram_choose_req_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed9 <= main_sdram_bankmachine0_cmd_payload_is_read;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_rhs_array_muxed9 <= main_sdram_bankmachine1_cmd_payload_is_read;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_rhs_array_muxed9 <= main_sdram_bankmachine2_cmd_payload_is_read;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed9 <= main_sdram_bankmachine3_cmd_payload_is_read;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed10 <= 1'd0;\n\tcase (main_sdram_choose_req_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed10 <= main_sdram_bankmachine0_cmd_payload_is_write;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_rhs_array_muxed10 <= main_sdram_bankmachine1_cmd_payload_is_write;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_rhs_array_muxed10 <= main_sdram_bankmachine2_cmd_payload_is_write;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed10 <= main_sdram_bankmachine3_cmd_payload_is_write;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed11 <= 1'd0;\n\tcase (main_sdram_choose_req_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed11 <= main_sdram_bankmachine0_cmd_payload_is_cmd;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_rhs_array_muxed11 <= main_sdram_bankmachine1_cmd_payload_is_cmd;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_rhs_array_muxed11 <= main_sdram_bankmachine2_cmd_payload_is_cmd;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed11 <= main_sdram_bankmachine3_cmd_payload_is_cmd;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_t_array_muxed3 <= 1'd0;\n\tcase (main_sdram_choose_req_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_t_array_muxed3 <= main_sdram_bankmachine0_cmd_payload_cas;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_t_array_muxed3 <= main_sdram_bankmachine1_cmd_payload_cas;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_t_array_muxed3 <= main_sdram_bankmachine2_cmd_payload_cas;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_t_array_muxed3 <= main_sdram_bankmachine3_cmd_payload_cas;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_t_array_muxed4 <= 1'd0;\n\tcase (main_sdram_choose_req_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_t_array_muxed4 <= main_sdram_bankmachine0_cmd_payload_ras;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_t_array_muxed4 <= main_sdram_bankmachine1_cmd_payload_ras;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_t_array_muxed4 <= main_sdram_bankmachine2_cmd_payload_ras;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_t_array_muxed4 <= main_sdram_bankmachine3_cmd_payload_ras;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_t_array_muxed5 <= 1'd0;\n\tcase (main_sdram_choose_req_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_t_array_muxed5 <= main_sdram_bankmachine0_cmd_payload_we;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_comb_t_array_muxed5 <= main_sdram_bankmachine1_cmd_payload_we;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_comb_t_array_muxed5 <= main_sdram_bankmachine2_cmd_payload_we;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_t_array_muxed5 <= main_sdram_bankmachine3_cmd_payload_we;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed12 <= 22'd0;\n\tcase (builder_roundrobin0_grant)\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed12 <= {main_port_cmd_payload_addr[23:11], main_port_cmd_payload_addr[8:0]};\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed13 <= 1'd0;\n\tcase (builder_roundrobin0_grant)\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed13 <= main_port_cmd_payload_we;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed14 <= 1'd0;\n\tcase (builder_roundrobin0_grant)\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed14 <= (((main_port_cmd_payload_addr[10:9] == 1'd0) & (~(((builder_locked0 | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))))) & main_port_cmd_valid);\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed15 <= 22'd0;\n\tcase (builder_roundrobin1_grant)\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed15 <= {main_port_cmd_payload_addr[23:11], main_port_cmd_payload_addr[8:0]};\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed16 <= 1'd0;\n\tcase (builder_roundrobin1_grant)\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed16 <= main_port_cmd_payload_we;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed17 <= 1'd0;\n\tcase (builder_roundrobin1_grant)\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed17 <= (((main_port_cmd_payload_addr[10:9] == 1'd1) & (~(((builder_locked1 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))))) & main_port_cmd_valid);\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed18 <= 22'd0;\n\tcase (builder_roundrobin2_grant)\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed18 <= {main_port_cmd_payload_addr[23:11], main_port_cmd_payload_addr[8:0]};\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed19 <= 1'd0;\n\tcase (builder_roundrobin2_grant)\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed19 <= main_port_cmd_payload_we;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed20 <= 1'd0;\n\tcase (builder_roundrobin2_grant)\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed20 <= (((main_port_cmd_payload_addr[10:9] == 2'd2) & (~(((builder_locked2 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))))) & main_port_cmd_valid);\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed21 <= 22'd0;\n\tcase (builder_roundrobin3_grant)\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed21 <= {main_port_cmd_payload_addr[23:11], main_port_cmd_payload_addr[8:0]};\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed22 <= 1'd0;\n\tcase (builder_roundrobin3_grant)\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed22 <= main_port_cmd_payload_we;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed23 <= 1'd0;\n\tcase (builder_roundrobin3_grant)\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed23 <= (((main_port_cmd_payload_addr[10:9] == 2'd3) & (~(((builder_locked3 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))))) & main_port_cmd_valid);\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed24 <= 30'd0;\n\tcase (builder_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed24 <= main_soclinux_cpu_ibus_adr;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed24 <= main_soclinux_cpu_dbus_adr;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed25 <= 32'd0;\n\tcase (builder_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed25 <= main_soclinux_cpu_ibus_dat_w;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed25 <= main_soclinux_cpu_dbus_dat_w;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed26 <= 4'd0;\n\tcase (builder_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed26 <= main_soclinux_cpu_ibus_sel;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed26 <= main_soclinux_cpu_dbus_sel;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed27 <= 1'd0;\n\tcase (builder_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed27 <= main_soclinux_cpu_ibus_cyc;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed27 <= main_soclinux_cpu_dbus_cyc;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed28 <= 1'd0;\n\tcase (builder_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed28 <= main_soclinux_cpu_ibus_stb;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed28 <= main_soclinux_cpu_dbus_stb;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed29 <= 1'd0;\n\tcase (builder_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed29 <= main_soclinux_cpu_ibus_we;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed29 <= main_soclinux_cpu_dbus_we;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed30 <= 3'd0;\n\tcase (builder_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed30 <= main_soclinux_cpu_ibus_cti;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed30 <= main_soclinux_cpu_dbus_cti;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_comb_rhs_array_muxed31 <= 2'd0;\n\tcase (builder_grant)\n\t\t1'd0: begin\n\t\t\tbuilder_comb_rhs_array_muxed31 <= main_soclinux_cpu_ibus_bte;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_comb_rhs_array_muxed31 <= main_soclinux_cpu_dbus_bte;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_sync_rhs_array_muxed0 <= 2'd0;\n\tcase (main_sdram_steerer_sel)\n\t\t1'd0: begin\n\t\t\tbuilder_sync_rhs_array_muxed0 <= main_sdram_nop_ba[1:0];\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_sync_rhs_array_muxed0 <= main_sdram_choose_req_cmd_payload_ba[1:0];\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_sync_rhs_array_muxed0 <= main_sdram_choose_req_cmd_payload_ba[1:0];\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_sync_rhs_array_muxed0 <= main_sdram_cmd_payload_ba[1:0];\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_sync_rhs_array_muxed1 <= 13'd0;\n\tcase (main_sdram_steerer_sel)\n\t\t1'd0: begin\n\t\t\tbuilder_sync_rhs_array_muxed1 <= main_sdram_nop_a;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_sync_rhs_array_muxed1 <= main_sdram_choose_req_cmd_payload_a;\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_sync_rhs_array_muxed1 <= main_sdram_choose_req_cmd_payload_a;\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_sync_rhs_array_muxed1 <= main_sdram_cmd_payload_a;\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_sync_rhs_array_muxed2 <= 1'd0;\n\tcase (main_sdram_steerer_sel)\n\t\t1'd0: begin\n\t\t\tbuilder_sync_rhs_array_muxed2 <= 1'd0;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_sync_rhs_array_muxed2 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas);\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_sync_rhs_array_muxed2 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas);\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_sync_rhs_array_muxed2 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas);\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_sync_rhs_array_muxed3 <= 1'd0;\n\tcase (main_sdram_steerer_sel)\n\t\t1'd0: begin\n\t\t\tbuilder_sync_rhs_array_muxed3 <= 1'd0;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_sync_rhs_array_muxed3 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras);\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_sync_rhs_array_muxed3 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras);\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_sync_rhs_array_muxed3 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras);\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_sync_rhs_array_muxed4 <= 1'd0;\n\tcase (main_sdram_steerer_sel)\n\t\t1'd0: begin\n\t\t\tbuilder_sync_rhs_array_muxed4 <= 1'd0;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_sync_rhs_array_muxed4 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we);\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_sync_rhs_array_muxed4 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we);\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_sync_rhs_array_muxed4 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we);\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_sync_rhs_array_muxed5 <= 1'd0;\n\tcase (main_sdram_steerer_sel)\n\t\t1'd0: begin\n\t\t\tbuilder_sync_rhs_array_muxed5 <= 1'd0;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_sync_rhs_array_muxed5 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read);\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_sync_rhs_array_muxed5 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read);\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_sync_rhs_array_muxed5 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read);\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_sync_rhs_array_muxed6 <= 1'd0;\n\tcase (main_sdram_steerer_sel)\n\t\t1'd0: begin\n\t\t\tbuilder_sync_rhs_array_muxed6 <= 1'd0;\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_sync_rhs_array_muxed6 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_sync_rhs_array_muxed6 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_sync_rhs_array_muxed6 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write);\n\t\tend\n\tendcase\nend\nalways @(*) begin\n\tbuilder_sync_f_array_muxed <= 1'd0;\n\tcase (soclinux_mosi_sel)\n\t\t1'd0: begin\n\t\t\tbuilder_sync_f_array_muxed <= soclinux_mosi_data[0];\n\t\tend\n\t\t1'd1: begin\n\t\t\tbuilder_sync_f_array_muxed <= soclinux_mosi_data[1];\n\t\tend\n\t\t2'd2: begin\n\t\t\tbuilder_sync_f_array_muxed <= soclinux_mosi_data[2];\n\t\tend\n\t\t2'd3: begin\n\t\t\tbuilder_sync_f_array_muxed <= soclinux_mosi_data[3];\n\t\tend\n\t\t3'd4: begin\n\t\t\tbuilder_sync_f_array_muxed <= soclinux_mosi_data[4];\n\t\tend\n\t\t3'd5: begin\n\t\t\tbuilder_sync_f_array_muxed <= soclinux_mosi_data[5];\n\t\tend\n\t\t3'd6: begin\n\t\t\tbuilder_sync_f_array_muxed <= soclinux_mosi_data[6];\n\t\tend\n\t\tdefault: begin\n\t\t\tbuilder_sync_f_array_muxed <= soclinux_mosi_data[7];\n\t\tend\n\tendcase\nend\nassign main_soclinux_rx = builder_regs1;\nassign sdrio_clk = sys_clk;\nassign sdrio_clk_1 = sys_clk;\nassign sdrio_clk_2 = sys_clk;\nassign sdrio_clk_3 = sys_clk;\nassign sdrio_clk_4 = sys_clk;\nassign sdrio_clk_5 = sys_clk;\nassign sdrio_clk_6 = sys_clk;\nassign sdrio_clk_7 = sys_clk;\nassign sdrio_clk_8 = sys_clk;\nassign sdrio_clk_9 = sys_clk;\nassign sdrio_clk_10 = sys_clk;\nassign sdrio_clk_11 = sys_clk;\nassign sdrio_clk_12 = sys_clk;\nassign sdrio_clk_13 = sys_clk;\nassign sdrio_clk_14 = sys_clk;\nassign sdrio_clk_15 = sys_clk;\n\nalways @(posedge sdrio_clk) begin\n\tbuilder_inferedsdrtristate0_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate1_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate2_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate3_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate4_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate5_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate6_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate7_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate8_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate9_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate10_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate11_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate12_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate13_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate14_oe <= main_dfi_p0_wrdata_en;\n\tbuilder_inferedsdrtristate15_oe <= main_dfi_p0_wrdata_en;\nend\n\nalways @(posedge sys_clk) begin\n\tif ((main_soclinux_soccontroller_bus_errors != 32'd4294967295)) begin\n\t\tif (main_soclinux_soccontroller_bus_error) begin\n\t\t\tmain_soclinux_soccontroller_bus_errors <= (main_soclinux_soccontroller_bus_errors + 1'd1);\n\t\tend\n\tend\n\tmain_soclinux_cpu_time <= (main_soclinux_cpu_time + 1'd1);\n\tif (main_soclinux_cpu_latch_re) begin\n\t\tmain_soclinux_cpu_time_status <= main_soclinux_cpu_time;\n\tend\n\tif (main_soclinux_cpu_latch_re) begin\n\t\tmain_soclinux_cpu_time_cmp <= main_soclinux_cpu_time_cmp_storage;\n\tend\n\tmain_soclinux_soclinux_ram_bus_ack <= 1'd0;\n\tif (((main_soclinux_soclinux_ram_bus_cyc & main_soclinux_soclinux_ram_bus_stb) & (~main_soclinux_soclinux_ram_bus_ack))) begin\n\t\tmain_soclinux_soclinux_ram_bus_ack <= 1'd1;\n\tend\n\tmain_soclinux_ram_bus_ram_bus_ack <= 1'd0;\n\tif (((main_soclinux_ram_bus_ram_bus_cyc & main_soclinux_ram_bus_ram_bus_stb) & (~main_soclinux_ram_bus_ram_bus_ack))) begin\n\t\tmain_soclinux_ram_bus_ram_bus_ack <= 1'd1;\n\tend\n\tmain_soclinux_sink_ready <= 1'd0;\n\tif (((main_soclinux_sink_valid & (~main_soclinux_tx_busy)) & (~main_soclinux_sink_ready))) begin\n\t\tmain_soclinux_tx_reg <= main_soclinux_sink_payload_data;\n\t\tmain_soclinux_tx_bitcount <= 1'd0;\n\t\tmain_soclinux_tx_busy <= 1'd1;\n\t\tserial_tx <= 1'd0;\n\tend else begin\n\t\tif ((main_soclinux_tx_clken & main_soclinux_tx_busy)) begin\n\t\t\tmain_soclinux_tx_bitcount <= (main_soclinux_tx_bitcount + 1'd1);\n\t\t\tif ((main_soclinux_tx_bitcount == 4'd8)) begin\n\t\t\t\tserial_tx <= 1'd1;\n\t\t\tend else begin\n\t\t\t\tif ((main_soclinux_tx_bitcount == 4'd9)) begin\n\t\t\t\t\tserial_tx <= 1'd1;\n\t\t\t\t\tmain_soclinux_tx_busy <= 1'd0;\n\t\t\t\t\tmain_soclinux_sink_ready <= 1'd1;\n\t\t\t\tend else begin\n\t\t\t\t\tserial_tx <= main_soclinux_tx_reg[0];\n\t\t\t\t\tmain_soclinux_tx_reg <= {1'd0, main_soclinux_tx_reg[7:1]};\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\tif (main_soclinux_tx_busy) begin\n\t\t{main_soclinux_tx_clken, main_soclinux_tx_clkphase} <= (main_soclinux_tx_clkphase + main_soclinux_storage);\n\tend else begin\n\t\t{main_soclinux_tx_clken, main_soclinux_tx_clkphase} <= main_soclinux_storage;\n\tend\n\tmain_soclinux_source_valid <= 1'd0;\n\tmain_soclinux_rx_r <= main_soclinux_rx;\n\tif ((~main_soclinux_rx_busy)) begin\n\t\tif (((~main_soclinux_rx) & main_soclinux_rx_r)) begin\n\t\t\tmain_soclinux_rx_busy <= 1'd1;\n\t\t\tmain_soclinux_rx_bitcount <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif (main_soclinux_rx_clken) begin\n\t\t\tmain_soclinux_rx_bitcount <= (main_soclinux_rx_bitcount + 1'd1);\n\t\t\tif ((main_soclinux_rx_bitcount == 1'd0)) begin\n\t\t\t\tif (main_soclinux_rx) begin\n\t\t\t\t\tmain_soclinux_rx_busy <= 1'd0;\n\t\t\t\tend\n\t\t\tend else begin\n\t\t\t\tif ((main_soclinux_rx_bitcount == 4'd9)) begin\n\t\t\t\t\tmain_soclinux_rx_busy <= 1'd0;\n\t\t\t\t\tif (main_soclinux_rx) begin\n\t\t\t\t\t\tmain_soclinux_source_payload_data <= main_soclinux_rx_reg;\n\t\t\t\t\t\tmain_soclinux_source_valid <= 1'd1;\n\t\t\t\t\tend\n\t\t\t\tend else begin\n\t\t\t\t\tmain_soclinux_rx_reg <= {main_soclinux_rx, main_soclinux_rx_reg[7:1]};\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\tif (main_soclinux_rx_busy) begin\n\t\t{main_soclinux_rx_clken, main_soclinux_rx_clkphase} <= (main_soclinux_rx_clkphase + main_soclinux_storage);\n\tend else begin\n\t\t{main_soclinux_rx_clken, main_soclinux_rx_clkphase} <= 32'd2147483648;\n\tend\n\tif (main_soclinux_uart_tx_clear) begin\n\t\tmain_soclinux_uart_tx_pending <= 1'd0;\n\tend\n\tmain_soclinux_uart_tx_old_trigger <= main_soclinux_uart_tx_trigger;\n\tif (((~main_soclinux_uart_tx_trigger) & main_soclinux_uart_tx_old_trigger)) begin\n\t\tmain_soclinux_uart_tx_pending <= 1'd1;\n\tend\n\tif (main_soclinux_uart_rx_clear) begin\n\t\tmain_soclinux_uart_rx_pending <= 1'd0;\n\tend\n\tmain_soclinux_uart_rx_old_trigger <= main_soclinux_uart_rx_trigger;\n\tif (((~main_soclinux_uart_rx_trigger) & main_soclinux_uart_rx_old_trigger)) begin\n\t\tmain_soclinux_uart_rx_pending <= 1'd1;\n\tend\n\tif (main_soclinux_uart_tx_fifo_syncfifo_re) begin\n\t\tmain_soclinux_uart_tx_fifo_readable <= 1'd1;\n\tend else begin\n\t\tif (main_soclinux_uart_tx_fifo_re) begin\n\t\t\tmain_soclinux_uart_tx_fifo_readable <= 1'd0;\n\t\tend\n\tend\n\tif (((main_soclinux_uart_tx_fifo_syncfifo_we & main_soclinux_uart_tx_fifo_syncfifo_writable) & (~main_soclinux_uart_tx_fifo_replace))) begin\n\t\tmain_soclinux_uart_tx_fifo_produce <= (main_soclinux_uart_tx_fifo_produce + 1'd1);\n\tend\n\tif (main_soclinux_uart_tx_fifo_do_read) begin\n\t\tmain_soclinux_uart_tx_fifo_consume <= (main_soclinux_uart_tx_fifo_consume + 1'd1);\n\tend\n\tif (((main_soclinux_uart_tx_fifo_syncfifo_we & main_soclinux_uart_tx_fifo_syncfifo_writable) & (~main_soclinux_uart_tx_fifo_replace))) begin\n\t\tif ((~main_soclinux_uart_tx_fifo_do_read)) begin\n\t\t\tmain_soclinux_uart_tx_fifo_level0 <= (main_soclinux_uart_tx_fifo_level0 + 1'd1);\n\t\tend\n\tend else begin\n\t\tif (main_soclinux_uart_tx_fifo_do_read) begin\n\t\t\tmain_soclinux_uart_tx_fifo_level0 <= (main_soclinux_uart_tx_fifo_level0 - 1'd1);\n\t\tend\n\tend\n\tif (main_soclinux_uart_rx_fifo_syncfifo_re) begin\n\t\tmain_soclinux_uart_rx_fifo_readable <= 1'd1;\n\tend else begin\n\t\tif (main_soclinux_uart_rx_fifo_re) begin\n\t\t\tmain_soclinux_uart_rx_fifo_readable <= 1'd0;\n\t\tend\n\tend\n\tif (((main_soclinux_uart_rx_fifo_syncfifo_we & main_soclinux_uart_rx_fifo_syncfifo_writable) & (~main_soclinux_uart_rx_fifo_replace))) begin\n\t\tmain_soclinux_uart_rx_fifo_produce <= (main_soclinux_uart_rx_fifo_produce + 1'd1);\n\tend\n\tif (main_soclinux_uart_rx_fifo_do_read) begin\n\t\tmain_soclinux_uart_rx_fifo_consume <= (main_soclinux_uart_rx_fifo_consume + 1'd1);\n\tend\n\tif (((main_soclinux_uart_rx_fifo_syncfifo_we & main_soclinux_uart_rx_fifo_syncfifo_writable) & (~main_soclinux_uart_rx_fifo_replace))) begin\n\t\tif ((~main_soclinux_uart_rx_fifo_do_read)) begin\n\t\t\tmain_soclinux_uart_rx_fifo_level0 <= (main_soclinux_uart_rx_fifo_level0 + 1'd1);\n\t\tend\n\tend else begin\n\t\tif (main_soclinux_uart_rx_fifo_do_read) begin\n\t\t\tmain_soclinux_uart_rx_fifo_level0 <= (main_soclinux_uart_rx_fifo_level0 - 1'd1);\n\t\tend\n\tend\n\tif (main_soclinux_uart_reset) begin\n\t\tmain_soclinux_uart_tx_pending <= 1'd0;\n\t\tmain_soclinux_uart_tx_old_trigger <= 1'd0;\n\t\tmain_soclinux_uart_rx_pending <= 1'd0;\n\t\tmain_soclinux_uart_rx_old_trigger <= 1'd0;\n\t\tmain_soclinux_uart_tx_fifo_readable <= 1'd0;\n\t\tmain_soclinux_uart_tx_fifo_level0 <= 5'd0;\n\t\tmain_soclinux_uart_tx_fifo_produce <= 4'd0;\n\t\tmain_soclinux_uart_tx_fifo_consume <= 4'd0;\n\t\tmain_soclinux_uart_rx_fifo_readable <= 1'd0;\n\t\tmain_soclinux_uart_rx_fifo_level0 <= 5'd0;\n\t\tmain_soclinux_uart_rx_fifo_produce <= 4'd0;\n\t\tmain_soclinux_uart_rx_fifo_consume <= 4'd0;\n\tend\n\tif (main_soclinux_timer_en_storage) begin\n\t\tif ((main_soclinux_timer_value == 1'd0)) begin\n\t\t\tmain_soclinux_timer_value <= main_soclinux_timer_reload_storage;\n\t\tend else begin\n\t\t\tmain_soclinux_timer_value <= (main_soclinux_timer_value - 1'd1);\n\t\tend\n\tend else begin\n\t\tmain_soclinux_timer_value <= main_soclinux_timer_load_storage;\n\tend\n\tif (main_soclinux_timer_update_value_re) begin\n\t\tmain_soclinux_timer_value_status <= main_soclinux_timer_value;\n\tend\n\tif (main_soclinux_timer_zero_clear) begin\n\t\tmain_soclinux_timer_zero_pending <= 1'd0;\n\tend\n\tmain_soclinux_timer_zero_old_trigger <= main_soclinux_timer_zero_trigger;\n\tif (((~main_soclinux_timer_zero_trigger) & main_soclinux_timer_zero_old_trigger)) begin\n\t\tmain_soclinux_timer_zero_pending <= 1'd1;\n\tend\n\tmain_rddata_en <= {main_rddata_en, main_dfi_p0_rddata_en};\n\tmain_dfi_p0_rddata_valid <= main_rddata_en[2];\n\tif (main_sdram_inti_p0_rddata_valid) begin\n\t\tmain_sdram_rddata_status <= main_sdram_inti_p0_rddata;\n\tend\n\tif ((main_sdram_timer_wait & (~main_sdram_timer_done0))) begin\n\t\tmain_sdram_timer_count1 <= (main_sdram_timer_count1 - 1'd1);\n\tend else begin\n\t\tmain_sdram_timer_count1 <= 9'd390;\n\tend\n\tmain_sdram_postponer_req_o <= 1'd0;\n\tif (main_sdram_postponer_req_i) begin\n\t\tmain_sdram_postponer_count <= (main_sdram_postponer_count - 1'd1);\n\t\tif ((main_sdram_postponer_count == 1'd0)) begin\n\t\t\tmain_sdram_postponer_count <= 1'd0;\n\t\t\tmain_sdram_postponer_req_o <= 1'd1;\n\t\tend\n\tend\n\tif (main_sdram_sequencer_start0) begin\n\t\tmain_sdram_sequencer_count <= 1'd0;\n\tend else begin\n\t\tif (main_sdram_sequencer_done1) begin\n\t\t\tif ((main_sdram_sequencer_count != 1'd0)) begin\n\t\t\t\tmain_sdram_sequencer_count <= (main_sdram_sequencer_count - 1'd1);\n\t\t\tend\n\t\tend\n\tend\n\tmain_sdram_cmd_payload_a <= 1'd0;\n\tmain_sdram_cmd_payload_ba <= 1'd0;\n\tmain_sdram_cmd_payload_cas <= 1'd0;\n\tmain_sdram_cmd_payload_ras <= 1'd0;\n\tmain_sdram_cmd_payload_we <= 1'd0;\n\tmain_sdram_sequencer_done1 <= 1'd0;\n\tif ((main_sdram_sequencer_start1 & (main_sdram_sequencer_counter == 1'd0))) begin\n\t\tmain_sdram_cmd_payload_a <= 11'd1024;\n\t\tmain_sdram_cmd_payload_ba <= 1'd0;\n\t\tmain_sdram_cmd_payload_cas <= 1'd0;\n\t\tmain_sdram_cmd_payload_ras <= 1'd1;\n\t\tmain_sdram_cmd_payload_we <= 1'd1;\n\tend\n\tif ((main_sdram_sequencer_counter == 1'd1)) begin\n\t\tmain_sdram_cmd_payload_a <= 1'd0;\n\t\tmain_sdram_cmd_payload_ba <= 1'd0;\n\t\tmain_sdram_cmd_payload_cas <= 1'd1;\n\t\tmain_sdram_cmd_payload_ras <= 1'd1;\n\t\tmain_sdram_cmd_payload_we <= 1'd0;\n\tend\n\tif ((main_sdram_sequencer_counter == 3'd5)) begin\n\t\tmain_sdram_cmd_payload_a <= 1'd0;\n\t\tmain_sdram_cmd_payload_ba <= 1'd0;\n\t\tmain_sdram_cmd_payload_cas <= 1'd0;\n\t\tmain_sdram_cmd_payload_ras <= 1'd0;\n\t\tmain_sdram_cmd_payload_we <= 1'd0;\n\t\tmain_sdram_sequencer_done1 <= 1'd1;\n\tend\n\tif ((main_sdram_sequencer_counter == 3'd5)) begin\n\t\tmain_sdram_sequencer_counter <= 1'd0;\n\tend else begin\n\t\tif ((main_sdram_sequencer_counter != 1'd0)) begin\n\t\t\tmain_sdram_sequencer_counter <= (main_sdram_sequencer_counter + 1'd1);\n\t\tend else begin\n\t\t\tif (main_sdram_sequencer_start1) begin\n\t\t\t\tmain_sdram_sequencer_counter <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tbuilder_refresher_state <= builder_refresher_next_state;\n\tif (main_sdram_bankmachine0_row_close) begin\n\t\tmain_sdram_bankmachine0_row_opened <= 1'd0;\n\tend else begin\n\t\tif (main_sdram_bankmachine0_row_open) begin\n\t\t\tmain_sdram_bankmachine0_row_opened <= 1'd1;\n\t\t\tmain_sdram_bankmachine0_row <= main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];\n\t\tend\n\tend\n\tif (((main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin\n\t\tmain_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);\n\tend\n\tif (main_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin\n\t\tmain_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);\n\tend\n\tif (((main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin\n\t\tif ((~main_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin\n\t\t\tmain_sdram_bankmachine0_cmd_buffer_lookahead_level <= (main_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);\n\t\tend\n\tend else begin\n\t\tif (main_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin\n\t\t\tmain_sdram_bankmachine0_cmd_buffer_lookahead_level <= (main_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);\n\t\tend\n\tend\n\tif (((~main_sdram_bankmachine0_cmd_buffer_source_valid) | main_sdram_bankmachine0_cmd_buffer_source_ready)) begin\n\t\tmain_sdram_bankmachine0_cmd_buffer_source_valid <= main_sdram_bankmachine0_cmd_buffer_sink_valid;\n\t\tmain_sdram_bankmachine0_cmd_buffer_source_first <= main_sdram_bankmachine0_cmd_buffer_sink_first;\n\t\tmain_sdram_bankmachine0_cmd_buffer_source_last <= main_sdram_bankmachine0_cmd_buffer_sink_last;\n\t\tmain_sdram_bankmachine0_cmd_buffer_source_payload_we <= main_sdram_bankmachine0_cmd_buffer_sink_payload_we;\n\t\tmain_sdram_bankmachine0_cmd_buffer_source_payload_addr <= main_sdram_bankmachine0_cmd_buffer_sink_payload_addr;\n\tend\n\tif (main_sdram_bankmachine0_twtpcon_valid) begin\n\t\tmain_sdram_bankmachine0_twtpcon_count <= 2'd3;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_bankmachine0_twtpcon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_bankmachine0_twtpcon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_bankmachine0_twtpcon_ready)) begin\n\t\t\tmain_sdram_bankmachine0_twtpcon_count <= (main_sdram_bankmachine0_twtpcon_count - 1'd1);\n\t\t\tif ((main_sdram_bankmachine0_twtpcon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_bankmachine0_twtpcon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tif (main_sdram_bankmachine0_trccon_valid) begin\n\t\tmain_sdram_bankmachine0_trccon_count <= 2'd3;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_bankmachine0_trccon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_bankmachine0_trccon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_bankmachine0_trccon_ready)) begin\n\t\t\tmain_sdram_bankmachine0_trccon_count <= (main_sdram_bankmachine0_trccon_count - 1'd1);\n\t\t\tif ((main_sdram_bankmachine0_trccon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_bankmachine0_trccon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tif (main_sdram_bankmachine0_trascon_valid) begin\n\t\tmain_sdram_bankmachine0_trascon_count <= 2'd2;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_bankmachine0_trascon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_bankmachine0_trascon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_bankmachine0_trascon_ready)) begin\n\t\t\tmain_sdram_bankmachine0_trascon_count <= (main_sdram_bankmachine0_trascon_count - 1'd1);\n\t\t\tif ((main_sdram_bankmachine0_trascon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_bankmachine0_trascon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tbuilder_bankmachine0_state <= builder_bankmachine0_next_state;\n\tif (main_sdram_bankmachine1_row_close) begin\n\t\tmain_sdram_bankmachine1_row_opened <= 1'd0;\n\tend else begin\n\t\tif (main_sdram_bankmachine1_row_open) begin\n\t\t\tmain_sdram_bankmachine1_row_opened <= 1'd1;\n\t\t\tmain_sdram_bankmachine1_row <= main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];\n\t\tend\n\tend\n\tif (((main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin\n\t\tmain_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);\n\tend\n\tif (main_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin\n\t\tmain_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);\n\tend\n\tif (((main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin\n\t\tif ((~main_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin\n\t\t\tmain_sdram_bankmachine1_cmd_buffer_lookahead_level <= (main_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);\n\t\tend\n\tend else begin\n\t\tif (main_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin\n\t\t\tmain_sdram_bankmachine1_cmd_buffer_lookahead_level <= (main_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);\n\t\tend\n\tend\n\tif (((~main_sdram_bankmachine1_cmd_buffer_source_valid) | main_sdram_bankmachine1_cmd_buffer_source_ready)) begin\n\t\tmain_sdram_bankmachine1_cmd_buffer_source_valid <= main_sdram_bankmachine1_cmd_buffer_sink_valid;\n\t\tmain_sdram_bankmachine1_cmd_buffer_source_first <= main_sdram_bankmachine1_cmd_buffer_sink_first;\n\t\tmain_sdram_bankmachine1_cmd_buffer_source_last <= main_sdram_bankmachine1_cmd_buffer_sink_last;\n\t\tmain_sdram_bankmachine1_cmd_buffer_source_payload_we <= main_sdram_bankmachine1_cmd_buffer_sink_payload_we;\n\t\tmain_sdram_bankmachine1_cmd_buffer_source_payload_addr <= main_sdram_bankmachine1_cmd_buffer_sink_payload_addr;\n\tend\n\tif (main_sdram_bankmachine1_twtpcon_valid) begin\n\t\tmain_sdram_bankmachine1_twtpcon_count <= 2'd3;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_bankmachine1_twtpcon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_bankmachine1_twtpcon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_bankmachine1_twtpcon_ready)) begin\n\t\t\tmain_sdram_bankmachine1_twtpcon_count <= (main_sdram_bankmachine1_twtpcon_count - 1'd1);\n\t\t\tif ((main_sdram_bankmachine1_twtpcon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_bankmachine1_twtpcon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tif (main_sdram_bankmachine1_trccon_valid) begin\n\t\tmain_sdram_bankmachine1_trccon_count <= 2'd3;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_bankmachine1_trccon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_bankmachine1_trccon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_bankmachine1_trccon_ready)) begin\n\t\t\tmain_sdram_bankmachine1_trccon_count <= (main_sdram_bankmachine1_trccon_count - 1'd1);\n\t\t\tif ((main_sdram_bankmachine1_trccon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_bankmachine1_trccon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tif (main_sdram_bankmachine1_trascon_valid) begin\n\t\tmain_sdram_bankmachine1_trascon_count <= 2'd2;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_bankmachine1_trascon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_bankmachine1_trascon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_bankmachine1_trascon_ready)) begin\n\t\t\tmain_sdram_bankmachine1_trascon_count <= (main_sdram_bankmachine1_trascon_count - 1'd1);\n\t\t\tif ((main_sdram_bankmachine1_trascon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_bankmachine1_trascon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tbuilder_bankmachine1_state <= builder_bankmachine1_next_state;\n\tif (main_sdram_bankmachine2_row_close) begin\n\t\tmain_sdram_bankmachine2_row_opened <= 1'd0;\n\tend else begin\n\t\tif (main_sdram_bankmachine2_row_open) begin\n\t\t\tmain_sdram_bankmachine2_row_opened <= 1'd1;\n\t\t\tmain_sdram_bankmachine2_row <= main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];\n\t\tend\n\tend\n\tif (((main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin\n\t\tmain_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);\n\tend\n\tif (main_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin\n\t\tmain_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);\n\tend\n\tif (((main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin\n\t\tif ((~main_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin\n\t\t\tmain_sdram_bankmachine2_cmd_buffer_lookahead_level <= (main_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);\n\t\tend\n\tend else begin\n\t\tif (main_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin\n\t\t\tmain_sdram_bankmachine2_cmd_buffer_lookahead_level <= (main_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);\n\t\tend\n\tend\n\tif (((~main_sdram_bankmachine2_cmd_buffer_source_valid) | main_sdram_bankmachine2_cmd_buffer_source_ready)) begin\n\t\tmain_sdram_bankmachine2_cmd_buffer_source_valid <= main_sdram_bankmachine2_cmd_buffer_sink_valid;\n\t\tmain_sdram_bankmachine2_cmd_buffer_source_first <= main_sdram_bankmachine2_cmd_buffer_sink_first;\n\t\tmain_sdram_bankmachine2_cmd_buffer_source_last <= main_sdram_bankmachine2_cmd_buffer_sink_last;\n\t\tmain_sdram_bankmachine2_cmd_buffer_source_payload_we <= main_sdram_bankmachine2_cmd_buffer_sink_payload_we;\n\t\tmain_sdram_bankmachine2_cmd_buffer_source_payload_addr <= main_sdram_bankmachine2_cmd_buffer_sink_payload_addr;\n\tend\n\tif (main_sdram_bankmachine2_twtpcon_valid) begin\n\t\tmain_sdram_bankmachine2_twtpcon_count <= 2'd3;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_bankmachine2_twtpcon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_bankmachine2_twtpcon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_bankmachine2_twtpcon_ready)) begin\n\t\t\tmain_sdram_bankmachine2_twtpcon_count <= (main_sdram_bankmachine2_twtpcon_count - 1'd1);\n\t\t\tif ((main_sdram_bankmachine2_twtpcon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_bankmachine2_twtpcon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tif (main_sdram_bankmachine2_trccon_valid) begin\n\t\tmain_sdram_bankmachine2_trccon_count <= 2'd3;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_bankmachine2_trccon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_bankmachine2_trccon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_bankmachine2_trccon_ready)) begin\n\t\t\tmain_sdram_bankmachine2_trccon_count <= (main_sdram_bankmachine2_trccon_count - 1'd1);\n\t\t\tif ((main_sdram_bankmachine2_trccon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_bankmachine2_trccon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tif (main_sdram_bankmachine2_trascon_valid) begin\n\t\tmain_sdram_bankmachine2_trascon_count <= 2'd2;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_bankmachine2_trascon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_bankmachine2_trascon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_bankmachine2_trascon_ready)) begin\n\t\t\tmain_sdram_bankmachine2_trascon_count <= (main_sdram_bankmachine2_trascon_count - 1'd1);\n\t\t\tif ((main_sdram_bankmachine2_trascon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_bankmachine2_trascon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tbuilder_bankmachine2_state <= builder_bankmachine2_next_state;\n\tif (main_sdram_bankmachine3_row_close) begin\n\t\tmain_sdram_bankmachine3_row_opened <= 1'd0;\n\tend else begin\n\t\tif (main_sdram_bankmachine3_row_open) begin\n\t\t\tmain_sdram_bankmachine3_row_opened <= 1'd1;\n\t\t\tmain_sdram_bankmachine3_row <= main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];\n\t\tend\n\tend\n\tif (((main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin\n\t\tmain_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);\n\tend\n\tif (main_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin\n\t\tmain_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);\n\tend\n\tif (((main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin\n\t\tif ((~main_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin\n\t\t\tmain_sdram_bankmachine3_cmd_buffer_lookahead_level <= (main_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);\n\t\tend\n\tend else begin\n\t\tif (main_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin\n\t\t\tmain_sdram_bankmachine3_cmd_buffer_lookahead_level <= (main_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);\n\t\tend\n\tend\n\tif (((~main_sdram_bankmachine3_cmd_buffer_source_valid) | main_sdram_bankmachine3_cmd_buffer_source_ready)) begin\n\t\tmain_sdram_bankmachine3_cmd_buffer_source_valid <= main_sdram_bankmachine3_cmd_buffer_sink_valid;\n\t\tmain_sdram_bankmachine3_cmd_buffer_source_first <= main_sdram_bankmachine3_cmd_buffer_sink_first;\n\t\tmain_sdram_bankmachine3_cmd_buffer_source_last <= main_sdram_bankmachine3_cmd_buffer_sink_last;\n\t\tmain_sdram_bankmachine3_cmd_buffer_source_payload_we <= main_sdram_bankmachine3_cmd_buffer_sink_payload_we;\n\t\tmain_sdram_bankmachine3_cmd_buffer_source_payload_addr <= main_sdram_bankmachine3_cmd_buffer_sink_payload_addr;\n\tend\n\tif (main_sdram_bankmachine3_twtpcon_valid) begin\n\t\tmain_sdram_bankmachine3_twtpcon_count <= 2'd3;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_bankmachine3_twtpcon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_bankmachine3_twtpcon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_bankmachine3_twtpcon_ready)) begin\n\t\t\tmain_sdram_bankmachine3_twtpcon_count <= (main_sdram_bankmachine3_twtpcon_count - 1'd1);\n\t\t\tif ((main_sdram_bankmachine3_twtpcon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_bankmachine3_twtpcon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tif (main_sdram_bankmachine3_trccon_valid) begin\n\t\tmain_sdram_bankmachine3_trccon_count <= 2'd3;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_bankmachine3_trccon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_bankmachine3_trccon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_bankmachine3_trccon_ready)) begin\n\t\t\tmain_sdram_bankmachine3_trccon_count <= (main_sdram_bankmachine3_trccon_count - 1'd1);\n\t\t\tif ((main_sdram_bankmachine3_trccon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_bankmachine3_trccon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tif (main_sdram_bankmachine3_trascon_valid) begin\n\t\tmain_sdram_bankmachine3_trascon_count <= 2'd2;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_bankmachine3_trascon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_bankmachine3_trascon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_bankmachine3_trascon_ready)) begin\n\t\t\tmain_sdram_bankmachine3_trascon_count <= (main_sdram_bankmachine3_trascon_count - 1'd1);\n\t\t\tif ((main_sdram_bankmachine3_trascon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_bankmachine3_trascon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tbuilder_bankmachine3_state <= builder_bankmachine3_next_state;\n\tif ((~main_sdram_en0)) begin\n\t\tmain_sdram_time0 <= 5'd31;\n\tend else begin\n\t\tif ((~main_sdram_max_time0)) begin\n\t\t\tmain_sdram_time0 <= (main_sdram_time0 - 1'd1);\n\t\tend\n\tend\n\tif ((~main_sdram_en1)) begin\n\t\tmain_sdram_time1 <= 4'd15;\n\tend else begin\n\t\tif ((~main_sdram_max_time1)) begin\n\t\t\tmain_sdram_time1 <= (main_sdram_time1 - 1'd1);\n\t\tend\n\tend\n\tif (main_sdram_choose_cmd_ce) begin\n\t\tcase (main_sdram_choose_cmd_grant)\n\t\t\t1'd0: begin\n\t\t\t\tif (main_sdram_choose_cmd_request[1]) begin\n\t\t\t\t\tmain_sdram_choose_cmd_grant <= 1'd1;\n\t\t\t\tend else begin\n\t\t\t\t\tif (main_sdram_choose_cmd_request[2]) begin\n\t\t\t\t\t\tmain_sdram_choose_cmd_grant <= 2'd2;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (main_sdram_choose_cmd_request[3]) begin\n\t\t\t\t\t\t\tmain_sdram_choose_cmd_grant <= 2'd3;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\t1'd1: begin\n\t\t\t\tif (main_sdram_choose_cmd_request[2]) begin\n\t\t\t\t\tmain_sdram_choose_cmd_grant <= 2'd2;\n\t\t\t\tend else begin\n\t\t\t\t\tif (main_sdram_choose_cmd_request[3]) begin\n\t\t\t\t\t\tmain_sdram_choose_cmd_grant <= 2'd3;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (main_sdram_choose_cmd_request[0]) begin\n\t\t\t\t\t\t\tmain_sdram_choose_cmd_grant <= 1'd0;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\t2'd2: begin\n\t\t\t\tif (main_sdram_choose_cmd_request[3]) begin\n\t\t\t\t\tmain_sdram_choose_cmd_grant <= 2'd3;\n\t\t\t\tend else begin\n\t\t\t\t\tif (main_sdram_choose_cmd_request[0]) begin\n\t\t\t\t\t\tmain_sdram_choose_cmd_grant <= 1'd0;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (main_sdram_choose_cmd_request[1]) begin\n\t\t\t\t\t\t\tmain_sdram_choose_cmd_grant <= 1'd1;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\t2'd3: begin\n\t\t\t\tif (main_sdram_choose_cmd_request[0]) begin\n\t\t\t\t\tmain_sdram_choose_cmd_grant <= 1'd0;\n\t\t\t\tend else begin\n\t\t\t\t\tif (main_sdram_choose_cmd_request[1]) begin\n\t\t\t\t\t\tmain_sdram_choose_cmd_grant <= 1'd1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (main_sdram_choose_cmd_request[2]) begin\n\t\t\t\t\t\t\tmain_sdram_choose_cmd_grant <= 2'd2;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tendcase\n\tend\n\tif (main_sdram_choose_req_ce) begin\n\t\tcase (main_sdram_choose_req_grant)\n\t\t\t1'd0: begin\n\t\t\t\tif (main_sdram_choose_req_request[1]) begin\n\t\t\t\t\tmain_sdram_choose_req_grant <= 1'd1;\n\t\t\t\tend else begin\n\t\t\t\t\tif (main_sdram_choose_req_request[2]) begin\n\t\t\t\t\t\tmain_sdram_choose_req_grant <= 2'd2;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (main_sdram_choose_req_request[3]) begin\n\t\t\t\t\t\t\tmain_sdram_choose_req_grant <= 2'd3;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\t1'd1: begin\n\t\t\t\tif (main_sdram_choose_req_request[2]) begin\n\t\t\t\t\tmain_sdram_choose_req_grant <= 2'd2;\n\t\t\t\tend else begin\n\t\t\t\t\tif (main_sdram_choose_req_request[3]) begin\n\t\t\t\t\t\tmain_sdram_choose_req_grant <= 2'd3;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (main_sdram_choose_req_request[0]) begin\n\t\t\t\t\t\t\tmain_sdram_choose_req_grant <= 1'd0;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\t2'd2: begin\n\t\t\t\tif (main_sdram_choose_req_request[3]) begin\n\t\t\t\t\tmain_sdram_choose_req_grant <= 2'd3;\n\t\t\t\tend else begin\n\t\t\t\t\tif (main_sdram_choose_req_request[0]) begin\n\t\t\t\t\t\tmain_sdram_choose_req_grant <= 1'd0;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (main_sdram_choose_req_request[1]) begin\n\t\t\t\t\t\t\tmain_sdram_choose_req_grant <= 1'd1;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\t2'd3: begin\n\t\t\t\tif (main_sdram_choose_req_request[0]) begin\n\t\t\t\t\tmain_sdram_choose_req_grant <= 1'd0;\n\t\t\t\tend else begin\n\t\t\t\t\tif (main_sdram_choose_req_request[1]) begin\n\t\t\t\t\t\tmain_sdram_choose_req_grant <= 1'd1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (main_sdram_choose_req_request[2]) begin\n\t\t\t\t\t\t\tmain_sdram_choose_req_grant <= 2'd2;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tendcase\n\tend\n\tmain_sdram_dfi_p0_cs_n <= 1'd0;\n\tmain_sdram_dfi_p0_bank <= builder_sync_rhs_array_muxed0;\n\tmain_sdram_dfi_p0_address <= builder_sync_rhs_array_muxed1;\n\tmain_sdram_dfi_p0_cas_n <= (~builder_sync_rhs_array_muxed2);\n\tmain_sdram_dfi_p0_ras_n <= (~builder_sync_rhs_array_muxed3);\n\tmain_sdram_dfi_p0_we_n <= (~builder_sync_rhs_array_muxed4);\n\tmain_sdram_dfi_p0_rddata_en <= builder_sync_rhs_array_muxed5;\n\tmain_sdram_dfi_p0_wrdata_en <= builder_sync_rhs_array_muxed6;\n\tif (main_sdram_trrdcon_valid) begin\n\t\tmain_sdram_trrdcon_count <= 1'd0;\n\t\tif (1'd1) begin\n\t\t\tmain_sdram_trrdcon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_trrdcon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_trrdcon_ready)) begin\n\t\t\tmain_sdram_trrdcon_count <= (main_sdram_trrdcon_count - 1'd1);\n\t\t\tif ((main_sdram_trrdcon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_trrdcon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tif (main_sdram_tccdcon_valid) begin\n\t\tmain_sdram_tccdcon_count <= 1'd0;\n\t\tif (1'd1) begin\n\t\t\tmain_sdram_tccdcon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_tccdcon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_tccdcon_ready)) begin\n\t\t\tmain_sdram_tccdcon_count <= (main_sdram_tccdcon_count - 1'd1);\n\t\t\tif ((main_sdram_tccdcon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_tccdcon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tif (main_sdram_twtrcon_valid) begin\n\t\tmain_sdram_twtrcon_count <= 3'd4;\n\t\tif (1'd0) begin\n\t\t\tmain_sdram_twtrcon_ready <= 1'd1;\n\t\tend else begin\n\t\t\tmain_sdram_twtrcon_ready <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((~main_sdram_twtrcon_ready)) begin\n\t\t\tmain_sdram_twtrcon_count <= (main_sdram_twtrcon_count - 1'd1);\n\t\t\tif ((main_sdram_twtrcon_count == 1'd1)) begin\n\t\t\t\tmain_sdram_twtrcon_ready <= 1'd1;\n\t\t\tend\n\t\tend\n\tend\n\tbuilder_multiplexer_state <= builder_multiplexer_next_state;\n\tbuilder_new_master_wdata_ready <= ((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_wdata_ready));\n\tbuilder_new_master_rdata_valid0 <= ((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_rdata_valid));\n\tbuilder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;\n\tbuilder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;\n\tbuilder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;\n\tmain_adr_offset_r <= main_wb_sdram_adr[1:0];\n\tbuilder_fullmemorywe_state <= builder_fullmemorywe_next_state;\n\tif (main_interface_ack) begin\n\t\tmain_wishbone_bridge_cmd_consumed <= 1'd0;\n\t\tmain_wishbone_bridge_wdata_consumed <= 1'd0;\n\tend else begin\n\t\tif ((main_wishbone_bridge_cmd_valid & main_wishbone_bridge_cmd_ready)) begin\n\t\t\tmain_wishbone_bridge_cmd_consumed <= 1'd1;\n\t\tend\n\t\tif ((main_wishbone_bridge_wdata_valid & main_wishbone_bridge_wdata_ready)) begin\n\t\t\tmain_wishbone_bridge_wdata_consumed <= 1'd1;\n\t\tend\n\tend\n\tbuilder_litedramwishbone2native_state <= builder_litedramwishbone2native_next_state;\n\tif (main_wishbone_bridge_count_litedramwishbone2native_next_value_ce) begin\n\t\tmain_wishbone_bridge_count <= main_wishbone_bridge_count_litedramwishbone2native_next_value;\n\tend\n\tif ((main_wishbone_bridge_wdata_converter_converter_source_valid & main_wishbone_bridge_wdata_converter_converter_source_ready)) begin\n\t\tif (main_wishbone_bridge_wdata_converter_converter_last) begin\n\t\t\tmain_wishbone_bridge_wdata_converter_converter_mux <= 1'd0;\n\t\tend else begin\n\t\t\tmain_wishbone_bridge_wdata_converter_converter_mux <= (main_wishbone_bridge_wdata_converter_converter_mux + 1'd1);\n\t\tend\n\tend\n\tif (main_wishbone_bridge_rdata_converter_converter_source_ready) begin\n\t\tmain_wishbone_bridge_rdata_converter_converter_strobe_all <= 1'd0;\n\tend\n\tif (main_wishbone_bridge_rdata_converter_converter_load_part) begin\n\t\tif (((main_wishbone_bridge_rdata_converter_converter_demux == 3'd7) | main_wishbone_bridge_rdata_converter_converter_sink_last)) begin\n\t\t\tmain_wishbone_bridge_rdata_converter_converter_demux <= 1'd0;\n\t\t\tmain_wishbone_bridge_rdata_converter_converter_strobe_all <= 1'd1;\n\t\tend else begin\n\t\t\tmain_wishbone_bridge_rdata_converter_converter_demux <= (main_wishbone_bridge_rdata_converter_converter_demux + 1'd1);\n\t\tend\n\tend\n\tif ((main_wishbone_bridge_rdata_converter_converter_source_valid & main_wishbone_bridge_rdata_converter_converter_source_ready)) begin\n\t\tif ((main_wishbone_bridge_rdata_converter_converter_sink_valid & main_wishbone_bridge_rdata_converter_converter_sink_ready)) begin\n\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_first <= main_wishbone_bridge_rdata_converter_converter_sink_first;\n\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_last <= main_wishbone_bridge_rdata_converter_converter_sink_last;\n\t\tend else begin\n\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_first <= 1'd0;\n\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_last <= 1'd0;\n\t\tend\n\tend else begin\n\t\tif ((main_wishbone_bridge_rdata_converter_converter_sink_valid & main_wishbone_bridge_rdata_converter_converter_sink_ready)) begin\n\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_first <= (main_wishbone_bridge_rdata_converter_converter_sink_first | main_wishbone_bridge_rdata_converter_converter_source_first);\n\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_last <= (main_wishbone_bridge_rdata_converter_converter_sink_last | main_wishbone_bridge_rdata_converter_converter_source_last);\n\t\tend\n\tend\n\tif (main_wishbone_bridge_rdata_converter_converter_load_part) begin\n\t\tcase (main_wishbone_bridge_rdata_converter_converter_demux)\n\t\t\t1'd0: begin\n\t\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_payload_data[15:0] <= main_wishbone_bridge_rdata_converter_converter_sink_payload_data;\n\t\t\tend\n\t\t\t1'd1: begin\n\t\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_payload_data[31:16] <= main_wishbone_bridge_rdata_converter_converter_sink_payload_data;\n\t\t\tend\n\t\t\t2'd2: begin\n\t\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_payload_data[47:32] <= main_wishbone_bridge_rdata_converter_converter_sink_payload_data;\n\t\t\tend\n\t\t\t2'd3: begin\n\t\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_payload_data[63:48] <= main_wishbone_bridge_rdata_converter_converter_sink_payload_data;\n\t\t\tend\n\t\t\t3'd4: begin\n\t\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_payload_data[79:64] <= main_wishbone_bridge_rdata_converter_converter_sink_payload_data;\n\t\t\tend\n\t\t\t3'd5: begin\n\t\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_payload_data[95:80] <= main_wishbone_bridge_rdata_converter_converter_sink_payload_data;\n\t\t\tend\n\t\t\t3'd6: begin\n\t\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_payload_data[111:96] <= main_wishbone_bridge_rdata_converter_converter_sink_payload_data;\n\t\t\tend\n\t\t\t3'd7: begin\n\t\t\t\tmain_wishbone_bridge_rdata_converter_converter_source_payload_data[127:112] <= main_wishbone_bridge_rdata_converter_converter_sink_payload_data;\n\t\t\tend\n\t\tendcase\n\tend\n\tif (main_wishbone_bridge_rdata_converter_converter_load_part) begin\n\t\tmain_wishbone_bridge_rdata_converter_converter_source_payload_valid_token_count <= (main_wishbone_bridge_rdata_converter_converter_demux + 1'd1);\n\tend\n\tif (main_done) begin\n\t\tmain_chaser <= {main_chaser, (~main_chaser[7])};\n\tend\n\tif (main_re) begin\n\t\tmain_mode <= 1'd1;\n\tend\n\tif (main_wait) begin\n\t\tif ((~main_done)) begin\n\t\t\tmain_count <= (main_count - 1'd1);\n\t\tend\n\tend else begin\n\t\tmain_count <= 22'd3125000;\n\tend\n\tsoclinux_clk_divider1 <= (soclinux_clk_divider1 + 1'd1);\n\tif (soclinux_clk_rise) begin\n\t\tspisdcard_clk <= soclinux_clk_enable;\n\tend else begin\n\t\tif (soclinux_clk_fall) begin\n\t\t\tsoclinux_clk_divider1 <= 1'd0;\n\t\t\tspisdcard_clk <= 1'd0;\n\t\tend\n\tend\n\tspisdcard_cs_n <= ((~soclinux_cs) | (~soclinux_cs_enable));\n\tif (soclinux_mosi_latch) begin\n\t\tsoclinux_mosi_data <= soclinux_mosi;\n\t\tsoclinux_mosi_sel <= 3'd7;\n\tend else begin\n\t\tif (soclinux_clk_fall) begin\n\t\t\tif (soclinux_cs_enable) begin\n\t\t\t\tspisdcard_mosi <= builder_sync_f_array_muxed;\n\t\t\tend\n\t\t\tsoclinux_mosi_sel <= (soclinux_mosi_sel - 1'd1);\n\t\tend\n\tend\n\tif (soclinux_clk_rise) begin\n\t\tif (soclinux_loopback) begin\n\t\t\tsoclinux_miso_data <= {soclinux_miso_data, spisdcard_mosi};\n\t\tend else begin\n\t\t\tsoclinux_miso_data <= {soclinux_miso_data, spisdcard_miso};\n\t\tend\n\tend\n\tif (soclinux_miso_latch) begin\n\t\tsoclinux_miso <= soclinux_miso_data;\n\tend\n\tbuilder_spimaster_state <= builder_spimaster_next_state;\n\tif (soclinux_count_spimaster_next_value_ce) begin\n\t\tsoclinux_count <= soclinux_count_spimaster_next_value;\n\tend\n\tbuilder_state <= builder_next_state;\n\tif (builder_soclinux_dat_w_next_value_ce0) begin\n\t\tbuilder_soclinux_dat_w <= builder_soclinux_dat_w_next_value0;\n\tend\n\tif (builder_soclinux_adr_next_value_ce1) begin\n\t\tbuilder_soclinux_adr <= builder_soclinux_adr_next_value1;\n\tend\n\tif (builder_soclinux_we_next_value_ce2) begin\n\t\tbuilder_soclinux_we <= builder_soclinux_we_next_value2;\n\tend\n\tcase (builder_grant)\n\t\t1'd0: begin\n\t\t\tif ((~builder_request[0])) begin\n\t\t\t\tif (builder_request[1]) begin\n\t\t\t\t\tbuilder_grant <= 1'd1;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\t\t1'd1: begin\n\t\t\tif ((~builder_request[1])) begin\n\t\t\t\tif (builder_request[0]) begin\n\t\t\t\t\tbuilder_grant <= 1'd0;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tendcase\n\tbuilder_slave_sel_r <= builder_slave_sel;\n\tif (builder_wait) begin\n\t\tif ((~builder_done)) begin\n\t\t\tbuilder_count <= (builder_count - 1'd1);\n\t\tend\n\tend else begin\n\t\tbuilder_count <= 20'd1000000;\n\tend\n\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= 1'd0;\n\tif (builder_csr_bankarray_csrbank0_sel) begin\n\t\tcase (builder_csr_bankarray_interface0_bank_bus_adr[4:0])\n\t\t\t1'd0: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= main_soclinux_cpu_latch_w;\n\t\t\tend\n\t\t\t1'd1: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time7_w;\n\t\t\tend\n\t\t\t2'd2: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time6_w;\n\t\t\tend\n\t\t\t2'd3: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time5_w;\n\t\t\tend\n\t\t\t3'd4: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time4_w;\n\t\t\tend\n\t\t\t3'd5: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time3_w;\n\t\t\tend\n\t\t\t3'd6: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time2_w;\n\t\t\tend\n\t\t\t3'd7: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time1_w;\n\t\t\tend\n\t\t\t4'd8: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time0_w;\n\t\t\tend\n\t\t\t4'd9: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time_cmp7_w;\n\t\t\tend\n\t\t\t4'd10: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time_cmp6_w;\n\t\t\tend\n\t\t\t4'd11: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time_cmp5_w;\n\t\t\tend\n\t\t\t4'd12: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time_cmp4_w;\n\t\t\tend\n\t\t\t4'd13: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time_cmp3_w;\n\t\t\tend\n\t\t\t4'd14: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time_cmp2_w;\n\t\t\tend\n\t\t\t4'd15: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time_cmp1_w;\n\t\t\tend\n\t\t\t5'd16: begin\n\t\t\t\tbuilder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_timer_time_cmp0_w;\n\t\t\tend\n\t\tendcase\n\tend\n\tif (builder_csr_bankarray_csrbank0_timer_time_cmp7_re) begin\n\t\tmain_soclinux_cpu_time_cmp_storage[63:56] <= builder_csr_bankarray_csrbank0_timer_time_cmp7_r;\n\tend\n\tif (builder_csr_bankarray_csrbank0_timer_time_cmp6_re) begin\n\t\tmain_soclinux_cpu_time_cmp_storage[55:48] <= builder_csr_bankarray_csrbank0_timer_time_cmp6_r;\n\tend\n\tif (builder_csr_bankarray_csrbank0_timer_time_cmp5_re) begin\n\t\tmain_soclinux_cpu_time_cmp_storage[47:40] <= builder_csr_bankarray_csrbank0_timer_time_cmp5_r;\n\tend\n\tif (builder_csr_bankarray_csrbank0_timer_time_cmp4_re) begin\n\t\tmain_soclinux_cpu_time_cmp_storage[39:32] <= builder_csr_bankarray_csrbank0_timer_time_cmp4_r;\n\tend\n\tif (builder_csr_bankarray_csrbank0_timer_time_cmp3_re) begin\n\t\tmain_soclinux_cpu_time_cmp_storage[31:24] <= builder_csr_bankarray_csrbank0_timer_time_cmp3_r;\n\tend\n\tif (builder_csr_bankarray_csrbank0_timer_time_cmp2_re) begin\n\t\tmain_soclinux_cpu_time_cmp_storage[23:16] <= builder_csr_bankarray_csrbank0_timer_time_cmp2_r;\n\tend\n\tif (builder_csr_bankarray_csrbank0_timer_time_cmp1_re) begin\n\t\tmain_soclinux_cpu_time_cmp_storage[15:8] <= builder_csr_bankarray_csrbank0_timer_time_cmp1_r;\n\tend\n\tif (builder_csr_bankarray_csrbank0_timer_time_cmp0_re) begin\n\t\tmain_soclinux_cpu_time_cmp_storage[7:0] <= builder_csr_bankarray_csrbank0_timer_time_cmp0_r;\n\tend\n\tmain_soclinux_cpu_time_cmp_re <= builder_csr_bankarray_csrbank0_timer_time_cmp0_re;\n\tbuilder_csr_bankarray_interface1_bank_bus_dat_r <= 1'd0;\n\tif (builder_csr_bankarray_csrbank1_sel) begin\n\t\tcase (builder_csr_bankarray_interface1_bank_bus_adr[3:0])\n\t\t\t1'd0: begin\n\t\t\t\tbuilder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_reset0_w;\n\t\t\tend\n\t\t\t1'd1: begin\n\t\t\t\tbuilder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_scratch3_w;\n\t\t\tend\n\t\t\t2'd2: begin\n\t\t\t\tbuilder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_scratch2_w;\n\t\t\tend\n\t\t\t2'd3: begin\n\t\t\t\tbuilder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_scratch1_w;\n\t\t\tend\n\t\t\t3'd4: begin\n\t\t\t\tbuilder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_scratch0_w;\n\t\t\tend\n\t\t\t3'd5: begin\n\t\t\t\tbuilder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_bus_errors3_w;\n\t\t\tend\n\t\t\t3'd6: begin\n\t\t\t\tbuilder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_bus_errors2_w;\n\t\t\tend\n\t\t\t3'd7: begin\n\t\t\t\tbuilder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_bus_errors1_w;\n\t\t\tend\n\t\t\t4'd8: begin\n\t\t\t\tbuilder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_bus_errors0_w;\n\t\t\tend\n\t\tendcase\n\tend\n\tif (builder_csr_bankarray_csrbank1_reset0_re) begin\n\t\tmain_soclinux_soccontroller_reset_storage <= builder_csr_bankarray_csrbank1_reset0_r;\n\tend\n\tmain_soclinux_soccontroller_reset_re <= builder_csr_bankarray_csrbank1_reset0_re;\n\tif (builder_csr_bankarray_csrbank1_scratch3_re) begin\n\t\tmain_soclinux_soccontroller_scratch_storage[31:24] <= builder_csr_bankarray_csrbank1_scratch3_r;\n\tend\n\tif (builder_csr_bankarray_csrbank1_scratch2_re) begin\n\t\tmain_soclinux_soccontroller_scratch_storage[23:16] <= builder_csr_bankarray_csrbank1_scratch2_r;\n\tend\n\tif (builder_csr_bankarray_csrbank1_scratch1_re) begin\n\t\tmain_soclinux_soccontroller_scratch_storage[15:8] <= builder_csr_bankarray_csrbank1_scratch1_r;\n\tend\n\tif (builder_csr_bankarray_csrbank1_scratch0_re) begin\n\t\tmain_soclinux_soccontroller_scratch_storage[7:0] <= builder_csr_bankarray_csrbank1_scratch0_r;\n\tend\n\tmain_soclinux_soccontroller_scratch_re <= builder_csr_bankarray_csrbank1_scratch0_re;\n\tbuilder_csr_bankarray_sel_r <= builder_csr_bankarray_sel;\n\tbuilder_csr_bankarray_interface2_bank_bus_dat_r <= 1'd0;\n\tif (builder_csr_bankarray_csrbank2_sel) begin\n\t\tcase (builder_csr_bankarray_interface2_bank_bus_adr[0])\n\t\t\t1'd0: begin\n\t\t\t\tbuilder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_out0_w;\n\t\t\tend\n\t\tendcase\n\tend\n\tif (builder_csr_bankarray_csrbank2_out0_re) begin\n\t\tmain_storage[7:0] <= builder_csr_bankarray_csrbank2_out0_r;\n\tend\n\tmain_re <= builder_csr_bankarray_csrbank2_out0_re;\n\tbuilder_csr_bankarray_interface3_bank_bus_dat_r <= 1'd0;\n\tif (builder_csr_bankarray_csrbank3_sel) begin\n\t\tcase (builder_csr_bankarray_interface3_bank_bus_adr[3:0])\n\t\t\t1'd0: begin\n\t\t\t\tbuilder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_dfii_control0_w;\n\t\t\tend\n\t\t\t1'd1: begin\n\t\t\t\tbuilder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_dfii_pi0_command0_w;\n\t\t\tend\n\t\t\t2'd2: begin\n\t\t\t\tbuilder_csr_bankarray_interface3_bank_bus_dat_r <= main_sdram_command_issue_w;\n\t\t\tend\n\t\t\t2'd3: begin\n\t\t\t\tbuilder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_dfii_pi0_address1_w;\n\t\t\tend\n\t\t\t3'd4: begin\n\t\t\t\tbuilder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_dfii_pi0_address0_w;\n\t\t\tend\n\t\t\t3'd5: begin\n\t\t\t\tbuilder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_dfii_pi0_baddress0_w;\n\t\t\tend\n\t\t\t3'd6: begin\n\t\t\t\tbuilder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_dfii_pi0_wrdata1_w;\n\t\t\tend\n\t\t\t3'd7: begin\n\t\t\t\tbuilder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_dfii_pi0_wrdata0_w;\n\t\t\tend\n\t\t\t4'd8: begin\n\t\t\t\tbuilder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_dfii_pi0_rddata1_w;\n\t\t\tend\n\t\t\t4'd9: begin\n\t\t\t\tbuilder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_dfii_pi0_rddata0_w;\n\t\t\tend\n\t\tendcase\n\tend\n\tif (builder_csr_bankarray_csrbank3_dfii_control0_re) begin\n\t\tmain_sdram_storage[3:0] <= builder_csr_bankarray_csrbank3_dfii_control0_r;\n\tend\n\tmain_sdram_re <= builder_csr_bankarray_csrbank3_dfii_control0_re;\n\tif (builder_csr_bankarray_csrbank3_dfii_pi0_command0_re) begin\n\t\tmain_sdram_command_storage[5:0] <= builder_csr_bankarray_csrbank3_dfii_pi0_command0_r;\n\tend\n\tmain_sdram_command_re <= builder_csr_bankarray_csrbank3_dfii_pi0_command0_re;\n\tif (builder_csr_bankarray_csrbank3_dfii_pi0_address1_re) begin\n\t\tmain_sdram_address_storage[12:8] <= builder_csr_bankarray_csrbank3_dfii_pi0_address1_r;\n\tend\n\tif (builder_csr_bankarray_csrbank3_dfii_pi0_address0_re) begin\n\t\tmain_sdram_address_storage[7:0] <= builder_csr_bankarray_csrbank3_dfii_pi0_address0_r;\n\tend\n\tmain_sdram_address_re <= builder_csr_bankarray_csrbank3_dfii_pi0_address0_re;\n\tif (builder_csr_bankarray_csrbank3_dfii_pi0_baddress0_re) begin\n\t\tmain_sdram_baddress_storage[1:0] <= builder_csr_bankarray_csrbank3_dfii_pi0_baddress0_r;\n\tend\n\tmain_sdram_baddress_re <= builder_csr_bankarray_csrbank3_dfii_pi0_baddress0_re;\n\tif (builder_csr_bankarray_csrbank3_dfii_pi0_wrdata1_re) begin\n\t\tmain_sdram_wrdata_storage[15:8] <= builder_csr_bankarray_csrbank3_dfii_pi0_wrdata1_r;\n\tend\n\tif (builder_csr_bankarray_csrbank3_dfii_pi0_wrdata0_re) begin\n\t\tmain_sdram_wrdata_storage[7:0] <= builder_csr_bankarray_csrbank3_dfii_pi0_wrdata0_r;\n\tend\n\tmain_sdram_wrdata_re <= builder_csr_bankarray_csrbank3_dfii_pi0_wrdata0_re;\n\tbuilder_csr_bankarray_interface4_bank_bus_dat_r <= 1'd0;\n\tif (builder_csr_bankarray_csrbank4_sel) begin\n\t\tcase (builder_csr_bankarray_interface4_bank_bus_adr[3:0])\n\t\t\t1'd0: begin\n\t\t\t\tbuilder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_control1_w;\n\t\t\tend\n\t\t\t1'd1: begin\n\t\t\t\tbuilder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_control0_w;\n\t\t\tend\n\t\t\t2'd2: begin\n\t\t\t\tbuilder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_status_w;\n\t\t\tend\n\t\t\t2'd3: begin\n\t\t\t\tbuilder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_mosi0_w;\n\t\t\tend\n\t\t\t3'd4: begin\n\t\t\t\tbuilder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_miso_w;\n\t\t\tend\n\t\t\t3'd5: begin\n\t\t\t\tbuilder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_cs0_w;\n\t\t\tend\n\t\t\t3'd6: begin\n\t\t\t\tbuilder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_loopback0_w;\n\t\t\tend\n\t\t\t3'd7: begin\n\t\t\t\tbuilder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_clk_divider1_w;\n\t\t\tend\n\t\t\t4'd8: begin\n\t\t\t\tbuilder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_clk_divider0_w;\n\t\t\tend\n\t\tendcase\n\tend\n\tif (builder_csr_bankarray_csrbank4_control1_re) begin\n\t\tsoclinux_control_storage[15:8] <= builder_csr_bankarray_csrbank4_control1_r;\n\tend\n\tif (builder_csr_bankarray_csrbank4_control0_re) begin\n\t\tsoclinux_control_storage[7:0] <= builder_csr_bankarray_csrbank4_control0_r;\n\tend\n\tsoclinux_control_re <= builder_csr_bankarray_csrbank4_control0_re;\n\tif (builder_csr_bankarray_csrbank4_mosi0_re) begin\n\t\tsoclinux_mosi_storage[7:0] <= builder_csr_bankarray_csrbank4_mosi0_r;\n\tend\n\tsoclinux_mosi_re <= builder_csr_bankarray_csrbank4_mosi0_re;\n\tif (builder_csr_bankarray_csrbank4_cs0_re) begin\n\t\tsoclinux_cs_storage <= builder_csr_bankarray_csrbank4_cs0_r;\n\tend\n\tsoclinux_cs_re <= builder_csr_bankarray_csrbank4_cs0_re;\n\tif (builder_csr_bankarray_csrbank4_loopback0_re) begin\n\t\tsoclinux_loopback_storage <= builder_csr_bankarray_csrbank4_loopback0_r;\n\tend\n\tsoclinux_loopback_re <= builder_csr_bankarray_csrbank4_loopback0_re;\n\tif (builder_csr_bankarray_csrbank4_clk_divider1_re) begin\n\t\tsoclinux_storage[15:8] <= builder_csr_bankarray_csrbank4_clk_divider1_r;\n\tend\n\tif (builder_csr_bankarray_csrbank4_clk_divider0_re) begin\n\t\tsoclinux_storage[7:0] <= builder_csr_bankarray_csrbank4_clk_divider0_r;\n\tend\n\tsoclinux_re <= builder_csr_bankarray_csrbank4_clk_divider0_re;\n\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= 1'd0;\n\tif (builder_csr_bankarray_csrbank5_sel) begin\n\t\tcase (builder_csr_bankarray_interface5_bank_bus_adr[4:0])\n\t\t\t1'd0: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_load3_w;\n\t\t\tend\n\t\t\t1'd1: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_load2_w;\n\t\t\tend\n\t\t\t2'd2: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_load1_w;\n\t\t\tend\n\t\t\t2'd3: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_load0_w;\n\t\t\tend\n\t\t\t3'd4: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_reload3_w;\n\t\t\tend\n\t\t\t3'd5: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_reload2_w;\n\t\t\tend\n\t\t\t3'd6: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_reload1_w;\n\t\t\tend\n\t\t\t3'd7: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_reload0_w;\n\t\t\tend\n\t\t\t4'd8: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_en0_w;\n\t\t\tend\n\t\t\t4'd9: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_update_value0_w;\n\t\t\tend\n\t\t\t4'd10: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_value3_w;\n\t\t\tend\n\t\t\t4'd11: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_value2_w;\n\t\t\tend\n\t\t\t4'd12: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_value1_w;\n\t\t\tend\n\t\t\t4'd13: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_value0_w;\n\t\t\tend\n\t\t\t4'd14: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= main_soclinux_timer_eventmanager_status_w;\n\t\t\tend\n\t\t\t4'd15: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= main_soclinux_timer_eventmanager_pending_w;\n\t\t\tend\n\t\t\t5'd16: begin\n\t\t\t\tbuilder_csr_bankarray_interface5_bank_bus_dat_r <= builder_csr_bankarray_csrbank5_ev_enable0_w;\n\t\t\tend\n\t\tendcase\n\tend\n\tif (builder_csr_bankarray_csrbank5_load3_re) begin\n\t\tmain_soclinux_timer_load_storage[31:24] <= builder_csr_bankarray_csrbank5_load3_r;\n\tend\n\tif (builder_csr_bankarray_csrbank5_load2_re) begin\n\t\tmain_soclinux_timer_load_storage[23:16] <= builder_csr_bankarray_csrbank5_load2_r;\n\tend\n\tif (builder_csr_bankarray_csrbank5_load1_re) begin\n\t\tmain_soclinux_timer_load_storage[15:8] <= builder_csr_bankarray_csrbank5_load1_r;\n\tend\n\tif (builder_csr_bankarray_csrbank5_load0_re) begin\n\t\tmain_soclinux_timer_load_storage[7:0] <= builder_csr_bankarray_csrbank5_load0_r;\n\tend\n\tmain_soclinux_timer_load_re <= builder_csr_bankarray_csrbank5_load0_re;\n\tif (builder_csr_bankarray_csrbank5_reload3_re) begin\n\t\tmain_soclinux_timer_reload_storage[31:24] <= builder_csr_bankarray_csrbank5_reload3_r;\n\tend\n\tif (builder_csr_bankarray_csrbank5_reload2_re) begin\n\t\tmain_soclinux_timer_reload_storage[23:16] <= builder_csr_bankarray_csrbank5_reload2_r;\n\tend\n\tif (builder_csr_bankarray_csrbank5_reload1_re) begin\n\t\tmain_soclinux_timer_reload_storage[15:8] <= builder_csr_bankarray_csrbank5_reload1_r;\n\tend\n\tif (builder_csr_bankarray_csrbank5_reload0_re) begin\n\t\tmain_soclinux_timer_reload_storage[7:0] <= builder_csr_bankarray_csrbank5_reload0_r;\n\tend\n\tmain_soclinux_timer_reload_re <= builder_csr_bankarray_csrbank5_reload0_re;\n\tif (builder_csr_bankarray_csrbank5_en0_re) begin\n\t\tmain_soclinux_timer_en_storage <= builder_csr_bankarray_csrbank5_en0_r;\n\tend\n\tmain_soclinux_timer_en_re <= builder_csr_bankarray_csrbank5_en0_re;\n\tif (builder_csr_bankarray_csrbank5_update_value0_re) begin\n\t\tmain_soclinux_timer_update_value_storage <= builder_csr_bankarray_csrbank5_update_value0_r;\n\tend\n\tmain_soclinux_timer_update_value_re <= builder_csr_bankarray_csrbank5_update_value0_re;\n\tif (builder_csr_bankarray_csrbank5_ev_enable0_re) begin\n\t\tmain_soclinux_timer_eventmanager_storage <= builder_csr_bankarray_csrbank5_ev_enable0_r;\n\tend\n\tmain_soclinux_timer_eventmanager_re <= builder_csr_bankarray_csrbank5_ev_enable0_re;\n\tbuilder_csr_bankarray_interface6_bank_bus_dat_r <= 1'd0;\n\tif (builder_csr_bankarray_csrbank6_sel) begin\n\t\tcase (builder_csr_bankarray_interface6_bank_bus_adr[2:0])\n\t\t\t1'd0: begin\n\t\t\t\tbuilder_csr_bankarray_interface6_bank_bus_dat_r <= main_soclinux_uart_rxtx_w;\n\t\t\tend\n\t\t\t1'd1: begin\n\t\t\t\tbuilder_csr_bankarray_interface6_bank_bus_dat_r <= builder_csr_bankarray_csrbank6_txfull_w;\n\t\t\tend\n\t\t\t2'd2: begin\n\t\t\t\tbuilder_csr_bankarray_interface6_bank_bus_dat_r <= builder_csr_bankarray_csrbank6_rxempty_w;\n\t\t\tend\n\t\t\t2'd3: begin\n\t\t\t\tbuilder_csr_bankarray_interface6_bank_bus_dat_r <= main_soclinux_uart_eventmanager_status_w;\n\t\t\tend\n\t\t\t3'd4: begin\n\t\t\t\tbuilder_csr_bankarray_interface6_bank_bus_dat_r <= main_soclinux_uart_eventmanager_pending_w;\n\t\t\tend\n\t\t\t3'd5: begin\n\t\t\t\tbuilder_csr_bankarray_interface6_bank_bus_dat_r <= builder_csr_bankarray_csrbank6_ev_enable0_w;\n\t\t\tend\n\t\t\t3'd6: begin\n\t\t\t\tbuilder_csr_bankarray_interface6_bank_bus_dat_r <= builder_csr_bankarray_csrbank6_txempty_w;\n\t\t\tend\n\t\t\t3'd7: begin\n\t\t\t\tbuilder_csr_bankarray_interface6_bank_bus_dat_r <= builder_csr_bankarray_csrbank6_rxfull_w;\n\t\t\tend\n\t\tendcase\n\tend\n\tif (builder_csr_bankarray_csrbank6_ev_enable0_re) begin\n\t\tmain_soclinux_uart_eventmanager_storage[1:0] <= builder_csr_bankarray_csrbank6_ev_enable0_r;\n\tend\n\tmain_soclinux_uart_eventmanager_re <= builder_csr_bankarray_csrbank6_ev_enable0_re;\n\tbuilder_csr_bankarray_interface7_bank_bus_dat_r <= 1'd0;\n\tif (builder_csr_bankarray_csrbank7_sel) begin\n\t\tcase (builder_csr_bankarray_interface7_bank_bus_adr[1:0])\n\t\t\t1'd0: begin\n\t\t\t\tbuilder_csr_bankarray_interface7_bank_bus_dat_r <= builder_csr_bankarray_csrbank7_tuning_word3_w;\n\t\t\tend\n\t\t\t1'd1: begin\n\t\t\t\tbuilder_csr_bankarray_interface7_bank_bus_dat_r <= builder_csr_bankarray_csrbank7_tuning_word2_w;\n\t\t\tend\n\t\t\t2'd2: begin\n\t\t\t\tbuilder_csr_bankarray_interface7_bank_bus_dat_r <= builder_csr_bankarray_csrbank7_tuning_word1_w;\n\t\t\tend\n\t\t\t2'd3: begin\n\t\t\t\tbuilder_csr_bankarray_interface7_bank_bus_dat_r <= builder_csr_bankarray_csrbank7_tuning_word0_w;\n\t\t\tend\n\t\tendcase\n\tend\n\tif (builder_csr_bankarray_csrbank7_tuning_word3_re) begin\n\t\tmain_soclinux_storage[31:24] <= builder_csr_bankarray_csrbank7_tuning_word3_r;\n\tend\n\tif (builder_csr_bankarray_csrbank7_tuning_word2_re) begin\n\t\tmain_soclinux_storage[23:16] <= builder_csr_bankarray_csrbank7_tuning_word2_r;\n\tend\n\tif (builder_csr_bankarray_csrbank7_tuning_word1_re) begin\n\t\tmain_soclinux_storage[15:8] <= builder_csr_bankarray_csrbank7_tuning_word1_r;\n\tend\n\tif (builder_csr_bankarray_csrbank7_tuning_word0_re) begin\n\t\tmain_soclinux_storage[7:0] <= builder_csr_bankarray_csrbank7_tuning_word0_r;\n\tend\n\tmain_soclinux_re <= builder_csr_bankarray_csrbank7_tuning_word0_re;\n\tif (sys_rst) begin\n\t\tmain_soclinux_soccontroller_reset_storage <= 1'd0;\n\t\tmain_soclinux_soccontroller_reset_re <= 1'd0;\n\t\tmain_soclinux_soccontroller_scratch_storage <= 32'd305419896;\n\t\tmain_soclinux_soccontroller_scratch_re <= 1'd0;\n\t\tmain_soclinux_soccontroller_bus_errors <= 32'd0;\n\t\tmain_soclinux_cpu_time_status <= 64'd0;\n\t\tmain_soclinux_cpu_time_cmp_storage <= 64'd18446744073709551615;\n\t\tmain_soclinux_cpu_time_cmp_re <= 1'd0;\n\t\tmain_soclinux_cpu_time <= 64'd0;\n\t\tmain_soclinux_cpu_time_cmp <= 64'd18446744073709551615;\n\t\tmain_soclinux_soclinux_ram_bus_ack <= 1'd0;\n\t\tmain_soclinux_ram_bus_ram_bus_ack <= 1'd0;\n\t\tserial_tx <= 1'd1;\n\t\tmain_soclinux_storage <= 32'd85899345;\n\t\tmain_soclinux_re <= 1'd0;\n\t\tmain_soclinux_sink_ready <= 1'd0;\n\t\tmain_soclinux_tx_clken <= 1'd0;\n\t\tmain_soclinux_tx_busy <= 1'd0;\n\t\tmain_soclinux_source_valid <= 1'd0;\n\t\tmain_soclinux_source_payload_data <= 8'd0;\n\t\tmain_soclinux_rx_clken <= 1'd0;\n\t\tmain_soclinux_rx_r <= 1'd0;\n\t\tmain_soclinux_rx_busy <= 1'd0;\n\t\tmain_soclinux_uart_tx_pending <= 1'd0;\n\t\tmain_soclinux_uart_tx_old_trigger <= 1'd0;\n\t\tmain_soclinux_uart_rx_pending <= 1'd0;\n\t\tmain_soclinux_uart_rx_old_trigger <= 1'd0;\n\t\tmain_soclinux_uart_eventmanager_storage <= 2'd0;\n\t\tmain_soclinux_uart_eventmanager_re <= 1'd0;\n\t\tmain_soclinux_uart_tx_fifo_readable <= 1'd0;\n\t\tmain_soclinux_uart_tx_fifo_level0 <= 5'd0;\n\t\tmain_soclinux_uart_tx_fifo_produce <= 4'd0;\n\t\tmain_soclinux_uart_tx_fifo_consume <= 4'd0;\n\t\tmain_soclinux_uart_rx_fifo_readable <= 1'd0;\n\t\tmain_soclinux_uart_rx_fifo_level0 <= 5'd0;\n\t\tmain_soclinux_uart_rx_fifo_produce <= 4'd0;\n\t\tmain_soclinux_uart_rx_fifo_consume <= 4'd0;\n\t\tmain_soclinux_timer_load_storage <= 32'd0;\n\t\tmain_soclinux_timer_load_re <= 1'd0;\n\t\tmain_soclinux_timer_reload_storage <= 32'd0;\n\t\tmain_soclinux_timer_reload_re <= 1'd0;\n\t\tmain_soclinux_timer_en_storage <= 1'd0;\n\t\tmain_soclinux_timer_en_re <= 1'd0;\n\t\tmain_soclinux_timer_update_value_storage <= 1'd0;\n\t\tmain_soclinux_timer_update_value_re <= 1'd0;\n\t\tmain_soclinux_timer_value_status <= 32'd0;\n\t\tmain_soclinux_timer_zero_pending <= 1'd0;\n\t\tmain_soclinux_timer_zero_old_trigger <= 1'd0;\n\t\tmain_soclinux_timer_eventmanager_storage <= 1'd0;\n\t\tmain_soclinux_timer_eventmanager_re <= 1'd0;\n\t\tmain_soclinux_timer_value <= 32'd0;\n\t\tmain_dfi_p0_rddata_valid <= 1'd0;\n\t\tmain_rddata_en <= 3'd0;\n\t\tmain_sdram_storage <= 4'd1;\n\t\tmain_sdram_re <= 1'd0;\n\t\tmain_sdram_command_storage <= 6'd0;\n\t\tmain_sdram_command_re <= 1'd0;\n\t\tmain_sdram_address_re <= 1'd0;\n\t\tmain_sdram_baddress_re <= 1'd0;\n\t\tmain_sdram_wrdata_re <= 1'd0;\n\t\tmain_sdram_rddata_status <= 16'd0;\n\t\tmain_sdram_dfi_p0_address <= 13'd0;\n\t\tmain_sdram_dfi_p0_bank <= 2'd0;\n\t\tmain_sdram_dfi_p0_cas_n <= 1'd1;\n\t\tmain_sdram_dfi_p0_cs_n <= 1'd1;\n\t\tmain_sdram_dfi_p0_ras_n <= 1'd1;\n\t\tmain_sdram_dfi_p0_we_n <= 1'd1;\n\t\tmain_sdram_dfi_p0_wrdata_en <= 1'd0;\n\t\tmain_sdram_dfi_p0_rddata_en <= 1'd0;\n\t\tmain_sdram_cmd_payload_a <= 13'd0;\n\t\tmain_sdram_cmd_payload_ba <= 2'd0;\n\t\tmain_sdram_cmd_payload_cas <= 1'd0;\n\t\tmain_sdram_cmd_payload_ras <= 1'd0;\n\t\tmain_sdram_cmd_payload_we <= 1'd0;\n\t\tmain_sdram_timer_count1 <= 9'd390;\n\t\tmain_sdram_postponer_req_o <= 1'd0;\n\t\tmain_sdram_postponer_count <= 1'd0;\n\t\tmain_sdram_sequencer_done1 <= 1'd0;\n\t\tmain_sdram_sequencer_counter <= 3'd0;\n\t\tmain_sdram_sequencer_count <= 1'd0;\n\t\tmain_sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0;\n\t\tmain_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0;\n\t\tmain_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0;\n\t\tmain_sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0;\n\t\tmain_sdram_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;\n\t\tmain_sdram_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0;\n\t\tmain_sdram_bankmachine0_row <= 13'd0;\n\t\tmain_sdram_bankmachine0_row_opened <= 1'd0;\n\t\tmain_sdram_bankmachine0_twtpcon_ready <= 1'd0;\n\t\tmain_sdram_bankmachine0_twtpcon_count <= 2'd0;\n\t\tmain_sdram_bankmachine0_trccon_ready <= 1'd0;\n\t\tmain_sdram_bankmachine0_trccon_count <= 2'd0;\n\t\tmain_sdram_bankmachine0_trascon_ready <= 1'd0;\n\t\tmain_sdram_bankmachine0_trascon_count <= 2'd0;\n\t\tmain_sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0;\n\t\tmain_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0;\n\t\tmain_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0;\n\t\tmain_sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0;\n\t\tmain_sdram_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;\n\t\tmain_sdram_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0;\n\t\tmain_sdram_bankmachine1_row <= 13'd0;\n\t\tmain_sdram_bankmachine1_row_opened <= 1'd0;\n\t\tmain_sdram_bankmachine1_twtpcon_ready <= 1'd0;\n\t\tmain_sdram_bankmachine1_twtpcon_count <= 2'd0;\n\t\tmain_sdram_bankmachine1_trccon_ready <= 1'd0;\n\t\tmain_sdram_bankmachine1_trccon_count <= 2'd0;\n\t\tmain_sdram_bankmachine1_trascon_ready <= 1'd0;\n\t\tmain_sdram_bankmachine1_trascon_count <= 2'd0;\n\t\tmain_sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0;\n\t\tmain_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0;\n\t\tmain_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0;\n\t\tmain_sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0;\n\t\tmain_sdram_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;\n\t\tmain_sdram_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0;\n\t\tmain_sdram_bankmachine2_row <= 13'd0;\n\t\tmain_sdram_bankmachine2_row_opened <= 1'd0;\n\t\tmain_sdram_bankmachine2_twtpcon_ready <= 1'd0;\n\t\tmain_sdram_bankmachine2_twtpcon_count <= 2'd0;\n\t\tmain_sdram_bankmachine2_trccon_ready <= 1'd0;\n\t\tmain_sdram_bankmachine2_trccon_count <= 2'd0;\n\t\tmain_sdram_bankmachine2_trascon_ready <= 1'd0;\n\t\tmain_sdram_bankmachine2_trascon_count <= 2'd0;\n\t\tmain_sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0;\n\t\tmain_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0;\n\t\tmain_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0;\n\t\tmain_sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0;\n\t\tmain_sdram_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;\n\t\tmain_sdram_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0;\n\t\tmain_sdram_bankmachine3_row <= 13'd0;\n\t\tmain_sdram_bankmachine3_row_opened <= 1'd0;\n\t\tmain_sdram_bankmachine3_twtpcon_ready <= 1'd0;\n\t\tmain_sdram_bankmachine3_twtpcon_count <= 2'd0;\n\t\tmain_sdram_bankmachine3_trccon_ready <= 1'd0;\n\t\tmain_sdram_bankmachine3_trccon_count <= 2'd0;\n\t\tmain_sdram_bankmachine3_trascon_ready <= 1'd0;\n\t\tmain_sdram_bankmachine3_trascon_count <= 2'd0;\n\t\tmain_sdram_choose_cmd_grant <= 2'd0;\n\t\tmain_sdram_choose_req_grant <= 2'd0;\n\t\tmain_sdram_trrdcon_ready <= 1'd0;\n\t\tmain_sdram_trrdcon_count <= 1'd0;\n\t\tmain_sdram_tccdcon_ready <= 1'd0;\n\t\tmain_sdram_tccdcon_count <= 1'd0;\n\t\tmain_sdram_twtrcon_ready <= 1'd0;\n\t\tmain_sdram_twtrcon_count <= 3'd0;\n\t\tmain_sdram_time0 <= 5'd0;\n\t\tmain_sdram_time1 <= 4'd0;\n\t\tmain_wishbone_bridge_count <= 3'd0;\n\t\tmain_wishbone_bridge_wdata_converter_converter_mux <= 3'd0;\n\t\tmain_wishbone_bridge_rdata_converter_converter_source_payload_data <= 128'd0;\n\t\tmain_wishbone_bridge_rdata_converter_converter_source_payload_valid_token_count <= 4'd0;\n\t\tmain_wishbone_bridge_rdata_converter_converter_demux <= 3'd0;\n\t\tmain_wishbone_bridge_rdata_converter_converter_strobe_all <= 1'd0;\n\t\tmain_wishbone_bridge_cmd_consumed <= 1'd0;\n\t\tmain_wishbone_bridge_wdata_consumed <= 1'd0;\n\t\tmain_storage <= 8'd0;\n\t\tmain_re <= 1'd0;\n\t\tmain_chaser <= 8'd0;\n\t\tmain_mode <= 1'd0;\n\t\tmain_count <= 22'd3125000;\n\t\tspisdcard_clk <= 1'd0;\n\t\tspisdcard_mosi <= 1'd0;\n\t\tspisdcard_cs_n <= 1'd0;\n\t\tsoclinux_miso <= 8'd0;\n\t\tsoclinux_control_storage <= 16'd0;\n\t\tsoclinux_control_re <= 1'd0;\n\t\tsoclinux_mosi_re <= 1'd0;\n\t\tsoclinux_cs_storage <= 1'd1;\n\t\tsoclinux_cs_re <= 1'd0;\n\t\tsoclinux_loopback_storage <= 1'd0;\n\t\tsoclinux_loopback_re <= 1'd0;\n\t\tsoclinux_count <= 3'd0;\n\t\tsoclinux_clk_divider1 <= 16'd0;\n\t\tsoclinux_mosi_data <= 8'd0;\n\t\tsoclinux_mosi_sel <= 3'd0;\n\t\tsoclinux_miso_data <= 8'd0;\n\t\tsoclinux_storage <= 16'd125;\n\t\tsoclinux_re <= 1'd0;\n\t\tbuilder_refresher_state <= 2'd0;\n\t\tbuilder_bankmachine0_state <= 3'd0;\n\t\tbuilder_bankmachine1_state <= 3'd0;\n\t\tbuilder_bankmachine2_state <= 3'd0;\n\t\tbuilder_bankmachine3_state <= 3'd0;\n\t\tbuilder_multiplexer_state <= 3'd0;\n\t\tbuilder_new_master_wdata_ready <= 1'd0;\n\t\tbuilder_new_master_rdata_valid0 <= 1'd0;\n\t\tbuilder_new_master_rdata_valid1 <= 1'd0;\n\t\tbuilder_new_master_rdata_valid2 <= 1'd0;\n\t\tbuilder_new_master_rdata_valid3 <= 1'd0;\n\t\tbuilder_fullmemorywe_state <= 2'd0;\n\t\tbuilder_litedramwishbone2native_state <= 1'd0;\n\t\tbuilder_spimaster_state <= 2'd0;\n\t\tbuilder_soclinux_we <= 1'd0;\n\t\tbuilder_grant <= 1'd0;\n\t\tbuilder_slave_sel_r <= 4'd0;\n\t\tbuilder_count <= 20'd1000000;\n\t\tbuilder_csr_bankarray_sel_r <= 1'd0;\n\t\tbuilder_state <= 2'd0;\n\tend\n\tbuilder_regs0 <= serial_rx;\n\tbuilder_regs1 <= builder_regs0;\nend\n\n//reg [31:0] mem[0:16383];\nreg [31:0] mem[0:10239];\nreg [31:0] memdat;\nalways @(posedge sys_clk) begin\n\tmemdat <= mem[main_soclinux_soclinux_adr];\nend\n\nassign main_soclinux_soclinux_dat_r = memdat;\n\ninitial begin\n\t$readmemh(\"mem.init\", mem);\nend\n\nreg [31:0] mem_1[0:2047];\nreg [10:0] memadr;\nalways @(posedge sys_clk) begin\n\tif (main_soclinux_ram_we[0])\n\t\tmem_1[main_soclinux_ram_adr][7:0] <= main_soclinux_ram_dat_w[7:0];\n\tif (main_soclinux_ram_we[1])\n\t\tmem_1[main_soclinux_ram_adr][15:8] <= main_soclinux_ram_dat_w[15:8];\n\tif (main_soclinux_ram_we[2])\n\t\tmem_1[main_soclinux_ram_adr][23:16] <= main_soclinux_ram_dat_w[23:16];\n\tif (main_soclinux_ram_we[3])\n\t\tmem_1[main_soclinux_ram_adr][31:24] <= main_soclinux_ram_dat_w[31:24];\n\tmemadr <= main_soclinux_ram_adr;\nend\n\nassign main_soclinux_ram_dat_r = mem_1[memadr];\n\ninitial begin\n\t$readmemh(\"mem_1.init\", mem_1);\nend\n\nreg [7:0] mem_2[0:38];\nreg [5:0] memadr_1;\nalways @(posedge sys_clk) begin\n\tmemadr_1 <= builder_csr_bankarray_adr;\nend\n\nassign builder_csr_bankarray_dat_r = mem_2[memadr_1];\n\ninitial begin\n\t$readmemh(\"mem_2.init\", mem_2);\nend\n\nreg [9:0] storage[0:15];\nreg [9:0] memdat_1;\nreg [9:0] memdat_2;\nalways @(posedge sys_clk) begin\n\tif (main_soclinux_uart_tx_fifo_wrport_we)\n\t\tstorage[main_soclinux_uart_tx_fifo_wrport_adr] <= main_soclinux_uart_tx_fifo_wrport_dat_w;\n\tmemdat_1 <= storage[main_soclinux_uart_tx_fifo_wrport_adr];\nend\n\nalways @(posedge sys_clk) begin\n\tif (main_soclinux_uart_tx_fifo_rdport_re)\n\t\tmemdat_2 <= storage[main_soclinux_uart_tx_fifo_rdport_adr];\nend\n\nassign main_soclinux_uart_tx_fifo_wrport_dat_r = memdat_1;\nassign main_soclinux_uart_tx_fifo_rdport_dat_r = memdat_2;\n\nreg [9:0] storage_1[0:15];\nreg [9:0] memdat_3;\nreg [9:0] memdat_4;\nalways @(posedge sys_clk) begin\n\tif (main_soclinux_uart_rx_fifo_wrport_we)\n\t\tstorage_1[main_soclinux_uart_rx_fifo_wrport_adr] <= main_soclinux_uart_rx_fifo_wrport_dat_w;\n\tmemdat_3 <= storage_1[main_soclinux_uart_rx_fifo_wrport_adr];\nend\n\nalways @(posedge sys_clk) begin\n\tif (main_soclinux_uart_rx_fifo_rdport_re)\n\t\tmemdat_4 <= storage_1[main_soclinux_uart_rx_fifo_rdport_adr];\nend\n\nassign main_soclinux_uart_rx_fifo_wrport_dat_r = memdat_3;\nassign main_soclinux_uart_rx_fifo_rdport_dat_r = memdat_4;\n\nreg [24:0] storage_2[0:7];\nreg [24:0] memdat_5;\nalways @(posedge sys_clk) begin\n\tif (main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)\n\t\tstorage_2[main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;\n\tmemdat_5 <= storage_2[main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];\nend\n\nalways @(posedge sys_clk) begin\nend\n\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5;\nassign main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];\n\nreg [24:0] storage_3[0:7];\nreg [24:0] memdat_6;\nalways @(posedge sys_clk) begin\n\tif (main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)\n\t\tstorage_3[main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;\n\tmemdat_6 <= storage_3[main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];\nend\n\nalways @(posedge sys_clk) begin\nend\n\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6;\nassign main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];\n\nreg [24:0] storage_4[0:7];\nreg [24:0] memdat_7;\nalways @(posedge sys_clk) begin\n\tif (main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)\n\t\tstorage_4[main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;\n\tmemdat_7 <= storage_4[main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];\nend\n\nalways @(posedge sys_clk) begin\nend\n\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7;\nassign main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];\n\nreg [24:0] storage_5[0:7];\nreg [24:0] memdat_8;\nalways @(posedge sys_clk) begin\n\tif (main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)\n\t\tstorage_5[main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;\n\tmemdat_8 <= storage_5[main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];\nend\n\nalways @(posedge sys_clk) begin\nend\n\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8;\nassign main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];\n\nreg [23:0] tag_mem[0:511];\nreg [8:0] memadr_2;\nalways @(posedge sys_clk) begin\n\tif (main_tag_port_we)\n\t\ttag_mem[main_tag_port_adr] <= main_tag_port_dat_w;\n\tmemadr_2 <= main_tag_port_adr;\nend\n\nassign main_tag_port_dat_r = tag_mem[memadr_2];\n\nVexRiscv VexRiscv(\n\t.clk(sys_clk),\n\t.dBusWishbone_ACK(main_soclinux_cpu_dbus_ack),\n\t.dBusWishbone_DAT_MISO(main_soclinux_cpu_dbus_dat_r),\n\t.dBusWishbone_ERR(main_soclinux_cpu_dbus_err),\n\t.externalInterruptArray(main_soclinux_cpu_interrupt0),\n\t.externalResetVector(main_soclinux_vexriscv),\n\t.iBusWishbone_ACK(main_soclinux_cpu_ibus_ack),\n\t.iBusWishbone_DAT_MISO(main_soclinux_cpu_ibus_dat_r),\n\t.iBusWishbone_ERR(main_soclinux_cpu_ibus_err),\n\t.reset((sys_rst | main_soclinux_cpu_reset)),\n\t.softwareInterrupt(1'd0),\n\t.timerInterrupt(main_soclinux_cpu_interrupt1),\n\t.dBusWishbone_ADR(main_soclinux_cpu_dbus_adr),\n\t.dBusWishbone_BTE(main_soclinux_cpu_dbus_bte),\n\t.dBusWishbone_CTI(main_soclinux_cpu_dbus_cti),\n\t.dBusWishbone_CYC(main_soclinux_cpu_dbus_cyc),\n\t.dBusWishbone_DAT_MOSI(main_soclinux_cpu_dbus_dat_w),\n\t.dBusWishbone_SEL(main_soclinux_cpu_dbus_sel),\n\t.dBusWishbone_STB(main_soclinux_cpu_dbus_stb),\n\t.dBusWishbone_WE(main_soclinux_cpu_dbus_we),\n\t.iBusWishbone_ADR(main_soclinux_cpu_ibus_adr),\n\t.iBusWishbone_BTE(main_soclinux_cpu_ibus_bte),\n\t.iBusWishbone_CTI(main_soclinux_cpu_ibus_cti),\n\t.iBusWishbone_CYC(main_soclinux_cpu_ibus_cyc),\n\t.iBusWishbone_DAT_MOSI(main_soclinux_cpu_ibus_dat_w),\n\t.iBusWishbone_SEL(main_soclinux_cpu_ibus_sel),\n\t.iBusWishbone_STB(main_soclinux_cpu_ibus_stb),\n\t.iBusWishbone_WE(main_soclinux_cpu_ibus_we)\n);\n\n(* FREQUENCY_PIN_CLKI = \"25.0\", ICP_CURRENT = \"6\", LPF_RESISTOR = \"16\", MFG_ENABLE_FILTEROPAMP = \"1\", MFG_GMCREF_SEL = \"2\" *) EHXPLLL #(\n\t.CLKFB_DIV(5'd16),\n\t.CLKI_DIV(1'd1),\n\t.CLKOP_CPHASE(3'd7),\n\t.CLKOP_DIV(4'd8),\n\t.CLKOP_ENABLE(\"ENABLED\"),\n\t.CLKOP_FPHASE(1'd0),\n\t.CLKOS3_CPHASE(5'd23),\n\t.CLKOS3_DIV(1'd1),\n\t.CLKOS3_ENABLE(\"ENABLED\"),\n\t.CLKOS3_FPHASE(1'd0),\n\t.CLKOS_CPHASE(4'd9),\n\t.CLKOS_DIV(4'd8),\n\t.CLKOS_ENABLE(\"ENABLED\"),\n\t.CLKOS_FPHASE(1'd0),\n\t.FEEDBK_PATH(\"INT_OS3\")\n) EHXPLLL (\n\t.CLKI(main_clkin),\n\t.RST(main_reset),\n\t.CLKOP(main_clkout0),\n\t.CLKOS(main_clkout1),\n\t.LOCK(main_locked)\n);\n\nreg [7:0] data_mem_grain0[0:511];\nreg [8:0] memadr_3;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[0])\n\t\tdata_mem_grain0[main_data_port_adr] <= main_data_port_dat_w[7:0];\n\tmemadr_3 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[7:0] = data_mem_grain0[memadr_3];\n\nreg [7:0] data_mem_grain1[0:511];\nreg [8:0] memadr_4;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[1])\n\t\tdata_mem_grain1[main_data_port_adr] <= main_data_port_dat_w[15:8];\n\tmemadr_4 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[15:8] = data_mem_grain1[memadr_4];\n\nreg [7:0] data_mem_grain2[0:511];\nreg [8:0] memadr_5;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[2])\n\t\tdata_mem_grain2[main_data_port_adr] <= main_data_port_dat_w[23:16];\n\tmemadr_5 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[23:16] = data_mem_grain2[memadr_5];\n\nreg [7:0] data_mem_grain3[0:511];\nreg [8:0] memadr_6;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[3])\n\t\tdata_mem_grain3[main_data_port_adr] <= main_data_port_dat_w[31:24];\n\tmemadr_6 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[31:24] = data_mem_grain3[memadr_6];\n\nreg [7:0] data_mem_grain4[0:511];\nreg [8:0] memadr_7;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[4])\n\t\tdata_mem_grain4[main_data_port_adr] <= main_data_port_dat_w[39:32];\n\tmemadr_7 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[39:32] = data_mem_grain4[memadr_7];\n\nreg [7:0] data_mem_grain5[0:511];\nreg [8:0] memadr_8;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[5])\n\t\tdata_mem_grain5[main_data_port_adr] <= main_data_port_dat_w[47:40];\n\tmemadr_8 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[47:40] = data_mem_grain5[memadr_8];\n\nreg [7:0] data_mem_grain6[0:511];\nreg [8:0] memadr_9;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[6])\n\t\tdata_mem_grain6[main_data_port_adr] <= main_data_port_dat_w[55:48];\n\tmemadr_9 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[55:48] = data_mem_grain6[memadr_9];\n\nreg [7:0] data_mem_grain7[0:511];\nreg [8:0] memadr_10;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[7])\n\t\tdata_mem_grain7[main_data_port_adr] <= main_data_port_dat_w[63:56];\n\tmemadr_10 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[63:56] = data_mem_grain7[memadr_10];\n\nreg [7:0] data_mem_grain8[0:511];\nreg [8:0] memadr_11;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[8])\n\t\tdata_mem_grain8[main_data_port_adr] <= main_data_port_dat_w[71:64];\n\tmemadr_11 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[71:64] = data_mem_grain8[memadr_11];\n\nreg [7:0] data_mem_grain9[0:511];\nreg [8:0] memadr_12;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[9])\n\t\tdata_mem_grain9[main_data_port_adr] <= main_data_port_dat_w[79:72];\n\tmemadr_12 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[79:72] = data_mem_grain9[memadr_12];\n\nreg [7:0] data_mem_grain10[0:511];\nreg [8:0] memadr_13;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[10])\n\t\tdata_mem_grain10[main_data_port_adr] <= main_data_port_dat_w[87:80];\n\tmemadr_13 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[87:80] = data_mem_grain10[memadr_13];\n\nreg [7:0] data_mem_grain11[0:511];\nreg [8:0] memadr_14;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[11])\n\t\tdata_mem_grain11[main_data_port_adr] <= main_data_port_dat_w[95:88];\n\tmemadr_14 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[95:88] = data_mem_grain11[memadr_14];\n\nreg [7:0] data_mem_grain12[0:511];\nreg [8:0] memadr_15;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[12])\n\t\tdata_mem_grain12[main_data_port_adr] <= main_data_port_dat_w[103:96];\n\tmemadr_15 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[103:96] = data_mem_grain12[memadr_15];\n\nreg [7:0] data_mem_grain13[0:511];\nreg [8:0] memadr_16;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[13])\n\t\tdata_mem_grain13[main_data_port_adr] <= main_data_port_dat_w[111:104];\n\tmemadr_16 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[111:104] = data_mem_grain13[memadr_16];\n\nreg [7:0] data_mem_grain14[0:511];\nreg [8:0] memadr_17;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[14])\n\t\tdata_mem_grain14[main_data_port_adr] <= main_data_port_dat_w[119:112];\n\tmemadr_17 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[119:112] = data_mem_grain14[memadr_17];\n\nreg [7:0] data_mem_grain15[0:511];\nreg [8:0] memadr_18;\nalways @(posedge sys_clk) begin\n\tif (main_data_port_we[15])\n\t\tdata_mem_grain15[main_data_port_adr] <= main_data_port_dat_w[127:120];\n\tmemadr_18 <= main_data_port_adr;\nend\n\nassign main_data_port_dat_r[127:120] = data_mem_grain15[memadr_18];\n\nFD1S3BX FD1S3BX(\n\t.CK(sys_clk),\n\t.D(1'd0),\n\t.PD((~main_locked)),\n\t.Q(builder_latticeecp5asyncresetsynchronizerimpl0_rst1)\n);\n\nFD1S3BX FD1S3BX_1(\n\t.CK(sys_clk),\n\t.D(builder_latticeecp5asyncresetsynchronizerimpl0_rst1),\n\t.PD((~main_locked)),\n\t.Q(sys_rst)\n);\n\nFD1S3BX FD1S3BX_2(\n\t.CK(sys_ps_clk),\n\t.D(1'd0),\n\t.PD((~main_locked)),\n\t.Q(builder_latticeecp5asyncresetsynchronizerimpl1_rst1)\n);\n\nFD1S3BX FD1S3BX_3(\n\t.CK(sys_ps_clk),\n\t.D(builder_latticeecp5asyncresetsynchronizerimpl1_rst1),\n\t.PD((~main_locked)),\n\t.Q(builder_latticeecp5asyncresetsynchronizerimpl1_expr)\n);\n\nODDRX1F ODDRX1F(\n\t.D0(1'd1),\n\t.D1(1'd0),\n\t.SCLK(sys_ps_clk),\n\t.Q(sdram_clock)\n);\n\nOFS1P3BX OFS1P3BX(\n\t.D(main_dfi_p0_address[0]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[0])\n);\n\nOFS1P3BX OFS1P3BX_1(\n\t.D(main_dfi_p0_address[1]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[1])\n);\n\nOFS1P3BX OFS1P3BX_2(\n\t.D(main_dfi_p0_address[2]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[2])\n);\n\nOFS1P3BX OFS1P3BX_3(\n\t.D(main_dfi_p0_address[3]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[3])\n);\n\nOFS1P3BX OFS1P3BX_4(\n\t.D(main_dfi_p0_address[4]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[4])\n);\n\nOFS1P3BX OFS1P3BX_5(\n\t.D(main_dfi_p0_address[5]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[5])\n);\n\nOFS1P3BX OFS1P3BX_6(\n\t.D(main_dfi_p0_address[6]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[6])\n);\n\nOFS1P3BX OFS1P3BX_7(\n\t.D(main_dfi_p0_address[7]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[7])\n);\n\nOFS1P3BX OFS1P3BX_8(\n\t.D(main_dfi_p0_address[8]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[8])\n);\n\nOFS1P3BX OFS1P3BX_9(\n\t.D(main_dfi_p0_address[9]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[9])\n);\n\nOFS1P3BX OFS1P3BX_10(\n\t.D(main_dfi_p0_address[10]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[10])\n);\n\nOFS1P3BX OFS1P3BX_11(\n\t.D(main_dfi_p0_address[11]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[11])\n);\n\nOFS1P3BX OFS1P3BX_12(\n\t.D(main_dfi_p0_address[12]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_a[12])\n);\n\nOFS1P3BX OFS1P3BX_13(\n\t.D(main_dfi_p0_bank[0]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_ba[0])\n);\n\nOFS1P3BX OFS1P3BX_14(\n\t.D(main_dfi_p0_bank[1]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_ba[1])\n);\n\nOFS1P3BX OFS1P3BX_15(\n\t.D(main_dfi_p0_ras_n),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_ras_n)\n);\n\nOFS1P3BX OFS1P3BX_16(\n\t.D(main_dfi_p0_cas_n),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_cas_n)\n);\n\nOFS1P3BX OFS1P3BX_17(\n\t.D(main_dfi_p0_we_n),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_we_n)\n);\n\nOFS1P3BX OFS1P3BX_18(\n\t.D(main_dfi_p0_cke),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_cke)\n);\n\nOFS1P3BX OFS1P3BX_19(\n\t.D(main_dfi_p0_cs_n),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_cs_n)\n);\n\nOFS1P3BX OFS1P3BX_20(\n\t.D((main_dfi_p0_wrdata_en & main_dfi_p0_wrdata_mask[0])),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_dm[0])\n);\n\nOFS1P3BX OFS1P3BX_21(\n\t.D((main_dfi_p0_wrdata_en & main_dfi_p0_wrdata_mask[1])),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(sdram_dm[1])\n);\n\nOFS1P3BX OFS1P3BX_22(\n\t.D(main_dfi_p0_wrdata[0]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate0__o)\n);\n\nIFS1P3BX IFS1P3BX(\n\t.D(builder_inferedsdrtristate0__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[0])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO (\n\t.B(sdram_dq[0]),\n\t.I(builder_inferedsdrtristate0__o),\n\t.T((~builder_inferedsdrtristate0_oe)),\n\t.O(builder_inferedsdrtristate0__i)\n);\n\nOFS1P3BX OFS1P3BX_23(\n\t.D(main_dfi_p0_wrdata[1]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate1__o)\n);\n\nIFS1P3BX IFS1P3BX_1(\n\t.D(builder_inferedsdrtristate1__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[1])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_1 (\n\t.B(sdram_dq[1]),\n\t.I(builder_inferedsdrtristate1__o),\n\t.T((~builder_inferedsdrtristate1_oe)),\n\t.O(builder_inferedsdrtristate1__i)\n);\n\nOFS1P3BX OFS1P3BX_24(\n\t.D(main_dfi_p0_wrdata[2]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate2__o)\n);\n\nIFS1P3BX IFS1P3BX_2(\n\t.D(builder_inferedsdrtristate2__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[2])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_2 (\n\t.B(sdram_dq[2]),\n\t.I(builder_inferedsdrtristate2__o),\n\t.T((~builder_inferedsdrtristate2_oe)),\n\t.O(builder_inferedsdrtristate2__i)\n);\n\nOFS1P3BX OFS1P3BX_25(\n\t.D(main_dfi_p0_wrdata[3]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate3__o)\n);\n\nIFS1P3BX IFS1P3BX_3(\n\t.D(builder_inferedsdrtristate3__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[3])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_3 (\n\t.B(sdram_dq[3]),\n\t.I(builder_inferedsdrtristate3__o),\n\t.T((~builder_inferedsdrtristate3_oe)),\n\t.O(builder_inferedsdrtristate3__i)\n);\n\nOFS1P3BX OFS1P3BX_26(\n\t.D(main_dfi_p0_wrdata[4]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate4__o)\n);\n\nIFS1P3BX IFS1P3BX_4(\n\t.D(builder_inferedsdrtristate4__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[4])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_4 (\n\t.B(sdram_dq[4]),\n\t.I(builder_inferedsdrtristate4__o),\n\t.T((~builder_inferedsdrtristate4_oe)),\n\t.O(builder_inferedsdrtristate4__i)\n);\n\nOFS1P3BX OFS1P3BX_27(\n\t.D(main_dfi_p0_wrdata[5]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate5__o)\n);\n\nIFS1P3BX IFS1P3BX_5(\n\t.D(builder_inferedsdrtristate5__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[5])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_5 (\n\t.B(sdram_dq[5]),\n\t.I(builder_inferedsdrtristate5__o),\n\t.T((~builder_inferedsdrtristate5_oe)),\n\t.O(builder_inferedsdrtristate5__i)\n);\n\nOFS1P3BX OFS1P3BX_28(\n\t.D(main_dfi_p0_wrdata[6]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate6__o)\n);\n\nIFS1P3BX IFS1P3BX_6(\n\t.D(builder_inferedsdrtristate6__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[6])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_6 (\n\t.B(sdram_dq[6]),\n\t.I(builder_inferedsdrtristate6__o),\n\t.T((~builder_inferedsdrtristate6_oe)),\n\t.O(builder_inferedsdrtristate6__i)\n);\n\nOFS1P3BX OFS1P3BX_29(\n\t.D(main_dfi_p0_wrdata[7]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate7__o)\n);\n\nIFS1P3BX IFS1P3BX_7(\n\t.D(builder_inferedsdrtristate7__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[7])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_7 (\n\t.B(sdram_dq[7]),\n\t.I(builder_inferedsdrtristate7__o),\n\t.T((~builder_inferedsdrtristate7_oe)),\n\t.O(builder_inferedsdrtristate7__i)\n);\n\nOFS1P3BX OFS1P3BX_30(\n\t.D(main_dfi_p0_wrdata[8]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate8__o)\n);\n\nIFS1P3BX IFS1P3BX_8(\n\t.D(builder_inferedsdrtristate8__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[8])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_8 (\n\t.B(sdram_dq[8]),\n\t.I(builder_inferedsdrtristate8__o),\n\t.T((~builder_inferedsdrtristate8_oe)),\n\t.O(builder_inferedsdrtristate8__i)\n);\n\nOFS1P3BX OFS1P3BX_31(\n\t.D(main_dfi_p0_wrdata[9]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate9__o)\n);\n\nIFS1P3BX IFS1P3BX_9(\n\t.D(builder_inferedsdrtristate9__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[9])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_9 (\n\t.B(sdram_dq[9]),\n\t.I(builder_inferedsdrtristate9__o),\n\t.T((~builder_inferedsdrtristate9_oe)),\n\t.O(builder_inferedsdrtristate9__i)\n);\n\nOFS1P3BX OFS1P3BX_32(\n\t.D(main_dfi_p0_wrdata[10]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate10__o)\n);\n\nIFS1P3BX IFS1P3BX_10(\n\t.D(builder_inferedsdrtristate10__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[10])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_10 (\n\t.B(sdram_dq[10]),\n\t.I(builder_inferedsdrtristate10__o),\n\t.T((~builder_inferedsdrtristate10_oe)),\n\t.O(builder_inferedsdrtristate10__i)\n);\n\nOFS1P3BX OFS1P3BX_33(\n\t.D(main_dfi_p0_wrdata[11]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate11__o)\n);\n\nIFS1P3BX IFS1P3BX_11(\n\t.D(builder_inferedsdrtristate11__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[11])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_11 (\n\t.B(sdram_dq[11]),\n\t.I(builder_inferedsdrtristate11__o),\n\t.T((~builder_inferedsdrtristate11_oe)),\n\t.O(builder_inferedsdrtristate11__i)\n);\n\nOFS1P3BX OFS1P3BX_34(\n\t.D(main_dfi_p0_wrdata[12]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate12__o)\n);\n\nIFS1P3BX IFS1P3BX_12(\n\t.D(builder_inferedsdrtristate12__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[12])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_12 (\n\t.B(sdram_dq[12]),\n\t.I(builder_inferedsdrtristate12__o),\n\t.T((~builder_inferedsdrtristate12_oe)),\n\t.O(builder_inferedsdrtristate12__i)\n);\n\nOFS1P3BX OFS1P3BX_35(\n\t.D(main_dfi_p0_wrdata[13]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate13__o)\n);\n\nIFS1P3BX IFS1P3BX_13(\n\t.D(builder_inferedsdrtristate13__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[13])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_13 (\n\t.B(sdram_dq[13]),\n\t.I(builder_inferedsdrtristate13__o),\n\t.T((~builder_inferedsdrtristate13_oe)),\n\t.O(builder_inferedsdrtristate13__i)\n);\n\nOFS1P3BX OFS1P3BX_36(\n\t.D(main_dfi_p0_wrdata[14]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate14__o)\n);\n\nIFS1P3BX IFS1P3BX_14(\n\t.D(builder_inferedsdrtristate14__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[14])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_14 (\n\t.B(sdram_dq[14]),\n\t.I(builder_inferedsdrtristate14__o),\n\t.T((~builder_inferedsdrtristate14_oe)),\n\t.O(builder_inferedsdrtristate14__i)\n);\n\nOFS1P3BX OFS1P3BX_37(\n\t.D(main_dfi_p0_wrdata[15]),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(builder_inferedsdrtristate15__o)\n);\n\nIFS1P3BX IFS1P3BX_15(\n\t.D(builder_inferedsdrtristate15__i),\n\t.PD(1'd0),\n\t.SCLK(sys_clk),\n\t.SP(1'd1),\n\t.Q(main_dfi_p0_rddata[15])\n);\n\nTRELLIS_IO #(\n\t.DIR(\"BIDIR\")\n) TRELLIS_IO_15 (\n\t.B(sdram_dq[15]),\n\t.I(builder_inferedsdrtristate15__o),\n\t.T((~builder_inferedsdrtristate15_oe)),\n\t.O(builder_inferedsdrtristate15__i)\n);\n\nendmodule\n"
  },
  {
    "path": "src/litex_linux/top.ys",
    "content": "verilog_defaults -push\nverilog_defaults -add -defer\nread_verilog /home/INSTALL_DIR/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v\nread_verilog /home/INSTALL_DIR/linux-on-litex-vexriscv/build/ulx3s/gateware/top.v\nverilog_defaults -pop\nattrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0\nsynth_ecp5   -json top.json -top top"
  },
  {
    "path": "src/litex_linux/top_bg256.lpf",
    "content": "BLOCK RESETPATHS;\nBLOCK ASYNCPATHS;\nLOCATE COMP \"serial_tx\" SITE \"B9\";\nIOBUF PORT \"serial_tx\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"serial_rx\" SITE \"A9\";\nIOBUF PORT \"serial_rx\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"clk25\" SITE \"P6\";\nIOBUF PORT \"clk25\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"rst\" SITE \"L14\";\nIOBUF PORT \"rst\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"wifi_gpio0\" SITE \"M14\";\nIOBUF PORT \"wifi_gpio0\" IO_TYPE=LVCMOS33;\n\nLOCATE COMP \"sdram_clock\" SITE \"R15\";\nIOBUF PORT \"sdram_clock\" PULLMODE=NONE;\nIOBUF PORT \"sdram_clock\" DRIVE=4;\nIOBUF PORT \"sdram_clock\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_clock\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[0]\" SITE \"H15\";\nIOBUF PORT \"sdram_a[0]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[0]\" DRIVE=4;\nIOBUF PORT \"sdram_a[0]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[0]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[1]\" SITE \"B13\";\nIOBUF PORT \"sdram_a[1]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[1]\" DRIVE=4;\nIOBUF PORT \"sdram_a[1]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[1]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[2]\" SITE \"B12\";\nIOBUF PORT \"sdram_a[2]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[2]\" DRIVE=4;\nIOBUF PORT \"sdram_a[2]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[2]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[3]\" SITE \"J16\";\nIOBUF PORT \"sdram_a[3]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[3]\" DRIVE=4;\nIOBUF PORT \"sdram_a[3]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[3]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[4]\" SITE \"J15\";\nIOBUF PORT \"sdram_a[4]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[4]\" DRIVE=4;\nIOBUF PORT \"sdram_a[4]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[4]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[5]\" SITE \"R12\";\nIOBUF PORT \"sdram_a[5]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[5]\" DRIVE=4;\nIOBUF PORT \"sdram_a[5]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[5]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[6]\" SITE \"K16\";\nIOBUF PORT \"sdram_a[6]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[6]\" DRIVE=4;\nIOBUF PORT \"sdram_a[6]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[6]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[7]\" SITE \"R13\";\nIOBUF PORT \"sdram_a[7]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[7]\" DRIVE=4;\nIOBUF PORT \"sdram_a[7]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[7]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[8]\" SITE \"T13\";\nIOBUF PORT \"sdram_a[8]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[8]\" DRIVE=4;\nIOBUF PORT \"sdram_a[8]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[8]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[9]\" SITE \"K15\";\nIOBUF PORT \"sdram_a[9]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[9]\" DRIVE=4;\nIOBUF PORT \"sdram_a[9]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[9]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[10]\" SITE \"A13\";\nIOBUF PORT \"sdram_a[10]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[10]\" DRIVE=4;\nIOBUF PORT \"sdram_a[10]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[10]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[11]\" SITE \"R14\";\nIOBUF PORT \"sdram_a[11]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[11]\" DRIVE=4;\nIOBUF PORT \"sdram_a[11]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[11]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_a[12]\" SITE \"T14\";\nIOBUF PORT \"sdram_a[12]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_a[12]\" DRIVE=4;\nIOBUF PORT \"sdram_a[12]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_a[12]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[0]\" SITE \"F16\";\nIOBUF PORT \"sdram_dq[0]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[0]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[0]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[0]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[1]\" SITE \"E15\";\nIOBUF PORT \"sdram_dq[1]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[1]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[1]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[1]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[2]\" SITE \"F15\";\nIOBUF PORT \"sdram_dq[2]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[2]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[2]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[2]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[3]\" SITE \"D14\";\nIOBUF PORT \"sdram_dq[3]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[3]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[3]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[3]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[4]\" SITE \"E16\";\nIOBUF PORT \"sdram_dq[4]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[4]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[4]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[4]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[5]\" SITE \"C15\";\nIOBUF PORT \"sdram_dq[5]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[5]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[5]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[5]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[6]\" SITE \"D16\";\nIOBUF PORT \"sdram_dq[6]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[6]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[6]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[6]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[7]\" SITE \"B15\";\nIOBUF PORT \"sdram_dq[7]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[7]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[7]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[7]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[8]\" SITE \"R16\";\nIOBUF PORT \"sdram_dq[8]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[8]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[8]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[8]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[9]\" SITE \"P16\";\nIOBUF PORT \"sdram_dq[9]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[9]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[9]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[9]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[10]\" SITE \"P15\";\nIOBUF PORT \"sdram_dq[10]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[10]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[10]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[10]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[11]\" SITE \"N16\";\nIOBUF PORT \"sdram_dq[11]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[11]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[11]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[11]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[12]\" SITE \"N14\";\nIOBUF PORT \"sdram_dq[12]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[12]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[12]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[12]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[13]\" SITE \"M16\";\nIOBUF PORT \"sdram_dq[13]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[13]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[13]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[13]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[14]\" SITE \"M15\";\nIOBUF PORT \"sdram_dq[14]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[14]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[14]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[14]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dq[15]\" SITE \"L15\";\nIOBUF PORT \"sdram_dq[15]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dq[15]\" DRIVE=4;\nIOBUF PORT \"sdram_dq[15]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dq[15]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_we_n\" SITE \"A15\";\nIOBUF PORT \"sdram_we_n\" PULLMODE=NONE;\nIOBUF PORT \"sdram_we_n\" DRIVE=4;\nIOBUF PORT \"sdram_we_n\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_we_n\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_ras_n\" SITE \"B16\";\nIOBUF PORT \"sdram_ras_n\" PULLMODE=NONE;\nIOBUF PORT \"sdram_ras_n\" DRIVE=4;\nIOBUF PORT \"sdram_ras_n\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_ras_n\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_cas_n\" SITE \"G16\";\nIOBUF PORT \"sdram_cas_n\" PULLMODE=NONE;\nIOBUF PORT \"sdram_cas_n\" DRIVE=4;\nIOBUF PORT \"sdram_cas_n\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_cas_n\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_cs_n\" SITE \"A14\";\nIOBUF PORT \"sdram_cs_n\" PULLMODE=NONE;\nIOBUF PORT \"sdram_cs_n\" DRIVE=4;\nIOBUF PORT \"sdram_cs_n\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_cs_n\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_cke\" SITE \"L16\";\nIOBUF PORT \"sdram_cke\" PULLMODE=NONE;\nIOBUF PORT \"sdram_cke\" DRIVE=4;\nIOBUF PORT \"sdram_cke\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_cke\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_ba[0]\" SITE \"G15\";\nIOBUF PORT \"sdram_ba[0]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_ba[0]\" DRIVE=4;\nIOBUF PORT \"sdram_ba[0]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_ba[0]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_ba[1]\" SITE \"B14\";\nIOBUF PORT \"sdram_ba[1]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_ba[1]\" DRIVE=4;\nIOBUF PORT \"sdram_ba[1]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_ba[1]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dm[0]\" SITE \"C16\";\nIOBUF PORT \"sdram_dm[0]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dm[0]\" DRIVE=4;\nIOBUF PORT \"sdram_dm[0]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dm[0]\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"sdram_dm[1]\" SITE \"T15\";\nIOBUF PORT \"sdram_dm[1]\" PULLMODE=NONE;\nIOBUF PORT \"sdram_dm[1]\" DRIVE=4;\nIOBUF PORT \"sdram_dm[1]\" SLEWRATE=FAST;\nIOBUF PORT \"sdram_dm[1]\" IO_TYPE=LVCMOS33;\n\nLOCATE COMP \"user_led0\" SITE \"B11\";\nIOBUF PORT \"user_led0\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"user_led1\" SITE \"A11\";\nIOBUF PORT \"user_led1\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"user_led2\" SITE \"A12\";\nIOBUF PORT \"user_led2\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"user_led3\" SITE \"R1\";\nIOBUF PORT \"user_led3\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"user_led4\" SITE \"R2\";\nIOBUF PORT \"user_led4\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"user_led5\" SITE \"R3\";\nIOBUF PORT \"user_led5\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"user_led6\" SITE \"R4\";\nIOBUF PORT \"user_led6\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"user_led7\" SITE \"R5\";\nIOBUF PORT \"user_led7\" IO_TYPE=LVCMOS33;\n\nLOCATE COMP \"spisdcard_clk\" SITE \"J12\";\nIOBUF PORT \"spisdcard_clk\" SLEWRATE=FAST;\nIOBUF PORT \"spisdcard_clk\" IO_TYPE=LVCMOS33;\nLOCATE COMP \"spisdcard_mosi\" SITE \"H12\";\nIOBUF PORT \"spisdcard_mosi\" SLEWRATE=FAST;\nIOBUF PORT \"spisdcard_mosi\" IO_TYPE=LVCMOS33;\nIOBUF PORT \"spisdcard_mosi\" PULLMODE=UP;\nLOCATE COMP \"spisdcard_cs_n\" SITE \"G12\";\nIOBUF PORT \"spisdcard_cs_n\" SLEWRATE=FAST;\nIOBUF PORT \"spisdcard_cs_n\" IO_TYPE=LVCMOS33;\nIOBUF PORT \"spisdcard_cs_n\" PULLMODE=UP;\nLOCATE COMP \"spisdcard_miso\" SITE \"K12\";\nIOBUF PORT \"spisdcard_miso\" SLEWRATE=FAST;\nIOBUF PORT \"spisdcard_miso\" IO_TYPE=LVCMOS33;\nIOBUF PORT \"spisdcard_miso\" PULLMODE=UP;\nFREQUENCY PORT \"clk25\" 25.0 MHz;\n"
  },
  {
    "path": "src/uart_tx/.gitignore",
    "content": "*.bit\n*.svf\n*.json\n\n"
  },
  {
    "path": "src/uart_tx/Makefile",
    "content": "TARGET=uart_tx\nTOP=uart_tx\n\nOBJS+=top.v\n\nTRELLIS=/usr/local/share/trellis\n\nall: ${TARGET}.bit\n\n$(TARGET).json: $(OBJS)\n\tyosys -p \"synth_ecp5 -json $@\" $(OBJS)\n\n$(TARGET)_out.config: $(TARGET).json\n\tnextpnr-ecp5 --25k --package CABGA256 --speed 6 --json $< --textcfg $@ --lpf top.lpf --freq 65\n\n$(TARGET).bit: $(TARGET)_out.config\n\tecppack --svf ${TARGET}.svf $< $@\n\n${TARGET}.svf : ${TARGET}.bit\n\nprog: ${TARGET}.svf\n\topenFPGALoader -c digilent_hs2 $(TARGET).bit\n\nclean:\n\trm -f *.svf *.bit *.config *.ys\n\n.PHONY: prog clean\n"
  },
  {
    "path": "src/uart_tx/rst_gen.v",
    "content": "module rst_gen (\n\tinput \t\t\tclk_i,\n\tinput \t\t\trst_i,\n\toutput\t\t\trst_o\n);\n\n/* try to generate a reset */\nreg [2:0]\trst_cpt;\nalways @(posedge clk_i) begin\n\tif (rst_i)\n\t\trst_cpt = 3'b0;\n\telse begin\n\t\tif (rst_cpt == 3'b100)\n\t\t\trst_cpt = rst_cpt;\n\t\telse\n\t\t\trst_cpt = rst_cpt + 3'b1;\n\tend\nend\n\nassign rst_o = !rst_cpt[2];\n\nendmodule\n"
  },
  {
    "path": "src/uart_tx/top.lpf",
    "content": "LOCATE      COMP \"clk_i\"    SITE \"P6\";\nIOBUF       PORT \"clk_i\"    IO_TYPE=LVCMOS33;\nFREQUENCY   PORT \"clk_i\"    25 MHZ;\n\nLOCATE      COMP \"TX\"       SITE \"B9\";   // iCELink-UART3-RX\n//LOCATE      COMP \"TX\"       SITE \"B4\"; // ext-board P2-7\nIOBUF       PORT \"TX\"       IO_TYPE=LVCMOS33;\n\nLOCATE      COMP \"RX\"       SITE \"A9\";\nIOBUF       PORT \"RX\"       IO_TYPE=LVCMOS33;\n\n"
  },
  {
    "path": "src/uart_tx/top.v",
    "content": "`include \"uart_tx.v\"\n\n/* baudrate: 9600 */\n/* Top level module for keypad + UART demo */\nmodule top (\n    // input hardware clock (25 MHz)\n    clk_i, \n    // UART lines\n    TX, \n    );\n\n    parameter clk_freq = 25000000;\n    parameter baudrate = 9600;\n\n    /* Clock input */\n    input clk_i;\n\n    /* FTDI I/O */\n    output TX;\n\n    /* 9600 Hz clock generation (from 25 MHz) */\n    reg clk_9600 = 0;\n    reg [31:0] cntr_9600 = 32'b0;\n    //parameter period_9600 = /* 2500 */; /* clk_freq / 2 / baudrate */\n    parameter period_9600 = (clk_freq / 2 / baudrate);\n\n    /* 1 Hz clock generation (from 25 MHz) */\n    reg clk_1 = 0;\n    reg [31:0] cntr_1 = 32'b0;\n    parameter period_1 = 12500000;\n\n    // Note: could also use \"0\" or \"9\" below, but I wanted to\n    // be clear about what the actual binary value is.\n    parameter ASCII_0 = 8'd48;\n    parameter ASCII_9 = 8'd57;\n\n    /* UART registers */\n    reg [7:0] uart_txbyte = ASCII_0;\n    reg uart_send = 1'b1;\n    wire uart_txed;\n\n    /* LED register */\n    reg ledval = 0;\n\n    /* UART transmitter module designed for\n       8 bits, no parity, 1 stop bit. \n    */\n    uart_tx_8n1 transmitter (\n        // 9600 baud rate clock\n        .clk (clk_9600),\n        // byte to be transmitted\n        .txbyte (uart_txbyte),\n        // trigger a UART transmit on baud clock\n        .senddata (uart_send),\n        // input: tx is finished\n        .txdone (uart_txed),\n        // output UART tx pin\n        .tx (TX),\n    );\n\n    /* Wiring */\n    assign LED=ledval;\n    \n    /* Low speed clock generation */\n    always @ (posedge clk_i) begin\n        /* generate 500K Hz clock */\n        cntr_9600 <= cntr_9600 + 1;\n        if (cntr_9600 == period_9600) begin\n            clk_9600 <= ~clk_9600;\n            cntr_9600 <= 32'b0;\n        end\n\n        /* generate 1 Hz clock */\n        cntr_1 <= cntr_1 + 1;\n        if (cntr_1 == period_1) begin\n            clk_1 <= ~clk_1;\n            cntr_1 <= 32'b0;\n        end\n    end\n\n    /* Increment ASCII digit and blink LED */\n    always @ (posedge clk_1 ) begin\n        ledval <= ~ledval;\n        if (uart_txbyte == ASCII_9) begin\n            uart_txbyte <= ASCII_0;\n        end else begin\n            uart_txbyte <= uart_txbyte + 1;\n        end\n    end\n\nendmodule\n"
  },
  {
    "path": "src/uart_tx/uart_tx.v",
    "content": "// 8N1 UART Module, transmit only\n\nmodule uart_tx_8n1 (\n    clk,        // input clock\n    txbyte,     // outgoing byte\n    senddata,   // trigger tx\n    txdone,     // outgoing byte sent\n    tx,         // tx wire\n    );\n\n    /* Inputs */\n    input clk;\n    input[7:0] txbyte;\n    input senddata;\n\n    /* Outputs */\n    output txdone;\n    output tx;\n\n    /* Parameters */\n    parameter STATE_IDLE=8'd0;\n    parameter STATE_STARTTX=8'd1;\n    parameter STATE_TXING=8'd2;\n    parameter STATE_TXDONE=8'd3;\n\n    /* State variables */\n    reg[7:0] state=8'b0;\n    reg[7:0] buf_tx=8'b0;\n    reg[7:0] bits_sent=8'b0;\n    reg txbit=1'b1;\n    reg txdone=1'b0;\n\n    /* Wiring */\n    assign tx=txbit;\n\n    /* always */\n    always @ (posedge clk) begin\n        // start sending?\n        if (senddata == 1 && state == STATE_IDLE) begin\n            state <= STATE_STARTTX;\n            buf_tx <= txbyte;\n            txdone <= 1'b0;\n        end else if (state == STATE_IDLE) begin\n            // idle at high\n            txbit <= 1'b1;\n            txdone <= 1'b0;\n        end\n\n        // send start bit (low)\n        if (state == STATE_STARTTX) begin\n            txbit <= 1'b0;\n            state <= STATE_TXING;\n        end\n        // clock data out\n        if (state == STATE_TXING && bits_sent < 8'd8) begin\n            txbit <= buf_tx[0];\n            buf_tx <= buf_tx>>1;\n            bits_sent = bits_sent + 1;\n        end else if (state == STATE_TXING) begin\n            // send stop bit (high)\n            txbit <= 1'b1;\n            bits_sent <= 8'b0;\n            state <= STATE_TXDONE;\n        end\n\n        // tx done\n        if (state == STATE_TXDONE) begin\n            txdone <= 1'b1;\n            state <= STATE_IDLE;\n        end\n\n    end\n\nendmodule"
  },
  {
    "path": "src/uart_tx/uart_tx_out.config",
    "content": ".device LFE5U-25F\n\n.comment Part: LFE5U-25F-6CABGA256\n\n.tile CIB_R1C24:CIB\narc: S1_V02S0001 V01N0001\n\n.tile CIB_R1C34:CIB\narc: S1_V02S0001 V01N0001\n\n.tile CIB_R1C38:CIB\narc: H00L0100 V02N0101\narc: JA0 H00L0100\nenum: CIB.JB0MUX 0\n\n.tile CIB_R1C39:CIB\narc: JD7 V02N0601\n\n.tile CIB_R29C1:CIB_LR\narc: JD7 V00B0000\narc: V00B0000 S1_V02N0201\n\n.tile CIB_R31C1:CIB_LR\narc: N1_V02N0201 S3_V06N0103\n\n.tile CIB_R37C1:CIB_LR_S\narc: N3_V06N0103 S3_V06N0003\n\n.tile CIB_R43C1:CIB_LR\narc: N3_V06N0003 S3_V06N0303\n\n.tile CIB_R49C1:CIB_LR_S\narc: N3_V06N0303 JF5\n\n.tile CIB_R49C3:CIB_PLL3\nenum: CIB.JA3MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R49C42:VCIB_DCU0\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C43:VCIB_DCUA\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C44:VCIB_DCUB\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C45:VCIB_DCUC\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C46:VCIB_DCUD\nenum: CIB.JA1MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C47:VCIB_DCUF\nenum: CIB.JA1MUX 0\nenum: CIB.JA3MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC2MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C48:VCIB_DCU3\nenum: CIB.JA5MUX 0\nenum: CIB.JA7MUX 0\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JC0MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C49:VCIB_DCU2\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C50:VCIB_DCUG\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C51:VCIB_DCUH\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C52:VCIB_DCUI\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB7MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C53:VCIB_DCU1\nenum: CIB.JB1MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JD0MUX 0\nenum: CIB.JD2MUX 0\n\n.tile CIB_R49C69:CIB_PLL3\nenum: CIB.JA3MUX 0\nenum: CIB.JB3MUX 0\n\n.tile CIB_R49C6:CIB_EFB0\nenum: CIB.JB3MUX 0\nenum: CIB.JC6MUX 0\nenum: CIB.JD6MUX 0\n\n.tile CIB_R49C7:CIB_EFB1\nenum: CIB.JA3MUX 0\nenum: CIB.JA4MUX 0\nenum: CIB.JA5MUX 0\nenum: CIB.JA6MUX 0\nenum: CIB.JB3MUX 0\nenum: CIB.JB4MUX 0\nenum: CIB.JB5MUX 0\nenum: CIB.JB6MUX 0\nenum: CIB.JC3MUX 0\nenum: CIB.JC4MUX 0\nenum: CIB.JC5MUX 0\nenum: CIB.JD3MUX 0\nenum: CIB.JD4MUX 0\nenum: CIB.JD5MUX 0\n\n.tile MIB_R0C31:TMID_0\narc: G_TDCC0CLKI G_JTRQPCLKCIB1\n\n.tile MIB_R0C38:PIOT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R0C69:BANKREF1\nenum: BANK.VCCIO 3V3\n\n.tile MIB_R13C21:DSP_SPINE_UL0\narc: G_VPTX0000 G_HPRX0000\narc: G_VPTX0100 G_HPRX0100\n\n.tile MIB_R13C31:CMUX_UL_0\narc: G_DCS0CLK0 G_VPFN0000\narc: G_ULPCLK0 G_HPFE0000\narc: G_ULPCLK1 G_VPFS0000\n\n.tile MIB_R13C32:CMUX_UR_0\narc: G_DCS0CLK1 G_VPFN0000\narc: G_URPCLK0 G_HPFE0000\narc: G_URPCLK1 G_VPFS0000\n\n.tile MIB_R13C3:DSP_SPINE_UL1\nunknown: F2B0\nunknown: F3B0\nunknown: F5B0\nunknown: F11B0\nunknown: F13B0\n\n.tile MIB_R13C41:DSP_SPINE_UR0\narc: G_VPTX0000 G_HPRX0000\narc: G_VPTX0100 G_HPRX0100\n\n.tile MIB_R1C38:PICT0\nenum: PIOA.BASE_TYPE OUTPUT_LVCMOS33\n\n.tile MIB_R25C3:LMID_0\narc: G_LDCC0CLKI G_JLLQPCLKCIB0\n\n.tile MIB_R37C31:CMUX_LL_0\narc: G_DCS1CLK0 G_VPFN0000\narc: G_LLPCLK0 G_HPFE0000\narc: G_LLPCLK1 G_VPFS0000\n\n.tile MIB_R37C32:CMUX_LR_0\narc: G_DCS1CLK1 G_VPFN0000\narc: G_LRPCLK0 G_HPFE0000\narc: G_LRPCLK1 G_VPFS0000\n\n.tile MIB_R48C0:PICL1\nenum: PIOC.BASE_TYPE INPUT_LVCMOS33\nenum: PIOC.HYSTERESIS ON\n\n.tile MIB_R49C0:MIB_CIB_LR\nenum: PIOC.BASE_TYPE INPUT_LVCMOS33\n\n.tile MIB_R50C4:EFB0_PICB0\nunknown: F54B1\nunknown: F56B1\nunknown: F82B1\nunknown: F94B1\n\n.tile R2C24:PLC2\narc: E1_H02E0501 V02N0501\narc: H00R0100 H02W0501\narc: S1_V02S0201 V01N0001\narc: V00B0000 V02S0001\narc: V00B0100 V02N0301\narc: V00T0100 V02N0501\narc: A5 V00T0100\narc: B5 H02W0301\narc: C5 V00B0100\narc: CLK0 G_HPBX0000\narc: D5 H00R0100\narc: F5 F5_SLICE\narc: LSR0 V00B0000\narc: M0 H02W0601\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F5\narc: V01S0000 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R2C25:PLC2\narc: E1_H02E0501 V06N0303\narc: V00B0000 V02N0001\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0501 V06N0303\narc: W1_H02W0601 S1_V02N0601\narc: A7 H02E0501\narc: B7 E1_H02W0101\narc: C7 V02N0201\narc: CLK0 G_HPBX0000\narc: D7 V02N0601\narc: F7 F7_SLICE\narc: LSR1 V00B0100\narc: M4 V00B0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: S1_V02S0401 Q4\narc: V00B0100 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R2C26:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: S1_V02S0301 V01N0101\narc: V00B0100 H02E0501\narc: A1 V02N0701\narc: B1 H02W0101\narc: C1 S1_V02N0401\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: F1 F1_SLICE\narc: LSR1 V00T0100\narc: M6 H02W0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: S1_V02S0601 Q6\narc: V00T0100 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R2C27:PLC2\narc: E1_H02E0101 V06N0103\narc: E1_H02E0301 E1_H01W0100\narc: H00R0000 V02N0401\narc: V00B0000 H02W0601\narc: V00B0100 V02N0101\narc: W1_H02W0101 V06N0103\narc: W1_H02W0201 V06N0103\narc: W1_H02W0401 S1_V02N0401\narc: A7 H00R0000\narc: B7 V00B0100\narc: C7 V02N0201\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR1 H02E0501\narc: M2 E1_H02W0601\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R2C28:PLC2\narc: E1_H02E0601 V06N0303\narc: V00B0100 V02N0301\narc: V00T0000 S1_V02N0401\narc: W1_H02W0601 V06N0303\narc: A7 V02N0101\narc: B7 H02E0101\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D7 V02N0601\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR0 H02E0301\narc: M2 V00T0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: S1_V02S0001 Q2\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R2C29:PLC2\narc: S1_V02S0101 W1_H02E0101\narc: V00B0000 H02E0601\narc: V00T0000 V02N0601\narc: V00T0100 S1_V02N0701\narc: W1_H02W0601 S1_V02N0601\narc: A5 V00T0000\narc: B5 W1_H02E0101\narc: C5 V02N0201\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: F5 F5_SLICE\narc: LSR0 V00B0100\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V00B0100 F5\narc: V01S0000 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R2C30:PLC2\narc: E1_H02E0301 V02N0301\narc: H00L0000 V02N0001\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D5 H00R0100\narc: E3_H06E0303 Q5\narc: F5 F5_SLICE\narc: H00R0100 Q5\narc: MUXCLK2 CLK0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R2C31:PLC2\narc: E1_H02E0101 V01N0101\narc: V00T0100 E1_H02W0301\narc: B7 H02E0301\narc: C7 V02N0001\narc: CE0 V02N0201\narc: CLK0 G_HPBX0100\narc: D7 V02N0401\narc: E1_H02E0201 Q0\narc: F7 F7_SLICE\narc: LSR0 V00B0100\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V00B0100 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000011000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R2C32:PLC2\narc: E1_H02E0401 S1_V02N0401\narc: H00R0000 E1_H02W0401\narc: S1_V02S0301 E1_H02W0301\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 H02W0401\narc: A0 H02W0501\narc: B2 V01N0001\narc: B3 H00R0000\narc: B4 E1_H02W0301\narc: B5 H02E0101\narc: B6 V00B0000\narc: B7 E1_H02W0101\nword: SLICED.K0.INIT 0011110000000000\nword: SLICED.K1.INIT 0011110000000000\nword: SLICEC.K0.INIT 0011110000000000\nword: SLICEC.K1.INIT 1001011010101010\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0011110000000000\nword: SLICEB.K1.INIT 0011110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R2C33:PLC2\narc: S1_V02S0201 W1_H02E0201\narc: V00B0100 V02N0101\narc: V00T0000 W1_H02E0201\narc: W1_H02W0301 V01N0101\narc: B0 V01N0001\narc: B1 V00T0000\narc: CE3 V02N0601\narc: CLK0 G_HPBX0100\narc: E1_H02E0001 F2\narc: F2 F2_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: LSR1 E1_H02W0501\narc: M6 V00B0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: V01S0000 Q6\narc: W1_H02W0401 Q6\narc: W1_H02W0501 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 0011110000000000\nword: SLICEA.K1.INIT 0011110000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1111111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R2C34:PLC2\narc: S1_V02S0201 H02W0201\narc: S1_V02S0501 E1_H01W0100\narc: V00B0000 V02S0001\narc: V00B0100 V02N0301\narc: V00T0100 V02N0501\narc: W1_H02W0101 V01N0101\narc: W1_H02W0301 E1_H01W0100\narc: B5 V00B0100\narc: C5 V00T0100\narc: CE3 S1_V02N0601\narc: CLK0 G_HPBX0100\narc: D5 V02N0401\narc: F5 F5_SLICE\narc: LSR0 V00B0000\narc: M6 W1_H02E0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V01N0001 F5\narc: V01S0100 Q6\narc: W1_H02W0401 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R2C35:PLC2\narc: E3_H06E0103 V01N0101\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0601 E1_H02W0601\narc: V00B0100 V02N0301\narc: V00T0100 V02N0701\narc: W1_H02W0201 V01N0001\narc: W1_H02W0501 V02N0501\narc: B5 V00B0100\narc: C5 V01N0101\narc: CE0 V02N0201\narc: CLK0 G_HPBX0100\narc: D5 S1_V02N0401\narc: E1_H01E0101 F5\narc: F5 F5_SLICE\narc: H01W0100 Q0\narc: LSR0 H02W0501\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R2C36:PLC2\narc: E1_H02E0201 V01N0001\narc: W1_H02W0501 H01E0101\narc: E3_H06E0303 W3_H06E0303\narc: B3 S1_V02N0101\narc: C3 E1_H01W0000\narc: CLK0 G_HPBX0100\narc: D3 S1_V02N0201\narc: E1_H02E0001 Q0\narc: F3 F3_SLICE\narc: LSR1 V00T0100\narc: M0 V00T0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: V00T0000 Q0\narc: V00T0100 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1100000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\n\n.tile R2C37:PLC2\narc: B5 V01S0000\narc: B7 V01S0000\narc: C4 V00T0000\narc: C5 S1_V02N0201\narc: C7 S1_V02N0001\narc: CLK0 G_HPBX0100\narc: D4 H02E0001\narc: D5 V02N0601\narc: D7 V02N0601\narc: E1_H01E0001 F4\narc: E1_H02E0601 F4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F4\narc: LSR1 V00B0100\narc: M0 V00T0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: S1_V02S0401 F4\narc: S1_V02S0501 F5\narc: S1_V02S0601 F4\narc: V00B0100 F7\narc: V00T0000 Q0\narc: V01S0000 F4\narc: W1_H02W0601 F4\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEC.K0.INIT 0000000000001111\nword: SLICEC.K1.INIT 1100000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R2C38:PLC2\narc: S1_V02S0001 H01E0001\narc: S1_V02S0201 H06E0103\narc: A2 S1_V02N0501\narc: A3 V01N0101\narc: B2 V02N0301\narc: B3 V02N0101\narc: C2 H02E0601\narc: C3 V02N0601\narc: CE1 H00L0000\narc: CLK0 G_HPBX0100\narc: D2 W1_H02E0201\narc: D3 V02N0001\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: H00L0000 F2\narc: MUXCLK1 CLK0\narc: N1_V02N0101 Q3\nword: SLICEB.K0.INIT 0110000000000000\nword: SLICEB.K1.INIT 1000000011000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET SET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R2C39:PLC2\narc: N1_V02N0601 H06E0303\n\n.tile R3C24:PLC2\narc: E1_H02E0001 N1_V01S0000\narc: E1_H02E0501 E1_H01W0100\narc: H00L0100 E1_H02W0101\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0501 E1_H02W0501\narc: S1_V02S0501 E1_H02W0501\narc: V00B0000 V02S0201\narc: V00B0100 S1_V02N0101\narc: V00T0100 E1_H02W0301\narc: A1 E1_H02W0501\narc: A5 E1_H02W0501\narc: B1 S1_V02N0101\narc: B5 V00B0100\narc: C1 H00L0100\narc: C5 V00T0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0001\narc: D5 S1_V02N0601\narc: E1_H02E0201 Q2\narc: E1_H02E0301 F1\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: LSR1 V00B0000\narc: M2 E1_H02W0601\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R3C25:PLC2\narc: E1_H02E0501 S1_V02N0501\narc: H00L0000 H02E0201\narc: N1_V02N0001 V01N0001\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0001 H02E0001\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 H02W0501\narc: V00B0000 S1_V02N0201\narc: V00B0100 S1_V02N0101\narc: V00T0100 H02W0301\narc: A3 V01N0101\narc: A5 H02W0501\narc: B3 H00L0000\narc: B5 V00B0100\narc: C3 E1_H02W0601\narc: C5 V00T0100\narc: CLK0 G_HPBX0000\narc: D3 H02E0001\narc: D5 S1_V02N0401\narc: E1_H02E0301 F3\narc: E1_H02E0701 F5\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q6\narc: LSR1 H02E0301\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: V01S0000 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0100000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R3C26:PLC2\narc: E1_H02E0701 E1_H01W0100\narc: H00R0000 S1_V02N0601\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0201 W1_H02E0201\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 E1_H01W0000\narc: V00B0000 V02N0201\narc: V00B0100 V02N0301\narc: V00T0000 V02S0601\narc: V00T0100 S1_V02N0701\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V01N0001\narc: A0 E1_H02W0701\narc: A1 F7\narc: A3 E1_H02W0501\narc: A7 W1_H02E0501\narc: B0 F1\narc: B1 H02E0301\narc: B3 F1\narc: B7 S1_V02N0501\narc: C0 S1_V02N0401\narc: C1 V02N0601\narc: C3 S1_V02N0401\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D0 H00R0000\narc: D1 V00T0100\narc: D3 H00R0000\narc: D7 V00B0000\narc: E1_H01E0001 F1\narc: E1_H02E0001 F0\narc: E1_H02E0101 F1\narc: E1_H02E0301 F1\narc: E3_H06E0103 F1\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: LSR1 H02E0501\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q4\narc: S1_V02S0401 Q4\narc: S3_V06S0103 F1\narc: V01S0000 F1\narc: V01S0100 F3\narc: W1_H02W0101 F1\narc: W1_H02W0301 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0111111111111111\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R3C27:PLC2\narc: E1_H02E0401 H01E0001\narc: H00L0100 H02E0101\narc: H00R0000 H02W0601\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0201 H01E0001\narc: S1_V02S0301 N1_V01S0100\narc: V00B0000 H02W0601\narc: V00B0100 W1_H02E0701\narc: V00T0100 V02N0501\narc: W1_H02W0401 E1_H01W0000\narc: A1 E1_H01E0001\narc: A4 N1_V01S0100\narc: A5 H02W0701\narc: B1 H02W0301\narc: B4 V02N0701\narc: B5 H02W0301\narc: C1 H00L0100\narc: C4 S1_V02N0201\narc: C5 H01E0001\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D4 E1_H02W0201\narc: D5 V00B0000\narc: E1_H01E0001 F4\narc: E1_H01E0101 F4\narc: E1_H02E0601 F4\narc: F1 F1_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 Q6\narc: H01W0100 F4\narc: LSR0 V00B0100\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: N1_V02N0401 F4\narc: S1_V02S0501 F5\narc: S3_V06S0203 F4\narc: V01S0100 F1\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R3C28:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V01N0001\narc: E1_H02E0501 H01E0101\narc: H00R0000 S1_V02N0601\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0601 S1_V02N0601\narc: S1_V02S0001 E1_H01W0000\narc: S1_V02S0201 H02W0201\narc: S1_V02S0501 V01N0101\narc: S1_V02S0601 H02E0601\narc: S1_V02S0701 N1_V01S0100\narc: V00B0000 V02S0001\narc: V00T0100 V02N0701\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0501 H01E0101\narc: W1_H02W0601 S1_V02N0601\narc: W1_H02W0701 H01E0101\narc: A1 E1_H01E0001\narc: A3 H01E0001\narc: A5 W1_H02E0701\narc: B1 V00B0000\narc: B3 S1_V02N0301\narc: B5 S1_V02N0501\narc: C1 E1_H01W0000\narc: C3 H02E0401\narc: C5 H02E0401\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D3 H00R0000\narc: D5 S1_V02N0601\narc: E1_H01E0001 Q6\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F1\narc: LSR1 V00B0100\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: S1_V02S0301 F3\narc: V00B0100 F5\narc: V01S0000 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R3C29:PLC2\narc: N1_V02N0201 H06E0103\narc: N1_V02N0601 W1_H02E0601\narc: S1_V02S0201 H06E0103\narc: S1_V02S0601 W1_H02E0601\narc: V00B0000 E1_H02W0601\narc: V00B0100 V02S0101\narc: W1_H02W0201 N1_V01S0000\narc: A5 H02E0501\narc: B5 V00B0100\narc: C5 V02N0001\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: F5 F5_SLICE\narc: H01W0000 Q6\narc: H01W0100 F5\narc: LSR1 H02E0301\narc: M6 H02E0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R3C30:PLC2\narc: E1_H02E0301 E3_H06W0003\narc: N1_V02N0001 W1_H02E0001\narc: N1_V02N0301 E3_H06W0003\narc: V00B0100 V02N0301\narc: V00T0100 S1_V02N0701\narc: CLK0 G_HPBX0000\narc: LSR0 V00B0100\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: S1_V02S0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R3C31:PLC2\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 E1_H02W0401\narc: V00B0000 E1_H02W0401\narc: V00T0000 E1_H02W0001\narc: V00T0100 V02N0701\narc: W1_H02W0601 S1_V02N0601\narc: B5 H02E0301\narc: C5 V00T0000\narc: CE0 E1_H02W0101\narc: CLK0 G_HPBX0100\narc: D5 V00B0000\narc: E1_H01E0101 Q0\narc: E3_H06E0003 Q0\narc: F5 F5_SLICE\narc: LSR0 V00B0100\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0101 Q0\narc: V00B0100 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R3C32:PLC2\narc: H00R0000 V02S0401\narc: V00B0000 E1_H02W0401\narc: V00B0100 V02S0301\narc: A0 V02N0501\narc: B2 H00L0000\narc: B3 H00R0000\narc: B4 V00B0100\narc: B5 H01E0101\narc: B6 V02S0701\narc: B7 V00B0000\narc: CE1 H02W0101\narc: CLK0 G_HPBX0100\narc: E1_H01E0001 Q2\narc: E1_H01E0101 F6\narc: E1_H02E0501 F7\narc: E3_H06E0203 F4\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: LSR1 E1_H02W0301\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 Q2\narc: S1_V02S0701 F5\narc: V01S0000 F3\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R3C33:PLC2\narc: E1_H02E0401 H01E0001\narc: H00R0000 E1_H02W0601\narc: N1_V02N0101 H01E0101\narc: N1_V02N0601 E1_H01W0000\narc: V00B0000 V02S0201\narc: W1_H02W0001 E1_H02W0501\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0401 E1_H02W0101\narc: A5 V00T0000\narc: B0 V00T0000\narc: B1 V00B0000\narc: B5 N1_V01S0000\narc: C5 H02W0401\narc: CE0 H00R0000\narc: CLK0 G_HPBX0100\narc: D5 V00B0000\narc: E1_H02E0501 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: LSR0 E1_H02W0301\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 F1\narc: V00T0000 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000001\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R3C34:PLC2\narc: E1_H02E0301 N1_V01S0100\narc: E1_H02E0501 V02S0501\narc: H00R0100 H02W0501\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 H02W0501\narc: V00B0000 H02W0401\narc: V00B0100 W1_H02E0501\narc: V00T0100 E1_H02W0301\narc: B1 E1_H02W0301\narc: B6 E1_H02W0301\narc: C1 H00R0100\narc: C6 V02S0201\narc: C7 V00T0100\narc: CE2 V02N0601\narc: CLK0 G_HPBX0100\narc: D1 E1_H02W0001\narc: D6 E1_H01W0100\narc: D7 H00R0100\narc: E1_H01E0001 F7\narc: E1_H01E0101 F6\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 F7\narc: LSR0 V00B0000\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 Q4\narc: V01S0000 F7\narc: W1_H02W0301 F1\narc: W1_H02W0401 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000011000000\nword: SLICED.K1.INIT 1111000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000011000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\n\n.tile R3C35:PLC2\narc: H00R0100 W1_H02E0501\narc: N1_V02N0201 H01E0001\narc: N1_V02N0301 H02W0301\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 H06E0203\narc: S1_V02S0001 V01N0001\narc: S1_V02S0201 E1_H01W0000\narc: S1_V02S0301 H02W0301\narc: S1_V02S0401 H02W0401\narc: V00T0100 V02N0701\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0601 H01E0001\narc: A2 H02E0501\narc: B2 H02E0301\narc: B3 H00L0000\narc: B4 H02W0301\narc: C2 W1_H02E0401\narc: C3 H00R0100\narc: C4 V00B0100\narc: C5 V02N0001\narc: CLK0 G_HPBX0100\narc: D2 E1_H02W0001\narc: D3 V02S0001\narc: D4 H01W0000\narc: D5 V02S0601\narc: E1_H01E0001 F3\narc: E1_H01E0101 F3\narc: E1_H02E0401 Q6\narc: E1_H02E0701 F5\narc: E3_H06E0003 F3\narc: E3_H06E0303 F5\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H00L0000 F2\narc: H01W0000 F3\narc: H01W0100 F3\narc: LSR1 V00T0100\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F5\narc: N1_V01N0101 F5\narc: S1_V02S0501 F5\narc: V00B0000 Q6\narc: V00B0100 F5\narc: V01S0000 F3\narc: W1_H02W0101 F3\narc: W1_H02W0401 F4\narc: W1_H02W0501 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000011000000\nword: SLICEC.K1.INIT 0000111100000000\nword: SLICEB.K0.INIT 0000000100000000\nword: SLICEB.K1.INIT 0011111100000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\n\n.tile R3C36:PLC2\narc: E1_H02E0201 H01E0001\narc: E1_H02E0501 S1_V02N0501\narc: H00R0000 V02N0601\narc: H00R0100 H02E0701\narc: V00B0000 H02E0401\narc: W1_H02W0001 H01E0001\narc: W1_H02W0401 H01E0001\narc: A5 V00T0000\narc: B2 F3\narc: B4 V02N0701\narc: B5 H00R0000\narc: C2 H00R0100\narc: C3 E1_H02W0601\narc: C4 V00B0100\narc: C5 H02W0601\narc: CLK0 G_HPBX0100\narc: D2 H01E0101\narc: D3 V00B0100\narc: D4 H00R0100\narc: D5 V00B0000\narc: E1_H01E0001 F3\narc: E1_H02E0101 F3\narc: E1_H02E0301 F3\narc: E1_H02E0701 F5\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F4\narc: H01W0100 F2\narc: LSR1 H02W0501\narc: M0 V00T0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0001 F5\narc: S1_V02S0101 F3\narc: V00B0100 F5\narc: V00T0000 Q0\narc: V01S0000 F3\narc: W1_H02W0301 F3\narc: W3_H06W0003 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 1100111111111111\nword: SLICEC.K1.INIT 0000000000000001\nword: SLICEB.K0.INIT 0000000011000000\nword: SLICEB.K1.INIT 1111000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\n\n.tile R3C37:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 S1_V02N0401\narc: E1_H02E0701 W1_H02E0701\narc: H00L0100 H02E0301\narc: N1_V02N0601 H01E0001\narc: S1_V02S0201 H02E0201\narc: S1_V02S0601 H01E0001\narc: S1_V02S0701 H02E0701\narc: V00T0000 V02S0601\narc: V00T0100 V02S0501\narc: W1_H02W0001 W3_H06E0003\narc: B5 S1_V02N0501\narc: C5 V00T0000\narc: CLK0 G_HPBX0100\narc: D5 H00L0100\narc: F5 F5_SLICE\narc: LSR0 V00T0100\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00B0000 Q6\narc: W1_H02W0501 F5\narc: W1_H02W0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R3C38:PLC2\narc: H00R0000 V02N0401\narc: H00R0100 H02E0701\narc: N1_V02N0001 H06E0003\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0301 H02E0301\narc: N1_V02N0601 H06E0303\narc: S1_V02S0001 H06E0003\narc: S1_V02S0101 W1_H02E0101\narc: S1_V02S0301 H06E0003\narc: S1_V02S0501 H06E0303\narc: S1_V02S0701 W1_H02E0701\narc: V00B0100 W1_H02E0501\narc: V00T0100 V02N0701\narc: W1_H02W0601 V01N0001\narc: A0 H00L0000\narc: A1 H00L0000\narc: A2 V00B0000\narc: A3 V00B0000\narc: A4 V00T0000\narc: A5 V00T0000\narc: A6 V02N0101\narc: A7 V02N0301\narc: B0 W1_H02E0101\narc: B1 W1_H02E0101\narc: B2 W1_H02E0101\narc: B3 W1_H02E0101\narc: B4 W1_H02E0101\narc: B5 W1_H02E0101\narc: B6 W1_H02E0101\narc: B7 W1_H02E0101\narc: C0 H00R0100\narc: C1 H00R0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 V02S0201\narc: C5 V02S0201\narc: C6 V02S0201\narc: C7 V02S0201\narc: CE0 H00R0000\narc: CE1 H00R0000\narc: CE2 H00R0000\narc: CE3 H00R0000\narc: CLK0 G_HPBX0100\narc: D0 W1_H02E0201\narc: D1 W1_H02E0201\narc: D2 W1_H02E0201\narc: D3 W1_H02E0201\narc: D4 W1_H02E0201\narc: D5 W1_H02E0201\narc: D6 W1_H02E0201\narc: D7 W1_H02E0201\narc: F0 F5A_SLICE\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: H00L0000 Q2\narc: M0 V00T0100\narc: M2 E1_H02W0601\narc: M4 H02E0401\narc: M6 V00B0100\narc: MUXCLK0 CLK0\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q4\narc: V00B0000 Q6\narc: V00T0000 Q0\nword: SLICEB.K0.INIT 1000000000000000\nword: SLICEB.K1.INIT 1011111111111111\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 1011111111111111\nword: SLICEA.K0.INIT 1000000000000000\nword: SLICEA.K1.INIT 1011111111111111\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 1011111111111111\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R3C40:PLC2\narc: W1_H02W0601 S1_V02N0601\n\n.tile R4C23:PLC2\narc: S1_V02S0201 E1_H02W0201\narc: V00B0100 E1_H02W0701\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 Q2\narc: E3_H06E0103 Q2\narc: LSR1 E1_H02W0501\narc: M2 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R4C24:PLC2\narc: E1_H02E0101 H01E0101\narc: S1_V02S0201 E1_H02W0201\narc: A1 V02S0501\narc: A3 V02S0501\narc: B1 V02N0101\narc: B3 V02N0101\narc: C1 E1_H02W0401\narc: C3 E1_H02W0601\narc: CLK0 G_HPBX0000\narc: D1 V02N0001\narc: D3 V02N0001\narc: E1_H01E0101 F1\narc: E1_H02E0401 Q6\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: M6 H02W0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00T0100 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R4C25:PLC2\narc: E1_H02E0101 S1_V02N0101\narc: E1_H02E0301 V01N0101\narc: H00L0000 V02S0001\narc: H00R0000 N1_V02S0401\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0501 N1_V02S0401\narc: V00B0000 S1_V02N0001\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0401 E1_H02W0101\narc: W1_H02W0501 H01E0101\narc: A0 E1_H02W0701\narc: B2 H01W0100\narc: B3 H00R0000\narc: B4 H00L0000\narc: B5 H02E0101\narc: B6 V00B0000\narc: B7 N1_V01S0000\narc: CLK0 G_HPBX0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: LSR0 H02W0501\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F3\narc: N1_V01N0101 Q2\narc: N1_V02N0601 F4\narc: V01S0000 F7\narc: V01S0100 F6\narc: W1_H02W0701 F5\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R4C26:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0401 W1_H02E0401\narc: E3_H06E0003 N1_V01S0000\narc: H00L0000 V02S0201\narc: H00R0000 V02S0601\narc: N1_V02N0201 H06E0103\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0601 V01N0001\narc: S1_V02S0001 N1_V01S0000\narc: S1_V02S0101 E1_H01W0100\narc: S1_V02S0401 W1_H02E0401\narc: S1_V02S0601 N1_V01S0000\narc: V00B0100 V02N0101\narc: V00T0000 N1_V02S0601\narc: W1_H02W0201 E1_H01W0000\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 N1_V01S0100\narc: W1_H02W0601 N1_V01S0000\narc: B0 H01W0100\narc: B1 V00T0000\narc: B2 H00R0000\narc: B3 N1_V02S0301\narc: B4 H00L0000\narc: B5 H02E0101\narc: B6 H02E0301\narc: B7 V00B0100\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F7\narc: H01W0100 Q0\narc: LSR0 H02W0301\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F4\narc: N1_V02N0301 F3\narc: S1_V02S0501 F5\narc: V01S0000 F6\narc: V01S0100 Q0\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R4C27:PLC2\narc: E1_H02E0301 V02S0301\narc: H00R0000 H02E0401\narc: H00R0100 V02N0501\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 H01E0101\narc: N1_V02N0701 E1_H01W0100\narc: V00B0000 S1_V02N0201\narc: V00B0100 S1_V02N0301\narc: V00T0000 V02N0401\narc: W1_H02W0001 E1_H02W0001\narc: W1_H02W0301 N1_V01S0100\narc: W1_H02W0701 E1_H02W0701\narc: B0 H01W0100\narc: B1 H00R0100\narc: B2 H02E0301\narc: B3 H00R0000\narc: B4 V02N0701\narc: B5 V00B0100\narc: B6 V00T0000\narc: B7 V00B0000\narc: CLK0 G_HPBX0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F1\narc: H01W0100 Q0\narc: LSR1 H02W0301\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: S1_V02S0401 F6\narc: S1_V02S0501 F7\narc: S1_V02S0601 F4\narc: S1_V02S0701 F5\narc: V01S0000 F2\narc: W1_H02W0101 F3\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R4C28:PLC2\narc: E1_H02E0101 V02N0101\narc: E1_H02E0601 V02N0601\narc: E1_H02E0701 S1_V02N0701\narc: H00L0000 V02S0201\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 S1_V02N0401\narc: W1_H02W0301 V01N0101\narc: B0 H01W0100\narc: B1 H02E0301\narc: B2 V01N0001\narc: B3 H00L0000\narc: B4 V02S0701\narc: B5 N1_V01S0000\narc: B6 V00T0000\narc: B7 V00B0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 F1\narc: E1_H01E0101 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 F7\narc: N1_V01N0101 F2\narc: N1_V02N0401 F4\narc: N1_V02N0701 F5\narc: V01S0000 F6\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R4C29:PLC2\narc: H00R0000 V02S0601\narc: N1_V02N0001 H06E0003\narc: N1_V02N0601 H01E0001\narc: N1_V02N0701 H01E0101\narc: V00B0000 H02E0601\narc: A7 H00R0000\narc: B0 V00T0000\narc: B1 V02N0101\narc: B7 H02E0101\narc: C7 V02S0201\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: E3_H06E0303 F5\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: LSR0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: S1_V02S0501 F5\narc: S3_V06S0103 F1\narc: V00B0100 F7\narc: V00T0000 Q0\narc: W1_H02W0001 Q0\narc: W1_H02W0701 F5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R4C30:PLC2\narc: H00L0100 S1_V02N0101\narc: A1 W1_H02E0701\narc: A3 W1_H02E0701\narc: B1 E1_H02W0101\narc: B3 E1_H02W0101\narc: C1 H00L0100\narc: C3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0001\narc: D3 E1_H02W0001\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: M4 E1_H02W0401\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V02N0301 F1\narc: V00T0100 F3\narc: V01S0100 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R4C31:PLC2\narc: E1_H02E0401 V01N0001\narc: N1_V02N0701 H02W0701\narc: V00B0000 E1_H02W0601\narc: V00T0100 V02N0501\narc: A5 V00B0000\narc: B5 H02W0101\narc: C5 S1_V02N0001\narc: CLK0 G_HPBX0000\narc: D5 H02W0001\narc: F5 F5_SLICE\narc: LSR0 V00B0100\narc: M2 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: S3_V06S0103 Q2\narc: V00B0100 F5\narc: V01S0000 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R4C32:PLC2\narc: E1_H02E0001 S1_V02N0001\narc: H00L0100 S1_V02N0301\narc: H00R0000 S1_V02N0601\narc: N1_V02N0401 N1_V01S0000\narc: N1_V02N0501 H06E0303\narc: V00B0000 S1_V02N0001\narc: V00B0100 S1_V02N0301\narc: V00T0000 S1_V02N0601\narc: W1_H02W0001 S1_V02N0001\narc: W1_H02W0101 S1_V02N0101\narc: W1_H02W0401 V02N0401\narc: W1_H02W0701 V02S0701\narc: A1 H00R0000\narc: A3 V00T0000\narc: A5 V00T0000\narc: B1 S1_V02N0101\narc: B3 S1_V02N0101\narc: B5 S1_V02N0701\narc: C1 H00L0100\narc: C3 H00L0100\narc: C5 V00B0100\narc: CLK0 G_HPBX0000\narc: D1 S1_V02N0201\narc: D3 S1_V02N0201\narc: D5 V00B0000\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: LSR1 V00T0100\narc: M6 H02E0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: S1_V02S0101 F3\narc: S1_V02S0601 Q6\narc: S1_V02S0701 F5\narc: V00T0100 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R4C33:PLC2\narc: E1_H02E0601 V01N0001\narc: H00L0100 S1_V02N0101\narc: H00R0100 S1_V02N0701\narc: S1_V02S0701 E1_H01W0100\narc: V00T0000 V02N0401\narc: W1_H02W0601 S1_V02N0601\narc: A1 S1_V02N0501\narc: A3 S1_V02N0501\narc: B1 V02N0301\narc: B3 V02N0101\narc: C1 H00R0100\narc: C3 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: D3 H02E0001\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: S1_V02S0101 F1\narc: S1_V02S0601 Q4\narc: V00T0100 F3\narc: V01S0000 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R4C34:PLC2\narc: H00L0100 S1_V02N0301\narc: N1_V02N0601 N1_V01S0000\narc: V00B0100 S1_V02N0301\narc: V00T0000 S1_V02N0601\narc: A3 V00T0000\narc: A5 V00T0000\narc: B3 V02N0101\narc: B5 V02N0701\narc: C3 H00L0100\narc: C5 V00B0100\narc: CLK0 G_HPBX0000\narc: D3 H02W0201\narc: D5 H02W0201\narc: E1_H01E0101 F5\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0100 Q0\narc: LSR1 H02W0301\narc: M0 H02E0601\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: S1_V02S0101 F3\narc: S1_V02S0201 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R4C35:PLC2\narc: E1_H02E0601 N1_V02S0601\narc: H00L0100 V02S0301\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0401 N1_V01S0000\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0601\narc: V00T0100 V02S0501\narc: W1_H02W0201 S1_V02N0201\narc: W1_H02W0301 H01E0101\narc: S1_V02S0501 W3_H06E0303\narc: B5 V00B0100\narc: B7 H02W0301\narc: C5 V00T0100\narc: C7 V00T0000\narc: CE0 V02S0201\narc: CLK0 G_HPBX0100\narc: D5 V02S0401\narc: D7 H00L0100\narc: E3_H06E0003 Q0\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: LSR1 V00B0000\narc: M0 H02W0601\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0001 F5\narc: N1_V02N0701 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1100000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX INV\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\n\n.tile R4C36:PLC2\narc: E1_H02E0701 V01N0101\narc: H00L0000 V02N0001\narc: H00L0100 V02S0101\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0701 E1_H02W0701\narc: V00T0000 H02W0001\narc: W1_H02W0301 E1_H01W0100\narc: W1_H02W0601 V02N0601\narc: A1 V01N0101\narc: A3 V02N0501\narc: B1 S1_V02N0301\narc: B3 V01N0001\narc: B7 V00T0000\narc: C1 V02N0601\narc: C3 H00L0000\narc: C7 H02E0601\narc: CLK0 G_HPBX0100\narc: D1 V02N0201\narc: D3 S1_V02N0201\narc: D7 H00L0100\narc: F0 F5A_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: LSR1 V00B0100\narc: M0 V00T0100\narc: M4 V00B0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V02N0601 Q4\narc: S1_V02S0201 F0\narc: V00B0000 Q4\narc: V00B0100 F7\narc: V00T0100 F3\narc: V01S0100 F0\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R4C37:PLC2\narc: E1_H02E0301 E1_H01W0100\narc: H00R0000 N1_V02S0401\narc: H00R0100 V02S0701\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02S0701\narc: A2 H02W0701\narc: B2 H00R0000\narc: B3 E1_H02W0301\narc: B7 V01S0000\narc: C2 H00R0100\narc: C3 N1_V02S0401\narc: C7 V00T0000\narc: CLK0 G_HPBX0100\narc: D2 V02S0201\narc: D3 V00T0100\narc: D7 V02S0601\narc: E1_H01E0101 Q2\narc: E1_H02E0001 Q2\narc: F2 F5B_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q2\narc: LSR0 V00B0100\narc: M2 N1_V01N0001\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 Q2\narc: N1_V01N0101 Q2\narc: N1_V02N0001 Q2\narc: N1_V02N0201 Q2\narc: V00B0100 F7\narc: V01S0000 Q2\narc: V01S0100 Q2\narc: W1_H02W0001 Q2\nword: SLICEB.K0.INIT 0100000011000000\nword: SLICEB.K1.INIT 1100111111111111\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1100000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\n\n.tile R4C38:PLC2\narc: H00L0000 N1_V02S0001\narc: H00R0100 V02S0701\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 V01N0101\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0301 H06E0003\narc: V00B0000 V02S0001\narc: V00B0100 V02S0101\narc: V00T0000 H02E0001\narc: V00T0100 V02S0501\narc: A6 V02N0301\narc: A7 Q7\narc: B1 V00T0000\narc: B6 V02S0701\narc: B7 H01E0101\narc: C1 H00L0000\narc: C6 V00T0100\narc: C7 N1_V02S0001\narc: CLK0 G_HPBX0100\narc: D1 V00B0100\narc: D6 V00B0000\narc: D7 H00R0100\narc: E1_H01E0101 Q7\narc: F1 F1_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 F1\narc: LSR1 H02E0301\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q7\narc: N1_V02N0401 F6\narc: N1_V02N0501 Q7\narc: S1_V02S0601 F6\narc: V01S0100 Q7\narc: W1_H02W0701 Q7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1100000000000000\nword: SLICED.K0.INIT 1100000001000000\nword: SLICED.K1.INIT 1110101010101010\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\n\n.tile R4C39:PLC2\narc: W1_H02W0301 H01E0101\n\n.tile R5C23:PLC2\narc: V00B0000 V02S0201\narc: CLK0 G_HPBX0000\narc: E1_H02E0201 Q2\narc: E3_H06E0103 Q2\narc: LSR0 E1_H02W0301\narc: M2 V00B0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R5C24:PLC2\narc: H00L0000 V02N0201\narc: H00R0000 V02N0401\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0201 H02W0201\narc: S1_V02S0601 E1_H01W0000\narc: V00B0000 V02S0201\narc: V00T0000 V02N0401\narc: A1 E1_H02W0501\narc: A5 E1_H02W0501\narc: B1 V00T0000\narc: B5 H00R0000\narc: C1 H00L0000\narc: C5 V02N0201\narc: CLK0 G_HPBX0000\narc: D1 E1_H02W0001\narc: D5 E1_H01W0100\narc: E1_H01E0101 F1\narc: E1_H02E0601 Q6\narc: E3_H06E0303 Q6\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: LSR0 V00B0100\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00B0100 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R5C25:PLC2\narc: E1_H02E0201 W1_H02E0201\narc: N1_V02N0101 H02W0101\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0501 E1_H02W0501\narc: S1_V02S0101 H02W0101\narc: S1_V02S0701 N1_V01S0100\narc: V00B0000 V02N0001\narc: V00T0000 H02W0201\narc: W1_H02W0201 E1_H02W0701\narc: W1_H02W0301 H01E0101\narc: A5 H02W0501\narc: A7 S1_V02N0101\narc: B5 N1_V02S0501\narc: B7 V02S0501\narc: C5 H02W0601\narc: C7 V02S0001\narc: CLK0 G_HPBX0000\narc: D5 H01W0000\narc: D7 N1_V02S0401\narc: E1_H01E0001 F6\narc: E1_H01E0101 Q0\narc: E1_H02E0401 F6\narc: E1_H02E0601 F6\narc: E3_H06E0303 F6\narc: F5 F5_SLICE\narc: F6 F5D_SLICE\narc: H01W0000 F6\narc: H01W0100 F6\narc: LSR1 V00B0100\narc: M0 V00T0000\narc: M6 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0101 Q0\narc: N1_V02N0401 F6\narc: N1_V02N0601 F6\narc: N3_V06N0303 F6\narc: S1_V02S0601 F6\narc: V00B0100 F5\narc: V01S0000 F6\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000010000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R5C26:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 V02S0601\narc: H00R0000 V02S0401\narc: N1_V02N0101 H06E0103\narc: N1_V02N0401 E1_H01W0000\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 H02E0601\narc: S1_V02S0501 E1_H01W0100\narc: S1_V02S0601 H02E0601\narc: V00B0000 H02E0401\narc: V00T0000 N1_V02S0401\narc: W1_H02W0001 H01E0001\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0201 N1_V01S0000\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 V02S0601\narc: A1 H00L0000\narc: A5 E1_H01W0000\narc: A7 S1_V02N0101\narc: B1 V02S0101\narc: B5 N1_V02S0501\narc: B7 H01E0101\narc: C1 W1_H02E0601\narc: C5 V02S0001\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: D5 V00B0000\narc: D7 H02E0201\narc: F1 F1_SLICE\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: LSR1 V00B0100\narc: M2 H02W0601\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 F1\narc: N1_V01N0101 Q2\narc: N1_V02N0701 F7\narc: V00B0100 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000001\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000001\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R5C27:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0601 W1_H02E0601\narc: E1_H02E0701 S1_V02N0701\narc: H00R0000 W1_H02E0601\narc: H00R0100 S1_V02N0701\narc: N1_V02N0201 E1_H01W0000\narc: N1_V02N0501 H06E0303\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0601 W1_H02E0601\narc: V00B0000 W1_H02E0601\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0601 N1_V01S0000\narc: W1_H02W0701 V02S0701\narc: A2 E1_H01E0001\narc: A3 H02E0501\narc: A5 H02E0501\narc: B2 V01N0001\narc: B3 H00R0100\narc: B5 S1_V02N0701\narc: C2 S1_V02N0601\narc: C3 H02E0601\narc: C5 H02E0601\narc: CLK0 G_HPBX0000\narc: D2 V02N0001\narc: D3 H00R0000\narc: D5 V00B0000\narc: E1_H01E0001 Q6\narc: E1_H01E0101 F2\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F2\narc: H01W0100 F2\narc: LSR1 V00T0100\narc: M6 V00T0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V02N0001 F2\narc: N1_V02N0401 Q6\narc: N3_V06N0103 F2\narc: S1_V02S0301 F3\narc: V01S0100 F2\narc: W1_H02W0501 F5\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000001\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R5C28:PLC2\narc: E1_H02E0201 E3_H06W0103\narc: H00R0000 N1_V02S0601\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 V01N0001\narc: N1_V02N0301 H01E0101\narc: N1_V02N0501 H01E0101\narc: N1_V02N0601 H06E0303\narc: N3_V06N0303 H06E0303\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 N1_V01S0000\narc: S1_V02S0601 H06E0303\narc: V00B0000 H02E0601\narc: V00B0100 H02E0701\narc: V00T0000 H02W0201\narc: V00T0100 N1_V02S0501\narc: A5 W1_H02E0501\narc: A7 W1_H02E0501\narc: B5 H00R0000\narc: B7 V00B0100\narc: C5 V02N0201\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: D7 V00B0000\narc: F5 F5_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 F7\narc: LSR0 H02E0501\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V01N0001 Q0\narc: N1_V01N0101 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R5C29:PLC2\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 V02S0501\narc: H00R0100 V02N0501\narc: N1_V02N0101 S1_V02N0101\narc: S1_V02S0201 E3_H06W0103\narc: S1_V02S0601 E1_H02W0601\narc: V00B0100 V02N0101\narc: V00T0000 H02E0201\narc: W1_H02W0201 N1_V02S0201\narc: A1 V02N0701\narc: B1 H00R0100\narc: C1 V02N0401\narc: CLK0 G_HPBX0000\narc: D1 V00B0100\narc: E3_H06E0203 Q4\narc: F1 F1_SLICE\narc: LSR1 V00T0100\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: V00T0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R5C30:PLC2\narc: E1_H02E0101 N1_V01S0100\narc: E1_H02E0201 V02N0201\narc: E1_H02E0601 N1_V02S0601\narc: H00L0100 V02N0301\narc: N1_V02N0701 E1_H02W0701\narc: S1_V02S0401 E1_H02W0401\narc: V00B0000 V02N0201\narc: V00B0100 E1_H02W0501\narc: V00T0000 N1_V02S0601\narc: A3 V02N0701\narc: A5 N1_V01S0100\narc: B3 E1_H02W0101\narc: B5 V02N0501\narc: C3 H00L0100\narc: C5 V00T0000\narc: CLK0 G_HPBX0000\narc: D3 V02N0001\narc: D5 V00B0000\narc: E3_H06E0003 Q0\narc: F3 F3_SLICE\narc: F5 F5_SLICE\narc: LSR1 V00T0100\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: S1_V02S0701 F5\narc: V00T0100 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0010000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R5C31:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: H00R0000 H02W0601\narc: V00B0100 V02N0301\narc: V00T0000 H02E0201\narc: N1_V02N0601 W3_H06E0303\narc: A0 W1_H02E0501\narc: B2 H00L0000\narc: B3 V01N0001\narc: B4 H00R0000\narc: B5 N1_V01S0000\narc: B6 W1_H02E0301\narc: B7 V00T0000\narc: CLK0 G_HPBX0000\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: LSR0 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V01N0001 F4\narc: N1_V02N0501 F5\narc: S1_V02S0301 F3\narc: S3_V06S0203 F7\narc: V01S0000 Q2\narc: W1_H02W0601 F6\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R5C32:PLC2\narc: H00L0000 S1_V02N0001\narc: H00R0000 W1_H02E0601\narc: S1_V02S0101 V01N0101\narc: S1_V02S0401 H06E0203\narc: V00B0100 V02S0101\narc: V00T0000 V02N0401\narc: W1_H02W0101 V02N0101\narc: W1_H02W0501 E1_H02W0401\narc: W1_H02W0601 V02S0601\narc: B0 H01W0100\narc: B1 V00T0000\narc: B2 V01N0001\narc: B3 H00L0000\narc: B4 W1_H02E0101\narc: B5 H00R0000\narc: B6 S1_V02N0501\narc: B7 V02N0501\narc: CLK0 G_HPBX0000\narc: E1_H01E0001 F3\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V02N0401 F4\narc: S1_V02S0001 F2\narc: S1_V02S0301 F1\narc: V01S0000 F7\narc: V01S0100 Q0\narc: W1_H02W0401 F6\narc: W1_H02W0701 F5\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\n\n.tile R5C33:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0701 V01N0101\narc: H00R0000 S1_V02N0601\narc: N1_V02N0101 V01N0101\narc: N1_V02N0301 V01N0101\narc: S1_V02S0301 H06E0003\narc: S1_V02S0401 H01E0001\narc: S1_V02S0501 E1_H01W0100\narc: V00B0100 V02S0101\narc: V00T0000 W1_H02E0201\narc: B0 H01W0100\narc: B1 V00T0000\narc: B2 H00R0000\narc: B3 V02N0301\narc: B4 N1_V01S0000\narc: B5 V02S0701\narc: B6 H02W0101\narc: B7 S1_V02N0501\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR1 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0001 F5\narc: N1_V02N0401 F4\narc: S1_V02S0001 Q0\narc: S1_V02S0101 F1\narc: S1_V02S0701 F7\narc: V01S0000 F6\narc: V01S0100 F3\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R5C34:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: H00L0000 E1_H02W0001\narc: H00R0100 H02W0701\narc: N1_V02N0101 H02E0101\narc: N1_V02N0701 H02E0701\narc: S1_V02S0101 H01E0101\narc: S1_V02S0401 E1_H01W0000\narc: V00B0000 S1_V02N0201\narc: V00B0100 V02S0101\narc: W1_H02W0101 V01N0101\narc: B0 V00T0000\narc: B1 H00R0100\narc: B2 V02N0101\narc: B3 S1_V02N0101\narc: B4 H00L0000\narc: B5 V02N0501\narc: B6 V02N0701\narc: B7 V00B0000\narc: CLK0 G_HPBX0000\narc: E1_H01E0101 F7\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H01W0100 Q0\narc: LSR0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: S1_V02S0601 F6\narc: S1_V02S0701 F5\narc: S3_V06S0003 F3\narc: S3_V06S0103 F2\narc: V00T0000 Q0\narc: W1_H02W0401 F4\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 1100110000000000\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R5C35:PLC2\narc: E1_H02E0101 E1_H01W0100\narc: E1_H02E0401 E1_H01W0000\narc: E1_H02E0501 V02S0501\narc: S1_V02S0501 H01E0101\narc: V00B0000 V02N0201\narc: V00B0100 V02N0301\narc: W1_H02W0701 W3_H06E0203\narc: A7 V02N0101\narc: B0 V00T0000\narc: B1 H02W0301\narc: B7 W1_H02E0101\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F7 F7_SLICE\narc: H01W0000 Q0\narc: H01W0100 F7\narc: LSR1 H02E0501\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: V00T0000 Q0\narc: W3_H06W0103 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R5C36:PLC2\narc: E1_H02E0501 N1_V01S0100\narc: N1_V02N0201 H02W0201\narc: N1_V02N0601 E1_H01W0000\narc: V00B0000 V02S0201\narc: W1_H02W0301 S1_V02N0301\narc: W1_H02W0001 W3_H06E0003\narc: A0 H02E0501\narc: B2 H00L0000\narc: B3 Q3\narc: B4 H00R0000\narc: B5 H02E0101\narc: B6 V01S0000\narc: B7 V00B0100\narc: CLK1 V02N0701\narc: E1_H01E0001 Q2\narc: E1_H01E0101 Q4\narc: E1_H02E0601 Q6\narc: F2 F2_SLICE\narc: F3 F3_SLICE\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: F6 F6_SLICE\narc: F7 F7_SLICE\narc: H00L0000 Q2\narc: H00R0000 Q4\narc: H01W0000 Q7\narc: H01W0100 Q5\narc: LSR1 V00B0000\narc: MUXCLK1 CLK1\narc: MUXCLK2 CLK1\narc: MUXCLK3 CLK1\narc: MUXLSR1 LSR1\narc: MUXLSR2 LSR1\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q7\narc: N1_V01N0101 Q3\narc: N1_V02N0001 Q2\narc: N1_V02N0501 Q5\narc: V00B0100 Q7\narc: V01S0000 Q6\narc: V01S0100 Q4\nword: SLICED.K0.INIT 1100110000000000\nword: SLICED.K1.INIT 1100110000000000\nword: SLICEC.K0.INIT 1100110000000000\nword: SLICEC.K1.INIT 1100110000000000\nword: SLICEB.K0.INIT 0110011010101010\nword: SLICEB.K1.INIT 1100110000000000\nword: SLICEA.K0.INIT 0000000000001010\nword: SLICEA.K1.INIT 1111111111111111\nenum: SLICED.MODE CCU2\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 1\nenum: SLICED.REG0.REGSET SET\nenum: SLICED.REG1.REGSET SET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 NO\nenum: SLICED.CCU2.INJECT1_1 NO\nenum: SLICED.A0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE CCU2\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 NO\nenum: SLICEC.CCU2.INJECT1_1 NO\nenum: SLICEC.A0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 1\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK1.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 YES\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R5C37:PLC2\narc: E1_H02E0401 W1_H02E0401\narc: E3_H06E0303 H01E0101\narc: N1_V02N0401 H01E0001\narc: N1_V02N0501 N1_V01S0100\narc: B0 V00T0000\narc: B1 Q1\narc: CLK0 V02N0701\narc: E1_H02E0001 Q0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: H01W0000 Q1\narc: LSR0 H02E0501\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: V00T0000 Q0\narc: W1_H02W0201 Q0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000001010\nword: SLICEA.K0.INIT 1100110000000000\nword: SLICEA.K1.INIT 1100110000000000\nenum: SLICEB.MODE CCU2\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 NO\nenum: SLICEB.CCU2.INJECT1_1 NO\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE CCU2\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 1\nenum: SLICEA.REG1.SD 1\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 NO\nenum: SLICEA.CCU2.INJECT1_1 NO\nenum: SLICEA.A0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\n\n.tile R5C38:PLC2\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02S0601\narc: H00R0100 N1_V02S0501\narc: N1_V02N0301 N1_V01S0100\narc: V00B0100 N1_V02S0101\narc: V00T0000 H02E0001\narc: V00T0100 N1_V02S0501\narc: A2 E1_H01E0001\narc: A3 E1_H01E0001\narc: A4 V00B0000\narc: A5 V00B0000\narc: A6 V02S0301\narc: A7 V02S0301\narc: B2 N1_V02S0101\narc: B3 N1_V02S0101\narc: B4 V00B0100\narc: B5 V00B0100\narc: B6 V00B0100\narc: B7 V00B0100\narc: C2 H00R0100\narc: C3 H00R0100\narc: C4 V00T0100\narc: C5 V00T0100\narc: C6 V00T0100\narc: C7 V00T0100\narc: CE1 H00R0000\narc: CE2 V02S0601\narc: CE3 V02S0601\narc: CLK0 G_HPBX0100\narc: D2 N1_V02S0001\narc: D3 N1_V02S0001\narc: D4 H00L0100\narc: D5 H00L0100\narc: D6 H00L0100\narc: D7 H00L0100\narc: E1_H01E0001 Q4\narc: F2 F5B_SLICE\narc: F4 F5C_SLICE\narc: F6 F5D_SLICE\narc: M2 W1_H02E0601\narc: M4 H02E0401\narc: M6 V00T0000\narc: MUXCLK1 CLK0\narc: MUXCLK2 CLK0\narc: MUXCLK3 CLK0\narc: N1_V01N0101 Q2\narc: V00B0000 Q6\nword: SLICED.K0.INIT 1000000000000000\nword: SLICED.K1.INIT 1011111111111111\nword: SLICEC.K0.INIT 1000000000000000\nword: SLICEC.K1.INIT 1011111111111111\nword: SLICEB.K0.INIT 1000000000000000\nword: SLICEB.K1.INIT 1011111111111111\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 1\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 1\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 1\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX CE\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\n\n.tile R5C40:PLC2\narc: N1_V02N0601 H06E0303\n\n.tile R6C24:PLC2\narc: H00R0000 H02W0401\narc: N1_V02N0201 E1_H02W0201\narc: N1_V02N0401 H02W0401\narc: V00B0000 V02S0201\narc: V00T0000 E1_H02W0201\narc: A5 V02S0101\narc: B5 H00R0000\narc: C5 V00T0000\narc: CLK0 G_HPBX0000\narc: D5 V02S0601\narc: E3_H06E0003 Q0\narc: F5 F5_SLICE\narc: LSR1 V00B0100\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: V00B0100 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R6C25:PLC2\narc: H00L0000 H02W0201\narc: H00L0100 V02S0101\narc: H00R0000 E1_H02W0401\narc: N1_V02N0101 E1_H01W0100\narc: V00B0000 E1_H02W0401\narc: V00T0000 H02W0201\narc: V00T0100 V02S0701\narc: W1_H02W0401 E1_H02W0401\narc: A3 H00L0100\narc: A7 V02S0101\narc: B3 H00R0000\narc: B7 V00B0000\narc: C3 H00L0000\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D3 N1_V01S0000\narc: D7 V02S0601\narc: E1_H02E0301 F3\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: LSR1 V00B0100\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V02N0001 Q0\narc: V00B0100 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R6C26:PLC2\narc: E1_H02E0201 V06S0103\narc: H00R0000 V02S0601\narc: V00B0000 H02W0401\narc: V00T0100 N1_V02S0501\narc: W1_H02W0201 V06S0103\narc: A1 V02S0501\narc: B1 V00B0000\narc: C1 N1_V02S0601\narc: CLK0 G_HPBX0000\narc: D1 H00R0000\narc: F1 F1_SLICE\narc: H01W0100 Q2\narc: LSR1 H02E0301\narc: M2 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: S1_V02S0301 F1\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R6C27:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 V06S0203\narc: N1_V02N0001 H06E0003\narc: N1_V02N0301 H06E0003\narc: S1_V02S0601 N1_V02S0601\narc: V00B0100 V02S0301\narc: V00T0000 H02E0201\narc: V00T0100 N1_V02S0501\narc: W1_H02W0401 V06S0203\narc: A5 N1_V01S0100\narc: B5 V02N0701\narc: C5 V00T0000\narc: CLK0 G_HPBX0000\narc: D5 V02S0601\narc: F5 F5_SLICE\narc: LSR1 V00B0100\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0001 Q0\narc: N1_V02N0201 Q0\narc: S1_V02S0501 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R6C28:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: E1_H02E0701 E3_H06W0203\narc: N1_V02N0201 W1_H02E0201\narc: N1_V02N0701 E3_H06W0203\narc: V00B0000 V02S0201\narc: V00B0100 H02E0701\narc: V00T0000 W1_H02E0201\narc: A5 V02S0101\narc: B5 V00B0100\narc: C5 V00T0000\narc: CLK0 G_HPBX0000\narc: D5 V02S0601\narc: F5 F5_SLICE\narc: H01W0100 F5\narc: LSR1 H02E0501\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V02N0401 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R6C29:PLC2\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0401 E1_H02W0401\narc: N1_V02N0501 H06W0303\narc: N1_V02N0701 H02E0701\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0401 E1_H02W0401\narc: S1_V02S0501 H06W0303\narc: S1_V02S0701 H02E0701\narc: V00T0000 V02S0601\narc: V00T0100 E1_H02W0101\narc: A1 H02E0701\narc: B1 E1_H02W0301\narc: C1 E1_H02W0601\narc: CLK0 G_HPBX0000\narc: D1 V00T0100\narc: F1 F1_SLICE\narc: H01W0100 F1\narc: LSR1 H02E0501\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q4\narc: V01S0000 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R6C30:PLC2\narc: E1_H02E0701 V02S0701\narc: N1_V02N0001 E1_H02W0001\narc: N1_V02N0101 E1_H02W0101\narc: N1_V02N0201 S1_V02N0201\narc: N1_V02N0301 E1_H02W0301\narc: N1_V02N0501 V01N0101\narc: N1_V02N0701 W1_H02E0701\narc: S1_V02S0001 E1_H02W0001\narc: S1_V02S0101 E1_H02W0101\narc: S1_V02S0501 E1_H02W0501\narc: S1_V02S0701 W1_H02E0701\narc: V00B0000 E1_H02W0401\narc: V00T0100 E1_H02W0301\narc: A5 W1_H02E0701\narc: B5 H02W0301\narc: C5 V00T0100\narc: CLK0 G_HPBX0000\narc: D5 E1_H02W0001\narc: E1_H01E0101 Q2\narc: F5 F5_SLICE\narc: LSR1 V00B0100\narc: M2 V00B0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: V00B0100 F5\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R6C31:PLC2\narc: E1_H02E0201 S1_V02N0201\narc: E1_H02E0301 V01N0101\narc: E1_H02E0501 H01E0101\narc: E1_H02E0601 E1_H01W0000\narc: H00L0000 E1_H02W0001\narc: N1_V02N0001 E1_H01W0000\narc: S1_V02S0401 E1_H01W0000\narc: S1_V02S0501 H02W0501\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 H02W0601\narc: V00B0100 V02S0301\narc: V00T0000 E1_H02W0201\narc: W1_H02W0101 E1_H01W0100\narc: W1_H02W0301 E1_H02W0201\narc: W1_H02W0401 E1_H01W0000\narc: W1_H02W0601 E1_H01W0000\narc: A1 E1_H02W0501\narc: A3 E1_H02W0501\narc: A7 H00R0000\narc: B1 V00T0000\narc: B3 H00L0000\narc: B7 N1_V01S0000\narc: C1 E1_H01W0000\narc: C3 E1_H01W0000\narc: C7 E1_H02W0601\narc: CLK0 G_HPBX0000\narc: D1 H02W0001\narc: D3 H02W0001\narc: D7 V00B0000\narc: E1_H02E0701 F7\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H00R0000 Q4\narc: LSR0 V00T0100\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0001 Q4\narc: N1_V02N0301 F1\narc: V00T0100 F3\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000010000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R6C32:PLC2\narc: E1_H02E0701 E1_H01W0100\narc: H00R0000 E1_H02W0601\narc: H00R0100 H02E0701\narc: N1_V02N0101 E1_H01W0100\narc: N1_V02N0401 V01N0001\narc: N1_V02N0501 H02E0501\narc: N1_V02N0601 E1_H02W0601\narc: N1_V02N0701 E1_H01W0100\narc: S1_V02S0601 E1_H02W0601\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 V02S0001\narc: V00B0100 W1_H02E0701\narc: V00T0000 V02S0401\narc: V00T0100 N1_V02S0701\narc: W1_H02W0401 N1_V01S0000\narc: W1_H02W0501 E1_H01W0100\narc: W1_H02W0601 N1_V02S0601\narc: W3_H06W0303 E1_H01W0100\narc: A0 H00R0000\narc: A1 H02W0701\narc: A3 H02E0501\narc: A5 N1_V01S0100\narc: B0 F1\narc: B1 V02S0101\narc: B3 H02E0301\narc: B5 S1_V02N0701\narc: C0 E1_H01W0000\narc: C1 H00R0100\narc: C3 V02N0601\narc: C5 V02N0201\narc: CLK0 G_HPBX0000\narc: D0 F2\narc: D1 E1_H02W0001\narc: D3 V00B0100\narc: D5 V02N0401\narc: E1_H01E0101 F1\narc: E1_H02E0001 F2\narc: E1_H02E0201 F2\narc: E1_H02E0301 F1\narc: E1_H02E0401 Q6\narc: E3_H06E0003 F0\narc: E3_H06E0103 F2\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F2 F5B_SLICE\narc: F5 F5_SLICE\narc: H01W0000 F1\narc: H01W0100 F2\narc: LSR1 V00T0100\narc: M2 V00T0000\narc: M6 V00B0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 Q6\narc: N1_V01N0101 F5\narc: N1_V02N0001 F2\narc: N1_V02N0201 F2\narc: N1_V02N0301 F1\narc: S1_V02S0201 F2\narc: S1_V02S0301 F1\narc: W1_H02W0001 F2\narc: W1_H02W0101 F1\narc: W1_H02W0301 F1\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0111111111111111\nword: SLICEA.K1.INIT 1000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R6C33:PLC2\narc: E1_H02E0401 N1_V01S0000\narc: H00L0000 W1_H02E0201\narc: H00R0000 H02E0401\narc: N1_V02N0101 H01E0101\narc: N1_V02N0301 S1_V02N0201\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0601 H02W0601\narc: N1_V02N0701 H01E0101\narc: S1_V02S0001 H02E0001\narc: S1_V02S0101 N1_V01S0100\narc: S1_V02S0301 H01E0101\narc: S1_V02S0701 E1_H01W0100\narc: V00B0000 H02W0401\narc: V00B0100 V02S0301\narc: V00T0000 V02N0401\narc: V00T0100 V02S0701\narc: W1_H02W0501 E1_H01W0100\narc: A0 V02S0501\narc: A1 H02E0701\narc: A3 V00B0000\narc: A7 H00R0000\narc: B0 V02N0101\narc: B1 E1_H01W0100\narc: B3 V02N0301\narc: B7 V00T0000\narc: C0 H00L0000\narc: C1 W1_H02E0601\narc: C3 N1_V02S0601\narc: C7 V02S0001\narc: CLK0 G_HPBX0000\narc: D0 V00B0100\narc: D1 H02E0201\narc: D3 H02W0201\narc: D7 V02N0601\narc: E1_H01E0001 F3\narc: E1_H01E0101 F1\narc: E1_H02E0201 F0\narc: F0 F0_SLICE\narc: F1 F1_SLICE\narc: F3 F3_SLICE\narc: F7 F7_SLICE\narc: H01W0000 F0\narc: H01W0100 F0\narc: LSR0 H02W0301\narc: M4 V00T0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V01N0101 F0\narc: V01S0000 F0\narc: V01S0100 Q4\narc: W1_H02W0001 F0\narc: W1_H02W0201 F0\narc: W1_H02W0601 Q4\narc: W1_H02W0701 F7\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000001\nword: SLICEA.K0.INIT 0000000000000001\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\n\n.tile R6C34:PLC2\narc: E1_H02E0001 W1_H02E0001\narc: E1_H02E0301 W1_H02E0301\narc: E1_H02E0601 W1_H02E0301\narc: E1_H02E0701 V02S0701\narc: H00L0000 H02E0201\narc: H00R0000 S1_V02N0601\narc: N1_V02N0101 S1_V02N0001\narc: N1_V02N0301 W1_H02E0301\narc: N1_V02N0501 E1_H01W0100\narc: N1_V02N0701 S1_V02N0601\narc: S1_V02S0001 W1_H02E0001\narc: S1_V02S0201 H02E0201\narc: S1_V02S0301 W1_H02E0301\narc: V00T0100 W1_H02E0301\narc: W1_H02W0001 H01E0001\narc: W1_H02W0201 N1_V02S0201\narc: W1_H02W0301 H01E0101\narc: A4 E1_H01W0000\narc: A5 V00B0000\narc: B4 H00R0000\narc: B5 H00L0000\narc: C4 V02N0201\narc: C5 V00T0100\narc: CLK0 G_HPBX0000\narc: D4 V02S0401\narc: D5 W1_H02E0001\narc: E1_H01E0001 F4\narc: E1_H01E0101 F4\narc: F4 F4_SLICE\narc: F5 F5_SLICE\narc: H01W0100 F4\narc: LSR1 V00B0100\narc: M6 H02E0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0101 Q6\narc: N1_V02N0601 F4\narc: S1_V02S0401 F4\narc: V00B0000 F4\narc: V00B0100 F5\narc: W1_H02W0401 Q6\narc: W1_H02W0601 F4\narc: W3_H06W0203 F4\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000001\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\n\n.tile R6C35:PLC2\narc: N1_V02N0101 H01E0101\narc: N1_V02N0201 H06E0103\narc: N1_V02N0301 H02E0301\narc: S1_V02S0101 H01E0101\narc: S1_V02S0201 H06E0103\narc: S1_V02S0301 H02E0301\narc: V00B0100 H02E0701\narc: V00T0000 W1_H02E0201\narc: A1 H01E0001\narc: B1 V00T0000\narc: C1 H02E0601\narc: CLK0 G_HPBX0000\narc: D1 H02E0001\narc: F1 F1_SLICE\narc: H01W0000 Q4\narc: H01W0100 Q4\narc: LSR0 V00T0100\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: V00T0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R6C36:PLC2\narc: H00L0000 E1_H02W0001\narc: N1_V02N0201 N1_V01S0000\narc: N1_V02N0301 N1_V01S0100\narc: CE2 H00L0000\narc: CLK0 G_HPBX0000\narc: D5 H00R0100\narc: E1_H02E0701 Q5\narc: F5 F5_SLICE\narc: H00R0100 Q5\narc: MUXCLK2 CLK0\narc: N1_V02N0701 Q5\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000011111111\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 1\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX INV\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\n\n.tile R6C37:PLC2\narc: N1_V02N0701 H02E0701\n\n.tile R6C38:PLC2\narc: W1_H02W0001 W3_H06E0003\n\n.tile R7C25:PLC2\narc: N1_V02N0101 E1_H01W0100\n\n.tile R7C26:PLC2\narc: N1_V02N0101 N1_V01S0100\narc: V00B0000 H02W0401\narc: V00B0100 V02S0301\narc: CLK0 G_HPBX0000\narc: E3_H06E0103 Q2\narc: H01W0100 Q2\narc: LSR0 V00B0100\narc: M2 V00B0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\n\n.tile R7C27:PLC2\narc: N1_V02N0701 S1_V02N0701\narc: V00T0000 V02S0601\narc: V00T0100 V02S0501\narc: W1_H02W0401 E1_H02W0101\narc: CLK0 G_HPBX0000\narc: LSR1 V00T0100\narc: M6 V00T0000\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V02N0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\n\n.tile R7C29:PLC2\narc: E1_H02E0201 N1_V02S0201\narc: E1_H02E0501 E1_H01W0100\narc: E3_H06E0203 N1_V01S0000\narc: H00R0100 V02S0501\narc: N1_V02N0101 H06E0103\narc: V00B0100 V02S0101\narc: W1_H02W0101 V06S0103\narc: A3 V02S0701\narc: B3 H00R0100\narc: C3 V02S0401\narc: CLK0 G_HPBX0000\narc: D3 V00B0100\narc: E3_H06E0303 Q6\narc: F3 F3_SLICE\narc: LSR0 V00T0100\narc: M6 H02W0401\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR0\narc: V00T0100 F3\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R7C30:PLC2\narc: V00B0000 V02S0001\narc: V00B0100 V02S0101\narc: V00T0000 H02E0201\narc: V00T0100 V02S0701\narc: W1_H02W0401 N1_V02S0401\narc: A5 V00T0100\narc: B5 V02S0501\narc: C5 V00B0100\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: E3_H06E0003 Q0\narc: F5 F5_SLICE\narc: H01W0100 F5\narc: LSR1 H02E0501\narc: M0 V00T0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0101 Q0\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R7C31:PLC2\narc: E1_H02E0201 V06S0103\narc: E1_H02E0301 E1_H01W0100\narc: E1_H02E0401 V02S0401\narc: H00R0100 V02S0701\narc: V00B0000 H02W0601\narc: V00T0000 V02S0401\narc: V00T0100 E1_H02W0101\narc: A5 V00B0000\narc: B5 V02S0501\narc: C5 V00T0000\narc: CLK0 G_HPBX0000\narc: D5 H00R0100\narc: F5 F5_SLICE\narc: LSR1 V00B0100\narc: M0 V00T0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0101 Q0\narc: N1_V02N0201 Q0\narc: V00B0100 F5\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R7C32:PLC2\narc: E1_H02E0101 V01N0101\narc: E1_H02E0301 E1_H01W0100\narc: N1_V02N0001 E1_H01W0000\narc: N1_V02N0201 H02E0201\narc: N1_V02N0401 H06E0203\narc: N1_V02N0501 H06E0303\narc: N1_V02N0601 H06E0303\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0301\narc: V00T0000 V02S0601\narc: W1_H02W0601 V02S0601\narc: A5 V00T0000\narc: B5 V02S0701\narc: C5 H02E0401\narc: CLK0 G_HPBX0000\narc: D5 V00B0000\narc: F5 F5_SLICE\narc: H01W0100 F5\narc: LSR1 H02E0301\narc: M2 V00B0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\narc: N1_V01N0001 Q2\narc: V01S0100 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R7C33:PLC2\narc: E1_H02E0201 N1_V01S0000\narc: N1_V02N0101 H02E0101\narc: N1_V02N0301 V01N0101\narc: N1_V02N0501 N1_V01S0100\narc: N1_V02N0601 E1_H01W0000\narc: S1_V02S0601 N1_V01S0000\narc: V00B0000 V02S0001\narc: V00B0100 V02S0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0101 N1_V02S0101\narc: A7 V00T0100\narc: B7 N1_V01S0000\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: F7 F7_SLICE\narc: H01W0000 Q4\narc: H01W0100 F7\narc: LSR0 H02E0301\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: N1_V02N0401 Q4\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R7C34:PLC2\narc: E1_H02E0501 E1_H01W0100\narc: H00L0100 V02S0301\narc: H00R0000 V02S0401\narc: N1_V02N0101 W1_H02E0101\narc: N1_V02N0201 E1_H01W0000\narc: S1_V02S0001 V01N0001\narc: S1_V02S0701 N1_V02S0601\narc: V00B0000 V02S0201\narc: V00B0100 N1_V02S0101\narc: A1 H00R0000\narc: B1 V00B0000\narc: C1 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 V02S0001\narc: F1 F1_SLICE\narc: H01W0000 Q4\narc: LSR0 V00T0100\narc: M4 V00B0100\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR0\narc: V00T0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R7C35:PLC2\narc: V00B0000 V02S0201\narc: V00B0100 V02S0301\narc: V00T0000 W1_H02E0201\narc: V00T0100 N1_V02S0501\narc: A7 V02S0101\narc: B7 V00T0000\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D7 V00B0000\narc: F7 F7_SLICE\narc: H01W0000 Q2\narc: H01W0100 F7\narc: LSR1 H02E0501\narc: M2 V00T0100\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR1\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R7C36:PLC2\narc: N1_V02N0301 W3_H06E0003\n\n.tile R8C29:PLC2\narc: E1_H02E0101 N1_V02S0101\narc: E1_H02E0501 E1_H01W0100\n\n.tile R8C30:PLC2\narc: E1_H02E0701 N1_V02S0701\narc: H00L0100 H02E0101\narc: V00B0000 H02W0401\narc: V00B0100 N1_V02S0101\narc: V00T0100 N1_V02S0701\narc: A7 V00T0100\narc: B7 N1_V02S0501\narc: C7 V00B0100\narc: CLK0 G_HPBX0000\narc: D7 H00L0100\narc: F7 F7_SLICE\narc: H01W0100 F7\narc: LSR0 H02E0501\narc: M2 V00B0000\narc: MUXCLK1 CLK0\narc: MUXLSR1 LSR0\narc: N1_V02N0201 Q2\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\nenum: SLICEB.A1MUX 1\nenum: SLICEB.B1MUX 1\nenum: SLICEB.C1MUX 1\nenum: SLICEB.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R8C31:PLC2\narc: H00R0100 N1_V02S0701\narc: V00B0000 H02W0401\narc: V00T0000 N1_V02S0401\narc: W1_H02W0401 V06S0203\narc: A7 H02E0701\narc: B7 N1_V02S0501\narc: C7 V00T0000\narc: CLK0 G_HPBX0000\narc: D7 H00R0100\narc: E3_H06E0003 Q0\narc: F7 F7_SLICE\narc: LSR0 V00B0100\narc: M0 V00B0000\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR0\narc: N1_V02N0201 Q0\narc: V00B0100 F7\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR0.SRMODE LSR_OVER_CE\nenum: LSR0.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\n\n.tile R8C32:PLC2\narc: H00L0100 N1_V02S0301\narc: H00R0000 N1_V02S0601\narc: H00R0100 N1_V02S0701\narc: N1_V02N0701 N1_V01S0100\narc: V00T0000 E1_H02W0001\narc: W1_H02W0401 E1_H02W0101\narc: A1 H00R0000\narc: B1 H00R0100\narc: C1 H00L0100\narc: CLK0 G_HPBX0000\narc: D1 N1_V02S0201\narc: F1 F1_SLICE\narc: LSR1 V00T0100\narc: M4 V00T0000\narc: MUXCLK2 CLK0\narc: MUXLSR2 LSR1\narc: N1_V01N0101 Q4\narc: V00T0100 F1\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 0000000000000000\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 1000000000000000\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\nenum: SLICEC.A1MUX 1\nenum: SLICEC.B1MUX 1\nenum: SLICEC.C1MUX 1\nenum: SLICEC.D1MUX 1\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\n\n.tile R8C33:PLC2\narc: H00L0100 N1_V02S0301\narc: H00R0000 V02S0601\narc: V00B0100 N1_V02S0101\narc: A3 N1_V02S0701\narc: B3 H00R0000\narc: C3 H00L0100\narc: CLK0 G_HPBX0000\narc: D3 N1_V02S0001\narc: F3 F3_SLICE\narc: LSR1 V00T0100\narc: M0 V00B0100\narc: MUXCLK0 CLK0\narc: MUXLSR0 LSR1\narc: N1_V01N0101 Q0\narc: N1_V02N0201 Q0\narc: V00T0100 F3\nword: SLICEA.K0.INIT 0000000000000000\nword: SLICEA.K1.INIT 0000000000000000\nword: SLICEB.K0.INIT 0000000000000000\nword: SLICEB.K1.INIT 1000000000000000\nenum: SLICEA.MODE LOGIC\nenum: SLICEA.GSR DISABLED\nenum: SLICEA.REG0.SD 0\nenum: SLICEA.REG1.SD 0\nenum: SLICEA.REG0.REGSET RESET\nenum: SLICEA.REG1.REGSET RESET\nenum: SLICEA.REG0.LSRMODE LSR\nenum: SLICEA.REG1.LSRMODE LSR\nenum: SLICEA.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICEA.CCU2.INJECT1_0 _NONE_\nenum: SLICEA.CCU2.INJECT1_1 _NONE_\nenum: SLICEA.A0MUX 1\nenum: SLICEA.B0MUX 1\nenum: SLICEA.C0MUX 1\nenum: SLICEA.D0MUX 1\nenum: SLICEA.A1MUX 1\nenum: SLICEA.B1MUX 1\nenum: SLICEA.C1MUX 1\nenum: SLICEA.D1MUX 1\nenum: SLICEB.MODE LOGIC\nenum: SLICEB.GSR DISABLED\nenum: SLICEB.REG0.SD 0\nenum: SLICEB.REG1.SD 0\nenum: SLICEB.REG0.REGSET RESET\nenum: SLICEB.REG1.REGSET RESET\nenum: SLICEB.REG0.LSRMODE LSR\nenum: SLICEB.REG1.LSRMODE LSR\nenum: SLICEB.CEMUX 1\nenum: SLICEB.CCU2.INJECT1_0 _NONE_\nenum: SLICEB.CCU2.INJECT1_1 _NONE_\nenum: SLICEB.A0MUX 1\nenum: SLICEB.B0MUX 1\nenum: SLICEB.C0MUX 1\nenum: SLICEB.D0MUX 1\n\n.tile R8C34:PLC2\narc: H00L0000 N1_V02S0201\narc: N1_V02N0001 H06E0003\narc: V00B0000 V02S0001\narc: V00B0100 N1_V02S0301\narc: V00T0000 N1_V02S0401\narc: V00T0100 V02S0701\narc: W1_H02W0001 V06S0003\narc: W1_H02W0101 V06S0103\narc: A5 V00T0000\narc: B5 H00L0000\narc: C5 V00B0100\narc: CLK0 G_HPBX0000\narc: D5 H02W0201\narc: F5 F5_SLICE\narc: LSR1 V00B0000\narc: M6 V00T0100\narc: MUXCLK3 CLK0\narc: MUXLSR3 LSR1\narc: N1_V01N0001 F5\narc: N1_V02N0601 Q6\nword: SLICED.K0.INIT 0000000000000000\nword: SLICED.K1.INIT 0000000000000000\nword: SLICEC.K0.INIT 0000000000000000\nword: SLICEC.K1.INIT 1000000000000000\nenum: SLICED.MODE LOGIC\nenum: SLICED.GSR DISABLED\nenum: SLICED.REG0.SD 0\nenum: SLICED.REG1.SD 0\nenum: SLICED.REG0.REGSET RESET\nenum: SLICED.REG1.REGSET RESET\nenum: SLICED.REG0.LSRMODE LSR\nenum: SLICED.REG1.LSRMODE LSR\nenum: SLICED.CEMUX 1\nenum: LSR1.SRMODE LSR_OVER_CE\nenum: LSR1.LSRMUX LSR\nenum: CLK0.CLKMUX CLK\nenum: SLICED.CCU2.INJECT1_0 _NONE_\nenum: SLICED.CCU2.INJECT1_1 _NONE_\nenum: SLICED.A0MUX 1\nenum: SLICED.B0MUX 1\nenum: SLICED.C0MUX 1\nenum: SLICED.D0MUX 1\nenum: SLICED.A1MUX 1\nenum: SLICED.B1MUX 1\nenum: SLICED.C1MUX 1\nenum: SLICED.D1MUX 1\nenum: SLICEC.MODE LOGIC\nenum: SLICEC.GSR DISABLED\nenum: SLICEC.REG0.SD 0\nenum: SLICEC.REG1.SD 0\nenum: SLICEC.REG0.REGSET RESET\nenum: SLICEC.REG1.REGSET RESET\nenum: SLICEC.REG0.LSRMODE LSR\nenum: SLICEC.REG1.LSRMODE LSR\nenum: SLICEC.CEMUX 1\nenum: SLICEC.CCU2.INJECT1_0 _NONE_\nenum: SLICEC.CCU2.INJECT1_1 _NONE_\nenum: SLICEC.A0MUX 1\nenum: SLICEC.B0MUX 1\nenum: SLICEC.C0MUX 1\nenum: SLICEC.D0MUX 1\n\n.tile R8C35:PLC2\narc: W1_H02W0201 N1_V02S0201\n\n.tile R9C27:PLC2\narc: N1_V02N0701 N3_V06S0203\n\n.tile TAP_R2C22:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R2C42:TAP_DRIVE\narc: L_HPBX0100 G_VPTX0100\n\n.tile TAP_R3C22:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\narc: R_HPBX0100 G_VPTX0100\n\n.tile TAP_R3C42:TAP_DRIVE\narc: L_HPBX0100 G_VPTX0100\n\n.tile TAP_R4C22:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R4C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: L_HPBX0100 G_VPTX0100\n\n.tile TAP_R5C22:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R5C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\narc: L_HPBX0100 G_VPTX0100\n\n.tile TAP_R6C22:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R6C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R7C22:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R7C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n.tile TAP_R8C22:TAP_DRIVE\narc: R_HPBX0000 G_VPTX0000\n\n.tile TAP_R8C42:TAP_DRIVE\narc: L_HPBX0000 G_VPTX0000\n\n"
  },
  {
    "path": "tools/README.md",
    "content": "# Get Start\n\n## Install openocd\n```\n$git clone https://github.com/ntfreak/openocd.git\n$cd openocd\n$git submodule init\n$git submodule update\n$./bootstrap\n$./configure --enable-cmsis-dap\n$make -j\n$sudo make install\n```\n\n## Setup\nafter openocd installed, a shell script `dapprog` is written for convenient, export the path of dapprog, then we can use it everywhere, because the openocd can only support svf file, so the bit file will be converted to svf file with a little modified urjtag. in addition, the svf file is program to sram and the bit file is program to the flash.\n`$cd icesugar-pro/tools`\n`$source env.sh`\n`$dapprog xxx.svf or xxx.bit`\n\n"
  },
  {
    "path": "tools/cmsisdap.cfg",
    "content": "#\n# Buspirate with OpenOCD support\n#\n# http://dangerousprototypes.com/bus-pirate-manual/\n#\n# http://www.fabienm.eu/flf/15-ecp5-board-kit/\n# https://github.com/Martoni/blp/tree/master/platforms/colorlight\n# https://github.com/HarmonInstruments/JTAG_SWD\n\ninterface cmsis-dap\ntransport select jtag\n\nadapter_khz 10000\n\njtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043\n\n#init\n#scan_chain\n#\n#svf -tap ecp5.tap -quiet -progress blink.svf\n#exit\n\n# this depends on the cable, you are safe with this option\n#reset_config srst_only\n"
  },
  {
    "path": "tools/dapprog",
    "content": "#!/bin/bash\n\nif [ ${#1} -eq 0 ]; then\n    echo \"usage: dapprog file\"\n    exit 0\nfi\n\nCURRENT_DIR=$(cd $(dirname $0); pwd)\nCONFIG=${CURRENT_DIR}/cmsisdap.cfg\n\nif [ \"$1\" == \"--probe\" ] || [ \"$1\" == \"-p\" ]; then\n    #probe add -d4 for detail log\n    sudo openocd -f ${CONFIG} -c \\\n    \"   init;\n        scan_chain;\n        exit;\n    \"\n    exit $?\n\nelse\n    # program \n    IMAGE_FILE=$1\n    \n    EXT=\"${IMAGE_FILE##*.}\"\n    echo EXT: $EXT\n    \n    #flash write_image erase xxx.hex;\n    #flash write_image erase xxx.bin 0x08000000;\n    \n    if [ \"${EXT}\" == \"svf\" ]; then\n        TARGET=\"$IMAGE_FILE\"\n    elif [ \"${EXT}\" == \"bit\" ]; then\n        NAME=\"${IMAGE_FILE%%.bit}\"\n        #/home/pi/oss/ulx3s/tools/ujprog/ujprog -j SRAM  ${IMAGE_FILE} > ${NAME}_sram.svf\n        ${CURRENT_DIR}/ujprog.bit2svf -j FLASH ${IMAGE_FILE} > ${NAME}_flash.svf\n        TARGET=\"${NAME}_flash.svf\"\n    else\n        echo \"illegal suffix [$EXT]\"\n        exit 1\n    fi\n    \n    echo \"TARGET: ${TARGET}\"\n    \n    sudo openocd -f ${CONFIG} -c \\\n    \"   init;\n        scan_chain;\n        svf -tap ecp5.tap -quiet -progress ${TARGET};\n        exit;\n    \"\n    \n    exit $?\n\nfi\n\n"
  },
  {
    "path": "tools/env.sh",
    "content": "#!/bin/bash\n\n#CURRENT_DIR=$(cd $(dirname $0); pwd)\n\nCURRENT_DIR=$(pwd)\n\nexport PATH=${PATH}:${CURRENT_DIR}\n"
  },
  {
    "path": "tools/ujprog.bit2svf",
    "content": "#!/bin/bash\n\nCURRENT_DIR=$(cd $(dirname $0); pwd)\n\nPLATFORM=$(uname -m)\n\nif [ \"${PLATFORM}\" == \"x86_64\" ]; then\n    ${CURRENT_DIR}/ujprog.bit2svf.x64 $@\nelse\n    ${CURRENT_DIR}/ujprog.bit2svf.arm $@\nfi\n\n"
  },
  {
    "path": "tools/ujprog.patch",
    "content": "diff --git a/ujprog/ujprog.c b/ujprog/ujprog.c\nindex a233bb7..0085bc6 100644\n--- a/ujprog/ujprog.c\n+++ b/ujprog/ujprog.c\n@@ -41,7 +41,7 @@\n  * - execute SVF commands provided as command line args?\n  */\n \n-static const char *verstr = \"ULX2S / ULX3S JTAG programmer v 3.0.92\";\n+static const char *verstr = \"//ULX2S / ULX3S JTAG programmer v 3.0.92\";\n \n \n #include <ctype.h>\n@@ -2550,6 +2550,14 @@ exec_svf_mem(char *fbuf, int lines_tot, int debug)\n \tcmd_complete = 0;\n \tparentheses_open = 0;\n \tlinebuf = fbuf;\n+    printf(\"//START\\r\\n\", linebuf);\n+\tfor (lno = 1; lno < lines_tot; lno++, linebuf += llen) {\n+        printf(\"%s\", linebuf);\n+\t\tllen = strlen(linebuf) + 1;\n+    }\n+    printf(\"//END\\r\\n\", linebuf);\n+    exit(0);\n+    while(1);\n \n \tfor (lno = 1; lno < lines_tot; lno++, linebuf += llen) {\n \t\tif (debug)\n@@ -4217,6 +4225,7 @@ main(int argc, char *argv[])\n \t\texit(EXIT_FAILURE);\n \t}\n \n+#if 0\n \tswitch (cable_hw) {\n \tcase CABLE_HW_UNKNOWN:\n \tcase CABLE_HW_USB:\n@@ -4299,7 +4308,7 @@ main(int argc, char *argv[])\n #endif\n #endif /* !WIN32 */\n \t}\n-\n+#endif\n \tdo {\n \t\tif (reload) {\n \t\t\tgenbrk();\n"
  }
]